Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.35 97.82 93.81 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2735
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T2572 /workspace/coverage/default/43.usbdev_min_length_in_transaction.2742179797 Jun 29 06:39:17 PM PDT 24 Jun 29 06:39:18 PM PDT 24 169057396 ps
T2573 /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3944660469 Jun 29 06:34:29 PM PDT 24 Jun 29 06:34:30 PM PDT 24 221297713 ps
T2574 /workspace/coverage/default/40.usbdev_enable.2965437384 Jun 29 06:39:07 PM PDT 24 Jun 29 06:39:09 PM PDT 24 43521336 ps
T2575 /workspace/coverage/default/23.usbdev_nak_trans.1728486956 Jun 29 06:37:06 PM PDT 24 Jun 29 06:37:07 PM PDT 24 201262455 ps
T2576 /workspace/coverage/default/37.usbdev_phy_pins_sense.3698934716 Jun 29 06:38:50 PM PDT 24 Jun 29 06:38:52 PM PDT 24 88053459 ps
T2577 /workspace/coverage/default/32.usbdev_pkt_sent.4214827037 Jun 29 06:38:07 PM PDT 24 Jun 29 06:38:11 PM PDT 24 244649583 ps
T2578 /workspace/coverage/default/25.usbdev_link_resume.3458488271 Jun 29 06:37:17 PM PDT 24 Jun 29 06:37:41 PM PDT 24 23308434389 ps
T2579 /workspace/coverage/default/36.usbdev_out_stall.2115954555 Jun 29 06:38:42 PM PDT 24 Jun 29 06:38:43 PM PDT 24 218500625 ps
T2580 /workspace/coverage/default/47.usbdev_max_usb_traffic.26436127 Jun 29 06:40:07 PM PDT 24 Jun 29 06:40:38 PM PDT 24 3798361619 ps
T2581 /workspace/coverage/default/34.usbdev_aon_wake_reset.4031405869 Jun 29 06:38:19 PM PDT 24 Jun 29 06:38:34 PM PDT 24 13324334294 ps
T2582 /workspace/coverage/default/36.usbdev_in_trans.871085424 Jun 29 06:38:27 PM PDT 24 Jun 29 06:38:28 PM PDT 24 209087770 ps
T2583 /workspace/coverage/default/0.usbdev_nak_trans.1554540955 Jun 29 06:33:33 PM PDT 24 Jun 29 06:33:35 PM PDT 24 195266189 ps
T2584 /workspace/coverage/default/10.usbdev_pkt_buffer.2641062332 Jun 29 06:35:09 PM PDT 24 Jun 29 06:35:55 PM PDT 24 19943694244 ps
T2585 /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1287615773 Jun 29 06:39:10 PM PDT 24 Jun 29 06:39:12 PM PDT 24 190455013 ps
T2586 /workspace/coverage/default/36.usbdev_setup_trans_ignored.3054059603 Jun 29 06:38:45 PM PDT 24 Jun 29 06:38:46 PM PDT 24 209877333 ps
T2587 /workspace/coverage/default/24.usbdev_in_trans.3853238071 Jun 29 06:37:12 PM PDT 24 Jun 29 06:37:13 PM PDT 24 163906655 ps
T2588 /workspace/coverage/default/7.usbdev_max_usb_traffic.1304649401 Jun 29 06:34:51 PM PDT 24 Jun 29 06:35:25 PM PDT 24 3461467926 ps
T2589 /workspace/coverage/default/21.usbdev_disable_endpoint.2676873117 Jun 29 06:36:37 PM PDT 24 Jun 29 06:36:39 PM PDT 24 370423599 ps
T2590 /workspace/coverage/default/5.usbdev_phy_config_pinflip.3383254790 Jun 29 06:34:23 PM PDT 24 Jun 29 06:34:24 PM PDT 24 234926110 ps
T2591 /workspace/coverage/default/42.usbdev_alert_test.1191192551 Jun 29 06:39:13 PM PDT 24 Jun 29 06:39:15 PM PDT 24 61736916 ps
T2592 /workspace/coverage/default/30.usbdev_link_suspend.4072450837 Jun 29 06:38:03 PM PDT 24 Jun 29 06:38:09 PM PDT 24 3350094118 ps
T2593 /workspace/coverage/default/5.usbdev_data_toggle_restore.2921968975 Jun 29 06:34:25 PM PDT 24 Jun 29 06:34:28 PM PDT 24 658381168 ps
T2594 /workspace/coverage/default/15.usbdev_data_toggle_restore.501822193 Jun 29 06:35:45 PM PDT 24 Jun 29 06:35:48 PM PDT 24 787638631 ps
T2595 /workspace/coverage/default/10.usbdev_link_suspend.2896302645 Jun 29 06:35:18 PM PDT 24 Jun 29 06:35:23 PM PDT 24 3351607220 ps
T2596 /workspace/coverage/default/18.usbdev_random_length_in_transaction.2730133295 Jun 29 06:36:12 PM PDT 24 Jun 29 06:36:13 PM PDT 24 233561206 ps
T93 /workspace/coverage/default/2.usbdev_av_overflow.3509171213 Jun 29 06:33:47 PM PDT 24 Jun 29 06:33:49 PM PDT 24 135464779 ps
T2597 /workspace/coverage/default/6.usbdev_stall_priority_over_nak.91634895 Jun 29 06:34:37 PM PDT 24 Jun 29 06:34:38 PM PDT 24 182710569 ps
T2598 /workspace/coverage/default/2.usbdev_nak_trans.3563078649 Jun 29 06:33:54 PM PDT 24 Jun 29 06:33:56 PM PDT 24 225658760 ps
T2599 /workspace/coverage/default/14.usbdev_disable_endpoint.2477355639 Jun 29 06:35:44 PM PDT 24 Jun 29 06:35:46 PM PDT 24 325300566 ps
T2600 /workspace/coverage/default/9.usbdev_streaming_out.4244558775 Jun 29 06:35:17 PM PDT 24 Jun 29 06:37:33 PM PDT 24 4886595684 ps
T2601 /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3923697372 Jun 29 06:33:33 PM PDT 24 Jun 29 06:33:35 PM PDT 24 312853412 ps
T2602 /workspace/coverage/default/15.usbdev_aon_wake_resume.3914694555 Jun 29 06:35:44 PM PDT 24 Jun 29 06:36:15 PM PDT 24 23406767584 ps
T2603 /workspace/coverage/default/1.usbdev_smoke.943655770 Jun 29 06:33:53 PM PDT 24 Jun 29 06:33:54 PM PDT 24 214334879 ps
T2604 /workspace/coverage/default/21.usbdev_random_length_out_transaction.2734874823 Jun 29 06:36:36 PM PDT 24 Jun 29 06:36:38 PM PDT 24 197839280 ps
T2605 /workspace/coverage/default/18.usbdev_phy_pins_sense.62650655 Jun 29 06:36:30 PM PDT 24 Jun 29 06:36:31 PM PDT 24 38328762 ps
T2606 /workspace/coverage/default/5.usbdev_random_length_out_transaction.1350969940 Jun 29 06:34:32 PM PDT 24 Jun 29 06:34:33 PM PDT 24 201864406 ps
T2607 /workspace/coverage/default/11.usbdev_data_toggle_clear.710225713 Jun 29 06:35:23 PM PDT 24 Jun 29 06:35:25 PM PDT 24 316568928 ps
T2608 /workspace/coverage/default/20.usbdev_out_iso.2208924413 Jun 29 06:36:30 PM PDT 24 Jun 29 06:36:32 PM PDT 24 159683521 ps
T2609 /workspace/coverage/default/15.usbdev_out_iso.3484215292 Jun 29 06:35:55 PM PDT 24 Jun 29 06:35:56 PM PDT 24 172328125 ps
T2610 /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1957919098 Jun 29 06:36:22 PM PDT 24 Jun 29 06:37:35 PM PDT 24 2699687512 ps
T2611 /workspace/coverage/default/8.usbdev_av_buffer.3993504696 Jun 29 06:34:53 PM PDT 24 Jun 29 06:34:54 PM PDT 24 147744920 ps
T2612 /workspace/coverage/default/38.usbdev_min_length_in_transaction.1738853900 Jun 29 06:38:55 PM PDT 24 Jun 29 06:38:56 PM PDT 24 151847781 ps
T2613 /workspace/coverage/default/36.usbdev_setup_stage.3623708423 Jun 29 06:38:47 PM PDT 24 Jun 29 06:38:49 PM PDT 24 154046380 ps
T2614 /workspace/coverage/default/27.usbdev_random_length_in_transaction.4072316358 Jun 29 06:37:27 PM PDT 24 Jun 29 06:37:30 PM PDT 24 221252810 ps
T2615 /workspace/coverage/default/44.usbdev_disable_endpoint.1201357197 Jun 29 06:39:43 PM PDT 24 Jun 29 06:39:46 PM PDT 24 397200070 ps
T2616 /workspace/coverage/default/42.usbdev_low_speed_traffic.2974893012 Jun 29 06:39:07 PM PDT 24 Jun 29 06:42:49 PM PDT 24 8378945110 ps
T2617 /workspace/coverage/default/10.usbdev_random_length_out_transaction.310579082 Jun 29 06:35:11 PM PDT 24 Jun 29 06:35:13 PM PDT 24 182477910 ps
T2618 /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1449441394 Jun 29 06:38:24 PM PDT 24 Jun 29 06:40:31 PM PDT 24 4704350573 ps
T2619 /workspace/coverage/default/32.usbdev_bitstuff_err.989827126 Jun 29 06:38:14 PM PDT 24 Jun 29 06:38:16 PM PDT 24 187560446 ps
T226 /workspace/coverage/default/2.usbdev_sec_cm.3985816165 Jun 29 06:34:02 PM PDT 24 Jun 29 06:34:03 PM PDT 24 557753602 ps
T2620 /workspace/coverage/default/1.usbdev_aon_wake_resume.2551991916 Jun 29 06:33:41 PM PDT 24 Jun 29 06:34:08 PM PDT 24 23338054819 ps
T2621 /workspace/coverage/default/22.usbdev_aon_wake_reset.894382215 Jun 29 06:36:44 PM PDT 24 Jun 29 06:36:59 PM PDT 24 13324455173 ps
T2622 /workspace/coverage/default/33.usbdev_low_speed_traffic.1830138238 Jun 29 06:38:08 PM PDT 24 Jun 29 06:40:48 PM PDT 24 5783716545 ps
T2623 /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1828776785 Jun 29 06:38:38 PM PDT 24 Jun 29 06:39:18 PM PDT 24 4232664463 ps
T2624 /workspace/coverage/default/13.usbdev_aon_wake_resume.122530459 Jun 29 06:35:37 PM PDT 24 Jun 29 06:36:02 PM PDT 24 23311585575 ps
T2625 /workspace/coverage/default/33.usbdev_min_length_in_transaction.1190042846 Jun 29 06:38:19 PM PDT 24 Jun 29 06:38:22 PM PDT 24 171076705 ps
T2626 /workspace/coverage/default/38.usbdev_smoke.903118664 Jun 29 06:39:10 PM PDT 24 Jun 29 06:39:11 PM PDT 24 238420862 ps
T2627 /workspace/coverage/default/14.usbdev_link_in_err.507790943 Jun 29 06:35:47 PM PDT 24 Jun 29 06:35:49 PM PDT 24 246927265 ps
T2628 /workspace/coverage/default/43.usbdev_nak_trans.1127802736 Jun 29 06:39:40 PM PDT 24 Jun 29 06:39:41 PM PDT 24 188666614 ps
T2629 /workspace/coverage/default/40.usbdev_in_stall.700380134 Jun 29 06:39:04 PM PDT 24 Jun 29 06:39:06 PM PDT 24 169126967 ps
T221 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.693063263 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:32 PM PDT 24 36354088 ps
T222 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2197172635 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:38 PM PDT 24 50418189 ps
T210 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2094491071 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:39 PM PDT 24 925727397 ps
T211 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3803622442 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:37 PM PDT 24 152971644 ps
T212 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2144544568 Jun 29 04:45:29 PM PDT 24 Jun 29 04:45:34 PM PDT 24 872775258 ps
T245 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2009494763 Jun 29 04:45:29 PM PDT 24 Jun 29 04:45:30 PM PDT 24 49328853 ps
T232 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1623923588 Jun 29 04:45:28 PM PDT 24 Jun 29 04:45:30 PM PDT 24 69084119 ps
T2630 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3252204214 Jun 29 04:45:30 PM PDT 24 Jun 29 04:45:34 PM PDT 24 302586712 ps
T233 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1027764490 Jun 29 04:45:30 PM PDT 24 Jun 29 04:45:34 PM PDT 24 122412942 ps
T216 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.198989764 Jun 29 04:45:29 PM PDT 24 Jun 29 04:45:31 PM PDT 24 187600388 ps
T275 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3869425292 Jun 29 04:45:41 PM PDT 24 Jun 29 04:45:43 PM PDT 24 75846104 ps
T223 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.4240596131 Jun 29 04:45:49 PM PDT 24 Jun 29 04:45:50 PM PDT 24 45556585 ps
T286 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2430181889 Jun 29 04:45:38 PM PDT 24 Jun 29 04:45:40 PM PDT 24 45317120 ps
T276 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1041108 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:37 PM PDT 24 103272666 ps
T249 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.760771976 Jun 29 04:45:32 PM PDT 24 Jun 29 04:45:35 PM PDT 24 149484061 ps
T277 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.213090294 Jun 29 04:45:46 PM PDT 24 Jun 29 04:45:48 PM PDT 24 59151087 ps
T224 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.411183391 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:35 PM PDT 24 36082262 ps
T262 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4007833443 Jun 29 04:45:30 PM PDT 24 Jun 29 04:45:32 PM PDT 24 128409068 ps
T242 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.786117234 Jun 29 04:45:36 PM PDT 24 Jun 29 04:45:41 PM PDT 24 148865961 ps
T237 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3778253870 Jun 29 04:45:32 PM PDT 24 Jun 29 04:45:37 PM PDT 24 946948211 ps
T263 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3686409437 Jun 29 04:45:19 PM PDT 24 Jun 29 04:45:28 PM PDT 24 1712069411 ps
T239 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2186610226 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:40 PM PDT 24 202720742 ps
T250 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2671405480 Jun 29 04:45:46 PM PDT 24 Jun 29 04:45:51 PM PDT 24 937417340 ps
T251 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.801901695 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:34 PM PDT 24 231422905 ps
T283 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3641977565 Jun 29 04:45:20 PM PDT 24 Jun 29 04:45:21 PM PDT 24 55305780 ps
T264 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1482695464 Jun 29 04:45:37 PM PDT 24 Jun 29 04:45:40 PM PDT 24 90431204 ps
T265 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1769979842 Jun 29 04:45:21 PM PDT 24 Jun 29 04:45:23 PM PDT 24 99539689 ps
T252 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2508896943 Jun 29 04:45:51 PM PDT 24 Jun 29 04:45:56 PM PDT 24 789994940 ps
T253 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.142988113 Jun 29 04:45:33 PM PDT 24 Jun 29 04:45:36 PM PDT 24 377831896 ps
T278 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3455442139 Jun 29 04:45:44 PM PDT 24 Jun 29 04:45:46 PM PDT 24 144438153 ps
T254 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.114483172 Jun 29 04:45:36 PM PDT 24 Jun 29 04:45:40 PM PDT 24 98795862 ps
T279 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3093632587 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:33 PM PDT 24 90037762 ps
T288 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2625324572 Jun 29 04:45:27 PM PDT 24 Jun 29 04:45:28 PM PDT 24 38980884 ps
T280 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1501452401 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:38 PM PDT 24 289414224 ps
T281 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.358881954 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:37 PM PDT 24 160384402 ps
T309 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2389542936 Jun 29 04:45:28 PM PDT 24 Jun 29 04:45:31 PM PDT 24 858261664 ps
T304 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2938567266 Jun 29 04:45:43 PM PDT 24 Jun 29 04:45:48 PM PDT 24 520114291 ps
T289 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.527621230 Jun 29 04:45:37 PM PDT 24 Jun 29 04:45:40 PM PDT 24 71507027 ps
T284 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3531898956 Jun 29 04:45:36 PM PDT 24 Jun 29 04:45:38 PM PDT 24 50608233 ps
T266 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3083965132 Jun 29 04:45:30 PM PDT 24 Jun 29 04:45:32 PM PDT 24 105965630 ps
T267 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.942883788 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:34 PM PDT 24 81548438 ps
T285 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3980450688 Jun 29 04:45:46 PM PDT 24 Jun 29 04:45:47 PM PDT 24 47659941 ps
T290 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3514874296 Jun 29 04:45:36 PM PDT 24 Jun 29 04:45:38 PM PDT 24 42999094 ps
T268 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.487098210 Jun 29 04:45:45 PM PDT 24 Jun 29 04:45:51 PM PDT 24 592652513 ps
T2631 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1983829061 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:43 PM PDT 24 209081639 ps
T269 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3610556281 Jun 29 04:45:48 PM PDT 24 Jun 29 04:45:49 PM PDT 24 90652247 ps
T240 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2765163434 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:39 PM PDT 24 107791432 ps
T292 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3148771735 Jun 29 04:45:28 PM PDT 24 Jun 29 04:45:29 PM PDT 24 95127243 ps
T243 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2858316322 Jun 29 04:45:46 PM PDT 24 Jun 29 04:45:49 PM PDT 24 201716009 ps
T2632 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3421690971 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:40 PM PDT 24 84875017 ps
T2633 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.4287161729 Jun 29 04:45:38 PM PDT 24 Jun 29 04:45:41 PM PDT 24 70657843 ps
T2634 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2005798206 Jun 29 04:45:51 PM PDT 24 Jun 29 04:45:53 PM PDT 24 141780774 ps
T241 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.764998907 Jun 29 04:45:38 PM PDT 24 Jun 29 04:45:42 PM PDT 24 116872530 ps
T305 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2428815519 Jun 29 04:45:20 PM PDT 24 Jun 29 04:45:25 PM PDT 24 858872328 ps
T282 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3646095122 Jun 29 04:45:24 PM PDT 24 Jun 29 04:45:26 PM PDT 24 200268782 ps
T244 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1958149383 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:36 PM PDT 24 364648051 ps
T2635 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.910957359 Jun 29 04:45:40 PM PDT 24 Jun 29 04:45:42 PM PDT 24 113637869 ps
T2636 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1387257753 Jun 29 04:45:24 PM PDT 24 Jun 29 04:45:25 PM PDT 24 49744841 ps
T2637 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2829227175 Jun 29 04:45:30 PM PDT 24 Jun 29 04:45:32 PM PDT 24 123917429 ps
T270 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2122401703 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:36 PM PDT 24 94949971 ps
T271 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1662108040 Jun 29 04:45:29 PM PDT 24 Jun 29 04:45:37 PM PDT 24 124403924 ps
T272 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1033225281 Jun 29 04:45:26 PM PDT 24 Jun 29 04:45:27 PM PDT 24 88684516 ps
T296 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2854031114 Jun 29 04:45:47 PM PDT 24 Jun 29 04:45:48 PM PDT 24 58057786 ps
T2638 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3704313141 Jun 29 04:45:28 PM PDT 24 Jun 29 04:45:33 PM PDT 24 653719628 ps
T291 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1532524906 Jun 29 04:45:41 PM PDT 24 Jun 29 04:45:42 PM PDT 24 45233484 ps
T2639 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1338816345 Jun 29 04:45:22 PM PDT 24 Jun 29 04:45:23 PM PDT 24 139261636 ps
T2640 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1041226576 Jun 29 04:45:21 PM PDT 24 Jun 29 04:45:24 PM PDT 24 339374368 ps
T2641 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3266339267 Jun 29 04:45:40 PM PDT 24 Jun 29 04:45:42 PM PDT 24 50944452 ps
T287 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2466271862 Jun 29 04:45:50 PM PDT 24 Jun 29 04:45:51 PM PDT 24 63259341 ps
T2642 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.628113697 Jun 29 04:45:14 PM PDT 24 Jun 29 04:45:15 PM PDT 24 86661669 ps
T297 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3411870948 Jun 29 04:45:52 PM PDT 24 Jun 29 04:45:53 PM PDT 24 41189437 ps
T2643 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1626890623 Jun 29 04:45:33 PM PDT 24 Jun 29 04:45:35 PM PDT 24 125041757 ps
T273 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.874345115 Jun 29 04:45:45 PM PDT 24 Jun 29 04:45:46 PM PDT 24 99688337 ps
T300 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1782711727 Jun 29 04:45:28 PM PDT 24 Jun 29 04:45:29 PM PDT 24 101710876 ps
T2644 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.977809574 Jun 29 04:45:27 PM PDT 24 Jun 29 04:45:32 PM PDT 24 624838051 ps
T2645 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.790864390 Jun 29 04:45:33 PM PDT 24 Jun 29 04:45:37 PM PDT 24 577527446 ps
T298 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3737895742 Jun 29 04:45:52 PM PDT 24 Jun 29 04:45:53 PM PDT 24 36233264 ps
T2646 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.72495652 Jun 29 04:45:36 PM PDT 24 Jun 29 04:45:39 PM PDT 24 101699712 ps
T2647 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.147244331 Jun 29 04:45:30 PM PDT 24 Jun 29 04:45:33 PM PDT 24 89432308 ps
T274 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.41299260 Jun 29 04:45:24 PM PDT 24 Jun 29 04:45:25 PM PDT 24 44488718 ps
T299 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3957041070 Jun 29 04:45:37 PM PDT 24 Jun 29 04:45:40 PM PDT 24 38315155 ps
T302 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.41571132 Jun 29 04:45:22 PM PDT 24 Jun 29 04:45:25 PM PDT 24 417112751 ps
T2648 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1723883317 Jun 29 04:45:49 PM PDT 24 Jun 29 04:45:51 PM PDT 24 144156348 ps
T2649 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4270966597 Jun 29 04:45:42 PM PDT 24 Jun 29 04:45:43 PM PDT 24 77742118 ps
T2650 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3820348564 Jun 29 04:45:54 PM PDT 24 Jun 29 04:45:56 PM PDT 24 48536571 ps
T2651 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3355546109 Jun 29 04:45:28 PM PDT 24 Jun 29 04:45:29 PM PDT 24 65901061 ps
T303 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3395769289 Jun 29 04:45:23 PM PDT 24 Jun 29 04:45:25 PM PDT 24 373097225 ps
T2652 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2283929573 Jun 29 04:45:24 PM PDT 24 Jun 29 04:45:27 PM PDT 24 184549590 ps
T2653 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.825498166 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:36 PM PDT 24 65706779 ps
T2654 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1085995286 Jun 29 04:45:56 PM PDT 24 Jun 29 04:45:59 PM PDT 24 156884779 ps
T2655 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.818355203 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:32 PM PDT 24 79044874 ps
T2656 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3814207471 Jun 29 04:45:19 PM PDT 24 Jun 29 04:45:20 PM PDT 24 47233690 ps
T2657 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4171132740 Jun 29 04:45:48 PM PDT 24 Jun 29 04:45:49 PM PDT 24 83282476 ps
T2658 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.928155440 Jun 29 04:45:24 PM PDT 24 Jun 29 04:45:26 PM PDT 24 135996939 ps
T2659 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1320406483 Jun 29 04:45:36 PM PDT 24 Jun 29 04:45:39 PM PDT 24 91747554 ps
T2660 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.37577497 Jun 29 04:45:36 PM PDT 24 Jun 29 04:45:39 PM PDT 24 47200791 ps
T2661 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.670374803 Jun 29 04:45:16 PM PDT 24 Jun 29 04:45:21 PM PDT 24 720002928 ps
T2662 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.729755198 Jun 29 04:45:21 PM PDT 24 Jun 29 04:45:23 PM PDT 24 95064227 ps
T2663 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1483603465 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:39 PM PDT 24 298123057 ps
T2664 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1896917684 Jun 29 04:45:30 PM PDT 24 Jun 29 04:45:33 PM PDT 24 115777700 ps
T2665 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3039995216 Jun 29 04:45:33 PM PDT 24 Jun 29 04:45:34 PM PDT 24 141031042 ps
T2666 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.746948111 Jun 29 04:45:53 PM PDT 24 Jun 29 04:45:54 PM PDT 24 37318261 ps
T2667 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3373573636 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:37 PM PDT 24 192973771 ps
T2668 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3293584196 Jun 29 04:45:29 PM PDT 24 Jun 29 04:45:30 PM PDT 24 61404553 ps
T2669 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1714075823 Jun 29 04:45:24 PM PDT 24 Jun 29 04:45:26 PM PDT 24 193789114 ps
T2670 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2446725775 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:34 PM PDT 24 192305235 ps
T2671 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.208188081 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:36 PM PDT 24 80126303 ps
T2672 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.925862671 Jun 29 04:45:47 PM PDT 24 Jun 29 04:45:49 PM PDT 24 246900661 ps
T2673 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4008076633 Jun 29 04:45:39 PM PDT 24 Jun 29 04:45:41 PM PDT 24 44010216 ps
T2674 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2480557257 Jun 29 04:45:29 PM PDT 24 Jun 29 04:45:35 PM PDT 24 926539239 ps
T2675 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2147811824 Jun 29 04:45:17 PM PDT 24 Jun 29 04:45:20 PM PDT 24 259678552 ps
T2676 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1394831540 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:38 PM PDT 24 88402973 ps
T2677 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2226890330 Jun 29 04:45:18 PM PDT 24 Jun 29 04:45:21 PM PDT 24 452283850 ps
T2678 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3416374818 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:33 PM PDT 24 306186797 ps
T2679 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.746681034 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:38 PM PDT 24 98824773 ps
T301 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3293776472 Jun 29 04:45:32 PM PDT 24 Jun 29 04:45:35 PM PDT 24 367159944 ps
T2680 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2387237804 Jun 29 04:45:42 PM PDT 24 Jun 29 04:45:43 PM PDT 24 34516681 ps
T2681 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.782353301 Jun 29 04:45:46 PM PDT 24 Jun 29 04:45:47 PM PDT 24 87964650 ps
T2682 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.572067801 Jun 29 04:45:23 PM PDT 24 Jun 29 04:45:24 PM PDT 24 43863660 ps
T2683 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2863686815 Jun 29 04:45:45 PM PDT 24 Jun 29 04:45:46 PM PDT 24 49486990 ps
T2684 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1202280411 Jun 29 04:45:24 PM PDT 24 Jun 29 04:45:26 PM PDT 24 179049774 ps
T2685 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.801456982 Jun 29 04:45:22 PM PDT 24 Jun 29 04:45:25 PM PDT 24 171745587 ps
T2686 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1672791443 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:33 PM PDT 24 55562634 ps
T2687 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2113076012 Jun 29 04:45:21 PM PDT 24 Jun 29 04:45:24 PM PDT 24 212336497 ps
T2688 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1738435363 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:33 PM PDT 24 42058978 ps
T2689 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.399665837 Jun 29 04:45:33 PM PDT 24 Jun 29 04:45:35 PM PDT 24 331627168 ps
T2690 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2306395690 Jun 29 04:45:42 PM PDT 24 Jun 29 04:45:43 PM PDT 24 57801590 ps
T306 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2527719773 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:42 PM PDT 24 823131111 ps
T2691 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3474316122 Jun 29 04:45:24 PM PDT 24 Jun 29 04:45:28 PM PDT 24 318979986 ps
T2692 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.622229536 Jun 29 04:45:27 PM PDT 24 Jun 29 04:45:29 PM PDT 24 198446013 ps
T2693 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4043928855 Jun 29 04:45:30 PM PDT 24 Jun 29 04:45:32 PM PDT 24 124266028 ps
T2694 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3629453879 Jun 29 04:45:37 PM PDT 24 Jun 29 04:45:40 PM PDT 24 127561754 ps
T2695 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3162253247 Jun 29 04:45:36 PM PDT 24 Jun 29 04:45:39 PM PDT 24 35923278 ps
T2696 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2149208453 Jun 29 04:45:38 PM PDT 24 Jun 29 04:45:40 PM PDT 24 51707005 ps
T2697 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3924311154 Jun 29 04:45:49 PM PDT 24 Jun 29 04:45:51 PM PDT 24 161029928 ps
T2698 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.448307859 Jun 29 04:45:39 PM PDT 24 Jun 29 04:45:41 PM PDT 24 41085332 ps
T2699 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2845803085 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:36 PM PDT 24 39549789 ps
T2700 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.823293476 Jun 29 04:45:40 PM PDT 24 Jun 29 04:45:42 PM PDT 24 39776497 ps
T2701 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3240343899 Jun 29 04:45:33 PM PDT 24 Jun 29 04:45:35 PM PDT 24 53510702 ps
T2702 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1050019789 Jun 29 04:45:38 PM PDT 24 Jun 29 04:45:40 PM PDT 24 41109250 ps
T2703 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3005335634 Jun 29 04:45:57 PM PDT 24 Jun 29 04:46:00 PM PDT 24 116081708 ps
T308 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1341340228 Jun 29 04:45:40 PM PDT 24 Jun 29 04:45:44 PM PDT 24 375299526 ps
T2704 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1130155957 Jun 29 04:45:48 PM PDT 24 Jun 29 04:45:50 PM PDT 24 48627590 ps
T2705 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3015811686 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:34 PM PDT 24 99464100 ps
T2706 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2703864918 Jun 29 04:45:23 PM PDT 24 Jun 29 04:45:25 PM PDT 24 65774447 ps
T2707 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1739220329 Jun 29 04:45:28 PM PDT 24 Jun 29 04:45:30 PM PDT 24 127370468 ps
T2708 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2114748322 Jun 29 04:45:40 PM PDT 24 Jun 29 04:45:42 PM PDT 24 41333686 ps
T2709 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2565489011 Jun 29 04:45:28 PM PDT 24 Jun 29 04:45:32 PM PDT 24 127231984 ps
T2710 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3376126772 Jun 29 04:45:29 PM PDT 24 Jun 29 04:45:32 PM PDT 24 98289743 ps
T2711 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3221656633 Jun 29 04:45:42 PM PDT 24 Jun 29 04:45:43 PM PDT 24 67322451 ps
T2712 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.377754692 Jun 29 04:45:39 PM PDT 24 Jun 29 04:45:42 PM PDT 24 113728973 ps
T2713 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.826121146 Jun 29 04:45:29 PM PDT 24 Jun 29 04:45:31 PM PDT 24 159998115 ps
T2714 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2715869220 Jun 29 04:45:30 PM PDT 24 Jun 29 04:45:33 PM PDT 24 274566465 ps
T2715 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.826288878 Jun 29 04:45:49 PM PDT 24 Jun 29 04:45:50 PM PDT 24 54387746 ps
T2716 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1719813291 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:39 PM PDT 24 361959720 ps
T2717 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.626070818 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:37 PM PDT 24 498461618 ps
T2718 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.746101501 Jun 29 04:45:22 PM PDT 24 Jun 29 04:45:27 PM PDT 24 703626309 ps
T2719 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2984086606 Jun 29 04:45:40 PM PDT 24 Jun 29 04:45:42 PM PDT 24 44209512 ps
T2720 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2342269552 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:38 PM PDT 24 47726604 ps
T2721 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3186991569 Jun 29 04:45:17 PM PDT 24 Jun 29 04:45:19 PM PDT 24 169318067 ps
T2722 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.93962686 Jun 29 04:45:46 PM PDT 24 Jun 29 04:45:47 PM PDT 24 44012174 ps
T2723 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3853402892 Jun 29 04:45:39 PM PDT 24 Jun 29 04:45:41 PM PDT 24 55053353 ps
T2724 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.159268819 Jun 29 04:45:20 PM PDT 24 Jun 29 04:45:21 PM PDT 24 59120035 ps
T2725 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4278226848 Jun 29 04:45:36 PM PDT 24 Jun 29 04:45:39 PM PDT 24 64228825 ps
T2726 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.797184007 Jun 29 04:45:31 PM PDT 24 Jun 29 04:45:33 PM PDT 24 56051772 ps
T2727 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1355798828 Jun 29 04:45:16 PM PDT 24 Jun 29 04:45:17 PM PDT 24 167881824 ps
T2728 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1492878231 Jun 29 04:45:29 PM PDT 24 Jun 29 04:45:32 PM PDT 24 228159220 ps
T2729 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2558901271 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:37 PM PDT 24 72661596 ps
T307 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.113113432 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:40 PM PDT 24 485723420 ps
T2730 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2341353321 Jun 29 04:45:22 PM PDT 24 Jun 29 04:45:25 PM PDT 24 79754735 ps
T2731 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1449055283 Jun 29 04:45:35 PM PDT 24 Jun 29 04:45:39 PM PDT 24 177552380 ps
T2732 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1171553331 Jun 29 04:45:29 PM PDT 24 Jun 29 04:45:30 PM PDT 24 48384847 ps
T2733 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1928391818 Jun 29 04:45:51 PM PDT 24 Jun 29 04:45:52 PM PDT 24 44631061 ps
T2734 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3139568292 Jun 29 04:45:25 PM PDT 24 Jun 29 04:45:33 PM PDT 24 285904530 ps
T2735 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2114761539 Jun 29 04:45:34 PM PDT 24 Jun 29 04:45:37 PM PDT 24 131434652 ps

Test location /workspace/coverage/default/18.usbdev_in_trans.3493459317
Short name T2
Test name
Test status
Simulation time 177829978 ps
CPU time 0.87 seconds
Started Jun 29 06:36:13 PM PDT 24
Finished Jun 29 06:36:15 PM PDT 24
Peak memory 206216 kb
Host smart-35913115-c922-4b31-8a8e-e77c80931a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34934
59317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3493459317
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_device_address.2662750734
Short name T36
Test name
Test status
Simulation time 22403255746 ps
CPU time 48.58 seconds
Started Jun 29 06:36:09 PM PDT 24
Finished Jun 29 06:37:03 PM PDT 24
Peak memory 206500 kb
Host smart-506a11af-2fde-4ee7-be88-8df4101c6dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26627
50734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.2662750734
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.693063263
Short name T221
Test name
Test status
Simulation time 36354088 ps
CPU time 0.66 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:32 PM PDT 24
Peak memory 205852 kb
Host smart-58054324-ff3f-4f0f-b001-9c9cdf55dd84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=693063263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.693063263
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.4012732331
Short name T7
Test name
Test status
Simulation time 23421923102 ps
CPU time 28.1 seconds
Started Jun 29 06:39:50 PM PDT 24
Finished Jun 29 06:40:19 PM PDT 24
Peak memory 206324 kb
Host smart-6064dc36-5733-4d7c-9b39-95e36e5f437f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4012732331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.4012732331
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2144544568
Short name T212
Test name
Test status
Simulation time 872775258 ps
CPU time 4.35 seconds
Started Jun 29 04:45:29 PM PDT 24
Finished Jun 29 04:45:34 PM PDT 24
Peak memory 206044 kb
Host smart-2fa56030-1275-47f5-80f7-4bb9c7287b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2144544568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2144544568
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.1003529522
Short name T48
Test name
Test status
Simulation time 7119436291 ps
CPU time 53.95 seconds
Started Jun 29 06:37:11 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206368 kb
Host smart-e0f01159-eebf-4214-b672-40752b159a4e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1003529522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.1003529522
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.682855713
Short name T26
Test name
Test status
Simulation time 43519217 ps
CPU time 0.68 seconds
Started Jun 29 06:37:23 PM PDT 24
Finished Jun 29 06:37:24 PM PDT 24
Peak memory 206204 kb
Host smart-c48efc97-e9e9-41ee-94a6-0e66774e7496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68285
5713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.682855713
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3691735103
Short name T102
Test name
Test status
Simulation time 178502337 ps
CPU time 0.87 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 206204 kb
Host smart-ad4efcaf-68d6-443c-9c49-a3f624fd7bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36917
35103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3691735103
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3514874296
Short name T290
Test name
Test status
Simulation time 42999094 ps
CPU time 0.67 seconds
Started Jun 29 04:45:36 PM PDT 24
Finished Jun 29 04:45:38 PM PDT 24
Peak memory 205820 kb
Host smart-3e3f08da-0d9b-44dc-a7e9-ef67b1cd493c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3514874296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3514874296
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3825915195
Short name T118
Test name
Test status
Simulation time 196159526 ps
CPU time 0.84 seconds
Started Jun 29 06:36:34 PM PDT 24
Finished Jun 29 06:36:36 PM PDT 24
Peak memory 206204 kb
Host smart-cd0982b2-1558-49c9-a296-6f3df78376ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38259
15195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3825915195
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3803622442
Short name T211
Test name
Test status
Simulation time 152971644 ps
CPU time 2.94 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 222168 kb
Host smart-f3fdae3e-286e-4e7c-91e5-a25acc090ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3803622442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3803622442
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2735375151
Short name T207
Test name
Test status
Simulation time 229583646 ps
CPU time 1.08 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:33:41 PM PDT 24
Peak memory 224060 kb
Host smart-04c068b6-f08c-4a20-91da-ee6112d5e01c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2735375151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2735375151
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.3107234932
Short name T8
Test name
Test status
Simulation time 4222745318 ps
CPU time 4.7 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:27 PM PDT 24
Peak memory 206364 kb
Host smart-dfc0456b-4d91-47f0-9750-9239a6bfb65c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3107234932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.3107234932
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1481280364
Short name T144
Test name
Test status
Simulation time 176661395 ps
CPU time 0.82 seconds
Started Jun 29 06:33:38 PM PDT 24
Finished Jun 29 06:33:40 PM PDT 24
Peak memory 206216 kb
Host smart-3a6de949-3eba-4fa6-804a-c38e1cb83ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14812
80364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1481280364
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.487098210
Short name T268
Test name
Test status
Simulation time 592652513 ps
CPU time 4.46 seconds
Started Jun 29 04:45:45 PM PDT 24
Finished Jun 29 04:45:51 PM PDT 24
Peak memory 205988 kb
Host smart-7941f567-6e21-4726-affe-e14040b5bd2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=487098210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.487098210
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.4134590942
Short name T51
Test name
Test status
Simulation time 951677096 ps
CPU time 2.27 seconds
Started Jun 29 06:39:41 PM PDT 24
Finished Jun 29 06:39:44 PM PDT 24
Peak memory 206252 kb
Host smart-95e09c37-02cc-4bb5-b480-251167df4020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41345
90942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.4134590942
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3451673347
Short name T499
Test name
Test status
Simulation time 140289853 ps
CPU time 0.85 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206192 kb
Host smart-97211b55-e519-401b-9b5d-a4a96b88a8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34516
73347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3451673347
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2625324572
Short name T288
Test name
Test status
Simulation time 38980884 ps
CPU time 0.67 seconds
Started Jun 29 04:45:27 PM PDT 24
Finished Jun 29 04:45:28 PM PDT 24
Peak memory 205788 kb
Host smart-6c4dbe7c-11df-420d-b4ee-b6913a3547bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2625324572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2625324572
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1076694272
Short name T87
Test name
Test status
Simulation time 408194284 ps
CPU time 1.08 seconds
Started Jun 29 06:33:36 PM PDT 24
Finished Jun 29 06:33:38 PM PDT 24
Peak memory 206164 kb
Host smart-b31d3e62-ad4b-4b20-9874-3c31027214c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10766
94272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.1076694272
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.2577054721
Short name T68
Test name
Test status
Simulation time 344798075 ps
CPU time 1.21 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:10 PM PDT 24
Peak memory 206196 kb
Host smart-f403dcbc-542a-4c91-962d-708b0586444a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25770
54721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.2577054721
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3626878778
Short name T56
Test name
Test status
Simulation time 20173897639 ps
CPU time 20.46 seconds
Started Jun 29 06:33:32 PM PDT 24
Finished Jun 29 06:33:53 PM PDT 24
Peak memory 206308 kb
Host smart-f588e03d-0d78-438f-bcd3-63fd2a56a7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36268
78778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3626878778
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2854031114
Short name T296
Test name
Test status
Simulation time 58057786 ps
CPU time 0.7 seconds
Started Jun 29 04:45:47 PM PDT 24
Finished Jun 29 04:45:48 PM PDT 24
Peak memory 205816 kb
Host smart-0e42ee7f-6e75-43d7-a317-9ee991ca306a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2854031114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2854031114
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1276595908
Short name T25
Test name
Test status
Simulation time 11388667446 ps
CPU time 306.27 seconds
Started Jun 29 06:34:36 PM PDT 24
Finished Jun 29 06:39:44 PM PDT 24
Peak memory 206500 kb
Host smart-64507e3c-6748-47a3-ad05-b5c0e2fb2109
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1276595908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1276595908
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.4181369501
Short name T457
Test name
Test status
Simulation time 246974677 ps
CPU time 0.92 seconds
Started Jun 29 06:36:34 PM PDT 24
Finished Jun 29 06:36:36 PM PDT 24
Peak memory 206192 kb
Host smart-383fe19f-b4ad-4ebe-b667-ed34539359db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41813
69501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.4181369501
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.4092548561
Short name T293
Test name
Test status
Simulation time 225852988 ps
CPU time 0.9 seconds
Started Jun 29 06:38:13 PM PDT 24
Finished Jun 29 06:38:15 PM PDT 24
Peak memory 206196 kb
Host smart-adfd0494-032e-4984-b1a4-9e9960b13c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40925
48561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.4092548561
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.411183391
Short name T224
Test name
Test status
Simulation time 36082262 ps
CPU time 0.64 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:35 PM PDT 24
Peak memory 205852 kb
Host smart-8b3623b9-faa1-474f-b98d-332e017652c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=411183391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.411183391
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2671405480
Short name T250
Test name
Test status
Simulation time 937417340 ps
CPU time 4.73 seconds
Started Jun 29 04:45:46 PM PDT 24
Finished Jun 29 04:45:51 PM PDT 24
Peak memory 205932 kb
Host smart-0fce0cec-7395-4e56-8e61-761e916dfb49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2671405480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2671405480
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2690667998
Short name T83
Test name
Test status
Simulation time 189880226 ps
CPU time 0.83 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:49 PM PDT 24
Peak memory 206224 kb
Host smart-c8e257f4-3a8c-4b8d-a7b7-e061333bcb36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26906
67998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2690667998
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.22327588
Short name T57
Test name
Test status
Simulation time 464613937 ps
CPU time 1.28 seconds
Started Jun 29 06:33:32 PM PDT 24
Finished Jun 29 06:33:35 PM PDT 24
Peak memory 206156 kb
Host smart-c2a3f3e3-d9de-4ca6-93ec-25e1058a8413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22327
588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.22327588
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.3837456822
Short name T17
Test name
Test status
Simulation time 43480565 ps
CPU time 0.67 seconds
Started Jun 29 06:33:37 PM PDT 24
Finished Jun 29 06:33:38 PM PDT 24
Peak memory 206212 kb
Host smart-50bb4958-33ed-4d11-b134-db1f45dcc411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3837456822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.3837456822
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2155523222
Short name T13
Test name
Test status
Simulation time 13353096130 ps
CPU time 15.55 seconds
Started Jun 29 06:39:39 PM PDT 24
Finished Jun 29 06:39:55 PM PDT 24
Peak memory 206340 kb
Host smart-5dde65bf-1cb1-45fd-b9fe-cd70acc4aeef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2155523222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2155523222
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3455442139
Short name T278
Test name
Test status
Simulation time 144438153 ps
CPU time 1.38 seconds
Started Jun 29 04:45:44 PM PDT 24
Finished Jun 29 04:45:46 PM PDT 24
Peak memory 206004 kb
Host smart-f9cac68e-fe7b-466a-b4cd-7a50281f4f40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3455442139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3455442139
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1625011952
Short name T170
Test name
Test status
Simulation time 14293053823 ps
CPU time 314.48 seconds
Started Jun 29 06:33:46 PM PDT 24
Finished Jun 29 06:39:01 PM PDT 24
Peak memory 206532 kb
Host smart-f6dc603a-8054-4fb5-b7a5-779f00d42c51
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1625011952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1625011952
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.1448209667
Short name T65
Test name
Test status
Simulation time 255933266 ps
CPU time 1.02 seconds
Started Jun 29 06:33:33 PM PDT 24
Finished Jun 29 06:33:35 PM PDT 24
Peak memory 206204 kb
Host smart-08e66832-6532-4339-ba5e-41b45ad37140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14482
09667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.1448209667
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.4036143365
Short name T75
Test name
Test status
Simulation time 136583358 ps
CPU time 0.78 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:33:29 PM PDT 24
Peak memory 206192 kb
Host smart-483c5ba3-73c7-4ee4-9a3a-2fcfe7b6ef99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40361
43365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.4036143365
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3814207471
Short name T2656
Test name
Test status
Simulation time 47233690 ps
CPU time 0.72 seconds
Started Jun 29 04:45:19 PM PDT 24
Finished Jun 29 04:45:20 PM PDT 24
Peak memory 205832 kb
Host smart-88e86150-0287-4ee6-a35c-8a4bbdcfd983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3814207471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3814207471
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2428815519
Short name T305
Test name
Test status
Simulation time 858872328 ps
CPU time 4.61 seconds
Started Jun 29 04:45:20 PM PDT 24
Finished Jun 29 04:45:25 PM PDT 24
Peak memory 206028 kb
Host smart-3f48787d-9d2d-4354-a778-8263deabe2a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2428815519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2428815519
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2094491071
Short name T210
Test name
Test status
Simulation time 925727397 ps
CPU time 4.39 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:39 PM PDT 24
Peak memory 206100 kb
Host smart-04fa2d2d-e233-456b-ae13-58d79dba2b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2094491071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2094491071
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2508896943
Short name T252
Test name
Test status
Simulation time 789994940 ps
CPU time 4.49 seconds
Started Jun 29 04:45:51 PM PDT 24
Finished Jun 29 04:45:56 PM PDT 24
Peak memory 206064 kb
Host smart-69563ebd-1f8b-40fb-97d0-4f77416f8846
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2508896943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2508896943
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.472207973
Short name T247
Test name
Test status
Simulation time 9280369700 ps
CPU time 62.22 seconds
Started Jun 29 06:33:43 PM PDT 24
Finished Jun 29 06:34:46 PM PDT 24
Peak memory 206680 kb
Host smart-be7c0648-061a-473c-9891-2f758be47400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47220
7973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.472207973
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2858316322
Short name T243
Test name
Test status
Simulation time 201716009 ps
CPU time 3.14 seconds
Started Jun 29 04:45:46 PM PDT 24
Finished Jun 29 04:45:49 PM PDT 24
Peak memory 214336 kb
Host smart-d02f2715-7c23-4077-8295-5e19538918b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2858316322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2858316322
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2796416103
Short name T175
Test name
Test status
Simulation time 1404953824 ps
CPU time 3.37 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:09 PM PDT 24
Peak memory 206300 kb
Host smart-ca5c944a-9bd5-4ac2-b1b9-43a225484f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27964
16103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2796416103
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1429908791
Short name T721
Test name
Test status
Simulation time 37129524 ps
CPU time 0.66 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:33:40 PM PDT 24
Peak memory 206212 kb
Host smart-08e763c8-2945-4ee8-99a4-0d57ee4111ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14299
08791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1429908791
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.894054483
Short name T166
Test name
Test status
Simulation time 10887295643 ps
CPU time 195.18 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:37:12 PM PDT 24
Peak memory 206500 kb
Host smart-834f1345-3a8b-42c6-9591-1a52467b8738
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=894054483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.894054483
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1487552708
Short name T724
Test name
Test status
Simulation time 164496110 ps
CPU time 0.83 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:33:41 PM PDT 24
Peak memory 206216 kb
Host smart-2288a5f3-042a-4dbc-97f7-10e00b70245d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14875
52708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1487552708
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1932802992
Short name T203
Test name
Test status
Simulation time 13374955820 ps
CPU time 12.83 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:35:34 PM PDT 24
Peak memory 206456 kb
Host smart-29b0acf0-b0d2-46b9-8117-a43cb72f4019
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1932802992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1932802992
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.746883264
Short name T73
Test name
Test status
Simulation time 143065028 ps
CPU time 0.82 seconds
Started Jun 29 06:33:40 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206196 kb
Host smart-eb25c80c-ce35-48b8-8128-f019dfc689e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74688
3264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.746883264
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1222655981
Short name T198
Test name
Test status
Simulation time 195059193 ps
CPU time 1.69 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206372 kb
Host smart-d6713ab3-1025-4aa0-b776-db6c8f541563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12226
55981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1222655981
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2586261421
Short name T193
Test name
Test status
Simulation time 16447337108 ps
CPU time 119.34 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:35:56 PM PDT 24
Peak memory 206476 kb
Host smart-234783cd-237d-4fb8-a563-1a4d4596ad2f
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2586261421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2586261421
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2259343344
Short name T156
Test name
Test status
Simulation time 7087221751 ps
CPU time 180.27 seconds
Started Jun 29 06:37:32 PM PDT 24
Finished Jun 29 06:40:34 PM PDT 24
Peak memory 206484 kb
Host smart-b18231bb-3030-413a-a541-d1252bbbbef8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2259343344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2259343344
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.2567500068
Short name T59
Test name
Test status
Simulation time 197181249 ps
CPU time 0.81 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:33:26 PM PDT 24
Peak memory 206180 kb
Host smart-9042f31e-bca6-4bf0-be3e-69b508a198bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25675
00068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.2567500068
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.2686196120
Short name T76
Test name
Test status
Simulation time 4162035013 ps
CPU time 9.86 seconds
Started Jun 29 06:33:31 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206412 kb
Host smart-d904ee9a-b0e9-4e32-b02c-2c38aadee90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26861
96120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.2686196120
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.80071078
Short name T77
Test name
Test status
Simulation time 261363823 ps
CPU time 0.89 seconds
Started Jun 29 06:33:35 PM PDT 24
Finished Jun 29 06:33:36 PM PDT 24
Peak memory 206160 kb
Host smart-3900a9d0-a907-4d94-86e5-a64f58a9dc23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80071
078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.80071078
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2819894784
Short name T84
Test name
Test status
Simulation time 147595351 ps
CPU time 0.78 seconds
Started Jun 29 06:33:36 PM PDT 24
Finished Jun 29 06:33:38 PM PDT 24
Peak memory 206164 kb
Host smart-7c172c97-ff18-44e6-a7db-4911f42518cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28198
94784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2819894784
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.3182982530
Short name T66
Test name
Test status
Simulation time 158019339 ps
CPU time 0.78 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:33:41 PM PDT 24
Peak memory 206160 kb
Host smart-993fc775-698c-4556-8447-47de1ef42452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31829
82530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.3182982530
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3787172380
Short name T172
Test name
Test status
Simulation time 970447116 ps
CPU time 2.07 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206292 kb
Host smart-897b465f-e338-427f-b2fa-e43a4ed77cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37871
72380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3787172380
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.760278028
Short name T187
Test name
Test status
Simulation time 1036239621 ps
CPU time 2.53 seconds
Started Jun 29 06:34:58 PM PDT 24
Finished Jun 29 06:35:01 PM PDT 24
Peak memory 206268 kb
Host smart-68193440-3a6e-449d-bb97-84b908f4e4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76027
8028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.760278028
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3376126772
Short name T2710
Test name
Test status
Simulation time 98289743 ps
CPU time 2.24 seconds
Started Jun 29 04:45:29 PM PDT 24
Finished Jun 29 04:45:32 PM PDT 24
Peak memory 214232 kb
Host smart-563a4418-acf6-4222-ba87-87bd02203c9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376126772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3376126772
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1554540955
Short name T2583
Test name
Test status
Simulation time 195266189 ps
CPU time 0.86 seconds
Started Jun 29 06:33:33 PM PDT 24
Finished Jun 29 06:33:35 PM PDT 24
Peak memory 206216 kb
Host smart-4f2a49ad-0ebf-4fd1-a8ea-50c31b859e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15545
40955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1554540955
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1995339811
Short name T62
Test name
Test status
Simulation time 421494286 ps
CPU time 1.32 seconds
Started Jun 29 06:33:36 PM PDT 24
Finished Jun 29 06:33:38 PM PDT 24
Peak memory 206220 kb
Host smart-64851e02-4fff-496a-ba10-7c35aee6d944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19953
39811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1995339811
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2566269389
Short name T146
Test name
Test status
Simulation time 189719924 ps
CPU time 0.79 seconds
Started Jun 29 06:35:19 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206172 kb
Host smart-3131d2f5-8b13-40d7-b0e5-8b1bfa3acb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25662
69389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2566269389
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2641062332
Short name T2584
Test name
Test status
Simulation time 19943694244 ps
CPU time 45.1 seconds
Started Jun 29 06:35:09 PM PDT 24
Finished Jun 29 06:35:55 PM PDT 24
Peak memory 206480 kb
Host smart-23cc805b-d50d-4abe-a7db-d9fc34dce93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26410
62332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2641062332
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.850609636
Short name T135
Test name
Test status
Simulation time 197877507 ps
CPU time 0.9 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:19 PM PDT 24
Peak memory 206208 kb
Host smart-36ff3b1d-d3c9-4ab8-b359-863fe911140f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85060
9636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.850609636
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2437359919
Short name T123
Test name
Test status
Simulation time 203904099 ps
CPU time 0.87 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 206196 kb
Host smart-e5cffaae-b273-4053-948c-82fb1ada287c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24373
59919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2437359919
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1523119935
Short name T133
Test name
Test status
Simulation time 179944543 ps
CPU time 0.83 seconds
Started Jun 29 06:35:55 PM PDT 24
Finished Jun 29 06:35:56 PM PDT 24
Peak memory 206188 kb
Host smart-04e9dcd6-b282-4404-873a-d1669776d5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15231
19935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1523119935
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_enable.1592845067
Short name T38
Test name
Test status
Simulation time 42572437 ps
CPU time 0.63 seconds
Started Jun 29 06:35:43 PM PDT 24
Finished Jun 29 06:35:45 PM PDT 24
Peak memory 206192 kb
Host smart-981aef28-bacb-4ead-80e2-0f5e9ba28326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15928
45067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1592845067
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.143422490
Short name T2269
Test name
Test status
Simulation time 200672068 ps
CPU time 0.85 seconds
Started Jun 29 06:35:52 PM PDT 24
Finished Jun 29 06:35:54 PM PDT 24
Peak memory 206216 kb
Host smart-b8971ce6-d60e-4492-b5b5-db24b5f2faf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14342
2490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.143422490
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1543708762
Short name T122
Test name
Test status
Simulation time 204877082 ps
CPU time 0.86 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206196 kb
Host smart-c3628bf5-a892-4117-8344-b5a1d255e83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15437
08762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1543708762
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3563078649
Short name T2598
Test name
Test status
Simulation time 225658760 ps
CPU time 0.88 seconds
Started Jun 29 06:33:54 PM PDT 24
Finished Jun 29 06:33:56 PM PDT 24
Peak memory 206216 kb
Host smart-1aca26cf-6d99-425e-ab6c-63e9bd2a32a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35630
78649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3563078649
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.966315062
Short name T149
Test name
Test status
Simulation time 191102742 ps
CPU time 0.87 seconds
Started Jun 29 06:36:56 PM PDT 24
Finished Jun 29 06:36:57 PM PDT 24
Peak memory 206216 kb
Host smart-9e36e1ce-3436-431e-bedf-d76509907f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96631
5062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.966315062
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.619927334
Short name T2084
Test name
Test status
Simulation time 272557800 ps
CPU time 0.99 seconds
Started Jun 29 06:37:23 PM PDT 24
Finished Jun 29 06:37:25 PM PDT 24
Peak memory 206204 kb
Host smart-972f1a7d-363f-48a7-a3ae-1435a2849a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61992
7334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.619927334
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2609726064
Short name T121
Test name
Test status
Simulation time 223467986 ps
CPU time 0.89 seconds
Started Jun 29 06:37:34 PM PDT 24
Finished Jun 29 06:37:35 PM PDT 24
Peak memory 206148 kb
Host smart-aefe3404-3223-4c9d-9d72-ab1f17c3f4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26097
26064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2609726064
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.2293871199
Short name T117
Test name
Test status
Simulation time 5102592748 ps
CPU time 36.07 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:35 PM PDT 24
Peak memory 206456 kb
Host smart-4faa2fd8-0157-4bef-a24e-cdcd502b90ec
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2293871199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.2293871199
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2113076012
Short name T2687
Test name
Test status
Simulation time 212336497 ps
CPU time 2.19 seconds
Started Jun 29 04:45:21 PM PDT 24
Finished Jun 29 04:45:24 PM PDT 24
Peak memory 206052 kb
Host smart-aa88131a-c8f0-4d49-be37-fb29309a742b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2113076012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2113076012
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.626070818
Short name T2717
Test name
Test status
Simulation time 498461618 ps
CPU time 4.32 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 206016 kb
Host smart-fb72ca99-2632-477b-80cd-c23948201902
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=626070818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.626070818
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.628113697
Short name T2642
Test name
Test status
Simulation time 86661669 ps
CPU time 0.86 seconds
Started Jun 29 04:45:14 PM PDT 24
Finished Jun 29 04:45:15 PM PDT 24
Peak memory 205856 kb
Host smart-9af2652f-a12f-4822-b881-e60d4e7d5d17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=628113697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.628113697
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1338816345
Short name T2639
Test name
Test status
Simulation time 139261636 ps
CPU time 1.2 seconds
Started Jun 29 04:45:22 PM PDT 24
Finished Jun 29 04:45:23 PM PDT 24
Peak memory 205996 kb
Host smart-e57f5db1-63ce-4868-ba4c-2de2eb854b48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1338816345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1338816345
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4043928855
Short name T2693
Test name
Test status
Simulation time 124266028 ps
CPU time 2.28 seconds
Started Jun 29 04:45:30 PM PDT 24
Finished Jun 29 04:45:32 PM PDT 24
Peak memory 215320 kb
Host smart-cf8ef77d-562a-4186-afb9-1a24dfd86a84
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4043928855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.4043928855
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1041226576
Short name T2640
Test name
Test status
Simulation time 339374368 ps
CPU time 2.66 seconds
Started Jun 29 04:45:21 PM PDT 24
Finished Jun 29 04:45:24 PM PDT 24
Peak memory 205928 kb
Host smart-cf47eba3-af86-4c0b-87c2-eee265d8cbed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1041226576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1041226576
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.825498166
Short name T2653
Test name
Test status
Simulation time 65706779 ps
CPU time 1.08 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:36 PM PDT 24
Peak memory 205836 kb
Host smart-8d6725d6-c832-46f3-a61c-761c59c02ca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=825498166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.825498166
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.928155440
Short name T2658
Test name
Test status
Simulation time 135996939 ps
CPU time 1.48 seconds
Started Jun 29 04:45:24 PM PDT 24
Finished Jun 29 04:45:26 PM PDT 24
Peak memory 221900 kb
Host smart-493fef86-451e-4102-8331-274d67c19599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=928155440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.928155440
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2341353321
Short name T2730
Test name
Test status
Simulation time 79754735 ps
CPU time 1.95 seconds
Started Jun 29 04:45:22 PM PDT 24
Finished Jun 29 04:45:25 PM PDT 24
Peak memory 206024 kb
Host smart-605fbbbe-5b77-4ff0-9594-8c6ec7cd6774
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2341353321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2341353321
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.797184007
Short name T2726
Test name
Test status
Simulation time 56051772 ps
CPU time 0.82 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:33 PM PDT 24
Peak memory 205916 kb
Host smart-ae0e744d-f120-4293-8b8f-5884db0db9c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=797184007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.797184007
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3015811686
Short name T2705
Test name
Test status
Simulation time 99464100 ps
CPU time 1.66 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:34 PM PDT 24
Peak memory 214244 kb
Host smart-ab7097f4-efa1-460d-8750-e777cb621b21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015811686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3015811686
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1387257753
Short name T2636
Test name
Test status
Simulation time 49744841 ps
CPU time 0.8 seconds
Started Jun 29 04:45:24 PM PDT 24
Finished Jun 29 04:45:25 PM PDT 24
Peak memory 205864 kb
Host smart-e09e0390-a732-4151-b86d-847c71b215d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1387257753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1387257753
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3531898956
Short name T284
Test name
Test status
Simulation time 50608233 ps
CPU time 0.68 seconds
Started Jun 29 04:45:36 PM PDT 24
Finished Jun 29 04:45:38 PM PDT 24
Peak memory 205800 kb
Host smart-2e547049-687c-4490-ba44-3e7c73110970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3531898956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3531898956
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2283929573
Short name T2652
Test name
Test status
Simulation time 184549590 ps
CPU time 2.38 seconds
Started Jun 29 04:45:24 PM PDT 24
Finished Jun 29 04:45:27 PM PDT 24
Peak memory 222480 kb
Host smart-6b56dbab-cc5d-4a1d-bd5b-d07745a84cd2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2283929573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2283929573
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.670374803
Short name T2661
Test name
Test status
Simulation time 720002928 ps
CPU time 4.57 seconds
Started Jun 29 04:45:16 PM PDT 24
Finished Jun 29 04:45:21 PM PDT 24
Peak memory 205976 kb
Host smart-97e03bef-7c93-437a-a144-a438b4497184
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=670374803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.670374803
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1355798828
Short name T2727
Test name
Test status
Simulation time 167881824 ps
CPU time 1.21 seconds
Started Jun 29 04:45:16 PM PDT 24
Finished Jun 29 04:45:17 PM PDT 24
Peak memory 205992 kb
Host smart-bad23f06-b197-44c3-aadd-eba7069e5c7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1355798828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1355798828
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1492878231
Short name T2728
Test name
Test status
Simulation time 228159220 ps
CPU time 2.5 seconds
Started Jun 29 04:45:29 PM PDT 24
Finished Jun 29 04:45:32 PM PDT 24
Peak memory 221560 kb
Host smart-070ccf5e-4848-433e-86ab-a6634311260f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1492878231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1492878231
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.910957359
Short name T2635
Test name
Test status
Simulation time 113637869 ps
CPU time 1.55 seconds
Started Jun 29 04:45:40 PM PDT 24
Finished Jun 29 04:45:42 PM PDT 24
Peak memory 214256 kb
Host smart-35646c05-4662-43d0-a5da-bac772bffee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910957359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.910957359
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2009494763
Short name T245
Test name
Test status
Simulation time 49328853 ps
CPU time 0.78 seconds
Started Jun 29 04:45:29 PM PDT 24
Finished Jun 29 04:45:30 PM PDT 24
Peak memory 205928 kb
Host smart-ecbfa595-e12f-4e77-a037-da7becb860bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2009494763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2009494763
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3853402892
Short name T2723
Test name
Test status
Simulation time 55053353 ps
CPU time 0.69 seconds
Started Jun 29 04:45:39 PM PDT 24
Finished Jun 29 04:45:41 PM PDT 24
Peak memory 205812 kb
Host smart-8409183d-87fe-4d4b-9cc9-ba8c8ec00b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3853402892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3853402892
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3924311154
Short name T2697
Test name
Test status
Simulation time 161029928 ps
CPU time 1.44 seconds
Started Jun 29 04:45:49 PM PDT 24
Finished Jun 29 04:45:51 PM PDT 24
Peak memory 206076 kb
Host smart-79b6b66b-38e6-4f4f-93ab-9a10cd345afd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3924311154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3924311154
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2527719773
Short name T306
Test name
Test status
Simulation time 823131111 ps
CPU time 4.81 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:42 PM PDT 24
Peak memory 205960 kb
Host smart-08f5437d-20e6-40d1-b019-bf5d510748b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2527719773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2527719773
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.114483172
Short name T254
Test name
Test status
Simulation time 98795862 ps
CPU time 1.27 seconds
Started Jun 29 04:45:36 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 214344 kb
Host smart-7f4769b1-1d0a-4cdf-be31-e2057f621732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114483172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.114483172
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.874345115
Short name T273
Test name
Test status
Simulation time 99688337 ps
CPU time 0.89 seconds
Started Jun 29 04:45:45 PM PDT 24
Finished Jun 29 04:45:46 PM PDT 24
Peak memory 205928 kb
Host smart-39ea940d-762a-466d-832c-69fb66d6e495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=874345115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.874345115
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.818355203
Short name T2655
Test name
Test status
Simulation time 79044874 ps
CPU time 0.7 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:32 PM PDT 24
Peak memory 205852 kb
Host smart-83b17179-e3f4-4a08-ba95-ad9d4f63bfe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=818355203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.818355203
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.358881954
Short name T281
Test name
Test status
Simulation time 160384402 ps
CPU time 1.64 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 206004 kb
Host smart-031242b5-19fe-4bcb-8eba-1bd7d8a36c2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=358881954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.358881954
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1341340228
Short name T308
Test name
Test status
Simulation time 375299526 ps
CPU time 2.32 seconds
Started Jun 29 04:45:40 PM PDT 24
Finished Jun 29 04:45:44 PM PDT 24
Peak memory 206044 kb
Host smart-3cfcc23e-4900-40db-aa74-d27d3831753d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1341340228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1341340228
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1394831540
Short name T2676
Test name
Test status
Simulation time 88402973 ps
CPU time 1.98 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:38 PM PDT 24
Peak memory 214352 kb
Host smart-0e5ddfaa-dcd3-4864-b381-e464447fce3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394831540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1394831540
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2122401703
Short name T270
Test name
Test status
Simulation time 94949971 ps
CPU time 0.96 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:36 PM PDT 24
Peak memory 205732 kb
Host smart-e2d5572d-1712-4a93-a8e6-bca2f68e8a67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2122401703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2122401703
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3240343899
Short name T2701
Test name
Test status
Simulation time 53510702 ps
CPU time 0.67 seconds
Started Jun 29 04:45:33 PM PDT 24
Finished Jun 29 04:45:35 PM PDT 24
Peak memory 205816 kb
Host smart-a8de4a83-e6de-4758-b241-bd0a95722ea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3240343899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3240343899
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.925862671
Short name T2672
Test name
Test status
Simulation time 246900661 ps
CPU time 1.69 seconds
Started Jun 29 04:45:47 PM PDT 24
Finished Jun 29 04:45:49 PM PDT 24
Peak memory 206012 kb
Host smart-d57a7779-f74c-4dc0-9a7e-eea5e052d79d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=925862671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.925862671
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2186610226
Short name T239
Test name
Test status
Simulation time 202720742 ps
CPU time 2.47 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 214300 kb
Host smart-a906b5c2-dfa0-46f5-adcc-e8f1109bcf36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2186610226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2186610226
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3778253870
Short name T237
Test name
Test status
Simulation time 946948211 ps
CPU time 3.69 seconds
Started Jun 29 04:45:32 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 206016 kb
Host smart-c973cdbb-a8d3-481d-85f9-2d6d5e2da8a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3778253870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3778253870
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1983829061
Short name T2631
Test name
Test status
Simulation time 209081639 ps
CPU time 1.32 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:43 PM PDT 24
Peak memory 222416 kb
Host smart-8e69f00b-f135-4deb-b85a-9cd25279af1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983829061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1983829061
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1033225281
Short name T272
Test name
Test status
Simulation time 88684516 ps
CPU time 1.02 seconds
Started Jun 29 04:45:26 PM PDT 24
Finished Jun 29 04:45:27 PM PDT 24
Peak memory 206064 kb
Host smart-5cf43f46-a19c-4f76-b4d3-9bc7a129dba9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1033225281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1033225281
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3162253247
Short name T2695
Test name
Test status
Simulation time 35923278 ps
CPU time 0.66 seconds
Started Jun 29 04:45:36 PM PDT 24
Finished Jun 29 04:45:39 PM PDT 24
Peak memory 205820 kb
Host smart-9f9a3f56-3447-4e2e-bc15-20adb86c7cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3162253247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3162253247
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.399665837
Short name T2689
Test name
Test status
Simulation time 331627168 ps
CPU time 1.73 seconds
Started Jun 29 04:45:33 PM PDT 24
Finished Jun 29 04:45:35 PM PDT 24
Peak memory 206000 kb
Host smart-6815c51a-4a05-4eef-8456-e158b0c98ed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=399665837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.399665837
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.764998907
Short name T241
Test name
Test status
Simulation time 116872530 ps
CPU time 2.61 seconds
Started Jun 29 04:45:38 PM PDT 24
Finished Jun 29 04:45:42 PM PDT 24
Peak memory 214280 kb
Host smart-31df1997-833c-4f30-b9f4-468a31c41dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=764998907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.764998907
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1719813291
Short name T2716
Test name
Test status
Simulation time 361959720 ps
CPU time 2.61 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:39 PM PDT 24
Peak memory 205924 kb
Host smart-02288184-9928-4102-b340-f6ee485de942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1719813291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1719813291
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.4287161729
Short name T2633
Test name
Test status
Simulation time 70657843 ps
CPU time 1.65 seconds
Started Jun 29 04:45:38 PM PDT 24
Finished Jun 29 04:45:41 PM PDT 24
Peak memory 214264 kb
Host smart-9264cd5a-67a7-4c5a-a4ac-d39963c5c0ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287161729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.4287161729
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1482695464
Short name T264
Test name
Test status
Simulation time 90431204 ps
CPU time 1.01 seconds
Started Jun 29 04:45:37 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 206016 kb
Host smart-a78d208d-3bfd-48f4-b369-31baac90166b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1482695464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1482695464
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.208188081
Short name T2671
Test name
Test status
Simulation time 80126303 ps
CPU time 0.7 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:36 PM PDT 24
Peak memory 205828 kb
Host smart-c15aaf9a-8790-443f-bc6e-82deefc46f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=208188081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.208188081
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1041108
Short name T276
Test name
Test status
Simulation time 103272666 ps
CPU time 1.65 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 206024 kb
Host smart-8ca101a5-aa7e-411e-b24d-e8dace6d5901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1041108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1041108
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3005335634
Short name T2703
Test name
Test status
Simulation time 116081708 ps
CPU time 1.61 seconds
Started Jun 29 04:45:57 PM PDT 24
Finished Jun 29 04:46:00 PM PDT 24
Peak memory 206024 kb
Host smart-002db59f-6cc2-4098-b8d2-284ddcfc20ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3005335634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3005335634
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.113113432
Short name T307
Test name
Test status
Simulation time 485723420 ps
CPU time 4 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 206044 kb
Host smart-6708fcbc-184f-498f-9376-57609061e36e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=113113432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.113113432
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1723883317
Short name T2648
Test name
Test status
Simulation time 144156348 ps
CPU time 1.74 seconds
Started Jun 29 04:45:49 PM PDT 24
Finished Jun 29 04:45:51 PM PDT 24
Peak memory 214288 kb
Host smart-2446bd26-4a83-40dd-b016-9bc5b42e3d62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723883317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1723883317
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.942883788
Short name T267
Test name
Test status
Simulation time 81548438 ps
CPU time 1.07 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:34 PM PDT 24
Peak memory 205992 kb
Host smart-3bf4f865-0896-4465-893a-9533b15b0081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=942883788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.942883788
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3355546109
Short name T2651
Test name
Test status
Simulation time 65901061 ps
CPU time 0.69 seconds
Started Jun 29 04:45:28 PM PDT 24
Finished Jun 29 04:45:29 PM PDT 24
Peak memory 205816 kb
Host smart-871aa8e2-4a01-4238-884b-0db8f523c5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3355546109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3355546109
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1896917684
Short name T2664
Test name
Test status
Simulation time 115777700 ps
CPU time 1.19 seconds
Started Jun 29 04:45:30 PM PDT 24
Finished Jun 29 04:45:33 PM PDT 24
Peak memory 206060 kb
Host smart-1fd92116-914c-4055-b6ac-a0d2c499883f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1896917684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1896917684
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1958149383
Short name T244
Test name
Test status
Simulation time 364648051 ps
CPU time 3.65 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:36 PM PDT 24
Peak memory 222228 kb
Host smart-35ec9af9-5408-4485-89f4-7617b22eb1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1958149383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1958149383
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2715869220
Short name T2714
Test name
Test status
Simulation time 274566465 ps
CPU time 2.32 seconds
Started Jun 29 04:45:30 PM PDT 24
Finished Jun 29 04:45:33 PM PDT 24
Peak memory 205964 kb
Host smart-a09c7c7f-2029-42eb-94df-b7a7bcc129dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2715869220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2715869220
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1449055283
Short name T2731
Test name
Test status
Simulation time 177552380 ps
CPU time 1.8 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:39 PM PDT 24
Peak memory 214260 kb
Host smart-58ac136a-4be3-4760-9c00-d0dbe4f75e58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449055283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1449055283
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3266339267
Short name T2641
Test name
Test status
Simulation time 50944452 ps
CPU time 0.84 seconds
Started Jun 29 04:45:40 PM PDT 24
Finished Jun 29 04:45:42 PM PDT 24
Peak memory 205836 kb
Host smart-40746dbb-0d01-466e-ab21-bd861cdc3f7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3266339267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3266339267
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2342269552
Short name T2720
Test name
Test status
Simulation time 47726604 ps
CPU time 0.66 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:38 PM PDT 24
Peak memory 205760 kb
Host smart-2664f76f-a8b7-4e99-bc29-b8b8d224a0c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2342269552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2342269552
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.213090294
Short name T277
Test name
Test status
Simulation time 59151087 ps
CPU time 1.06 seconds
Started Jun 29 04:45:46 PM PDT 24
Finished Jun 29 04:45:48 PM PDT 24
Peak memory 206004 kb
Host smart-f779e689-62fa-4f15-8ca2-c6187f826a97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=213090294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.213090294
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.760771976
Short name T249
Test name
Test status
Simulation time 149484061 ps
CPU time 1.84 seconds
Started Jun 29 04:45:32 PM PDT 24
Finished Jun 29 04:45:35 PM PDT 24
Peak memory 221632 kb
Host smart-319a150c-c29f-4818-ad7b-cc9d8b39d7ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=760771976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.760771976
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.142988113
Short name T253
Test name
Test status
Simulation time 377831896 ps
CPU time 2.78 seconds
Started Jun 29 04:45:33 PM PDT 24
Finished Jun 29 04:45:36 PM PDT 24
Peak memory 206108 kb
Host smart-8c6fe1b0-624a-43dc-b983-3482a94a4cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=142988113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.142988113
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1626890623
Short name T2643
Test name
Test status
Simulation time 125041757 ps
CPU time 2.5 seconds
Started Jun 29 04:45:33 PM PDT 24
Finished Jun 29 04:45:35 PM PDT 24
Peak memory 214272 kb
Host smart-8ce2fecd-f4c2-480a-b866-3218db5ddb3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626890623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1626890623
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3610556281
Short name T269
Test name
Test status
Simulation time 90652247 ps
CPU time 0.94 seconds
Started Jun 29 04:45:48 PM PDT 24
Finished Jun 29 04:45:49 PM PDT 24
Peak memory 205896 kb
Host smart-44ba2cdd-717b-45c9-841b-a19c17bd4859
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3610556281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3610556281
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1130155957
Short name T2704
Test name
Test status
Simulation time 48627590 ps
CPU time 0.7 seconds
Started Jun 29 04:45:48 PM PDT 24
Finished Jun 29 04:45:50 PM PDT 24
Peak memory 205820 kb
Host smart-c7fd5e2d-46ad-4d32-8533-a1156b541ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1130155957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1130155957
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.746681034
Short name T2679
Test name
Test status
Simulation time 98824773 ps
CPU time 1.57 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:38 PM PDT 24
Peak memory 221660 kb
Host smart-6286175a-3df9-4563-b127-bdd8b4c49d95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=746681034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.746681034
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2005798206
Short name T2634
Test name
Test status
Simulation time 141780774 ps
CPU time 1.92 seconds
Started Jun 29 04:45:51 PM PDT 24
Finished Jun 29 04:45:53 PM PDT 24
Peak memory 214280 kb
Host smart-adfc0c23-a0bd-4097-9eef-66e5441612b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005798206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2005798206
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3039995216
Short name T2665
Test name
Test status
Simulation time 141031042 ps
CPU time 1.11 seconds
Started Jun 29 04:45:33 PM PDT 24
Finished Jun 29 04:45:34 PM PDT 24
Peak memory 206080 kb
Host smart-b45ef1b5-a3c0-4856-a7f9-47fd6d7605ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3039995216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3039995216
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.622229536
Short name T2692
Test name
Test status
Simulation time 198446013 ps
CPU time 1.72 seconds
Started Jun 29 04:45:27 PM PDT 24
Finished Jun 29 04:45:29 PM PDT 24
Peak memory 206008 kb
Host smart-e7470c0b-87f1-494c-b796-a3c869722269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=622229536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.622229536
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2765163434
Short name T240
Test name
Test status
Simulation time 107791432 ps
CPU time 1.86 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:39 PM PDT 24
Peak memory 206072 kb
Host smart-84277f97-334f-4006-881e-e8ed08ffaea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2765163434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2765163434
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1085995286
Short name T2654
Test name
Test status
Simulation time 156884779 ps
CPU time 1.7 seconds
Started Jun 29 04:45:56 PM PDT 24
Finished Jun 29 04:45:59 PM PDT 24
Peak memory 214284 kb
Host smart-d07b8c51-7fe3-4eab-a06b-da17de85099b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085995286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1085995286
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4171132740
Short name T2657
Test name
Test status
Simulation time 83282476 ps
CPU time 0.85 seconds
Started Jun 29 04:45:48 PM PDT 24
Finished Jun 29 04:45:49 PM PDT 24
Peak memory 205872 kb
Host smart-08c5e103-f57d-4c50-9f29-e7772149cf9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4171132740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4171132740
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2430181889
Short name T286
Test name
Test status
Simulation time 45317120 ps
CPU time 0.73 seconds
Started Jun 29 04:45:38 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 205764 kb
Host smart-578d090e-50b4-45e3-82e3-8405af924afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2430181889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2430181889
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.377754692
Short name T2712
Test name
Test status
Simulation time 113728973 ps
CPU time 1.62 seconds
Started Jun 29 04:45:39 PM PDT 24
Finished Jun 29 04:45:42 PM PDT 24
Peak memory 205980 kb
Host smart-0e596671-1170-464a-ba48-87e24e6c93c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=377754692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.377754692
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3373573636
Short name T2667
Test name
Test status
Simulation time 192973771 ps
CPU time 1.96 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 206076 kb
Host smart-7a2277d5-32dc-4469-8509-b0c243604e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3373573636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3373573636
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2938567266
Short name T304
Test name
Test status
Simulation time 520114291 ps
CPU time 4.42 seconds
Started Jun 29 04:45:43 PM PDT 24
Finished Jun 29 04:45:48 PM PDT 24
Peak memory 206048 kb
Host smart-20433dfb-f762-4053-8a5c-e3f761bc5ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2938567266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2938567266
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3252204214
Short name T2630
Test name
Test status
Simulation time 302586712 ps
CPU time 3.57 seconds
Started Jun 29 04:45:30 PM PDT 24
Finished Jun 29 04:45:34 PM PDT 24
Peak memory 205992 kb
Host smart-6bc777fe-f887-4d16-86ed-3d7d02fffbf6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3252204214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3252204214
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3704313141
Short name T2638
Test name
Test status
Simulation time 653719628 ps
CPU time 4.46 seconds
Started Jun 29 04:45:28 PM PDT 24
Finished Jun 29 04:45:33 PM PDT 24
Peak memory 206044 kb
Host smart-c6564d5a-13b6-4a5b-a70f-bff3d23b48fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3704313141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3704313141
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1714075823
Short name T2669
Test name
Test status
Simulation time 193789114 ps
CPU time 1 seconds
Started Jun 29 04:45:24 PM PDT 24
Finished Jun 29 04:45:26 PM PDT 24
Peak memory 205916 kb
Host smart-ff9acb48-b707-4466-8d67-1af1a49a1d19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1714075823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1714075823
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3646095122
Short name T282
Test name
Test status
Simulation time 200268782 ps
CPU time 1.97 seconds
Started Jun 29 04:45:24 PM PDT 24
Finished Jun 29 04:45:26 PM PDT 24
Peak memory 214196 kb
Host smart-734b7ba5-fec1-4f04-8db6-56986682c92b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646095122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3646095122
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.41299260
Short name T274
Test name
Test status
Simulation time 44488718 ps
CPU time 0.83 seconds
Started Jun 29 04:45:24 PM PDT 24
Finished Jun 29 04:45:25 PM PDT 24
Peak memory 205916 kb
Host smart-637f0ff3-07ed-4262-a8f9-d8c118cd9ea2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=41299260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.41299260
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3186991569
Short name T2721
Test name
Test status
Simulation time 169318067 ps
CPU time 2.39 seconds
Started Jun 29 04:45:17 PM PDT 24
Finished Jun 29 04:45:19 PM PDT 24
Peak memory 215412 kb
Host smart-eafc63d6-fef8-414a-9b9a-bffd9f1c93b0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3186991569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3186991569
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2147811824
Short name T2675
Test name
Test status
Simulation time 259678552 ps
CPU time 2.59 seconds
Started Jun 29 04:45:17 PM PDT 24
Finished Jun 29 04:45:20 PM PDT 24
Peak memory 205928 kb
Host smart-24707e6a-bbf4-49a7-a050-abec9e2e5f2c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2147811824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2147811824
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3869425292
Short name T275
Test name
Test status
Simulation time 75846104 ps
CPU time 1.11 seconds
Started Jun 29 04:45:41 PM PDT 24
Finished Jun 29 04:45:43 PM PDT 24
Peak memory 205992 kb
Host smart-e9071884-467b-4aa5-bd65-53b38bc0893b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3869425292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3869425292
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.826121146
Short name T2713
Test name
Test status
Simulation time 159998115 ps
CPU time 1.83 seconds
Started Jun 29 04:45:29 PM PDT 24
Finished Jun 29 04:45:31 PM PDT 24
Peak memory 206072 kb
Host smart-79258cbe-8749-4c88-b574-8a45059e2da4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=826121146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.826121146
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3293776472
Short name T301
Test name
Test status
Simulation time 367159944 ps
CPU time 2.71 seconds
Started Jun 29 04:45:32 PM PDT 24
Finished Jun 29 04:45:35 PM PDT 24
Peak memory 206044 kb
Host smart-ff96f56c-18ea-4367-a56e-bd48cdaeb3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3293776472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3293776472
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2306395690
Short name T2690
Test name
Test status
Simulation time 57801590 ps
CPU time 0.7 seconds
Started Jun 29 04:45:42 PM PDT 24
Finished Jun 29 04:45:43 PM PDT 24
Peak memory 205760 kb
Host smart-14846881-b140-466f-95eb-c5d8cfa82621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2306395690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2306395690
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4270966597
Short name T2649
Test name
Test status
Simulation time 77742118 ps
CPU time 0.68 seconds
Started Jun 29 04:45:42 PM PDT 24
Finished Jun 29 04:45:43 PM PDT 24
Peak memory 205820 kb
Host smart-5671cb16-c5a2-41c8-b253-4bdaad59faf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4270966597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4270966597
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3221656633
Short name T2711
Test name
Test status
Simulation time 67322451 ps
CPU time 0.72 seconds
Started Jun 29 04:45:42 PM PDT 24
Finished Jun 29 04:45:43 PM PDT 24
Peak memory 205808 kb
Host smart-9861665b-fabd-4917-a151-0e380a78f5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3221656633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3221656633
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1050019789
Short name T2702
Test name
Test status
Simulation time 41109250 ps
CPU time 0.69 seconds
Started Jun 29 04:45:38 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 205820 kb
Host smart-3ea77563-71c0-4f43-bf9b-ee0de3ff3c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1050019789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1050019789
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.37577497
Short name T2660
Test name
Test status
Simulation time 47200791 ps
CPU time 0.66 seconds
Started Jun 29 04:45:36 PM PDT 24
Finished Jun 29 04:45:39 PM PDT 24
Peak memory 205788 kb
Host smart-7d38acac-38e0-42a6-9404-0aa890d2d6b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=37577497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.37577497
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2984086606
Short name T2719
Test name
Test status
Simulation time 44209512 ps
CPU time 0.73 seconds
Started Jun 29 04:45:40 PM PDT 24
Finished Jun 29 04:45:42 PM PDT 24
Peak memory 205820 kb
Host smart-31b71694-5ad8-4ab5-8556-fe96c99b9c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2984086606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2984086606
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.826288878
Short name T2715
Test name
Test status
Simulation time 54387746 ps
CPU time 0.69 seconds
Started Jun 29 04:45:49 PM PDT 24
Finished Jun 29 04:45:50 PM PDT 24
Peak memory 205852 kb
Host smart-61b01ee9-66ec-462f-88af-db1e2bb0788d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=826288878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.826288878
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3980450688
Short name T285
Test name
Test status
Simulation time 47659941 ps
CPU time 0.72 seconds
Started Jun 29 04:45:46 PM PDT 24
Finished Jun 29 04:45:47 PM PDT 24
Peak memory 205764 kb
Host smart-4fb76077-6a16-443d-8bf9-368bf1466a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3980450688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3980450688
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.4240596131
Short name T223
Test name
Test status
Simulation time 45556585 ps
CPU time 0.68 seconds
Started Jun 29 04:45:49 PM PDT 24
Finished Jun 29 04:45:50 PM PDT 24
Peak memory 205832 kb
Host smart-ea3ba9d7-4562-4c14-84ee-5cba757a95bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4240596131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.4240596131
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4278226848
Short name T2725
Test name
Test status
Simulation time 64228825 ps
CPU time 0.73 seconds
Started Jun 29 04:45:36 PM PDT 24
Finished Jun 29 04:45:39 PM PDT 24
Peak memory 205760 kb
Host smart-e06f1461-1de9-436e-8c76-993040c7928d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4278226848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.4278226848
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1769979842
Short name T265
Test name
Test status
Simulation time 99539689 ps
CPU time 2.04 seconds
Started Jun 29 04:45:21 PM PDT 24
Finished Jun 29 04:45:23 PM PDT 24
Peak memory 206028 kb
Host smart-ea80af36-8580-4dd8-b7de-f5fdde714662
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1769979842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1769979842
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3686409437
Short name T263
Test name
Test status
Simulation time 1712069411 ps
CPU time 8.62 seconds
Started Jun 29 04:45:19 PM PDT 24
Finished Jun 29 04:45:28 PM PDT 24
Peak memory 205924 kb
Host smart-73c1205d-64d0-4af7-8821-d67ad6088b7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3686409437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3686409437
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3416374818
Short name T2678
Test name
Test status
Simulation time 306186797 ps
CPU time 1.12 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:33 PM PDT 24
Peak memory 205948 kb
Host smart-3b4ed2aa-a0fa-4e4d-9aa4-e0b0a5e411e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3416374818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3416374818
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.801901695
Short name T251
Test name
Test status
Simulation time 231422905 ps
CPU time 1.97 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:34 PM PDT 24
Peak memory 214280 kb
Host smart-2cc98feb-b555-4461-acdb-cf2868e48642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801901695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.801901695
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.572067801
Short name T2682
Test name
Test status
Simulation time 43863660 ps
CPU time 0.83 seconds
Started Jun 29 04:45:23 PM PDT 24
Finished Jun 29 04:45:24 PM PDT 24
Peak memory 205860 kb
Host smart-c4b90c64-6bcf-408b-9aa2-f00bdfdb143b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=572067801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.572067801
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1782711727
Short name T300
Test name
Test status
Simulation time 101710876 ps
CPU time 0.71 seconds
Started Jun 29 04:45:28 PM PDT 24
Finished Jun 29 04:45:29 PM PDT 24
Peak memory 205852 kb
Host smart-881f86d1-1306-4995-a04e-7ea78f55b50c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1782711727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1782711727
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1662108040
Short name T271
Test name
Test status
Simulation time 124403924 ps
CPU time 1.55 seconds
Started Jun 29 04:45:29 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 214196 kb
Host smart-04051eb6-fd3c-407c-9ca2-fef98c2ff6ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1662108040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1662108040
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.746101501
Short name T2718
Test name
Test status
Simulation time 703626309 ps
CPU time 4.67 seconds
Started Jun 29 04:45:22 PM PDT 24
Finished Jun 29 04:45:27 PM PDT 24
Peak memory 205944 kb
Host smart-e8ce926c-4227-4f23-b880-a941c9f54492
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=746101501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.746101501
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3093632587
Short name T279
Test name
Test status
Simulation time 90037762 ps
CPU time 1.1 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:33 PM PDT 24
Peak memory 206052 kb
Host smart-2a9c8cc8-0af5-4991-8499-db7c48b7f6e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3093632587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3093632587
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.801456982
Short name T2685
Test name
Test status
Simulation time 171745587 ps
CPU time 2.01 seconds
Started Jun 29 04:45:22 PM PDT 24
Finished Jun 29 04:45:25 PM PDT 24
Peak memory 214288 kb
Host smart-718dea51-a38c-45d9-afc9-971cded4bea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=801456982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.801456982
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2226890330
Short name T2677
Test name
Test status
Simulation time 452283850 ps
CPU time 2.58 seconds
Started Jun 29 04:45:18 PM PDT 24
Finished Jun 29 04:45:21 PM PDT 24
Peak memory 206084 kb
Host smart-96e3a9e9-6625-40c9-803c-afdafc038fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2226890330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2226890330
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.823293476
Short name T2700
Test name
Test status
Simulation time 39776497 ps
CPU time 0.66 seconds
Started Jun 29 04:45:40 PM PDT 24
Finished Jun 29 04:45:42 PM PDT 24
Peak memory 205852 kb
Host smart-ded3e1ce-5aba-4e28-a8bc-7357f701cdf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=823293476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.823293476
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2149208453
Short name T2696
Test name
Test status
Simulation time 51707005 ps
CPU time 0.72 seconds
Started Jun 29 04:45:38 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 205764 kb
Host smart-a8f46005-985c-483f-8bef-c32e7a63ede0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2149208453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2149208453
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3411870948
Short name T297
Test name
Test status
Simulation time 41189437 ps
CPU time 0.67 seconds
Started Jun 29 04:45:52 PM PDT 24
Finished Jun 29 04:45:53 PM PDT 24
Peak memory 205812 kb
Host smart-94afc7f0-7b99-4723-a2f8-5da5eae8f15a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3411870948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3411870948
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1928391818
Short name T2733
Test name
Test status
Simulation time 44631061 ps
CPU time 0.68 seconds
Started Jun 29 04:45:51 PM PDT 24
Finished Jun 29 04:45:52 PM PDT 24
Peak memory 205820 kb
Host smart-91f9610a-c256-4b5c-bd0c-fc1449789306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1928391818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1928391818
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.746948111
Short name T2666
Test name
Test status
Simulation time 37318261 ps
CPU time 0.66 seconds
Started Jun 29 04:45:53 PM PDT 24
Finished Jun 29 04:45:54 PM PDT 24
Peak memory 205852 kb
Host smart-2655364a-e4c3-4ddd-97da-c6e81afa1037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=746948111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.746948111
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1738435363
Short name T2688
Test name
Test status
Simulation time 42058978 ps
CPU time 0.73 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:33 PM PDT 24
Peak memory 205816 kb
Host smart-8f38a59c-9c8d-4599-a218-5669f71bc410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1738435363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1738435363
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3820348564
Short name T2650
Test name
Test status
Simulation time 48536571 ps
CPU time 0.71 seconds
Started Jun 29 04:45:54 PM PDT 24
Finished Jun 29 04:45:56 PM PDT 24
Peak memory 205820 kb
Host smart-3e72390d-f596-4ad1-b262-354929f2fa98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3820348564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3820348564
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2466271862
Short name T287
Test name
Test status
Simulation time 63259341 ps
CPU time 0.68 seconds
Started Jun 29 04:45:50 PM PDT 24
Finished Jun 29 04:45:51 PM PDT 24
Peak memory 205808 kb
Host smart-42b700d2-2ec5-475e-bf39-1754691ed5bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2466271862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2466271862
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2863686815
Short name T2683
Test name
Test status
Simulation time 49486990 ps
CPU time 0.67 seconds
Started Jun 29 04:45:45 PM PDT 24
Finished Jun 29 04:45:46 PM PDT 24
Peak memory 205816 kb
Host smart-dd94a456-16b8-4b73-920c-f917f9bf5721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2863686815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2863686815
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2565489011
Short name T2709
Test name
Test status
Simulation time 127231984 ps
CPU time 3.34 seconds
Started Jun 29 04:45:28 PM PDT 24
Finished Jun 29 04:45:32 PM PDT 24
Peak memory 206028 kb
Host smart-aaa8532c-4f71-4ee1-a133-dfbf19d294f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2565489011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2565489011
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2480557257
Short name T2674
Test name
Test status
Simulation time 926539239 ps
CPU time 5.1 seconds
Started Jun 29 04:45:29 PM PDT 24
Finished Jun 29 04:45:35 PM PDT 24
Peak memory 206076 kb
Host smart-eaafd0ad-2548-4881-b077-4e6139283746
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2480557257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2480557257
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1171553331
Short name T2732
Test name
Test status
Simulation time 48384847 ps
CPU time 0.77 seconds
Started Jun 29 04:45:29 PM PDT 24
Finished Jun 29 04:45:30 PM PDT 24
Peak memory 205948 kb
Host smart-6db8486a-0a94-497c-9149-30de5b8e01c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1171553331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1171553331
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2446725775
Short name T2670
Test name
Test status
Simulation time 192305235 ps
CPU time 1.66 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:34 PM PDT 24
Peak memory 214260 kb
Host smart-322ec9b8-8d89-4f49-b773-be8a93eb6839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446725775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2446725775
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3629453879
Short name T2694
Test name
Test status
Simulation time 127561754 ps
CPU time 0.86 seconds
Started Jun 29 04:45:37 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 205896 kb
Host smart-057b727a-bddd-4eaa-9841-51e4a52ffa18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3629453879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3629453879
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.159268819
Short name T2724
Test name
Test status
Simulation time 59120035 ps
CPU time 0.7 seconds
Started Jun 29 04:45:20 PM PDT 24
Finished Jun 29 04:45:21 PM PDT 24
Peak memory 205764 kb
Host smart-5e1caed1-a8cf-4bb3-b724-8d7c6a310db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=159268819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.159268819
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4007833443
Short name T262
Test name
Test status
Simulation time 128409068 ps
CPU time 1.56 seconds
Started Jun 29 04:45:30 PM PDT 24
Finished Jun 29 04:45:32 PM PDT 24
Peak memory 214284 kb
Host smart-e11de2ed-30e5-479c-ab86-d75402d2c328
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4007833443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4007833443
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.977809574
Short name T2644
Test name
Test status
Simulation time 624838051 ps
CPU time 4.44 seconds
Started Jun 29 04:45:27 PM PDT 24
Finished Jun 29 04:45:32 PM PDT 24
Peak memory 205976 kb
Host smart-b8e0cdf5-8c27-4728-a002-a0baa09825a5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=977809574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.977809574
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.198989764
Short name T216
Test name
Test status
Simulation time 187600388 ps
CPU time 1.65 seconds
Started Jun 29 04:45:29 PM PDT 24
Finished Jun 29 04:45:31 PM PDT 24
Peak memory 206008 kb
Host smart-a918f14b-0dd0-47bc-8b6b-e6afa7f306c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=198989764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.198989764
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1027764490
Short name T233
Test name
Test status
Simulation time 122412942 ps
CPU time 3.34 seconds
Started Jun 29 04:45:30 PM PDT 24
Finished Jun 29 04:45:34 PM PDT 24
Peak memory 222132 kb
Host smart-88307a23-02fb-4b31-a364-3090c190e973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1027764490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1027764490
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3395769289
Short name T303
Test name
Test status
Simulation time 373097225 ps
CPU time 2.44 seconds
Started Jun 29 04:45:23 PM PDT 24
Finished Jun 29 04:45:25 PM PDT 24
Peak memory 206108 kb
Host smart-7d6ac6dc-f6f4-45ae-8138-1040b1904f03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3395769289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3395769289
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.448307859
Short name T2698
Test name
Test status
Simulation time 41085332 ps
CPU time 0.7 seconds
Started Jun 29 04:45:39 PM PDT 24
Finished Jun 29 04:45:41 PM PDT 24
Peak memory 205852 kb
Host smart-f6726576-da31-4122-a3f5-80c1367201e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=448307859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.448307859
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2387237804
Short name T2680
Test name
Test status
Simulation time 34516681 ps
CPU time 0.67 seconds
Started Jun 29 04:45:42 PM PDT 24
Finished Jun 29 04:45:43 PM PDT 24
Peak memory 205732 kb
Host smart-9d5bc16c-df17-4195-99fb-3d21f2aa4e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2387237804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2387237804
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3737895742
Short name T298
Test name
Test status
Simulation time 36233264 ps
CPU time 0.72 seconds
Started Jun 29 04:45:52 PM PDT 24
Finished Jun 29 04:45:53 PM PDT 24
Peak memory 205816 kb
Host smart-d6573113-092b-46c9-a366-0f450a3dcd6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3737895742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3737895742
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1532524906
Short name T291
Test name
Test status
Simulation time 45233484 ps
CPU time 0.68 seconds
Started Jun 29 04:45:41 PM PDT 24
Finished Jun 29 04:45:42 PM PDT 24
Peak memory 205820 kb
Host smart-0481d742-d353-49cb-b599-c94284482e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1532524906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1532524906
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3957041070
Short name T299
Test name
Test status
Simulation time 38315155 ps
CPU time 0.67 seconds
Started Jun 29 04:45:37 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 205804 kb
Host smart-1ea6c06d-5e85-430c-bf71-d67d0ad12c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3957041070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3957041070
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4008076633
Short name T2673
Test name
Test status
Simulation time 44010216 ps
CPU time 0.68 seconds
Started Jun 29 04:45:39 PM PDT 24
Finished Jun 29 04:45:41 PM PDT 24
Peak memory 205824 kb
Host smart-7ede5e3f-c869-4719-b478-31f6886a09df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4008076633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.4008076633
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.93962686
Short name T2722
Test name
Test status
Simulation time 44012174 ps
CPU time 0.67 seconds
Started Jun 29 04:45:46 PM PDT 24
Finished Jun 29 04:45:47 PM PDT 24
Peak memory 205844 kb
Host smart-a60c46c3-74c2-43fe-9283-88d48bdb0b55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=93962686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.93962686
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.527621230
Short name T289
Test name
Test status
Simulation time 71507027 ps
CPU time 0.71 seconds
Started Jun 29 04:45:37 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 205852 kb
Host smart-e1886e6a-0dcb-4e84-b865-8ad8459ede32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=527621230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.527621230
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2114761539
Short name T2735
Test name
Test status
Simulation time 131434652 ps
CPU time 1.21 seconds
Started Jun 29 04:45:34 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 222432 kb
Host smart-37af482d-a6e9-4b03-a063-3444e4b0d4de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114761539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2114761539
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1672791443
Short name T2686
Test name
Test status
Simulation time 55562634 ps
CPU time 0.94 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:33 PM PDT 24
Peak memory 205992 kb
Host smart-a5c17dc0-8000-4a59-9b32-2cab8d7b9e4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1672791443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1672791443
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3641977565
Short name T283
Test name
Test status
Simulation time 55305780 ps
CPU time 0.69 seconds
Started Jun 29 04:45:20 PM PDT 24
Finished Jun 29 04:45:21 PM PDT 24
Peak memory 205848 kb
Host smart-f0dfdfb8-4286-4f22-8c24-47338c832bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3641977565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3641977565
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2829227175
Short name T2637
Test name
Test status
Simulation time 123917429 ps
CPU time 1.93 seconds
Started Jun 29 04:45:30 PM PDT 24
Finished Jun 29 04:45:32 PM PDT 24
Peak memory 205964 kb
Host smart-493763c7-2d6e-4fc4-aad8-a23b49c91f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2829227175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2829227175
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1739220329
Short name T2707
Test name
Test status
Simulation time 127370468 ps
CPU time 1.55 seconds
Started Jun 29 04:45:28 PM PDT 24
Finished Jun 29 04:45:30 PM PDT 24
Peak memory 206108 kb
Host smart-6f6f3988-4bdf-4eff-9748-8b72461fd134
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1739220329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1739220329
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3474316122
Short name T2691
Test name
Test status
Simulation time 318979986 ps
CPU time 2.65 seconds
Started Jun 29 04:45:24 PM PDT 24
Finished Jun 29 04:45:28 PM PDT 24
Peak memory 206092 kb
Host smart-5d4da9b6-a566-4cd4-8040-27bd2292df1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3474316122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3474316122
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3139568292
Short name T2734
Test name
Test status
Simulation time 285904530 ps
CPU time 1.87 seconds
Started Jun 29 04:45:25 PM PDT 24
Finished Jun 29 04:45:33 PM PDT 24
Peak memory 217780 kb
Host smart-7c3e40f1-0edc-43f2-98a0-6aab015c7421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139568292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3139568292
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3083965132
Short name T266
Test name
Test status
Simulation time 105965630 ps
CPU time 1.01 seconds
Started Jun 29 04:45:30 PM PDT 24
Finished Jun 29 04:45:32 PM PDT 24
Peak memory 205924 kb
Host smart-1e398f49-5126-40ca-8dd4-75274ce620bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3083965132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3083965132
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3148771735
Short name T292
Test name
Test status
Simulation time 95127243 ps
CPU time 0.76 seconds
Started Jun 29 04:45:28 PM PDT 24
Finished Jun 29 04:45:29 PM PDT 24
Peak memory 205796 kb
Host smart-03c26419-29ac-41ae-ba59-a31daa3921f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3148771735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3148771735
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3421690971
Short name T2632
Test name
Test status
Simulation time 84875017 ps
CPU time 1.13 seconds
Started Jun 29 04:45:31 PM PDT 24
Finished Jun 29 04:45:40 PM PDT 24
Peak memory 206008 kb
Host smart-6ee038da-2fa0-484e-87c2-f06761140bc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3421690971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3421690971
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1202280411
Short name T2684
Test name
Test status
Simulation time 179049774 ps
CPU time 1.68 seconds
Started Jun 29 04:45:24 PM PDT 24
Finished Jun 29 04:45:26 PM PDT 24
Peak memory 206080 kb
Host smart-23178ca7-1745-4014-b0dd-63ad903d6f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1202280411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1202280411
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.729755198
Short name T2662
Test name
Test status
Simulation time 95064227 ps
CPU time 1.26 seconds
Started Jun 29 04:45:21 PM PDT 24
Finished Jun 29 04:45:23 PM PDT 24
Peak memory 214256 kb
Host smart-ec11784a-d7de-46e3-bf4c-d5d65d9df3b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729755198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.729755198
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2114748322
Short name T2708
Test name
Test status
Simulation time 41333686 ps
CPU time 0.79 seconds
Started Jun 29 04:45:40 PM PDT 24
Finished Jun 29 04:45:42 PM PDT 24
Peak memory 205928 kb
Host smart-3eed62a4-f255-4b8e-b1b2-02d817bdc9ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2114748322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2114748322
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2845803085
Short name T2699
Test name
Test status
Simulation time 39549789 ps
CPU time 0.66 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:36 PM PDT 24
Peak memory 205784 kb
Host smart-dd6aa46a-c49f-4eae-8e1b-71c06233418f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2845803085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2845803085
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1483603465
Short name T2663
Test name
Test status
Simulation time 298123057 ps
CPU time 2.09 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:39 PM PDT 24
Peak memory 206056 kb
Host smart-8268bf6d-b2fe-4e44-80e7-a019aa25101f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1483603465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1483603465
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1623923588
Short name T232
Test name
Test status
Simulation time 69084119 ps
CPU time 1.56 seconds
Started Jun 29 04:45:28 PM PDT 24
Finished Jun 29 04:45:30 PM PDT 24
Peak memory 214248 kb
Host smart-e6045a9a-83a4-48e4-9776-03b7301616d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1623923588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1623923588
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2389542936
Short name T309
Test name
Test status
Simulation time 858261664 ps
CPU time 2.91 seconds
Started Jun 29 04:45:28 PM PDT 24
Finished Jun 29 04:45:31 PM PDT 24
Peak memory 206076 kb
Host smart-4cb548e0-cd33-41a3-bb0c-7ea82686d6f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2389542936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2389542936
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.786117234
Short name T242
Test name
Test status
Simulation time 148865961 ps
CPU time 2.5 seconds
Started Jun 29 04:45:36 PM PDT 24
Finished Jun 29 04:45:41 PM PDT 24
Peak memory 214336 kb
Host smart-9cfddf61-e268-4969-b0dc-68726bba6ae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786117234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.786117234
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3293584196
Short name T2668
Test name
Test status
Simulation time 61404553 ps
CPU time 0.84 seconds
Started Jun 29 04:45:29 PM PDT 24
Finished Jun 29 04:45:30 PM PDT 24
Peak memory 205876 kb
Host smart-60765bc4-88c3-4d20-a7a5-eb6a88f8bd16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3293584196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3293584196
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2197172635
Short name T222
Test name
Test status
Simulation time 50418189 ps
CPU time 0.7 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:38 PM PDT 24
Peak memory 205848 kb
Host smart-a0501d73-0e34-40e8-8051-7c2837a12100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2197172635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2197172635
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1501452401
Short name T280
Test name
Test status
Simulation time 289414224 ps
CPU time 1.79 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:38 PM PDT 24
Peak memory 205992 kb
Host smart-64ae8b5b-d75e-4080-bd56-96b143911cee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1501452401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1501452401
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2703864918
Short name T2706
Test name
Test status
Simulation time 65774447 ps
CPU time 1.68 seconds
Started Jun 29 04:45:23 PM PDT 24
Finished Jun 29 04:45:25 PM PDT 24
Peak memory 221812 kb
Host smart-8217fd01-5393-4b86-bf84-e6454ab3b1b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2703864918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2703864918
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.41571132
Short name T302
Test name
Test status
Simulation time 417112751 ps
CPU time 2.56 seconds
Started Jun 29 04:45:22 PM PDT 24
Finished Jun 29 04:45:25 PM PDT 24
Peak memory 206068 kb
Host smart-c4bb2001-0cb9-4e94-8846-2d6d48ac290b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=41571132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.41571132
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.72495652
Short name T2646
Test name
Test status
Simulation time 101699712 ps
CPU time 1.31 seconds
Started Jun 29 04:45:36 PM PDT 24
Finished Jun 29 04:45:39 PM PDT 24
Peak memory 214276 kb
Host smart-13dd779b-c5e4-4237-bbdd-97a578e4458a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72495652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_
csr_mem_rw_with_rand_reset.72495652
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.782353301
Short name T2681
Test name
Test status
Simulation time 87964650 ps
CPU time 1 seconds
Started Jun 29 04:45:46 PM PDT 24
Finished Jun 29 04:45:47 PM PDT 24
Peak memory 206036 kb
Host smart-36950306-4612-4861-81ee-70eadb7e1c40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=782353301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.782353301
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1320406483
Short name T2659
Test name
Test status
Simulation time 91747554 ps
CPU time 0.74 seconds
Started Jun 29 04:45:36 PM PDT 24
Finished Jun 29 04:45:39 PM PDT 24
Peak memory 205852 kb
Host smart-3786f46b-c86c-4425-aff3-96c15958fc32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1320406483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1320406483
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2558901271
Short name T2729
Test name
Test status
Simulation time 72661596 ps
CPU time 1.06 seconds
Started Jun 29 04:45:35 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 205988 kb
Host smart-56c6589a-eca8-44c4-8a71-09e1a229247d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2558901271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2558901271
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.147244331
Short name T2647
Test name
Test status
Simulation time 89432308 ps
CPU time 2.14 seconds
Started Jun 29 04:45:30 PM PDT 24
Finished Jun 29 04:45:33 PM PDT 24
Peak memory 221732 kb
Host smart-c6edba07-26af-4a70-9030-d4fdb4095ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=147244331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.147244331
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.790864390
Short name T2645
Test name
Test status
Simulation time 577527446 ps
CPU time 3.1 seconds
Started Jun 29 04:45:33 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 206076 kb
Host smart-2086fab0-18e0-4383-9390-3fe3a0e92968
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=790864390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.790864390
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2195915784
Short name T2070
Test name
Test status
Simulation time 4343265413 ps
CPU time 5.78 seconds
Started Jun 29 06:33:31 PM PDT 24
Finished Jun 29 06:33:38 PM PDT 24
Peak memory 206512 kb
Host smart-ce398942-0246-4690-9d37-33c6c0062c75
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2195915784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.2195915784
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3926964323
Short name T618
Test name
Test status
Simulation time 13351718570 ps
CPU time 15.38 seconds
Started Jun 29 06:33:31 PM PDT 24
Finished Jun 29 06:33:47 PM PDT 24
Peak memory 206656 kb
Host smart-fa6e08d8-d255-447f-9eaa-1457004af03d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3926964323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3926964323
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2728256941
Short name T869
Test name
Test status
Simulation time 23397014937 ps
CPU time 23.05 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:33:49 PM PDT 24
Peak memory 206328 kb
Host smart-cafcb950-85f2-41b5-b9fc-99b00300e00c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2728256941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.2728256941
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3718480847
Short name T734
Test name
Test status
Simulation time 152580748 ps
CPU time 0.74 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:33:28 PM PDT 24
Peak memory 206216 kb
Host smart-3390dc32-3bc7-4d00-9d09-4ca39f152d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37184
80847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3718480847
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.2082172376
Short name T1817
Test name
Test status
Simulation time 145289688 ps
CPU time 0.78 seconds
Started Jun 29 06:33:23 PM PDT 24
Finished Jun 29 06:33:24 PM PDT 24
Peak memory 206204 kb
Host smart-3b43892f-6014-4c09-ad87-08d5ed7183d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20821
72376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.2082172376
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.4071417637
Short name T939
Test name
Test status
Simulation time 684137039 ps
CPU time 1.97 seconds
Started Jun 29 06:33:27 PM PDT 24
Finished Jun 29 06:33:31 PM PDT 24
Peak memory 206312 kb
Host smart-5d2eb665-a1f1-4b69-8c3c-4e2513c87bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40714
17637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.4071417637
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2163674585
Short name T160
Test name
Test status
Simulation time 1106562100 ps
CPU time 2.84 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:33:30 PM PDT 24
Peak memory 206272 kb
Host smart-d10ec0e7-2b13-4246-86e7-c6573b38db63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21636
74585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2163674585
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.1378615428
Short name T770
Test name
Test status
Simulation time 7379096264 ps
CPU time 14.22 seconds
Started Jun 29 06:33:30 PM PDT 24
Finished Jun 29 06:33:45 PM PDT 24
Peak memory 206420 kb
Host smart-a038a491-db39-4bec-ac66-246b57d4b335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13786
15428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.1378615428
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.966043720
Short name T2413
Test name
Test status
Simulation time 362297244 ps
CPU time 1.25 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:33:29 PM PDT 24
Peak memory 206164 kb
Host smart-1df079a6-b81f-4b88-b174-4793bb28e641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96604
3720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.966043720
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.3712503512
Short name T2239
Test name
Test status
Simulation time 169434100 ps
CPU time 0.75 seconds
Started Jun 29 06:33:30 PM PDT 24
Finished Jun 29 06:33:31 PM PDT 24
Peak memory 206136 kb
Host smart-0a309761-caf7-4ca8-b91e-50ec642e9ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37125
03512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3712503512
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.961284715
Short name T832
Test name
Test status
Simulation time 5124851563 ps
CPU time 132.63 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:35:41 PM PDT 24
Peak memory 206464 kb
Host smart-24b3b465-6c74-4460-96d7-2230ff2b828d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96128
4715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.961284715
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.2261579879
Short name T1038
Test name
Test status
Simulation time 53707551 ps
CPU time 0.67 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:33:29 PM PDT 24
Peak memory 206148 kb
Host smart-a0047cde-0349-4e58-ba5e-8e5308264ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22615
79879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2261579879
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.558944861
Short name T1057
Test name
Test status
Simulation time 1016586074 ps
CPU time 2.42 seconds
Started Jun 29 06:33:37 PM PDT 24
Finished Jun 29 06:33:40 PM PDT 24
Peak memory 206336 kb
Host smart-2ef3f0be-29b1-469f-861e-26510883bf35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55894
4861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.558944861
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.4051362672
Short name T1801
Test name
Test status
Simulation time 340194711 ps
CPU time 2.55 seconds
Started Jun 29 06:33:33 PM PDT 24
Finished Jun 29 06:33:37 PM PDT 24
Peak memory 206304 kb
Host smart-cf2aa898-c9b1-4fac-a636-94ee204220e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40513
62672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.4051362672
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2851507820
Short name T1691
Test name
Test status
Simulation time 160342451 ps
CPU time 0.82 seconds
Started Jun 29 06:33:32 PM PDT 24
Finished Jun 29 06:33:34 PM PDT 24
Peak memory 206212 kb
Host smart-ed450e58-6b22-4b6d-b5cf-815dc31c0132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28515
07820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2851507820
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3993044866
Short name T2391
Test name
Test status
Simulation time 192598801 ps
CPU time 0.86 seconds
Started Jun 29 06:33:34 PM PDT 24
Finished Jun 29 06:33:36 PM PDT 24
Peak memory 206136 kb
Host smart-7c460dc2-f88f-4fb9-ae35-d2e95e2bebea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39930
44866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3993044866
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1772017817
Short name T768
Test name
Test status
Simulation time 178521987 ps
CPU time 0.8 seconds
Started Jun 29 06:33:35 PM PDT 24
Finished Jun 29 06:33:37 PM PDT 24
Peak memory 206184 kb
Host smart-7fe7be9a-8964-4c25-b313-b5a5bc9755f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17720
17817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1772017817
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1658144398
Short name T2345
Test name
Test status
Simulation time 229812390 ps
CPU time 0.87 seconds
Started Jun 29 06:33:32 PM PDT 24
Finished Jun 29 06:33:34 PM PDT 24
Peak memory 206192 kb
Host smart-07d1c090-4f7e-479b-8c14-7591b8cb96ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16581
44398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1658144398
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.311636642
Short name T79
Test name
Test status
Simulation time 539730642 ps
CPU time 1.49 seconds
Started Jun 29 06:33:35 PM PDT 24
Finished Jun 29 06:33:37 PM PDT 24
Peak memory 206204 kb
Host smart-8fb4909b-fb81-4279-8a56-c5cd76641e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31163
6642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.311636642
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.57990966
Short name T1078
Test name
Test status
Simulation time 23279331842 ps
CPU time 22.51 seconds
Started Jun 29 06:33:35 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 206316 kb
Host smart-2c2fc4f2-cd29-4c79-acdf-c58d0c7a3e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57990
966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.57990966
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1933877926
Short name T860
Test name
Test status
Simulation time 3318446180 ps
CPU time 4.5 seconds
Started Jun 29 06:33:34 PM PDT 24
Finished Jun 29 06:33:39 PM PDT 24
Peak memory 206260 kb
Host smart-a1c3dbdb-4169-404b-b7f3-2898acdd4cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19338
77926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1933877926
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3340995415
Short name T419
Test name
Test status
Simulation time 6687660045 ps
CPU time 65.81 seconds
Started Jun 29 06:33:34 PM PDT 24
Finished Jun 29 06:34:41 PM PDT 24
Peak memory 206428 kb
Host smart-a4f21d36-a716-447a-a055-0fe15a722104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33409
95415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3340995415
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.4073046956
Short name T571
Test name
Test status
Simulation time 4320899698 ps
CPU time 127.15 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 206460 kb
Host smart-a07e8b1c-ccd5-4f3e-8e5e-43679a093a41
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4073046956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.4073046956
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3717389401
Short name T510
Test name
Test status
Simulation time 261244943 ps
CPU time 0.95 seconds
Started Jun 29 06:33:34 PM PDT 24
Finished Jun 29 06:33:35 PM PDT 24
Peak memory 206220 kb
Host smart-103760bb-f57a-4e0f-bfb4-eabe60597769
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3717389401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3717389401
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2635089803
Short name T2309
Test name
Test status
Simulation time 205278028 ps
CPU time 0.88 seconds
Started Jun 29 06:33:35 PM PDT 24
Finished Jun 29 06:33:37 PM PDT 24
Peak memory 206216 kb
Host smart-c1d11b9a-4f17-4bc3-bff6-1703a3bf8801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26350
89803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2635089803
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.3464317004
Short name T1924
Test name
Test status
Simulation time 5141711998 ps
CPU time 144.14 seconds
Started Jun 29 06:33:35 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206372 kb
Host smart-95b57874-5b2b-443d-97e0-2c3633f08f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34643
17004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3464317004
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.2587932957
Short name T2173
Test name
Test status
Simulation time 5679648447 ps
CPU time 161.22 seconds
Started Jun 29 06:33:33 PM PDT 24
Finished Jun 29 06:36:15 PM PDT 24
Peak memory 206452 kb
Host smart-c30a98ce-32a8-452b-a651-91c48d281db0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2587932957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.2587932957
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1363022953
Short name T1797
Test name
Test status
Simulation time 183872943 ps
CPU time 0.84 seconds
Started Jun 29 06:33:32 PM PDT 24
Finished Jun 29 06:33:33 PM PDT 24
Peak memory 206220 kb
Host smart-53d36150-f1de-4dcc-ae25-5928c186f6e3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1363022953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1363022953
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.390666526
Short name T1472
Test name
Test status
Simulation time 140779112 ps
CPU time 0.77 seconds
Started Jun 29 06:33:33 PM PDT 24
Finished Jun 29 06:33:35 PM PDT 24
Peak memory 206208 kb
Host smart-6cb72a94-a71f-43d6-aa8c-133a945412b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39066
6526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.390666526
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2539918920
Short name T78
Test name
Test status
Simulation time 478314103 ps
CPU time 1.27 seconds
Started Jun 29 06:33:36 PM PDT 24
Finished Jun 29 06:33:38 PM PDT 24
Peak memory 206192 kb
Host smart-c0ca1e5d-cad9-4d28-a1db-2d555a73829a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25399
18920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2539918920
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3234979598
Short name T1651
Test name
Test status
Simulation time 159228405 ps
CPU time 0.85 seconds
Started Jun 29 06:33:32 PM PDT 24
Finished Jun 29 06:33:34 PM PDT 24
Peak memory 206204 kb
Host smart-47b7d62f-c54b-40e3-9cfe-add0add1ee01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32349
79598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3234979598
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.4089556969
Short name T346
Test name
Test status
Simulation time 227435636 ps
CPU time 0.85 seconds
Started Jun 29 06:33:32 PM PDT 24
Finished Jun 29 06:33:33 PM PDT 24
Peak memory 206216 kb
Host smart-0a19de8d-ce74-452a-8e38-f14319636f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40895
56969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.4089556969
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3186783941
Short name T1452
Test name
Test status
Simulation time 177672514 ps
CPU time 0.83 seconds
Started Jun 29 06:33:33 PM PDT 24
Finished Jun 29 06:33:34 PM PDT 24
Peak memory 206196 kb
Host smart-9454b6ed-5272-4b2c-b5e1-a32a771c19cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31867
83941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3186783941
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.250650602
Short name T2506
Test name
Test status
Simulation time 183534912 ps
CPU time 0.81 seconds
Started Jun 29 06:33:35 PM PDT 24
Finished Jun 29 06:33:37 PM PDT 24
Peak memory 206184 kb
Host smart-4fe9c1f1-c5b3-46e2-a468-b45d49091c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25065
0602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.250650602
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.311299700
Short name T1812
Test name
Test status
Simulation time 173689948 ps
CPU time 0.81 seconds
Started Jun 29 06:33:32 PM PDT 24
Finished Jun 29 06:33:34 PM PDT 24
Peak memory 206168 kb
Host smart-deb3bbed-4783-48f8-826d-4fa2284230f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31129
9700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.311299700
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.186657295
Short name T512
Test name
Test status
Simulation time 218357823 ps
CPU time 0.9 seconds
Started Jun 29 06:33:31 PM PDT 24
Finished Jun 29 06:33:33 PM PDT 24
Peak memory 206220 kb
Host smart-b7520a21-b4bf-4fc6-a16d-9ce5faa18891
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=186657295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.186657295
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.453637172
Short name T726
Test name
Test status
Simulation time 258915510 ps
CPU time 0.92 seconds
Started Jun 29 06:33:32 PM PDT 24
Finished Jun 29 06:33:34 PM PDT 24
Peak memory 206196 kb
Host smart-1e9c0382-992f-41f7-bb93-5d56ac62b13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45363
7172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.453637172
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.104878613
Short name T884
Test name
Test status
Simulation time 283776714 ps
CPU time 1.05 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206216 kb
Host smart-4c9a3694-2467-41bc-b795-307f5532d9a4
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=104878613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.104878613
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1462972531
Short name T217
Test name
Test status
Simulation time 244435537 ps
CPU time 0.95 seconds
Started Jun 29 06:33:36 PM PDT 24
Finished Jun 29 06:33:38 PM PDT 24
Peak memory 206160 kb
Host smart-c2a7e9bc-0e4b-4992-8727-3993943770e2
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1462972531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1462972531
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2795347000
Short name T2346
Test name
Test status
Simulation time 11959415502 ps
CPU time 25.61 seconds
Started Jun 29 06:33:32 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 206448 kb
Host smart-5ee4c5ae-3211-4ad1-9827-30291e577421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27953
47000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2795347000
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2163569479
Short name T2183
Test name
Test status
Simulation time 207888520 ps
CPU time 0.84 seconds
Started Jun 29 06:33:38 PM PDT 24
Finished Jun 29 06:33:39 PM PDT 24
Peak memory 206204 kb
Host smart-bd5e6efd-256b-470d-9601-579677be0465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21635
69479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2163569479
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1321920595
Short name T2261
Test name
Test status
Simulation time 221061198 ps
CPU time 0.91 seconds
Started Jun 29 06:33:35 PM PDT 24
Finished Jun 29 06:33:37 PM PDT 24
Peak memory 206212 kb
Host smart-92195b8a-16a0-4518-963f-86449e5a0322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13219
20595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1321920595
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1870135671
Short name T171
Test name
Test status
Simulation time 8164857549 ps
CPU time 50.78 seconds
Started Jun 29 06:33:33 PM PDT 24
Finished Jun 29 06:34:25 PM PDT 24
Peak memory 206384 kb
Host smart-ff4b9077-6505-4ec7-b86b-60887947dfe0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1870135671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1870135671
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2994911290
Short name T188
Test name
Test status
Simulation time 9579054874 ps
CPU time 51.78 seconds
Started Jun 29 06:33:31 PM PDT 24
Finished Jun 29 06:34:24 PM PDT 24
Peak memory 206444 kb
Host smart-1fd30c42-cdad-4fe2-9b71-201f270f36bb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2994911290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2994911290
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.3774227961
Short name T2426
Test name
Test status
Simulation time 14999540515 ps
CPU time 78.45 seconds
Started Jun 29 06:33:33 PM PDT 24
Finished Jun 29 06:34:52 PM PDT 24
Peak memory 206500 kb
Host smart-44ad26f2-3fc6-4438-b594-b5d8e66cbb9f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3774227961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3774227961
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1951203205
Short name T1880
Test name
Test status
Simulation time 158860997 ps
CPU time 0.81 seconds
Started Jun 29 06:33:35 PM PDT 24
Finished Jun 29 06:33:36 PM PDT 24
Peak memory 206180 kb
Host smart-b619db7e-79ed-443a-81ca-364a8b59f613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19512
03205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1951203205
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.2318986587
Short name T2333
Test name
Test status
Simulation time 187609790 ps
CPU time 0.91 seconds
Started Jun 29 06:33:34 PM PDT 24
Finished Jun 29 06:33:36 PM PDT 24
Peak memory 206200 kb
Host smart-b4a01e32-f650-4408-ba78-9e93ef932381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23189
86587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.2318986587
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1303840414
Short name T1194
Test name
Test status
Simulation time 137660777 ps
CPU time 0.77 seconds
Started Jun 29 06:33:31 PM PDT 24
Finished Jun 29 06:33:33 PM PDT 24
Peak memory 206148 kb
Host smart-abd7cf49-5926-4cbf-aa35-8c0d68412b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13038
40414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1303840414
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3923697372
Short name T2601
Test name
Test status
Simulation time 312853412 ps
CPU time 1.02 seconds
Started Jun 29 06:33:33 PM PDT 24
Finished Jun 29 06:33:35 PM PDT 24
Peak memory 206200 kb
Host smart-c8905349-de1b-4918-b972-52074d981652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39236
97372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.3923697372
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.4023035237
Short name T1732
Test name
Test status
Simulation time 157179539 ps
CPU time 0.83 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:33:41 PM PDT 24
Peak memory 206192 kb
Host smart-440c7611-8674-4b20-b46e-d7fff0e20ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40230
35237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.4023035237
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2121794115
Short name T500
Test name
Test status
Simulation time 151799946 ps
CPU time 0.87 seconds
Started Jun 29 06:33:38 PM PDT 24
Finished Jun 29 06:33:40 PM PDT 24
Peak memory 206196 kb
Host smart-8d5ac98e-63dc-4c74-85ce-9863c563de61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21217
94115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2121794115
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3878133174
Short name T516
Test name
Test status
Simulation time 213359660 ps
CPU time 0.9 seconds
Started Jun 29 06:33:44 PM PDT 24
Finished Jun 29 06:33:45 PM PDT 24
Peak memory 206216 kb
Host smart-76cfdffc-cd96-472f-b125-810cc97d3169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38781
33174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3878133174
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.4166054400
Short name T1032
Test name
Test status
Simulation time 3666121724 ps
CPU time 36.86 seconds
Started Jun 29 06:33:38 PM PDT 24
Finished Jun 29 06:34:15 PM PDT 24
Peak memory 206452 kb
Host smart-d9cd17f1-d75b-4ee3-89b6-79e3aa7070d9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4166054400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.4166054400
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3535157036
Short name T1851
Test name
Test status
Simulation time 174334713 ps
CPU time 0.9 seconds
Started Jun 29 06:33:41 PM PDT 24
Finished Jun 29 06:33:43 PM PDT 24
Peak memory 206224 kb
Host smart-b62796b5-9204-4dd6-9292-9c8d66dadef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35351
57036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3535157036
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.662698534
Short name T1730
Test name
Test status
Simulation time 173092804 ps
CPU time 0.83 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:33:49 PM PDT 24
Peak memory 206112 kb
Host smart-5fd7ad97-57ee-47a4-8d4e-f0a5bfeddb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66269
8534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.662698534
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.854694125
Short name T2566
Test name
Test status
Simulation time 4547068066 ps
CPU time 34.26 seconds
Started Jun 29 06:33:37 PM PDT 24
Finished Jun 29 06:34:12 PM PDT 24
Peak memory 206436 kb
Host smart-1d5632e9-7e4c-4625-ac29-26dcf05c0c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85469
4125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.854694125
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.3804256219
Short name T1874
Test name
Test status
Simulation time 75496929 ps
CPU time 0.72 seconds
Started Jun 29 06:33:45 PM PDT 24
Finished Jun 29 06:33:46 PM PDT 24
Peak memory 206208 kb
Host smart-118df08c-5f10-43c5-a93d-090ad393d5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3804256219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.3804256219
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.519360687
Short name T847
Test name
Test status
Simulation time 3850295590 ps
CPU time 4.7 seconds
Started Jun 29 06:33:43 PM PDT 24
Finished Jun 29 06:33:48 PM PDT 24
Peak memory 206252 kb
Host smart-61597df1-c7fe-4c95-a481-8c4560b5b722
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=519360687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.519360687
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2566020343
Short name T1383
Test name
Test status
Simulation time 13433828849 ps
CPU time 15.84 seconds
Started Jun 29 06:33:41 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 206460 kb
Host smart-572c7b29-0ee4-4c4e-8e52-21d7b1002f76
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2566020343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2566020343
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2551991916
Short name T2620
Test name
Test status
Simulation time 23338054819 ps
CPU time 25.86 seconds
Started Jun 29 06:33:41 PM PDT 24
Finished Jun 29 06:34:08 PM PDT 24
Peak memory 206336 kb
Host smart-d1de64c0-9077-4e2f-9dec-c0ea2c1b4c52
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2551991916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.2551991916
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1518169827
Short name T1883
Test name
Test status
Simulation time 190222135 ps
CPU time 0.84 seconds
Started Jun 29 06:33:40 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206216 kb
Host smart-dff93d94-2c03-44e2-bf7f-3ac7d59ed63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15181
69827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1518169827
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1945487938
Short name T71
Test name
Test status
Simulation time 172348907 ps
CPU time 0.8 seconds
Started Jun 29 06:33:42 PM PDT 24
Finished Jun 29 06:33:43 PM PDT 24
Peak memory 206204 kb
Host smart-abebab47-8ff9-467a-ae06-a876f0299db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19454
87938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1945487938
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1185841350
Short name T1822
Test name
Test status
Simulation time 460115963 ps
CPU time 1.48 seconds
Started Jun 29 06:33:40 PM PDT 24
Finished Jun 29 06:33:43 PM PDT 24
Peak memory 206196 kb
Host smart-6c95d104-cb9c-4d53-bd28-43260e02e4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11858
41350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1185841350
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1430017513
Short name T802
Test name
Test status
Simulation time 463178261 ps
CPU time 1.34 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206196 kb
Host smart-1a529db9-dd7d-44ee-95be-e9eddb030189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14300
17513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1430017513
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2996229396
Short name T2236
Test name
Test status
Simulation time 21354985098 ps
CPU time 42.32 seconds
Started Jun 29 06:33:37 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 206416 kb
Host smart-b3500ae5-fd22-466c-9ae4-10606789bef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29962
29396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2996229396
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.875120668
Short name T380
Test name
Test status
Simulation time 302171591 ps
CPU time 1.02 seconds
Started Jun 29 06:33:40 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206200 kb
Host smart-e604f046-6421-41fa-b7fa-28727b50cec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87512
0668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.875120668
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.883254494
Short name T972
Test name
Test status
Simulation time 155839909 ps
CPU time 0.78 seconds
Started Jun 29 06:33:44 PM PDT 24
Finished Jun 29 06:33:46 PM PDT 24
Peak memory 206200 kb
Host smart-988b56d0-3cfd-4449-acd4-61a70b0d1f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88325
4494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.883254494
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.4234671409
Short name T18
Test name
Test status
Simulation time 35603034 ps
CPU time 0.66 seconds
Started Jun 29 06:33:41 PM PDT 24
Finished Jun 29 06:33:43 PM PDT 24
Peak memory 206204 kb
Host smart-a64ffb83-1118-4048-935c-4f581d891046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42346
71409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.4234671409
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.433630559
Short name T1402
Test name
Test status
Simulation time 887696864 ps
CPU time 2.27 seconds
Started Jun 29 06:33:40 PM PDT 24
Finished Jun 29 06:33:43 PM PDT 24
Peak memory 206296 kb
Host smart-4aaef1ce-42a3-4f98-b664-b30ea3de1e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43363
0559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.433630559
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.117681788
Short name T2473
Test name
Test status
Simulation time 258863273 ps
CPU time 1.88 seconds
Started Jun 29 06:33:42 PM PDT 24
Finished Jun 29 06:33:45 PM PDT 24
Peak memory 206276 kb
Host smart-7a9466b0-5afb-49a5-a5be-97fbbdec8651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11768
1788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.117681788
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1784622208
Short name T1859
Test name
Test status
Simulation time 205017750 ps
CPU time 0.89 seconds
Started Jun 29 06:33:40 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206208 kb
Host smart-6b6c1911-d45c-4d12-8b24-a3e0e40e315a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17846
22208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1784622208
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1246716739
Short name T2394
Test name
Test status
Simulation time 146804173 ps
CPU time 0.92 seconds
Started Jun 29 06:33:40 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206172 kb
Host smart-6107389b-676e-461d-a619-c945b59dbe2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
16739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1246716739
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1652070722
Short name T2109
Test name
Test status
Simulation time 242501529 ps
CPU time 0.92 seconds
Started Jun 29 06:33:42 PM PDT 24
Finished Jun 29 06:33:44 PM PDT 24
Peak memory 206212 kb
Host smart-ee90223f-f856-4f56-ac3b-2c9befc9a6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16520
70722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1652070722
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.317635916
Short name T748
Test name
Test status
Simulation time 162722164 ps
CPU time 0.82 seconds
Started Jun 29 06:33:40 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206180 kb
Host smart-f4157302-3836-4ced-8681-6e38e9147540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31763
5916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.317635916
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.1056361747
Short name T2219
Test name
Test status
Simulation time 23321609523 ps
CPU time 24.35 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:34:12 PM PDT 24
Peak memory 206324 kb
Host smart-dd8ad9e3-74f6-4922-81c7-63dde936fdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10563
61747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.1056361747
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3156957686
Short name T1268
Test name
Test status
Simulation time 3304301707 ps
CPU time 3.91 seconds
Started Jun 29 06:33:38 PM PDT 24
Finished Jun 29 06:33:43 PM PDT 24
Peak memory 206264 kb
Host smart-e9a70783-afc3-4608-8ce1-4f4f5b2342c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31569
57686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3156957686
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.4238062827
Short name T2176
Test name
Test status
Simulation time 5723740402 ps
CPU time 55.56 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:34:35 PM PDT 24
Peak memory 206404 kb
Host smart-7e131784-d7d2-4e14-baa3-4f238118b589
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4238062827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.4238062827
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.315130185
Short name T1925
Test name
Test status
Simulation time 286301408 ps
CPU time 0.98 seconds
Started Jun 29 06:33:38 PM PDT 24
Finished Jun 29 06:33:40 PM PDT 24
Peak memory 206200 kb
Host smart-860f96c7-b97d-4ca5-9b81-87b6def92352
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=315130185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.315130185
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.517267124
Short name T1939
Test name
Test status
Simulation time 194756898 ps
CPU time 0.87 seconds
Started Jun 29 06:33:40 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206212 kb
Host smart-7ebb7cc0-0128-4c2e-a56c-9dbe942b3b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51726
7124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.517267124
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3163530708
Short name T2318
Test name
Test status
Simulation time 4089812253 ps
CPU time 113.33 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:35:41 PM PDT 24
Peak memory 206400 kb
Host smart-82a223fd-efcc-45b0-b19f-f933169f2260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31635
30708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3163530708
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.628409528
Short name T1790
Test name
Test status
Simulation time 7001780594 ps
CPU time 194.33 seconds
Started Jun 29 06:33:44 PM PDT 24
Finished Jun 29 06:36:59 PM PDT 24
Peak memory 206464 kb
Host smart-6a152888-14a1-478e-ba2e-3902627f70d6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=628409528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.628409528
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1270084183
Short name T2555
Test name
Test status
Simulation time 151317353 ps
CPU time 0.81 seconds
Started Jun 29 06:33:38 PM PDT 24
Finished Jun 29 06:33:39 PM PDT 24
Peak memory 206220 kb
Host smart-ff521f72-253a-48de-b305-adc7aa63b9c3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1270084183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1270084183
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2884432442
Short name T2385
Test name
Test status
Simulation time 138242100 ps
CPU time 0.75 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:33:40 PM PDT 24
Peak memory 206216 kb
Host smart-2a79e3f2-cd03-4ab3-bbe2-d2700b0d45b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28844
32442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2884432442
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1113623799
Short name T1541
Test name
Test status
Simulation time 191209373 ps
CPU time 0.85 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:33:41 PM PDT 24
Peak memory 206192 kb
Host smart-76dedefc-27a4-46c3-85b1-ebdf8ca9af57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11136
23799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1113623799
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.4093916529
Short name T1760
Test name
Test status
Simulation time 171009155 ps
CPU time 0.78 seconds
Started Jun 29 06:33:39 PM PDT 24
Finished Jun 29 06:33:41 PM PDT 24
Peak memory 206228 kb
Host smart-397b89e7-d5cd-456d-882a-c0f0a6684c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40939
16529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.4093916529
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2817536048
Short name T2201
Test name
Test status
Simulation time 195366718 ps
CPU time 0.82 seconds
Started Jun 29 06:33:40 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 206020 kb
Host smart-63542bd5-9fb7-402c-b2ee-77e667d0ad5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28175
36048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2817536048
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2516050099
Short name T934
Test name
Test status
Simulation time 166036502 ps
CPU time 0.84 seconds
Started Jun 29 06:33:45 PM PDT 24
Finished Jun 29 06:33:46 PM PDT 24
Peak memory 206220 kb
Host smart-57a64472-485f-4332-a759-42488ff1aaea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25160
50099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2516050099
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3090588551
Short name T2022
Test name
Test status
Simulation time 211342432 ps
CPU time 0.92 seconds
Started Jun 29 06:33:50 PM PDT 24
Finished Jun 29 06:33:52 PM PDT 24
Peak memory 206224 kb
Host smart-4a39b981-47ec-449c-a39c-ee2eecee4280
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3090588551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3090588551
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.2687556128
Short name T426
Test name
Test status
Simulation time 215730814 ps
CPU time 0.96 seconds
Started Jun 29 06:33:48 PM PDT 24
Finished Jun 29 06:33:50 PM PDT 24
Peak memory 206116 kb
Host smart-317e1af2-54d1-41a4-98e7-515514169de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26875
56128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.2687556128
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3569593088
Short name T2351
Test name
Test status
Simulation time 142903232 ps
CPU time 0.75 seconds
Started Jun 29 06:33:45 PM PDT 24
Finished Jun 29 06:33:47 PM PDT 24
Peak memory 206212 kb
Host smart-55e36cba-6e78-4ac0-be29-dd7579cf9ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35695
93088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3569593088
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3498261265
Short name T1012
Test name
Test status
Simulation time 64132467 ps
CPU time 0.69 seconds
Started Jun 29 06:33:46 PM PDT 24
Finished Jun 29 06:33:47 PM PDT 24
Peak memory 206208 kb
Host smart-7a9b9285-9e8a-49c5-94b2-094ef160b243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34982
61265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3498261265
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1912439040
Short name T1702
Test name
Test status
Simulation time 17717262502 ps
CPU time 44.46 seconds
Started Jun 29 06:33:46 PM PDT 24
Finished Jun 29 06:34:31 PM PDT 24
Peak memory 206428 kb
Host smart-aa03eaf9-ad35-4e60-bd0b-83abfe695601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19124
39040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1912439040
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1089002247
Short name T1712
Test name
Test status
Simulation time 192204308 ps
CPU time 0.91 seconds
Started Jun 29 06:33:48 PM PDT 24
Finished Jun 29 06:33:50 PM PDT 24
Peak memory 206196 kb
Host smart-bf71f907-2ce4-42d6-bdb2-acde61c4da7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10890
02247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1089002247
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3294247390
Short name T2058
Test name
Test status
Simulation time 275495669 ps
CPU time 0.98 seconds
Started Jun 29 06:33:54 PM PDT 24
Finished Jun 29 06:33:56 PM PDT 24
Peak memory 206356 kb
Host smart-546b72e8-0eb1-4abb-b3e2-9c0b9408083b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32942
47390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3294247390
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.860116443
Short name T2080
Test name
Test status
Simulation time 9675712058 ps
CPU time 46.21 seconds
Started Jun 29 06:33:49 PM PDT 24
Finished Jun 29 06:34:36 PM PDT 24
Peak memory 206416 kb
Host smart-8ca07eb0-4ded-4e92-a11c-f0d596b724ff
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=860116443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.860116443
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.351324567
Short name T1783
Test name
Test status
Simulation time 7958450918 ps
CPU time 31.86 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 206432 kb
Host smart-4b6c6122-2155-4eb3-a6d3-b8d48c778218
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=351324567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.351324567
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3703202362
Short name T2430
Test name
Test status
Simulation time 157941041 ps
CPU time 0.77 seconds
Started Jun 29 06:33:49 PM PDT 24
Finished Jun 29 06:33:51 PM PDT 24
Peak memory 206208 kb
Host smart-510d82ae-a9a6-4f7b-91a2-b160a6f1728d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37032
02362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3703202362
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.498403715
Short name T2240
Test name
Test status
Simulation time 181075704 ps
CPU time 0.82 seconds
Started Jun 29 06:33:46 PM PDT 24
Finished Jun 29 06:33:48 PM PDT 24
Peak memory 206172 kb
Host smart-ac7adc62-9bdf-41ab-8c8e-ca2e18f8d087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49840
3715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.498403715
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.4080695360
Short name T2442
Test name
Test status
Simulation time 144233840 ps
CPU time 0.75 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:33:57 PM PDT 24
Peak memory 206188 kb
Host smart-739361a5-2340-45eb-bb67-eb14cbd033df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40806
95360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.4080695360
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.1136149655
Short name T2282
Test name
Test status
Simulation time 228361503 ps
CPU time 0.94 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:33:49 PM PDT 24
Peak memory 206200 kb
Host smart-44183367-246f-47d9-b814-fbed125ece66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361
49655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.1136149655
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.439166471
Short name T225
Test name
Test status
Simulation time 252937876 ps
CPU time 1.05 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 224072 kb
Host smart-76e989ac-898f-4154-a78e-9b77f7795359
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=439166471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.439166471
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.66553726
Short name T2552
Test name
Test status
Simulation time 355654244 ps
CPU time 1.27 seconds
Started Jun 29 06:33:48 PM PDT 24
Finished Jun 29 06:33:50 PM PDT 24
Peak memory 206196 kb
Host smart-e67a56b7-fad3-45cd-a559-a1e9e320159a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66553
726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.66553726
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.1210094900
Short name T506
Test name
Test status
Simulation time 173739878 ps
CPU time 0.86 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:33:49 PM PDT 24
Peak memory 206184 kb
Host smart-5e1205b6-d532-4a9e-ab0f-3a9249561dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12100
94900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.1210094900
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2385678682
Short name T867
Test name
Test status
Simulation time 153375806 ps
CPU time 0.78 seconds
Started Jun 29 06:33:48 PM PDT 24
Finished Jun 29 06:33:50 PM PDT 24
Peak memory 206196 kb
Host smart-b60ae86b-fef6-419c-b01d-4b255345a86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23856
78682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2385678682
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.867870668
Short name T2549
Test name
Test status
Simulation time 164755006 ps
CPU time 0.79 seconds
Started Jun 29 06:33:46 PM PDT 24
Finished Jun 29 06:33:48 PM PDT 24
Peak memory 206188 kb
Host smart-8736c599-445d-47e2-ba2d-956f9e7a07a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86787
0668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.867870668
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.943655770
Short name T2603
Test name
Test status
Simulation time 214334879 ps
CPU time 1.01 seconds
Started Jun 29 06:33:53 PM PDT 24
Finished Jun 29 06:33:54 PM PDT 24
Peak memory 206188 kb
Host smart-3b723f61-34ed-48c3-a408-8fb73cffc5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94365
5770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.943655770
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.1789585362
Short name T1854
Test name
Test status
Simulation time 4470162149 ps
CPU time 32.29 seconds
Started Jun 29 06:33:48 PM PDT 24
Finished Jun 29 06:34:21 PM PDT 24
Peak memory 206396 kb
Host smart-85a8fc29-34c5-4339-8bd2-60863bc4b66f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1789585362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.1789585362
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.3741140445
Short name T1158
Test name
Test status
Simulation time 161297113 ps
CPU time 0.78 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 206372 kb
Host smart-1df63e1c-99c4-470a-af4f-9685b7c941a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37411
40445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.3741140445
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1850837932
Short name T2217
Test name
Test status
Simulation time 166312767 ps
CPU time 0.8 seconds
Started Jun 29 06:33:49 PM PDT 24
Finished Jun 29 06:33:51 PM PDT 24
Peak memory 206204 kb
Host smart-f51e7ef1-6e32-41c6-92db-a481089473c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18508
37932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1850837932
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3494324652
Short name T1891
Test name
Test status
Simulation time 5224275176 ps
CPU time 51.93 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 206344 kb
Host smart-d4c245b7-e551-456e-8e22-36e3c434c383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34943
24652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3494324652
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.294878759
Short name T248
Test name
Test status
Simulation time 22897864500 ps
CPU time 534.06 seconds
Started Jun 29 06:33:46 PM PDT 24
Finished Jun 29 06:42:40 PM PDT 24
Peak memory 206476 kb
Host smart-c4d2568e-019f-4098-8b36-57038b137ceb
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=294878759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.294878759
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.642373500
Short name T572
Test name
Test status
Simulation time 72013300 ps
CPU time 0.72 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:18 PM PDT 24
Peak memory 206208 kb
Host smart-a8a7ffc9-700e-47cd-8e18-84d36c8b2b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=642373500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.642373500
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.4012124870
Short name T796
Test name
Test status
Simulation time 3661818020 ps
CPU time 4.42 seconds
Started Jun 29 06:35:14 PM PDT 24
Finished Jun 29 06:35:20 PM PDT 24
Peak memory 206280 kb
Host smart-f590f22b-af13-424a-9ef4-e33df1561213
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4012124870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.4012124870
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2603702466
Short name T2193
Test name
Test status
Simulation time 13421867619 ps
CPU time 13.37 seconds
Started Jun 29 06:35:14 PM PDT 24
Finished Jun 29 06:35:28 PM PDT 24
Peak memory 206340 kb
Host smart-27637323-cdb6-4e21-9c7e-f003626eef58
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2603702466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2603702466
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3738917389
Short name T1654
Test name
Test status
Simulation time 23343189155 ps
CPU time 26.33 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:48 PM PDT 24
Peak memory 206328 kb
Host smart-e199280e-675e-4b1d-bb87-641d69a1495d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3738917389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.3738917389
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1073157270
Short name T1406
Test name
Test status
Simulation time 201333724 ps
CPU time 0.88 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206172 kb
Host smart-c613b206-9710-493c-bf98-5c177ad8971b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10731
57270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1073157270
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.744068310
Short name T1660
Test name
Test status
Simulation time 163726761 ps
CPU time 0.84 seconds
Started Jun 29 06:35:10 PM PDT 24
Finished Jun 29 06:35:12 PM PDT 24
Peak memory 206212 kb
Host smart-f5c084c5-4165-44a8-8def-3759e143bf1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74406
8310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.744068310
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3104283664
Short name T108
Test name
Test status
Simulation time 191289768 ps
CPU time 0.9 seconds
Started Jun 29 06:35:10 PM PDT 24
Finished Jun 29 06:35:11 PM PDT 24
Peak memory 206144 kb
Host smart-4f4550e0-5258-4283-a60c-0bae5981a0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31042
83664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3104283664
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3345007045
Short name T1210
Test name
Test status
Simulation time 900398550 ps
CPU time 2.18 seconds
Started Jun 29 06:35:13 PM PDT 24
Finished Jun 29 06:35:16 PM PDT 24
Peak memory 206312 kb
Host smart-3aeeeb06-f19f-4579-8aa3-b0652e50f0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33450
07045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3345007045
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3278333221
Short name T2028
Test name
Test status
Simulation time 8207160143 ps
CPU time 16.83 seconds
Started Jun 29 06:35:16 PM PDT 24
Finished Jun 29 06:35:34 PM PDT 24
Peak memory 206504 kb
Host smart-70f071d4-95c4-4bbc-9564-d64871f96477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32783
33221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3278333221
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.906988527
Short name T1092
Test name
Test status
Simulation time 442782224 ps
CPU time 1.4 seconds
Started Jun 29 06:35:15 PM PDT 24
Finished Jun 29 06:35:17 PM PDT 24
Peak memory 206212 kb
Host smart-f768b8f5-aa3a-48cd-aa28-bb0c3607e2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90698
8527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.906988527
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.955502237
Short name T1787
Test name
Test status
Simulation time 169559491 ps
CPU time 0.8 seconds
Started Jun 29 06:35:11 PM PDT 24
Finished Jun 29 06:35:12 PM PDT 24
Peak memory 206148 kb
Host smart-ab44fd6e-fbef-4bc6-9eea-28592fce1394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95550
2237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.955502237
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1764417752
Short name T2089
Test name
Test status
Simulation time 33111411 ps
CPU time 0.7 seconds
Started Jun 29 06:35:16 PM PDT 24
Finished Jun 29 06:35:18 PM PDT 24
Peak memory 206196 kb
Host smart-1163bd20-885a-4aae-a087-d4e4309a2de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17644
17752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1764417752
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.1420330779
Short name T2525
Test name
Test status
Simulation time 953297869 ps
CPU time 2.4 seconds
Started Jun 29 06:35:09 PM PDT 24
Finished Jun 29 06:35:12 PM PDT 24
Peak memory 206300 kb
Host smart-e9eea43b-ef5c-4a59-bec0-0c0da96e5451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14203
30779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.1420330779
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1939406771
Short name T2370
Test name
Test status
Simulation time 344592050 ps
CPU time 1.97 seconds
Started Jun 29 06:35:10 PM PDT 24
Finished Jun 29 06:35:13 PM PDT 24
Peak memory 206264 kb
Host smart-3e03091e-68b7-493a-a78a-f76273c71d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19394
06771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1939406771
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1738311580
Short name T459
Test name
Test status
Simulation time 167366208 ps
CPU time 0.81 seconds
Started Jun 29 06:35:15 PM PDT 24
Finished Jun 29 06:35:17 PM PDT 24
Peak memory 206204 kb
Host smart-bfda8470-e536-4e48-9f12-ff14b48e890f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17383
11580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1738311580
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2762052550
Short name T1744
Test name
Test status
Simulation time 155595293 ps
CPU time 0.77 seconds
Started Jun 29 06:35:11 PM PDT 24
Finished Jun 29 06:35:12 PM PDT 24
Peak memory 206156 kb
Host smart-7f4a0a23-44ae-4e83-bd95-8935df569814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27620
52550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2762052550
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.4229895779
Short name T2221
Test name
Test status
Simulation time 245747085 ps
CPU time 0.93 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:20 PM PDT 24
Peak memory 206216 kb
Host smart-6353814a-0d99-46a3-ada0-684059bd0f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42298
95779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.4229895779
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3074625202
Short name T839
Test name
Test status
Simulation time 190029315 ps
CPU time 0.88 seconds
Started Jun 29 06:35:08 PM PDT 24
Finished Jun 29 06:35:09 PM PDT 24
Peak memory 206196 kb
Host smart-699bd748-fcb9-4830-9325-15d411555e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30746
25202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3074625202
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2183441878
Short name T682
Test name
Test status
Simulation time 23341997833 ps
CPU time 23.27 seconds
Started Jun 29 06:35:12 PM PDT 24
Finished Jun 29 06:35:36 PM PDT 24
Peak memory 206312 kb
Host smart-c1ca2ab5-c6c4-495b-86b4-b9122f0bcfe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21834
41878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2183441878
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.2896302645
Short name T2595
Test name
Test status
Simulation time 3351607220 ps
CPU time 4.01 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206256 kb
Host smart-811e4f31-eac6-404a-adc4-c4a631097445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28963
02645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.2896302645
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2049720180
Short name T2272
Test name
Test status
Simulation time 11073037766 ps
CPU time 313.51 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:40:33 PM PDT 24
Peak memory 206504 kb
Host smart-3cc8ec64-7f28-4fdf-93a6-df5e5d833d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20497
20180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2049720180
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.1075379770
Short name T2189
Test name
Test status
Simulation time 3394986525 ps
CPU time 94.82 seconds
Started Jun 29 06:35:07 PM PDT 24
Finished Jun 29 06:36:42 PM PDT 24
Peak memory 206460 kb
Host smart-a27cb72a-9161-4d01-be32-b7fffa38eab1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1075379770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.1075379770
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.319172112
Short name T402
Test name
Test status
Simulation time 234675304 ps
CPU time 0.97 seconds
Started Jun 29 06:35:10 PM PDT 24
Finished Jun 29 06:35:11 PM PDT 24
Peak memory 206220 kb
Host smart-ccdf3a8c-d548-48cb-8541-42ddb2821601
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=319172112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.319172112
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2683315637
Short name T2403
Test name
Test status
Simulation time 186050919 ps
CPU time 0.85 seconds
Started Jun 29 06:35:13 PM PDT 24
Finished Jun 29 06:35:14 PM PDT 24
Peak memory 206216 kb
Host smart-0597ccb6-808d-4c61-a140-f083329063e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26833
15637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2683315637
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1673408529
Short name T2486
Test name
Test status
Simulation time 6518345957 ps
CPU time 64.89 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:36:25 PM PDT 24
Peak memory 206484 kb
Host smart-ad974e78-82b3-4961-8cc4-0741345e0bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
08529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1673408529
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.3399591164
Short name T364
Test name
Test status
Simulation time 4504069902 ps
CPU time 122.68 seconds
Started Jun 29 06:35:10 PM PDT 24
Finished Jun 29 06:37:13 PM PDT 24
Peak memory 206404 kb
Host smart-53b50b6a-1d56-49f2-a467-68677e983635
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3399591164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3399591164
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1504572198
Short name T2194
Test name
Test status
Simulation time 211801375 ps
CPU time 0.93 seconds
Started Jun 29 06:35:08 PM PDT 24
Finished Jun 29 06:35:09 PM PDT 24
Peak memory 206220 kb
Host smart-68429c90-839a-4125-9fcf-450dab91af79
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1504572198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1504572198
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2619132958
Short name T766
Test name
Test status
Simulation time 173342162 ps
CPU time 0.81 seconds
Started Jun 29 06:35:08 PM PDT 24
Finished Jun 29 06:35:09 PM PDT 24
Peak memory 206216 kb
Host smart-cd3e24cb-a0fb-4659-93cc-f751ce127ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26191
32958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2619132958
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1283039326
Short name T1881
Test name
Test status
Simulation time 186616890 ps
CPU time 0.87 seconds
Started Jun 29 06:35:15 PM PDT 24
Finished Jun 29 06:35:17 PM PDT 24
Peak memory 206204 kb
Host smart-6daef7d4-ef80-4212-88ec-277a26620a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12830
39326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1283039326
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4222864619
Short name T643
Test name
Test status
Simulation time 158401143 ps
CPU time 0.83 seconds
Started Jun 29 06:35:11 PM PDT 24
Finished Jun 29 06:35:12 PM PDT 24
Peak memory 206136 kb
Host smart-eaf1ee98-c1b0-4577-8dc1-38db462d8db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42228
64619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4222864619
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.353109665
Short name T1567
Test name
Test status
Simulation time 177883015 ps
CPU time 0.91 seconds
Started Jun 29 06:35:08 PM PDT 24
Finished Jun 29 06:35:09 PM PDT 24
Peak memory 206196 kb
Host smart-75d348cc-247c-41e1-b6e6-167ed03d0e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35310
9665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.353109665
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2914162891
Short name T1565
Test name
Test status
Simulation time 171272370 ps
CPU time 0.82 seconds
Started Jun 29 06:35:14 PM PDT 24
Finished Jun 29 06:35:15 PM PDT 24
Peak memory 206220 kb
Host smart-e8a0f12f-b769-4321-9ac3-3d48399f9a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29141
62891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2914162891
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.222118609
Short name T2036
Test name
Test status
Simulation time 227364236 ps
CPU time 0.95 seconds
Started Jun 29 06:35:14 PM PDT 24
Finished Jun 29 06:35:16 PM PDT 24
Peak memory 206136 kb
Host smart-f5b29641-d687-494f-aa26-e83cc3ef7113
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=222118609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.222118609
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1633870434
Short name T1223
Test name
Test status
Simulation time 148748623 ps
CPU time 0.76 seconds
Started Jun 29 06:35:07 PM PDT 24
Finished Jun 29 06:35:09 PM PDT 24
Peak memory 206212 kb
Host smart-48d0c798-cc1e-4625-b15c-9a1c4cb8f700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16338
70434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1633870434
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3241559617
Short name T894
Test name
Test status
Simulation time 52033462 ps
CPU time 0.71 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 205624 kb
Host smart-5d7712e1-d312-4923-b3e6-d80a4e23344e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32415
59617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3241559617
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1336077596
Short name T1434
Test name
Test status
Simulation time 160506214 ps
CPU time 0.82 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:35:20 PM PDT 24
Peak memory 206160 kb
Host smart-f2758c8f-c2b6-4ccf-8bfb-4104450ab764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13360
77596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1336077596
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.566735748
Short name T1485
Test name
Test status
Simulation time 232836726 ps
CPU time 0.95 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:18 PM PDT 24
Peak memory 206208 kb
Host smart-8bae0e4c-70e1-4d32-9373-cf31ead3c9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56673
5748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.566735748
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2642619717
Short name T447
Test name
Test status
Simulation time 228088255 ps
CPU time 0.94 seconds
Started Jun 29 06:35:14 PM PDT 24
Finished Jun 29 06:35:16 PM PDT 24
Peak memory 206388 kb
Host smart-21aacf02-dfb0-46c5-8743-9ff85634068d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26426
19717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2642619717
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.310579082
Short name T2617
Test name
Test status
Simulation time 182477910 ps
CPU time 0.87 seconds
Started Jun 29 06:35:11 PM PDT 24
Finished Jun 29 06:35:13 PM PDT 24
Peak memory 206204 kb
Host smart-a73708eb-26ce-4c46-98d8-9611260ab76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31057
9082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.310579082
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1149252419
Short name T2241
Test name
Test status
Simulation time 139382667 ps
CPU time 0.74 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206196 kb
Host smart-dfeabbb3-63ce-4970-acec-4f59cd4bfa7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11492
52419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1149252419
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3487473743
Short name T1632
Test name
Test status
Simulation time 173266093 ps
CPU time 0.82 seconds
Started Jun 29 06:35:24 PM PDT 24
Finished Jun 29 06:35:26 PM PDT 24
Peak memory 206196 kb
Host smart-ee565b26-a1dc-47e7-9480-f1bae9902616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34874
73743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3487473743
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2066646018
Short name T2118
Test name
Test status
Simulation time 161364318 ps
CPU time 0.84 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 205700 kb
Host smart-fe8d71dd-ba97-46b8-8bcd-fd585b0b6902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20666
46018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2066646018
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2122223372
Short name T1825
Test name
Test status
Simulation time 226273174 ps
CPU time 1 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:20 PM PDT 24
Peak memory 206216 kb
Host smart-456d6256-5fed-4dcb-b8c0-fed3f82ca838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21222
23372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2122223372
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.3750590712
Short name T1684
Test name
Test status
Simulation time 5660274861 ps
CPU time 40.59 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206404 kb
Host smart-9af3f59f-8035-4194-800c-3f6e88aca340
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3750590712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.3750590712
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2531359910
Short name T453
Test name
Test status
Simulation time 149065400 ps
CPU time 0.8 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:25 PM PDT 24
Peak memory 206220 kb
Host smart-0e91fe03-520d-444c-b2b7-ca3ed31a9610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25313
59910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2531359910
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.964753276
Short name T1714
Test name
Test status
Simulation time 170105946 ps
CPU time 0.84 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206196 kb
Host smart-ee6c2451-c062-440e-b8f6-379c231eafc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96475
3276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.964753276
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.4086046997
Short name T1333
Test name
Test status
Simulation time 4291113508 ps
CPU time 42.84 seconds
Started Jun 29 06:35:22 PM PDT 24
Finished Jun 29 06:36:07 PM PDT 24
Peak memory 206480 kb
Host smart-6730f006-b249-475a-a731-2790503247ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40860
46997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.4086046997
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3922320124
Short name T1077
Test name
Test status
Simulation time 38647757 ps
CPU time 0.7 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206192 kb
Host smart-0477f47b-3ff5-488e-b1b5-725301643d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3922320124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3922320124
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.2379089494
Short name T1001
Test name
Test status
Simulation time 3840988623 ps
CPU time 5.5 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:27 PM PDT 24
Peak memory 206280 kb
Host smart-94c590b1-8d57-42fc-b2d1-fe43d2addced
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2379089494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.2379089494
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1431666948
Short name T1175
Test name
Test status
Simulation time 13447251497 ps
CPU time 13.76 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:32 PM PDT 24
Peak memory 206340 kb
Host smart-656dddae-f351-4e30-9c5e-cbdbcf8c4d46
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1431666948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1431666948
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1442927178
Short name T1782
Test name
Test status
Simulation time 23325462584 ps
CPU time 23.98 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:48 PM PDT 24
Peak memory 206324 kb
Host smart-cef82c03-fde6-4558-97e4-e5a40866f7e4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1442927178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1442927178
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2005335807
Short name T445
Test name
Test status
Simulation time 186657823 ps
CPU time 0.87 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206172 kb
Host smart-42b1e690-d318-4d34-8bbc-7557a779be06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20053
35807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2005335807
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1075474484
Short name T575
Test name
Test status
Simulation time 194341999 ps
CPU time 0.92 seconds
Started Jun 29 06:35:15 PM PDT 24
Finished Jun 29 06:35:16 PM PDT 24
Peak memory 206196 kb
Host smart-1e35cbfc-8f2c-4bd9-b576-2bdff75557bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10754
74484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1075474484
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.710225713
Short name T2607
Test name
Test status
Simulation time 316568928 ps
CPU time 1.07 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:25 PM PDT 24
Peak memory 206200 kb
Host smart-07f714ee-c350-4c87-92f0-9aaca677842c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71022
5713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.710225713
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.334056857
Short name T1227
Test name
Test status
Simulation time 609771140 ps
CPU time 1.6 seconds
Started Jun 29 06:35:16 PM PDT 24
Finished Jun 29 06:35:19 PM PDT 24
Peak memory 206192 kb
Host smart-9e9f0ea5-4450-43e9-8e60-0025b3c08d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33405
6857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.334056857
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1261950403
Short name T2364
Test name
Test status
Simulation time 21298931681 ps
CPU time 39.96 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:36:01 PM PDT 24
Peak memory 206468 kb
Host smart-6e516505-ec84-4ebc-8576-48c0aaccdcca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12619
50403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1261950403
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.3822747059
Short name T2065
Test name
Test status
Simulation time 331514062 ps
CPU time 1.24 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:20 PM PDT 24
Peak memory 206196 kb
Host smart-dc784cac-53ab-4858-8969-835587973912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227
47059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.3822747059
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_enable.1865559238
Short name T2276
Test name
Test status
Simulation time 40283416 ps
CPU time 0.66 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206384 kb
Host smart-73e5b898-453c-412d-8cc4-0ca01715db76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18655
59238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1865559238
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3829796739
Short name T2336
Test name
Test status
Simulation time 846394075 ps
CPU time 2.28 seconds
Started Jun 29 06:35:13 PM PDT 24
Finished Jun 29 06:35:16 PM PDT 24
Peak memory 206336 kb
Host smart-051178c6-c4fa-4fa4-876f-865caec87e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38297
96739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3829796739
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2250018046
Short name T1445
Test name
Test status
Simulation time 265849547 ps
CPU time 0.97 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206176 kb
Host smart-69383f9b-2be5-4d01-9bab-a7d0a5e49ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22500
18046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2250018046
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3351818736
Short name T1171
Test name
Test status
Simulation time 134741764 ps
CPU time 0.76 seconds
Started Jun 29 06:35:12 PM PDT 24
Finished Jun 29 06:35:13 PM PDT 24
Peak memory 206216 kb
Host smart-f45fc426-0815-4dcc-b673-438db3ddecf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33518
18736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3351818736
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2019071197
Short name T1661
Test name
Test status
Simulation time 205990780 ps
CPU time 0.9 seconds
Started Jun 29 06:35:29 PM PDT 24
Finished Jun 29 06:35:30 PM PDT 24
Peak memory 206216 kb
Host smart-971e1eeb-d8fb-4065-978c-3b288d8b9326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20190
71197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2019071197
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.3008930229
Short name T864
Test name
Test status
Simulation time 7120431081 ps
CPU time 50.37 seconds
Started Jun 29 06:35:14 PM PDT 24
Finished Jun 29 06:36:05 PM PDT 24
Peak memory 206416 kb
Host smart-18c1a103-ac77-4e6f-b93b-03a2ceb4c3fa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3008930229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.3008930229
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.4143894659
Short name T551
Test name
Test status
Simulation time 217468757 ps
CPU time 0.88 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:18 PM PDT 24
Peak memory 206192 kb
Host smart-a90e8f29-59d1-4db1-8a2d-3c835ce0cb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41438
94659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.4143894659
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.20371695
Short name T1980
Test name
Test status
Simulation time 23325681137 ps
CPU time 22.9 seconds
Started Jun 29 06:35:19 PM PDT 24
Finished Jun 29 06:35:43 PM PDT 24
Peak memory 206340 kb
Host smart-20e73c75-389d-43e5-97f6-b57e11e7f094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20371
695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.20371695
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.13325386
Short name T1454
Test name
Test status
Simulation time 3293904023 ps
CPU time 4.16 seconds
Started Jun 29 06:35:14 PM PDT 24
Finished Jun 29 06:35:19 PM PDT 24
Peak memory 206260 kb
Host smart-115143ed-519a-4fbb-8430-dd1b5b6579d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13325
386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.13325386
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2443068754
Short name T640
Test name
Test status
Simulation time 11041579783 ps
CPU time 307.82 seconds
Started Jun 29 06:35:22 PM PDT 24
Finished Jun 29 06:40:31 PM PDT 24
Peak memory 206448 kb
Host smart-edb37c0e-334f-490e-a11c-db90c3586a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24430
68754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2443068754
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.2453289692
Short name T1328
Test name
Test status
Simulation time 4644735618 ps
CPU time 34.82 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:35:54 PM PDT 24
Peak memory 206432 kb
Host smart-8701d202-6486-40dc-a319-5d4365db3b04
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2453289692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.2453289692
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.3542083701
Short name T473
Test name
Test status
Simulation time 255674283 ps
CPU time 0.9 seconds
Started Jun 29 06:35:15 PM PDT 24
Finished Jun 29 06:35:17 PM PDT 24
Peak memory 206220 kb
Host smart-3013c48f-e05f-4038-aad3-17cfac55486a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3542083701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.3542083701
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.513179081
Short name T1022
Test name
Test status
Simulation time 215761365 ps
CPU time 0.9 seconds
Started Jun 29 06:35:19 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206216 kb
Host smart-f6d3a849-f739-48e9-8ef1-b990d54bd547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51317
9081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.513179081
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.44958660
Short name T514
Test name
Test status
Simulation time 4918844546 ps
CPU time 46.34 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:36:07 PM PDT 24
Peak memory 206404 kb
Host smart-55841b61-0a70-4830-99a7-24d7c6ba69e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44958
660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.44958660
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.1210120086
Short name T657
Test name
Test status
Simulation time 7245676888 ps
CPU time 70.79 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:36:35 PM PDT 24
Peak memory 206500 kb
Host smart-00a1d9e2-f0aa-435d-a3ed-2a7f8c30b4e1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1210120086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.1210120086
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3071062046
Short name T1788
Test name
Test status
Simulation time 148748045 ps
CPU time 0.76 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:20 PM PDT 24
Peak memory 206184 kb
Host smart-ea6be44b-f31b-47fc-b831-d56deda8e927
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3071062046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3071062046
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1874613862
Short name T550
Test name
Test status
Simulation time 147971475 ps
CPU time 0.84 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:19 PM PDT 24
Peak memory 206164 kb
Host smart-db06cd1b-2210-4ca9-950b-3fb680f70e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18746
13862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1874613862
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2574832141
Short name T2061
Test name
Test status
Simulation time 158066553 ps
CPU time 0.78 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206200 kb
Host smart-1085eae0-af5d-4457-a8a5-771d170e308b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25748
32141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2574832141
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1914870056
Short name T2055
Test name
Test status
Simulation time 184613780 ps
CPU time 0.83 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:18 PM PDT 24
Peak memory 206196 kb
Host smart-31eba149-f29a-4973-bc72-e145c8d6b9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19148
70056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1914870056
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.30783752
Short name T2190
Test name
Test status
Simulation time 169151423 ps
CPU time 0.92 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:25 PM PDT 24
Peak memory 206200 kb
Host smart-5ebe236f-1e24-4f8e-bf8f-48c0afd02e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30783
752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.30783752
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.29040796
Short name T1884
Test name
Test status
Simulation time 183847783 ps
CPU time 0.83 seconds
Started Jun 29 06:35:19 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206220 kb
Host smart-adc0e0ef-2b8b-41f6-a116-04d96e0438e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29040
796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.29040796
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1475438227
Short name T2005
Test name
Test status
Simulation time 225662485 ps
CPU time 0.97 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206224 kb
Host smart-95ec4058-5aad-4a96-92b1-db99b1ab46db
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1475438227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1475438227
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3581371529
Short name T1140
Test name
Test status
Simulation time 135528977 ps
CPU time 0.81 seconds
Started Jun 29 06:35:24 PM PDT 24
Finished Jun 29 06:35:26 PM PDT 24
Peak memory 206212 kb
Host smart-4922c721-8529-4b77-ac08-4c519c9279dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35813
71529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3581371529
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2791914889
Short name T921
Test name
Test status
Simulation time 106502513 ps
CPU time 0.72 seconds
Started Jun 29 06:35:34 PM PDT 24
Finished Jun 29 06:35:35 PM PDT 24
Peak memory 206176 kb
Host smart-6ad87739-08a4-4a35-a26b-63d1946ec17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27919
14889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2791914889
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3097107366
Short name T96
Test name
Test status
Simulation time 13087179026 ps
CPU time 29.87 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:54 PM PDT 24
Peak memory 206428 kb
Host smart-ccf4ab1f-efc6-4e9c-97af-10c696a54686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30971
07366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3097107366
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2384932731
Short name T401
Test name
Test status
Simulation time 167779971 ps
CPU time 0.83 seconds
Started Jun 29 06:35:19 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206192 kb
Host smart-d15556c1-1787-411e-a0a1-222a769bec62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23849
32731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2384932731
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3452012880
Short name T388
Test name
Test status
Simulation time 215020173 ps
CPU time 0.86 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206212 kb
Host smart-6df7e573-711f-4168-b81c-13f20dc3c18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34520
12880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3452012880
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.770397547
Short name T2416
Test name
Test status
Simulation time 228183165 ps
CPU time 0.87 seconds
Started Jun 29 06:35:41 PM PDT 24
Finished Jun 29 06:35:42 PM PDT 24
Peak memory 206212 kb
Host smart-90ac7938-d6ea-4fde-bfa5-c20e4f46a827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77039
7547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.770397547
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.3565549476
Short name T227
Test name
Test status
Simulation time 190411125 ps
CPU time 0.83 seconds
Started Jun 29 06:35:24 PM PDT 24
Finished Jun 29 06:35:26 PM PDT 24
Peak memory 206200 kb
Host smart-bba60df3-6185-4234-9c36-e77969c97513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35655
49476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.3565549476
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2165794665
Short name T1574
Test name
Test status
Simulation time 162377835 ps
CPU time 0.84 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:25 PM PDT 24
Peak memory 206196 kb
Host smart-de875807-f35f-4c7d-b0f3-18624438d7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21657
94665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2165794665
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2691268486
Short name T1909
Test name
Test status
Simulation time 218337874 ps
CPU time 0.79 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:25 PM PDT 24
Peak memory 206196 kb
Host smart-d211cb95-513e-4f15-9eac-597811510c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26912
68486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2691268486
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.720138742
Short name T756
Test name
Test status
Simulation time 169121875 ps
CPU time 0.77 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:25 PM PDT 24
Peak memory 206192 kb
Host smart-05eb1918-eb44-4ab0-9306-3bb1ac294db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72013
8742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.720138742
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2011594166
Short name T1827
Test name
Test status
Simulation time 264232231 ps
CPU time 1 seconds
Started Jun 29 06:35:29 PM PDT 24
Finished Jun 29 06:35:30 PM PDT 24
Peak memory 206180 kb
Host smart-fd24cd2f-ada2-42c0-a7ee-230eb4ef998d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20115
94166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2011594166
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3132477575
Short name T2074
Test name
Test status
Simulation time 3653097464 ps
CPU time 26.27 seconds
Started Jun 29 06:35:22 PM PDT 24
Finished Jun 29 06:35:50 PM PDT 24
Peak memory 206400 kb
Host smart-7212867b-4a51-4870-b87f-84266d8acecd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3132477575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3132477575
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2284569674
Short name T1148
Test name
Test status
Simulation time 167323418 ps
CPU time 0.77 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206224 kb
Host smart-84fbf524-440e-4bb8-8db5-690f2a5d9133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22845
69674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2284569674
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.847065405
Short name T557
Test name
Test status
Simulation time 193338145 ps
CPU time 0.83 seconds
Started Jun 29 06:35:25 PM PDT 24
Finished Jun 29 06:35:26 PM PDT 24
Peak memory 206196 kb
Host smart-ba72038f-b4dc-4544-8b84-47c05433355d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84706
5405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.847065405
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1165667175
Short name T2396
Test name
Test status
Simulation time 3968902650 ps
CPU time 28.38 seconds
Started Jun 29 06:35:31 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206468 kb
Host smart-720ab2be-bce7-4d6b-b41c-c1a0e99e855a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
67175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1165667175
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.3217458535
Short name T2220
Test name
Test status
Simulation time 73907228 ps
CPU time 0.67 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 206132 kb
Host smart-4b64db24-7203-44e1-befd-dccb9e143685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3217458535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.3217458535
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2264507254
Short name T10
Test name
Test status
Simulation time 23379312713 ps
CPU time 23.65 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:35:45 PM PDT 24
Peak memory 206324 kb
Host smart-91c7e3e6-36e1-44e8-9276-2d824dba0751
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2264507254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2264507254
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1621666904
Short name T663
Test name
Test status
Simulation time 156653405 ps
CPU time 0.76 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206220 kb
Host smart-53b4bbae-9dba-4fb7-b0ae-f3cfb49e562e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216
66904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1621666904
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3233072755
Short name T70
Test name
Test status
Simulation time 154098633 ps
CPU time 0.77 seconds
Started Jun 29 06:35:24 PM PDT 24
Finished Jun 29 06:35:26 PM PDT 24
Peak memory 206172 kb
Host smart-a9345298-8f2b-44f5-a39e-c5a6fe19ccfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32330
72755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3233072755
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.483530402
Short name T1359
Test name
Test status
Simulation time 198811684 ps
CPU time 0.88 seconds
Started Jun 29 06:35:35 PM PDT 24
Finished Jun 29 06:35:36 PM PDT 24
Peak memory 206164 kb
Host smart-85f18cf0-54f4-4ce9-978f-2e821cea140b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48353
0402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.483530402
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1978219583
Short name T616
Test name
Test status
Simulation time 22037074875 ps
CPU time 38.68 seconds
Started Jun 29 06:35:19 PM PDT 24
Finished Jun 29 06:35:59 PM PDT 24
Peak memory 206384 kb
Host smart-62838523-5767-461f-b34c-f280a7b96b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19782
19583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1978219583
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.4141038276
Short name T1335
Test name
Test status
Simulation time 469770340 ps
CPU time 1.46 seconds
Started Jun 29 06:35:24 PM PDT 24
Finished Jun 29 06:35:26 PM PDT 24
Peak memory 206176 kb
Host smart-02802abe-59e7-4ca7-9bdb-74ff1972f588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41410
38276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.4141038276
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.1058844720
Short name T1670
Test name
Test status
Simulation time 167868986 ps
CPU time 0.79 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206220 kb
Host smart-968ed17d-dc96-43d9-8b08-645e28231211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10588
44720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.1058844720
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1325769008
Short name T1170
Test name
Test status
Simulation time 89151467 ps
CPU time 0.78 seconds
Started Jun 29 06:35:28 PM PDT 24
Finished Jun 29 06:35:30 PM PDT 24
Peak memory 206116 kb
Host smart-daf12f95-684f-4e57-b81e-25be2c628fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13257
69008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1325769008
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.483831536
Short name T1033
Test name
Test status
Simulation time 928397352 ps
CPU time 2.37 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:27 PM PDT 24
Peak memory 206348 kb
Host smart-30561244-1a9e-4231-a6c1-d0b37c2d2ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48383
1536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.483831536
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1508662848
Short name T1222
Test name
Test status
Simulation time 159506920 ps
CPU time 1.53 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:26 PM PDT 24
Peak memory 206256 kb
Host smart-b327b0bc-c374-4de6-901e-25c9c371b39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15086
62848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1508662848
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3695034127
Short name T1509
Test name
Test status
Simulation time 198095028 ps
CPU time 0.84 seconds
Started Jun 29 06:35:34 PM PDT 24
Finished Jun 29 06:35:36 PM PDT 24
Peak memory 206200 kb
Host smart-34cfe9ed-7f21-48ac-b617-944afe10dfdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36950
34127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3695034127
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2268213024
Short name T1320
Test name
Test status
Simulation time 141984569 ps
CPU time 0.75 seconds
Started Jun 29 06:35:29 PM PDT 24
Finished Jun 29 06:35:30 PM PDT 24
Peak memory 206192 kb
Host smart-2e8eb704-ddfd-4552-8078-98dbf654dc66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22682
13024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2268213024
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3648271149
Short name T1097
Test name
Test status
Simulation time 191267071 ps
CPU time 0.91 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206212 kb
Host smart-38699e79-b4ee-473a-bd8b-0a10332e3e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36482
71149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3648271149
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.3420300756
Short name T112
Test name
Test status
Simulation time 8861481076 ps
CPU time 63.96 seconds
Started Jun 29 06:35:35 PM PDT 24
Finished Jun 29 06:36:40 PM PDT 24
Peak memory 206412 kb
Host smart-ca1bab25-8847-4a7b-9074-bdc65989e08b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3420300756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.3420300756
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3215150785
Short name T566
Test name
Test status
Simulation time 153911090 ps
CPU time 0.8 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206196 kb
Host smart-6a69d0c3-cec3-4e55-a982-9aaf13fc8481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32151
50785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3215150785
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2716167197
Short name T1476
Test name
Test status
Simulation time 23286029498 ps
CPU time 22.37 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 206316 kb
Host smart-6959c784-fa21-4a61-bd8e-ab96eea59b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27161
67197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2716167197
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.655394884
Short name T1722
Test name
Test status
Simulation time 3282123201 ps
CPU time 3.72 seconds
Started Jun 29 06:35:28 PM PDT 24
Finished Jun 29 06:35:32 PM PDT 24
Peak memory 206240 kb
Host smart-e02e70f4-4c78-4c59-91a7-3a580e52d62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65539
4884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.655394884
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.1865783329
Short name T1255
Test name
Test status
Simulation time 7183424351 ps
CPU time 202.18 seconds
Started Jun 29 06:35:21 PM PDT 24
Finished Jun 29 06:38:44 PM PDT 24
Peak memory 206464 kb
Host smart-f58777f8-afe2-4bf8-9fec-02723e52efd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18657
83329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1865783329
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3252484997
Short name T535
Test name
Test status
Simulation time 7475181980 ps
CPU time 196.86 seconds
Started Jun 29 06:35:23 PM PDT 24
Finished Jun 29 06:38:41 PM PDT 24
Peak memory 206452 kb
Host smart-a24e196c-4c26-4249-90b6-cff172bf2ab5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3252484997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3252484997
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.207374462
Short name T1324
Test name
Test status
Simulation time 239849083 ps
CPU time 0.93 seconds
Started Jun 29 06:35:34 PM PDT 24
Finished Jun 29 06:35:36 PM PDT 24
Peak memory 206168 kb
Host smart-4278cbea-891a-4fe8-a661-7c1205724d89
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=207374462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.207374462
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.639925778
Short name T795
Test name
Test status
Simulation time 192200918 ps
CPU time 0.91 seconds
Started Jun 29 06:35:30 PM PDT 24
Finished Jun 29 06:35:32 PM PDT 24
Peak memory 206216 kb
Host smart-d3026654-ddd5-4699-8daf-14d421be88e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63992
5778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.639925778
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.397492353
Short name T2454
Test name
Test status
Simulation time 5605925920 ps
CPU time 50.18 seconds
Started Jun 29 06:35:41 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206440 kb
Host smart-8ea7b489-360a-432f-980a-e509413b8562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39749
2353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.397492353
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.43939102
Short name T1162
Test name
Test status
Simulation time 5582605969 ps
CPU time 53.86 seconds
Started Jun 29 06:35:42 PM PDT 24
Finished Jun 29 06:36:36 PM PDT 24
Peak memory 206460 kb
Host smart-671ca7f4-7541-444c-a05a-9b29584aaa90
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=43939102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.43939102
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3380108070
Short name T1130
Test name
Test status
Simulation time 210546648 ps
CPU time 0.89 seconds
Started Jun 29 06:35:36 PM PDT 24
Finished Jun 29 06:35:38 PM PDT 24
Peak memory 206216 kb
Host smart-90a56845-e83e-4b22-9db5-a97f3e4df607
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3380108070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3380108070
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.919053635
Short name T1860
Test name
Test status
Simulation time 147305132 ps
CPU time 0.77 seconds
Started Jun 29 06:35:33 PM PDT 24
Finished Jun 29 06:35:34 PM PDT 24
Peak memory 206180 kb
Host smart-caf40c34-839f-4a0d-8585-f1487e92bdf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91905
3635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.919053635
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2789224878
Short name T145
Test name
Test status
Simulation time 174720239 ps
CPU time 0.82 seconds
Started Jun 29 06:35:32 PM PDT 24
Finished Jun 29 06:35:33 PM PDT 24
Peak memory 206196 kb
Host smart-b829208f-c73d-44ce-8d16-de60414e89f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27892
24878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2789224878
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2206478057
Short name T2066
Test name
Test status
Simulation time 152431876 ps
CPU time 0.8 seconds
Started Jun 29 06:35:30 PM PDT 24
Finished Jun 29 06:35:32 PM PDT 24
Peak memory 206196 kb
Host smart-56045f84-bfec-40af-aa1b-d4e59d202b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22064
78057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2206478057
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1745502913
Short name T1381
Test name
Test status
Simulation time 179649469 ps
CPU time 0.79 seconds
Started Jun 29 06:35:30 PM PDT 24
Finished Jun 29 06:35:31 PM PDT 24
Peak memory 206196 kb
Host smart-fb82a5a8-9842-4194-b5a6-ca59a6e96a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17455
02913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1745502913
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.180498021
Short name T2537
Test name
Test status
Simulation time 183167583 ps
CPU time 0.82 seconds
Started Jun 29 06:35:30 PM PDT 24
Finished Jun 29 06:35:32 PM PDT 24
Peak memory 206192 kb
Host smart-67443e2e-fdc7-40e1-9e61-be84c73c2446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18049
8021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.180498021
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.4108409571
Short name T1218
Test name
Test status
Simulation time 165188797 ps
CPU time 0.82 seconds
Started Jun 29 06:35:26 PM PDT 24
Finished Jun 29 06:35:27 PM PDT 24
Peak memory 206200 kb
Host smart-a6e35c87-dfe6-430d-acf8-3f78ba6df418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41084
09571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.4108409571
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.2573492443
Short name T1412
Test name
Test status
Simulation time 239004711 ps
CPU time 0.92 seconds
Started Jun 29 06:35:43 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 206216 kb
Host smart-981a9040-651e-49e7-8288-faf3c6b3460c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2573492443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2573492443
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1703673060
Short name T46
Test name
Test status
Simulation time 169998618 ps
CPU time 0.81 seconds
Started Jun 29 06:35:29 PM PDT 24
Finished Jun 29 06:35:30 PM PDT 24
Peak memory 206200 kb
Host smart-99e32ff4-ce36-4120-9fce-0d169db3ba2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17036
73060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1703673060
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4264977369
Short name T1312
Test name
Test status
Simulation time 36599470 ps
CPU time 0.64 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206132 kb
Host smart-713dffaa-4dd0-4968-b5a9-2b745a1b9fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42649
77369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4264977369
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.762031639
Short name T2238
Test name
Test status
Simulation time 18809683418 ps
CPU time 40.5 seconds
Started Jun 29 06:35:40 PM PDT 24
Finished Jun 29 06:36:21 PM PDT 24
Peak memory 206468 kb
Host smart-1cd18ee0-6623-47e9-bc24-de9fbf53c8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76203
1639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.762031639
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2269813683
Short name T2286
Test name
Test status
Simulation time 150813687 ps
CPU time 0.77 seconds
Started Jun 29 06:35:27 PM PDT 24
Finished Jun 29 06:35:28 PM PDT 24
Peak memory 206196 kb
Host smart-cef279d3-85aa-40f5-9844-d57e346b8b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22698
13683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2269813683
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3138284414
Short name T738
Test name
Test status
Simulation time 223279476 ps
CPU time 0.94 seconds
Started Jun 29 06:35:40 PM PDT 24
Finished Jun 29 06:35:41 PM PDT 24
Peak memory 206212 kb
Host smart-6277eb45-48a5-4f6a-aafd-a8a71f528f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31382
84414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3138284414
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1182945784
Short name T2355
Test name
Test status
Simulation time 166432182 ps
CPU time 0.85 seconds
Started Jun 29 06:35:40 PM PDT 24
Finished Jun 29 06:35:41 PM PDT 24
Peak memory 206212 kb
Host smart-5c8c205d-8ff2-4938-8284-b3cfd87e1866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11829
45784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1182945784
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.1315370505
Short name T671
Test name
Test status
Simulation time 179737591 ps
CPU time 0.81 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206120 kb
Host smart-e681db63-4325-4644-bdf6-207b8f5e8ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13153
70505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.1315370505
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3446671127
Short name T2108
Test name
Test status
Simulation time 248347518 ps
CPU time 0.89 seconds
Started Jun 29 06:35:31 PM PDT 24
Finished Jun 29 06:35:32 PM PDT 24
Peak memory 206196 kb
Host smart-0d14fee6-4560-4956-9bde-2e140d5e6078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34466
71127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3446671127
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3943577943
Short name T812
Test name
Test status
Simulation time 156963121 ps
CPU time 0.87 seconds
Started Jun 29 06:35:37 PM PDT 24
Finished Jun 29 06:35:39 PM PDT 24
Peak memory 206196 kb
Host smart-1c37448f-fa4c-4f5d-b4b0-1a90bc994b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39435
77943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3943577943
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1100622749
Short name T2561
Test name
Test status
Simulation time 172323760 ps
CPU time 0.83 seconds
Started Jun 29 06:35:28 PM PDT 24
Finished Jun 29 06:35:30 PM PDT 24
Peak memory 206192 kb
Host smart-5c666b63-2965-41a6-b61e-206d58451d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11006
22749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1100622749
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2853833306
Short name T825
Test name
Test status
Simulation time 212258994 ps
CPU time 0.94 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206384 kb
Host smart-2c0baccf-8399-4303-a035-016601fab9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28538
33306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2853833306
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3535206860
Short name T2477
Test name
Test status
Simulation time 4297210451 ps
CPU time 120.86 seconds
Started Jun 29 06:35:38 PM PDT 24
Finished Jun 29 06:37:39 PM PDT 24
Peak memory 206488 kb
Host smart-294abf3e-cfa4-4f57-a856-38606905e2f2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3535206860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3535206860
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3024061085
Short name T1234
Test name
Test status
Simulation time 168029795 ps
CPU time 0.8 seconds
Started Jun 29 06:35:35 PM PDT 24
Finished Jun 29 06:35:37 PM PDT 24
Peak memory 206224 kb
Host smart-a5c8dbef-18f6-4a61-9a4e-bd35fa479619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30240
61085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3024061085
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3364182628
Short name T824
Test name
Test status
Simulation time 181756710 ps
CPU time 0.83 seconds
Started Jun 29 06:35:27 PM PDT 24
Finished Jun 29 06:35:28 PM PDT 24
Peak memory 206172 kb
Host smart-3ec30989-18ce-4f72-a1f3-6b712c755907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33641
82628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3364182628
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.2080695705
Short name T593
Test name
Test status
Simulation time 6234325954 ps
CPU time 157.83 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:38:24 PM PDT 24
Peak memory 206200 kb
Host smart-bb1a8835-f758-45dc-a6cd-eb4fde906d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20806
95705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.2080695705
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.1284579912
Short name T2095
Test name
Test status
Simulation time 42347004 ps
CPU time 0.7 seconds
Started Jun 29 06:35:36 PM PDT 24
Finished Jun 29 06:35:37 PM PDT 24
Peak memory 206212 kb
Host smart-60802ede-80ef-4a9f-a0e4-3a9a2aa717a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1284579912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1284579912
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.1840035528
Short name T1913
Test name
Test status
Simulation time 3854944472 ps
CPU time 4.29 seconds
Started Jun 29 06:35:29 PM PDT 24
Finished Jun 29 06:35:34 PM PDT 24
Peak memory 206356 kb
Host smart-b1a4a287-2ceb-4c29-8d52-a89523c8a20a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1840035528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.1840035528
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.159525191
Short name T1387
Test name
Test status
Simulation time 13332169841 ps
CPU time 13.62 seconds
Started Jun 29 06:35:29 PM PDT 24
Finished Jun 29 06:35:44 PM PDT 24
Peak memory 206252 kb
Host smart-aaadf5fb-f3c1-4fb8-9170-dece1fb29c5b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=159525191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.159525191
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.122530459
Short name T2624
Test name
Test status
Simulation time 23311585575 ps
CPU time 24.28 seconds
Started Jun 29 06:35:37 PM PDT 24
Finished Jun 29 06:36:02 PM PDT 24
Peak memory 206316 kb
Host smart-a4335b38-de2e-484d-82f9-a7a2aca56a91
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=122530459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.122530459
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2911047963
Short name T1547
Test name
Test status
Simulation time 175895509 ps
CPU time 0.87 seconds
Started Jun 29 06:35:28 PM PDT 24
Finished Jun 29 06:35:29 PM PDT 24
Peak memory 206192 kb
Host smart-aef467b0-fd9a-4712-a5ae-9d65cd0d0011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29110
47963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2911047963
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3189773085
Short name T1994
Test name
Test status
Simulation time 147193284 ps
CPU time 0.79 seconds
Started Jun 29 06:35:35 PM PDT 24
Finished Jun 29 06:35:36 PM PDT 24
Peak memory 206196 kb
Host smart-ea3a4e0f-c3ef-42ba-a587-c2ebc7eb8482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31897
73085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3189773085
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.44431659
Short name T931
Test name
Test status
Simulation time 490935140 ps
CPU time 1.52 seconds
Started Jun 29 06:35:35 PM PDT 24
Finished Jun 29 06:35:37 PM PDT 24
Peak memory 206336 kb
Host smart-ee94c84c-4f20-458e-bfb8-4e6e9e7f74a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44431
659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.44431659
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3163137400
Short name T723
Test name
Test status
Simulation time 373902781 ps
CPU time 1.2 seconds
Started Jun 29 06:35:43 PM PDT 24
Finished Jun 29 06:35:45 PM PDT 24
Peak memory 206196 kb
Host smart-448a24d4-a796-4892-9d14-8f956bd4f0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31631
37400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3163137400
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.58069285
Short name T2156
Test name
Test status
Simulation time 13384310542 ps
CPU time 23.53 seconds
Started Jun 29 06:35:33 PM PDT 24
Finished Jun 29 06:35:57 PM PDT 24
Peak memory 206476 kb
Host smart-ae66fd7b-394d-478e-8263-25ad01386ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58069
285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.58069285
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.3625018840
Short name T2452
Test name
Test status
Simulation time 331579928 ps
CPU time 1.19 seconds
Started Jun 29 06:35:37 PM PDT 24
Finished Jun 29 06:35:39 PM PDT 24
Peak memory 206192 kb
Host smart-d84f4b51-7323-4b5c-9673-f5a3c59e7223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36250
18840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.3625018840
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3750716797
Short name T1069
Test name
Test status
Simulation time 137478758 ps
CPU time 0.75 seconds
Started Jun 29 06:35:42 PM PDT 24
Finished Jun 29 06:35:43 PM PDT 24
Peak memory 206148 kb
Host smart-c51f39f4-5c80-437a-8ddc-4ee14bb96498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37507
16797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3750716797
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2887261158
Short name T329
Test name
Test status
Simulation time 69111949 ps
CPU time 0.64 seconds
Started Jun 29 06:35:30 PM PDT 24
Finished Jun 29 06:35:31 PM PDT 24
Peak memory 206192 kb
Host smart-051cc564-cacc-4a2e-b737-f7f6faebc09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28872
61158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2887261158
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.4088577333
Short name T833
Test name
Test status
Simulation time 869953410 ps
CPU time 2.02 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:48 PM PDT 24
Peak memory 206244 kb
Host smart-ea1a8d97-8d51-4ad6-84bb-242a6d56ab3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40885
77333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.4088577333
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.515705761
Short name T2481
Test name
Test status
Simulation time 178530618 ps
CPU time 1.99 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:35:48 PM PDT 24
Peak memory 206100 kb
Host smart-8e154c34-6dbe-474f-b339-82716a060cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51570
5761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.515705761
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1130398916
Short name T920
Test name
Test status
Simulation time 214883568 ps
CPU time 0.87 seconds
Started Jun 29 06:35:33 PM PDT 24
Finished Jun 29 06:35:34 PM PDT 24
Peak memory 206200 kb
Host smart-46bb008f-2c37-4735-9ed5-7ca0f763eeae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11303
98916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1130398916
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.722292866
Short name T1331
Test name
Test status
Simulation time 141455156 ps
CPU time 0.77 seconds
Started Jun 29 06:35:42 PM PDT 24
Finished Jun 29 06:35:43 PM PDT 24
Peak memory 206212 kb
Host smart-f2f6f837-fa0f-4946-b581-97d45e315ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72229
2866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.722292866
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2546631527
Short name T406
Test name
Test status
Simulation time 213988080 ps
CPU time 0.86 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 206136 kb
Host smart-bad14e7d-22d7-48b5-8d54-f657dce7412d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25466
31527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2546631527
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3873267651
Short name T2227
Test name
Test status
Simulation time 10125767395 ps
CPU time 278.75 seconds
Started Jun 29 06:35:29 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206500 kb
Host smart-605487ee-143f-4b65-816d-6114b08ab23f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3873267651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3873267651
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.4219922849
Short name T820
Test name
Test status
Simulation time 260066747 ps
CPU time 0.93 seconds
Started Jun 29 06:35:46 PM PDT 24
Finished Jun 29 06:35:48 PM PDT 24
Peak memory 206116 kb
Host smart-30772dce-0eec-41cc-b2d2-4ab3a1cae93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42199
22849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.4219922849
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.871621907
Short name T2547
Test name
Test status
Simulation time 23274216866 ps
CPU time 24.13 seconds
Started Jun 29 06:35:43 PM PDT 24
Finished Jun 29 06:36:08 PM PDT 24
Peak memory 206316 kb
Host smart-e9410e5c-69f7-400a-9e8d-f67ef02cbb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87162
1907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.871621907
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.563784557
Short name T2377
Test name
Test status
Simulation time 3350316241 ps
CPU time 4.41 seconds
Started Jun 29 06:35:42 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206264 kb
Host smart-30e0d2d1-b544-4239-9e9f-0d8c074cc925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56378
4557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.563784557
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.3156854690
Short name T1501
Test name
Test status
Simulation time 9192328158 ps
CPU time 66.75 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:36:52 PM PDT 24
Peak memory 206472 kb
Host smart-11b065db-3a19-4ad0-ac16-729b436179dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31568
54690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.3156854690
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1371436554
Short name T2271
Test name
Test status
Simulation time 4192978220 ps
CPU time 121.11 seconds
Started Jun 29 06:35:36 PM PDT 24
Finished Jun 29 06:37:38 PM PDT 24
Peak memory 206432 kb
Host smart-87dcc60f-5590-4ceb-a67d-abdd704a0df2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1371436554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1371436554
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1554570198
Short name T1379
Test name
Test status
Simulation time 245995144 ps
CPU time 0.97 seconds
Started Jun 29 06:35:35 PM PDT 24
Finished Jun 29 06:35:37 PM PDT 24
Peak memory 206196 kb
Host smart-f47b3f5b-9c44-4e11-bad9-d6cc7b9bf510
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1554570198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1554570198
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2175960534
Short name T313
Test name
Test status
Simulation time 190906497 ps
CPU time 0.95 seconds
Started Jun 29 06:35:42 PM PDT 24
Finished Jun 29 06:35:43 PM PDT 24
Peak memory 206216 kb
Host smart-c8d120d8-fa4b-45f0-b286-c50f286a883a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21759
60534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2175960534
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2065682466
Short name T786
Test name
Test status
Simulation time 3575952102 ps
CPU time 32.63 seconds
Started Jun 29 06:35:36 PM PDT 24
Finished Jun 29 06:36:09 PM PDT 24
Peak memory 206504 kb
Host smart-aea48a52-4bd9-4c55-8735-11482c5e8a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20656
82466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2065682466
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.128952917
Short name T1906
Test name
Test status
Simulation time 4745600273 ps
CPU time 128.46 seconds
Started Jun 29 06:35:41 PM PDT 24
Finished Jun 29 06:37:50 PM PDT 24
Peak memory 206476 kb
Host smart-76f739b3-1439-4f2a-ad09-eeb368df3508
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=128952917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.128952917
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3253065918
Short name T328
Test name
Test status
Simulation time 152442332 ps
CPU time 0.82 seconds
Started Jun 29 06:35:40 PM PDT 24
Finished Jun 29 06:35:42 PM PDT 24
Peak memory 206220 kb
Host smart-828cec6e-e094-4b99-89fc-892d43d4aa93
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3253065918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3253065918
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.934001587
Short name T1450
Test name
Test status
Simulation time 144800527 ps
CPU time 0.81 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206160 kb
Host smart-9be88dc3-ddc8-4c82-815d-bcc5db459c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93400
1587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.934001587
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.3783635955
Short name T1663
Test name
Test status
Simulation time 190819731 ps
CPU time 0.91 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 206212 kb
Host smart-7261960c-4225-4253-aaa2-55dc58964efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37836
35955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3783635955
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1770504908
Short name T638
Test name
Test status
Simulation time 193601027 ps
CPU time 0.81 seconds
Started Jun 29 06:35:38 PM PDT 24
Finished Jun 29 06:35:39 PM PDT 24
Peak memory 206200 kb
Host smart-ebf3e49f-75ec-48ed-bbac-6ec9181beb8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17705
04908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1770504908
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.4094127517
Short name T848
Test name
Test status
Simulation time 156073600 ps
CPU time 0.82 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206196 kb
Host smart-502a1e36-d181-4595-8294-1205a1cfce09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40941
27517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.4094127517
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1641591563
Short name T2476
Test name
Test status
Simulation time 152935519 ps
CPU time 0.77 seconds
Started Jun 29 06:35:35 PM PDT 24
Finished Jun 29 06:35:37 PM PDT 24
Peak memory 206200 kb
Host smart-69cf9c06-a57b-4569-a50b-d75d194639cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16415
91563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1641591563
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3606545302
Short name T215
Test name
Test status
Simulation time 255444398 ps
CPU time 0.96 seconds
Started Jun 29 06:35:38 PM PDT 24
Finished Jun 29 06:35:40 PM PDT 24
Peak memory 206224 kb
Host smart-46258115-d17d-442c-ba9d-7c1a5296698b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3606545302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3606545302
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.947986154
Short name T1035
Test name
Test status
Simulation time 168072148 ps
CPU time 0.78 seconds
Started Jun 29 06:35:38 PM PDT 24
Finished Jun 29 06:35:39 PM PDT 24
Peak memory 206216 kb
Host smart-1c727bb0-f460-43a9-9b7d-a1b86bff5af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94798
6154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.947986154
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2198758809
Short name T2060
Test name
Test status
Simulation time 35051908 ps
CPU time 0.67 seconds
Started Jun 29 06:35:41 PM PDT 24
Finished Jun 29 06:35:42 PM PDT 24
Peak memory 206212 kb
Host smart-dba65dad-44f1-45a8-ba94-fd2c42278e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21987
58809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2198758809
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1097700391
Short name T2453
Test name
Test status
Simulation time 6766505230 ps
CPU time 15.88 seconds
Started Jun 29 06:35:36 PM PDT 24
Finished Jun 29 06:35:53 PM PDT 24
Peak memory 206500 kb
Host smart-93be3501-f8f1-49cf-8580-2ab62125e65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10977
00391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1097700391
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.17912182
Short name T874
Test name
Test status
Simulation time 166545700 ps
CPU time 0.81 seconds
Started Jun 29 06:35:39 PM PDT 24
Finished Jun 29 06:35:40 PM PDT 24
Peak memory 206164 kb
Host smart-75773b51-36b6-427f-a02f-cfd86bf40dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17912
182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.17912182
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1720483727
Short name T1522
Test name
Test status
Simulation time 227717460 ps
CPU time 0.92 seconds
Started Jun 29 06:35:35 PM PDT 24
Finished Jun 29 06:35:37 PM PDT 24
Peak memory 206216 kb
Host smart-863bf96d-1b54-4648-a7ac-3ea1d395f7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17204
83727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1720483727
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.3542901223
Short name T2015
Test name
Test status
Simulation time 213997111 ps
CPU time 0.96 seconds
Started Jun 29 06:35:42 PM PDT 24
Finished Jun 29 06:35:44 PM PDT 24
Peak memory 206204 kb
Host smart-74650446-5b56-403d-9f39-d8d0ad1beaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35429
01223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.3542901223
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.340151831
Short name T1879
Test name
Test status
Simulation time 178332033 ps
CPU time 0.84 seconds
Started Jun 29 06:35:36 PM PDT 24
Finished Jun 29 06:35:38 PM PDT 24
Peak memory 206200 kb
Host smart-c922ac50-3830-4920-902f-e5dbbb1ea8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34015
1831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.340151831
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2519528326
Short name T1772
Test name
Test status
Simulation time 231485702 ps
CPU time 0.91 seconds
Started Jun 29 06:35:49 PM PDT 24
Finished Jun 29 06:35:50 PM PDT 24
Peak memory 206368 kb
Host smart-a6356298-9d44-4c9e-9d58-23ee3196c0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25195
28326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2519528326
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1978417444
Short name T1987
Test name
Test status
Simulation time 169987500 ps
CPU time 0.77 seconds
Started Jun 29 06:35:35 PM PDT 24
Finished Jun 29 06:35:36 PM PDT 24
Peak memory 206188 kb
Host smart-f220c6d3-6f9d-4cd5-8d93-d974cb34265e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19784
17444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1978417444
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1288597387
Short name T495
Test name
Test status
Simulation time 152026579 ps
CPU time 0.76 seconds
Started Jun 29 06:35:43 PM PDT 24
Finished Jun 29 06:35:44 PM PDT 24
Peak memory 206192 kb
Host smart-28940e24-c357-4d97-b3d7-9b854135e07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12885
97387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1288597387
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3792400917
Short name T1146
Test name
Test status
Simulation time 236609625 ps
CPU time 0.96 seconds
Started Jun 29 06:35:40 PM PDT 24
Finished Jun 29 06:35:41 PM PDT 24
Peak memory 206180 kb
Host smart-bf161dc5-6807-4caf-9568-a9cadb43a06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37924
00917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3792400917
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3256042896
Short name T417
Test name
Test status
Simulation time 5924542235 ps
CPU time 171.57 seconds
Started Jun 29 06:35:40 PM PDT 24
Finished Jun 29 06:38:32 PM PDT 24
Peak memory 206516 kb
Host smart-b2110bb0-258f-4c1e-b0a5-069cab63e679
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3256042896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3256042896
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2058146531
Short name T484
Test name
Test status
Simulation time 161983970 ps
CPU time 0.8 seconds
Started Jun 29 06:35:39 PM PDT 24
Finished Jun 29 06:35:40 PM PDT 24
Peak memory 206192 kb
Host smart-1ebfc7e2-9ed2-4a1c-a96d-48a3dcfe8fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20581
46531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2058146531
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1877123973
Short name T2164
Test name
Test status
Simulation time 181312878 ps
CPU time 0.88 seconds
Started Jun 29 06:35:35 PM PDT 24
Finished Jun 29 06:35:37 PM PDT 24
Peak memory 206196 kb
Host smart-8738d7cf-111a-4a99-ab78-ba03df2bb67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18771
23973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1877123973
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.1589651197
Short name T1623
Test name
Test status
Simulation time 6830192397 ps
CPU time 188.6 seconds
Started Jun 29 06:35:41 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206472 kb
Host smart-e80573a5-1f82-435c-9b83-f331588fdfcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15896
51197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.1589651197
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.3567693748
Short name T1527
Test name
Test status
Simulation time 48155701 ps
CPU time 0.67 seconds
Started Jun 29 06:35:52 PM PDT 24
Finished Jun 29 06:35:54 PM PDT 24
Peak memory 206204 kb
Host smart-8fcc424e-cf69-4d7f-9973-95efd1eb0df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3567693748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.3567693748
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.87131215
Short name T942
Test name
Test status
Simulation time 4140041949 ps
CPU time 4.85 seconds
Started Jun 29 06:35:36 PM PDT 24
Finished Jun 29 06:35:41 PM PDT 24
Peak memory 206284 kb
Host smart-28dab4d0-2489-4fae-8969-cc1838abe06b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=87131215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.87131215
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1791150341
Short name T204
Test name
Test status
Simulation time 13370817913 ps
CPU time 11.73 seconds
Started Jun 29 06:35:43 PM PDT 24
Finished Jun 29 06:35:55 PM PDT 24
Peak memory 206488 kb
Host smart-383e018c-4069-424d-8227-2ad904ec7079
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1791150341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1791150341
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2992532215
Short name T2014
Test name
Test status
Simulation time 23345401374 ps
CPU time 29.51 seconds
Started Jun 29 06:35:38 PM PDT 24
Finished Jun 29 06:36:08 PM PDT 24
Peak memory 206488 kb
Host smart-0117f235-e980-4734-9da0-936d37f8951c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2992532215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.2992532215
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1090668675
Short name T1109
Test name
Test status
Simulation time 162541780 ps
CPU time 0.89 seconds
Started Jun 29 06:35:38 PM PDT 24
Finished Jun 29 06:35:40 PM PDT 24
Peak memory 206188 kb
Host smart-0dce5ddc-ee81-4c1e-9cf3-de38b5420b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10906
68675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1090668675
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.614746056
Short name T230
Test name
Test status
Simulation time 149300290 ps
CPU time 0.74 seconds
Started Jun 29 06:35:37 PM PDT 24
Finished Jun 29 06:35:38 PM PDT 24
Peak memory 206180 kb
Host smart-e0b7b410-5569-42e2-a38d-e3d951e48a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61474
6056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.614746056
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2888067775
Short name T1015
Test name
Test status
Simulation time 173215557 ps
CPU time 0.82 seconds
Started Jun 29 06:35:39 PM PDT 24
Finished Jun 29 06:35:40 PM PDT 24
Peak memory 206192 kb
Host smart-6e499924-7745-4ba6-a2c1-61997ece74e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28880
67775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2888067775
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2856237538
Short name T1636
Test name
Test status
Simulation time 344755996 ps
CPU time 1.12 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:35:48 PM PDT 24
Peak memory 206196 kb
Host smart-ecc54f4f-cc20-4a3e-865b-f243b47997b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28562
37538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2856237538
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.2469063611
Short name T1391
Test name
Test status
Simulation time 15077690569 ps
CPU time 29.72 seconds
Started Jun 29 06:35:39 PM PDT 24
Finished Jun 29 06:36:09 PM PDT 24
Peak memory 206460 kb
Host smart-f80c3698-c9ab-4d51-9a98-4a4acbcdc7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24690
63611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.2469063611
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.2477355639
Short name T2599
Test name
Test status
Simulation time 325300566 ps
CPU time 1.12 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 206192 kb
Host smart-929f2ed1-66d6-43e6-ac4a-d935bebc3115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24773
55639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.2477355639
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.976171483
Short name T1047
Test name
Test status
Simulation time 159907726 ps
CPU time 0.8 seconds
Started Jun 29 06:35:47 PM PDT 24
Finished Jun 29 06:35:48 PM PDT 24
Peak memory 206200 kb
Host smart-a92d95bd-5937-4f82-8984-05bc2748ded8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97617
1483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.976171483
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.895055447
Short name T947
Test name
Test status
Simulation time 38095751 ps
CPU time 0.74 seconds
Started Jun 29 06:35:47 PM PDT 24
Finished Jun 29 06:35:49 PM PDT 24
Peak memory 206184 kb
Host smart-b9b2b572-a7c7-466b-b5e8-1e0bec7ad9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89505
5447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.895055447
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1005651668
Short name T709
Test name
Test status
Simulation time 885342732 ps
CPU time 2.03 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206340 kb
Host smart-4a368340-3a8b-4fae-81dd-fdf18affabee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10056
51668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1005651668
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3601663979
Short name T2099
Test name
Test status
Simulation time 219691843 ps
CPU time 1.34 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206208 kb
Host smart-31bbafe8-3e62-42b1-a04a-fcf0839b23e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36016
63979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3601663979
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3675345759
Short name T2259
Test name
Test status
Simulation time 236370495 ps
CPU time 0.96 seconds
Started Jun 29 06:35:50 PM PDT 24
Finished Jun 29 06:35:52 PM PDT 24
Peak memory 206204 kb
Host smart-6e857681-fdc4-4395-bdb9-293633254d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36753
45759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3675345759
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1984043616
Short name T1534
Test name
Test status
Simulation time 133737300 ps
CPU time 0.75 seconds
Started Jun 29 06:35:47 PM PDT 24
Finished Jun 29 06:35:48 PM PDT 24
Peak memory 206216 kb
Host smart-c5af8a08-0e9f-4f57-9732-1afdb87d7707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19840
43616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1984043616
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3113821350
Short name T2169
Test name
Test status
Simulation time 203828718 ps
CPU time 0.92 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206184 kb
Host smart-1eaa1a5c-fcbb-4e4b-89ee-3fc6d5e8421c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
21350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3113821350
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.507790943
Short name T2627
Test name
Test status
Simulation time 246927265 ps
CPU time 0.93 seconds
Started Jun 29 06:35:47 PM PDT 24
Finished Jun 29 06:35:49 PM PDT 24
Peak memory 206196 kb
Host smart-2b510bdc-5942-4a4a-ab82-c99b6f2dfb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50779
0943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.507790943
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.2242401163
Short name T1830
Test name
Test status
Simulation time 23313257138 ps
CPU time 29.52 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:36:16 PM PDT 24
Peak memory 206312 kb
Host smart-fb255520-cc02-4757-ac7d-85615ee3e707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22424
01163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2242401163
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.225651534
Short name T885
Test name
Test status
Simulation time 3341768851 ps
CPU time 4.74 seconds
Started Jun 29 06:35:55 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206136 kb
Host smart-d9eb8098-8ee0-4649-8f8e-a79ee346c6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22565
1534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.225651534
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3251756455
Short name T1256
Test name
Test status
Simulation time 7671160420 ps
CPU time 73.08 seconds
Started Jun 29 06:35:55 PM PDT 24
Finished Jun 29 06:37:09 PM PDT 24
Peak memory 206420 kb
Host smart-150bd569-4c4f-4a7a-9203-a325640e86be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32517
56455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3251756455
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3791084818
Short name T1446
Test name
Test status
Simulation time 4339075969 ps
CPU time 119.19 seconds
Started Jun 29 06:35:46 PM PDT 24
Finished Jun 29 06:37:46 PM PDT 24
Peak memory 206460 kb
Host smart-f32a29bf-f986-4ccc-9411-da53db8d32d4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3791084818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3791084818
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2223848230
Short name T1072
Test name
Test status
Simulation time 246905976 ps
CPU time 0.91 seconds
Started Jun 29 06:35:43 PM PDT 24
Finished Jun 29 06:35:45 PM PDT 24
Peak memory 206220 kb
Host smart-c1325596-5b56-4534-98a3-d90d7f274a61
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2223848230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2223848230
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1422099418
Short name T1051
Test name
Test status
Simulation time 193536500 ps
CPU time 0.92 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206216 kb
Host smart-0479351f-97ea-4255-8657-de490668bc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14220
99418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1422099418
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1901499708
Short name T2224
Test name
Test status
Simulation time 4830596418 ps
CPU time 42.22 seconds
Started Jun 29 06:35:57 PM PDT 24
Finished Jun 29 06:36:39 PM PDT 24
Peak memory 206368 kb
Host smart-161a5857-ac41-4250-9121-dfea14e09e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19014
99708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1901499708
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3599199009
Short name T2111
Test name
Test status
Simulation time 3113713916 ps
CPU time 29.15 seconds
Started Jun 29 06:35:51 PM PDT 24
Finished Jun 29 06:36:21 PM PDT 24
Peak memory 206416 kb
Host smart-ebabc8e4-18a6-4921-b171-cbf6cfe82c15
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3599199009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3599199009
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2918837229
Short name T1070
Test name
Test status
Simulation time 230002773 ps
CPU time 0.87 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206212 kb
Host smart-798a67dd-7d94-4ffb-83c5-f25275c025ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2918837229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2918837229
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2924642394
Short name T1073
Test name
Test status
Simulation time 146929193 ps
CPU time 0.77 seconds
Started Jun 29 06:35:42 PM PDT 24
Finished Jun 29 06:35:43 PM PDT 24
Peak memory 206116 kb
Host smart-e8ce9bea-6c5e-4247-9b9f-5f7d70e64fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29246
42394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2924642394
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.776712008
Short name T2163
Test name
Test status
Simulation time 225296938 ps
CPU time 0.9 seconds
Started Jun 29 06:35:57 PM PDT 24
Finished Jun 29 06:35:58 PM PDT 24
Peak memory 206204 kb
Host smart-55ec007a-b417-46a3-9fba-ed62c3dc5983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77671
2008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.776712008
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1680665869
Short name T2508
Test name
Test status
Simulation time 205803478 ps
CPU time 0.87 seconds
Started Jun 29 06:35:51 PM PDT 24
Finished Jun 29 06:35:53 PM PDT 24
Peak memory 206196 kb
Host smart-2a76def6-ae83-44bb-9e12-869390356477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16806
65869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1680665869
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2695285844
Short name T1132
Test name
Test status
Simulation time 158031677 ps
CPU time 0.83 seconds
Started Jun 29 06:35:47 PM PDT 24
Finished Jun 29 06:35:49 PM PDT 24
Peak memory 206196 kb
Host smart-a29a26f8-965f-4a03-b680-e636f37240ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26952
85844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2695285844
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3088063424
Short name T2071
Test name
Test status
Simulation time 155510236 ps
CPU time 0.81 seconds
Started Jun 29 06:35:48 PM PDT 24
Finished Jun 29 06:35:49 PM PDT 24
Peak memory 206200 kb
Host smart-391aeb7e-09ac-4539-b615-a37231e055e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30880
63424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3088063424
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2339461273
Short name T1653
Test name
Test status
Simulation time 203094344 ps
CPU time 0.88 seconds
Started Jun 29 06:35:51 PM PDT 24
Finished Jun 29 06:35:53 PM PDT 24
Peak memory 206224 kb
Host smart-5ada310d-e73a-4258-9f9a-3b201b9c9ca3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2339461273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2339461273
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.804602270
Short name T852
Test name
Test status
Simulation time 146532945 ps
CPU time 0.79 seconds
Started Jun 29 06:36:10 PM PDT 24
Finished Jun 29 06:36:12 PM PDT 24
Peak memory 206368 kb
Host smart-317db171-8d6a-4c52-8f94-c54f3ba1baf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80460
2270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.804602270
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.669123672
Short name T1707
Test name
Test status
Simulation time 96847726 ps
CPU time 0.72 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 206212 kb
Host smart-b8189700-79a5-44a4-a41d-41e468d5e029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66912
3672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.669123672
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.784597245
Short name T1403
Test name
Test status
Simulation time 6098761230 ps
CPU time 13.33 seconds
Started Jun 29 06:35:46 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206428 kb
Host smart-937111b3-88e9-4008-9f31-0081993f5c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78459
7245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.784597245
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3642974703
Short name T660
Test name
Test status
Simulation time 154758300 ps
CPU time 0.75 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:35:59 PM PDT 24
Peak memory 206108 kb
Host smart-a8abe53b-646c-4360-a4a4-21b68e48f7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36429
74703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3642974703
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.252194447
Short name T829
Test name
Test status
Simulation time 189440813 ps
CPU time 0.83 seconds
Started Jun 29 06:35:47 PM PDT 24
Finished Jun 29 06:35:49 PM PDT 24
Peak memory 206212 kb
Host smart-9fd5f944-576a-45f9-bf40-afb3026b86f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25219
4447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.252194447
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2251283156
Short name T938
Test name
Test status
Simulation time 208728598 ps
CPU time 0.89 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 206128 kb
Host smart-07f13a63-34ea-4045-a773-214a813b0763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22512
83156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2251283156
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.242671338
Short name T1843
Test name
Test status
Simulation time 205352542 ps
CPU time 0.98 seconds
Started Jun 29 06:35:42 PM PDT 24
Finished Jun 29 06:35:44 PM PDT 24
Peak memory 206200 kb
Host smart-c97da584-bc1b-467e-a269-fb94c0e26eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24267
1338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.242671338
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1132061044
Short name T1849
Test name
Test status
Simulation time 142225841 ps
CPU time 0.76 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206160 kb
Host smart-9f1c5266-05b3-4da7-bde7-2158d300fee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11320
61044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1132061044
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1494494724
Short name T2384
Test name
Test status
Simulation time 158590935 ps
CPU time 0.8 seconds
Started Jun 29 06:35:47 PM PDT 24
Finished Jun 29 06:35:49 PM PDT 24
Peak memory 206196 kb
Host smart-3f2b98f0-3425-4c75-b079-c6f28ad90b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14944
94724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1494494724
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.273338380
Short name T1384
Test name
Test status
Simulation time 159773277 ps
CPU time 0.81 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206188 kb
Host smart-d17197eb-f25f-48be-84d0-95a801a7d3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27333
8380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.273338380
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3817618204
Short name T507
Test name
Test status
Simulation time 207250156 ps
CPU time 0.95 seconds
Started Jun 29 06:35:42 PM PDT 24
Finished Jun 29 06:35:43 PM PDT 24
Peak memory 206216 kb
Host smart-b278ff57-529b-44ee-ba8c-82e30e51ea6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
18204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3817618204
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2643193171
Short name T1985
Test name
Test status
Simulation time 5881780433 ps
CPU time 52.42 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:36:38 PM PDT 24
Peak memory 206412 kb
Host smart-d04f5911-d2eb-40a6-b2e0-c5fee93ee8e4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2643193171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2643193171
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.546307562
Short name T2371
Test name
Test status
Simulation time 233923658 ps
CPU time 0.86 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206220 kb
Host smart-f408c2bc-7930-41a9-8d54-67e926ad116e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54630
7562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.546307562
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.4203306764
Short name T1317
Test name
Test status
Simulation time 167181155 ps
CPU time 0.8 seconds
Started Jun 29 06:35:51 PM PDT 24
Finished Jun 29 06:35:52 PM PDT 24
Peak memory 206196 kb
Host smart-b7c265cc-7104-41ef-aca4-4423df0b0843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42033
06764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.4203306764
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.399368386
Short name T1423
Test name
Test status
Simulation time 5416455980 ps
CPU time 158.58 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:38:24 PM PDT 24
Peak memory 206440 kb
Host smart-7ca19c88-ee34-448a-a98d-66f11d3e5976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39936
8386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.399368386
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.3456656251
Short name T2168
Test name
Test status
Simulation time 41150322 ps
CPU time 0.68 seconds
Started Jun 29 06:35:52 PM PDT 24
Finished Jun 29 06:35:54 PM PDT 24
Peak memory 206212 kb
Host smart-ff7f8f5a-4202-4723-890b-3098f2843dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3456656251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3456656251
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.671803345
Short name T1499
Test name
Test status
Simulation time 4039912876 ps
CPU time 4.67 seconds
Started Jun 29 06:35:52 PM PDT 24
Finished Jun 29 06:35:58 PM PDT 24
Peak memory 206308 kb
Host smart-c8e7e720-8dbf-4a37-bdf0-631e6e5695d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=671803345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.671803345
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2198544159
Short name T960
Test name
Test status
Simulation time 13335482424 ps
CPU time 12.32 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:14 PM PDT 24
Peak memory 206328 kb
Host smart-0ab1f9dc-7edc-4fdc-8223-748fd32d1510
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2198544159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2198544159
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3914694555
Short name T2602
Test name
Test status
Simulation time 23406767584 ps
CPU time 29.57 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:36:15 PM PDT 24
Peak memory 206436 kb
Host smart-6ef9a56d-5488-4ec2-b67d-c0f53dec57fb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3914694555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3914694555
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3275347887
Short name T538
Test name
Test status
Simulation time 176322533 ps
CPU time 0.87 seconds
Started Jun 29 06:35:49 PM PDT 24
Finished Jun 29 06:35:50 PM PDT 24
Peak memory 206368 kb
Host smart-543f5319-454f-4f29-bffc-a90285c6bfe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32753
47887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3275347887
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2811902382
Short name T456
Test name
Test status
Simulation time 173341112 ps
CPU time 0.81 seconds
Started Jun 29 06:35:51 PM PDT 24
Finished Jun 29 06:35:53 PM PDT 24
Peak memory 206192 kb
Host smart-efa1a873-d9b4-4432-b230-08bf4099777a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28119
02382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2811902382
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1548750554
Short name T2140
Test name
Test status
Simulation time 283053429 ps
CPU time 1.09 seconds
Started Jun 29 06:35:51 PM PDT 24
Finished Jun 29 06:35:52 PM PDT 24
Peak memory 206196 kb
Host smart-377151d4-2f35-4157-89a6-e7df1535899a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15487
50554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1548750554
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.501822193
Short name T2594
Test name
Test status
Simulation time 787638631 ps
CPU time 1.86 seconds
Started Jun 29 06:35:45 PM PDT 24
Finished Jun 29 06:35:48 PM PDT 24
Peak memory 206352 kb
Host smart-9020f26a-5960-4146-8b6e-3de447348976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50182
2193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.501822193
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.4171356719
Short name T2158
Test name
Test status
Simulation time 7915157386 ps
CPU time 15.61 seconds
Started Jun 29 06:35:44 PM PDT 24
Finished Jun 29 06:36:01 PM PDT 24
Peak memory 206408 kb
Host smart-7c8c38a2-2bb0-4dcb-b503-fbb867ccf913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41713
56719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.4171356719
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.1838530259
Short name T1048
Test name
Test status
Simulation time 449383107 ps
CPU time 1.39 seconds
Started Jun 29 06:35:50 PM PDT 24
Finished Jun 29 06:35:52 PM PDT 24
Peak memory 206200 kb
Host smart-5f3bfa10-6493-4ae7-a4b4-95b05ed3e42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18385
30259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.1838530259
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.4141076569
Short name T2331
Test name
Test status
Simulation time 165510403 ps
CPU time 0.8 seconds
Started Jun 29 06:35:51 PM PDT 24
Finished Jun 29 06:35:53 PM PDT 24
Peak memory 206192 kb
Host smart-fbbd9258-0075-43eb-97df-f12894136827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41410
76569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.4141076569
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.387457544
Short name T505
Test name
Test status
Simulation time 878202576 ps
CPU time 2.19 seconds
Started Jun 29 06:36:00 PM PDT 24
Finished Jun 29 06:36:03 PM PDT 24
Peak memory 206324 kb
Host smart-f34bc581-8185-4c49-88a0-6131555b9b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38745
7544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.387457544
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2884797236
Short name T1867
Test name
Test status
Simulation time 272234030 ps
CPU time 1.9 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206288 kb
Host smart-0147bf94-e5dc-4d4d-aaca-0978a446686f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28847
97236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2884797236
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.4145492134
Short name T1699
Test name
Test status
Simulation time 219177021 ps
CPU time 0.92 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:36:02 PM PDT 24
Peak memory 206196 kb
Host smart-b7bb2b01-806a-40cf-8432-dfa4d13144fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41454
92134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.4145492134
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.655093462
Short name T336
Test name
Test status
Simulation time 137376387 ps
CPU time 0.75 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206112 kb
Host smart-69489620-da0b-422f-b34e-ef0208bb5945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65509
3462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.655093462
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1380461629
Short name T1371
Test name
Test status
Simulation time 207193777 ps
CPU time 0.88 seconds
Started Jun 29 06:35:57 PM PDT 24
Finished Jun 29 06:35:59 PM PDT 24
Peak memory 206188 kb
Host smart-cc995ff9-edd3-4eed-8556-ffb50f95a267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13804
61629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1380461629
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3954343955
Short name T1865
Test name
Test status
Simulation time 5051876715 ps
CPU time 36.17 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:39 PM PDT 24
Peak memory 206444 kb
Host smart-90d0776a-7490-4c82-a2b1-31d5f2fa8a8f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3954343955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3954343955
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3159526293
Short name T408
Test name
Test status
Simulation time 223053896 ps
CPU time 0.91 seconds
Started Jun 29 06:35:56 PM PDT 24
Finished Jun 29 06:35:57 PM PDT 24
Peak memory 206196 kb
Host smart-1e3609ea-099c-4ffc-8d5d-87e09be5b831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31595
26293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3159526293
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.1355472264
Short name T49
Test name
Test status
Simulation time 23283883089 ps
CPU time 26.89 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:29 PM PDT 24
Peak memory 206320 kb
Host smart-0b4dab23-2331-4090-935d-f8dc31aaa872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13554
72264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.1355472264
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.1716984789
Short name T1748
Test name
Test status
Simulation time 3342026516 ps
CPU time 4.25 seconds
Started Jun 29 06:35:56 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206268 kb
Host smart-ef56492c-d309-40c5-91a5-c01909672804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17169
84789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1716984789
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.3794006093
Short name T642
Test name
Test status
Simulation time 9306553213 ps
CPU time 259.03 seconds
Started Jun 29 06:36:07 PM PDT 24
Finished Jun 29 06:40:27 PM PDT 24
Peak memory 206472 kb
Host smart-13cbe091-60a3-49d9-a051-5ccaa10306b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37940
06093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.3794006093
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3635550857
Short name T1318
Test name
Test status
Simulation time 7593942435 ps
CPU time 228.34 seconds
Started Jun 29 06:35:50 PM PDT 24
Finished Jun 29 06:39:39 PM PDT 24
Peak memory 206460 kb
Host smart-0654e41e-6f3d-4f47-b763-1b8abf168265
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3635550857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3635550857
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.4211644255
Short name T1802
Test name
Test status
Simulation time 240886257 ps
CPU time 0.88 seconds
Started Jun 29 06:35:51 PM PDT 24
Finished Jun 29 06:35:53 PM PDT 24
Peak memory 206216 kb
Host smart-4435a61e-f943-41c8-9b1d-5572d760ca6c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4211644255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.4211644255
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.51060871
Short name T791
Test name
Test status
Simulation time 241595350 ps
CPU time 0.94 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206216 kb
Host smart-fc6730fc-f01a-495e-93ae-887dde428886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51060
871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.51060871
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1040592432
Short name T1998
Test name
Test status
Simulation time 5670455850 ps
CPU time 151.21 seconds
Started Jun 29 06:35:52 PM PDT 24
Finished Jun 29 06:38:24 PM PDT 24
Peak memory 206432 kb
Host smart-fd016140-2007-43b0-8368-3b738bf10140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10405
92432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1040592432
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1986444318
Short name T468
Test name
Test status
Simulation time 4527219990 ps
CPU time 34.02 seconds
Started Jun 29 06:35:51 PM PDT 24
Finished Jun 29 06:36:26 PM PDT 24
Peak memory 206496 kb
Host smart-33c51a40-494d-46fd-9d52-98196d722b66
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1986444318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1986444318
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3535009893
Short name T2147
Test name
Test status
Simulation time 154076622 ps
CPU time 0.91 seconds
Started Jun 29 06:36:03 PM PDT 24
Finished Jun 29 06:36:05 PM PDT 24
Peak memory 206224 kb
Host smart-eedead9a-ce53-4654-b468-a0c593119070
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3535009893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3535009893
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.4253588265
Short name T343
Test name
Test status
Simulation time 171859790 ps
CPU time 0.78 seconds
Started Jun 29 06:36:00 PM PDT 24
Finished Jun 29 06:36:02 PM PDT 24
Peak memory 206180 kb
Host smart-48031819-a2f5-425a-8df2-f640251a494f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42535
88265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.4253588265
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3484215292
Short name T2609
Test name
Test status
Simulation time 172328125 ps
CPU time 0.84 seconds
Started Jun 29 06:35:55 PM PDT 24
Finished Jun 29 06:35:56 PM PDT 24
Peak memory 206040 kb
Host smart-25f36823-2df1-438d-9e06-4a8141f44527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34842
15292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3484215292
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.4005516725
Short name T1449
Test name
Test status
Simulation time 196222781 ps
CPU time 0.85 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206068 kb
Host smart-a45324d7-a2a2-4858-ad60-526631daf9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40055
16725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.4005516725
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1677949331
Short name T1418
Test name
Test status
Simulation time 242058587 ps
CPU time 0.91 seconds
Started Jun 29 06:36:00 PM PDT 24
Finished Jun 29 06:36:03 PM PDT 24
Peak memory 206164 kb
Host smart-ed9a93d4-f70d-4758-8165-1935133c18c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16779
49331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1677949331
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2910029057
Short name T755
Test name
Test status
Simulation time 147858125 ps
CPU time 0.86 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206200 kb
Host smart-906debaf-559a-4e8c-aed5-6b4521541078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29100
29057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2910029057
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2890248701
Short name T2019
Test name
Test status
Simulation time 252947582 ps
CPU time 1.08 seconds
Started Jun 29 06:36:02 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206224 kb
Host smart-7d9cb3e9-ae94-44fd-a638-a4641e95b0e7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2890248701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2890248701
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2549847825
Short name T1900
Test name
Test status
Simulation time 144109914 ps
CPU time 0.77 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206216 kb
Host smart-07ee6d61-5352-423f-9298-46ab6518444d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25498
47825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2549847825
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2511421916
Short name T40
Test name
Test status
Simulation time 39198565 ps
CPU time 0.66 seconds
Started Jun 29 06:35:52 PM PDT 24
Finished Jun 29 06:35:54 PM PDT 24
Peak memory 206184 kb
Host smart-96ca6bb1-c7ef-47ef-a5de-3ac6d7ccad16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25114
21916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2511421916
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2936140869
Short name T2107
Test name
Test status
Simulation time 17595011752 ps
CPU time 37.69 seconds
Started Jun 29 06:35:50 PM PDT 24
Finished Jun 29 06:36:28 PM PDT 24
Peak memory 206468 kb
Host smart-1215fa3f-19c5-40d8-aa56-4c0c214f90e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29361
40869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2936140869
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1611311252
Short name T1886
Test name
Test status
Simulation time 166810703 ps
CPU time 0.85 seconds
Started Jun 29 06:35:51 PM PDT 24
Finished Jun 29 06:35:52 PM PDT 24
Peak memory 206160 kb
Host smart-dbbdde9f-1628-4c23-b0aa-099a08f76444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16113
11252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1611311252
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.4219852989
Short name T1926
Test name
Test status
Simulation time 202982423 ps
CPU time 0.93 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206156 kb
Host smart-703300aa-a6ea-46eb-8a40-b72662cba133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42198
52989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.4219852989
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.1530995555
Short name T425
Test name
Test status
Simulation time 248515533 ps
CPU time 0.9 seconds
Started Jun 29 06:35:52 PM PDT 24
Finished Jun 29 06:35:54 PM PDT 24
Peak memory 206128 kb
Host smart-e23c6b74-9d98-4c86-8b63-1b1329944abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15309
95555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1530995555
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.4193330835
Short name T722
Test name
Test status
Simulation time 146314907 ps
CPU time 0.74 seconds
Started Jun 29 06:35:50 PM PDT 24
Finished Jun 29 06:35:51 PM PDT 24
Peak memory 206200 kb
Host smart-084dc866-1ecf-4b86-81e5-54fd1a642bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41933
30835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.4193330835
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2320229527
Short name T2196
Test name
Test status
Simulation time 161158692 ps
CPU time 0.82 seconds
Started Jun 29 06:35:50 PM PDT 24
Finished Jun 29 06:35:51 PM PDT 24
Peak memory 206200 kb
Host smart-5a327328-e672-4cea-b78d-f6afbb4c6913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
29527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2320229527
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2848364729
Short name T2407
Test name
Test status
Simulation time 164147641 ps
CPU time 0.8 seconds
Started Jun 29 06:35:50 PM PDT 24
Finished Jun 29 06:35:52 PM PDT 24
Peak memory 206196 kb
Host smart-e6242481-e082-41d7-91bc-3d3a2b4b533e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28483
64729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2848364729
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3901719382
Short name T2529
Test name
Test status
Simulation time 144047094 ps
CPU time 0.73 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:36:01 PM PDT 24
Peak memory 206196 kb
Host smart-39f18a84-a870-4d0e-9eba-40760150ecb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39017
19382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3901719382
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2167019497
Short name T2134
Test name
Test status
Simulation time 226128580 ps
CPU time 0.94 seconds
Started Jun 29 06:35:55 PM PDT 24
Finished Jun 29 06:35:57 PM PDT 24
Peak memory 206208 kb
Host smart-a2cf29e1-abc7-4322-8ed6-e69c8d336c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21670
19497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2167019497
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2634644775
Short name T2411
Test name
Test status
Simulation time 4494972007 ps
CPU time 33.66 seconds
Started Jun 29 06:35:52 PM PDT 24
Finished Jun 29 06:36:26 PM PDT 24
Peak memory 206428 kb
Host smart-3cd621a4-e06d-4e09-9771-25b8e59a8853
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2634644775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2634644775
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.911412724
Short name T707
Test name
Test status
Simulation time 150398563 ps
CPU time 0.84 seconds
Started Jun 29 06:35:48 PM PDT 24
Finished Jun 29 06:35:49 PM PDT 24
Peak memory 206220 kb
Host smart-08adb83a-09d8-40a4-8aae-de81610bf267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91141
2724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.911412724
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.665285501
Short name T597
Test name
Test status
Simulation time 180778662 ps
CPU time 0.79 seconds
Started Jun 29 06:35:50 PM PDT 24
Finished Jun 29 06:35:52 PM PDT 24
Peak memory 206192 kb
Host smart-f2aafb23-cd8c-4339-9a62-aeae3a60384c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66528
5501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.665285501
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3669343229
Short name T88
Test name
Test status
Simulation time 3025913143 ps
CPU time 83.33 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:37:23 PM PDT 24
Peak memory 206440 kb
Host smart-b506732f-9004-4d6a-a402-8ce88ca8a94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36693
43229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3669343229
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2072841511
Short name T1685
Test name
Test status
Simulation time 72384642 ps
CPU time 0.69 seconds
Started Jun 29 06:35:57 PM PDT 24
Finished Jun 29 06:35:58 PM PDT 24
Peak memory 206212 kb
Host smart-c67786fd-01f0-48a6-ab4d-3fcb5b6694c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2072841511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2072841511
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.162056518
Short name T2000
Test name
Test status
Simulation time 3709230792 ps
CPU time 4.48 seconds
Started Jun 29 06:36:00 PM PDT 24
Finished Jun 29 06:36:06 PM PDT 24
Peak memory 206404 kb
Host smart-1863fafd-8bc6-4687-bef5-f7b243d88ee4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=162056518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.162056518
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2167240597
Short name T1877
Test name
Test status
Simulation time 13425921253 ps
CPU time 11.89 seconds
Started Jun 29 06:36:09 PM PDT 24
Finished Jun 29 06:36:22 PM PDT 24
Peak memory 206404 kb
Host smart-0b6be999-5dc1-4a13-8eca-85b4fe57cf9b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2167240597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2167240597
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.79333219
Short name T1338
Test name
Test status
Simulation time 23390453008 ps
CPU time 23.44 seconds
Started Jun 29 06:36:00 PM PDT 24
Finished Jun 29 06:36:25 PM PDT 24
Peak memory 206340 kb
Host smart-be956f61-b9c5-4942-a54c-142dd2324cc2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=79333219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.79333219
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2743081198
Short name T1583
Test name
Test status
Simulation time 162778509 ps
CPU time 0.8 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:03 PM PDT 24
Peak memory 206160 kb
Host smart-e7c11d2c-965d-4eab-837d-fcf7ec2a12a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27430
81198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2743081198
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3297374439
Short name T1795
Test name
Test status
Simulation time 162688823 ps
CPU time 0.77 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206200 kb
Host smart-8080848c-9958-43c6-aca1-b29294832a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32973
74439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3297374439
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1026560269
Short name T1937
Test name
Test status
Simulation time 604410192 ps
CPU time 1.59 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206316 kb
Host smart-6ae2ef31-a50c-4791-a77a-3ae2ecd01be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10265
60269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1026560269
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3527265575
Short name T548
Test name
Test status
Simulation time 475736753 ps
CPU time 1.41 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206196 kb
Host smart-67f54b69-a3f1-4620-bd13-ed38a28bb90f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35272
65575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3527265575
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3354655454
Short name T993
Test name
Test status
Simulation time 331909742 ps
CPU time 1.13 seconds
Started Jun 29 06:36:03 PM PDT 24
Finished Jun 29 06:36:06 PM PDT 24
Peak memory 206180 kb
Host smart-4e0d27ce-2c39-4786-9a08-a3047db7a4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33546
55454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3354655454
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1672693611
Short name T1550
Test name
Test status
Simulation time 141887408 ps
CPU time 0.79 seconds
Started Jun 29 06:36:14 PM PDT 24
Finished Jun 29 06:36:15 PM PDT 24
Peak memory 206184 kb
Host smart-b17099dd-49d3-4e80-b75d-4b1705ceaa92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16726
93611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1672693611
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.2529310268
Short name T631
Test name
Test status
Simulation time 33833920 ps
CPU time 0.7 seconds
Started Jun 29 06:36:11 PM PDT 24
Finished Jun 29 06:36:12 PM PDT 24
Peak memory 206192 kb
Host smart-581f3db3-1392-4e06-a401-18597e57bf77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25293
10268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2529310268
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.3731697105
Short name T357
Test name
Test status
Simulation time 1068765624 ps
CPU time 2.55 seconds
Started Jun 29 06:36:03 PM PDT 24
Finished Jun 29 06:36:06 PM PDT 24
Peak memory 206324 kb
Host smart-c7192f84-501c-4e27-8599-d57e45659da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37316
97105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3731697105
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.741967687
Short name T629
Test name
Test status
Simulation time 219811304 ps
CPU time 1.52 seconds
Started Jun 29 06:36:02 PM PDT 24
Finished Jun 29 06:36:05 PM PDT 24
Peak memory 206324 kb
Host smart-6adaf8ca-25ae-4134-926a-76c68101d9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74196
7687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.741967687
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3980208793
Short name T2550
Test name
Test status
Simulation time 209521785 ps
CPU time 0.92 seconds
Started Jun 29 06:36:02 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206204 kb
Host smart-c230b9fb-b721-452d-96e6-6eeecec42a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39802
08793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3980208793
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3093212019
Short name T621
Test name
Test status
Simulation time 131917884 ps
CPU time 0.74 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:35:59 PM PDT 24
Peak memory 206216 kb
Host smart-a3f232af-0feb-4a7d-80d6-1de759d28710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30932
12019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3093212019
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4168184449
Short name T2226
Test name
Test status
Simulation time 226472963 ps
CPU time 0.87 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:03 PM PDT 24
Peak memory 206216 kb
Host smart-60e47add-f238-43b7-90dd-82e7eda08798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41681
84449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4168184449
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2371711312
Short name T1419
Test name
Test status
Simulation time 200742895 ps
CPU time 0.89 seconds
Started Jun 29 06:36:04 PM PDT 24
Finished Jun 29 06:36:06 PM PDT 24
Peak memory 206196 kb
Host smart-6b21e6bc-b985-48ac-a8d3-3289b963b0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23717
11312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2371711312
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.2550828603
Short name T344
Test name
Test status
Simulation time 23308617498 ps
CPU time 22.91 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:21 PM PDT 24
Peak memory 206224 kb
Host smart-9facdbd9-1f8c-40cd-9715-feb90852a581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25508
28603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.2550828603
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2582048263
Short name T1016
Test name
Test status
Simulation time 3310503450 ps
CPU time 4.14 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:03 PM PDT 24
Peak memory 206268 kb
Host smart-d0093344-38a1-4cac-a53c-794b0d7407d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25820
48263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2582048263
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.291210162
Short name T1656
Test name
Test status
Simulation time 8302972182 ps
CPU time 211.57 seconds
Started Jun 29 06:36:05 PM PDT 24
Finished Jun 29 06:39:38 PM PDT 24
Peak memory 206448 kb
Host smart-51978961-0388-459f-b28d-ce8052c06216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29121
0162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.291210162
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1366070594
Short name T665
Test name
Test status
Simulation time 5086464449 ps
CPU time 134.59 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:38:15 PM PDT 24
Peak memory 206428 kb
Host smart-1bab0e32-9299-4a24-8f1c-c6c21b1a5fea
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1366070594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1366070594
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1636060437
Short name T1339
Test name
Test status
Simulation time 258578989 ps
CPU time 0.93 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:36:02 PM PDT 24
Peak memory 206216 kb
Host smart-80ccd0f1-e67e-4347-9920-94b5d251d475
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1636060437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1636060437
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.643387026
Short name T1990
Test name
Test status
Simulation time 189845494 ps
CPU time 0.85 seconds
Started Jun 29 06:36:08 PM PDT 24
Finished Jun 29 06:36:09 PM PDT 24
Peak memory 206216 kb
Host smart-962ea776-3ada-48c1-8260-a5efe1280b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64338
7026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.643387026
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2317579645
Short name T1700
Test name
Test status
Simulation time 4907875553 ps
CPU time 38.1 seconds
Started Jun 29 06:36:05 PM PDT 24
Finished Jun 29 06:36:45 PM PDT 24
Peak memory 206508 kb
Host smart-7b1a5bf4-1beb-4a98-8d8b-8f34b77201b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23175
79645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2317579645
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1346760801
Short name T2307
Test name
Test status
Simulation time 6159464970 ps
CPU time 46 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:36:47 PM PDT 24
Peak memory 206396 kb
Host smart-1744a031-2505-4584-8621-d2872034f63e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1346760801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1346760801
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.322261460
Short name T1890
Test name
Test status
Simulation time 163926758 ps
CPU time 0.82 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206220 kb
Host smart-44693acc-8b8d-4314-b764-27980518120a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=322261460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.322261460
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.487341783
Short name T2424
Test name
Test status
Simulation time 144654176 ps
CPU time 0.84 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206216 kb
Host smart-0b9153a0-03c4-4510-b64e-671f97eaf7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48734
1783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.487341783
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1740656382
Short name T1723
Test name
Test status
Simulation time 151426180 ps
CPU time 0.79 seconds
Started Jun 29 06:36:03 PM PDT 24
Finished Jun 29 06:36:05 PM PDT 24
Peak memory 206168 kb
Host smart-d1b7c832-24b0-47da-8441-30151ad008cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17406
56382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1740656382
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3807695418
Short name T1898
Test name
Test status
Simulation time 201266956 ps
CPU time 0.9 seconds
Started Jun 29 06:36:03 PM PDT 24
Finished Jun 29 06:36:06 PM PDT 24
Peak memory 206196 kb
Host smart-a77745d6-be96-43cc-b671-51c0ac48c532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38076
95418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3807695418
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2838518043
Short name T418
Test name
Test status
Simulation time 160688439 ps
CPU time 0.81 seconds
Started Jun 29 06:36:06 PM PDT 24
Finished Jun 29 06:36:08 PM PDT 24
Peak memory 206196 kb
Host smart-b8b971d5-c705-4c85-868c-d23cbd9319bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28385
18043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2838518043
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3775787698
Short name T1805
Test name
Test status
Simulation time 180255516 ps
CPU time 0.8 seconds
Started Jun 29 06:36:00 PM PDT 24
Finished Jun 29 06:36:02 PM PDT 24
Peak memory 206200 kb
Host smart-9c144e9e-815a-45af-a9c6-040c222d3874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37757
87698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3775787698
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.32531471
Short name T1
Test name
Test status
Simulation time 242700817 ps
CPU time 0.96 seconds
Started Jun 29 06:36:02 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206216 kb
Host smart-52d44e40-d10d-4125-bbf0-3752c9f83b0c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=32531471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.32531471
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.612485348
Short name T1646
Test name
Test status
Simulation time 153667764 ps
CPU time 0.77 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206224 kb
Host smart-954ecc9a-eafd-4361-9790-c7e0d0d58aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61248
5348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.612485348
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.377223878
Short name T2441
Test name
Test status
Simulation time 40762329 ps
CPU time 0.67 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:03 PM PDT 24
Peak memory 206212 kb
Host smart-743df335-235f-4172-ae6b-4c0970b86e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37722
3878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.377223878
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2674388487
Short name T1150
Test name
Test status
Simulation time 13315311206 ps
CPU time 29.47 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:29 PM PDT 24
Peak memory 206488 kb
Host smart-063555b8-8103-4fe0-aac8-6a143ecdf33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26743
88487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2674388487
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2930931687
Short name T2130
Test name
Test status
Simulation time 193726688 ps
CPU time 0.89 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206196 kb
Host smart-6224193f-7bab-47fc-a4d9-d3fb23e34215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29309
31687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2930931687
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.340881851
Short name T2029
Test name
Test status
Simulation time 200656386 ps
CPU time 0.88 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206208 kb
Host smart-8a927c06-2e7b-4947-baab-9efee57869e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34088
1851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.340881851
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.956125583
Short name T1404
Test name
Test status
Simulation time 150597031 ps
CPU time 0.78 seconds
Started Jun 29 06:36:10 PM PDT 24
Finished Jun 29 06:36:11 PM PDT 24
Peak memory 206380 kb
Host smart-d3b43976-9b10-4a11-89fb-b30af27e0526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95612
5583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.956125583
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.263589660
Short name T2105
Test name
Test status
Simulation time 188217821 ps
CPU time 0.88 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206200 kb
Host smart-1f4f4c71-fb4d-41f2-a03c-9c3269cdb97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26358
9660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.263589660
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2745449563
Short name T1577
Test name
Test status
Simulation time 190918365 ps
CPU time 0.83 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:36:01 PM PDT 24
Peak memory 206200 kb
Host smart-d195394c-e61c-407f-b996-260172400835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27454
49563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2745449563
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2989940461
Short name T348
Test name
Test status
Simulation time 164151535 ps
CPU time 0.83 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206192 kb
Host smart-24e2afca-f2f9-477e-b31a-49024123fb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29899
40461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2989940461
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.700027105
Short name T929
Test name
Test status
Simulation time 206156421 ps
CPU time 0.85 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206112 kb
Host smart-78820263-9fcd-440f-a057-9ec298ee294d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70002
7105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.700027105
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2933931271
Short name T767
Test name
Test status
Simulation time 198168678 ps
CPU time 0.91 seconds
Started Jun 29 06:36:02 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206216 kb
Host smart-1df68545-b250-4fb9-a5fe-609b262d33d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29339
31271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2933931271
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.377816704
Short name T857
Test name
Test status
Simulation time 3583943004 ps
CPU time 33.17 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:36:34 PM PDT 24
Peak memory 206448 kb
Host smart-5a66540b-a76c-4aa7-ad1f-1beb0d7b2de7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=377816704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.377816704
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1419751034
Short name T1261
Test name
Test status
Simulation time 186906057 ps
CPU time 0.84 seconds
Started Jun 29 06:36:04 PM PDT 24
Finished Jun 29 06:36:06 PM PDT 24
Peak memory 206372 kb
Host smart-ea200cb8-5772-44b9-a907-dabbf3153d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14197
51034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1419751034
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2191163978
Short name T400
Test name
Test status
Simulation time 144911018 ps
CPU time 0.75 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206216 kb
Host smart-5fc1b2c3-4bb8-48c1-97f6-482713e7d5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21911
63978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2191163978
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.1839354509
Short name T1715
Test name
Test status
Simulation time 3861803796 ps
CPU time 101.81 seconds
Started Jun 29 06:35:57 PM PDT 24
Finished Jun 29 06:37:39 PM PDT 24
Peak memory 206440 kb
Host smart-95cb1088-6867-4f48-84d9-ede17cfc6bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18393
54509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1839354509
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.129482176
Short name T1405
Test name
Test status
Simulation time 36612268 ps
CPU time 0.7 seconds
Started Jun 29 06:36:15 PM PDT 24
Finished Jun 29 06:36:16 PM PDT 24
Peak memory 206188 kb
Host smart-488437ec-9160-40be-846c-f3839be0cb3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=129482176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.129482176
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1336865584
Short name T1027
Test name
Test status
Simulation time 3634081023 ps
CPU time 4.09 seconds
Started Jun 29 06:36:14 PM PDT 24
Finished Jun 29 06:36:18 PM PDT 24
Peak memory 206264 kb
Host smart-d4093724-72bf-4075-a156-0dc4c31d667b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1336865584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1336865584
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.242081519
Short name T2030
Test name
Test status
Simulation time 13512831204 ps
CPU time 13.3 seconds
Started Jun 29 06:36:06 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 206488 kb
Host smart-f560d018-1b26-4606-b844-8c71477a950f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=242081519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.242081519
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2502081986
Short name T1460
Test name
Test status
Simulation time 23493379567 ps
CPU time 22.95 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:25 PM PDT 24
Peak memory 206452 kb
Host smart-e046069b-2606-40d4-9d8e-d050bffd7c9a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2502081986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2502081986
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2754509939
Short name T1433
Test name
Test status
Simulation time 165617149 ps
CPU time 0.85 seconds
Started Jun 29 06:35:58 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 206184 kb
Host smart-8a45b3df-be41-49bd-8273-c6764e544451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27545
09939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2754509939
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1967550093
Short name T389
Test name
Test status
Simulation time 157799008 ps
CPU time 0.81 seconds
Started Jun 29 06:36:09 PM PDT 24
Finished Jun 29 06:36:11 PM PDT 24
Peak memory 206192 kb
Host smart-ae21bf37-f8b0-4f4d-9913-6e20d09bf7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19675
50093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1967550093
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.385340885
Short name T1587
Test name
Test status
Simulation time 262431924 ps
CPU time 1.07 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:03 PM PDT 24
Peak memory 206200 kb
Host smart-75926791-2b81-4394-a35d-54b7dbfe486d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38534
0885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.385340885
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.3273361905
Short name T2528
Test name
Test status
Simulation time 469174933 ps
CPU time 1.31 seconds
Started Jun 29 06:36:13 PM PDT 24
Finished Jun 29 06:36:15 PM PDT 24
Peak memory 206188 kb
Host smart-dcd37a44-0191-4aae-ad15-bc49f9300a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32733
61905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.3273361905
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.3265238728
Short name T99
Test name
Test status
Simulation time 15896011786 ps
CPU time 30.63 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 206504 kb
Host smart-c675639f-fba9-4ff4-acdf-b1c3edb335ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32652
38728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3265238728
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2609722867
Short name T377
Test name
Test status
Simulation time 433798427 ps
CPU time 1.42 seconds
Started Jun 29 06:36:01 PM PDT 24
Finished Jun 29 06:36:04 PM PDT 24
Peak memory 206196 kb
Host smart-adae36c9-291a-4c79-a845-68edc8526c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26097
22867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2609722867
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1995075440
Short name T54
Test name
Test status
Simulation time 137433999 ps
CPU time 0.77 seconds
Started Jun 29 06:36:05 PM PDT 24
Finished Jun 29 06:36:07 PM PDT 24
Peak memory 206172 kb
Host smart-42f293bd-f046-4949-92ec-3df858d21583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19950
75440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1995075440
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.905916589
Short name T968
Test name
Test status
Simulation time 50368891 ps
CPU time 0.67 seconds
Started Jun 29 06:35:59 PM PDT 24
Finished Jun 29 06:36:02 PM PDT 24
Peak memory 206156 kb
Host smart-a676cc03-a684-4732-a2e8-310bdc7bea8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90591
6589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.905916589
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.4182697258
Short name T1000
Test name
Test status
Simulation time 742288023 ps
CPU time 1.82 seconds
Started Jun 29 06:36:14 PM PDT 24
Finished Jun 29 06:36:16 PM PDT 24
Peak memory 206372 kb
Host smart-1399a77f-e848-484d-a030-3af8d0c653c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41826
97258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.4182697258
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.293049559
Short name T1731
Test name
Test status
Simulation time 285360338 ps
CPU time 1.84 seconds
Started Jun 29 06:36:05 PM PDT 24
Finished Jun 29 06:36:08 PM PDT 24
Peak memory 206248 kb
Host smart-3ce59374-9282-4def-b1c8-eafa1d74d97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29304
9559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.293049559
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.4172754357
Short name T691
Test name
Test status
Simulation time 182227663 ps
CPU time 0.91 seconds
Started Jun 29 06:36:18 PM PDT 24
Finished Jun 29 06:36:19 PM PDT 24
Peak memory 206168 kb
Host smart-40339599-fd0a-4602-bb9e-a046a345b9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41727
54357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.4172754357
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.4081001199
Short name T773
Test name
Test status
Simulation time 161175029 ps
CPU time 0.78 seconds
Started Jun 29 06:36:07 PM PDT 24
Finished Jun 29 06:36:09 PM PDT 24
Peak memory 206212 kb
Host smart-2c87641a-952d-4c4a-b0af-1e486ea36f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40810
01199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.4081001199
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1549407230
Short name T1861
Test name
Test status
Simulation time 240322329 ps
CPU time 0.96 seconds
Started Jun 29 06:36:14 PM PDT 24
Finished Jun 29 06:36:15 PM PDT 24
Peak memory 206368 kb
Host smart-db40e093-653f-453f-90ba-d1dd4b88d11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15494
07230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1549407230
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.669018128
Short name T1855
Test name
Test status
Simulation time 4733449056 ps
CPU time 129.52 seconds
Started Jun 29 06:36:14 PM PDT 24
Finished Jun 29 06:38:24 PM PDT 24
Peak memory 206480 kb
Host smart-5f7ef000-d2c1-40e3-accf-46641ffc9b52
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=669018128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.669018128
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3262547204
Short name T943
Test name
Test status
Simulation time 212696970 ps
CPU time 0.88 seconds
Started Jun 29 06:36:14 PM PDT 24
Finished Jun 29 06:36:15 PM PDT 24
Peak memory 206196 kb
Host smart-089d38f0-236f-4d54-8a1d-d9372f489341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32625
47204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3262547204
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2572054909
Short name T1912
Test name
Test status
Simulation time 23278058353 ps
CPU time 23.67 seconds
Started Jun 29 06:36:11 PM PDT 24
Finished Jun 29 06:36:36 PM PDT 24
Peak memory 206312 kb
Host smart-18cd3224-c1d0-4b9b-8eb4-984ba4d4075c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25720
54909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2572054909
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3144309951
Short name T944
Test name
Test status
Simulation time 3283794379 ps
CPU time 3.93 seconds
Started Jun 29 06:36:05 PM PDT 24
Finished Jun 29 06:36:10 PM PDT 24
Peak memory 206232 kb
Host smart-e73e70f9-4e72-4be5-922e-fcdb2ca9acb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31443
09951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3144309951
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3921090731
Short name T2480
Test name
Test status
Simulation time 10861837519 ps
CPU time 76.51 seconds
Started Jun 29 06:36:13 PM PDT 24
Finished Jun 29 06:37:30 PM PDT 24
Peak memory 206464 kb
Host smart-85594529-277a-413d-8241-b1d52af6fbb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39210
90731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3921090731
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2613656460
Short name T2035
Test name
Test status
Simulation time 5363081877 ps
CPU time 39.01 seconds
Started Jun 29 06:36:05 PM PDT 24
Finished Jun 29 06:36:46 PM PDT 24
Peak memory 206472 kb
Host smart-1ab7578b-2c56-458e-93d8-78e9bdca0936
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2613656460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2613656460
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3837343841
Short name T1390
Test name
Test status
Simulation time 237521274 ps
CPU time 1.01 seconds
Started Jun 29 06:36:04 PM PDT 24
Finished Jun 29 06:36:07 PM PDT 24
Peak memory 206196 kb
Host smart-14a4761b-e18a-4eef-a97b-906e922bc449
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3837343841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3837343841
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3221373112
Short name T372
Test name
Test status
Simulation time 194205528 ps
CPU time 0.9 seconds
Started Jun 29 06:36:04 PM PDT 24
Finished Jun 29 06:36:07 PM PDT 24
Peak memory 206216 kb
Host smart-a57935b1-8043-4fc2-8d88-da047ec58c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32213
73112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3221373112
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.4132350540
Short name T155
Test name
Test status
Simulation time 4264712432 ps
CPU time 117.05 seconds
Started Jun 29 06:36:13 PM PDT 24
Finished Jun 29 06:38:11 PM PDT 24
Peak memory 206412 kb
Host smart-ab428095-4df3-404a-ad51-265e71a99cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41323
50540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.4132350540
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2252564166
Short name T2235
Test name
Test status
Simulation time 6675124648 ps
CPU time 178.17 seconds
Started Jun 29 06:36:04 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206460 kb
Host smart-87f74a2f-c3ff-42df-91ca-b9ea49963d53
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2252564166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2252564166
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3104423471
Short name T2100
Test name
Test status
Simulation time 192520299 ps
CPU time 0.83 seconds
Started Jun 29 06:36:06 PM PDT 24
Finished Jun 29 06:36:08 PM PDT 24
Peak memory 206196 kb
Host smart-6ee5aa33-a4d9-4271-ac8a-6e2fa68407fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3104423471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3104423471
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1954824032
Short name T681
Test name
Test status
Simulation time 172643285 ps
CPU time 0.88 seconds
Started Jun 29 06:36:05 PM PDT 24
Finished Jun 29 06:36:07 PM PDT 24
Peak memory 206212 kb
Host smart-4efb380a-0c3b-4ddb-9615-aeaab97c01c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548
24032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1954824032
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2561587124
Short name T136
Test name
Test status
Simulation time 238743828 ps
CPU time 0.93 seconds
Started Jun 29 06:36:09 PM PDT 24
Finished Jun 29 06:36:11 PM PDT 24
Peak memory 206216 kb
Host smart-b83787cb-44d6-4a1c-b2d8-bb03183fc713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25615
87124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2561587124
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2478156759
Short name T667
Test name
Test status
Simulation time 175665765 ps
CPU time 0.9 seconds
Started Jun 29 06:36:08 PM PDT 24
Finished Jun 29 06:36:10 PM PDT 24
Peak memory 206148 kb
Host smart-15fbfde9-1ca1-4724-8fc4-76df6a257f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24781
56759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2478156759
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2607344779
Short name T2167
Test name
Test status
Simulation time 185189993 ps
CPU time 0.78 seconds
Started Jun 29 06:36:11 PM PDT 24
Finished Jun 29 06:36:12 PM PDT 24
Peak memory 206144 kb
Host smart-ff33c7da-b516-48ba-90a5-349ee50b156f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26073
44779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2607344779
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2768286777
Short name T1511
Test name
Test status
Simulation time 174143400 ps
CPU time 0.8 seconds
Started Jun 29 06:36:12 PM PDT 24
Finished Jun 29 06:36:13 PM PDT 24
Peak memory 206172 kb
Host smart-3de2d547-5bcf-4cb1-85eb-f51e4db89e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27682
86777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2768286777
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.726596124
Short name T1668
Test name
Test status
Simulation time 173995520 ps
CPU time 0.77 seconds
Started Jun 29 06:36:20 PM PDT 24
Finished Jun 29 06:36:21 PM PDT 24
Peak memory 206168 kb
Host smart-56749711-611a-4939-955e-dd23dfc71e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72659
6124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.726596124
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1801775080
Short name T841
Test name
Test status
Simulation time 241653239 ps
CPU time 0.95 seconds
Started Jun 29 06:36:11 PM PDT 24
Finished Jun 29 06:36:13 PM PDT 24
Peak memory 206216 kb
Host smart-dc172efd-3960-4b2d-8a3f-0cd56d690f3c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1801775080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1801775080
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2856103452
Short name T978
Test name
Test status
Simulation time 165816674 ps
CPU time 0.85 seconds
Started Jun 29 06:36:05 PM PDT 24
Finished Jun 29 06:36:07 PM PDT 24
Peak memory 206204 kb
Host smart-dfceef6f-e32f-485b-bcf2-e5400beb9207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28561
03452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2856103452
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1616161761
Short name T687
Test name
Test status
Simulation time 36399553 ps
CPU time 0.67 seconds
Started Jun 29 06:36:05 PM PDT 24
Finished Jun 29 06:36:07 PM PDT 24
Peak memory 206204 kb
Host smart-8d9b8eca-c6b0-4e84-b9a8-3d787232c74e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16161
61761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1616161761
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3425773597
Short name T52
Test name
Test status
Simulation time 8671881856 ps
CPU time 24.04 seconds
Started Jun 29 06:36:08 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 206428 kb
Host smart-d36c94a4-d961-4e07-b1ed-4dfc2ce45356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34257
73597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3425773597
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1505081939
Short name T973
Test name
Test status
Simulation time 178905999 ps
CPU time 0.86 seconds
Started Jun 29 06:36:08 PM PDT 24
Finished Jun 29 06:36:10 PM PDT 24
Peak memory 206132 kb
Host smart-664d405d-947c-45c6-bd2a-02f047270767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15050
81939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1505081939
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.109889
Short name T1991
Test name
Test status
Simulation time 190006613 ps
CPU time 0.84 seconds
Started Jun 29 06:36:14 PM PDT 24
Finished Jun 29 06:36:16 PM PDT 24
Peak memory 206212 kb
Host smart-50db9f8b-255d-4cb2-b512-9f684f196dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10988
9 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.109889
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1224046571
Short name T1019
Test name
Test status
Simulation time 260976039 ps
CPU time 0.91 seconds
Started Jun 29 06:36:04 PM PDT 24
Finished Jun 29 06:36:07 PM PDT 24
Peak memory 206212 kb
Host smart-0cd6cbe3-c131-47cc-8319-6bbae4d71048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12240
46571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1224046571
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3876709695
Short name T1420
Test name
Test status
Simulation time 160235709 ps
CPU time 0.85 seconds
Started Jun 29 06:36:07 PM PDT 24
Finished Jun 29 06:36:09 PM PDT 24
Peak memory 206076 kb
Host smart-3b91928f-ee88-4927-b0d0-8c0e4b50cbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38767
09695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3876709695
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2249047120
Short name T949
Test name
Test status
Simulation time 182901234 ps
CPU time 0.86 seconds
Started Jun 29 06:36:04 PM PDT 24
Finished Jun 29 06:36:06 PM PDT 24
Peak memory 206200 kb
Host smart-4bf7af65-b1e6-4ff3-953d-fdfd2b9dacf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22490
47120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2249047120
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3137102295
Short name T411
Test name
Test status
Simulation time 153469389 ps
CPU time 0.77 seconds
Started Jun 29 06:36:11 PM PDT 24
Finished Jun 29 06:36:12 PM PDT 24
Peak memory 206208 kb
Host smart-dd5697cc-ba0b-4006-ab91-5313ef04b056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31371
02295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3137102295
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1877405879
Short name T2155
Test name
Test status
Simulation time 157553412 ps
CPU time 0.84 seconds
Started Jun 29 06:36:04 PM PDT 24
Finished Jun 29 06:36:06 PM PDT 24
Peak memory 206196 kb
Host smart-285cef1a-b044-4000-aaaf-f6ef3536940a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18774
05879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1877405879
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2629754288
Short name T35
Test name
Test status
Simulation time 219960565 ps
CPU time 0.96 seconds
Started Jun 29 06:36:06 PM PDT 24
Finished Jun 29 06:36:08 PM PDT 24
Peak memory 206192 kb
Host smart-d02a8285-e5dd-4972-8024-63f5517420b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26297
54288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2629754288
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.4256117337
Short name T1631
Test name
Test status
Simulation time 5728681020 ps
CPU time 43.31 seconds
Started Jun 29 06:36:08 PM PDT 24
Finished Jun 29 06:36:52 PM PDT 24
Peak memory 206396 kb
Host smart-c6ee64bc-a544-4e6b-9ab0-1325fa9c594c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4256117337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.4256117337
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3140943869
Short name T1091
Test name
Test status
Simulation time 162190006 ps
CPU time 0.83 seconds
Started Jun 29 06:36:05 PM PDT 24
Finished Jun 29 06:36:07 PM PDT 24
Peak memory 206224 kb
Host smart-d2a12ddd-8ee2-40b7-a251-98f908734c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31409
43869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3140943869
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1544408700
Short name T385
Test name
Test status
Simulation time 169109157 ps
CPU time 0.84 seconds
Started Jun 29 06:36:03 PM PDT 24
Finished Jun 29 06:36:05 PM PDT 24
Peak memory 206196 kb
Host smart-1b82090a-97a3-4a51-b2fc-a831eb080dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15444
08700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1544408700
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.891382738
Short name T2531
Test name
Test status
Simulation time 7301855087 ps
CPU time 205.25 seconds
Started Jun 29 06:36:07 PM PDT 24
Finished Jun 29 06:39:33 PM PDT 24
Peak memory 206308 kb
Host smart-71f8176a-0af3-47b5-a34c-2f64cdc992f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89138
2738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.891382738
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.3078290325
Short name T916
Test name
Test status
Simulation time 91277794 ps
CPU time 0.75 seconds
Started Jun 29 06:36:28 PM PDT 24
Finished Jun 29 06:36:30 PM PDT 24
Peak memory 206212 kb
Host smart-bb5ab7cd-2481-46e0-a1a0-ca7859caaf75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3078290325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.3078290325
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3009657912
Short name T762
Test name
Test status
Simulation time 4391270576 ps
CPU time 5.15 seconds
Started Jun 29 06:36:16 PM PDT 24
Finished Jun 29 06:36:21 PM PDT 24
Peak memory 206456 kb
Host smart-6f3f8ff1-b65f-4049-833d-fa585d47c9e7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3009657912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3009657912
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2788447823
Short name T2007
Test name
Test status
Simulation time 13356460797 ps
CPU time 12.75 seconds
Started Jun 29 06:36:11 PM PDT 24
Finished Jun 29 06:36:24 PM PDT 24
Peak memory 206340 kb
Host smart-ec645eb2-c988-43fa-9102-ede6871ca0d7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2788447823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2788447823
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3429749481
Short name T1089
Test name
Test status
Simulation time 23331544993 ps
CPU time 21.44 seconds
Started Jun 29 06:36:13 PM PDT 24
Finished Jun 29 06:36:35 PM PDT 24
Peak memory 206476 kb
Host smart-a7f99012-d3f5-48f7-9e3c-e864c4bf05b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3429749481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3429749481
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2569068957
Short name T541
Test name
Test status
Simulation time 150378755 ps
CPU time 0.79 seconds
Started Jun 29 06:36:09 PM PDT 24
Finished Jun 29 06:36:10 PM PDT 24
Peak memory 206200 kb
Host smart-67288bad-8dfd-4cd5-a5c6-43c1aaf5acd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690
68957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2569068957
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.2465173774
Short name T584
Test name
Test status
Simulation time 208345266 ps
CPU time 0.87 seconds
Started Jun 29 06:36:14 PM PDT 24
Finished Jun 29 06:36:16 PM PDT 24
Peak memory 206196 kb
Host smart-d3e3120e-6a44-46fd-bcc6-47ca05cc2714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24651
73774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.2465173774
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3485688833
Short name T2205
Test name
Test status
Simulation time 379935163 ps
CPU time 1.41 seconds
Started Jun 29 06:36:19 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 206172 kb
Host smart-6aee134f-bf91-4c7a-8cb7-a48c4507e52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34856
88833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3485688833
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.4006101705
Short name T1108
Test name
Test status
Simulation time 508200939 ps
CPU time 1.27 seconds
Started Jun 29 06:36:17 PM PDT 24
Finished Jun 29 06:36:18 PM PDT 24
Peak memory 206196 kb
Host smart-a66f0fd4-2ed8-45de-8a47-a27e6669d2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40061
01705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.4006101705
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.1359088902
Short name T1283
Test name
Test status
Simulation time 10020015927 ps
CPU time 19.23 seconds
Started Jun 29 06:36:23 PM PDT 24
Finished Jun 29 06:36:43 PM PDT 24
Peak memory 206492 kb
Host smart-769375f6-6f1b-4bd0-b58a-7bef0d7a8656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13590
88902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1359088902
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3571523124
Short name T2310
Test name
Test status
Simulation time 499355398 ps
CPU time 1.44 seconds
Started Jun 29 06:36:24 PM PDT 24
Finished Jun 29 06:36:26 PM PDT 24
Peak memory 206200 kb
Host smart-1b9af5b3-8582-43a8-bf4c-34304a2440a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35715
23124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3571523124
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3721666683
Short name T2242
Test name
Test status
Simulation time 148120438 ps
CPU time 0.8 seconds
Started Jun 29 06:36:13 PM PDT 24
Finished Jun 29 06:36:14 PM PDT 24
Peak memory 206196 kb
Host smart-5acc96c4-f9c5-4c22-9375-589f000a81dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37216
66683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3721666683
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2102796120
Short name T339
Test name
Test status
Simulation time 55078932 ps
CPU time 0.68 seconds
Started Jun 29 06:36:18 PM PDT 24
Finished Jun 29 06:36:19 PM PDT 24
Peak memory 206168 kb
Host smart-12e2754e-87e0-4fe9-a138-cbf7ae9e7745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21027
96120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2102796120
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2608411720
Short name T1972
Test name
Test status
Simulation time 805450009 ps
CPU time 2.04 seconds
Started Jun 29 06:36:18 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 206380 kb
Host smart-50cf34b1-f5ae-411f-a8a6-188c4e9cbaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26084
11720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2608411720
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.930580364
Short name T1648
Test name
Test status
Simulation time 184647135 ps
CPU time 1.65 seconds
Started Jun 29 06:36:18 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 206284 kb
Host smart-70122027-7a69-4ceb-953d-a1dbe454e126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93058
0364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.930580364
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2920901055
Short name T2372
Test name
Test status
Simulation time 209572352 ps
CPU time 0.89 seconds
Started Jun 29 06:36:18 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 206204 kb
Host smart-407fa3f8-7741-46c9-be34-736b5f3b9fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29209
01055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2920901055
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3651318049
Short name T1655
Test name
Test status
Simulation time 144423868 ps
CPU time 0.76 seconds
Started Jun 29 06:36:18 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 206168 kb
Host smart-4716ffe4-4d44-4274-83cc-b0f78ff1c5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36513
18049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3651318049
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.1347959122
Short name T2146
Test name
Test status
Simulation time 233911393 ps
CPU time 0.89 seconds
Started Jun 29 06:36:20 PM PDT 24
Finished Jun 29 06:36:22 PM PDT 24
Peak memory 206164 kb
Host smart-221d8ccc-086b-41d7-b8f7-114033bb4543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13479
59122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.1347959122
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1102232301
Short name T1232
Test name
Test status
Simulation time 23384665138 ps
CPU time 23.34 seconds
Started Jun 29 06:36:18 PM PDT 24
Finished Jun 29 06:36:42 PM PDT 24
Peak memory 206312 kb
Host smart-c34a1bb8-3c36-4147-80a1-6f8f44b28e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11022
32301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1102232301
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1874976942
Short name T1280
Test name
Test status
Simulation time 3323506615 ps
CPU time 3.95 seconds
Started Jun 29 06:36:12 PM PDT 24
Finished Jun 29 06:36:17 PM PDT 24
Peak memory 206252 kb
Host smart-5d8d21a5-acbe-4ff5-9761-654266186612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18749
76942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1874976942
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.1863876288
Short name T915
Test name
Test status
Simulation time 10361702985 ps
CPU time 296.24 seconds
Started Jun 29 06:36:12 PM PDT 24
Finished Jun 29 06:41:09 PM PDT 24
Peak memory 206472 kb
Host smart-4608de13-8547-453b-94d5-0688dac17b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18638
76288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.1863876288
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1957919098
Short name T2610
Test name
Test status
Simulation time 2699687512 ps
CPU time 71.94 seconds
Started Jun 29 06:36:22 PM PDT 24
Finished Jun 29 06:37:35 PM PDT 24
Peak memory 206460 kb
Host smart-50b7c299-af10-4fe4-a20d-f50b08d4e4e1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1957919098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1957919098
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2318760540
Short name T719
Test name
Test status
Simulation time 248921069 ps
CPU time 0.97 seconds
Started Jun 29 06:36:23 PM PDT 24
Finished Jun 29 06:36:24 PM PDT 24
Peak memory 206212 kb
Host smart-2909f1d5-e205-4618-9533-5503996f69ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2318760540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2318760540
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.4099751037
Short name T897
Test name
Test status
Simulation time 212299377 ps
CPU time 0.88 seconds
Started Jun 29 06:36:19 PM PDT 24
Finished Jun 29 06:36:21 PM PDT 24
Peak memory 206204 kb
Host smart-62d7b467-8ddf-4197-960d-ac8db82e1a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40997
51037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.4099751037
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3317840699
Short name T361
Test name
Test status
Simulation time 4874471850 ps
CPU time 34 seconds
Started Jun 29 06:36:13 PM PDT 24
Finished Jun 29 06:36:47 PM PDT 24
Peak memory 206420 kb
Host smart-c2a48cc8-858e-4fd3-9bb1-94419026053e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33178
40699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3317840699
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1231822639
Short name T753
Test name
Test status
Simulation time 5631784560 ps
CPU time 54 seconds
Started Jun 29 06:36:19 PM PDT 24
Finished Jun 29 06:37:13 PM PDT 24
Peak memory 206500 kb
Host smart-63db07d8-4bc9-4985-ac79-f674486c9642
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1231822639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1231822639
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.297170712
Short name T922
Test name
Test status
Simulation time 148685195 ps
CPU time 0.87 seconds
Started Jun 29 06:36:21 PM PDT 24
Finished Jun 29 06:36:23 PM PDT 24
Peak memory 206220 kb
Host smart-b4013dc1-126c-48db-8d71-79173e98636c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=297170712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.297170712
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2460896857
Short name T1516
Test name
Test status
Simulation time 141152745 ps
CPU time 0.74 seconds
Started Jun 29 06:36:12 PM PDT 24
Finished Jun 29 06:36:13 PM PDT 24
Peak memory 206216 kb
Host smart-f87e80dd-8c4f-428d-b140-d2db853818ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24608
96857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2460896857
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1622279126
Short name T2291
Test name
Test status
Simulation time 228893569 ps
CPU time 0.87 seconds
Started Jun 29 06:36:18 PM PDT 24
Finished Jun 29 06:36:19 PM PDT 24
Peak memory 206196 kb
Host smart-5733b146-9cc8-4e16-b51c-e6e9610407f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16222
79126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1622279126
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.3035375181
Short name T1079
Test name
Test status
Simulation time 201262524 ps
CPU time 0.87 seconds
Started Jun 29 06:36:17 PM PDT 24
Finished Jun 29 06:36:18 PM PDT 24
Peak memory 206204 kb
Host smart-7176720e-d10e-48cd-bd6b-f0f353844aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30353
75181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3035375181
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1143759104
Short name T1627
Test name
Test status
Simulation time 163901567 ps
CPU time 0.84 seconds
Started Jun 29 06:36:18 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 206172 kb
Host smart-83fecb8a-5144-4c52-bfbd-4c00182b8c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437
59104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1143759104
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3561642454
Short name T918
Test name
Test status
Simulation time 188090792 ps
CPU time 0.81 seconds
Started Jun 29 06:36:33 PM PDT 24
Finished Jun 29 06:36:35 PM PDT 24
Peak memory 206164 kb
Host smart-4fce656b-d2b6-42d7-b373-bb94297945e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35616
42454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3561642454
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3467020443
Short name T196
Test name
Test status
Simulation time 144648308 ps
CPU time 0.78 seconds
Started Jun 29 06:36:15 PM PDT 24
Finished Jun 29 06:36:16 PM PDT 24
Peak memory 206220 kb
Host smart-18066723-36a3-4cf3-b4df-313e086e221b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34670
20443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3467020443
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2369874406
Short name T1794
Test name
Test status
Simulation time 228378536 ps
CPU time 0.93 seconds
Started Jun 29 06:36:27 PM PDT 24
Finished Jun 29 06:36:29 PM PDT 24
Peak memory 206144 kb
Host smart-e1c6eb86-9b27-4129-8f51-779b99f389f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2369874406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2369874406
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1425085036
Short name T1846
Test name
Test status
Simulation time 179976124 ps
CPU time 0.86 seconds
Started Jun 29 06:36:22 PM PDT 24
Finished Jun 29 06:36:23 PM PDT 24
Peak memory 206204 kb
Host smart-9316ac28-0dd0-4fd5-b0b9-a230c80ec2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14250
85036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1425085036
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.62650655
Short name T2605
Test name
Test status
Simulation time 38328762 ps
CPU time 0.65 seconds
Started Jun 29 06:36:30 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206188 kb
Host smart-e05aae37-e062-4823-b374-96cf6e4f18a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62650
655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.62650655
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1438285810
Short name T1229
Test name
Test status
Simulation time 23066183282 ps
CPU time 49.92 seconds
Started Jun 29 06:36:12 PM PDT 24
Finished Jun 29 06:37:03 PM PDT 24
Peak memory 206428 kb
Host smart-983e1543-f306-4eb2-a4ef-84eb49cb6ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14382
85810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1438285810
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2098188437
Short name T893
Test name
Test status
Simulation time 217883720 ps
CPU time 0.94 seconds
Started Jun 29 06:36:19 PM PDT 24
Finished Jun 29 06:36:21 PM PDT 24
Peak memory 206196 kb
Host smart-ebe6cd1d-5bb1-418a-9c07-37b76b096187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20981
88437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2098188437
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.40925025
Short name T1853
Test name
Test status
Simulation time 255487257 ps
CPU time 0.96 seconds
Started Jun 29 06:36:18 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 206164 kb
Host smart-3075005b-479b-47ec-a5cb-feed51269ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40925
025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.40925025
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2730133295
Short name T2596
Test name
Test status
Simulation time 233561206 ps
CPU time 0.87 seconds
Started Jun 29 06:36:12 PM PDT 24
Finished Jun 29 06:36:13 PM PDT 24
Peak memory 206216 kb
Host smart-cd798afe-248c-401f-b94e-d6302ff9a041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27301
33295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2730133295
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2439180873
Short name T1713
Test name
Test status
Simulation time 160447946 ps
CPU time 0.88 seconds
Started Jun 29 06:36:21 PM PDT 24
Finished Jun 29 06:36:23 PM PDT 24
Peak memory 206192 kb
Host smart-494c3156-1413-4537-9052-51b13b4fd489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24391
80873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2439180873
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3574696873
Short name T2565
Test name
Test status
Simulation time 149851219 ps
CPU time 0.75 seconds
Started Jun 29 06:36:26 PM PDT 24
Finished Jun 29 06:36:27 PM PDT 24
Peak memory 206196 kb
Host smart-22fe147e-5e11-443d-aa25-2a9d570ea46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35746
96873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3574696873
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.4233154075
Short name T116
Test name
Test status
Simulation time 141918157 ps
CPU time 0.79 seconds
Started Jun 29 06:36:41 PM PDT 24
Finished Jun 29 06:36:42 PM PDT 24
Peak memory 206204 kb
Host smart-f00e686d-000c-49f1-bb0e-09255fa81802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42331
54075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.4233154075
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.103946341
Short name T2478
Test name
Test status
Simulation time 162377686 ps
CPU time 0.79 seconds
Started Jun 29 06:36:21 PM PDT 24
Finished Jun 29 06:36:23 PM PDT 24
Peak memory 206216 kb
Host smart-af98425b-8dff-4739-a29a-297812ea68f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10394
6341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.103946341
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1191261431
Short name T2160
Test name
Test status
Simulation time 187225992 ps
CPU time 0.84 seconds
Started Jun 29 06:36:30 PM PDT 24
Finished Jun 29 06:36:32 PM PDT 24
Peak memory 206216 kb
Host smart-7aafcaea-2d42-4d04-aae1-28c522085eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11912
61431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1191261431
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3646577824
Short name T2313
Test name
Test status
Simulation time 4115604697 ps
CPU time 39.3 seconds
Started Jun 29 06:36:33 PM PDT 24
Finished Jun 29 06:37:13 PM PDT 24
Peak memory 206408 kb
Host smart-f59d6b61-2d7a-4be7-b1eb-fab88d18f343
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3646577824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3646577824
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.625246875
Short name T1681
Test name
Test status
Simulation time 187815418 ps
CPU time 0.87 seconds
Started Jun 29 06:36:21 PM PDT 24
Finished Jun 29 06:36:22 PM PDT 24
Peak memory 206220 kb
Host smart-948962f6-d3d4-48aa-a3ea-09303fe3ed71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62524
6875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.625246875
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3070137927
Short name T311
Test name
Test status
Simulation time 182945559 ps
CPU time 0.92 seconds
Started Jun 29 06:36:30 PM PDT 24
Finished Jun 29 06:36:32 PM PDT 24
Peak memory 206140 kb
Host smart-c996f254-7003-43cc-a0e9-bcf317d5a79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30701
37927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3070137927
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.144244163
Short name T1871
Test name
Test status
Simulation time 7335369399 ps
CPU time 71.69 seconds
Started Jun 29 06:36:26 PM PDT 24
Finished Jun 29 06:37:38 PM PDT 24
Peak memory 206480 kb
Host smart-8a90fbc5-26ba-499b-ab12-3ba07e75214d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14424
4163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.144244163
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.1883835947
Short name T200
Test name
Test status
Simulation time 79072218 ps
CPU time 0.76 seconds
Started Jun 29 06:36:45 PM PDT 24
Finished Jun 29 06:36:47 PM PDT 24
Peak memory 206212 kb
Host smart-4b68c313-efb4-47ef-9e13-4b6704c9a6db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1883835947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.1883835947
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2861511475
Short name T1028
Test name
Test status
Simulation time 3794696714 ps
CPU time 5.06 seconds
Started Jun 29 06:36:28 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 206360 kb
Host smart-5502287a-216c-4d47-a8ab-e40c10aeeae3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2861511475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.2861511475
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1867032500
Short name T214
Test name
Test status
Simulation time 13373888935 ps
CPU time 14.06 seconds
Started Jun 29 06:36:33 PM PDT 24
Finished Jun 29 06:36:48 PM PDT 24
Peak memory 206340 kb
Host smart-e42f4542-6dc3-4172-8b41-2932bab4fc36
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1867032500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1867032500
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2361234884
Short name T620
Test name
Test status
Simulation time 23309712672 ps
CPU time 22.99 seconds
Started Jun 29 06:36:20 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 206324 kb
Host smart-70527af0-f140-4819-b14e-b742daedbbd7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2361234884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.2361234884
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.515355893
Short name T454
Test name
Test status
Simulation time 184473815 ps
CPU time 0.82 seconds
Started Jun 29 06:36:32 PM PDT 24
Finished Jun 29 06:36:34 PM PDT 24
Peak memory 206200 kb
Host smart-1805367c-7899-4770-9860-0120014906c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51535
5893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.515355893
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1760680040
Short name T1174
Test name
Test status
Simulation time 186523163 ps
CPU time 0.86 seconds
Started Jun 29 06:36:32 PM PDT 24
Finished Jun 29 06:36:34 PM PDT 24
Peak memory 206372 kb
Host smart-46edc21c-2c89-44f0-bae6-e22f18b4744f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606
80040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1760680040
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.2613987846
Short name T601
Test name
Test status
Simulation time 162120777 ps
CPU time 0.84 seconds
Started Jun 29 06:36:27 PM PDT 24
Finished Jun 29 06:36:28 PM PDT 24
Peak memory 206196 kb
Host smart-22706534-5983-4fe7-b6d4-b62742b0f887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26139
87846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.2613987846
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2817712827
Short name T1708
Test name
Test status
Simulation time 829709384 ps
CPU time 2.1 seconds
Started Jun 29 06:36:32 PM PDT 24
Finished Jun 29 06:36:35 PM PDT 24
Peak memory 206276 kb
Host smart-e1a5aebb-992b-4953-bf43-4fd578d70781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28177
12827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2817712827
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1093711676
Short name T179
Test name
Test status
Simulation time 18666812165 ps
CPU time 36.37 seconds
Started Jun 29 06:36:32 PM PDT 24
Finished Jun 29 06:37:10 PM PDT 24
Peak memory 206464 kb
Host smart-2d3f691c-dea1-4622-adc2-004e86832b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10937
11676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1093711676
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.323794058
Short name T853
Test name
Test status
Simulation time 437872819 ps
CPU time 1.28 seconds
Started Jun 29 06:36:28 PM PDT 24
Finished Jun 29 06:36:30 PM PDT 24
Peak memory 206220 kb
Host smart-7adaa05b-602d-4bcd-99cc-7c1e0107af68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32379
4058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.323794058
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3888330690
Short name T1809
Test name
Test status
Simulation time 138420095 ps
CPU time 0.8 seconds
Started Jun 29 06:36:30 PM PDT 24
Finished Jun 29 06:36:32 PM PDT 24
Peak memory 206196 kb
Host smart-e4af7658-5cf5-405b-8fd7-ae09e8056743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38883
30690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3888330690
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2834513707
Short name T1126
Test name
Test status
Simulation time 36714654 ps
CPU time 0.71 seconds
Started Jun 29 06:36:23 PM PDT 24
Finished Jun 29 06:36:24 PM PDT 24
Peak memory 206108 kb
Host smart-a441d200-c53d-4a99-adb3-d33aefffe729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28345
13707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2834513707
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.4118270776
Short name T727
Test name
Test status
Simulation time 913708370 ps
CPU time 2.22 seconds
Started Jun 29 06:36:26 PM PDT 24
Finished Jun 29 06:36:29 PM PDT 24
Peak memory 206292 kb
Host smart-ef7ee3b3-70cb-4b43-b139-50aaa32f1000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41182
70776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.4118270776
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1908282478
Short name T598
Test name
Test status
Simulation time 331823350 ps
CPU time 2.12 seconds
Started Jun 29 06:36:30 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 206244 kb
Host smart-7641fb51-3047-4cf0-ba8c-ea5664c3ce32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19082
82478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1908282478
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2610495550
Short name T661
Test name
Test status
Simulation time 200772626 ps
CPU time 0.89 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206172 kb
Host smart-1bac0a06-d54a-4330-9767-fbe6a0c9d19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26104
95550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2610495550
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2125019663
Short name T2457
Test name
Test status
Simulation time 175871881 ps
CPU time 0.82 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:30 PM PDT 24
Peak memory 206168 kb
Host smart-f78cd92a-5a16-48cf-80b7-4ce43fe67b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21250
19663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2125019663
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.985481903
Short name T2016
Test name
Test status
Simulation time 252372693 ps
CPU time 0.91 seconds
Started Jun 29 06:36:28 PM PDT 24
Finished Jun 29 06:36:30 PM PDT 24
Peak memory 206212 kb
Host smart-0d30e28a-a895-4e0b-8518-8efd375c4057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98548
1903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.985481903
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.2529390461
Short name T82
Test name
Test status
Simulation time 5329422385 ps
CPU time 155.36 seconds
Started Jun 29 06:36:38 PM PDT 24
Finished Jun 29 06:39:14 PM PDT 24
Peak memory 206492 kb
Host smart-87f858fe-88f5-4e87-9d6a-1b1235dc71c7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2529390461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2529390461
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.843699845
Short name T1747
Test name
Test status
Simulation time 225393035 ps
CPU time 0.9 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:30 PM PDT 24
Peak memory 206152 kb
Host smart-918e34c0-a69b-4e02-bb7b-d27277a430d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84369
9845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.843699845
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3809316720
Short name T2192
Test name
Test status
Simulation time 23365226486 ps
CPU time 28.91 seconds
Started Jun 29 06:36:28 PM PDT 24
Finished Jun 29 06:36:58 PM PDT 24
Peak memory 206316 kb
Host smart-fc2ba0f8-da91-446a-b1e6-9f99aff3968d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38093
16720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3809316720
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2325795401
Short name T1517
Test name
Test status
Simulation time 3266164413 ps
CPU time 4.17 seconds
Started Jun 29 06:36:27 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206256 kb
Host smart-6b9763d9-eb7d-4f65-8442-eb77a5fcd67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23257
95401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2325795401
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.922477509
Short name T1895
Test name
Test status
Simulation time 7637694729 ps
CPU time 216.95 seconds
Started Jun 29 06:36:33 PM PDT 24
Finished Jun 29 06:40:11 PM PDT 24
Peak memory 206508 kb
Host smart-aa3c06ed-1e5f-4576-88b5-9dd73de9488e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92247
7509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.922477509
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.639772915
Short name T2252
Test name
Test status
Simulation time 3700580126 ps
CPU time 33.48 seconds
Started Jun 29 06:36:30 PM PDT 24
Finished Jun 29 06:37:05 PM PDT 24
Peak memory 206456 kb
Host smart-05ad16b9-ef53-4a3c-852d-a71d1e556383
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=639772915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.639772915
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3183599895
Short name T429
Test name
Test status
Simulation time 263858815 ps
CPU time 1 seconds
Started Jun 29 06:36:21 PM PDT 24
Finished Jun 29 06:36:23 PM PDT 24
Peak memory 206220 kb
Host smart-8b5ee03a-107e-4ace-8bb2-5dd0f490bf3b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3183599895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3183599895
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.855078472
Short name T961
Test name
Test status
Simulation time 186059220 ps
CPU time 0.88 seconds
Started Jun 29 06:36:22 PM PDT 24
Finished Jun 29 06:36:24 PM PDT 24
Peak memory 206216 kb
Host smart-78e4557d-df33-45ee-952d-40e5450aa010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85507
8472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.855078472
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1781920900
Short name T238
Test name
Test status
Simulation time 5505460385 ps
CPU time 153.79 seconds
Started Jun 29 06:36:20 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206492 kb
Host smart-b9e5a3c6-4225-4a8a-a5d4-0e149dc382c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17819
20900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1781920900
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2502704484
Short name T854
Test name
Test status
Simulation time 3304385102 ps
CPU time 91.11 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:38:01 PM PDT 24
Peak memory 206408 kb
Host smart-35901e91-2bbd-4868-9610-b3d343427f13
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2502704484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2502704484
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1483914543
Short name T2251
Test name
Test status
Simulation time 149066292 ps
CPU time 0.77 seconds
Started Jun 29 06:36:27 PM PDT 24
Finished Jun 29 06:36:29 PM PDT 24
Peak memory 206196 kb
Host smart-3aa3b70c-0a8c-407c-bc7f-3a0a963596e3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1483914543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1483914543
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2514642187
Short name T1960
Test name
Test status
Simulation time 145359415 ps
CPU time 0.78 seconds
Started Jun 29 06:36:25 PM PDT 24
Finished Jun 29 06:36:26 PM PDT 24
Peak memory 206212 kb
Host smart-947a68e3-311c-4011-b40b-e558d1bb35a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25146
42187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2514642187
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1088301937
Short name T2255
Test name
Test status
Simulation time 198059519 ps
CPU time 0.86 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:30 PM PDT 24
Peak memory 206196 kb
Host smart-930b8999-ec4f-4ded-907a-f7f902ffbc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10883
01937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1088301937
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3772573342
Short name T611
Test name
Test status
Simulation time 193205031 ps
CPU time 0.83 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206204 kb
Host smart-f8bbe0d4-8a5c-461e-8468-6c63b83a54a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37725
73342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3772573342
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1965695002
Short name T1641
Test name
Test status
Simulation time 160615513 ps
CPU time 0.81 seconds
Started Jun 29 06:36:27 PM PDT 24
Finished Jun 29 06:36:28 PM PDT 24
Peak memory 206108 kb
Host smart-881291c5-8e17-4b46-bb0e-e813df1f907f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19656
95002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1965695002
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.348738806
Short name T2447
Test name
Test status
Simulation time 191260973 ps
CPU time 0.88 seconds
Started Jun 29 06:36:31 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 206196 kb
Host smart-ea3c0c8c-25e8-4740-8cf0-36327964904b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34873
8806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.348738806
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.804851120
Short name T1645
Test name
Test status
Simulation time 150887840 ps
CPU time 0.81 seconds
Started Jun 29 06:36:42 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 206220 kb
Host smart-6e75b4ab-e6c8-47c1-ae0b-11e7b28f05f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80485
1120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.804851120
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.1386712342
Short name T1240
Test name
Test status
Simulation time 259362636 ps
CPU time 0.97 seconds
Started Jun 29 06:36:22 PM PDT 24
Finished Jun 29 06:36:24 PM PDT 24
Peak memory 206200 kb
Host smart-7971cef5-bc3d-4a12-a85d-5bb19b0e5d07
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1386712342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.1386712342
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.4238822523
Short name T2047
Test name
Test status
Simulation time 188828778 ps
CPU time 0.84 seconds
Started Jun 29 06:36:34 PM PDT 24
Finished Jun 29 06:36:40 PM PDT 24
Peak memory 206216 kb
Host smart-88579c36-2ecb-4750-8dc7-b792fae4c1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42388
22523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.4238822523
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2995944588
Short name T932
Test name
Test status
Simulation time 63302077 ps
CPU time 0.75 seconds
Started Jun 29 06:36:28 PM PDT 24
Finished Jun 29 06:36:29 PM PDT 24
Peak memory 206216 kb
Host smart-2f5ee026-1aed-4edc-befa-f4d42eb9f736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29959
44588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2995944588
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2260702737
Short name T1973
Test name
Test status
Simulation time 7866261942 ps
CPU time 17.73 seconds
Started Jun 29 06:36:23 PM PDT 24
Finished Jun 29 06:36:41 PM PDT 24
Peak memory 206428 kb
Host smart-86e2f154-ce95-4882-81f2-1fbfca480b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22607
02737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2260702737
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3780404124
Short name T1430
Test name
Test status
Simulation time 203671975 ps
CPU time 0.9 seconds
Started Jun 29 06:36:21 PM PDT 24
Finished Jun 29 06:36:23 PM PDT 24
Peak memory 206192 kb
Host smart-08a27258-e040-4a02-b66f-e829f797eb39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37804
04124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3780404124
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3971583940
Short name T1220
Test name
Test status
Simulation time 156375245 ps
CPU time 0.84 seconds
Started Jun 29 06:36:31 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 206212 kb
Host smart-994d6266-de14-4bd6-b659-c284509f237e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715
83940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3971583940
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.1935805009
Short name T1442
Test name
Test status
Simulation time 259521181 ps
CPU time 0.9 seconds
Started Jun 29 06:36:34 PM PDT 24
Finished Jun 29 06:36:36 PM PDT 24
Peak memory 206212 kb
Host smart-6552c06e-365e-4fad-a209-ec5bb4cf2ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19358
05009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.1935805009
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.772170491
Short name T1992
Test name
Test status
Simulation time 185440398 ps
CPU time 0.85 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206172 kb
Host smart-fae30af0-c60c-48ba-aad7-90906d97a5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77217
0491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.772170491
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3220384010
Short name T849
Test name
Test status
Simulation time 173272487 ps
CPU time 0.76 seconds
Started Jun 29 06:36:27 PM PDT 24
Finished Jun 29 06:36:28 PM PDT 24
Peak memory 206200 kb
Host smart-e8a48c4d-d38e-4a72-8281-d7fa70a8b65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32203
84010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3220384010
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3926245614
Short name T2209
Test name
Test status
Simulation time 161156563 ps
CPU time 0.8 seconds
Started Jun 29 06:36:33 PM PDT 24
Finished Jun 29 06:36:35 PM PDT 24
Peak memory 206196 kb
Host smart-20eaefc8-2f2a-4ca1-b4c2-53e4ffaaac77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39262
45614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3926245614
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1506956876
Short name T1345
Test name
Test status
Simulation time 154172187 ps
CPU time 0.8 seconds
Started Jun 29 06:36:30 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206196 kb
Host smart-a8d932b4-bffd-44ab-970d-6a29a7389a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15069
56876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1506956876
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.939210560
Short name T1100
Test name
Test status
Simulation time 229473658 ps
CPU time 0.89 seconds
Started Jun 29 06:36:28 PM PDT 24
Finished Jun 29 06:36:30 PM PDT 24
Peak memory 206192 kb
Host smart-2ec507eb-bda1-4b7d-b8b5-474fdae81b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93921
0560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.939210560
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2127568533
Short name T2075
Test name
Test status
Simulation time 7389653138 ps
CPU time 208.49 seconds
Started Jun 29 06:36:32 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206444 kb
Host smart-315526b7-457a-42bc-a920-147debb6bde1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2127568533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2127568533
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3683568494
Short name T1610
Test name
Test status
Simulation time 164130859 ps
CPU time 0.83 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206224 kb
Host smart-914dfbc9-843f-41b0-a204-3d8d69de63e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36835
68494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3683568494
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.4092276304
Short name T1536
Test name
Test status
Simulation time 163007003 ps
CPU time 0.82 seconds
Started Jun 29 06:36:31 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 206196 kb
Host smart-f555816a-b150-4519-9fff-21bdcc8112f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40922
76304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.4092276304
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.3642317860
Short name T2444
Test name
Test status
Simulation time 5463604799 ps
CPU time 50.61 seconds
Started Jun 29 06:36:27 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 206396 kb
Host smart-80e63b2e-f4c6-4016-9f6b-e9d32c86a531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36423
17860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.3642317860
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3510633866
Short name T2417
Test name
Test status
Simulation time 100371054 ps
CPU time 0.74 seconds
Started Jun 29 06:33:55 PM PDT 24
Finished Jun 29 06:33:56 PM PDT 24
Peak memory 206212 kb
Host smart-a317d81f-a17c-4f0a-8516-8fb22c46b312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3510633866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3510633866
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3982722252
Short name T2021
Test name
Test status
Simulation time 3430205545 ps
CPU time 4.18 seconds
Started Jun 29 06:33:45 PM PDT 24
Finished Jun 29 06:33:49 PM PDT 24
Peak memory 206272 kb
Host smart-cc3d6666-6e57-4702-97b2-ae1ada24de0d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3982722252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.3982722252
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.4120600593
Short name T1810
Test name
Test status
Simulation time 13348184573 ps
CPU time 13.36 seconds
Started Jun 29 06:33:46 PM PDT 24
Finished Jun 29 06:33:59 PM PDT 24
Peak memory 206432 kb
Host smart-32ba968d-eb56-40ee-ab2f-36f1d4a543b8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4120600593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.4120600593
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1657626180
Short name T1264
Test name
Test status
Simulation time 23375439310 ps
CPU time 26.18 seconds
Started Jun 29 06:33:48 PM PDT 24
Finished Jun 29 06:34:16 PM PDT 24
Peak memory 206488 kb
Host smart-eb0f14f0-f562-47ae-9848-6faa3ba70ddb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1657626180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.1657626180
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2591158523
Short name T953
Test name
Test status
Simulation time 191402078 ps
CPU time 0.8 seconds
Started Jun 29 06:33:45 PM PDT 24
Finished Jun 29 06:33:46 PM PDT 24
Peak memory 206168 kb
Host smart-62f8093e-94ad-47f3-81c8-25db4f29cc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25911
58523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2591158523
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.3091561704
Short name T61
Test name
Test status
Simulation time 165326048 ps
CPU time 0.82 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:33:48 PM PDT 24
Peak memory 206208 kb
Host smart-f66a3542-bf1e-496e-9c62-103c81079a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30915
61704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3091561704
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.3509171213
Short name T93
Test name
Test status
Simulation time 135464779 ps
CPU time 0.78 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:33:49 PM PDT 24
Peak memory 206192 kb
Host smart-43798148-a55d-4ce6-886e-4dcf34c20335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35091
71213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.3509171213
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1693140481
Short name T998
Test name
Test status
Simulation time 148436436 ps
CPU time 0.78 seconds
Started Jun 29 06:33:50 PM PDT 24
Finished Jun 29 06:33:51 PM PDT 24
Peak memory 206204 kb
Host smart-7750763d-2798-47b7-9373-f76ed3bd7bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16931
40481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1693140481
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.2251446776
Short name T622
Test name
Test status
Simulation time 381375902 ps
CPU time 1.27 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 206188 kb
Host smart-0f840e4e-9409-4774-8184-15d68b0b9cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22514
46776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.2251446776
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2708377332
Short name T1690
Test name
Test status
Simulation time 1434046351 ps
CPU time 3.38 seconds
Started Jun 29 06:33:45 PM PDT 24
Finished Jun 29 06:33:49 PM PDT 24
Peak memory 206272 kb
Host smart-1eb93db7-f0f9-48d7-8e13-31b1616eda62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083
77332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2708377332
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1272751608
Short name T1573
Test name
Test status
Simulation time 15430291820 ps
CPU time 29.74 seconds
Started Jun 29 06:33:49 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 206440 kb
Host smart-62a1aec4-6eff-4255-af52-110a7515c161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12727
51608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1272751608
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.3869368908
Short name T1611
Test name
Test status
Simulation time 339222083 ps
CPU time 1.13 seconds
Started Jun 29 06:33:49 PM PDT 24
Finished Jun 29 06:33:51 PM PDT 24
Peak memory 206220 kb
Host smart-66128e07-22c6-4c7a-bc1c-59724fe31aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38693
68908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.3869368908
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3853465591
Short name T1903
Test name
Test status
Simulation time 148563468 ps
CPU time 0.75 seconds
Started Jun 29 06:33:48 PM PDT 24
Finished Jun 29 06:33:50 PM PDT 24
Peak memory 206200 kb
Host smart-b17155f1-d2d5-464a-83dd-5fde9541ba70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38534
65591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3853465591
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2305147769
Short name T347
Test name
Test status
Simulation time 95693660 ps
CPU time 0.73 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:33:48 PM PDT 24
Peak memory 206208 kb
Host smart-d79364c1-d869-4895-afee-9c6fdb767e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23051
47769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2305147769
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.4128081083
Short name T2142
Test name
Test status
Simulation time 872341965 ps
CPU time 2.23 seconds
Started Jun 29 06:33:47 PM PDT 24
Finished Jun 29 06:33:51 PM PDT 24
Peak memory 206376 kb
Host smart-1ba3590b-f2ce-43dd-8930-9d04f815d675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41280
81083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.4128081083
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.3051466119
Short name T2127
Test name
Test status
Simulation time 167999451 ps
CPU time 1.41 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 206276 kb
Host smart-77fb0c26-662b-4228-9ae6-53dfb0171a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30514
66119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.3051466119
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3079140626
Short name T119
Test name
Test status
Simulation time 233836052 ps
CPU time 0.89 seconds
Started Jun 29 06:33:48 PM PDT 24
Finished Jun 29 06:33:50 PM PDT 24
Peak memory 206212 kb
Host smart-f72c1bbe-3fbc-4dfc-8367-9ac79ef984c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30791
40626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3079140626
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3296481610
Short name T1562
Test name
Test status
Simulation time 142639626 ps
CPU time 0.75 seconds
Started Jun 29 06:33:54 PM PDT 24
Finished Jun 29 06:33:56 PM PDT 24
Peak memory 206360 kb
Host smart-f9f39277-7ac1-4dca-9564-c552fcaad9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32964
81610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3296481610
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.4084812626
Short name T1844
Test name
Test status
Simulation time 163442394 ps
CPU time 0.82 seconds
Started Jun 29 06:33:46 PM PDT 24
Finished Jun 29 06:33:48 PM PDT 24
Peak memory 206212 kb
Host smart-d705f4f0-cdad-4bce-9ad9-76adfa622112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40848
12626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.4084812626
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.665735892
Short name T2352
Test name
Test status
Simulation time 5846571385 ps
CPU time 55.36 seconds
Started Jun 29 06:33:53 PM PDT 24
Finished Jun 29 06:34:49 PM PDT 24
Peak memory 206392 kb
Host smart-2cf00d21-cd49-4639-a72f-2212202a31ae
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=665735892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.665735892
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1745024795
Short name T485
Test name
Test status
Simulation time 213812099 ps
CPU time 0.9 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 206368 kb
Host smart-858a1485-ca30-477d-b1f2-cdce736e3843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17450
24795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1745024795
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.3316534249
Short name T1885
Test name
Test status
Simulation time 23301215662 ps
CPU time 27.29 seconds
Started Jun 29 06:33:52 PM PDT 24
Finished Jun 29 06:34:19 PM PDT 24
Peak memory 206316 kb
Host smart-8565db90-7a23-4396-9c9e-7373312730c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33165
34249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3316534249
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3009211692
Short name T1398
Test name
Test status
Simulation time 3317448956 ps
CPU time 4.37 seconds
Started Jun 29 06:33:54 PM PDT 24
Finished Jun 29 06:34:00 PM PDT 24
Peak memory 206260 kb
Host smart-db6e0b20-412a-4889-9ac2-64516b0c1123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30092
11692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3009211692
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.65489969
Short name T685
Test name
Test status
Simulation time 11615895466 ps
CPU time 111.94 seconds
Started Jun 29 06:34:04 PM PDT 24
Finished Jun 29 06:35:57 PM PDT 24
Peak memory 206448 kb
Host smart-f5b8e2a6-7080-4114-97f9-96b77090f42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65489
969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.65489969
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3284242286
Short name T1156
Test name
Test status
Simulation time 7237660936 ps
CPU time 196.42 seconds
Started Jun 29 06:33:53 PM PDT 24
Finished Jun 29 06:37:09 PM PDT 24
Peak memory 206460 kb
Host smart-32957d23-fa8d-4249-8b44-39d4f6a1f96c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3284242286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3284242286
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.4262661324
Short name T2516
Test name
Test status
Simulation time 330130240 ps
CPU time 0.99 seconds
Started Jun 29 06:34:04 PM PDT 24
Finished Jun 29 06:34:07 PM PDT 24
Peak memory 206216 kb
Host smart-72fa0805-9425-456b-97c6-88c02939869d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4262661324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.4262661324
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1274889572
Short name T1619
Test name
Test status
Simulation time 188271167 ps
CPU time 0.84 seconds
Started Jun 29 06:33:53 PM PDT 24
Finished Jun 29 06:33:55 PM PDT 24
Peak memory 206216 kb
Host smart-f7fc296c-e9cb-49bc-83ea-dd37dd6311c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12748
89572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1274889572
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2196001183
Short name T2170
Test name
Test status
Simulation time 3628248983 ps
CPU time 97.41 seconds
Started Jun 29 06:33:57 PM PDT 24
Finished Jun 29 06:35:35 PM PDT 24
Peak memory 206468 kb
Host smart-7f425e92-254d-4241-b54f-c82adff420d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
01183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2196001183
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3101674781
Short name T654
Test name
Test status
Simulation time 5048935232 ps
CPU time 34.45 seconds
Started Jun 29 06:33:55 PM PDT 24
Finished Jun 29 06:34:31 PM PDT 24
Peak memory 206500 kb
Host smart-fbb24fab-dec5-45e1-9111-472c82e77510
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3101674781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3101674781
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1631007212
Short name T2433
Test name
Test status
Simulation time 155269906 ps
CPU time 0.79 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:33:57 PM PDT 24
Peak memory 206220 kb
Host smart-7cc8e6fd-5607-4c95-b474-7fd49c8c2065
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1631007212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1631007212
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3442397768
Short name T1275
Test name
Test status
Simulation time 182947202 ps
CPU time 0.82 seconds
Started Jun 29 06:34:02 PM PDT 24
Finished Jun 29 06:34:03 PM PDT 24
Peak memory 206216 kb
Host smart-3492af22-ae32-4d74-b5f7-d96fdeaa1b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34423
97768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3442397768
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.60998805
Short name T1364
Test name
Test status
Simulation time 202502873 ps
CPU time 0.86 seconds
Started Jun 29 06:34:11 PM PDT 24
Finished Jun 29 06:34:12 PM PDT 24
Peak memory 206204 kb
Host smart-a5de1726-dca4-4f5c-ab49-af962c2bcf51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60998
805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.60998805
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.4118046613
Short name T1068
Test name
Test status
Simulation time 182526595 ps
CPU time 0.88 seconds
Started Jun 29 06:34:05 PM PDT 24
Finished Jun 29 06:34:07 PM PDT 24
Peak memory 206196 kb
Host smart-e65c71ed-f9f8-4d53-a24b-d1571031f295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
46613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.4118046613
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1033686528
Short name T2485
Test name
Test status
Simulation time 154516477 ps
CPU time 0.77 seconds
Started Jun 29 06:34:03 PM PDT 24
Finished Jun 29 06:34:04 PM PDT 24
Peak memory 206224 kb
Host smart-672de2b1-4fa5-4a6e-bcba-732ff1f30d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10336
86528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1033686528
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3732058195
Short name T1164
Test name
Test status
Simulation time 224458333 ps
CPU time 0.9 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 206224 kb
Host smart-ac76c6d1-f41c-425a-aaf8-22cc9517fcf2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3732058195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3732058195
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.505061316
Short name T218
Test name
Test status
Simulation time 212895807 ps
CPU time 0.95 seconds
Started Jun 29 06:33:58 PM PDT 24
Finished Jun 29 06:33:59 PM PDT 24
Peak memory 206220 kb
Host smart-ec3aeba6-845e-4fdd-822b-1df22b712933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50506
1316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.505061316
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.637839961
Short name T1467
Test name
Test status
Simulation time 156582951 ps
CPU time 0.76 seconds
Started Jun 29 06:34:06 PM PDT 24
Finished Jun 29 06:34:08 PM PDT 24
Peak memory 206200 kb
Host smart-091b5537-161c-4641-9f78-23e489095b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63783
9961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.637839961
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.4012410541
Short name T1818
Test name
Test status
Simulation time 43153160 ps
CPU time 0.65 seconds
Started Jun 29 06:34:03 PM PDT 24
Finished Jun 29 06:34:04 PM PDT 24
Peak memory 206212 kb
Host smart-88b43e56-b2a6-4691-999d-9c26ddec2d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40124
10541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.4012410541
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2976061165
Short name T2551
Test name
Test status
Simulation time 10673195371 ps
CPU time 23.2 seconds
Started Jun 29 06:34:05 PM PDT 24
Finished Jun 29 06:34:30 PM PDT 24
Peak memory 206376 kb
Host smart-81ee2024-67b1-4b6a-9504-407d706bb2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29760
61165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2976061165
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3722009913
Short name T1003
Test name
Test status
Simulation time 167484167 ps
CPU time 0.89 seconds
Started Jun 29 06:34:06 PM PDT 24
Finished Jun 29 06:34:08 PM PDT 24
Peak memory 206204 kb
Host smart-f3bbbf9e-982d-40fe-a721-2e1f540fca68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37220
09913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3722009913
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.4121582232
Short name T2266
Test name
Test status
Simulation time 184813172 ps
CPU time 0.79 seconds
Started Jun 29 06:33:55 PM PDT 24
Finished Jun 29 06:33:56 PM PDT 24
Peak memory 206212 kb
Host smart-91b14e1c-dddc-4590-8870-6e096c5e191a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41215
82232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.4121582232
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3733422070
Short name T1677
Test name
Test status
Simulation time 5378326411 ps
CPU time 131.35 seconds
Started Jun 29 06:34:09 PM PDT 24
Finished Jun 29 06:36:21 PM PDT 24
Peak memory 206420 kb
Host smart-2e5618f6-1d43-422e-bd2d-a567f3debb33
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3733422070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3733422070
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.1872166075
Short name T1263
Test name
Test status
Simulation time 7425172473 ps
CPU time 30.32 seconds
Started Jun 29 06:34:06 PM PDT 24
Finished Jun 29 06:34:38 PM PDT 24
Peak memory 206532 kb
Host smart-737833f8-ff2e-4d32-b2c2-8d8f9dfd5dc2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1872166075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.1872166075
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1409495321
Short name T1695
Test name
Test status
Simulation time 200188572 ps
CPU time 0.92 seconds
Started Jun 29 06:33:55 PM PDT 24
Finished Jun 29 06:33:56 PM PDT 24
Peak memory 206216 kb
Host smart-d424943e-b8f9-4a3e-b77a-201eb5ff14e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14094
95321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1409495321
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.3417206022
Short name T2475
Test name
Test status
Simulation time 160232579 ps
CPU time 0.81 seconds
Started Jun 29 06:33:52 PM PDT 24
Finished Jun 29 06:33:53 PM PDT 24
Peak memory 206196 kb
Host smart-7cb9ce26-34fb-4c55-8fa2-04458ad86690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34172
06022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.3417206022
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1548125484
Short name T800
Test name
Test status
Simulation time 201110448 ps
CPU time 0.81 seconds
Started Jun 29 06:33:54 PM PDT 24
Finished Jun 29 06:33:55 PM PDT 24
Peak memory 206200 kb
Host smart-b7fdc1e5-8bd9-4866-b498-1301e1502ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481
25484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1548125484
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.125408854
Short name T85
Test name
Test status
Simulation time 172676420 ps
CPU time 0.79 seconds
Started Jun 29 06:34:04 PM PDT 24
Finished Jun 29 06:34:05 PM PDT 24
Peak memory 206196 kb
Host smart-cc435374-00b0-4bab-9bb4-746069931cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12540
8854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.125408854
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3985816165
Short name T226
Test name
Test status
Simulation time 557753602 ps
CPU time 1.32 seconds
Started Jun 29 06:34:02 PM PDT 24
Finished Jun 29 06:34:03 PM PDT 24
Peak memory 224080 kb
Host smart-ba8ace79-9540-4d3b-b3cf-2beeb90146de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3985816165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3985816165
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3725280295
Short name T64
Test name
Test status
Simulation time 376882193 ps
CPU time 1.2 seconds
Started Jun 29 06:33:57 PM PDT 24
Finished Jun 29 06:33:59 PM PDT 24
Peak memory 206220 kb
Host smart-f98b3374-6d13-4d0f-98ef-fb1bd19188b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37252
80295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3725280295
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3453248096
Short name T1773
Test name
Test status
Simulation time 313425714 ps
CPU time 0.95 seconds
Started Jun 29 06:33:54 PM PDT 24
Finished Jun 29 06:33:56 PM PDT 24
Peak memory 206196 kb
Host smart-1bce84c5-8a14-40b5-a6cf-2d6a323be0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34532
48096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3453248096
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2249900696
Short name T797
Test name
Test status
Simulation time 161452758 ps
CPU time 0.86 seconds
Started Jun 29 06:34:11 PM PDT 24
Finished Jun 29 06:34:12 PM PDT 24
Peak memory 206188 kb
Host smart-2c345698-db62-4ed4-8041-08c064133c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22499
00696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2249900696
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1166558871
Short name T383
Test name
Test status
Simulation time 155256717 ps
CPU time 0.77 seconds
Started Jun 29 06:34:02 PM PDT 24
Finished Jun 29 06:34:04 PM PDT 24
Peak memory 206156 kb
Host smart-7ca903dc-71f0-44ba-91ad-ce3d07542f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11665
58871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1166558871
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2056546631
Short name T554
Test name
Test status
Simulation time 241485750 ps
CPU time 0.93 seconds
Started Jun 29 06:33:53 PM PDT 24
Finished Jun 29 06:33:55 PM PDT 24
Peak memory 206216 kb
Host smart-27886e97-17c1-4846-bec3-b6a409e99625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565
46631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2056546631
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.744001249
Short name T1575
Test name
Test status
Simulation time 4160439274 ps
CPU time 115.6 seconds
Started Jun 29 06:33:56 PM PDT 24
Finished Jun 29 06:35:52 PM PDT 24
Peak memory 206504 kb
Host smart-74bbf94c-b25e-4355-bc97-b04974178871
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=744001249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.744001249
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1643248562
Short name T712
Test name
Test status
Simulation time 181149653 ps
CPU time 0.83 seconds
Started Jun 29 06:34:06 PM PDT 24
Finished Jun 29 06:34:08 PM PDT 24
Peak memory 206224 kb
Host smart-967be952-c486-439a-834c-eb720367d4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16432
48562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1643248562
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2787249980
Short name T1777
Test name
Test status
Simulation time 162503085 ps
CPU time 0.79 seconds
Started Jun 29 06:34:04 PM PDT 24
Finished Jun 29 06:34:06 PM PDT 24
Peak memory 206196 kb
Host smart-82fd80d1-8200-492b-910a-9e75cff823a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27872
49980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2787249980
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.3779177076
Short name T1621
Test name
Test status
Simulation time 5239272497 ps
CPU time 145.96 seconds
Started Jun 29 06:33:54 PM PDT 24
Finished Jun 29 06:36:21 PM PDT 24
Peak memory 206440 kb
Host smart-95b4fb56-e87d-4abf-8f7b-76d49b8ed682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37791
77076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.3779177076
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.2062413406
Short name T201
Test name
Test status
Simulation time 72761481 ps
CPU time 0.71 seconds
Started Jun 29 06:36:36 PM PDT 24
Finished Jun 29 06:36:38 PM PDT 24
Peak memory 206212 kb
Host smart-a371e670-8133-42f1-8886-2d210bc22e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2062413406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2062413406
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.3563302024
Short name T901
Test name
Test status
Simulation time 3646017983 ps
CPU time 4.25 seconds
Started Jun 29 06:36:35 PM PDT 24
Finished Jun 29 06:36:40 PM PDT 24
Peak memory 206368 kb
Host smart-db78d891-772d-45c5-a7ad-7168512fe64f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3563302024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.3563302024
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.3777084756
Short name T924
Test name
Test status
Simulation time 13360147337 ps
CPU time 11.92 seconds
Started Jun 29 06:36:32 PM PDT 24
Finished Jun 29 06:36:45 PM PDT 24
Peak memory 206420 kb
Host smart-f81b21be-1a06-4497-9325-7a24b4419f81
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3777084756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.3777084756
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.2559899365
Short name T1667
Test name
Test status
Simulation time 23374605551 ps
CPU time 21.34 seconds
Started Jun 29 06:36:44 PM PDT 24
Finished Jun 29 06:37:07 PM PDT 24
Peak memory 206360 kb
Host smart-08f1ea96-4c42-46d5-a12c-3bd3565a12ed
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2559899365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.2559899365
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1753161274
Short name T1473
Test name
Test status
Simulation time 155364049 ps
CPU time 0.8 seconds
Started Jun 29 06:36:30 PM PDT 24
Finished Jun 29 06:36:32 PM PDT 24
Peak memory 206104 kb
Host smart-87f7c299-e1e5-4cb1-a45b-5f35f01cb965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17531
61274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1753161274
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.872089760
Short name T481
Test name
Test status
Simulation time 174304853 ps
CPU time 0.81 seconds
Started Jun 29 06:36:32 PM PDT 24
Finished Jun 29 06:36:34 PM PDT 24
Peak memory 206204 kb
Host smart-d3917bba-8dfc-45c1-afce-93762d7a6441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87208
9760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.872089760
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2530152220
Short name T530
Test name
Test status
Simulation time 248903147 ps
CPU time 1.02 seconds
Started Jun 29 06:36:35 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206196 kb
Host smart-6ac3ac69-b261-40d4-a61a-b7e3f5219e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25301
52220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2530152220
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2927280108
Short name T191
Test name
Test status
Simulation time 999150961 ps
CPU time 2.2 seconds
Started Jun 29 06:36:41 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 206100 kb
Host smart-88177dd0-97fb-48d0-9a9e-5915119060fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29272
80108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2927280108
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.691400425
Short name T1642
Test name
Test status
Simulation time 15881753718 ps
CPU time 28.44 seconds
Started Jun 29 06:36:41 PM PDT 24
Finished Jun 29 06:37:10 PM PDT 24
Peak memory 206420 kb
Host smart-3b4bd8d7-d370-4251-9a15-f204e7402627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69140
0425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.691400425
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.4156092338
Short name T1833
Test name
Test status
Simulation time 472328634 ps
CPU time 1.34 seconds
Started Jun 29 06:36:35 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206200 kb
Host smart-e134eb6e-efc1-4eed-9fc3-1f0f47e95e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41560
92338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.4156092338
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1773784448
Short name T53
Test name
Test status
Simulation time 136166747 ps
CPU time 0.79 seconds
Started Jun 29 06:36:42 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 206372 kb
Host smart-ec4bbe00-935c-40cb-8b97-25c9575496c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17737
84448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1773784448
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3393651743
Short name T521
Test name
Test status
Simulation time 50020636 ps
CPU time 0.68 seconds
Started Jun 29 06:36:46 PM PDT 24
Finished Jun 29 06:36:48 PM PDT 24
Peak memory 206196 kb
Host smart-9ef83790-c3b6-420f-8d0d-17b87dd99237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33936
51743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3393651743
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.4211161705
Short name T588
Test name
Test status
Simulation time 961587024 ps
CPU time 2.16 seconds
Started Jun 29 06:36:49 PM PDT 24
Finished Jun 29 06:36:56 PM PDT 24
Peak memory 206296 kb
Host smart-ab1d840e-caad-46bd-a694-29cbf1f31287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42111
61705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.4211161705
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1921884402
Short name T1378
Test name
Test status
Simulation time 148792405 ps
CPU time 1.27 seconds
Started Jun 29 06:36:34 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206332 kb
Host smart-6cd9955b-0ea4-46ed-bf75-c946048692c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19218
84402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1921884402
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.4120605538
Short name T2038
Test name
Test status
Simulation time 156328449 ps
CPU time 0.78 seconds
Started Jun 29 06:36:34 PM PDT 24
Finished Jun 29 06:36:35 PM PDT 24
Peak memory 206208 kb
Host smart-3b674dce-d85a-4b1e-b293-a7166ac7eb0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41206
05538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.4120605538
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2422005448
Short name T1189
Test name
Test status
Simulation time 233389666 ps
CPU time 0.93 seconds
Started Jun 29 06:36:48 PM PDT 24
Finished Jun 29 06:36:50 PM PDT 24
Peak memory 206216 kb
Host smart-b45787c1-27d7-454f-8ac9-67bce981a8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24220
05448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2422005448
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.2067405898
Short name T1538
Test name
Test status
Simulation time 4916287654 ps
CPU time 35.75 seconds
Started Jun 29 06:36:46 PM PDT 24
Finished Jun 29 06:37:23 PM PDT 24
Peak memory 206416 kb
Host smart-070d2ae6-47ad-45ee-bbed-86dc01bade73
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2067405898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2067405898
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.1586615336
Short name T386
Test name
Test status
Simulation time 222494319 ps
CPU time 0.91 seconds
Started Jun 29 06:36:35 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206192 kb
Host smart-fe5bd16e-4232-421a-8809-74bc63f7db4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15866
15336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1586615336
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.2728120390
Short name T1634
Test name
Test status
Simulation time 23337376056 ps
CPU time 22.41 seconds
Started Jun 29 06:36:46 PM PDT 24
Finished Jun 29 06:37:10 PM PDT 24
Peak memory 206320 kb
Host smart-5caaa2a3-059d-4d53-a4f6-fcfb74063ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27281
20390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.2728120390
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3897737544
Short name T2335
Test name
Test status
Simulation time 3311911474 ps
CPU time 3.99 seconds
Started Jun 29 06:36:41 PM PDT 24
Finished Jun 29 06:36:45 PM PDT 24
Peak memory 206256 kb
Host smart-d6ad423e-0ea3-430b-bc3b-b084cd2f1a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38977
37544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3897737544
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.2955620648
Short name T1074
Test name
Test status
Simulation time 7221107158 ps
CPU time 67.74 seconds
Started Jun 29 06:36:40 PM PDT 24
Finished Jun 29 06:37:48 PM PDT 24
Peak memory 206472 kb
Host smart-c29f33d2-e187-4deb-bac9-fadfdf3abbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29556
20648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.2955620648
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.417409969
Short name T1918
Test name
Test status
Simulation time 5108353454 ps
CPU time 35.75 seconds
Started Jun 29 06:36:33 PM PDT 24
Finished Jun 29 06:37:10 PM PDT 24
Peak memory 206488 kb
Host smart-d92b14da-c11f-4ac7-a6f6-3a022b45df10
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=417409969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.417409969
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1314500189
Short name T694
Test name
Test status
Simulation time 237902456 ps
CPU time 0.96 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206200 kb
Host smart-ca8d4a25-9f01-4153-8f53-939c552c65bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1314500189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1314500189
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3932059061
Short name T816
Test name
Test status
Simulation time 238046056 ps
CPU time 0.94 seconds
Started Jun 29 06:36:33 PM PDT 24
Finished Jun 29 06:36:35 PM PDT 24
Peak memory 206168 kb
Host smart-83d0aad8-b5b2-4e9d-971e-5a9c9833c8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39320
59061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3932059061
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.401474840
Short name T553
Test name
Test status
Simulation time 4431198933 ps
CPU time 30.81 seconds
Started Jun 29 06:36:57 PM PDT 24
Finished Jun 29 06:37:28 PM PDT 24
Peak memory 206504 kb
Host smart-24efa669-9123-462f-898f-53b6de2c0a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40147
4840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.401474840
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1750857127
Short name T997
Test name
Test status
Simulation time 4107721528 ps
CPU time 31.59 seconds
Started Jun 29 06:36:33 PM PDT 24
Finished Jun 29 06:37:05 PM PDT 24
Peak memory 206484 kb
Host smart-998566b3-a661-4bf9-99bf-159f8a61cfc7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1750857127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1750857127
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.3154323858
Short name T1308
Test name
Test status
Simulation time 153307110 ps
CPU time 0.79 seconds
Started Jun 29 06:36:35 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206220 kb
Host smart-1cde50e9-e1b3-4f07-92d5-71342c934433
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3154323858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.3154323858
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.741885613
Short name T255
Test name
Test status
Simulation time 147562022 ps
CPU time 0.78 seconds
Started Jun 29 06:36:38 PM PDT 24
Finished Jun 29 06:36:40 PM PDT 24
Peak memory 206216 kb
Host smart-a817d915-2c9d-47fc-9750-014202420226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74188
5613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.741885613
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.4292457067
Short name T153
Test name
Test status
Simulation time 248388072 ps
CPU time 0.91 seconds
Started Jun 29 06:36:33 PM PDT 24
Finished Jun 29 06:36:35 PM PDT 24
Peak memory 206196 kb
Host smart-0ef9d784-3800-469b-928b-8324d3ff8db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42924
57067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.4292457067
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2208924413
Short name T2608
Test name
Test status
Simulation time 159683521 ps
CPU time 0.79 seconds
Started Jun 29 06:36:30 PM PDT 24
Finished Jun 29 06:36:32 PM PDT 24
Peak memory 206180 kb
Host smart-87ebe334-9cc1-4617-a1e2-99842b9cecc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22089
24413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2208924413
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2921102502
Short name T2050
Test name
Test status
Simulation time 257961440 ps
CPU time 0.94 seconds
Started Jun 29 06:36:27 PM PDT 24
Finished Jun 29 06:36:29 PM PDT 24
Peak memory 206196 kb
Host smart-ff1849a3-74e6-4885-a524-b22f014dd653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29211
02502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2921102502
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3605920971
Short name T1675
Test name
Test status
Simulation time 183740184 ps
CPU time 0.81 seconds
Started Jun 29 06:36:28 PM PDT 24
Finished Jun 29 06:36:30 PM PDT 24
Peak memory 206216 kb
Host smart-60bfe8d9-1661-4eff-870e-31838b602c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36059
20971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3605920971
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3854700549
Short name T163
Test name
Test status
Simulation time 150805923 ps
CPU time 0.81 seconds
Started Jun 29 06:36:30 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206200 kb
Host smart-df2f5ed2-1bf3-4e1c-b7d7-1e6040814bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38547
00549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3854700549
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1269590063
Short name T1202
Test name
Test status
Simulation time 206397148 ps
CPU time 0.86 seconds
Started Jun 29 06:36:34 PM PDT 24
Finished Jun 29 06:36:36 PM PDT 24
Peak memory 206224 kb
Host smart-0b983d05-7fef-4f74-98a6-7324dc1810e6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1269590063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1269590063
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2780712971
Short name T980
Test name
Test status
Simulation time 139917137 ps
CPU time 0.76 seconds
Started Jun 29 06:36:34 PM PDT 24
Finished Jun 29 06:36:36 PM PDT 24
Peak memory 206212 kb
Host smart-72eea8ed-1e21-4021-80c2-050a6c24d9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27807
12971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2780712971
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1607819421
Short name T1873
Test name
Test status
Simulation time 43542891 ps
CPU time 0.67 seconds
Started Jun 29 06:36:31 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 206212 kb
Host smart-8da8fb41-47ae-4182-a35a-a0d66d05e464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16078
19421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1607819421
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3409565473
Short name T1697
Test name
Test status
Simulation time 8396104406 ps
CPU time 17.93 seconds
Started Jun 29 06:36:31 PM PDT 24
Finished Jun 29 06:36:50 PM PDT 24
Peak memory 206460 kb
Host smart-78f05670-1d69-43e5-8284-2ff4bbebedd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34095
65473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3409565473
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1825523939
Short name T2436
Test name
Test status
Simulation time 160038356 ps
CPU time 0.82 seconds
Started Jun 29 06:36:31 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 206196 kb
Host smart-189fefe8-560c-480f-a90b-d9835d5518a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18255
23939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1825523939
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.405098083
Short name T1482
Test name
Test status
Simulation time 165752843 ps
CPU time 0.85 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206184 kb
Host smart-304f46d3-4539-4f59-9d04-43b6cdc38d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40509
8083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.405098083
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.4223737957
Short name T1832
Test name
Test status
Simulation time 170594508 ps
CPU time 0.89 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:31 PM PDT 24
Peak memory 206216 kb
Host smart-6a0d8dfe-3052-4e20-b36d-3a4da4c3a5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42237
37957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.4223737957
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.1399978929
Short name T1009
Test name
Test status
Simulation time 178715272 ps
CPU time 0.82 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:36:46 PM PDT 24
Peak memory 206164 kb
Host smart-f85e011c-9325-4b47-8924-70482b3a45d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13999
78929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.1399978929
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2543834254
Short name T158
Test name
Test status
Simulation time 164044938 ps
CPU time 0.79 seconds
Started Jun 29 06:36:38 PM PDT 24
Finished Jun 29 06:36:40 PM PDT 24
Peak memory 206196 kb
Host smart-ad52d63a-65c0-4f1d-915f-18f043b76fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25438
34254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2543834254
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.933370516
Short name T492
Test name
Test status
Simulation time 159114757 ps
CPU time 0.8 seconds
Started Jun 29 06:36:41 PM PDT 24
Finished Jun 29 06:36:42 PM PDT 24
Peak memory 206020 kb
Host smart-4353b201-321b-44e6-8899-6d9a44789738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93337
0516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.933370516
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.4068014756
Short name T1448
Test name
Test status
Simulation time 239242326 ps
CPU time 0.98 seconds
Started Jun 29 06:36:31 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 206216 kb
Host smart-0be95119-0f82-4a5c-be85-ede25c5a0aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40680
14756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.4068014756
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1229546193
Short name T1045
Test name
Test status
Simulation time 3767699399 ps
CPU time 27.78 seconds
Started Jun 29 06:37:01 PM PDT 24
Finished Jun 29 06:37:29 PM PDT 24
Peak memory 206404 kb
Host smart-1fe102ae-2567-472d-9765-13238864cbea
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1229546193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1229546193
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2299038811
Short name T710
Test name
Test status
Simulation time 158785948 ps
CPU time 0.82 seconds
Started Jun 29 06:36:42 PM PDT 24
Finished Jun 29 06:36:43 PM PDT 24
Peak memory 206220 kb
Host smart-e9ce2b30-d14e-4deb-b416-9b1686e63a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22990
38811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2299038811
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2070704706
Short name T2340
Test name
Test status
Simulation time 202356991 ps
CPU time 0.89 seconds
Started Jun 29 06:36:40 PM PDT 24
Finished Jun 29 06:36:41 PM PDT 24
Peak memory 206368 kb
Host smart-59f3664f-becd-4c86-8919-471816cdda26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20707
04706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2070704706
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.17876735
Short name T1620
Test name
Test status
Simulation time 5145714942 ps
CPU time 35.9 seconds
Started Jun 29 06:36:31 PM PDT 24
Finished Jun 29 06:37:09 PM PDT 24
Peak memory 206464 kb
Host smart-ba0bbbf0-dcf4-40bf-b3b2-236f8d80735b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17876
735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.17876735
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.2256176148
Short name T1915
Test name
Test status
Simulation time 36600359 ps
CPU time 0.64 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 206212 kb
Host smart-22ab7d4f-c5f3-494f-ba25-3697a3641706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2256176148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.2256176148
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3666341429
Short name T1356
Test name
Test status
Simulation time 3823205289 ps
CPU time 4.81 seconds
Started Jun 29 06:36:47 PM PDT 24
Finished Jun 29 06:36:53 PM PDT 24
Peak memory 206352 kb
Host smart-470dfe6f-c56a-4285-a057-388e1d0490fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3666341429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3666341429
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.831884338
Short name T1735
Test name
Test status
Simulation time 13377635180 ps
CPU time 12.12 seconds
Started Jun 29 06:36:29 PM PDT 24
Finished Jun 29 06:36:42 PM PDT 24
Peak memory 206436 kb
Host smart-718dbd64-da42-4118-a4a4-e62923f0b3f9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=831884338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.831884338
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1970271498
Short name T234
Test name
Test status
Simulation time 23379371160 ps
CPU time 22.05 seconds
Started Jun 29 06:36:49 PM PDT 24
Finished Jun 29 06:37:11 PM PDT 24
Peak memory 206348 kb
Host smart-58f0448b-360c-4bfa-a7af-1c655e20621b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1970271498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.1970271498
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3952383140
Short name T1276
Test name
Test status
Simulation time 213762742 ps
CPU time 0.89 seconds
Started Jun 29 06:36:32 PM PDT 24
Finished Jun 29 06:36:34 PM PDT 24
Peak memory 206192 kb
Host smart-0d490c27-28d7-4c3b-a172-8c6b3cfff80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39523
83140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3952383140
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.4048415725
Short name T433
Test name
Test status
Simulation time 161869480 ps
CPU time 0.77 seconds
Started Jun 29 06:36:33 PM PDT 24
Finished Jun 29 06:36:35 PM PDT 24
Peak memory 206196 kb
Host smart-6cb90dd9-be54-4412-bb96-fa27d6645bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40484
15725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.4048415725
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.3086510129
Short name T1580
Test name
Test status
Simulation time 425749749 ps
CPU time 1.34 seconds
Started Jun 29 06:36:34 PM PDT 24
Finished Jun 29 06:36:36 PM PDT 24
Peak memory 206196 kb
Host smart-88cbbe1c-f291-4f09-91fa-3fb4ab9567a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30865
10129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.3086510129
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2292770755
Short name T2103
Test name
Test status
Simulation time 310352397 ps
CPU time 1.03 seconds
Started Jun 29 06:36:36 PM PDT 24
Finished Jun 29 06:36:38 PM PDT 24
Peak memory 206196 kb
Host smart-4076edc8-f11e-47c7-8693-225e002acd06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22927
70755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2292770755
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.2738586617
Short name T2104
Test name
Test status
Simulation time 13907478749 ps
CPU time 27.69 seconds
Started Jun 29 06:36:36 PM PDT 24
Finished Jun 29 06:37:05 PM PDT 24
Peak memory 206420 kb
Host smart-e72e2fee-15c1-4da1-9d30-a5b2272ffcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27385
86617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2738586617
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.2676873117
Short name T2589
Test name
Test status
Simulation time 370423599 ps
CPU time 1.27 seconds
Started Jun 29 06:36:37 PM PDT 24
Finished Jun 29 06:36:39 PM PDT 24
Peak memory 206200 kb
Host smart-1399a9e4-8b49-4a4d-a054-909297be9292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26768
73117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2676873117
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1947387921
Short name T1689
Test name
Test status
Simulation time 136800660 ps
CPU time 0.78 seconds
Started Jun 29 06:36:36 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206196 kb
Host smart-e1f06afa-8fe7-4d39-9dfb-1b7c5bd334af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19473
87921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1947387921
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.793864730
Short name T1705
Test name
Test status
Simulation time 57525549 ps
CPU time 0.7 seconds
Started Jun 29 06:36:58 PM PDT 24
Finished Jun 29 06:37:00 PM PDT 24
Peak memory 206212 kb
Host smart-7ce4d274-da31-4821-85b5-a5f6f0af5e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79386
4730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.793864730
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3660658876
Short name T1736
Test name
Test status
Simulation time 648229890 ps
CPU time 1.72 seconds
Started Jun 29 06:36:51 PM PDT 24
Finished Jun 29 06:36:53 PM PDT 24
Peak memory 206272 kb
Host smart-197c8178-6888-4b67-bf79-52781dd85f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36606
58876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3660658876
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.464874653
Short name T799
Test name
Test status
Simulation time 185912065 ps
CPU time 2.24 seconds
Started Jun 29 06:36:41 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 206356 kb
Host smart-585f509e-8841-4849-af20-a117678b9f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46487
4653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.464874653
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.471582469
Short name T1892
Test name
Test status
Simulation time 182802504 ps
CPU time 0.85 seconds
Started Jun 29 06:36:47 PM PDT 24
Finished Jun 29 06:36:49 PM PDT 24
Peak memory 206216 kb
Host smart-334a5fbc-6f66-4554-a5ec-ffc5592847cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47158
2469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.471582469
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3120924737
Short name T870
Test name
Test status
Simulation time 137326251 ps
CPU time 0.78 seconds
Started Jun 29 06:36:38 PM PDT 24
Finished Jun 29 06:36:39 PM PDT 24
Peak memory 206212 kb
Host smart-1c6f0916-cd32-40bd-b2c2-64e9e9f6c092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31209
24737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3120924737
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.270474873
Short name T1236
Test name
Test status
Simulation time 209105986 ps
CPU time 0.9 seconds
Started Jun 29 06:36:35 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206212 kb
Host smart-d7683b9b-175f-4d47-912b-b9c86da42eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27047
4873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.270474873
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.203483028
Short name T1160
Test name
Test status
Simulation time 9247881847 ps
CPU time 64.27 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:37:49 PM PDT 24
Peak memory 206320 kb
Host smart-28088746-362f-4f84-a84e-44aa37a25fe3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=203483028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.203483028
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.2467720786
Short name T2317
Test name
Test status
Simulation time 232396224 ps
CPU time 0.91 seconds
Started Jun 29 06:36:34 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206212 kb
Host smart-35bf18f9-9225-4f53-971b-1b799767d6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24677
20786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.2467720786
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.1825850355
Short name T470
Test name
Test status
Simulation time 23358133446 ps
CPU time 26.89 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:37:12 PM PDT 24
Peak memory 206316 kb
Host smart-89a32343-397a-42d7-9a9c-6804c5cf5407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18258
50355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1825850355
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3989934445
Short name T320
Test name
Test status
Simulation time 3303159849 ps
CPU time 3.72 seconds
Started Jun 29 06:36:51 PM PDT 24
Finished Jun 29 06:36:55 PM PDT 24
Peak memory 206264 kb
Host smart-a5dc4571-5e7a-43c3-8b19-2ff7bef8fc2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39899
34445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3989934445
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1896156740
Short name T246
Test name
Test status
Simulation time 6290112751 ps
CPU time 43.92 seconds
Started Jun 29 06:36:36 PM PDT 24
Finished Jun 29 06:37:21 PM PDT 24
Peak memory 206440 kb
Host smart-f5d2e8f5-d7e5-4829-915a-0bfaff45da67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18961
56740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1896156740
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.4144883277
Short name T1764
Test name
Test status
Simulation time 4896441401 ps
CPU time 133.61 seconds
Started Jun 29 06:36:47 PM PDT 24
Finished Jun 29 06:39:01 PM PDT 24
Peak memory 206456 kb
Host smart-f761e005-7380-4a88-b864-0706e8b0e5a4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4144883277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.4144883277
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.479627249
Short name T2527
Test name
Test status
Simulation time 296039658 ps
CPU time 0.97 seconds
Started Jun 29 06:36:36 PM PDT 24
Finished Jun 29 06:36:38 PM PDT 24
Peak memory 206220 kb
Host smart-9d39e027-e92d-404c-97de-c87ffa8797a8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=479627249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.479627249
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.4020520307
Short name T2539
Test name
Test status
Simulation time 244917568 ps
CPU time 0.93 seconds
Started Jun 29 06:36:42 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 206208 kb
Host smart-933dc623-c0be-480d-a4c0-fe3fcbd83094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40205
20307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.4020520307
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2597677111
Short name T1435
Test name
Test status
Simulation time 5901112930 ps
CPU time 43.41 seconds
Started Jun 29 06:36:40 PM PDT 24
Finished Jun 29 06:37:24 PM PDT 24
Peak memory 206408 kb
Host smart-9362cd60-2848-4a6a-8a4d-2a7fc0e81d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25976
77111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2597677111
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3504748029
Short name T1669
Test name
Test status
Simulation time 5669086004 ps
CPU time 42.55 seconds
Started Jun 29 06:36:50 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206592 kb
Host smart-7f325767-9af5-478a-b98d-9aed11084368
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3504748029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3504748029
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1882187878
Short name T94
Test name
Test status
Simulation time 156073135 ps
CPU time 0.74 seconds
Started Jun 29 06:36:50 PM PDT 24
Finished Jun 29 06:36:51 PM PDT 24
Peak memory 206136 kb
Host smart-c2c189b1-fc79-4def-a711-6246b3dde1d4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1882187878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1882187878
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3601860473
Short name T1969
Test name
Test status
Simulation time 157343251 ps
CPU time 0.83 seconds
Started Jun 29 06:36:38 PM PDT 24
Finished Jun 29 06:36:39 PM PDT 24
Peak memory 206192 kb
Host smart-5880fe3f-fa16-447f-a986-3b4a5b9d93ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36018
60473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3601860473
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1175055223
Short name T2311
Test name
Test status
Simulation time 195727391 ps
CPU time 0.85 seconds
Started Jun 29 06:36:36 PM PDT 24
Finished Jun 29 06:36:38 PM PDT 24
Peak memory 206196 kb
Host smart-eba5f384-8537-4921-9b58-9192a2677be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11750
55223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1175055223
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2270661040
Short name T743
Test name
Test status
Simulation time 196162796 ps
CPU time 0.81 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:36:46 PM PDT 24
Peak memory 206204 kb
Host smart-8c7a63b0-88a3-4fb0-a82a-4cf35377ef28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22706
61040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2270661040
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2873008769
Short name T2479
Test name
Test status
Simulation time 158240826 ps
CPU time 0.81 seconds
Started Jun 29 06:36:38 PM PDT 24
Finished Jun 29 06:36:39 PM PDT 24
Peak memory 206188 kb
Host smart-c0452014-d93b-484f-961c-d2a96dd5a54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28730
08769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2873008769
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1498643846
Short name T2570
Test name
Test status
Simulation time 152100898 ps
CPU time 0.76 seconds
Started Jun 29 06:36:36 PM PDT 24
Finished Jun 29 06:36:38 PM PDT 24
Peak memory 206196 kb
Host smart-86be7161-929b-4276-bacd-6aefbede5692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14986
43846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1498643846
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2473234976
Short name T1778
Test name
Test status
Simulation time 167502127 ps
CPU time 0.82 seconds
Started Jun 29 06:36:35 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206200 kb
Host smart-291edebf-8b72-4543-a90a-38f2980fef01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24732
34976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2473234976
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.1681996527
Short name T2006
Test name
Test status
Simulation time 221889267 ps
CPU time 1.02 seconds
Started Jun 29 06:36:42 PM PDT 24
Finished Jun 29 06:36:43 PM PDT 24
Peak memory 206224 kb
Host smart-8581a9bb-e468-47ce-ac73-5b03232fee91
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1681996527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.1681996527
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3161051960
Short name T862
Test name
Test status
Simulation time 151257132 ps
CPU time 0.76 seconds
Started Jun 29 06:36:35 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206216 kb
Host smart-8ecc93ee-e95a-468d-a26c-e29230b0dfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31610
51960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3161051960
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2586562734
Short name T1043
Test name
Test status
Simulation time 41152899 ps
CPU time 0.68 seconds
Started Jun 29 06:36:54 PM PDT 24
Finished Jun 29 06:36:55 PM PDT 24
Peak memory 206212 kb
Host smart-9cdd4215-6513-4c03-aa17-4d3fbe67f652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25865
62734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2586562734
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2659115377
Short name T1226
Test name
Test status
Simulation time 10665496716 ps
CPU time 25.19 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:37:10 PM PDT 24
Peak memory 206504 kb
Host smart-b39680a3-d913-435a-bf6c-78b8549f60f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
15377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2659115377
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.775050583
Short name T1116
Test name
Test status
Simulation time 182890447 ps
CPU time 0.9 seconds
Started Jun 29 06:36:48 PM PDT 24
Finished Jun 29 06:36:50 PM PDT 24
Peak memory 206208 kb
Host smart-102dbfc9-da38-4a96-bf26-336898721866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77505
0583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.775050583
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3622680368
Short name T623
Test name
Test status
Simulation time 246617810 ps
CPU time 0.94 seconds
Started Jun 29 06:36:49 PM PDT 24
Finished Jun 29 06:36:50 PM PDT 24
Peak memory 206208 kb
Host smart-431ca999-ef48-46b5-bee1-485629863fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226
80368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3622680368
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.351583036
Short name T324
Test name
Test status
Simulation time 223562873 ps
CPU time 0.84 seconds
Started Jun 29 06:36:42 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 206208 kb
Host smart-df73a106-9586-440c-8d0d-23418d240ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35158
3036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.351583036
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2734874823
Short name T2604
Test name
Test status
Simulation time 197839280 ps
CPU time 0.85 seconds
Started Jun 29 06:36:36 PM PDT 24
Finished Jun 29 06:36:38 PM PDT 24
Peak memory 206200 kb
Host smart-38471381-1c9e-4347-ba67-9476fd26d0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27348
74823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2734874823
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.614814360
Short name T467
Test name
Test status
Simulation time 192365772 ps
CPU time 0.85 seconds
Started Jun 29 06:36:45 PM PDT 24
Finished Jun 29 06:36:47 PM PDT 24
Peak memory 206192 kb
Host smart-8675d89f-acae-415c-bda5-900d83d83f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61481
4360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.614814360
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.3969423950
Short name T1200
Test name
Test status
Simulation time 152891825 ps
CPU time 0.8 seconds
Started Jun 29 06:36:44 PM PDT 24
Finished Jun 29 06:36:47 PM PDT 24
Peak memory 206196 kb
Host smart-d958761e-7558-472c-9834-64438810bac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39694
23950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3969423950
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3935636810
Short name T409
Test name
Test status
Simulation time 151088531 ps
CPU time 0.8 seconds
Started Jun 29 06:36:37 PM PDT 24
Finished Jun 29 06:36:38 PM PDT 24
Peak memory 206196 kb
Host smart-373038a6-dd3d-4e75-9587-52af7ab2f6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39356
36810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3935636810
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1445929240
Short name T1504
Test name
Test status
Simulation time 233181535 ps
CPU time 0.85 seconds
Started Jun 29 06:36:44 PM PDT 24
Finished Jun 29 06:36:46 PM PDT 24
Peak memory 206216 kb
Host smart-80ceb356-fc65-4346-b620-2f095441882d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14459
29240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1445929240
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3948992295
Short name T355
Test name
Test status
Simulation time 4049600079 ps
CPU time 35.05 seconds
Started Jun 29 06:36:44 PM PDT 24
Finished Jun 29 06:37:20 PM PDT 24
Peak memory 206432 kb
Host smart-3afc8b97-dbbd-4a15-8720-7ed76cd689ef
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3948992295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3948992295
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.987172084
Short name T1803
Test name
Test status
Simulation time 184277582 ps
CPU time 0.76 seconds
Started Jun 29 06:36:44 PM PDT 24
Finished Jun 29 06:36:46 PM PDT 24
Peak memory 206140 kb
Host smart-0b8be171-2b75-44ff-9cb9-589f38af49f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98717
2084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.987172084
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2278011260
Short name T526
Test name
Test status
Simulation time 161215285 ps
CPU time 0.79 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:36:46 PM PDT 24
Peak memory 206196 kb
Host smart-c513f09e-7b6c-45b2-9fc9-9c10ed51214d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22780
11260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2278011260
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.1524380748
Short name T2402
Test name
Test status
Simulation time 3027178979 ps
CPU time 22.41 seconds
Started Jun 29 06:36:46 PM PDT 24
Finished Jun 29 06:37:10 PM PDT 24
Peak memory 206460 kb
Host smart-2ef1bb33-e40d-47a9-ab12-b60ae14a7238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15243
80748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1524380748
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.4145405062
Short name T545
Test name
Test status
Simulation time 44119151 ps
CPU time 0.63 seconds
Started Jun 29 06:36:45 PM PDT 24
Finished Jun 29 06:36:47 PM PDT 24
Peak memory 206196 kb
Host smart-c2b10039-bf2b-470b-b85b-edc86d6fd996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4145405062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.4145405062
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2911104826
Short name T537
Test name
Test status
Simulation time 3622588627 ps
CPU time 4.12 seconds
Started Jun 29 06:36:45 PM PDT 24
Finished Jun 29 06:36:51 PM PDT 24
Peak memory 206352 kb
Host smart-982b77ee-6830-4699-8234-e6f0783d4b87
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2911104826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2911104826
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.894382215
Short name T2621
Test name
Test status
Simulation time 13324455173 ps
CPU time 13.5 seconds
Started Jun 29 06:36:44 PM PDT 24
Finished Jun 29 06:36:59 PM PDT 24
Peak memory 206340 kb
Host smart-ab94a979-fec4-43f1-aad9-bac9eec10635
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=894382215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.894382215
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.4211828750
Short name T235
Test name
Test status
Simulation time 23345395873 ps
CPU time 21.4 seconds
Started Jun 29 06:37:02 PM PDT 24
Finished Jun 29 06:37:24 PM PDT 24
Peak memory 206404 kb
Host smart-63756a2c-de14-46a2-905f-9cc333009c27
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4211828750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.4211828750
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.261160635
Short name T335
Test name
Test status
Simulation time 226703224 ps
CPU time 0.89 seconds
Started Jun 29 06:37:00 PM PDT 24
Finished Jun 29 06:37:02 PM PDT 24
Peak memory 206208 kb
Host smart-ad117bc4-2cd8-457b-b303-fa50adfd19a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116
0635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.261160635
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.918219195
Short name T2342
Test name
Test status
Simulation time 168798753 ps
CPU time 0.8 seconds
Started Jun 29 06:36:41 PM PDT 24
Finished Jun 29 06:36:42 PM PDT 24
Peak memory 206196 kb
Host smart-0f4ecfdd-d77e-4fbc-b5e5-39a278410656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91821
9195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.918219195
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.285428558
Short name T2135
Test name
Test status
Simulation time 248528826 ps
CPU time 1 seconds
Started Jun 29 06:37:01 PM PDT 24
Finished Jun 29 06:37:03 PM PDT 24
Peak memory 206200 kb
Host smart-5c872ae4-a1ee-41b5-9eed-4abfc48eaeb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28542
8558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.285428558
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2486686211
Short name T1889
Test name
Test status
Simulation time 474623499 ps
CPU time 1.26 seconds
Started Jun 29 06:36:50 PM PDT 24
Finished Jun 29 06:36:56 PM PDT 24
Peak memory 206196 kb
Host smart-0cde02b8-8604-4906-8b2d-15a5b6e29a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24866
86211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2486686211
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2885356570
Short name T2275
Test name
Test status
Simulation time 14074834842 ps
CPU time 26.74 seconds
Started Jun 29 06:36:40 PM PDT 24
Finished Jun 29 06:37:07 PM PDT 24
Peak memory 206488 kb
Host smart-54d43ce3-112e-4fbd-b64c-5731304213bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28853
56570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2885356570
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.3463155183
Short name T2360
Test name
Test status
Simulation time 334797695 ps
CPU time 1.14 seconds
Started Jun 29 06:36:46 PM PDT 24
Finished Jun 29 06:36:49 PM PDT 24
Peak memory 206200 kb
Host smart-5e1cef57-27ed-49b4-98ae-89e526b896b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34631
55183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.3463155183
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2068165767
Short name T1292
Test name
Test status
Simulation time 152329337 ps
CPU time 0.78 seconds
Started Jun 29 06:36:42 PM PDT 24
Finished Jun 29 06:36:43 PM PDT 24
Peak memory 206196 kb
Host smart-7558426a-3fcc-4397-8bd9-02f21023a662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20681
65767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2068165767
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2999449008
Short name T2511
Test name
Test status
Simulation time 33670243 ps
CPU time 0.71 seconds
Started Jun 29 06:36:40 PM PDT 24
Finished Jun 29 06:36:41 PM PDT 24
Peak memory 206192 kb
Host smart-ad47eb8f-91a3-48b9-a8e0-361807f0ea7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29994
49008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2999449008
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.146353077
Short name T2378
Test name
Test status
Simulation time 925930213 ps
CPU time 2.14 seconds
Started Jun 29 06:36:51 PM PDT 24
Finished Jun 29 06:36:54 PM PDT 24
Peak memory 206340 kb
Host smart-e509fa08-f70c-40dd-8c34-ce5b49324478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14635
3077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.146353077
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3197652446
Short name T1500
Test name
Test status
Simulation time 235858502 ps
CPU time 1.92 seconds
Started Jun 29 06:36:49 PM PDT 24
Finished Jun 29 06:36:51 PM PDT 24
Peak memory 206292 kb
Host smart-5a6007f4-323b-443a-9548-040b411219ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31976
52446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3197652446
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.215106398
Short name T2418
Test name
Test status
Simulation time 195830539 ps
CPU time 0.81 seconds
Started Jun 29 06:36:48 PM PDT 24
Finished Jun 29 06:36:50 PM PDT 24
Peak memory 206216 kb
Host smart-289796af-1083-4115-87b5-5d7a4248539f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21510
6398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.215106398
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2733387458
Short name T1143
Test name
Test status
Simulation time 161480879 ps
CPU time 0.74 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 206212 kb
Host smart-063ead29-8105-48df-91a5-755e82734542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27333
87458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2733387458
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.4056257812
Short name T2512
Test name
Test status
Simulation time 197356997 ps
CPU time 0.9 seconds
Started Jun 29 06:36:48 PM PDT 24
Finished Jun 29 06:36:50 PM PDT 24
Peak memory 206152 kb
Host smart-ae5bc926-fac7-4974-8667-22c6dc016b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40562
57812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.4056257812
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.622905428
Short name T809
Test name
Test status
Simulation time 200776172 ps
CPU time 0.81 seconds
Started Jun 29 06:36:42 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 206200 kb
Host smart-a91ab7d9-f076-4a0a-8e84-57e5c2db7cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62290
5428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.622905428
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.902577684
Short name T2265
Test name
Test status
Simulation time 23272717199 ps
CPU time 24.44 seconds
Started Jun 29 06:36:45 PM PDT 24
Finished Jun 29 06:37:11 PM PDT 24
Peak memory 206316 kb
Host smart-cc95537a-7a05-4e50-ac45-6fbbeb048a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90257
7684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.902577684
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.424385664
Short name T1599
Test name
Test status
Simulation time 3322590753 ps
CPU time 4.78 seconds
Started Jun 29 06:36:46 PM PDT 24
Finished Jun 29 06:36:52 PM PDT 24
Peak memory 205720 kb
Host smart-d943432d-d36f-4d66-98bb-42a20b49f7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42438
5664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.424385664
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.877196483
Short name T1737
Test name
Test status
Simulation time 11632988915 ps
CPU time 84.69 seconds
Started Jun 29 06:36:47 PM PDT 24
Finished Jun 29 06:38:13 PM PDT 24
Peak memory 206432 kb
Host smart-31c382b4-a439-480d-ac01-69b6d8478426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87719
6483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.877196483
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1273631310
Short name T2182
Test name
Test status
Simulation time 5149808483 ps
CPU time 147.23 seconds
Started Jun 29 06:36:50 PM PDT 24
Finished Jun 29 06:39:18 PM PDT 24
Peak memory 206460 kb
Host smart-77affc9d-6b3f-4786-a834-6c9d54d49558
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1273631310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1273631310
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1829678278
Short name T690
Test name
Test status
Simulation time 230845868 ps
CPU time 0.92 seconds
Started Jun 29 06:36:41 PM PDT 24
Finished Jun 29 06:36:42 PM PDT 24
Peak memory 206220 kb
Host smart-315c38f9-4933-4021-a13c-71a3ae9bb629
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1829678278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1829678278
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.739322887
Short name T713
Test name
Test status
Simulation time 193387349 ps
CPU time 0.9 seconds
Started Jun 29 06:36:56 PM PDT 24
Finished Jun 29 06:36:57 PM PDT 24
Peak memory 206164 kb
Host smart-95ebb0a4-7365-45dd-ad99-67be078bb2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73932
2887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.739322887
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2018616440
Short name T776
Test name
Test status
Simulation time 4305624400 ps
CPU time 33.53 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 206436 kb
Host smart-8fc187ec-2e89-4ddb-b0c5-33bbe8de466f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20186
16440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2018616440
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.668458109
Short name T1428
Test name
Test status
Simulation time 3850958541 ps
CPU time 107.97 seconds
Started Jun 29 06:36:49 PM PDT 24
Finished Jun 29 06:38:38 PM PDT 24
Peak memory 206464 kb
Host smart-6d437992-3b64-49cc-bbfe-1cce7520699c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=668458109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.668458109
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.537994229
Short name T674
Test name
Test status
Simulation time 151042000 ps
CPU time 0.8 seconds
Started Jun 29 06:36:54 PM PDT 24
Finished Jun 29 06:36:55 PM PDT 24
Peak memory 206212 kb
Host smart-5fd2aa04-1f61-4264-be36-f63989463bfb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=537994229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.537994229
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2580364649
Short name T310
Test name
Test status
Simulation time 159520270 ps
CPU time 0.79 seconds
Started Jun 29 06:37:02 PM PDT 24
Finished Jun 29 06:37:03 PM PDT 24
Peak memory 206212 kb
Host smart-61a541f9-21a6-47d5-93f7-d19d55139a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25803
64649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2580364649
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2791851774
Short name T142
Test name
Test status
Simulation time 220611465 ps
CPU time 0.84 seconds
Started Jun 29 06:36:59 PM PDT 24
Finished Jun 29 06:37:00 PM PDT 24
Peak memory 206196 kb
Host smart-d7faa42c-b919-4781-a6b3-d4cc78bb47ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27918
51774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2791851774
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1999890584
Short name T2137
Test name
Test status
Simulation time 170726542 ps
CPU time 0.84 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:36:46 PM PDT 24
Peak memory 206176 kb
Host smart-eec66806-31f7-498f-be78-f69a216cd9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19998
90584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1999890584
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2549409220
Short name T2197
Test name
Test status
Simulation time 210775127 ps
CPU time 0.83 seconds
Started Jun 29 06:36:47 PM PDT 24
Finished Jun 29 06:36:48 PM PDT 24
Peak memory 206196 kb
Host smart-c2f7ec00-db46-4ef9-ba96-30bfa09e8a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25494
09220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2549409220
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2202889286
Short name T1311
Test name
Test status
Simulation time 150067960 ps
CPU time 0.72 seconds
Started Jun 29 06:36:41 PM PDT 24
Finished Jun 29 06:36:42 PM PDT 24
Peak memory 206196 kb
Host smart-29632c98-6a95-4ef9-b1fb-e80bb4231943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22028
89286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2202889286
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3454434082
Short name T1219
Test name
Test status
Simulation time 151753843 ps
CPU time 0.77 seconds
Started Jun 29 06:36:43 PM PDT 24
Finished Jun 29 06:36:46 PM PDT 24
Peak memory 206200 kb
Host smart-a0329ab1-7524-493a-979d-84bce7406199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34544
34082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3454434082
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.887639
Short name T428
Test name
Test status
Simulation time 222798542 ps
CPU time 0.98 seconds
Started Jun 29 06:36:57 PM PDT 24
Finished Jun 29 06:36:58 PM PDT 24
Peak memory 206212 kb
Host smart-604bc4c9-329c-4573-8d99-17b62b4d4654
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=887639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.887639
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3170656307
Short name T1024
Test name
Test status
Simulation time 177371600 ps
CPU time 0.82 seconds
Started Jun 29 06:36:51 PM PDT 24
Finished Jun 29 06:36:53 PM PDT 24
Peak memory 206216 kb
Host smart-6118a2dd-c5e3-4447-bff7-644f75d9dbac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31706
56307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3170656307
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1564665815
Short name T462
Test name
Test status
Simulation time 34926239 ps
CPU time 0.67 seconds
Started Jun 29 06:36:41 PM PDT 24
Finished Jun 29 06:36:43 PM PDT 24
Peak memory 206212 kb
Host smart-8d6949e2-536c-4a41-a6c9-0ca678ee1806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15646
65815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1564665815
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1578697864
Short name T1837
Test name
Test status
Simulation time 19055204482 ps
CPU time 43.88 seconds
Started Jun 29 06:36:58 PM PDT 24
Finished Jun 29 06:37:42 PM PDT 24
Peak memory 206432 kb
Host smart-b0e82298-e717-47fa-aa40-fbb25c661cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15786
97864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1578697864
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1974368137
Short name T2091
Test name
Test status
Simulation time 185363955 ps
CPU time 0.9 seconds
Started Jun 29 06:36:46 PM PDT 24
Finished Jun 29 06:36:48 PM PDT 24
Peak memory 205740 kb
Host smart-023ca25e-b701-4875-9b08-ca571681f238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19743
68137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1974368137
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1976660003
Short name T391
Test name
Test status
Simulation time 230152266 ps
CPU time 0.94 seconds
Started Jun 29 06:36:47 PM PDT 24
Finished Jun 29 06:36:49 PM PDT 24
Peak memory 206192 kb
Host smart-efbd2a09-b95d-4cef-aa7c-77255a7ec283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19766
60003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1976660003
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2798897649
Short name T1995
Test name
Test status
Simulation time 189088528 ps
CPU time 0.8 seconds
Started Jun 29 06:36:56 PM PDT 24
Finished Jun 29 06:36:57 PM PDT 24
Peak memory 206216 kb
Host smart-87d01e04-1c8e-4d96-a6b9-61344540a981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27988
97649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2798897649
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1524015017
Short name T1807
Test name
Test status
Simulation time 198858864 ps
CPU time 0.84 seconds
Started Jun 29 06:36:48 PM PDT 24
Finished Jun 29 06:36:49 PM PDT 24
Peak memory 206200 kb
Host smart-56e40315-f375-4d59-9ba1-e7fe5ff43deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15240
15017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1524015017
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.99085539
Short name T1518
Test name
Test status
Simulation time 178824624 ps
CPU time 0.88 seconds
Started Jun 29 06:36:45 PM PDT 24
Finished Jun 29 06:36:47 PM PDT 24
Peak memory 206196 kb
Host smart-ee473e1c-3098-4672-9345-8880893c6028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99085
539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.99085539
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.933545155
Short name T2202
Test name
Test status
Simulation time 168757871 ps
CPU time 0.75 seconds
Started Jun 29 06:36:54 PM PDT 24
Finished Jun 29 06:36:55 PM PDT 24
Peak memory 206196 kb
Host smart-6e20c237-fb7c-44cb-a416-268f627410c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93354
5155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.933545155
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1838664751
Short name T892
Test name
Test status
Simulation time 173221301 ps
CPU time 0.8 seconds
Started Jun 29 06:37:01 PM PDT 24
Finished Jun 29 06:37:02 PM PDT 24
Peak memory 206204 kb
Host smart-d2db96be-bda8-43d0-87d1-84d7da74fe71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18386
64751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1838664751
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2749741806
Short name T2533
Test name
Test status
Simulation time 223766795 ps
CPU time 0.98 seconds
Started Jun 29 06:37:02 PM PDT 24
Finished Jun 29 06:37:04 PM PDT 24
Peak memory 206216 kb
Host smart-d23f1ab5-56b3-4635-b0bf-d39da041de01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27497
41806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2749741806
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.3096351751
Short name T1105
Test name
Test status
Simulation time 4643371267 ps
CPU time 36.17 seconds
Started Jun 29 06:36:50 PM PDT 24
Finished Jun 29 06:37:26 PM PDT 24
Peak memory 206424 kb
Host smart-0eb5a392-b302-49d8-949c-1fdab721c389
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3096351751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.3096351751
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2487737681
Short name T1935
Test name
Test status
Simulation time 197717687 ps
CPU time 0.84 seconds
Started Jun 29 06:36:59 PM PDT 24
Finished Jun 29 06:37:00 PM PDT 24
Peak memory 206224 kb
Host smart-aeda4a74-fd02-443b-9552-c505a2f38348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24877
37681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2487737681
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3657037011
Short name T2513
Test name
Test status
Simulation time 183819151 ps
CPU time 0.89 seconds
Started Jun 29 06:37:04 PM PDT 24
Finished Jun 29 06:37:05 PM PDT 24
Peak memory 206196 kb
Host smart-6a8786e1-d787-4706-8a17-661c86cab446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36570
37011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3657037011
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.691921647
Short name T2179
Test name
Test status
Simulation time 3521725208 ps
CPU time 24.25 seconds
Started Jun 29 06:36:45 PM PDT 24
Finished Jun 29 06:37:10 PM PDT 24
Peak memory 206424 kb
Host smart-3d53849c-0208-4eca-bfd1-fbc0894c20fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69192
1647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.691921647
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.1376016403
Short name T398
Test name
Test status
Simulation time 44972694 ps
CPU time 0.68 seconds
Started Jun 29 06:37:10 PM PDT 24
Finished Jun 29 06:37:11 PM PDT 24
Peak memory 206212 kb
Host smart-689d52bd-4e3c-49ad-ae1f-958ab3a8fea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1376016403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1376016403
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2245264512
Short name T1678
Test name
Test status
Simulation time 4008361925 ps
CPU time 5.35 seconds
Started Jun 29 06:36:44 PM PDT 24
Finished Jun 29 06:36:51 PM PDT 24
Peak memory 206336 kb
Host smart-b37b0beb-4f6a-4a6a-8fd4-7b2bc6d43190
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2245264512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.2245264512
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.251309246
Short name T798
Test name
Test status
Simulation time 13367500831 ps
CPU time 16.1 seconds
Started Jun 29 06:36:47 PM PDT 24
Finished Jun 29 06:37:04 PM PDT 24
Peak memory 206488 kb
Host smart-50bb0554-346d-4b32-803f-fc2270904cdd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=251309246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.251309246
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.4018035901
Short name T2253
Test name
Test status
Simulation time 23349712707 ps
CPU time 24.45 seconds
Started Jun 29 06:36:54 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 206380 kb
Host smart-ccfdb9be-25df-469d-b72c-1b82e6114bef
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4018035901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.4018035901
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2207533915
Short name T1104
Test name
Test status
Simulation time 174823148 ps
CPU time 0.84 seconds
Started Jun 29 06:36:48 PM PDT 24
Finished Jun 29 06:36:50 PM PDT 24
Peak memory 206196 kb
Host smart-c7336228-da59-4ae2-bb85-a779306aa0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22075
33915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2207533915
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.1853520166
Short name T1630
Test name
Test status
Simulation time 143296212 ps
CPU time 0.78 seconds
Started Jun 29 06:36:53 PM PDT 24
Finished Jun 29 06:36:54 PM PDT 24
Peak memory 206192 kb
Host smart-1457069e-ed8e-45f7-bc14-5178ca0e4da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18535
20166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.1853520166
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1761348115
Short name T1422
Test name
Test status
Simulation time 340668479 ps
CPU time 1.19 seconds
Started Jun 29 06:36:47 PM PDT 24
Finished Jun 29 06:36:53 PM PDT 24
Peak memory 206196 kb
Host smart-ab362dcf-593f-40a3-9709-9d2d57da399e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17613
48115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1761348115
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.365707491
Short name T1215
Test name
Test status
Simulation time 1017267639 ps
CPU time 2.23 seconds
Started Jun 29 06:36:47 PM PDT 24
Finished Jun 29 06:36:50 PM PDT 24
Peak memory 206256 kb
Host smart-77a9352a-ae08-4843-804d-e627013ccaf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36570
7491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.365707491
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.1985067926
Short name T568
Test name
Test status
Simulation time 8027739597 ps
CPU time 17.47 seconds
Started Jun 29 06:37:00 PM PDT 24
Finished Jun 29 06:37:18 PM PDT 24
Peak memory 206448 kb
Host smart-2396acdb-508b-4e00-a3c4-bec152d4f5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19850
67926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1985067926
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2345327340
Short name T502
Test name
Test status
Simulation time 503595132 ps
CPU time 1.31 seconds
Started Jun 29 06:36:50 PM PDT 24
Finished Jun 29 06:36:51 PM PDT 24
Peak memory 206200 kb
Host smart-648dc631-6d22-4ad4-bdff-ea4db9a412bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23453
27340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2345327340
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.756880256
Short name T2545
Test name
Test status
Simulation time 158332078 ps
CPU time 0.79 seconds
Started Jun 29 06:36:58 PM PDT 24
Finished Jun 29 06:37:00 PM PDT 24
Peak memory 206204 kb
Host smart-5b23f074-ef28-4c8f-91db-330339424689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75688
0256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.756880256
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2046063746
Short name T2569
Test name
Test status
Simulation time 56335246 ps
CPU time 0.74 seconds
Started Jun 29 06:37:05 PM PDT 24
Finished Jun 29 06:37:06 PM PDT 24
Peak memory 206188 kb
Host smart-b4a7886c-ebf2-41dc-97b6-8a421e6d2a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20460
63746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2046063746
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.3838449825
Short name T2262
Test name
Test status
Simulation time 929426626 ps
CPU time 2.17 seconds
Started Jun 29 06:37:03 PM PDT 24
Finished Jun 29 06:37:05 PM PDT 24
Peak memory 206308 kb
Host smart-0a579e5b-a47a-4249-aed7-95acedefb3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38384
49825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.3838449825
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1056171541
Short name T2562
Test name
Test status
Simulation time 174375278 ps
CPU time 1.71 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:37:11 PM PDT 24
Peak memory 206256 kb
Host smart-49cd5173-c311-48b0-ad7a-6fe79b71935d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
71541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1056171541
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2010534825
Short name T2267
Test name
Test status
Simulation time 246247442 ps
CPU time 0.92 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:37:09 PM PDT 24
Peak memory 206204 kb
Host smart-acbc3773-9116-4f46-bfc3-ff3f70d3c488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20105
34825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2010534825
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1760573835
Short name T475
Test name
Test status
Simulation time 144137518 ps
CPU time 0.76 seconds
Started Jun 29 06:37:02 PM PDT 24
Finished Jun 29 06:37:03 PM PDT 24
Peak memory 206204 kb
Host smart-0d079e97-a385-4f20-8a77-8da98f9ac307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17605
73835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1760573835
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2416312026
Short name T1863
Test name
Test status
Simulation time 194083262 ps
CPU time 0.87 seconds
Started Jun 29 06:37:09 PM PDT 24
Finished Jun 29 06:37:11 PM PDT 24
Peak memory 206216 kb
Host smart-25a10991-6e0b-4cb8-95e5-927f69983dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24163
12026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2416312026
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3847715890
Short name T2546
Test name
Test status
Simulation time 7657920833 ps
CPU time 213.05 seconds
Started Jun 29 06:36:57 PM PDT 24
Finished Jun 29 06:40:31 PM PDT 24
Peak memory 206464 kb
Host smart-90ffa956-e40d-420c-923c-778119d4b74e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3847715890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3847715890
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.147694238
Short name T455
Test name
Test status
Simulation time 166145040 ps
CPU time 0.82 seconds
Started Jun 29 06:36:57 PM PDT 24
Finished Jun 29 06:36:58 PM PDT 24
Peak memory 206188 kb
Host smart-2a1d29ac-7e53-4a46-b8d0-1a5e493fba5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14769
4238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.147694238
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2284327579
Short name T910
Test name
Test status
Simulation time 23364220448 ps
CPU time 22.16 seconds
Started Jun 29 06:37:11 PM PDT 24
Finished Jun 29 06:37:34 PM PDT 24
Peak memory 206488 kb
Host smart-ac9aa18b-66ff-49f9-be3b-cf859414f14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22843
27579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2284327579
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.202833292
Short name T2218
Test name
Test status
Simulation time 3381507480 ps
CPU time 3.88 seconds
Started Jun 29 06:37:03 PM PDT 24
Finished Jun 29 06:37:07 PM PDT 24
Peak memory 206260 kb
Host smart-835cf1c8-9b9e-402a-bd24-d95ec4d15d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20283
3292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.202833292
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.320546471
Short name T1603
Test name
Test status
Simulation time 11045723772 ps
CPU time 105.89 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 206428 kb
Host smart-ed1c4705-605a-40dc-b4e2-44de53b74ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32054
6471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.320546471
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.4196598458
Short name T536
Test name
Test status
Simulation time 4972018699 ps
CPU time 138.74 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:39:26 PM PDT 24
Peak memory 206452 kb
Host smart-760b59b3-f270-4c99-ae7a-c20b10996cc9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4196598458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.4196598458
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3873158978
Short name T607
Test name
Test status
Simulation time 290360238 ps
CPU time 0.96 seconds
Started Jun 29 06:37:03 PM PDT 24
Finished Jun 29 06:37:05 PM PDT 24
Peak memory 206164 kb
Host smart-3416f0a4-164c-4d79-adea-097a2db083a1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3873158978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3873158978
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3063540652
Short name T1950
Test name
Test status
Simulation time 191247647 ps
CPU time 0.9 seconds
Started Jun 29 06:37:02 PM PDT 24
Finished Jun 29 06:37:03 PM PDT 24
Peak memory 206148 kb
Host smart-49203e26-9bc0-46b9-9e04-14b98e2e5b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30635
40652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3063540652
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.4023902560
Short name T2180
Test name
Test status
Simulation time 3113899445 ps
CPU time 28.78 seconds
Started Jun 29 06:36:58 PM PDT 24
Finished Jun 29 06:37:27 PM PDT 24
Peak memory 206464 kb
Host smart-223d6df8-4ab1-47b3-bbd4-9ce27c2c8f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40239
02560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.4023902560
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2886084357
Short name T2210
Test name
Test status
Simulation time 5026209673 ps
CPU time 132.83 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:39:20 PM PDT 24
Peak memory 206376 kb
Host smart-f104f13e-e3eb-440c-84d9-6836b6e74393
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2886084357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2886084357
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1629621835
Short name T1754
Test name
Test status
Simulation time 159778359 ps
CPU time 0.81 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:37:09 PM PDT 24
Peak memory 206216 kb
Host smart-124eac6d-88b4-4ccb-9684-e2b075a1f99c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1629621835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1629621835
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3486198648
Short name T708
Test name
Test status
Simulation time 155783500 ps
CPU time 0.88 seconds
Started Jun 29 06:37:03 PM PDT 24
Finished Jun 29 06:37:05 PM PDT 24
Peak memory 206372 kb
Host smart-74b0005f-6648-4b87-be02-c5e0ac62cd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34861
98648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3486198648
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1728486956
Short name T2575
Test name
Test status
Simulation time 201262455 ps
CPU time 0.94 seconds
Started Jun 29 06:37:06 PM PDT 24
Finished Jun 29 06:37:07 PM PDT 24
Peak memory 206148 kb
Host smart-ede300b0-98a4-43ed-9384-f840378e7bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17284
86956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1728486956
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.500278560
Short name T703
Test name
Test status
Simulation time 218873761 ps
CPU time 0.94 seconds
Started Jun 29 06:36:53 PM PDT 24
Finished Jun 29 06:36:54 PM PDT 24
Peak memory 206200 kb
Host smart-85016a1e-acb2-4985-a575-9a25a9cc3217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50027
8560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.500278560
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3881266607
Short name T570
Test name
Test status
Simulation time 178660908 ps
CPU time 0.83 seconds
Started Jun 29 06:36:55 PM PDT 24
Finished Jun 29 06:36:56 PM PDT 24
Peak memory 206196 kb
Host smart-7376fe59-c0d1-4ee2-a886-baca93b0df45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38812
66607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3881266607
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1274946856
Short name T395
Test name
Test status
Simulation time 189435109 ps
CPU time 0.81 seconds
Started Jun 29 06:36:55 PM PDT 24
Finished Jun 29 06:36:56 PM PDT 24
Peak memory 206216 kb
Host smart-d7d874e1-c99e-45cc-8018-83c7a8e0fc35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12749
46856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1274946856
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3420459198
Short name T1498
Test name
Test status
Simulation time 148218382 ps
CPU time 0.82 seconds
Started Jun 29 06:36:55 PM PDT 24
Finished Jun 29 06:36:56 PM PDT 24
Peak memory 206200 kb
Host smart-b1151e93-c1fa-4880-9c67-855126dc3505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34204
59198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3420459198
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1444356634
Short name T2365
Test name
Test status
Simulation time 219310705 ps
CPU time 0.96 seconds
Started Jun 29 06:37:01 PM PDT 24
Finished Jun 29 06:37:03 PM PDT 24
Peak memory 206224 kb
Host smart-5e85ce10-d576-4f2b-b25e-c44868fe7a7c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1444356634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1444356634
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1861443258
Short name T1153
Test name
Test status
Simulation time 152345615 ps
CPU time 0.79 seconds
Started Jun 29 06:37:11 PM PDT 24
Finished Jun 29 06:37:12 PM PDT 24
Peak memory 206212 kb
Host smart-201022ad-d315-4f3b-b083-a6ce95d552da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18614
43258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1861443258
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2568088095
Short name T41
Test name
Test status
Simulation time 43072543 ps
CPU time 0.68 seconds
Started Jun 29 06:36:57 PM PDT 24
Finished Jun 29 06:36:59 PM PDT 24
Peak memory 206212 kb
Host smart-73d33e74-aeae-4ab4-ad13-ca7e70daf8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25680
88095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2568088095
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.707055001
Short name T97
Test name
Test status
Simulation time 16455507457 ps
CPU time 38.69 seconds
Started Jun 29 06:37:04 PM PDT 24
Finished Jun 29 06:37:43 PM PDT 24
Peak memory 206448 kb
Host smart-003b2ebf-32f3-4bce-bf64-79dba1ca4474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70705
5001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.707055001
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.4163097149
Short name T2469
Test name
Test status
Simulation time 192481126 ps
CPU time 0.92 seconds
Started Jun 29 06:36:49 PM PDT 24
Finished Jun 29 06:36:56 PM PDT 24
Peak memory 206172 kb
Host smart-7185a6f6-c2e8-45e1-80d9-69fefbea74c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41630
97149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.4163097149
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2190197779
Short name T1213
Test name
Test status
Simulation time 212125334 ps
CPU time 0.91 seconds
Started Jun 29 06:37:05 PM PDT 24
Finished Jun 29 06:37:07 PM PDT 24
Peak memory 206204 kb
Host smart-997a71c9-06a2-4360-b00c-4629758d350d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21901
97779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2190197779
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1137384140
Short name T861
Test name
Test status
Simulation time 238637440 ps
CPU time 1.03 seconds
Started Jun 29 06:37:02 PM PDT 24
Finished Jun 29 06:37:03 PM PDT 24
Peak memory 206216 kb
Host smart-7456f957-19f1-4490-bbc8-a29759f858b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11373
84140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1137384140
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3872419279
Short name T1258
Test name
Test status
Simulation time 183077055 ps
CPU time 0.87 seconds
Started Jun 29 06:36:54 PM PDT 24
Finished Jun 29 06:36:55 PM PDT 24
Peak memory 206204 kb
Host smart-49c7db20-4e6d-4a1b-aa26-fad5fdabf199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38724
19279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3872419279
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2783186290
Short name T994
Test name
Test status
Simulation time 225276623 ps
CPU time 0.87 seconds
Started Jun 29 06:37:02 PM PDT 24
Finished Jun 29 06:37:04 PM PDT 24
Peak memory 206176 kb
Host smart-a420dc29-b990-4b52-9924-57efcb4b4cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27831
86290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2783186290
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2068966387
Short name T1816
Test name
Test status
Simulation time 147524425 ps
CPU time 0.79 seconds
Started Jun 29 06:37:02 PM PDT 24
Finished Jun 29 06:37:04 PM PDT 24
Peak memory 206208 kb
Host smart-5c079060-9029-4002-b6d3-e4e843aa73ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20689
66387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2068966387
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3070763166
Short name T494
Test name
Test status
Simulation time 149443396 ps
CPU time 0.78 seconds
Started Jun 29 06:36:56 PM PDT 24
Finished Jun 29 06:36:57 PM PDT 24
Peak memory 206196 kb
Host smart-24ec8a8a-ab98-49c4-8b4d-1348035b804c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30707
63166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3070763166
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1130797955
Short name T1966
Test name
Test status
Simulation time 223130061 ps
CPU time 0.98 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:37:10 PM PDT 24
Peak memory 206384 kb
Host smart-5a9552b5-ee73-4ba0-a15e-3948d024d329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11307
97955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1130797955
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.2300248849
Short name T1882
Test name
Test status
Simulation time 3152751982 ps
CPU time 92.86 seconds
Started Jun 29 06:37:02 PM PDT 24
Finished Jun 29 06:38:35 PM PDT 24
Peak memory 206488 kb
Host smart-25d98e07-7365-4527-8071-7d0bee4abae7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2300248849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.2300248849
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3593062462
Short name T1942
Test name
Test status
Simulation time 179005120 ps
CPU time 0.79 seconds
Started Jun 29 06:36:57 PM PDT 24
Finished Jun 29 06:36:58 PM PDT 24
Peak memory 206200 kb
Host smart-95900345-5336-4abf-bb79-605968aaa360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35930
62462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3593062462
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1391677677
Short name T330
Test name
Test status
Simulation time 182038328 ps
CPU time 0.83 seconds
Started Jun 29 06:36:57 PM PDT 24
Finished Jun 29 06:36:59 PM PDT 24
Peak memory 206140 kb
Host smart-58a26ca3-cb80-4683-9069-ad6b33c149f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13916
77677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1391677677
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2406531977
Short name T778
Test name
Test status
Simulation time 5175641081 ps
CPU time 34.92 seconds
Started Jun 29 06:37:09 PM PDT 24
Finished Jun 29 06:37:44 PM PDT 24
Peak memory 206480 kb
Host smart-581a7b55-bd75-40c7-bacf-4fb501ea7218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24065
31977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2406531977
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.1585127087
Short name T1720
Test name
Test status
Simulation time 40953070 ps
CPU time 0.68 seconds
Started Jun 29 06:37:20 PM PDT 24
Finished Jun 29 06:37:21 PM PDT 24
Peak memory 206180 kb
Host smart-c5d83122-3b23-4133-b09d-838907ff468d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1585127087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.1585127087
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3745109036
Short name T1481
Test name
Test status
Simulation time 4383499568 ps
CPU time 4.72 seconds
Started Jun 29 06:37:13 PM PDT 24
Finished Jun 29 06:37:18 PM PDT 24
Peak memory 206336 kb
Host smart-8521e3f6-af48-4a36-bd81-06b004e0c0e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3745109036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3745109036
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.480291331
Short name T1751
Test name
Test status
Simulation time 13394877645 ps
CPU time 12.05 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 206416 kb
Host smart-779dfe00-8cc3-4db2-9bad-1ccf34d977ab
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=480291331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.480291331
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2007335691
Short name T2200
Test name
Test status
Simulation time 23414608956 ps
CPU time 23.65 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206404 kb
Host smart-edce1328-a8cb-4b9a-b1d1-af3a044ae4f4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2007335691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.2007335691
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1310281109
Short name T1372
Test name
Test status
Simulation time 230749180 ps
CPU time 0.87 seconds
Started Jun 29 06:37:06 PM PDT 24
Finished Jun 29 06:37:07 PM PDT 24
Peak memory 206160 kb
Host smart-76677792-f5ba-4086-b482-3cfb6e11b489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13102
81109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1310281109
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.494543732
Short name T2141
Test name
Test status
Simulation time 176303190 ps
CPU time 0.83 seconds
Started Jun 29 06:37:14 PM PDT 24
Finished Jun 29 06:37:16 PM PDT 24
Peak memory 206204 kb
Host smart-9220e25e-cb45-42a6-afc8-9b7f1f6b6e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49454
3732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.494543732
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2462254745
Short name T1337
Test name
Test status
Simulation time 271047134 ps
CPU time 1.09 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:37:10 PM PDT 24
Peak memory 206196 kb
Host smart-19f5989c-9040-4d22-9f81-eacf4be1ccf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24622
54745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2462254745
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2610501531
Short name T184
Test name
Test status
Simulation time 1172364550 ps
CPU time 2.62 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:37:11 PM PDT 24
Peak memory 206212 kb
Host smart-2bd714bb-928c-45b3-b319-b21f55db01c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26105
01531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2610501531
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3904515132
Short name T552
Test name
Test status
Simulation time 15785423691 ps
CPU time 29.62 seconds
Started Jun 29 06:36:56 PM PDT 24
Finished Jun 29 06:37:26 PM PDT 24
Peak memory 206468 kb
Host smart-3038408b-56a4-4509-a652-c32cb1c3d71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39045
15132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3904515132
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2463701516
Short name T2395
Test name
Test status
Simulation time 354662785 ps
CPU time 1.36 seconds
Started Jun 29 06:37:10 PM PDT 24
Finished Jun 29 06:37:12 PM PDT 24
Peak memory 206200 kb
Host smart-4ca1a074-c4e5-4365-8556-5bc1d39a76c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24637
01516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2463701516
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1933683468
Short name T1767
Test name
Test status
Simulation time 201701129 ps
CPU time 0.83 seconds
Started Jun 29 06:37:11 PM PDT 24
Finished Jun 29 06:37:13 PM PDT 24
Peak memory 206192 kb
Host smart-57a9ce5e-1c8e-46f5-94ab-7dd2910b0b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19336
83468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1933683468
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.4125793517
Short name T2567
Test name
Test status
Simulation time 35236744 ps
CPU time 0.67 seconds
Started Jun 29 06:37:03 PM PDT 24
Finished Jun 29 06:37:04 PM PDT 24
Peak memory 206196 kb
Host smart-980293a3-40ba-472a-b7b0-a903ce87a106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
93517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.4125793517
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.627689100
Short name T1340
Test name
Test status
Simulation time 944942659 ps
CPU time 2.14 seconds
Started Jun 29 06:37:09 PM PDT 24
Finished Jun 29 06:37:12 PM PDT 24
Peak memory 206272 kb
Host smart-7a327d14-721e-43b0-ba2c-6aadd10d6efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62768
9100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.627689100
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.4202231827
Short name T1118
Test name
Test status
Simulation time 188823705 ps
CPU time 2.22 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:37:11 PM PDT 24
Peak memory 206264 kb
Host smart-b9f6d564-4fff-4050-a1a1-ecbf422da95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42022
31827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.4202231827
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2569783368
Short name T1948
Test name
Test status
Simulation time 190385471 ps
CPU time 0.92 seconds
Started Jun 29 06:37:04 PM PDT 24
Finished Jun 29 06:37:06 PM PDT 24
Peak memory 206192 kb
Host smart-6995f2df-f7ae-4b0c-bda6-40dc8971a564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25697
83368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2569783368
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.305474254
Short name T1098
Test name
Test status
Simulation time 137277835 ps
CPU time 0.79 seconds
Started Jun 29 06:36:57 PM PDT 24
Finished Jun 29 06:36:58 PM PDT 24
Peak memory 206164 kb
Host smart-452ec24a-0cca-4f50-8592-fc77e653692c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30547
4254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.305474254
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3853238071
Short name T2587
Test name
Test status
Simulation time 163906655 ps
CPU time 0.84 seconds
Started Jun 29 06:37:12 PM PDT 24
Finished Jun 29 06:37:13 PM PDT 24
Peak memory 206180 kb
Host smart-1fbb5064-e63b-4be1-a10f-1186b5144d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38532
38071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3853238071
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2531430192
Short name T991
Test name
Test status
Simulation time 187235301 ps
CPU time 0.81 seconds
Started Jun 29 06:37:05 PM PDT 24
Finished Jun 29 06:37:06 PM PDT 24
Peak memory 206196 kb
Host smart-bc579961-1b8f-41cc-bff4-4cc177368910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25314
30192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2531430192
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.4120096568
Short name T202
Test name
Test status
Simulation time 23259096058 ps
CPU time 24.62 seconds
Started Jun 29 06:37:06 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206316 kb
Host smart-65b0f113-7efb-44a4-b4eb-112b0685249a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41200
96568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.4120096568
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.3420284836
Short name T1166
Test name
Test status
Simulation time 3329502841 ps
CPU time 3.95 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:37:13 PM PDT 24
Peak memory 206256 kb
Host smart-6a6d9218-eef1-40c3-a4b3-c3843a20019f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34202
84836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3420284836
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.78284513
Short name T390
Test name
Test status
Simulation time 10469836242 ps
CPU time 80.78 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:38:29 PM PDT 24
Peak memory 206500 kb
Host smart-31ec10b1-70ce-4744-b8e5-ac7157fa05d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78284
513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.78284513
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1444610729
Short name T1231
Test name
Test status
Simulation time 5911518537 ps
CPU time 40.1 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:37:49 PM PDT 24
Peak memory 206460 kb
Host smart-ba17dff9-1163-4f2d-b83e-3c11cc959693
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1444610729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1444610729
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.4115186131
Short name T1285
Test name
Test status
Simulation time 236217592 ps
CPU time 0.91 seconds
Started Jun 29 06:37:03 PM PDT 24
Finished Jun 29 06:37:05 PM PDT 24
Peak memory 206220 kb
Host smart-0ecbc952-1207-412d-8d2e-ddce07b2fa35
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4115186131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.4115186131
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.891411480
Short name T838
Test name
Test status
Simulation time 202712685 ps
CPU time 0.9 seconds
Started Jun 29 06:37:04 PM PDT 24
Finished Jun 29 06:37:06 PM PDT 24
Peak memory 206216 kb
Host smart-160e9a54-e40a-4586-932f-f0ebbfe5a921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89141
1480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.891411480
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.4202131237
Short name T1606
Test name
Test status
Simulation time 4781896099 ps
CPU time 130.3 seconds
Started Jun 29 06:37:14 PM PDT 24
Finished Jun 29 06:39:25 PM PDT 24
Peak memory 206492 kb
Host smart-ff078886-4613-4839-a382-5017a72d099d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42021
31237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.4202131237
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3191083825
Short name T902
Test name
Test status
Simulation time 5654771662 ps
CPU time 151.02 seconds
Started Jun 29 06:37:03 PM PDT 24
Finished Jun 29 06:39:35 PM PDT 24
Peak memory 206488 kb
Host smart-163e42d9-2b09-4677-a236-c3148a9a861b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3191083825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3191083825
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.4287102337
Short name T576
Test name
Test status
Simulation time 243359481 ps
CPU time 0.94 seconds
Started Jun 29 06:37:11 PM PDT 24
Finished Jun 29 06:37:12 PM PDT 24
Peak memory 206216 kb
Host smart-db47c81c-5539-46aa-a386-19737fd04ad8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4287102337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.4287102337
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3268309709
Short name T1133
Test name
Test status
Simulation time 169630073 ps
CPU time 0.84 seconds
Started Jun 29 06:37:04 PM PDT 24
Finished Jun 29 06:37:05 PM PDT 24
Peak memory 206216 kb
Host smart-5bc051d3-b861-4309-934b-ab702056c0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32683
09709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3268309709
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.377117636
Short name T1765
Test name
Test status
Simulation time 237825780 ps
CPU time 0.94 seconds
Started Jun 29 06:37:05 PM PDT 24
Finished Jun 29 06:37:07 PM PDT 24
Peak memory 206204 kb
Host smart-fa3a1a16-306f-45cb-be8f-36710a5b7a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37711
7636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.377117636
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.819594672
Short name T1178
Test name
Test status
Simulation time 213732037 ps
CPU time 0.87 seconds
Started Jun 29 06:37:06 PM PDT 24
Finished Jun 29 06:37:08 PM PDT 24
Peak memory 206168 kb
Host smart-9f335fac-b351-4a21-9d6e-028c4452b68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81959
4672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.819594672
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3622669114
Short name T1564
Test name
Test status
Simulation time 213008356 ps
CPU time 0.87 seconds
Started Jun 29 06:37:05 PM PDT 24
Finished Jun 29 06:37:06 PM PDT 24
Peak memory 206172 kb
Host smart-3f83938c-c790-400d-b391-64d3b90981e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226
69114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3622669114
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.622764441
Short name T564
Test name
Test status
Simulation time 171318497 ps
CPU time 0.76 seconds
Started Jun 29 06:36:56 PM PDT 24
Finished Jun 29 06:36:57 PM PDT 24
Peak memory 206220 kb
Host smart-49cd3be7-0940-4e17-b27e-253a32db6b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62276
4441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.622764441
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.2485674201
Short name T412
Test name
Test status
Simulation time 206326032 ps
CPU time 0.95 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:37:09 PM PDT 24
Peak memory 206224 kb
Host smart-fa7717e4-2955-4328-ab0c-640c6400a81e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2485674201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.2485674201
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2239409379
Short name T1696
Test name
Test status
Simulation time 151142483 ps
CPU time 0.81 seconds
Started Jun 29 06:37:01 PM PDT 24
Finished Jun 29 06:37:02 PM PDT 24
Peak memory 206212 kb
Host smart-db4d9e1b-e786-4ff0-94b4-50e2f7479c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22394
09379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2239409379
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.776312206
Short name T913
Test name
Test status
Simulation time 91583225 ps
CPU time 0.69 seconds
Started Jun 29 06:37:09 PM PDT 24
Finished Jun 29 06:37:11 PM PDT 24
Peak memory 206212 kb
Host smart-e8d016cc-6422-468a-93a3-0f99d7c6233d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77631
2206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.776312206
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2624378696
Short name T260
Test name
Test status
Simulation time 12278425022 ps
CPU time 27.68 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:37:36 PM PDT 24
Peak memory 206516 kb
Host smart-01d08350-9fca-42cf-a7c7-014b07ecbc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26243
78696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2624378696
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2147624066
Short name T2117
Test name
Test status
Simulation time 211630401 ps
CPU time 0.94 seconds
Started Jun 29 06:37:14 PM PDT 24
Finished Jun 29 06:37:16 PM PDT 24
Peak memory 206192 kb
Host smart-5ef23b3b-8354-492e-818d-f6710eeaf36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21476
24066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2147624066
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3793450388
Short name T1592
Test name
Test status
Simulation time 162036561 ps
CPU time 0.8 seconds
Started Jun 29 06:37:11 PM PDT 24
Finished Jun 29 06:37:12 PM PDT 24
Peak memory 206212 kb
Host smart-468df766-5f6d-4d8f-8689-fc098317e859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37934
50388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3793450388
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3558052350
Short name T2498
Test name
Test status
Simulation time 237135920 ps
CPU time 0.93 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:37:10 PM PDT 24
Peak memory 206192 kb
Host smart-c364b561-45e9-46f4-81f0-dcc6c6107200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35580
52350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3558052350
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2574178104
Short name T1247
Test name
Test status
Simulation time 166825088 ps
CPU time 0.8 seconds
Started Jun 29 06:37:15 PM PDT 24
Finished Jun 29 06:37:16 PM PDT 24
Peak memory 206204 kb
Host smart-997b1945-f6cd-44ce-b279-4d235fad3eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25741
78104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2574178104
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.953059515
Short name T1163
Test name
Test status
Simulation time 178728480 ps
CPU time 0.92 seconds
Started Jun 29 06:37:04 PM PDT 24
Finished Jun 29 06:37:06 PM PDT 24
Peak memory 206196 kb
Host smart-c52c6dc6-50a1-4b8c-ba07-0bf11e6d3d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95305
9515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.953059515
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3727323037
Short name T487
Test name
Test status
Simulation time 171552232 ps
CPU time 0.82 seconds
Started Jun 29 06:37:19 PM PDT 24
Finished Jun 29 06:37:21 PM PDT 24
Peak memory 206192 kb
Host smart-aea5ccfe-7ee1-42a3-bd6a-677b9dfd7cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37273
23037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3727323037
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2118565511
Short name T37
Test name
Test status
Simulation time 151980919 ps
CPU time 0.83 seconds
Started Jun 29 06:37:18 PM PDT 24
Finished Jun 29 06:37:20 PM PDT 24
Peak memory 206368 kb
Host smart-367d20c9-a556-45cb-9593-b1609cbf550b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185
65511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2118565511
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2954144147
Short name T582
Test name
Test status
Simulation time 236657366 ps
CPU time 0.94 seconds
Started Jun 29 06:37:12 PM PDT 24
Finished Jun 29 06:37:13 PM PDT 24
Peak memory 206208 kb
Host smart-de9adb0f-115f-4f57-afa3-39dbfc76cdac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29541
44147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2954144147
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3703601290
Short name T1037
Test name
Test status
Simulation time 7146955591 ps
CPU time 51.69 seconds
Started Jun 29 06:37:08 PM PDT 24
Finished Jun 29 06:38:00 PM PDT 24
Peak memory 206368 kb
Host smart-42f49745-8079-4fcc-8be4-ddaf3f7be1bf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3703601290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3703601290
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.485563628
Short name T2181
Test name
Test status
Simulation time 194813209 ps
CPU time 0.85 seconds
Started Jun 29 06:37:09 PM PDT 24
Finished Jun 29 06:37:11 PM PDT 24
Peak memory 206192 kb
Host smart-8b5b14f5-8c91-4a30-bd5b-6aeaf243fa6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48556
3628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.485563628
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1429381534
Short name T2314
Test name
Test status
Simulation time 150130921 ps
CPU time 0.8 seconds
Started Jun 29 06:37:15 PM PDT 24
Finished Jun 29 06:37:16 PM PDT 24
Peak memory 206108 kb
Host smart-5b1ef075-0723-4d0d-99e5-0a16fc28719f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14293
81534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1429381534
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2377967575
Short name T1030
Test name
Test status
Simulation time 5643538496 ps
CPU time 152.04 seconds
Started Jun 29 06:37:14 PM PDT 24
Finished Jun 29 06:39:47 PM PDT 24
Peak memory 206440 kb
Host smart-f498b9fb-96c2-4b68-bc9e-43b7c1efc0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779
67575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2377967575
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2360525243
Short name T1514
Test name
Test status
Simulation time 104290455 ps
CPU time 0.73 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206160 kb
Host smart-a4ee2f10-cfdd-45ff-832b-f9d5bdb52728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2360525243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2360525243
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.483068311
Short name T2393
Test name
Test status
Simulation time 3585497670 ps
CPU time 4.35 seconds
Started Jun 29 06:37:13 PM PDT 24
Finished Jun 29 06:37:18 PM PDT 24
Peak memory 206280 kb
Host smart-082912d9-26ca-4494-98a7-43e346cd2cbb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=483068311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.483068311
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2352563588
Short name T808
Test name
Test status
Simulation time 13367547227 ps
CPU time 13.47 seconds
Started Jun 29 06:37:18 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206336 kb
Host smart-16429118-979f-467a-b8c1-8378685e4ac8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2352563588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2352563588
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2852993326
Short name T213
Test name
Test status
Simulation time 23333569732 ps
CPU time 23.16 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:37:48 PM PDT 24
Peak memory 206328 kb
Host smart-f5cfb996-e737-48bf-94e1-310e500837c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2852993326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2852993326
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1810794430
Short name T2521
Test name
Test status
Simulation time 229062568 ps
CPU time 0.93 seconds
Started Jun 29 06:37:14 PM PDT 24
Finished Jun 29 06:37:15 PM PDT 24
Peak memory 206196 kb
Host smart-aa3ecee7-3fb0-43d7-b454-0140e0bef5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
94430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1810794430
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.1041358952
Short name T617
Test name
Test status
Simulation time 183823909 ps
CPU time 0.8 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:37:08 PM PDT 24
Peak memory 206196 kb
Host smart-fc3112c3-0265-4538-8147-caf4e67c8daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10413
58952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.1041358952
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.3670569571
Short name T2046
Test name
Test status
Simulation time 187759426 ps
CPU time 0.87 seconds
Started Jun 29 06:37:14 PM PDT 24
Finished Jun 29 06:37:16 PM PDT 24
Peak memory 206196 kb
Host smart-868d82b0-6e54-450d-ab09-708b65ba8f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36705
69571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3670569571
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.206859535
Short name T2382
Test name
Test status
Simulation time 380057554 ps
CPU time 1.16 seconds
Started Jun 29 06:37:18 PM PDT 24
Finished Jun 29 06:37:20 PM PDT 24
Peak memory 206192 kb
Host smart-3e6c8c36-c1db-4852-b5c1-94706c2056ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20685
9535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.206859535
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.963893867
Short name T2281
Test name
Test status
Simulation time 20206410773 ps
CPU time 39.28 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206476 kb
Host smart-c74ef0ed-889d-478d-8512-5686dc90e16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96389
3867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.963893867
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1980776865
Short name T1951
Test name
Test status
Simulation time 423204762 ps
CPU time 1.31 seconds
Started Jun 29 06:37:19 PM PDT 24
Finished Jun 29 06:37:21 PM PDT 24
Peak memory 206220 kb
Host smart-ab3121ce-f952-4a7d-b4bf-75e16f38ccff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19807
76865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1980776865
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.2455555027
Short name T2234
Test name
Test status
Simulation time 142241300 ps
CPU time 0.83 seconds
Started Jun 29 06:37:15 PM PDT 24
Finished Jun 29 06:37:17 PM PDT 24
Peak memory 206196 kb
Host smart-38e2242b-ccef-4f60-b1ae-4be75091b4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24555
55027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.2455555027
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.578472060
Short name T619
Test name
Test status
Simulation time 44945598 ps
CPU time 0.69 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:37:09 PM PDT 24
Peak memory 206208 kb
Host smart-bbdf5330-aa88-443d-a73f-5daed914ead3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57847
2060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.578472060
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.4036407556
Short name T533
Test name
Test status
Simulation time 782269663 ps
CPU time 1.87 seconds
Started Jun 29 06:37:06 PM PDT 24
Finished Jun 29 06:37:09 PM PDT 24
Peak memory 206380 kb
Host smart-7afc6a0b-7ff5-4182-838c-9634ea7e18c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40364
07556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.4036407556
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1993201449
Short name T1798
Test name
Test status
Simulation time 162648377 ps
CPU time 1.36 seconds
Started Jun 29 06:37:16 PM PDT 24
Finished Jun 29 06:37:18 PM PDT 24
Peak memory 206332 kb
Host smart-f6c56b35-e67f-4357-a369-4b01ecaee2a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19932
01449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1993201449
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1749720584
Short name T2032
Test name
Test status
Simulation time 195731253 ps
CPU time 0.87 seconds
Started Jun 29 06:37:05 PM PDT 24
Finished Jun 29 06:37:06 PM PDT 24
Peak memory 206200 kb
Host smart-a6b46b6a-7132-4cc8-b48c-2a33a8721f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17497
20584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1749720584
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1012960873
Short name T591
Test name
Test status
Simulation time 165402979 ps
CPU time 0.75 seconds
Started Jun 29 06:37:16 PM PDT 24
Finished Jun 29 06:37:18 PM PDT 24
Peak memory 206212 kb
Host smart-5b0ba934-a744-4a0c-9108-80ddf24179b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10129
60873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1012960873
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.518227163
Short name T2113
Test name
Test status
Simulation time 178049017 ps
CPU time 0.92 seconds
Started Jun 29 06:37:14 PM PDT 24
Finished Jun 29 06:37:16 PM PDT 24
Peak memory 206212 kb
Host smart-e54ba947-f438-424f-857a-41761a9bb291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51822
7163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.518227163
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3389496001
Short name T2509
Test name
Test status
Simulation time 232874752 ps
CPU time 0.91 seconds
Started Jun 29 06:37:15 PM PDT 24
Finished Jun 29 06:37:16 PM PDT 24
Peak memory 206164 kb
Host smart-128293ea-ca3e-42d9-95a8-2f51dea0b2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33894
96001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3389496001
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.3458488271
Short name T2578
Test name
Test status
Simulation time 23308434389 ps
CPU time 23.61 seconds
Started Jun 29 06:37:17 PM PDT 24
Finished Jun 29 06:37:41 PM PDT 24
Peak memory 206316 kb
Host smart-e492da8d-b622-4166-a06b-f4ff3f15adf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34584
88271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.3458488271
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2272473560
Short name T432
Test name
Test status
Simulation time 3295301208 ps
CPU time 3.89 seconds
Started Jun 29 06:37:14 PM PDT 24
Finished Jun 29 06:37:18 PM PDT 24
Peak memory 206236 kb
Host smart-ca03b519-3ae7-44d7-bbee-2d4f54c8afb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22724
73560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2272473560
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.778293444
Short name T818
Test name
Test status
Simulation time 8125355741 ps
CPU time 79.65 seconds
Started Jun 29 06:37:12 PM PDT 24
Finished Jun 29 06:38:32 PM PDT 24
Peak memory 206480 kb
Host smart-ae485c71-3bd5-448d-8916-e337ccd39c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77829
3444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.778293444
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.4230014821
Short name T605
Test name
Test status
Simulation time 6716026523 ps
CPU time 181.49 seconds
Started Jun 29 06:37:11 PM PDT 24
Finished Jun 29 06:40:12 PM PDT 24
Peak memory 206488 kb
Host smart-cc4a0a83-85f7-4763-a018-b538d0b3917e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4230014821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.4230014821
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3791444091
Short name T513
Test name
Test status
Simulation time 263200310 ps
CPU time 0.93 seconds
Started Jun 29 06:37:15 PM PDT 24
Finished Jun 29 06:37:17 PM PDT 24
Peak memory 206220 kb
Host smart-37a9685b-a82e-4dfd-970d-6b7ea15cae5d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3791444091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3791444091
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3448684197
Short name T2482
Test name
Test status
Simulation time 238435022 ps
CPU time 0.92 seconds
Started Jun 29 06:37:07 PM PDT 24
Finished Jun 29 06:37:09 PM PDT 24
Peak memory 206216 kb
Host smart-b0ea08c3-3113-4f12-838e-6d2126440e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34486
84197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3448684197
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2885070477
Short name T1352
Test name
Test status
Simulation time 3484959774 ps
CPU time 33.29 seconds
Started Jun 29 06:37:09 PM PDT 24
Finished Jun 29 06:37:43 PM PDT 24
Peak memory 206376 kb
Host smart-fb23a245-f3e7-47de-8b9f-43cdcc45dbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28850
70477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2885070477
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1551039053
Short name T1616
Test name
Test status
Simulation time 6722850623 ps
CPU time 46.35 seconds
Started Jun 29 06:37:06 PM PDT 24
Finished Jun 29 06:37:53 PM PDT 24
Peak memory 206500 kb
Host smart-7f7be053-cc80-42cb-aa0a-851aab2b9dc8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1551039053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1551039053
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2976346481
Short name T2231
Test name
Test status
Simulation time 176957071 ps
CPU time 0.82 seconds
Started Jun 29 06:37:25 PM PDT 24
Finished Jun 29 06:37:26 PM PDT 24
Peak memory 206220 kb
Host smart-5b6b2cc2-f003-40d5-8d64-a25c8eef093d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2976346481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2976346481
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.947355226
Short name T2300
Test name
Test status
Simulation time 167765353 ps
CPU time 0.82 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:37:26 PM PDT 24
Peak memory 206216 kb
Host smart-4e51ed5b-5947-44fb-bf2d-fae4a0db0a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94735
5226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.947355226
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3979928348
Short name T2119
Test name
Test status
Simulation time 195741331 ps
CPU time 0.86 seconds
Started Jun 29 06:37:20 PM PDT 24
Finished Jun 29 06:37:22 PM PDT 24
Peak memory 206116 kb
Host smart-e9d880b7-f94d-417b-8117-2bcbf093fde7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39799
28348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3979928348
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3966433344
Short name T2011
Test name
Test status
Simulation time 161680877 ps
CPU time 0.82 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:37:25 PM PDT 24
Peak memory 206196 kb
Host smart-fc8138bb-fd31-45da-ae00-aad622052ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664
33344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3966433344
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3303038491
Short name T106
Test name
Test status
Simulation time 173151645 ps
CPU time 0.79 seconds
Started Jun 29 06:37:25 PM PDT 24
Finished Jun 29 06:37:27 PM PDT 24
Peak memory 206196 kb
Host smart-05b703ef-c406-4add-899b-2704c8819c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33030
38491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3303038491
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.667696727
Short name T649
Test name
Test status
Simulation time 176471692 ps
CPU time 0.83 seconds
Started Jun 29 06:37:17 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 206220 kb
Host smart-ce85e672-4143-4755-85d0-43d8e4c861d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66769
6727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.667696727
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2009778273
Short name T807
Test name
Test status
Simulation time 211620468 ps
CPU time 0.91 seconds
Started Jun 29 06:37:16 PM PDT 24
Finished Jun 29 06:37:18 PM PDT 24
Peak memory 206216 kb
Host smart-fd079fc4-5ef4-4ffb-9ef9-ab2eab206025
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2009778273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2009778273
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3399950203
Short name T1665
Test name
Test status
Simulation time 142042460 ps
CPU time 0.74 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:28 PM PDT 24
Peak memory 206152 kb
Host smart-185628b1-812b-4bf0-8ae0-977387d42c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33999
50203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3399950203
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.521573315
Short name T1273
Test name
Test status
Simulation time 56790913 ps
CPU time 0.72 seconds
Started Jun 29 06:37:18 PM PDT 24
Finished Jun 29 06:37:20 PM PDT 24
Peak memory 206212 kb
Host smart-45b6ac98-4491-437d-9403-108ad3c841a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52157
3315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.521573315
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2222211522
Short name T2483
Test name
Test status
Simulation time 11623789424 ps
CPU time 28.36 seconds
Started Jun 29 06:37:14 PM PDT 24
Finished Jun 29 06:37:42 PM PDT 24
Peak memory 206428 kb
Host smart-7bb7d8ab-9d40-48b3-b399-c95bf36338ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22222
11522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2222211522
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.808863132
Short name T1453
Test name
Test status
Simulation time 181073480 ps
CPU time 0.84 seconds
Started Jun 29 06:37:23 PM PDT 24
Finished Jun 29 06:37:24 PM PDT 24
Peak memory 206204 kb
Host smart-495c76ae-5206-49d3-99ee-cc81769e3595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80886
3132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.808863132
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1818645661
Short name T1901
Test name
Test status
Simulation time 221192110 ps
CPU time 0.98 seconds
Started Jun 29 06:37:33 PM PDT 24
Finished Jun 29 06:37:35 PM PDT 24
Peak memory 206212 kb
Host smart-64b62d54-eac2-4883-a001-2089510dd9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18186
45661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1818645661
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.4149694045
Short name T615
Test name
Test status
Simulation time 168136804 ps
CPU time 0.81 seconds
Started Jun 29 06:37:21 PM PDT 24
Finished Jun 29 06:37:22 PM PDT 24
Peak memory 206216 kb
Host smart-04c2cb5d-6c97-4dad-8391-e734100318fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41496
94045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.4149694045
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.131824246
Short name T2419
Test name
Test status
Simulation time 153393899 ps
CPU time 0.77 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:37:25 PM PDT 24
Peak memory 206212 kb
Host smart-d346df43-8a82-4304-8ae9-3e4382253fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13182
4246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.131824246
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1937680157
Short name T1979
Test name
Test status
Simulation time 145780241 ps
CPU time 0.8 seconds
Started Jun 29 06:37:18 PM PDT 24
Finished Jun 29 06:37:20 PM PDT 24
Peak memory 206192 kb
Host smart-ea4ef15d-ef74-4ba5-b85f-ad6dd82973f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19376
80157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1937680157
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2325397140
Short name T2327
Test name
Test status
Simulation time 157035028 ps
CPU time 0.75 seconds
Started Jun 29 06:37:16 PM PDT 24
Finished Jun 29 06:37:18 PM PDT 24
Peak memory 206196 kb
Host smart-6d3e13d6-88b2-4fa1-a0fb-d974666b8a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23253
97140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2325397140
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1190632803
Short name T608
Test name
Test status
Simulation time 156678491 ps
CPU time 0.81 seconds
Started Jun 29 06:37:21 PM PDT 24
Finished Jun 29 06:37:23 PM PDT 24
Peak memory 206196 kb
Host smart-92fcd42a-11d5-413b-ab05-4d858a5699d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11906
32803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1190632803
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2115479615
Short name T90
Test name
Test status
Simulation time 211219156 ps
CPU time 0.98 seconds
Started Jun 29 06:37:15 PM PDT 24
Finished Jun 29 06:37:17 PM PDT 24
Peak memory 206192 kb
Host smart-4118eac3-2f52-48e5-8ae0-73becf4bb04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21154
79615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2115479615
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.1840996692
Short name T159
Test name
Test status
Simulation time 4681964903 ps
CPU time 33.51 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206444 kb
Host smart-e1424c9c-54d3-4a31-80c6-fbe46d19100a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1840996692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.1840996692
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2271747159
Short name T651
Test name
Test status
Simulation time 229300573 ps
CPU time 0.84 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:28 PM PDT 24
Peak memory 206224 kb
Host smart-acbe7409-d8a6-4d9a-8d3c-1b3d18f6f981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22717
47159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2271747159
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2972400804
Short name T1977
Test name
Test status
Simulation time 224818490 ps
CPU time 0.86 seconds
Started Jun 29 06:37:22 PM PDT 24
Finished Jun 29 06:37:24 PM PDT 24
Peak memory 206196 kb
Host smart-46d2463f-91cd-4a5d-9c00-89e6aa3f055f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29724
00804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2972400804
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.1480392370
Short name T1749
Test name
Test status
Simulation time 7165813904 ps
CPU time 67.21 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:38:39 PM PDT 24
Peak memory 206440 kb
Host smart-9caa6d7e-b556-4c56-8e51-7059ac9bf8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14803
92370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.1480392370
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.1411598075
Short name T1134
Test name
Test status
Simulation time 47666253 ps
CPU time 0.7 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:37:32 PM PDT 24
Peak memory 206212 kb
Host smart-ffe6482e-8b55-40ba-963b-fed5ec6e96ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1411598075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.1411598075
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1019573446
Short name T2421
Test name
Test status
Simulation time 3887696160 ps
CPU time 4.64 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:37:30 PM PDT 24
Peak memory 206276 kb
Host smart-def2b698-8aab-41fb-92fd-096d95a0188a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1019573446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.1019573446
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.4262359681
Short name T1417
Test name
Test status
Simulation time 13319876128 ps
CPU time 12.13 seconds
Started Jun 29 06:37:16 PM PDT 24
Finished Jun 29 06:37:29 PM PDT 24
Peak memory 206428 kb
Host smart-cf39a85f-0c5b-4511-b69b-8a60e6e09086
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4262359681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.4262359681
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1255570633
Short name T2438
Test name
Test status
Simulation time 23391696285 ps
CPU time 23.16 seconds
Started Jun 29 06:37:17 PM PDT 24
Finished Jun 29 06:37:41 PM PDT 24
Peak memory 206400 kb
Host smart-5d6f31f9-a1ca-4bb1-a6f3-4cac9cdc4509
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1255570633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.1255570633
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.935794790
Short name T511
Test name
Test status
Simulation time 167216202 ps
CPU time 0.82 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:28 PM PDT 24
Peak memory 206212 kb
Host smart-f3006e3d-7e3e-4661-8233-d81e622cfdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93579
4790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.935794790
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3825833197
Short name T2131
Test name
Test status
Simulation time 142339595 ps
CPU time 0.77 seconds
Started Jun 29 06:37:15 PM PDT 24
Finished Jun 29 06:37:17 PM PDT 24
Peak memory 206196 kb
Host smart-5002674c-9d73-49fc-b38b-0ece128b6a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38258
33197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3825833197
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3869313565
Short name T2059
Test name
Test status
Simulation time 342114041 ps
CPU time 1.26 seconds
Started Jun 29 06:37:16 PM PDT 24
Finished Jun 29 06:37:18 PM PDT 24
Peak memory 206196 kb
Host smart-78f21362-6717-4ebe-b45c-b84b8325fe6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38693
13565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3869313565
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3571421423
Short name T113
Test name
Test status
Simulation time 718893342 ps
CPU time 1.74 seconds
Started Jun 29 06:37:18 PM PDT 24
Finished Jun 29 06:37:21 PM PDT 24
Peak memory 206264 kb
Host smart-106810c6-ac4d-4b49-9dea-9d716e1574d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35714
21423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3571421423
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1686047306
Short name T677
Test name
Test status
Simulation time 20993251064 ps
CPU time 41.67 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:38:11 PM PDT 24
Peak memory 206380 kb
Host smart-f31c914c-c86d-4824-a394-f65c0861ce1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16860
47306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1686047306
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1375377381
Short name T2073
Test name
Test status
Simulation time 338175103 ps
CPU time 1.2 seconds
Started Jun 29 06:37:14 PM PDT 24
Finished Jun 29 06:37:16 PM PDT 24
Peak memory 206176 kb
Host smart-68a1d3db-4b0e-49ee-8ff4-4c3e845eaac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753
77381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1375377381
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2138354387
Short name T1556
Test name
Test status
Simulation time 152127194 ps
CPU time 0.75 seconds
Started Jun 29 06:37:22 PM PDT 24
Finished Jun 29 06:37:23 PM PDT 24
Peak memory 206220 kb
Host smart-1d56adb7-5402-4b36-ba97-460c9e71342d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21383
54387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2138354387
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3523170320
Short name T2206
Test name
Test status
Simulation time 54375136 ps
CPU time 0.72 seconds
Started Jun 29 06:37:17 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 206180 kb
Host smart-9dfe872b-b986-4ebc-8b99-23499257364f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35231
70320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3523170320
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3665585522
Short name T1336
Test name
Test status
Simulation time 992645921 ps
CPU time 2.24 seconds
Started Jun 29 06:37:11 PM PDT 24
Finished Jun 29 06:37:14 PM PDT 24
Peak memory 206296 kb
Host smart-c5e6e7cc-496e-4342-831f-134da15c635f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36655
85522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3665585522
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1584391080
Short name T1637
Test name
Test status
Simulation time 225725687 ps
CPU time 1.51 seconds
Started Jun 29 06:37:17 PM PDT 24
Finished Jun 29 06:37:20 PM PDT 24
Peak memory 206288 kb
Host smart-7f706f25-feb6-494f-82d2-c1daca133396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15843
91080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1584391080
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1312857517
Short name T1904
Test name
Test status
Simulation time 150596037 ps
CPU time 0.81 seconds
Started Jun 29 06:37:17 PM PDT 24
Finished Jun 29 06:37:18 PM PDT 24
Peak memory 206200 kb
Host smart-20f7e358-652d-4024-9ff9-9b5990c8f4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13128
57517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1312857517
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1690066624
Short name T1793
Test name
Test status
Simulation time 151233414 ps
CPU time 0.73 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:37:25 PM PDT 24
Peak memory 206216 kb
Host smart-d84f407c-caa9-48c5-ad81-edd978024369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16900
66624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1690066624
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.520176028
Short name T1249
Test name
Test status
Simulation time 238015684 ps
CPU time 0.95 seconds
Started Jun 29 06:37:21 PM PDT 24
Finished Jun 29 06:37:23 PM PDT 24
Peak memory 206212 kb
Host smart-581ea730-456f-49bd-953b-a4bbea250536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52017
6028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.520176028
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3551592123
Short name T587
Test name
Test status
Simulation time 201811988 ps
CPU time 0.92 seconds
Started Jun 29 06:37:20 PM PDT 24
Finished Jun 29 06:37:22 PM PDT 24
Peak memory 206196 kb
Host smart-456db780-4a2d-4342-9d12-5e3ed9f66c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35515
92123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3551592123
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.4089506673
Short name T1831
Test name
Test status
Simulation time 23302163604 ps
CPU time 21.52 seconds
Started Jun 29 06:37:23 PM PDT 24
Finished Jun 29 06:37:45 PM PDT 24
Peak memory 206292 kb
Host smart-2cc76d73-8a67-4e3b-b752-f84776c3c543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40895
06673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.4089506673
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.755522674
Short name T2359
Test name
Test status
Simulation time 3311363679 ps
CPU time 4.42 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:37:29 PM PDT 24
Peak memory 206276 kb
Host smart-e1552f1f-b714-42de-9763-e32550111524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75552
2674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.755522674
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.483678348
Short name T1291
Test name
Test status
Simulation time 8239032037 ps
CPU time 224.12 seconds
Started Jun 29 06:37:25 PM PDT 24
Finished Jun 29 06:41:10 PM PDT 24
Peak memory 206468 kb
Host smart-3bd8d855-27cc-4628-98ca-47a7c7010f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48367
8348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.483678348
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.4024952806
Short name T325
Test name
Test status
Simulation time 6965461854 ps
CPU time 49.81 seconds
Started Jun 29 06:37:22 PM PDT 24
Finished Jun 29 06:38:13 PM PDT 24
Peak memory 206440 kb
Host smart-9334c4cf-8566-481c-b072-dcc148dc1134
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4024952806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.4024952806
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3098807208
Short name T1014
Test name
Test status
Simulation time 247060082 ps
CPU time 0.92 seconds
Started Jun 29 06:37:15 PM PDT 24
Finished Jun 29 06:37:17 PM PDT 24
Peak memory 206184 kb
Host smart-b98f49d5-ba5f-47bc-bcf6-2b764eb79f8c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3098807208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3098807208
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.4262879270
Short name T483
Test name
Test status
Simulation time 197504824 ps
CPU time 0.89 seconds
Started Jun 29 06:37:17 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 206216 kb
Host smart-3b340563-26a4-45cc-9110-596a106de105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42628
79270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.4262879270
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.2016086465
Short name T1710
Test name
Test status
Simulation time 5383801588 ps
CPU time 47.69 seconds
Started Jun 29 06:37:17 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206504 kb
Host smart-ea19b37a-2a0a-4332-9fbf-b45d0ff825b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20160
86465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.2016086465
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.407652047
Short name T702
Test name
Test status
Simulation time 5854270296 ps
CPU time 42 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:38:07 PM PDT 24
Peak memory 206632 kb
Host smart-6c6bc387-3994-4a58-bee6-978d63f02799
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=407652047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.407652047
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3822427879
Short name T374
Test name
Test status
Simulation time 157780436 ps
CPU time 0.79 seconds
Started Jun 29 06:37:19 PM PDT 24
Finished Jun 29 06:37:20 PM PDT 24
Peak memory 206220 kb
Host smart-eb852fad-948f-44e7-982f-d149e8e523bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3822427879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3822427879
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3211354652
Short name T1349
Test name
Test status
Simulation time 158389101 ps
CPU time 0.78 seconds
Started Jun 29 06:37:12 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 206216 kb
Host smart-71a0b117-452e-4a3b-aabe-87abd460541f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32113
54652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3211354652
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3148200024
Short name T131
Test name
Test status
Simulation time 168324074 ps
CPU time 0.81 seconds
Started Jun 29 06:37:17 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 206196 kb
Host smart-eeed1f3c-b557-4e55-8693-dd639d0dd7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31482
00024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3148200024
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3579850351
Short name T811
Test name
Test status
Simulation time 221229092 ps
CPU time 0.85 seconds
Started Jun 29 06:37:19 PM PDT 24
Finished Jun 29 06:37:21 PM PDT 24
Peak memory 206196 kb
Host smart-9d1bb732-e6e2-4b3b-a62b-76b9bdae5ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35798
50351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3579850351
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1314833665
Short name T1136
Test name
Test status
Simulation time 173557267 ps
CPU time 0.81 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:27 PM PDT 24
Peak memory 206188 kb
Host smart-aaf9ddda-b8b8-4cc6-a5c2-354449902970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13148
33665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1314833665
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2544969975
Short name T609
Test name
Test status
Simulation time 195089554 ps
CPU time 0.77 seconds
Started Jun 29 06:37:19 PM PDT 24
Finished Jun 29 06:37:20 PM PDT 24
Peak memory 206188 kb
Host smart-ffc4abd8-60b4-4257-a5c4-afd254109a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25449
69975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2544969975
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3048376271
Short name T2422
Test name
Test status
Simulation time 181595933 ps
CPU time 0.79 seconds
Started Jun 29 06:37:15 PM PDT 24
Finished Jun 29 06:37:17 PM PDT 24
Peak memory 206176 kb
Host smart-c0eeda00-ba56-4a9d-8f5e-962906439268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30483
76271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3048376271
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1562813087
Short name T1529
Test name
Test status
Simulation time 208863297 ps
CPU time 0.91 seconds
Started Jun 29 06:37:23 PM PDT 24
Finished Jun 29 06:37:25 PM PDT 24
Peak memory 206200 kb
Host smart-625327c0-c441-4912-9853-297c0a229adc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1562813087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1562813087
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.3337629143
Short name T1724
Test name
Test status
Simulation time 161546019 ps
CPU time 0.77 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:37:32 PM PDT 24
Peak memory 206192 kb
Host smart-d7f418ad-74b0-4f23-80df-4fe92d6a2367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33376
29143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.3337629143
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1637945623
Short name T1396
Test name
Test status
Simulation time 47518583 ps
CPU time 0.66 seconds
Started Jun 29 06:37:23 PM PDT 24
Finished Jun 29 06:37:24 PM PDT 24
Peak memory 206212 kb
Host smart-75cf44cb-30a8-4337-9169-eae3465848ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16379
45623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1637945623
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2793232642
Short name T258
Test name
Test status
Simulation time 9358748558 ps
CPU time 23.91 seconds
Started Jun 29 06:37:18 PM PDT 24
Finished Jun 29 06:37:43 PM PDT 24
Peak memory 206424 kb
Host smart-fc014b7f-04e4-4948-b270-31edddd3223b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27932
32642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2793232642
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.4172354945
Short name T1711
Test name
Test status
Simulation time 179206776 ps
CPU time 0.86 seconds
Started Jun 29 06:37:13 PM PDT 24
Finished Jun 29 06:37:14 PM PDT 24
Peak memory 206192 kb
Host smart-129abf71-e4d2-4bc8-aaaf-41a56e617df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41723
54945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.4172354945
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2837416552
Short name T865
Test name
Test status
Simulation time 193598014 ps
CPU time 0.84 seconds
Started Jun 29 06:37:18 PM PDT 24
Finished Jun 29 06:37:20 PM PDT 24
Peak memory 206212 kb
Host smart-fe67d148-3e1b-4dba-9a42-5adff9a30b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374
16552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2837416552
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1450880956
Short name T2304
Test name
Test status
Simulation time 205349794 ps
CPU time 0.87 seconds
Started Jun 29 06:37:13 PM PDT 24
Finished Jun 29 06:37:14 PM PDT 24
Peak memory 206188 kb
Host smart-14cbb163-8772-4258-9e94-ddbf6a881e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14508
80956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1450880956
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.412471499
Short name T1322
Test name
Test status
Simulation time 174532444 ps
CPU time 0.85 seconds
Started Jun 29 06:37:17 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 206200 kb
Host smart-f5a66e31-348c-458d-812d-23bdc8df87c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41247
1499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.412471499
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1261871318
Short name T1323
Test name
Test status
Simulation time 141782594 ps
CPU time 0.78 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:28 PM PDT 24
Peak memory 206192 kb
Host smart-c02434ae-7fd0-4bc2-855f-86b643c52051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12618
71318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1261871318
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1605310667
Short name T771
Test name
Test status
Simulation time 164867888 ps
CPU time 0.79 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:37:30 PM PDT 24
Peak memory 206160 kb
Host smart-72023765-6384-4d13-94b4-0e906f299656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16053
10667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1605310667
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.776663754
Short name T1326
Test name
Test status
Simulation time 154741830 ps
CPU time 0.8 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:28 PM PDT 24
Peak memory 206132 kb
Host smart-52455de0-b204-48b6-9c95-cd3be2654989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77666
3754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.776663754
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3870935713
Short name T2499
Test name
Test status
Simulation time 213898967 ps
CPU time 0.92 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:29 PM PDT 24
Peak memory 206212 kb
Host smart-826ac967-a448-40d6-807d-63b79197dde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
35713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3870935713
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.324119016
Short name T1706
Test name
Test status
Simulation time 4615944472 ps
CPU time 44.43 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:38:16 PM PDT 24
Peak memory 206448 kb
Host smart-1e7978ca-12d8-45f9-a6e3-fa69663f66a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=324119016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.324119016
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.305732731
Short name T2334
Test name
Test status
Simulation time 193654337 ps
CPU time 0.86 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:28 PM PDT 24
Peak memory 206220 kb
Host smart-d014a3b4-2132-4f3a-8cfb-e390d2b3f8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30573
2731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.305732731
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2359955063
Short name T559
Test name
Test status
Simulation time 168136590 ps
CPU time 0.83 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206188 kb
Host smart-6ef010f0-0854-4976-8f65-24ab28174fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23599
55063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2359955063
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1887089803
Short name T2270
Test name
Test status
Simulation time 4248106279 ps
CPU time 118.25 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:39:30 PM PDT 24
Peak memory 206440 kb
Host smart-55ecf472-a744-4814-8ee1-299aca0fee25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18870
89803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1887089803
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.4137848427
Short name T441
Test name
Test status
Simulation time 43849418 ps
CPU time 0.67 seconds
Started Jun 29 06:37:45 PM PDT 24
Finished Jun 29 06:37:46 PM PDT 24
Peak memory 206388 kb
Host smart-d5b89e18-f7e1-4467-a045-3571782e54d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4137848427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.4137848427
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3652660843
Short name T2213
Test name
Test status
Simulation time 4080456249 ps
CPU time 5.09 seconds
Started Jun 29 06:37:25 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206272 kb
Host smart-e76304fa-f953-429e-9430-151989e6d80a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3652660843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.3652660843
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.4045918117
Short name T12
Test name
Test status
Simulation time 13363633080 ps
CPU time 13.43 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:40 PM PDT 24
Peak memory 206432 kb
Host smart-44130aab-5e5e-4a2e-a1ba-8593b628e68b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4045918117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.4045918117
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.252247085
Short name T14
Test name
Test status
Simulation time 23420474151 ps
CPU time 24.7 seconds
Started Jun 29 06:37:22 PM PDT 24
Finished Jun 29 06:37:48 PM PDT 24
Peak memory 206264 kb
Host smart-051de13b-10e8-4e12-b891-bc4c9bea1ad0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=252247085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.252247085
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.295958539
Short name T2031
Test name
Test status
Simulation time 184750244 ps
CPU time 0.87 seconds
Started Jun 29 06:37:20 PM PDT 24
Finished Jun 29 06:37:21 PM PDT 24
Peak memory 206216 kb
Host smart-847b3c71-c235-4b01-8f25-2d97a6b2687a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29595
8539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.295958539
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.1400511571
Short name T1480
Test name
Test status
Simulation time 167585754 ps
CPU time 0.84 seconds
Started Jun 29 06:37:20 PM PDT 24
Finished Jun 29 06:37:21 PM PDT 24
Peak memory 206192 kb
Host smart-10a8abfe-5ff1-427a-8c40-55c701e503a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14005
11571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.1400511571
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.4256552599
Short name T1866
Test name
Test status
Simulation time 319991239 ps
CPU time 1.13 seconds
Started Jun 29 06:37:25 PM PDT 24
Finished Jun 29 06:37:26 PM PDT 24
Peak memory 206196 kb
Host smart-f7be8054-a0ca-4a5f-b155-746521636ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42565
52599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.4256552599
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.958936372
Short name T165
Test name
Test status
Simulation time 881107910 ps
CPU time 1.99 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:29 PM PDT 24
Peak memory 206260 kb
Host smart-081494cc-f2d6-4baa-ac44-e1f0053e6294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95893
6372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.958936372
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3645346017
Short name T1555
Test name
Test status
Simulation time 8857944080 ps
CPU time 17.24 seconds
Started Jun 29 06:37:18 PM PDT 24
Finished Jun 29 06:37:36 PM PDT 24
Peak memory 206400 kb
Host smart-c213cebd-a908-4069-a429-8bbdb13c7ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36453
46017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3645346017
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.589920454
Short name T2277
Test name
Test status
Simulation time 439385915 ps
CPU time 1.33 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206212 kb
Host smart-382c24ea-a19a-4509-9ab4-517c931ce7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58992
0454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.589920454
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.494042054
Short name T2144
Test name
Test status
Simulation time 135579947 ps
CPU time 0.76 seconds
Started Jun 29 06:37:22 PM PDT 24
Finished Jun 29 06:37:24 PM PDT 24
Peak memory 206200 kb
Host smart-b9964b2d-bf74-45a4-a1fa-a31345899a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49404
2054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.494042054
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2523891958
Short name T1491
Test name
Test status
Simulation time 57338619 ps
CPU time 0.72 seconds
Started Jun 29 06:37:20 PM PDT 24
Finished Jun 29 06:37:22 PM PDT 24
Peak memory 206196 kb
Host smart-74848cc1-a731-4bbe-b638-df3755a61cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25238
91958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2523891958
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.4054887188
Short name T1415
Test name
Test status
Simulation time 907462681 ps
CPU time 2.06 seconds
Started Jun 29 06:37:32 PM PDT 24
Finished Jun 29 06:37:35 PM PDT 24
Peak memory 206292 kb
Host smart-8f25d4dd-8f88-46d7-b8a1-0114852686d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40548
87188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.4054887188
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3147880033
Short name T1609
Test name
Test status
Simulation time 244800098 ps
CPU time 1.2 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:28 PM PDT 24
Peak memory 206324 kb
Host smart-0e1ef5f9-d4f7-4200-ad13-593e1d88d988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31478
80033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3147880033
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.534778331
Short name T1762
Test name
Test status
Simulation time 225107445 ps
CPU time 0.88 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:28 PM PDT 24
Peak memory 206212 kb
Host smart-bcd2d898-3e32-42cd-b266-8dbcaa9ff499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53477
8331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.534778331
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.849187490
Short name T458
Test name
Test status
Simulation time 139768025 ps
CPU time 0.8 seconds
Started Jun 29 06:37:21 PM PDT 24
Finished Jun 29 06:37:22 PM PDT 24
Peak memory 206212 kb
Host smart-8d0a11b6-78da-4fd0-aa0f-1b02e592aab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84918
7490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.849187490
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3365419420
Short name T312
Test name
Test status
Simulation time 224829777 ps
CPU time 0.91 seconds
Started Jun 29 06:37:21 PM PDT 24
Finished Jun 29 06:37:22 PM PDT 24
Peak memory 206216 kb
Host smart-66fdd406-cf08-45be-ab66-6c894eafd9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33654
19420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3365419420
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.4214827649
Short name T1513
Test name
Test status
Simulation time 4950779987 ps
CPU time 33.43 seconds
Started Jun 29 06:37:20 PM PDT 24
Finished Jun 29 06:37:54 PM PDT 24
Peak memory 206416 kb
Host smart-430478ec-aede-4d56-ad8e-183138e15333
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4214827649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.4214827649
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2239589307
Short name T2041
Test name
Test status
Simulation time 231312620 ps
CPU time 0.87 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:37:29 PM PDT 24
Peak memory 206176 kb
Host smart-85fc4a88-cdce-4ea5-a2fa-e64596cf19e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22395
89307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2239589307
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.126563399
Short name T1123
Test name
Test status
Simulation time 23341374561 ps
CPU time 26.55 seconds
Started Jun 29 06:37:22 PM PDT 24
Finished Jun 29 06:37:49 PM PDT 24
Peak memory 206320 kb
Host smart-a72a9306-35d4-411a-af66-db2fb95f1b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12656
3399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.126563399
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.3873006051
Short name T2496
Test name
Test status
Simulation time 3293394787 ps
CPU time 3.8 seconds
Started Jun 29 06:37:31 PM PDT 24
Finished Jun 29 06:37:36 PM PDT 24
Peak memory 206256 kb
Host smart-b827c2f9-74b5-4f7b-88a3-ca093daf1547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38730
06051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.3873006051
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3747441634
Short name T1350
Test name
Test status
Simulation time 5437155166 ps
CPU time 50.11 seconds
Started Jun 29 06:37:22 PM PDT 24
Finished Jun 29 06:38:13 PM PDT 24
Peak memory 206468 kb
Host smart-d8fe555d-b4de-4af2-996a-3f12e34ac0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37474
41634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3747441634
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.567892976
Short name T563
Test name
Test status
Simulation time 3826158698 ps
CPU time 98.76 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:39:08 PM PDT 24
Peak memory 206452 kb
Host smart-b3eb58bd-546d-4fbf-9295-ed365000e5fb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=567892976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.567892976
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.3067959501
Short name T463
Test name
Test status
Simulation time 257069544 ps
CPU time 0.94 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206368 kb
Host smart-e3f9df38-09b8-4dba-b360-7ccc771a7056
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3067959501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.3067959501
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.843064657
Short name T596
Test name
Test status
Simulation time 200521780 ps
CPU time 0.89 seconds
Started Jun 29 06:37:23 PM PDT 24
Finished Jun 29 06:37:25 PM PDT 24
Peak memory 206180 kb
Host smart-b28cac1d-bbcd-4b4e-afc8-a6b3e3335f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84306
4657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.843064657
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.915480907
Short name T6
Test name
Test status
Simulation time 5254858075 ps
CPU time 149.16 seconds
Started Jun 29 06:37:22 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206376 kb
Host smart-5c43f2df-2685-4bcb-a0bb-8a1b0644cefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91548
0907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.915480907
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.528414048
Short name T1652
Test name
Test status
Simulation time 5346571854 ps
CPU time 38.36 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206468 kb
Host smart-11122dc9-c613-4250-967b-81ab1e32b3e5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=528414048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.528414048
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2175916737
Short name T1046
Test name
Test status
Simulation time 173862838 ps
CPU time 0.86 seconds
Started Jun 29 06:37:25 PM PDT 24
Finished Jun 29 06:37:27 PM PDT 24
Peak memory 206220 kb
Host smart-7a96478b-c28f-4610-a2db-0982d55506c6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2175916737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2175916737
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.771864970
Short name T1780
Test name
Test status
Simulation time 148017616 ps
CPU time 0.79 seconds
Started Jun 29 06:37:18 PM PDT 24
Finished Jun 29 06:37:20 PM PDT 24
Peak memory 206216 kb
Host smart-172887d0-3a26-45e0-ab62-b733781c2ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77186
4970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.771864970
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3917006478
Short name T2519
Test name
Test status
Simulation time 183655995 ps
CPU time 0.77 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:29 PM PDT 24
Peak memory 206200 kb
Host smart-25f74017-4d2b-4087-8fbf-e2ceaf7ec71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39170
06478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3917006478
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.526061443
Short name T1745
Test name
Test status
Simulation time 201427511 ps
CPU time 0.93 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:37:29 PM PDT 24
Peak memory 206216 kb
Host smart-f0664f61-9541-44c7-8c88-30b7f5a2c1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52606
1443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.526061443
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3697536184
Short name T830
Test name
Test status
Simulation time 166797231 ps
CPU time 0.79 seconds
Started Jun 29 06:37:21 PM PDT 24
Finished Jun 29 06:37:23 PM PDT 24
Peak memory 206216 kb
Host smart-1bc29502-032d-467c-99d4-bb596323003b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36975
36184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3697536184
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2811974558
Short name T1127
Test name
Test status
Simulation time 151347549 ps
CPU time 0.8 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:29 PM PDT 24
Peak memory 206208 kb
Host smart-98385ed1-38c4-4f14-8893-f0da370bbbe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28119
74558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2811974558
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.1259818022
Short name T1475
Test name
Test status
Simulation time 225237184 ps
CPU time 0.87 seconds
Started Jun 29 06:37:25 PM PDT 24
Finished Jun 29 06:37:26 PM PDT 24
Peak memory 206224 kb
Host smart-f75e7d87-3993-4c51-87ea-4df2dae87b83
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1259818022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.1259818022
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.566266007
Short name T788
Test name
Test status
Simulation time 144823048 ps
CPU time 0.81 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206212 kb
Host smart-97815919-2a98-4205-be5d-d036ecfddd69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56626
6007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.566266007
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1395141809
Short name T1820
Test name
Test status
Simulation time 13125120984 ps
CPU time 27.54 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:37:55 PM PDT 24
Peak memory 206488 kb
Host smart-e5a3b356-cbc4-428c-873f-159ad99e6509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13951
41809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1395141809
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2789420846
Short name T981
Test name
Test status
Simulation time 158473404 ps
CPU time 0.78 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:37:26 PM PDT 24
Peak memory 206192 kb
Host smart-18b90e70-3cc6-40c3-8b5f-0922502d9546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27894
20846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2789420846
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2306293330
Short name T1639
Test name
Test status
Simulation time 224802550 ps
CPU time 0.9 seconds
Started Jun 29 06:37:20 PM PDT 24
Finished Jun 29 06:37:22 PM PDT 24
Peak memory 206212 kb
Host smart-8eaae944-be70-407b-8da4-4195d0231e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23062
93330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2306293330
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.4072316358
Short name T2614
Test name
Test status
Simulation time 221252810 ps
CPU time 0.91 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:37:30 PM PDT 24
Peak memory 206204 kb
Host smart-54425123-cc36-4317-b36a-d48c80e38d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40723
16358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.4072316358
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3135383102
Short name T2172
Test name
Test status
Simulation time 207431293 ps
CPU time 0.86 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:37:26 PM PDT 24
Peak memory 206200 kb
Host smart-cf6c8f46-11cf-4666-be72-1835b3abe40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31353
83102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3135383102
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3373041299
Short name T2325
Test name
Test status
Simulation time 166591404 ps
CPU time 0.82 seconds
Started Jun 29 06:37:19 PM PDT 24
Finished Jun 29 06:37:21 PM PDT 24
Peak memory 206220 kb
Host smart-e35dee37-c33a-4e72-84e8-9a9dc992da5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33730
41299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3373041299
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.149612767
Short name T471
Test name
Test status
Simulation time 149106207 ps
CPU time 0.8 seconds
Started Jun 29 06:37:22 PM PDT 24
Finished Jun 29 06:37:23 PM PDT 24
Peak memory 206196 kb
Host smart-e51496a0-568b-49d7-9396-2a5aa41a333c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14961
2767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.149612767
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1259676793
Short name T393
Test name
Test status
Simulation time 158844600 ps
CPU time 0.77 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206192 kb
Host smart-082962a4-8417-4fc0-8445-c09ea26d66e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12596
76793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1259676793
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.171695254
Short name T976
Test name
Test status
Simulation time 247232324 ps
CPU time 1.01 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:37:30 PM PDT 24
Peak memory 206216 kb
Host smart-aaef146d-0fb2-4639-8d38-8646a0d677b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17169
5254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.171695254
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2099276558
Short name T2115
Test name
Test status
Simulation time 6671058616 ps
CPU time 64.07 seconds
Started Jun 29 06:37:24 PM PDT 24
Finished Jun 29 06:38:29 PM PDT 24
Peak memory 206360 kb
Host smart-8cb2dee4-d19e-44f5-b9ba-5be026419d82
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2099276558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2099276558
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1636172111
Short name T925
Test name
Test status
Simulation time 163523970 ps
CPU time 0.78 seconds
Started Jun 29 06:37:25 PM PDT 24
Finished Jun 29 06:37:27 PM PDT 24
Peak memory 206224 kb
Host smart-c8f6bf6b-d57d-4e91-a368-14ef434a01cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16361
72111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1636172111
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3192036693
Short name T508
Test name
Test status
Simulation time 181537969 ps
CPU time 0.86 seconds
Started Jun 29 06:37:43 PM PDT 24
Finished Jun 29 06:37:45 PM PDT 24
Peak memory 206196 kb
Host smart-a81800b4-cee9-4ef9-bac5-58a095853b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31920
36693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3192036693
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.3866864406
Short name T1278
Test name
Test status
Simulation time 3984006055 ps
CPU time 38.95 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:38:10 PM PDT 24
Peak memory 206396 kb
Host smart-01977921-a696-4395-981f-8b816a4cd89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38668
64406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.3866864406
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.987399186
Short name T1041
Test name
Test status
Simulation time 53031814 ps
CPU time 0.76 seconds
Started Jun 29 06:37:38 PM PDT 24
Finished Jun 29 06:37:39 PM PDT 24
Peak memory 206212 kb
Host smart-21915879-12f9-4e24-9641-ff13c2f804f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=987399186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.987399186
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.2169178115
Short name T1209
Test name
Test status
Simulation time 4061483212 ps
CPU time 4.98 seconds
Started Jun 29 06:37:37 PM PDT 24
Finished Jun 29 06:37:42 PM PDT 24
Peak memory 206276 kb
Host smart-61096774-9094-43d1-8102-0ce0ab579305
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2169178115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.2169178115
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.2902811124
Short name T2087
Test name
Test status
Simulation time 13311717071 ps
CPU time 12.31 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:37:40 PM PDT 24
Peak memory 206336 kb
Host smart-17323d6a-830c-49f7-b026-9265e15d235c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2902811124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.2902811124
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.949050722
Short name T2369
Test name
Test status
Simulation time 23370308328 ps
CPU time 22.2 seconds
Started Jun 29 06:37:46 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206436 kb
Host smart-f7a13a8d-caa6-4d75-be69-a8b510c28f1f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=949050722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.949050722
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3159099050
Short name T2230
Test name
Test status
Simulation time 147858132 ps
CPU time 0.83 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206196 kb
Host smart-21bcbaad-6ef0-4597-8c2e-84592a2e2d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31590
99050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3159099050
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3235035238
Short name T2408
Test name
Test status
Simulation time 185226646 ps
CPU time 0.8 seconds
Started Jun 29 06:37:47 PM PDT 24
Finished Jun 29 06:37:49 PM PDT 24
Peak memory 206160 kb
Host smart-48c45088-8e26-4ebe-a635-9eaab666cf72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32350
35238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3235035238
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2938344137
Short name T1063
Test name
Test status
Simulation time 343509457 ps
CPU time 1.19 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206196 kb
Host smart-8655042c-4622-4160-b482-837939e49e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29383
44137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2938344137
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2682455386
Short name T2295
Test name
Test status
Simulation time 313651152 ps
CPU time 0.97 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:28 PM PDT 24
Peak memory 206196 kb
Host smart-fc1f6549-6061-4b71-b1c4-6eff402a9bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26824
55386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2682455386
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.4261175878
Short name T98
Test name
Test status
Simulation time 10282942345 ps
CPU time 20.08 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:48 PM PDT 24
Peak memory 206404 kb
Host smart-79a706b9-466c-4ff7-8bc2-d8c247066871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42611
75878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.4261175878
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.4258122582
Short name T940
Test name
Test status
Simulation time 332650535 ps
CPU time 1.12 seconds
Started Jun 29 06:37:38 PM PDT 24
Finished Jun 29 06:37:39 PM PDT 24
Peak memory 206184 kb
Host smart-60462469-00cf-40ea-be5f-6565eb231971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42581
22582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.4258122582
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1659222138
Short name T2491
Test name
Test status
Simulation time 154865126 ps
CPU time 0.79 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206172 kb
Host smart-fe4b57db-2442-44ac-9a36-b619e317c9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16592
22138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1659222138
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3530666025
Short name T338
Test name
Test status
Simulation time 35682450 ps
CPU time 0.65 seconds
Started Jun 29 06:37:32 PM PDT 24
Finished Jun 29 06:37:34 PM PDT 24
Peak memory 206208 kb
Host smart-9529062e-86f8-4aee-846f-4591f434a18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35306
66025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3530666025
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2074999060
Short name T2024
Test name
Test status
Simulation time 993825868 ps
CPU time 2.16 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206296 kb
Host smart-4fb9c433-6bb5-473c-b4b3-e2b4225f8423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20749
99060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2074999060
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.120530454
Short name T659
Test name
Test status
Simulation time 374849526 ps
CPU time 2.49 seconds
Started Jun 29 06:37:34 PM PDT 24
Finished Jun 29 06:37:37 PM PDT 24
Peak memory 206300 kb
Host smart-cc356416-fec9-4030-94ad-056e516724eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12053
0454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.120530454
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3090213970
Short name T120
Test name
Test status
Simulation time 217577752 ps
CPU time 0.91 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:37:29 PM PDT 24
Peak memory 206200 kb
Host smart-3c7c5853-29d8-4087-98fa-be0def332782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30902
13970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3090213970
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.130626139
Short name T2214
Test name
Test status
Simulation time 144198970 ps
CPU time 0.75 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206208 kb
Host smart-8c3f5497-4b91-472b-88cc-eabed9b0300e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13062
6139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.130626139
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3911839937
Short name T2553
Test name
Test status
Simulation time 195992715 ps
CPU time 0.89 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206196 kb
Host smart-5688f013-3931-4196-bee2-e4bc800afae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39118
39937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3911839937
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.1838685231
Short name T2337
Test name
Test status
Simulation time 5753779316 ps
CPU time 42.13 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206212 kb
Host smart-be39bba7-1f57-4a66-a510-d20f261a47dc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1838685231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.1838685231
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3128434485
Short name T340
Test name
Test status
Simulation time 248939157 ps
CPU time 0.92 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206196 kb
Host smart-2416ef2b-daac-49de-85f6-efcec01839af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
34485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3128434485
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.3830214456
Short name T1997
Test name
Test status
Simulation time 23301360538 ps
CPU time 22.72 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:53 PM PDT 24
Peak memory 206316 kb
Host smart-5e3ae799-6a81-45d9-beca-a395e7e63b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38302
14456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.3830214456
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.579718030
Short name T387
Test name
Test status
Simulation time 3257238081 ps
CPU time 3.97 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:37:35 PM PDT 24
Peak memory 206264 kb
Host smart-802e6c48-60ed-4e5b-b0a9-833431ccbf2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57971
8030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.579718030
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1636989736
Short name T1141
Test name
Test status
Simulation time 8000665291 ps
CPU time 57.32 seconds
Started Jun 29 06:37:32 PM PDT 24
Finished Jun 29 06:38:30 PM PDT 24
Peak memory 206472 kb
Host smart-0afe050b-77ad-42b8-a19b-9f7a3f1085c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16369
89736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1636989736
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.4046367867
Short name T2138
Test name
Test status
Simulation time 3692154948 ps
CPU time 98.34 seconds
Started Jun 29 06:37:34 PM PDT 24
Finished Jun 29 06:39:13 PM PDT 24
Peak memory 206460 kb
Host smart-1db526d3-4cd8-443f-8e31-b1ef45a55699
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4046367867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.4046367867
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.3622514680
Short name T2150
Test name
Test status
Simulation time 247993959 ps
CPU time 0.91 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206220 kb
Host smart-eb3a0614-70a0-4381-81de-f5f5f0ebc413
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3622514680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.3622514680
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3247816655
Short name T2290
Test name
Test status
Simulation time 188509873 ps
CPU time 0.86 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:37:32 PM PDT 24
Peak memory 206216 kb
Host smart-14000f69-923a-4b80-bdb4-e979c5d8a093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32478
16655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3247816655
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2439257888
Short name T1598
Test name
Test status
Simulation time 4053534158 ps
CPU time 37.85 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:38:08 PM PDT 24
Peak memory 206412 kb
Host smart-cda686c6-024e-46e9-8b94-2d05f42d2937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24392
57888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2439257888
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.204490444
Short name T952
Test name
Test status
Simulation time 4858704048 ps
CPU time 138.17 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:39:50 PM PDT 24
Peak memory 206460 kb
Host smart-57f6279c-d17e-412f-a3d5-f764be68b335
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=204490444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.204490444
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.3594507047
Short name T1750
Test name
Test status
Simulation time 163953205 ps
CPU time 0.81 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:30 PM PDT 24
Peak memory 206216 kb
Host smart-b1cc4abf-1b98-4d5e-bfa3-232b4eeff0e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3594507047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.3594507047
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.4272686564
Short name T2341
Test name
Test status
Simulation time 230970698 ps
CPU time 0.83 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:38 PM PDT 24
Peak memory 206216 kb
Host smart-69a373a7-a090-4af3-ac06-4556b4e4d49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42726
86564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.4272686564
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2249679877
Short name T138
Test name
Test status
Simulation time 242526095 ps
CPU time 0.87 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:37:32 PM PDT 24
Peak memory 206196 kb
Host smart-7bb8a3f4-95aa-4633-ba2c-bb67a9680270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22496
79877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2249679877
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3773044193
Short name T737
Test name
Test status
Simulation time 147046091 ps
CPU time 0.76 seconds
Started Jun 29 06:37:31 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206204 kb
Host smart-87a813f7-2a5d-422c-97a4-1e9dbf88f7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37730
44193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3773044193
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1362826129
Short name T731
Test name
Test status
Simulation time 188536571 ps
CPU time 0.81 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206192 kb
Host smart-bd7af8d5-8108-4be2-ad46-81a97e0e0770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13628
26129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1362826129
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2062198840
Short name T2356
Test name
Test status
Simulation time 152214037 ps
CPU time 0.79 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206196 kb
Host smart-d875aa5f-761d-498b-ac4f-3469fcc646be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20621
98840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2062198840
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3866019854
Short name T168
Test name
Test status
Simulation time 148977646 ps
CPU time 0.79 seconds
Started Jun 29 06:37:53 PM PDT 24
Finished Jun 29 06:37:55 PM PDT 24
Peak memory 206200 kb
Host smart-0b246de9-1fe4-4301-ba42-54f7453f506a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38660
19854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3866019854
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3074989421
Short name T2467
Test name
Test status
Simulation time 226337760 ps
CPU time 0.93 seconds
Started Jun 29 06:37:31 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206224 kb
Host smart-16ac198d-9873-4766-b997-a48c691ce5d9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3074989421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3074989421
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.572502000
Short name T1483
Test name
Test status
Simulation time 190994031 ps
CPU time 0.81 seconds
Started Jun 29 06:37:26 PM PDT 24
Finished Jun 29 06:37:27 PM PDT 24
Peak memory 206188 kb
Host smart-a6c708da-e7e5-4ff2-bd4c-c460d62bb128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57250
2000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.572502000
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2762194606
Short name T1114
Test name
Test status
Simulation time 40152548 ps
CPU time 0.68 seconds
Started Jun 29 06:37:33 PM PDT 24
Finished Jun 29 06:37:35 PM PDT 24
Peak memory 206216 kb
Host smart-da28bb1f-ddd0-4852-b0d1-bc60daa8e264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27621
94606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2762194606
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2478633623
Short name T1451
Test name
Test status
Simulation time 6466226215 ps
CPU time 17.93 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:37:49 PM PDT 24
Peak memory 206520 kb
Host smart-47c8bffd-3293-4104-b875-5083a53a056c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24786
33623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2478633623
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1756169687
Short name T2263
Test name
Test status
Simulation time 145997347 ps
CPU time 0.84 seconds
Started Jun 29 06:37:36 PM PDT 24
Finished Jun 29 06:37:37 PM PDT 24
Peak memory 206140 kb
Host smart-36cf7925-d3f2-4c4c-9d96-f6374db47af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17561
69687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1756169687
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2596668095
Short name T821
Test name
Test status
Simulation time 184805703 ps
CPU time 0.83 seconds
Started Jun 29 06:37:33 PM PDT 24
Finished Jun 29 06:37:34 PM PDT 24
Peak memory 206212 kb
Host smart-778a92b2-4316-461e-b74d-c33fbde334dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25966
68095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2596668095
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1734349973
Short name T1525
Test name
Test status
Simulation time 229603896 ps
CPU time 0.85 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:31 PM PDT 24
Peak memory 206216 kb
Host smart-978eb026-8586-45f7-b693-0581a82b7d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17343
49973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1734349973
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.368294120
Short name T772
Test name
Test status
Simulation time 183490161 ps
CPU time 0.9 seconds
Started Jun 29 06:37:35 PM PDT 24
Finished Jun 29 06:37:36 PM PDT 24
Peak memory 206200 kb
Host smart-bfe2a5e0-3599-445d-9a84-12ac0f5de9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36829
4120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.368294120
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2773480211
Short name T1267
Test name
Test status
Simulation time 225012225 ps
CPU time 0.84 seconds
Started Jun 29 06:37:31 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206200 kb
Host smart-d2740cae-c909-42c6-9d52-ad30f85f7990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27734
80211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2773480211
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2199172478
Short name T1975
Test name
Test status
Simulation time 154431092 ps
CPU time 0.8 seconds
Started Jun 29 06:37:27 PM PDT 24
Finished Jun 29 06:37:30 PM PDT 24
Peak memory 206192 kb
Host smart-be46d19d-de43-46e1-b326-b0894f664b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21991
72478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2199172478
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1435340084
Short name T1266
Test name
Test status
Simulation time 168384117 ps
CPU time 0.8 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206196 kb
Host smart-abd3fd53-096b-4bcb-a625-63d8a5a79da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
40084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1435340084
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3614999940
Short name T2057
Test name
Test status
Simulation time 247902782 ps
CPU time 0.96 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 205968 kb
Host smart-a3eda27b-fcd9-47ed-aa1b-24e7e4a2d6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36149
99940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3614999940
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3134236279
Short name T751
Test name
Test status
Simulation time 182566849 ps
CPU time 0.81 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206224 kb
Host smart-132cb2d4-5e33-4320-9219-91d605a30b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31342
36279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3134236279
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2006829435
Short name T1572
Test name
Test status
Simulation time 155036873 ps
CPU time 0.79 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:37:32 PM PDT 24
Peak memory 206196 kb
Host smart-e47cf09e-6875-4bee-8f0c-1fa96bcc502e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
29435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2006829435
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.4140456844
Short name T524
Test name
Test status
Simulation time 3001320302 ps
CPU time 80.6 seconds
Started Jun 29 06:37:30 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206436 kb
Host smart-250d9c5b-aa29-47ee-a3bf-921f6c39581e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41404
56844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.4140456844
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3032552995
Short name T531
Test name
Test status
Simulation time 45457098 ps
CPU time 0.77 seconds
Started Jun 29 06:38:01 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206212 kb
Host smart-335c581b-edca-4040-b091-a209bc934656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3032552995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3032552995
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.2069844205
Short name T1088
Test name
Test status
Simulation time 4253717399 ps
CPU time 5.98 seconds
Started Jun 29 06:37:29 PM PDT 24
Finished Jun 29 06:37:37 PM PDT 24
Peak memory 206276 kb
Host smart-d037e37f-3ea7-4050-bcc9-c246e72f88e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2069844205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.2069844205
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1516161488
Short name T219
Test name
Test status
Simulation time 13317734085 ps
CPU time 11.61 seconds
Started Jun 29 06:37:28 PM PDT 24
Finished Jun 29 06:37:41 PM PDT 24
Peak memory 206456 kb
Host smart-71d83d71-f8f9-453e-b149-a64118675f99
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1516161488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1516161488
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.3291119738
Short name T2428
Test name
Test status
Simulation time 23413091839 ps
CPU time 30.44 seconds
Started Jun 29 06:37:32 PM PDT 24
Finished Jun 29 06:38:03 PM PDT 24
Peak memory 206324 kb
Host smart-9fc9994c-5446-43e4-82e5-7077cef7c4c8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3291119738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.3291119738
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1359109928
Short name T2177
Test name
Test status
Simulation time 160255236 ps
CPU time 0.92 seconds
Started Jun 29 06:37:42 PM PDT 24
Finished Jun 29 06:37:43 PM PDT 24
Peak memory 206104 kb
Host smart-9f348050-4ed0-4321-badc-87b7de778905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13591
09928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1359109928
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3690712662
Short name T1408
Test name
Test status
Simulation time 198894522 ps
CPU time 0.85 seconds
Started Jun 29 06:37:51 PM PDT 24
Finished Jun 29 06:37:52 PM PDT 24
Peak memory 206196 kb
Host smart-b72d8107-9c2f-4b4b-878a-95834e64ceff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36907
12662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3690712662
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.4100767587
Short name T2320
Test name
Test status
Simulation time 348964998 ps
CPU time 1.17 seconds
Started Jun 29 06:37:35 PM PDT 24
Finished Jun 29 06:37:37 PM PDT 24
Peak memory 206196 kb
Host smart-4ee25f18-b732-4d88-a068-53f9432aaa6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41007
67587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.4100767587
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3162025322
Short name T185
Test name
Test status
Simulation time 907724755 ps
CPU time 2.21 seconds
Started Jun 29 06:37:50 PM PDT 24
Finished Jun 29 06:37:53 PM PDT 24
Peak memory 206272 kb
Host smart-4184508d-f288-48ae-8aee-1bc1d0df48c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31620
25322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3162025322
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.4029902836
Short name T2054
Test name
Test status
Simulation time 9319791977 ps
CPU time 20.59 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206504 kb
Host smart-b6b3b103-4d2a-4a68-9b4b-462b7ded952e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40299
02836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.4029902836
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.2412506592
Short name T842
Test name
Test status
Simulation time 398509272 ps
CPU time 1.22 seconds
Started Jun 29 06:37:46 PM PDT 24
Finished Jun 29 06:37:47 PM PDT 24
Peak memory 206200 kb
Host smart-c899a245-798d-4041-86ab-9ee1588ef6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24125
06592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.2412506592
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2541241394
Short name T1095
Test name
Test status
Simulation time 137845748 ps
CPU time 0.73 seconds
Started Jun 29 06:37:40 PM PDT 24
Finished Jun 29 06:37:42 PM PDT 24
Peak memory 206192 kb
Host smart-793daf4b-ecee-4bb5-86ef-9168d25ef2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25412
41394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2541241394
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3568968962
Short name T1184
Test name
Test status
Simulation time 44465094 ps
CPU time 0.66 seconds
Started Jun 29 06:37:38 PM PDT 24
Finished Jun 29 06:37:39 PM PDT 24
Peak memory 206196 kb
Host smart-07b6fa63-2dc9-4830-aee8-990406d631c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35689
68962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3568968962
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.2867189747
Short name T2184
Test name
Test status
Simulation time 841458094 ps
CPU time 2.02 seconds
Started Jun 29 06:37:45 PM PDT 24
Finished Jun 29 06:37:48 PM PDT 24
Peak memory 206380 kb
Host smart-823ac4f0-0de0-4693-9831-6effe1523ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28671
89747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2867189747
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2559667121
Short name T775
Test name
Test status
Simulation time 381016805 ps
CPU time 2.35 seconds
Started Jun 29 06:37:34 PM PDT 24
Finished Jun 29 06:37:37 PM PDT 24
Peak memory 206288 kb
Host smart-68112901-1baf-4dd6-88ea-eae24ccee3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25596
67121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2559667121
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3492852890
Short name T995
Test name
Test status
Simulation time 177957243 ps
CPU time 0.81 seconds
Started Jun 29 06:37:33 PM PDT 24
Finished Jun 29 06:37:35 PM PDT 24
Peak memory 206228 kb
Host smart-b63913e5-7d8c-45fd-b731-4e4a9935dd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34928
52890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3492852890
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.768494255
Short name T2357
Test name
Test status
Simulation time 161434057 ps
CPU time 0.77 seconds
Started Jun 29 06:37:41 PM PDT 24
Finished Jun 29 06:37:42 PM PDT 24
Peak memory 206208 kb
Host smart-3e80485f-d4ef-49fa-a2bc-8c8f7af16acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76849
4255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.768494255
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.841314844
Short name T2350
Test name
Test status
Simulation time 179266154 ps
CPU time 0.9 seconds
Started Jun 29 06:37:38 PM PDT 24
Finished Jun 29 06:37:40 PM PDT 24
Peak memory 206208 kb
Host smart-152d4df6-d1de-480d-9a51-fb827ebb9268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84131
4844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.841314844
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.936949948
Short name T109
Test name
Test status
Simulation time 6681657656 ps
CPU time 59.33 seconds
Started Jun 29 06:37:34 PM PDT 24
Finished Jun 29 06:38:34 PM PDT 24
Peak memory 206436 kb
Host smart-39cbb305-f8e5-4dcf-9a49-a8f596a9f721
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=936949948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.936949948
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.3962349338
Short name T1493
Test name
Test status
Simulation time 242443110 ps
CPU time 0.88 seconds
Started Jun 29 06:37:33 PM PDT 24
Finished Jun 29 06:37:35 PM PDT 24
Peak memory 206196 kb
Host smart-7ce0a6e8-98b6-4475-bbb4-d3904b3bc5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39623
49338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3962349338
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3976577669
Short name T844
Test name
Test status
Simulation time 23307727480 ps
CPU time 26.15 seconds
Started Jun 29 06:37:39 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206316 kb
Host smart-ba30d1b2-f2ca-416b-aed9-5935021d3f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
77669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3976577669
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3689661504
Short name T316
Test name
Test status
Simulation time 3374390739 ps
CPU time 3.7 seconds
Started Jun 29 06:37:50 PM PDT 24
Finished Jun 29 06:37:54 PM PDT 24
Peak memory 206256 kb
Host smart-056f40ff-9340-45b7-89bb-e8921bfdba96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36896
61504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3689661504
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3743669114
Short name T2571
Test name
Test status
Simulation time 5925677267 ps
CPU time 40.45 seconds
Started Jun 29 06:37:38 PM PDT 24
Finished Jun 29 06:38:19 PM PDT 24
Peak memory 206484 kb
Host smart-68055760-bc56-40a6-892a-f1f537d8959d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37436
69114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3743669114
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2308723612
Short name T1034
Test name
Test status
Simulation time 4408565532 ps
CPU time 123.95 seconds
Started Jun 29 06:37:41 PM PDT 24
Finished Jun 29 06:39:45 PM PDT 24
Peak memory 206492 kb
Host smart-a6e46138-5c95-4ccd-91f3-c358d5c2909a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2308723612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2308723612
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.2835341516
Short name T1083
Test name
Test status
Simulation time 279877992 ps
CPU time 0.9 seconds
Started Jun 29 06:37:47 PM PDT 24
Finished Jun 29 06:37:49 PM PDT 24
Peak memory 206196 kb
Host smart-b6b77f41-2a6a-489b-9ded-3ab436849bcc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2835341516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.2835341516
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.791455393
Short name T986
Test name
Test status
Simulation time 191374100 ps
CPU time 0.87 seconds
Started Jun 29 06:37:34 PM PDT 24
Finished Jun 29 06:37:36 PM PDT 24
Peak memory 206216 kb
Host smart-cf2439a0-d952-4c73-ab5b-fbbb91968856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79145
5393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.791455393
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3756210719
Short name T1342
Test name
Test status
Simulation time 5352074742 ps
CPU time 49.25 seconds
Started Jun 29 06:37:39 PM PDT 24
Finished Jun 29 06:38:29 PM PDT 24
Peak memory 206464 kb
Host smart-2a2ee02c-c5f3-4d2a-b808-797c3c59405a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37562
10719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3756210719
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.1509836207
Short name T917
Test name
Test status
Simulation time 7781506750 ps
CPU time 209.5 seconds
Started Jun 29 06:37:43 PM PDT 24
Finished Jun 29 06:41:12 PM PDT 24
Peak memory 206460 kb
Host smart-4be9e51a-b505-423f-9080-7a028ce363fd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1509836207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.1509836207
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2934852742
Short name T964
Test name
Test status
Simulation time 177523492 ps
CPU time 0.81 seconds
Started Jun 29 06:37:52 PM PDT 24
Finished Jun 29 06:37:54 PM PDT 24
Peak memory 206220 kb
Host smart-5f85f8fd-f1da-4697-963b-9e1d6565cb02
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2934852742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2934852742
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2696652751
Short name T650
Test name
Test status
Simulation time 169690308 ps
CPU time 0.82 seconds
Started Jun 29 06:37:49 PM PDT 24
Finished Jun 29 06:37:50 PM PDT 24
Peak memory 206216 kb
Host smart-0bc8c6aa-5b76-4c1d-ba89-3944f42a7e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26966
52751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2696652751
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2496732452
Short name T139
Test name
Test status
Simulation time 192676845 ps
CPU time 0.81 seconds
Started Jun 29 06:37:36 PM PDT 24
Finished Jun 29 06:37:37 PM PDT 24
Peak memory 206148 kb
Host smart-11293bbc-ce43-460c-8541-cb08b14fa308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24967
32452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2496732452
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.744209667
Short name T717
Test name
Test status
Simulation time 152139496 ps
CPU time 0.79 seconds
Started Jun 29 06:37:34 PM PDT 24
Finished Jun 29 06:37:35 PM PDT 24
Peak memory 206216 kb
Host smart-d15593d7-047c-4c44-918d-4f2ed57b5384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74420
9667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.744209667
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2805036082
Short name T873
Test name
Test status
Simulation time 164364615 ps
CPU time 0.79 seconds
Started Jun 29 06:37:43 PM PDT 24
Finished Jun 29 06:37:44 PM PDT 24
Peak memory 206160 kb
Host smart-cfc202dc-c7aa-4946-a292-40fe823897bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28050
36082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2805036082
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.557104014
Short name T903
Test name
Test status
Simulation time 268822268 ps
CPU time 0.96 seconds
Started Jun 29 06:37:37 PM PDT 24
Finished Jun 29 06:37:38 PM PDT 24
Peak memory 206196 kb
Host smart-599a2b1c-0357-498c-9cb1-5455ce4407fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55710
4014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.557104014
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3852884799
Short name T1279
Test name
Test status
Simulation time 166282485 ps
CPU time 0.84 seconds
Started Jun 29 06:37:46 PM PDT 24
Finished Jun 29 06:37:48 PM PDT 24
Peak memory 206200 kb
Host smart-190e7a07-c327-4a43-8e7c-1d223b4d0742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38528
84799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3852884799
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.3310811425
Short name T2299
Test name
Test status
Simulation time 188652314 ps
CPU time 0.89 seconds
Started Jun 29 06:37:57 PM PDT 24
Finished Jun 29 06:37:59 PM PDT 24
Peak memory 206184 kb
Host smart-807e7a59-88cb-43dd-81ac-0f4020e9e42c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3310811425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.3310811425
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3765171392
Short name T1129
Test name
Test status
Simulation time 154229313 ps
CPU time 0.74 seconds
Started Jun 29 06:37:33 PM PDT 24
Finished Jun 29 06:37:34 PM PDT 24
Peak memory 206192 kb
Host smart-0bcc1aa6-3595-44fa-8fd4-e839566ddb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37651
71392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3765171392
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1566923094
Short name T1965
Test name
Test status
Simulation time 38401512 ps
CPU time 0.66 seconds
Started Jun 29 06:37:39 PM PDT 24
Finished Jun 29 06:37:40 PM PDT 24
Peak memory 206212 kb
Host smart-6f0e948d-8122-42ac-92b9-113b8a942c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15669
23094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1566923094
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2027536267
Short name T1784
Test name
Test status
Simulation time 7469290818 ps
CPU time 16.04 seconds
Started Jun 29 06:37:42 PM PDT 24
Finished Jun 29 06:37:58 PM PDT 24
Peak memory 206484 kb
Host smart-3ae0d382-7c1b-4b97-b810-a14600265fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275
36267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2027536267
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3315344761
Short name T295
Test name
Test status
Simulation time 168476649 ps
CPU time 0.82 seconds
Started Jun 29 06:37:38 PM PDT 24
Finished Jun 29 06:37:39 PM PDT 24
Peak memory 206172 kb
Host smart-bc24fc19-5145-42a1-82dd-68d8ae583cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33153
44761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3315344761
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2855306212
Short name T2312
Test name
Test status
Simulation time 233847907 ps
CPU time 0.98 seconds
Started Jun 29 06:37:44 PM PDT 24
Finished Jun 29 06:37:46 PM PDT 24
Peak memory 206212 kb
Host smart-e0eb998c-2ffc-4f7e-a39e-31ba8f899e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28553
06212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2855306212
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.1876402659
Short name T1698
Test name
Test status
Simulation time 188054165 ps
CPU time 0.95 seconds
Started Jun 29 06:37:55 PM PDT 24
Finished Jun 29 06:37:57 PM PDT 24
Peak memory 206216 kb
Host smart-0fafa34e-4faa-45d3-8c4f-1bb9084430f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18764
02659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.1876402659
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3714263513
Short name T898
Test name
Test status
Simulation time 165189762 ps
CPU time 0.79 seconds
Started Jun 29 06:37:54 PM PDT 24
Finished Jun 29 06:37:56 PM PDT 24
Peak memory 206192 kb
Host smart-6c467fa2-6ed1-42da-8a4b-f6037900f530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37142
63513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3714263513
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1281047873
Short name T1686
Test name
Test status
Simulation time 168417697 ps
CPU time 0.82 seconds
Started Jun 29 06:37:46 PM PDT 24
Finished Jun 29 06:37:48 PM PDT 24
Peak memory 206196 kb
Host smart-9718362a-81c3-4fea-9668-8b0978f671f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12810
47873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1281047873
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.4071805127
Short name T1986
Test name
Test status
Simulation time 162915621 ps
CPU time 0.77 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:08 PM PDT 24
Peak memory 206192 kb
Host smart-f257cd32-f47a-4941-b38d-4407c52ef8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40718
05127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.4071805127
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3297583867
Short name T2488
Test name
Test status
Simulation time 164437255 ps
CPU time 0.81 seconds
Started Jun 29 06:38:01 PM PDT 24
Finished Jun 29 06:38:03 PM PDT 24
Peak memory 206196 kb
Host smart-532e99f2-36a2-4d7a-8908-791d453387cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32975
83867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3297583867
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2850352141
Short name T1314
Test name
Test status
Simulation time 202630459 ps
CPU time 0.96 seconds
Started Jun 29 06:38:01 PM PDT 24
Finished Jun 29 06:38:03 PM PDT 24
Peak memory 206208 kb
Host smart-b1d77422-20c2-40aa-8b5b-681714c14ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28503
52141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2850352141
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2532244692
Short name T1168
Test name
Test status
Simulation time 6241579113 ps
CPU time 47.23 seconds
Started Jun 29 06:37:54 PM PDT 24
Finished Jun 29 06:38:42 PM PDT 24
Peak memory 206400 kb
Host smart-d2b56c50-4fc9-4cf9-b8fd-30671c143d16
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2532244692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2532244692
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3836600074
Short name T2076
Test name
Test status
Simulation time 155063739 ps
CPU time 0.77 seconds
Started Jun 29 06:37:45 PM PDT 24
Finished Jun 29 06:37:46 PM PDT 24
Peak memory 206224 kb
Host smart-348fabda-c544-4d90-82ff-b0c9371c99a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38366
00074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3836600074
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2006795848
Short name T1461
Test name
Test status
Simulation time 205090724 ps
CPU time 0.83 seconds
Started Jun 29 06:37:54 PM PDT 24
Finished Jun 29 06:37:55 PM PDT 24
Peak memory 206196 kb
Host smart-59e21bd4-fc2a-4e45-b338-56a593c97447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20067
95848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2006795848
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3099698014
Short name T1058
Test name
Test status
Simulation time 4250470146 ps
CPU time 42.27 seconds
Started Jun 29 06:38:02 PM PDT 24
Finished Jun 29 06:38:46 PM PDT 24
Peak memory 206412 kb
Host smart-c798493a-8652-46f7-9733-0a5caf63b3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30996
98014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3099698014
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.1827532421
Short name T2316
Test name
Test status
Simulation time 52390444 ps
CPU time 0.7 seconds
Started Jun 29 06:34:19 PM PDT 24
Finished Jun 29 06:34:21 PM PDT 24
Peak memory 206388 kb
Host smart-d6989187-bd30-492a-8802-e50c3d0f74b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1827532421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.1827532421
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.435898871
Short name T2152
Test name
Test status
Simulation time 4459573522 ps
CPU time 5.34 seconds
Started Jun 29 06:34:05 PM PDT 24
Finished Jun 29 06:34:12 PM PDT 24
Peak memory 206460 kb
Host smart-52b79b68-7cc4-4cba-bed1-546f7cf59395
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=435898871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.435898871
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.4021755131
Short name T539
Test name
Test status
Simulation time 13339434737 ps
CPU time 13.02 seconds
Started Jun 29 06:34:02 PM PDT 24
Finished Jun 29 06:34:15 PM PDT 24
Peak memory 206348 kb
Host smart-74e2beb9-0fd4-4070-932b-785874e10d67
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4021755131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.4021755131
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.565572558
Short name T444
Test name
Test status
Simulation time 23360345485 ps
CPU time 22.71 seconds
Started Jun 29 06:33:53 PM PDT 24
Finished Jun 29 06:34:16 PM PDT 24
Peak memory 206252 kb
Host smart-650947aa-67e8-4634-b91e-6f474f7d8946
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=565572558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.565572558
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.393455235
Short name T1316
Test name
Test status
Simulation time 159025160 ps
CPU time 0.79 seconds
Started Jun 29 06:34:03 PM PDT 24
Finished Jun 29 06:34:04 PM PDT 24
Peak memory 206216 kb
Host smart-7b381685-8179-4f09-b0a0-62a358ef4c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39345
5235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.393455235
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2340882775
Short name T67
Test name
Test status
Simulation time 185927877 ps
CPU time 0.88 seconds
Started Jun 29 06:34:09 PM PDT 24
Finished Jun 29 06:34:11 PM PDT 24
Peak memory 206212 kb
Host smart-ea80ef0c-ff88-4f90-992c-165eb16acf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23408
82775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2340882775
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.2684700632
Short name T92
Test name
Test status
Simulation time 159499296 ps
CPU time 0.78 seconds
Started Jun 29 06:34:14 PM PDT 24
Finished Jun 29 06:34:16 PM PDT 24
Peak memory 206184 kb
Host smart-2c0427f8-f9e1-479a-ab59-9541c5b34de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26847
00632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2684700632
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3939306831
Short name T928
Test name
Test status
Simulation time 184945291 ps
CPU time 0.82 seconds
Started Jun 29 06:34:04 PM PDT 24
Finished Jun 29 06:34:06 PM PDT 24
Peak memory 206204 kb
Host smart-b92351f1-8c4e-4957-85cf-b5c8ca917ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39393
06831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3939306831
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3417370477
Short name T754
Test name
Test status
Simulation time 545287118 ps
CPU time 1.5 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:11 PM PDT 24
Peak memory 206196 kb
Host smart-9e09d2c0-26a2-4057-ac20-d9a7385e5663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34173
70477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3417370477
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2813900908
Short name T1040
Test name
Test status
Simulation time 6382648344 ps
CPU time 13.97 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:31 PM PDT 24
Peak memory 206440 kb
Host smart-7996990b-428e-4738-9cba-096e5a20d54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28139
00908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2813900908
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.2855057426
Short name T705
Test name
Test status
Simulation time 464521476 ps
CPU time 1.39 seconds
Started Jun 29 06:34:03 PM PDT 24
Finished Jun 29 06:34:06 PM PDT 24
Peak memory 206196 kb
Host smart-afde0781-f551-4035-8e30-a3bff65f88d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28550
57426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.2855057426
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2843835975
Short name T1869
Test name
Test status
Simulation time 157699563 ps
CPU time 0.78 seconds
Started Jun 29 06:34:09 PM PDT 24
Finished Jun 29 06:34:11 PM PDT 24
Peak memory 206204 kb
Host smart-43fead2b-f941-4392-92b3-f4db017ec1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28438
35975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2843835975
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2578550405
Short name T1169
Test name
Test status
Simulation time 46762992 ps
CPU time 0.71 seconds
Started Jun 29 06:34:05 PM PDT 24
Finished Jun 29 06:34:07 PM PDT 24
Peak memory 206208 kb
Host smart-0d47d8bd-64f7-4993-a482-91a2bd22960d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25785
50405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2578550405
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.406975118
Short name T858
Test name
Test status
Simulation time 848125004 ps
CPU time 1.96 seconds
Started Jun 29 06:34:05 PM PDT 24
Finished Jun 29 06:34:08 PM PDT 24
Peak memory 206376 kb
Host smart-9bc5f425-4c58-4a3a-bc56-f3af6baadfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40697
5118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.406975118
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3851952241
Short name T1683
Test name
Test status
Simulation time 199243087 ps
CPU time 1.99 seconds
Started Jun 29 06:34:05 PM PDT 24
Finished Jun 29 06:34:09 PM PDT 24
Peak memory 206320 kb
Host smart-a0b3945c-c066-47f8-83b2-a952d5859510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38519
52241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3851952241
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3149552812
Short name T592
Test name
Test status
Simulation time 197015429 ps
CPU time 0.9 seconds
Started Jun 29 06:34:05 PM PDT 24
Finished Jun 29 06:34:07 PM PDT 24
Peak memory 206212 kb
Host smart-0530dd75-13b0-41f2-a6cf-b246ba8bf344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31495
52812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3149552812
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.433295906
Short name T948
Test name
Test status
Simulation time 199774202 ps
CPU time 0.9 seconds
Started Jun 29 06:34:05 PM PDT 24
Finished Jun 29 06:34:07 PM PDT 24
Peak memory 206196 kb
Host smart-cc93a9be-1bc8-4336-9548-a5aafee002d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43329
5906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.433295906
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.441457572
Short name T449
Test name
Test status
Simulation time 213115377 ps
CPU time 0.95 seconds
Started Jun 29 06:34:09 PM PDT 24
Finished Jun 29 06:34:11 PM PDT 24
Peak memory 206204 kb
Host smart-87ca05c5-fa9e-4f1b-8e46-df5c7ccec851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44145
7572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.441457572
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.725632870
Short name T2186
Test name
Test status
Simulation time 5417099643 ps
CPU time 153.21 seconds
Started Jun 29 06:34:04 PM PDT 24
Finished Jun 29 06:36:38 PM PDT 24
Peak memory 206480 kb
Host smart-29d3598b-e678-49e3-b764-b94269d02e3f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=725632870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.725632870
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.113924069
Short name T1064
Test name
Test status
Simulation time 194250269 ps
CPU time 0.85 seconds
Started Jun 29 06:34:09 PM PDT 24
Finished Jun 29 06:34:11 PM PDT 24
Peak memory 206152 kb
Host smart-a401cfe8-037e-4649-9db4-655ad621cf54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11392
4069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.113924069
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.4113603223
Short name T2423
Test name
Test status
Simulation time 23290515497 ps
CPU time 25.93 seconds
Started Jun 29 06:34:04 PM PDT 24
Finished Jun 29 06:34:30 PM PDT 24
Peak memory 206312 kb
Host smart-7cc05bc2-0906-402f-bebd-9d7f0bea0d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41136
03223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.4113603223
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1126762445
Short name T405
Test name
Test status
Simulation time 3383166510 ps
CPU time 3.77 seconds
Started Jun 29 06:34:06 PM PDT 24
Finished Jun 29 06:34:11 PM PDT 24
Peak memory 206260 kb
Host smart-c3326926-8179-4a4c-8935-611f958af547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11267
62445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1126762445
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1756283890
Short name T1947
Test name
Test status
Simulation time 9322775632 ps
CPU time 64.16 seconds
Started Jun 29 06:34:15 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206464 kb
Host smart-16ffa699-50f0-44dc-8c80-3809651d3a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17562
83890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1756283890
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.4074349227
Short name T1733
Test name
Test status
Simulation time 3213799649 ps
CPU time 90 seconds
Started Jun 29 06:34:09 PM PDT 24
Finished Jun 29 06:35:40 PM PDT 24
Peak memory 206380 kb
Host smart-12547b03-d64c-4209-969f-27064b0f5766
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4074349227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.4074349227
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2708741203
Short name T413
Test name
Test status
Simulation time 242615406 ps
CPU time 0.91 seconds
Started Jun 29 06:34:04 PM PDT 24
Finished Jun 29 06:34:06 PM PDT 24
Peak memory 206196 kb
Host smart-6c5197cc-9913-4e16-84e2-c090768098e2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2708741203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2708741203
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.473181404
Short name T1107
Test name
Test status
Simulation time 195692119 ps
CPU time 0.91 seconds
Started Jun 29 06:34:04 PM PDT 24
Finished Jun 29 06:34:06 PM PDT 24
Peak memory 206212 kb
Host smart-d148f400-e68e-4c5c-93cc-facfcfd8cd27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47318
1404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.473181404
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1680578415
Short name T2044
Test name
Test status
Simulation time 5306742449 ps
CPU time 51.94 seconds
Started Jun 29 06:34:07 PM PDT 24
Finished Jun 29 06:35:00 PM PDT 24
Peak memory 206408 kb
Host smart-716c5c63-96c9-4c8d-b355-9e3d48292898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16805
78415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1680578415
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3184370976
Short name T2090
Test name
Test status
Simulation time 5456469162 ps
CPU time 149.12 seconds
Started Jun 29 06:34:09 PM PDT 24
Finished Jun 29 06:36:39 PM PDT 24
Peak memory 206460 kb
Host smart-19298403-bcfe-4fe2-ba22-e209d8fa6fc2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3184370976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3184370976
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3699534690
Short name T2328
Test name
Test status
Simulation time 169099287 ps
CPU time 0.78 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:10 PM PDT 24
Peak memory 206220 kb
Host smart-9f611bbb-ce81-4d67-85cc-46b4d0c66be0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3699534690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3699534690
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2423866288
Short name T729
Test name
Test status
Simulation time 140853467 ps
CPU time 0.74 seconds
Started Jun 29 06:34:10 PM PDT 24
Finished Jun 29 06:34:11 PM PDT 24
Peak memory 206216 kb
Host smart-ea24245c-f972-458e-bdda-8405914e2652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24238
66288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2423866288
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1845714503
Short name T125
Test name
Test status
Simulation time 189912633 ps
CPU time 0.84 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:10 PM PDT 24
Peak memory 206216 kb
Host smart-c1396390-515b-44b5-9e58-cd9f5d62f0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18457
14503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1845714503
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2524986849
Short name T1288
Test name
Test status
Simulation time 162521049 ps
CPU time 0.85 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:10 PM PDT 24
Peak memory 206196 kb
Host smart-15f5e7ea-c9ee-4aea-8b1a-afebd7fc62c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25249
86849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2524986849
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.174182726
Short name T436
Test name
Test status
Simulation time 239620369 ps
CPU time 0.88 seconds
Started Jun 29 06:34:14 PM PDT 24
Finished Jun 29 06:34:15 PM PDT 24
Peak memory 206168 kb
Host smart-f2d60f71-1b9b-447c-9283-c52a391f797d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17418
2726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.174182726
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2956195845
Short name T1376
Test name
Test status
Simulation time 186010007 ps
CPU time 0.84 seconds
Started Jun 29 06:34:05 PM PDT 24
Finished Jun 29 06:34:08 PM PDT 24
Peak memory 206196 kb
Host smart-a86d7dc5-d3bf-44b2-8c4f-8f1c5320c085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29561
95845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2956195845
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1120809184
Short name T1179
Test name
Test status
Simulation time 206805311 ps
CPU time 0.87 seconds
Started Jun 29 06:34:06 PM PDT 24
Finished Jun 29 06:34:08 PM PDT 24
Peak memory 206220 kb
Host smart-b84eeb76-854c-456d-801a-5537083f59ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11208
09184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1120809184
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3299880005
Short name T2381
Test name
Test status
Simulation time 239724730 ps
CPU time 0.95 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:10 PM PDT 24
Peak memory 206224 kb
Host smart-eef420b4-5a0e-4de9-aed7-f1bc525b8bf9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3299880005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3299880005
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1163373716
Short name T1128
Test name
Test status
Simulation time 221469470 ps
CPU time 0.9 seconds
Started Jun 29 06:34:09 PM PDT 24
Finished Jun 29 06:34:11 PM PDT 24
Peak memory 206204 kb
Host smart-2a8af8f6-21a7-48e9-8d42-f80482144000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11633
73716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1163373716
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2985892865
Short name T837
Test name
Test status
Simulation time 163963633 ps
CPU time 0.83 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:10 PM PDT 24
Peak memory 206216 kb
Host smart-b5645816-5b81-42aa-9438-18ab9a52852f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29858
92865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2985892865
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2116008587
Short name T2302
Test name
Test status
Simulation time 41634242 ps
CPU time 0.68 seconds
Started Jun 29 06:34:06 PM PDT 24
Finished Jun 29 06:34:08 PM PDT 24
Peak memory 206212 kb
Host smart-00ffe4de-748c-4777-94d4-d6363c12f5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21160
08587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2116008587
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3223888762
Short name T2353
Test name
Test status
Simulation time 19790758664 ps
CPU time 52.04 seconds
Started Jun 29 06:34:14 PM PDT 24
Finished Jun 29 06:35:07 PM PDT 24
Peak memory 206456 kb
Host smart-1e2aa3e4-bdd0-421d-a87e-53879df17ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32238
88762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3223888762
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.169658168
Short name T1257
Test name
Test status
Simulation time 175711138 ps
CPU time 0.83 seconds
Started Jun 29 06:34:09 PM PDT 24
Finished Jun 29 06:34:10 PM PDT 24
Peak memory 206124 kb
Host smart-44e6ac6b-f0c7-41d0-9083-46217e3d3066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16965
8168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.169658168
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.395528232
Short name T1444
Test name
Test status
Simulation time 243840416 ps
CPU time 0.9 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:10 PM PDT 24
Peak memory 206200 kb
Host smart-26f803b4-8270-4679-93dd-4ee44c6b7463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39552
8232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.395528232
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.2355502716
Short name T194
Test name
Test status
Simulation time 9049147246 ps
CPU time 38.9 seconds
Started Jun 29 06:34:07 PM PDT 24
Finished Jun 29 06:34:47 PM PDT 24
Peak memory 206500 kb
Host smart-5e939c8a-6cf5-4b37-9d17-1fe41dbb9a90
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2355502716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2355502716
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.1152060834
Short name T167
Test name
Test status
Simulation time 9186280562 ps
CPU time 146.21 seconds
Started Jun 29 06:34:07 PM PDT 24
Finished Jun 29 06:36:34 PM PDT 24
Peak memory 206500 kb
Host smart-b8a33477-dda6-45dc-9a82-cc2147c3c5be
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1152060834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.1152060834
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2386470092
Short name T415
Test name
Test status
Simulation time 15161806789 ps
CPU time 80.54 seconds
Started Jun 29 06:34:09 PM PDT 24
Finished Jun 29 06:35:31 PM PDT 24
Peak memory 206488 kb
Host smart-553318df-705b-4e2a-bc4e-0a20986aada2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2386470092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2386470092
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2043315085
Short name T1968
Test name
Test status
Simulation time 207546483 ps
CPU time 0.92 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 206208 kb
Host smart-c1a7196e-2ee1-4965-a969-15288e20d0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20433
15085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2043315085
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3795656565
Short name T1512
Test name
Test status
Simulation time 213411209 ps
CPU time 1.02 seconds
Started Jun 29 06:34:12 PM PDT 24
Finished Jun 29 06:34:13 PM PDT 24
Peak memory 206192 kb
Host smart-e9708e54-7234-4dfc-9eb1-c4ffa585d07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37956
56565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3795656565
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1896534275
Short name T1958
Test name
Test status
Simulation time 157168288 ps
CPU time 0.79 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:10 PM PDT 24
Peak memory 206196 kb
Host smart-d682da48-4cda-4b4c-90c1-788ce5af800c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18965
34275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1896534275
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.3783416061
Short name T1952
Test name
Test status
Simulation time 156652729 ps
CPU time 0.83 seconds
Started Jun 29 06:34:14 PM PDT 24
Finished Jun 29 06:34:15 PM PDT 24
Peak memory 206192 kb
Host smart-5665385a-93eb-48f2-8b21-02864abc24e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37834
16061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.3783416061
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.223729978
Short name T208
Test name
Test status
Simulation time 249051311 ps
CPU time 1.12 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 224016 kb
Host smart-4676e196-923f-40a9-aaf5-7bf59352045d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=223729978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.223729978
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.601162073
Short name T63
Test name
Test status
Simulation time 441677614 ps
CPU time 1.35 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:10 PM PDT 24
Peak memory 206216 kb
Host smart-655ced33-7658-4901-b4c6-7cdf49966283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60116
2073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.601162073
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.958261886
Short name T1290
Test name
Test status
Simulation time 223815653 ps
CPU time 0.96 seconds
Started Jun 29 06:34:14 PM PDT 24
Finished Jun 29 06:34:15 PM PDT 24
Peak memory 206132 kb
Host smart-096e4e6f-1038-4f72-817d-0c292473073a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95826
1886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.958261886
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1836226440
Short name T1775
Test name
Test status
Simulation time 149737486 ps
CPU time 0.82 seconds
Started Jun 29 06:34:08 PM PDT 24
Finished Jun 29 06:34:09 PM PDT 24
Peak memory 206196 kb
Host smart-a18595d8-ab3e-433b-a712-0ba152c57e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18362
26440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1836226440
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2800906088
Short name T1842
Test name
Test status
Simulation time 151545797 ps
CPU time 0.83 seconds
Started Jun 29 06:34:15 PM PDT 24
Finished Jun 29 06:34:17 PM PDT 24
Peak memory 206180 kb
Host smart-b853c696-1ab3-4a24-b700-e716d90f38a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28009
06088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2800906088
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1474482202
Short name T1535
Test name
Test status
Simulation time 212744620 ps
CPU time 0.9 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 206216 kb
Host smart-0db12c5a-0241-4909-9011-3cd6769c96b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14744
82202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1474482202
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3353792876
Short name T1955
Test name
Test status
Simulation time 3784146515 ps
CPU time 35.03 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:52 PM PDT 24
Peak memory 206448 kb
Host smart-2f609134-055e-4119-b014-c3b15ba5a10c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3353792876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3353792876
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1712279142
Short name T1571
Test name
Test status
Simulation time 167281466 ps
CPU time 0.82 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 205816 kb
Host smart-e58a30a4-aaeb-4eab-82e7-a3a17b8073ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17122
79142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1712279142
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3767964533
Short name T1674
Test name
Test status
Simulation time 176245796 ps
CPU time 0.79 seconds
Started Jun 29 06:34:15 PM PDT 24
Finished Jun 29 06:34:17 PM PDT 24
Peak memory 206196 kb
Host smart-ea4fa7f0-00e5-43e8-95c5-f20702275495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37679
64533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3767964533
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2422357515
Short name T2004
Test name
Test status
Simulation time 5315885724 ps
CPU time 151.97 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:36:49 PM PDT 24
Peak memory 206472 kb
Host smart-f2ae863f-3507-4845-9b6a-2aad38cd0566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24223
57515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2422357515
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.546787352
Short name T1821
Test name
Test status
Simulation time 24832421894 ps
CPU time 226.9 seconds
Started Jun 29 06:34:14 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206592 kb
Host smart-99cb2bf2-d606-4aa5-985a-80c517e217cf
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=546787352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.546787352
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2059897408
Short name T1407
Test name
Test status
Simulation time 39014232 ps
CPU time 0.67 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206176 kb
Host smart-efc1f421-db71-4bdf-b316-a2786b1d87bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2059897408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2059897408
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1088401300
Short name T1858
Test name
Test status
Simulation time 3646161968 ps
CPU time 4.6 seconds
Started Jun 29 06:37:44 PM PDT 24
Finished Jun 29 06:37:49 PM PDT 24
Peak memory 206280 kb
Host smart-b9b9b938-be9c-44bc-8dc5-5cc3b0ab592c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1088401300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.1088401300
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3069427174
Short name T2460
Test name
Test status
Simulation time 13356982150 ps
CPU time 13.19 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:18 PM PDT 24
Peak memory 206340 kb
Host smart-2e44f771-c83c-44bf-bec8-f1ce7608290f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3069427174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3069427174
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.270872368
Short name T1941
Test name
Test status
Simulation time 23323678591 ps
CPU time 21.64 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206368 kb
Host smart-538bbbea-f3e1-4e60-bd29-d580ec6e5eac
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=270872368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.270872368
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.43656124
Short name T1962
Test name
Test status
Simulation time 161813576 ps
CPU time 0.88 seconds
Started Jun 29 06:37:47 PM PDT 24
Finished Jun 29 06:37:49 PM PDT 24
Peak memory 206204 kb
Host smart-1982fbe6-af72-4b1a-b922-f623a8faecad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43656
124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.43656124
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1435261855
Short name T1042
Test name
Test status
Simulation time 144949935 ps
CPU time 0.78 seconds
Started Jun 29 06:38:00 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206196 kb
Host smart-034f072f-1176-4734-822f-8895603108c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14352
61855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1435261855
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1683817509
Short name T1238
Test name
Test status
Simulation time 519945400 ps
CPU time 1.61 seconds
Started Jun 29 06:37:46 PM PDT 24
Finished Jun 29 06:37:48 PM PDT 24
Peak memory 206356 kb
Host smart-de13dea1-ca2f-4918-a2cc-264056c39daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16838
17509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1683817509
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1077495211
Short name T736
Test name
Test status
Simulation time 1127896771 ps
CPU time 2.55 seconds
Started Jun 29 06:37:46 PM PDT 24
Finished Jun 29 06:37:49 PM PDT 24
Peak memory 206272 kb
Host smart-1c186303-9234-4378-84ac-7a52b821ac53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10774
95211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1077495211
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.935864535
Short name T2204
Test name
Test status
Simulation time 16622116632 ps
CPU time 30.3 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:31 PM PDT 24
Peak memory 206404 kb
Host smart-8cebd79c-f16b-46dc-a486-fc539c533895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93586
4535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.935864535
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3119794902
Short name T750
Test name
Test status
Simulation time 353477722 ps
CPU time 1.32 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206192 kb
Host smart-cd255e0d-cd46-4d3d-9863-0f7506ad6965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31197
94902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3119794902
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.216259387
Short name T1262
Test name
Test status
Simulation time 131710075 ps
CPU time 0.83 seconds
Started Jun 29 06:37:49 PM PDT 24
Finished Jun 29 06:37:50 PM PDT 24
Peak memory 206200 kb
Host smart-cd7d8314-7d0e-4487-b1eb-c3ccd4e3e23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21625
9387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.216259387
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2075997825
Short name T1439
Test name
Test status
Simulation time 73647956 ps
CPU time 0.74 seconds
Started Jun 29 06:37:46 PM PDT 24
Finished Jun 29 06:37:47 PM PDT 24
Peak memory 206192 kb
Host smart-11269396-9305-4dde-b6bf-98ba78b351c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20759
97825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2075997825
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3186964157
Short name T1625
Test name
Test status
Simulation time 935529074 ps
CPU time 2.32 seconds
Started Jun 29 06:38:04 PM PDT 24
Finished Jun 29 06:38:08 PM PDT 24
Peak memory 206340 kb
Host smart-5bc844d6-6599-4943-a2c1-69eca70f26af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31869
64157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3186964157
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2631480555
Short name T728
Test name
Test status
Simulation time 174323056 ps
CPU time 1.82 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206288 kb
Host smart-f8ff876d-398e-4ec9-b597-a0db4892d8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26314
80555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2631480555
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.274350225
Short name T2260
Test name
Test status
Simulation time 242931236 ps
CPU time 0.98 seconds
Started Jun 29 06:37:49 PM PDT 24
Finished Jun 29 06:37:50 PM PDT 24
Peak memory 206200 kb
Host smart-952f0fea-52b6-4edc-a8cf-3caa02a1368d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27435
0225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.274350225
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2823407677
Short name T1902
Test name
Test status
Simulation time 139116921 ps
CPU time 0.81 seconds
Started Jun 29 06:37:48 PM PDT 24
Finished Jun 29 06:37:50 PM PDT 24
Peak memory 206212 kb
Host smart-8f2084cc-ce35-4020-9c47-5e8bd98db75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28234
07677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2823407677
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1094333549
Short name T2288
Test name
Test status
Simulation time 220144710 ps
CPU time 0.9 seconds
Started Jun 29 06:37:46 PM PDT 24
Finished Jun 29 06:37:48 PM PDT 24
Peak memory 206216 kb
Host smart-d477912d-495a-4ab7-a2ec-9aa2de65b6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
33549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1094333549
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.811516647
Short name T2258
Test name
Test status
Simulation time 4813937088 ps
CPU time 136.4 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:40:23 PM PDT 24
Peak memory 206444 kb
Host smart-fdef64f3-789f-4cca-8844-17fcb9911d9e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=811516647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.811516647
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3651769887
Short name T2145
Test name
Test status
Simulation time 214194631 ps
CPU time 0.88 seconds
Started Jun 29 06:38:00 PM PDT 24
Finished Jun 29 06:38:03 PM PDT 24
Peak memory 206196 kb
Host smart-a5591585-e524-4b3b-8362-d4c448ce97b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36517
69887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3651769887
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.1239339378
Short name T1191
Test name
Test status
Simulation time 23314170130 ps
CPU time 29.32 seconds
Started Jun 29 06:37:54 PM PDT 24
Finished Jun 29 06:38:24 PM PDT 24
Peak memory 206316 kb
Host smart-177c29ac-f8f4-43c0-91cf-487d699f1d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12393
39378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1239339378
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.4072450837
Short name T2592
Test name
Test status
Simulation time 3350094118 ps
CPU time 4.25 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206224 kb
Host smart-e90c8f7b-41b5-4e19-b20f-09d4bdc39477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40724
50837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.4072450837
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2850384894
Short name T599
Test name
Test status
Simulation time 6889587010 ps
CPU time 184.38 seconds
Started Jun 29 06:37:48 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 206472 kb
Host smart-1cc7c413-062a-428e-a54d-55449873775b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28503
84894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2850384894
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1174090752
Short name T2026
Test name
Test status
Simulation time 7180500562 ps
CPU time 64.17 seconds
Started Jun 29 06:37:52 PM PDT 24
Finished Jun 29 06:38:57 PM PDT 24
Peak memory 206500 kb
Host smart-b18434fc-a0c6-4e3a-a938-c8421cb32741
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1174090752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1174090752
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.617301097
Short name T1848
Test name
Test status
Simulation time 253317953 ps
CPU time 0.9 seconds
Started Jun 29 06:37:56 PM PDT 24
Finished Jun 29 06:37:59 PM PDT 24
Peak memory 206220 kb
Host smart-d26db8bc-fd49-40c6-9265-ca60bd8cd349
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=617301097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.617301097
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1719033450
Short name T2098
Test name
Test status
Simulation time 232074372 ps
CPU time 0.94 seconds
Started Jun 29 06:37:54 PM PDT 24
Finished Jun 29 06:37:55 PM PDT 24
Peak memory 206212 kb
Host smart-02a4ef8f-724d-4417-9e8f-387185515281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17190
33450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1719033450
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.2973425021
Short name T1528
Test name
Test status
Simulation time 3457497317 ps
CPU time 94.76 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:39:36 PM PDT 24
Peak memory 206420 kb
Host smart-a6ae0283-bca9-4809-8291-ab791c58c8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29734
25021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.2973425021
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3592674291
Short name T856
Test name
Test status
Simulation time 4852494106 ps
CPU time 34.96 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:35 PM PDT 24
Peak memory 206496 kb
Host smart-19e6626a-8314-4e8b-b2fb-be45da6c11b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3592674291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3592674291
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1610246576
Short name T626
Test name
Test status
Simulation time 149992458 ps
CPU time 0.78 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206220 kb
Host smart-814787ec-e8e9-416e-94ce-81b1e86ac416
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1610246576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1610246576
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1171526105
Short name T438
Test name
Test status
Simulation time 169992078 ps
CPU time 0.84 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206216 kb
Host smart-b40f0043-3673-479f-a945-4dd63ddfcf6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11715
26105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1171526105
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3185782556
Short name T132
Test name
Test status
Simulation time 226914788 ps
CPU time 0.9 seconds
Started Jun 29 06:37:54 PM PDT 24
Finished Jun 29 06:37:55 PM PDT 24
Peak memory 206208 kb
Host smart-af09be9f-c83e-4a11-9b40-662811eb14ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31857
82556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3185782556
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1272163820
Short name T740
Test name
Test status
Simulation time 157234528 ps
CPU time 0.8 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206192 kb
Host smart-576d520c-00e9-4aed-8677-84311429c3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12721
63820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1272163820
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1957334402
Short name T2195
Test name
Test status
Simulation time 171364235 ps
CPU time 0.82 seconds
Started Jun 29 06:37:50 PM PDT 24
Finished Jun 29 06:37:51 PM PDT 24
Peak memory 206140 kb
Host smart-7e80ef59-3712-4273-a59c-72b1102a4587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19573
34402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1957334402
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2506388548
Short name T1607
Test name
Test status
Simulation time 163550971 ps
CPU time 0.78 seconds
Started Jun 29 06:38:02 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206172 kb
Host smart-a24f8624-e840-4e11-829c-0c28ac2fd414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
88548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2506388548
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1916974291
Short name T2471
Test name
Test status
Simulation time 146060584 ps
CPU time 0.83 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:05 PM PDT 24
Peak memory 206200 kb
Host smart-0de22e83-450f-49d1-8bb4-0214a45f6507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19169
74291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1916974291
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1580460478
Short name T2222
Test name
Test status
Simulation time 217558666 ps
CPU time 0.9 seconds
Started Jun 29 06:37:56 PM PDT 24
Finished Jun 29 06:37:58 PM PDT 24
Peak memory 206224 kb
Host smart-30327adc-22bd-4d1c-9fa3-68652406211f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1580460478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1580460478
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1435522985
Short name T686
Test name
Test status
Simulation time 145305469 ps
CPU time 0.79 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:08 PM PDT 24
Peak memory 206168 kb
Host smart-9ef4da8a-8e5b-4643-a39a-1a567149c3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14355
22985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1435522985
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3743428403
Short name T1974
Test name
Test status
Simulation time 37225068 ps
CPU time 0.7 seconds
Started Jun 29 06:37:57 PM PDT 24
Finished Jun 29 06:37:59 PM PDT 24
Peak memory 206212 kb
Host smart-bd07bd53-2f18-4e18-b8e7-686fa6c3a51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37434
28403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3743428403
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.708665204
Short name T1477
Test name
Test status
Simulation time 6040438703 ps
CPU time 13.6 seconds
Started Jun 29 06:37:56 PM PDT 24
Finished Jun 29 06:38:11 PM PDT 24
Peak memory 206416 kb
Host smart-75aff6f3-1f3e-44ba-b21f-d09d3236444c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70866
5204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.708665204
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.813637455
Short name T2125
Test name
Test status
Simulation time 210346323 ps
CPU time 0.85 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206152 kb
Host smart-91ca92af-70cc-4b20-b628-88decd1c4752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81363
7455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.813637455
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.516041554
Short name T843
Test name
Test status
Simulation time 176886738 ps
CPU time 0.91 seconds
Started Jun 29 06:37:57 PM PDT 24
Finished Jun 29 06:38:00 PM PDT 24
Peak memory 206360 kb
Host smart-d30bd409-c1c6-4f30-8040-c977070f28aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51604
1554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.516041554
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3505280607
Short name T1067
Test name
Test status
Simulation time 231470690 ps
CPU time 0.95 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:01 PM PDT 24
Peak memory 206128 kb
Host smart-c7e1c1cc-3f83-4a67-ac78-f8c8fb6aa8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35052
80607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3505280607
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.4001326967
Short name T1343
Test name
Test status
Simulation time 156442592 ps
CPU time 0.85 seconds
Started Jun 29 06:37:57 PM PDT 24
Finished Jun 29 06:38:00 PM PDT 24
Peak memory 206200 kb
Host smart-f363b9d0-ce05-4b38-880a-c089f2317d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40013
26967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.4001326967
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3126836566
Short name T420
Test name
Test status
Simulation time 137091401 ps
CPU time 0.77 seconds
Started Jun 29 06:37:57 PM PDT 24
Finished Jun 29 06:38:00 PM PDT 24
Peak memory 206192 kb
Host smart-8be1e733-1a48-4596-8438-fb288208af2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31268
36566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3126836566
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.297610103
Short name T1031
Test name
Test status
Simulation time 146275060 ps
CPU time 0.79 seconds
Started Jun 29 06:37:52 PM PDT 24
Finished Jun 29 06:37:53 PM PDT 24
Peak memory 206196 kb
Host smart-4181e499-0dd2-4edb-a6b2-93a75f942a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761
0103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.297610103
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1531549454
Short name T1876
Test name
Test status
Simulation time 152987254 ps
CPU time 0.84 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206188 kb
Host smart-d58d198d-48bb-428e-8346-bdcf7c9fdc5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15315
49454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1531549454
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.4222280511
Short name T32
Test name
Test status
Simulation time 210141167 ps
CPU time 0.86 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206168 kb
Host smart-73228422-e331-4c4a-aafe-93a409575ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42222
80511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.4222280511
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2615923599
Short name T1053
Test name
Test status
Simulation time 3624671555 ps
CPU time 36.56 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:37 PM PDT 24
Peak memory 206432 kb
Host smart-f89b6a66-47a8-4b21-8282-98c61be3275e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2615923599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2615923599
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1815012568
Short name T1367
Test name
Test status
Simulation time 177336733 ps
CPU time 0.83 seconds
Started Jun 29 06:37:57 PM PDT 24
Finished Jun 29 06:38:01 PM PDT 24
Peak memory 206192 kb
Host smart-2c890338-3c16-45e2-9218-de293a82e84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18150
12568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1815012568
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3098769436
Short name T540
Test name
Test status
Simulation time 198145070 ps
CPU time 0.83 seconds
Started Jun 29 06:38:02 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206196 kb
Host smart-1c519b78-4f9b-4c5e-9253-1d1f10150656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30987
69436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3098769436
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.1648859343
Short name T2321
Test name
Test status
Simulation time 3231469877 ps
CPU time 21.53 seconds
Started Jun 29 06:38:04 PM PDT 24
Finished Jun 29 06:38:27 PM PDT 24
Peak memory 206396 kb
Host smart-47ce831f-cf5f-44c4-864d-6993ea9dee9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16488
59343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.1648859343
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.1811314421
Short name T327
Test name
Test status
Simulation time 97886806 ps
CPU time 0.75 seconds
Started Jun 29 06:38:02 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206212 kb
Host smart-b2ea8b97-73dc-4419-a32f-b9ddbcb36f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1811314421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1811314421
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1019065506
Short name T1799
Test name
Test status
Simulation time 3602252392 ps
CPU time 4.6 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206392 kb
Host smart-29318d32-fc18-4391-a79b-642bdd785d32
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1019065506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.1019065506
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3051319494
Short name T1814
Test name
Test status
Simulation time 13349309955 ps
CPU time 12.75 seconds
Started Jun 29 06:38:01 PM PDT 24
Finished Jun 29 06:38:15 PM PDT 24
Peak memory 206416 kb
Host smart-1cbead89-5113-4efb-87c0-52aa9f13b86f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3051319494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3051319494
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3787134315
Short name T236
Test name
Test status
Simulation time 23414178762 ps
CPU time 23.29 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:24 PM PDT 24
Peak memory 206480 kb
Host smart-69fcb825-d314-4f36-8b2a-9cea62e6a36b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3787134315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.3787134315
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.977962833
Short name T1205
Test name
Test status
Simulation time 225629537 ps
CPU time 0.86 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206216 kb
Host smart-2e18a3c3-f221-4b31-9eb3-f5c32f3d0ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97796
2833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.977962833
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1208734156
Short name T397
Test name
Test status
Simulation time 154584761 ps
CPU time 0.79 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:20 PM PDT 24
Peak memory 206196 kb
Host smart-6d76dbb5-6906-4169-b847-5b62dea33759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12087
34156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1208734156
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.961176348
Short name T69
Test name
Test status
Simulation time 423520056 ps
CPU time 1.43 seconds
Started Jun 29 06:37:53 PM PDT 24
Finished Jun 29 06:37:55 PM PDT 24
Peak memory 206200 kb
Host smart-0a84a1ea-2385-4948-a98c-5284b938e793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96117
6348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.961176348
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.1229943997
Short name T174
Test name
Test status
Simulation time 1360180905 ps
CPU time 2.91 seconds
Started Jun 29 06:37:56 PM PDT 24
Finished Jun 29 06:38:00 PM PDT 24
Peak memory 206316 kb
Host smart-3da6ec27-915e-42d5-b6e1-76bfacda147e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12299
43997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.1229943997
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.2818668635
Short name T183
Test name
Test status
Simulation time 7963407479 ps
CPU time 16.23 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:16 PM PDT 24
Peak memory 206420 kb
Host smart-2399307f-97ef-42c9-9cbe-93acba46beff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28186
68635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.2818668635
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.4202086129
Short name T1259
Test name
Test status
Simulation time 344696661 ps
CPU time 1.13 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:08 PM PDT 24
Peak memory 206164 kb
Host smart-19d0f102-e460-4ccd-8512-091ff27b0376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42020
86129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.4202086129
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1605471591
Short name T1251
Test name
Test status
Simulation time 142525826 ps
CPU time 0.8 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206192 kb
Host smart-8f9b88df-b655-4b94-9de0-de8cbeb05ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16054
71591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1605471591
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3019116940
Short name T2339
Test name
Test status
Simulation time 39713480 ps
CPU time 0.69 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:05 PM PDT 24
Peak memory 206200 kb
Host smart-1d6c5d08-df23-43ab-b720-001f2eb187b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30191
16940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3019116940
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2143202016
Short name T322
Test name
Test status
Simulation time 937252558 ps
CPU time 2.18 seconds
Started Jun 29 06:37:52 PM PDT 24
Finished Jun 29 06:37:54 PM PDT 24
Peak memory 206268 kb
Host smart-7c8b5d02-7c95-48d6-a400-20f8fd8183d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21432
02016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2143202016
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3500383940
Short name T987
Test name
Test status
Simulation time 312959836 ps
CPU time 1.97 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:07 PM PDT 24
Peak memory 206372 kb
Host smart-5975a1cf-b4d4-4edc-8e82-16738989ae4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35003
83940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3500383940
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4032329405
Short name T394
Test name
Test status
Simulation time 160744128 ps
CPU time 0.81 seconds
Started Jun 29 06:38:01 PM PDT 24
Finished Jun 29 06:38:03 PM PDT 24
Peak memory 206148 kb
Host smart-73710240-d256-408b-b092-04d5955d8815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40323
29405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4032329405
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2699190267
Short name T1743
Test name
Test status
Simulation time 168165846 ps
CPU time 0.76 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:01 PM PDT 24
Peak memory 206216 kb
Host smart-a138f53f-07d2-44e7-8922-18a25103c54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26991
90267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2699190267
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1219246195
Short name T50
Test name
Test status
Simulation time 206221068 ps
CPU time 0.86 seconds
Started Jun 29 06:38:02 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206216 kb
Host smart-579beb66-04dd-4ca2-8646-95abb55b4659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12192
46195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1219246195
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.2859989676
Short name T479
Test name
Test status
Simulation time 224660501 ps
CPU time 0.94 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:10 PM PDT 24
Peak memory 206196 kb
Host smart-85e98e8e-a14f-4a93-ba57-13dbd6b07670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28599
89676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.2859989676
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.2640133649
Short name T1591
Test name
Test status
Simulation time 23347387005 ps
CPU time 21.35 seconds
Started Jun 29 06:38:04 PM PDT 24
Finished Jun 29 06:38:27 PM PDT 24
Peak memory 206312 kb
Host smart-4c4a6485-2124-446a-ae06-31809c41676f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26401
33649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.2640133649
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1627946960
Short name T1688
Test name
Test status
Simulation time 3309303340 ps
CPU time 4.1 seconds
Started Jun 29 06:37:56 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206256 kb
Host smart-86e00f19-72ad-4cb3-baaa-67e940b26d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16279
46960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1627946960
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.3720379587
Short name T2188
Test name
Test status
Simulation time 6016265051 ps
CPU time 54.47 seconds
Started Jun 29 06:38:09 PM PDT 24
Finished Jun 29 06:39:06 PM PDT 24
Peak memory 206428 kb
Host smart-10c10652-8637-49cc-adc7-979c28bc1c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37203
79587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.3720379587
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.3906877380
Short name T977
Test name
Test status
Simulation time 3769838921 ps
CPU time 34.63 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:35 PM PDT 24
Peak memory 206416 kb
Host smart-76351d24-f7fa-4f57-a2d0-5c8290151356
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3906877380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.3906877380
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3737466214
Short name T2052
Test name
Test status
Simulation time 256606546 ps
CPU time 0.89 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206168 kb
Host smart-7ebb8cb7-2c61-48d5-ae31-a808fbe40b7c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3737466214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3737466214
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2126360401
Short name T988
Test name
Test status
Simulation time 191454441 ps
CPU time 0.9 seconds
Started Jun 29 06:38:02 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206192 kb
Host smart-05fd4e36-3ba0-4ee9-85be-46af357dabf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21263
60401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2126360401
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.3640765479
Short name T2308
Test name
Test status
Simulation time 4779239215 ps
CPU time 33.21 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:33 PM PDT 24
Peak memory 206420 kb
Host smart-e20348bd-f6f4-45c9-9dce-85733e5af338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36407
65479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.3640765479
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.1525883229
Short name T792
Test name
Test status
Simulation time 3796514381 ps
CPU time 102.87 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206432 kb
Host smart-2b00f79c-9f5c-4efa-9a7b-ba35f2659821
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1525883229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.1525883229
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1533112866
Short name T1701
Test name
Test status
Simulation time 173371845 ps
CPU time 0.86 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:11 PM PDT 24
Peak memory 206172 kb
Host smart-a284b0c2-f01d-4442-9773-1f414af25d72
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1533112866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1533112866
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2401462772
Short name T2544
Test name
Test status
Simulation time 142245378 ps
CPU time 0.8 seconds
Started Jun 29 06:38:02 PM PDT 24
Finished Jun 29 06:38:05 PM PDT 24
Peak memory 206216 kb
Host smart-80ea7b47-66be-471d-88b5-d42db887bd9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24014
62772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2401462772
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2493327100
Short name T2246
Test name
Test status
Simulation time 223245767 ps
CPU time 0.99 seconds
Started Jun 29 06:37:52 PM PDT 24
Finished Jun 29 06:37:53 PM PDT 24
Peak memory 206196 kb
Host smart-9235c5f4-c911-4576-b685-64712818b937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24933
27100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2493327100
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2504146738
Short name T1727
Test name
Test status
Simulation time 195744134 ps
CPU time 0.86 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206204 kb
Host smart-0b759101-9225-411c-83b6-504cec982cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25041
46738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2504146738
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.153530959
Short name T326
Test name
Test status
Simulation time 156860800 ps
CPU time 0.8 seconds
Started Jun 29 06:37:56 PM PDT 24
Finished Jun 29 06:37:57 PM PDT 24
Peak memory 206216 kb
Host smart-8a71014a-2b93-4a4a-a384-7105a5bb1439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15353
0959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.153530959
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1161826437
Short name T1542
Test name
Test status
Simulation time 168201546 ps
CPU time 0.78 seconds
Started Jun 29 06:37:56 PM PDT 24
Finished Jun 29 06:37:57 PM PDT 24
Peak memory 206208 kb
Host smart-b1757bc8-d728-4ce0-9d4d-47aa0367f823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11618
26437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1161826437
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1749714599
Short name T680
Test name
Test status
Simulation time 189123640 ps
CPU time 0.8 seconds
Started Jun 29 06:38:06 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206200 kb
Host smart-dff8324b-c320-4250-944d-8031676dfcda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17497
14599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1749714599
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.558460802
Short name T1395
Test name
Test status
Simulation time 245806672 ps
CPU time 1.04 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206204 kb
Host smart-271f7bdf-fd8c-4c46-81b3-cda7dac184ac
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=558460802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.558460802
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1139371936
Short name T957
Test name
Test status
Simulation time 137839106 ps
CPU time 0.79 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:10 PM PDT 24
Peak memory 206192 kb
Host smart-1d372187-2853-4ed7-b963-00967fd17809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11393
71936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1139371936
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1467401445
Short name T2062
Test name
Test status
Simulation time 40198046 ps
CPU time 0.65 seconds
Started Jun 29 06:38:04 PM PDT 24
Finished Jun 29 06:38:07 PM PDT 24
Peak memory 206192 kb
Host smart-a04b296d-1b8b-4a5c-823f-fc7da333fb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14674
01445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1467401445
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2389357151
Short name T1111
Test name
Test status
Simulation time 15192837860 ps
CPU time 32.26 seconds
Started Jun 29 06:37:57 PM PDT 24
Finished Jun 29 06:38:31 PM PDT 24
Peak memory 206464 kb
Host smart-daef108a-069f-445b-b6b1-2490e5e6bf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23893
57151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2389357151
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3225981333
Short name T817
Test name
Test status
Simulation time 201093072 ps
CPU time 0.89 seconds
Started Jun 29 06:38:06 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206168 kb
Host smart-0b439d9d-badf-428e-b8fb-f7a33f0dad00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32259
81333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3225981333
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2572186034
Short name T350
Test name
Test status
Simulation time 238470603 ps
CPU time 0.92 seconds
Started Jun 29 06:38:06 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206208 kb
Host smart-621d6701-3fdd-4536-a171-323e7c6d6889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25721
86034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2572186034
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1386643406
Short name T1007
Test name
Test status
Simulation time 246901745 ps
CPU time 0.92 seconds
Started Jun 29 06:38:06 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206128 kb
Host smart-1426e290-3ab5-4234-83c9-17028978f081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13866
43406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1386643406
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3596796934
Short name T497
Test name
Test status
Simulation time 201752683 ps
CPU time 0.8 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206200 kb
Host smart-589d2218-50be-4f84-8e5f-1d0f8ba83413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35967
96934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3596796934
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3944248524
Short name T81
Test name
Test status
Simulation time 169897256 ps
CPU time 0.78 seconds
Started Jun 29 06:38:00 PM PDT 24
Finished Jun 29 06:38:03 PM PDT 24
Peak memory 206144 kb
Host smart-0f064def-dc5a-469f-9a85-8b7f2bf916f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39442
48524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3944248524
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1521456025
Short name T1217
Test name
Test status
Simulation time 146595044 ps
CPU time 0.82 seconds
Started Jun 29 06:37:58 PM PDT 24
Finished Jun 29 06:38:01 PM PDT 24
Peak memory 206196 kb
Host smart-30e0780d-be98-425f-953b-0bcc3b61dd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15214
56025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1521456025
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1801331841
Short name T966
Test name
Test status
Simulation time 182988902 ps
CPU time 0.83 seconds
Started Jun 29 06:38:06 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206200 kb
Host smart-3498a202-9d69-4837-b08c-5ddf774a308b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18013
31841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1801331841
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3131679573
Short name T366
Test name
Test status
Simulation time 194001338 ps
CPU time 0.86 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:08 PM PDT 24
Peak memory 206216 kb
Host smart-b4491c9e-fd46-420f-93f4-0b61b97ca554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31316
79573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3131679573
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.2509109063
Short name T876
Test name
Test status
Simulation time 3643070055 ps
CPU time 24.38 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:32 PM PDT 24
Peak memory 206444 kb
Host smart-be7c7069-70ad-4858-b6bc-b805eb74643a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2509109063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.2509109063
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1559830399
Short name T1050
Test name
Test status
Simulation time 161707267 ps
CPU time 0.85 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206224 kb
Host smart-e1034382-25ab-45d1-bd32-8fb531ed23ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15598
30399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1559830399
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.624447139
Short name T1353
Test name
Test status
Simulation time 156313988 ps
CPU time 0.77 seconds
Started Jun 29 06:38:06 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206196 kb
Host smart-b739da25-6595-4d17-bf22-c747fe6984d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62444
7139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.624447139
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1192297517
Short name T803
Test name
Test status
Simulation time 4309587865 ps
CPU time 42.08 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:52 PM PDT 24
Peak memory 206436 kb
Host smart-b32131a1-4d83-4d4a-9b4e-8428694ac8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11922
97517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1192297517
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.1202355940
Short name T2081
Test name
Test status
Simulation time 46988542 ps
CPU time 0.68 seconds
Started Jun 29 06:38:11 PM PDT 24
Finished Jun 29 06:38:13 PM PDT 24
Peak memory 206204 kb
Host smart-7208b2ce-e0d1-40f1-85c4-c2d0ab6aee27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1202355940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1202355940
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.733233393
Short name T2362
Test name
Test status
Simulation time 3571669760 ps
CPU time 4.1 seconds
Started Jun 29 06:38:04 PM PDT 24
Finished Jun 29 06:38:10 PM PDT 24
Peak memory 206276 kb
Host smart-b8defe31-cb6c-49a1-99da-07c469537a0d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=733233393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.733233393
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.4240557999
Short name T1823
Test name
Test status
Simulation time 13316673321 ps
CPU time 15.21 seconds
Started Jun 29 06:38:00 PM PDT 24
Finished Jun 29 06:38:17 PM PDT 24
Peak memory 206444 kb
Host smart-09ddda30-0844-4800-8a3b-3554bdd3e9a0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4240557999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.4240557999
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2948878860
Short name T2319
Test name
Test status
Simulation time 23338527337 ps
CPU time 25.21 seconds
Started Jun 29 06:38:10 PM PDT 24
Finished Jun 29 06:38:37 PM PDT 24
Peak memory 206292 kb
Host smart-b6d75f3f-776c-42cd-991e-e08e06ef0332
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2948878860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.2948878860
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2923297118
Short name T1319
Test name
Test status
Simulation time 154321133 ps
CPU time 0.76 seconds
Started Jun 29 06:38:02 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206192 kb
Host smart-74042244-59d4-4f5e-b8f5-f8f87369aaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29232
97118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2923297118
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.989827126
Short name T2619
Test name
Test status
Simulation time 187560446 ps
CPU time 0.85 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:38:16 PM PDT 24
Peak memory 206204 kb
Host smart-0c952502-e049-4fcf-9cd0-fa80e6bafedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98982
7126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.989827126
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1571856908
Short name T1560
Test name
Test status
Simulation time 497230959 ps
CPU time 1.42 seconds
Started Jun 29 06:38:09 PM PDT 24
Finished Jun 29 06:38:12 PM PDT 24
Peak memory 206272 kb
Host smart-754d9569-544b-4989-ac2b-84b7cb9d072d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15718
56908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1571856908
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3394977431
Short name T1910
Test name
Test status
Simulation time 645866062 ps
CPU time 1.67 seconds
Started Jun 29 06:38:11 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206196 kb
Host smart-d07daff6-78df-4d23-ab73-7d3bc69dcff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33949
77431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3394977431
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.4161011000
Short name T1254
Test name
Test status
Simulation time 18486362525 ps
CPU time 37.28 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:47 PM PDT 24
Peak memory 206496 kb
Host smart-1c16bb6b-3271-4d34-acb4-d0371a29ad23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41610
11000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.4161011000
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.977984771
Short name T1375
Test name
Test status
Simulation time 464929847 ps
CPU time 1.44 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206220 kb
Host smart-141a25ed-e1d1-4b70-8757-cdfe706872fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97798
4771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.977984771
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.97030266
Short name T2323
Test name
Test status
Simulation time 151527692 ps
CPU time 0.78 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:19 PM PDT 24
Peak memory 206196 kb
Host smart-96f5015f-35b6-4f8e-a7d0-279c5eb2c8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97030
266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.97030266
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.1294908662
Short name T965
Test name
Test status
Simulation time 70407733 ps
CPU time 0.7 seconds
Started Jun 29 06:38:02 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206200 kb
Host smart-6c530d6a-c03f-4da3-ba77-420dc8313491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12949
08662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1294908662
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3656836013
Short name T2012
Test name
Test status
Simulation time 999085399 ps
CPU time 2.45 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206352 kb
Host smart-7a4d4ba5-3265-4dc7-8888-c5df22cdd25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36568
36013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3656836013
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3368802948
Short name T906
Test name
Test status
Simulation time 190424499 ps
CPU time 1.39 seconds
Started Jun 29 06:38:03 PM PDT 24
Finished Jun 29 06:38:06 PM PDT 24
Peak memory 206284 kb
Host smart-24e5ff3e-2e57-40c7-99c5-06f10e4bf6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33688
02948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3368802948
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2718837326
Short name T2162
Test name
Test status
Simulation time 225604849 ps
CPU time 0.86 seconds
Started Jun 29 06:38:06 PM PDT 24
Finished Jun 29 06:38:10 PM PDT 24
Peak memory 206220 kb
Host smart-970d2354-e587-4fe6-9b7b-80c94feb0f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27188
37326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2718837326
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.577332246
Short name T1484
Test name
Test status
Simulation time 147939171 ps
CPU time 0.83 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206208 kb
Host smart-26bd378b-0407-4c7a-9ada-3c358af185ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57733
2246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.577332246
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3287411778
Short name T658
Test name
Test status
Simulation time 162615992 ps
CPU time 0.81 seconds
Started Jun 29 06:37:59 PM PDT 24
Finished Jun 29 06:38:02 PM PDT 24
Peak memory 206192 kb
Host smart-a6c2e542-8d21-42fb-99b5-8aab2b6926a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32874
11778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3287411778
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.105096683
Short name T105
Test name
Test status
Simulation time 5141478334 ps
CPU time 135.49 seconds
Started Jun 29 06:38:09 PM PDT 24
Finished Jun 29 06:40:27 PM PDT 24
Peak memory 206488 kb
Host smart-107f0cf3-4053-4b8c-b73d-5eb4a7c1c23a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=105096683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.105096683
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.3026058552
Short name T1310
Test name
Test status
Simulation time 207185008 ps
CPU time 0.85 seconds
Started Jun 29 06:38:13 PM PDT 24
Finished Jun 29 06:38:15 PM PDT 24
Peak memory 206196 kb
Host smart-355bfb57-65f5-4efd-92d8-bcb041f17858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30260
58552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.3026058552
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3278098741
Short name T1005
Test name
Test status
Simulation time 23285350449 ps
CPU time 21.69 seconds
Started Jun 29 06:38:10 PM PDT 24
Finished Jun 29 06:38:33 PM PDT 24
Peak memory 206316 kb
Host smart-b213feef-dac3-4654-a488-8a91a94feb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32780
98741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3278098741
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.879739882
Short name T422
Test name
Test status
Simulation time 3304473244 ps
CPU time 4.28 seconds
Started Jun 29 06:38:06 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206264 kb
Host smart-2b31878c-1a71-47e1-9bf4-1b0fbd1cf97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87973
9882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.879739882
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.3714742246
Short name T1399
Test name
Test status
Simulation time 8210775819 ps
CPU time 218.91 seconds
Started Jun 29 06:38:15 PM PDT 24
Finished Jun 29 06:41:55 PM PDT 24
Peak memory 206500 kb
Host smart-c34fef69-d11a-4961-a7d9-55f905750c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37147
42246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.3714742246
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.752126260
Short name T1302
Test name
Test status
Simulation time 4246392511 ps
CPU time 40.18 seconds
Started Jun 29 06:38:12 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206460 kb
Host smart-546cd9e3-acae-4237-a188-f4f24c832a6e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=752126260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.752126260
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.2470994731
Short name T765
Test name
Test status
Simulation time 267594082 ps
CPU time 0.9 seconds
Started Jun 29 06:38:06 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206220 kb
Host smart-9f8f9434-5495-4e51-9f9e-f275d8a12518
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2470994731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.2470994731
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1661194439
Short name T1081
Test name
Test status
Simulation time 212315711 ps
CPU time 0.93 seconds
Started Jun 29 06:38:11 PM PDT 24
Finished Jun 29 06:38:13 PM PDT 24
Peak memory 206216 kb
Host smart-e95650e4-7885-47c1-8870-be8b63b7f745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16611
94439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1661194439
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1291104603
Short name T2518
Test name
Test status
Simulation time 6034233467 ps
CPU time 172.45 seconds
Started Jun 29 06:38:06 PM PDT 24
Finished Jun 29 06:41:01 PM PDT 24
Peak memory 206464 kb
Host smart-d4725a06-5e96-4df9-adb3-ac715e6d1c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12911
04603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1291104603
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1819768878
Short name T2535
Test name
Test status
Simulation time 7560838082 ps
CPU time 53.66 seconds
Started Jun 29 06:38:08 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206440 kb
Host smart-d9438b72-ba07-46cd-b689-0eac4464bb6c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1819768878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1819768878
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.1837512457
Short name T1569
Test name
Test status
Simulation time 200451166 ps
CPU time 0.85 seconds
Started Jun 29 06:38:04 PM PDT 24
Finished Jun 29 06:38:07 PM PDT 24
Peak memory 206220 kb
Host smart-5784582d-998d-406a-a374-42dbb61765ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1837512457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.1837512457
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3627644374
Short name T1996
Test name
Test status
Simulation time 147483033 ps
CPU time 0.78 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:08 PM PDT 24
Peak memory 206216 kb
Host smart-a63d1c9a-6138-4fb6-aca9-f7d4b0464bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36276
44374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3627644374
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.756086421
Short name T141
Test name
Test status
Simulation time 219057059 ps
CPU time 0.87 seconds
Started Jun 29 06:38:15 PM PDT 24
Finished Jun 29 06:38:18 PM PDT 24
Peak memory 206216 kb
Host smart-b5562730-511d-4044-a423-08cf5dfac91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75608
6421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.756086421
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1054141669
Short name T2294
Test name
Test status
Simulation time 192555692 ps
CPU time 0.83 seconds
Started Jun 29 06:38:08 PM PDT 24
Finished Jun 29 06:38:12 PM PDT 24
Peak memory 206204 kb
Host smart-2d724361-664b-479e-89a7-4f054af92434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10541
41669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1054141669
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.624798230
Short name T532
Test name
Test status
Simulation time 184577413 ps
CPU time 0.84 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206212 kb
Host smart-387ceb89-a7a3-4f28-9c84-151986cec682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62479
8230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.624798230
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1837957539
Short name T2078
Test name
Test status
Simulation time 182570319 ps
CPU time 0.81 seconds
Started Jun 29 06:38:02 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206196 kb
Host smart-4dcb4c44-fb29-4c39-a6aa-12ad0e7ade28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18379
57539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1837957539
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2890390790
Short name T2558
Test name
Test status
Simulation time 166195239 ps
CPU time 0.77 seconds
Started Jun 29 06:38:08 PM PDT 24
Finished Jun 29 06:38:12 PM PDT 24
Peak memory 206200 kb
Host smart-3cf8fe00-978b-45fd-b908-6b3a338cfd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28903
90790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2890390790
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2034176865
Short name T603
Test name
Test status
Simulation time 265832364 ps
CPU time 1.13 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:38:17 PM PDT 24
Peak memory 206216 kb
Host smart-5bf40486-9706-4902-b920-26c7d05751df
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2034176865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2034176865
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3619529323
Short name T206
Test name
Test status
Simulation time 152077965 ps
CPU time 0.74 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:08 PM PDT 24
Peak memory 206180 kb
Host smart-6d2fd4f9-9dd6-43bf-b173-1da4d886fdc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36195
29323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3619529323
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.429457889
Short name T39
Test name
Test status
Simulation time 43249275 ps
CPU time 0.65 seconds
Started Jun 29 06:38:12 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206212 kb
Host smart-c25ab385-3e8f-4e2c-9164-a438f731d1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42945
7889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.429457889
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3564091883
Short name T1771
Test name
Test status
Simulation time 14481249558 ps
CPU time 33.59 seconds
Started Jun 29 06:38:22 PM PDT 24
Finished Jun 29 06:38:57 PM PDT 24
Peak memory 206432 kb
Host smart-1248dd16-b1f8-4252-8112-c129ff5088c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35640
91883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3564091883
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.390275052
Short name T1020
Test name
Test status
Simulation time 203098347 ps
CPU time 0.87 seconds
Started Jun 29 06:38:13 PM PDT 24
Finished Jun 29 06:38:15 PM PDT 24
Peak memory 206180 kb
Host smart-f36811f3-883e-4d9f-a29c-6b33d5cc2cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39027
5052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.390275052
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.4214827037
Short name T2577
Test name
Test status
Simulation time 244649583 ps
CPU time 0.9 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:11 PM PDT 24
Peak memory 206180 kb
Host smart-cd66890a-f63f-4c04-8ad5-dedad8b2e32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42148
27037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.4214827037
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.37241691
Short name T2541
Test name
Test status
Simulation time 184280413 ps
CPU time 0.84 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:10 PM PDT 24
Peak memory 206196 kb
Host smart-e51f009f-5ea6-400e-87dc-b918c7200fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37241
691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.37241691
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2298544767
Short name T735
Test name
Test status
Simulation time 185900549 ps
CPU time 0.83 seconds
Started Jun 29 06:38:12 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206196 kb
Host smart-a9a65ac9-3591-49ee-819d-58560d41bdac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22985
44767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2298544767
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1562698489
Short name T567
Test name
Test status
Simulation time 174451214 ps
CPU time 0.78 seconds
Started Jun 29 06:38:21 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206192 kb
Host smart-ba047644-857f-4024-bebf-1593d22cdfd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15626
98489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1562698489
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1597871237
Short name T1694
Test name
Test status
Simulation time 141520251 ps
CPU time 0.78 seconds
Started Jun 29 06:38:08 PM PDT 24
Finished Jun 29 06:38:11 PM PDT 24
Peak memory 206196 kb
Host smart-b1c5502a-81a1-4fae-a029-31f82794bc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15978
71237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1597871237
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.386983647
Short name T2020
Test name
Test status
Simulation time 164148604 ps
CPU time 0.81 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:18 PM PDT 24
Peak memory 206188 kb
Host smart-b0f17207-7506-4d35-8ff6-fbdea5e768d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38698
3647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.386983647
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1195054834
Short name T370
Test name
Test status
Simulation time 249680908 ps
CPU time 1 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:19 PM PDT 24
Peak memory 206220 kb
Host smart-62047dd6-fc14-42fd-87ba-212e08316e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11950
54834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1195054834
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3711832145
Short name T2039
Test name
Test status
Simulation time 4418995036 ps
CPU time 125.09 seconds
Started Jun 29 06:38:09 PM PDT 24
Finished Jun 29 06:40:16 PM PDT 24
Peak memory 206488 kb
Host smart-090284eb-0e78-426b-ae60-c9c3f63f085c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3711832145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3711832145
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3623306105
Short name T2040
Test name
Test status
Simulation time 165019565 ps
CPU time 0.87 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:09 PM PDT 24
Peak memory 206224 kb
Host smart-4fb335e2-59cd-463e-9457-d8a8081dae7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36233
06105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3623306105
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2564924179
Short name T583
Test name
Test status
Simulation time 193050655 ps
CPU time 0.83 seconds
Started Jun 29 06:38:11 PM PDT 24
Finished Jun 29 06:38:13 PM PDT 24
Peak memory 206188 kb
Host smart-fa730d83-4e59-4166-9184-d6b3241f05bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25649
24179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2564924179
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2444364449
Short name T356
Test name
Test status
Simulation time 5158985804 ps
CPU time 146.87 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:40:37 PM PDT 24
Peak memory 206432 kb
Host smart-e48fa6d9-4cc3-4445-b0af-4ac2b62b7ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24443
64449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2444364449
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.4040318357
Short name T1440
Test name
Test status
Simulation time 35354323 ps
CPU time 0.68 seconds
Started Jun 29 06:38:09 PM PDT 24
Finished Jun 29 06:38:12 PM PDT 24
Peak memory 206184 kb
Host smart-60c34070-7b60-44ce-9a83-cd91e7d16b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4040318357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.4040318357
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.532584067
Short name T1061
Test name
Test status
Simulation time 4309983152 ps
CPU time 5.01 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:26 PM PDT 24
Peak memory 206416 kb
Host smart-a2f32d68-564b-4dc2-8102-6517e970d765
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=532584067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.532584067
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.1588001551
Short name T1739
Test name
Test status
Simulation time 13350798412 ps
CPU time 13.03 seconds
Started Jun 29 06:38:09 PM PDT 24
Finished Jun 29 06:38:24 PM PDT 24
Peak memory 206320 kb
Host smart-b1a3ead0-40be-4189-83d6-7e923e5af8f9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1588001551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.1588001551
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.3468244814
Short name T1294
Test name
Test status
Simulation time 23325576218 ps
CPU time 23.76 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:41 PM PDT 24
Peak memory 206284 kb
Host smart-4faec886-4cf2-4a78-acee-9d14a0b1823a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3468244814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.3468244814
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1138687213
Short name T440
Test name
Test status
Simulation time 168510889 ps
CPU time 0.85 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:10 PM PDT 24
Peak memory 206184 kb
Host smart-3e357175-1ec7-4a9e-8f99-7c7fa8338526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11386
87213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1138687213
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.261397666
Short name T1463
Test name
Test status
Simulation time 154814521 ps
CPU time 0.82 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:10 PM PDT 24
Peak memory 206204 kb
Host smart-5acccd81-3135-45db-8181-9a8b532547bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26139
7666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.261397666
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.2324365220
Short name T1704
Test name
Test status
Simulation time 161419221 ps
CPU time 0.81 seconds
Started Jun 29 06:38:15 PM PDT 24
Finished Jun 29 06:38:17 PM PDT 24
Peak memory 206160 kb
Host smart-e7364187-7d47-411a-aea6-0a6a9d73039d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23243
65220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.2324365220
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1060213417
Short name T2174
Test name
Test status
Simulation time 1176458745 ps
CPU time 2.62 seconds
Started Jun 29 06:38:20 PM PDT 24
Finished Jun 29 06:38:25 PM PDT 24
Peak memory 206272 kb
Host smart-32c33e78-4070-457e-b5a7-1bd06351deba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10602
13417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1060213417
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2751734136
Short name T1899
Test name
Test status
Simulation time 6576898210 ps
CPU time 12.06 seconds
Started Jun 29 06:38:09 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206444 kb
Host smart-f456058c-3477-48fc-8e2d-3ac27a311a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27517
34136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2751734136
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.904333765
Short name T1237
Test name
Test status
Simulation time 321853784 ps
CPU time 1.08 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206172 kb
Host smart-43509561-65e5-4901-9773-4eb310690c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90433
3765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.904333765
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.3947422615
Short name T1368
Test name
Test status
Simulation time 161643557 ps
CPU time 0.78 seconds
Started Jun 29 06:38:12 PM PDT 24
Finished Jun 29 06:38:13 PM PDT 24
Peak memory 206192 kb
Host smart-9e495a67-0d8a-47a6-94dc-dc8b8b4c1a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39474
22615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.3947422615
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3893782259
Short name T1025
Test name
Test status
Simulation time 66766061 ps
CPU time 0.68 seconds
Started Jun 29 06:38:01 PM PDT 24
Finished Jun 29 06:38:04 PM PDT 24
Peak memory 206208 kb
Host smart-2efb81e9-63b4-4c92-9ada-4d8fe45b016e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38937
82259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3893782259
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2424937693
Short name T1649
Test name
Test status
Simulation time 767650136 ps
CPU time 1.78 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:38:17 PM PDT 24
Peak memory 206296 kb
Host smart-025a5dcf-3c0b-487f-812f-2ac2e965cba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24249
37693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2424937693
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2089720139
Short name T2534
Test name
Test status
Simulation time 208620273 ps
CPU time 1.45 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:11 PM PDT 24
Peak memory 206324 kb
Host smart-1977a501-0f7b-4175-97cb-6a45ed1c161a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20897
20139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2089720139
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.935794551
Short name T2542
Test name
Test status
Simulation time 233876431 ps
CPU time 1.04 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206212 kb
Host smart-684c0b5d-8f5e-4e03-b5e2-488751850e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93579
4551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.935794551
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2255941638
Short name T1177
Test name
Test status
Simulation time 141738275 ps
CPU time 0.74 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:19 PM PDT 24
Peak memory 206212 kb
Host smart-dc2c1e4d-eef5-4b50-b1d1-cc0e4e743694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22559
41638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2255941638
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3120290361
Short name T725
Test name
Test status
Simulation time 240603153 ps
CPU time 0.93 seconds
Started Jun 29 06:38:10 PM PDT 24
Finished Jun 29 06:38:12 PM PDT 24
Peak memory 206216 kb
Host smart-bacec5c9-f77c-4b68-9f3c-53c0c427101c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31202
90361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3120290361
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.2707199811
Short name T927
Test name
Test status
Simulation time 5500702103 ps
CPU time 155.8 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:40:56 PM PDT 24
Peak memory 206656 kb
Host smart-6f9d7f1a-c300-4bb4-99d7-41e4de95f2da
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2707199811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.2707199811
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3251309883
Short name T2191
Test name
Test status
Simulation time 180034864 ps
CPU time 0.83 seconds
Started Jun 29 06:38:11 PM PDT 24
Finished Jun 29 06:38:13 PM PDT 24
Peak memory 206196 kb
Host smart-a01e2bd7-684a-42ab-97ef-b2df2368a273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32513
09883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3251309883
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.731044494
Short name T337
Test name
Test status
Simulation time 23342991908 ps
CPU time 24.59 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:38:40 PM PDT 24
Peak memory 206316 kb
Host smart-a34896e6-f5f8-4eff-913f-18a9e756275a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73104
4494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.731044494
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1324057543
Short name T2244
Test name
Test status
Simulation time 3356338406 ps
CPU time 4.26 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206252 kb
Host smart-684dd9ce-ce88-48d6-9194-227f77d9f47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13240
57543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1324057543
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1830138238
Short name T2622
Test name
Test status
Simulation time 5783716545 ps
CPU time 157.44 seconds
Started Jun 29 06:38:08 PM PDT 24
Finished Jun 29 06:40:48 PM PDT 24
Peak memory 206472 kb
Host smart-12222db3-0d8b-43f4-aa0c-4fb1b2172576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18301
38238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1830138238
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1635037069
Short name T672
Test name
Test status
Simulation time 5100035185 ps
CPU time 146.57 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:40:42 PM PDT 24
Peak memory 206460 kb
Host smart-6b930041-c828-49ab-a9fa-4960e07e54ec
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1635037069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1635037069
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.2306719399
Short name T317
Test name
Test status
Simulation time 269088442 ps
CPU time 0.94 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206172 kb
Host smart-380099c8-1c01-48d4-af95-8d41da7d35ad
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2306719399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.2306719399
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3325427589
Short name T879
Test name
Test status
Simulation time 187726246 ps
CPU time 0.9 seconds
Started Jun 29 06:38:12 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206204 kb
Host smart-8a52df56-4967-4d3a-943d-2c284de5162e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254
27589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3325427589
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1101518485
Short name T984
Test name
Test status
Simulation time 4305327388 ps
CPU time 41.04 seconds
Started Jun 29 06:38:11 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206500 kb
Host smart-b1a3db7b-8fb0-42df-91cc-40a979bcad02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11015
18485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1101518485
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3362497852
Short name T1531
Test name
Test status
Simulation time 4943031315 ps
CPU time 34.36 seconds
Started Jun 29 06:38:23 PM PDT 24
Finished Jun 29 06:38:58 PM PDT 24
Peak memory 206460 kb
Host smart-52fe91e1-c26e-48f3-8f51-e82031ea6c50
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3362497852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3362497852
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.1190042846
Short name T2625
Test name
Test status
Simulation time 171076705 ps
CPU time 0.79 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206172 kb
Host smart-22968a10-da72-410d-8971-d28fed917d99
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1190042846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.1190042846
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1736930239
Short name T2501
Test name
Test status
Simulation time 171763834 ps
CPU time 0.77 seconds
Started Jun 29 06:38:05 PM PDT 24
Finished Jun 29 06:38:08 PM PDT 24
Peak memory 206216 kb
Host smart-4a2cdfcc-6b0d-4e59-b7ac-d5e86f61e3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17369
30239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1736930239
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.579310305
Short name T140
Test name
Test status
Simulation time 174428770 ps
CPU time 0.79 seconds
Started Jun 29 06:38:08 PM PDT 24
Finished Jun 29 06:38:11 PM PDT 24
Peak memory 206192 kb
Host smart-42f1c1df-315d-4570-81c3-fbe9b5df5202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57931
0305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.579310305
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3719867536
Short name T2434
Test name
Test status
Simulation time 169774718 ps
CPU time 0.81 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:11 PM PDT 24
Peak memory 206180 kb
Host smart-961d8237-94d7-4882-a9f1-60ca3f360ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37198
67536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3719867536
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2970234616
Short name T747
Test name
Test status
Simulation time 155735989 ps
CPU time 0.78 seconds
Started Jun 29 06:38:04 PM PDT 24
Finished Jun 29 06:38:07 PM PDT 24
Peak memory 206196 kb
Host smart-fa57986b-1b17-4cd8-8ff9-2ed19d65869c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29702
34616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2970234616
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3134869331
Short name T1144
Test name
Test status
Simulation time 191585185 ps
CPU time 0.87 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 205892 kb
Host smart-7437118f-433d-4ad4-9844-f9d7a9996f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31348
69331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3134869331
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.149468265
Short name T466
Test name
Test status
Simulation time 158291759 ps
CPU time 0.78 seconds
Started Jun 29 06:38:09 PM PDT 24
Finished Jun 29 06:38:12 PM PDT 24
Peak memory 206220 kb
Host smart-4c32f7b7-a363-456b-841a-82ba6e2dbfa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14946
8265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.149468265
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.240630706
Short name T1703
Test name
Test status
Simulation time 284497805 ps
CPU time 0.98 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:38:17 PM PDT 24
Peak memory 206224 kb
Host smart-dc2c3ae4-1dc3-4a4d-a5e5-22e3830bea9f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=240630706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.240630706
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.951367519
Short name T781
Test name
Test status
Simulation time 138124613 ps
CPU time 0.72 seconds
Started Jun 29 06:38:13 PM PDT 24
Finished Jun 29 06:38:15 PM PDT 24
Peak memory 206212 kb
Host smart-9e4d5e7c-a6b7-4b1e-aebf-63c68a41978c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95136
7519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.951367519
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.341407650
Short name T1036
Test name
Test status
Simulation time 34243952 ps
CPU time 0.68 seconds
Started Jun 29 06:38:07 PM PDT 24
Finished Jun 29 06:38:10 PM PDT 24
Peak memory 206212 kb
Host smart-e38593e5-e765-4969-86d0-83f490daeeea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34140
7650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.341407650
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.313736912
Short name T1198
Test name
Test status
Simulation time 16639670864 ps
CPU time 33.42 seconds
Started Jun 29 06:38:10 PM PDT 24
Finished Jun 29 06:38:45 PM PDT 24
Peak memory 206484 kb
Host smart-c05545b9-fb79-4bb3-b2d0-69e25ed1d651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31373
6912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.313736912
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.12900951
Short name T2037
Test name
Test status
Simulation time 198027875 ps
CPU time 0.89 seconds
Started Jun 29 06:38:28 PM PDT 24
Finished Jun 29 06:38:29 PM PDT 24
Peak memory 206196 kb
Host smart-ad49fdb7-5c01-4d42-9a7f-a09070499c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12900
951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.12900951
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.30327868
Short name T793
Test name
Test status
Simulation time 234368827 ps
CPU time 0.92 seconds
Started Jun 29 06:38:13 PM PDT 24
Finished Jun 29 06:38:16 PM PDT 24
Peak memory 206132 kb
Host smart-52eaa48b-a273-4a18-a7dc-c0a74534e221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30327
868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.30327868
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.1235938554
Short name T2532
Test name
Test status
Simulation time 190808511 ps
CPU time 0.88 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:38:17 PM PDT 24
Peak memory 206204 kb
Host smart-9f5d048c-6daa-468c-b9b6-3afdfe647d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12359
38554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.1235938554
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1940690007
Short name T835
Test name
Test status
Simulation time 188743989 ps
CPU time 0.79 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:20 PM PDT 24
Peak memory 206204 kb
Host smart-27fd42c5-504e-4752-861e-cc335f1e93a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19406
90007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1940690007
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1891760158
Short name T2425
Test name
Test status
Simulation time 169858546 ps
CPU time 0.85 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:18 PM PDT 24
Peak memory 206192 kb
Host smart-23bfc9b4-f8df-4179-9a6f-7c23af42c214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18917
60158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1891760158
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1309947979
Short name T880
Test name
Test status
Simulation time 197113602 ps
CPU time 0.82 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:38:16 PM PDT 24
Peak memory 206188 kb
Host smart-564c8d1e-9d4c-4fd8-9a27-4c9aa39eee7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13099
47979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1309947979
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2342208114
Short name T637
Test name
Test status
Simulation time 179052715 ps
CPU time 0.89 seconds
Started Jun 29 06:38:21 PM PDT 24
Finished Jun 29 06:38:24 PM PDT 24
Peak memory 206208 kb
Host smart-133e69ee-ce79-41fb-85f0-caf080d8dd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23422
08114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2342208114
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3855648504
Short name T1490
Test name
Test status
Simulation time 5783917474 ps
CPU time 154.32 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:40:50 PM PDT 24
Peak memory 206520 kb
Host smart-58e8ace6-3e4c-4d2d-af16-5e89eeb1335a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3855648504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3855648504
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1059235553
Short name T2187
Test name
Test status
Simulation time 239861928 ps
CPU time 0.96 seconds
Started Jun 29 06:38:13 PM PDT 24
Finished Jun 29 06:38:16 PM PDT 24
Peak memory 206160 kb
Host smart-cc4ba2e8-9af1-4556-b1f0-b5aced1a0157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10592
35553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1059235553
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2608924816
Short name T1673
Test name
Test status
Simulation time 160228030 ps
CPU time 0.78 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206148 kb
Host smart-51693c75-52b9-4402-b36f-e27d4778ec75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26089
24816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2608924816
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3926770078
Short name T1519
Test name
Test status
Simulation time 5322282249 ps
CPU time 146.6 seconds
Started Jun 29 06:38:10 PM PDT 24
Finished Jun 29 06:40:38 PM PDT 24
Peak memory 206412 kb
Host smart-905c9c84-0eac-493e-a462-047706fb41a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39267
70078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3926770078
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.1172686290
Short name T1850
Test name
Test status
Simulation time 50354842 ps
CPU time 0.71 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:19 PM PDT 24
Peak memory 206136 kb
Host smart-a5c74f52-7ac2-417a-bde4-61a56f1ed329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1172686290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.1172686290
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1278885207
Short name T1549
Test name
Test status
Simulation time 3805064918 ps
CPU time 4.28 seconds
Started Jun 29 06:38:11 PM PDT 24
Finished Jun 29 06:38:17 PM PDT 24
Peak memory 206380 kb
Host smart-f0758380-29fc-4819-8433-88cfe37934dc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1278885207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1278885207
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.4031405869
Short name T2581
Test name
Test status
Simulation time 13324334294 ps
CPU time 12.58 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:34 PM PDT 24
Peak memory 206292 kb
Host smart-044c35a3-9d88-4440-b09c-caf1373dc09c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4031405869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.4031405869
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3809387842
Short name T1474
Test name
Test status
Simulation time 23394089710 ps
CPU time 26.12 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:46 PM PDT 24
Peak memory 206472 kb
Host smart-9259b862-05cc-4018-af45-a5821a2787b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3809387842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.3809387842
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3110314843
Short name T613
Test name
Test status
Simulation time 166698910 ps
CPU time 0.85 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:19 PM PDT 24
Peak memory 206192 kb
Host smart-02d36a1f-e24c-44ef-ae15-0c3d31fe25af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31103
14843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3110314843
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.145544640
Short name T850
Test name
Test status
Simulation time 163792305 ps
CPU time 0.76 seconds
Started Jun 29 06:38:15 PM PDT 24
Finished Jun 29 06:38:18 PM PDT 24
Peak memory 206196 kb
Host smart-6b8262e5-ca2f-411e-8ae0-c090ba2d7ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14554
4640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.145544640
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3378274645
Short name T1546
Test name
Test status
Simulation time 275718316 ps
CPU time 0.96 seconds
Started Jun 29 06:38:15 PM PDT 24
Finished Jun 29 06:38:17 PM PDT 24
Peak memory 206196 kb
Host smart-fc724e6e-a78b-4719-8ada-ad68ba4af1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33782
74645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3378274645
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1707881430
Short name T2215
Test name
Test status
Simulation time 472734819 ps
CPU time 1.33 seconds
Started Jun 29 06:38:22 PM PDT 24
Finished Jun 29 06:38:25 PM PDT 24
Peak memory 206188 kb
Host smart-888134a7-136c-468e-a408-3d47b71a3ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17078
81430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1707881430
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.883994913
Short name T2470
Test name
Test status
Simulation time 9712797514 ps
CPU time 18.45 seconds
Started Jun 29 06:38:21 PM PDT 24
Finished Jun 29 06:38:41 PM PDT 24
Peak memory 206420 kb
Host smart-8c01ef6f-644d-42c9-b1fb-244dfebe128c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88399
4913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.883994913
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1928278773
Short name T1757
Test name
Test status
Simulation time 479721414 ps
CPU time 1.36 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206152 kb
Host smart-3bbabe20-89ef-4341-ab3a-00d3d0e2677f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19282
78773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1928278773
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1181525776
Short name T683
Test name
Test status
Simulation time 135663412 ps
CPU time 0.76 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:20 PM PDT 24
Peak memory 206192 kb
Host smart-0a0a8abe-a8c9-4b93-8eab-e5c02f111ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11815
25776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1181525776
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3848759653
Short name T1409
Test name
Test status
Simulation time 54122158 ps
CPU time 0.69 seconds
Started Jun 29 06:38:12 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206220 kb
Host smart-33280497-7dab-4a90-b918-d258f28a90d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38487
59653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3848759653
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.4220107663
Short name T1596
Test name
Test status
Simulation time 949921650 ps
CPU time 2.26 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:20 PM PDT 24
Peak memory 206368 kb
Host smart-e316b5f4-dcab-4762-8c51-8f5e4fb23b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42201
07663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.4220107663
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2972648659
Short name T2278
Test name
Test status
Simulation time 174057426 ps
CPU time 1.69 seconds
Started Jun 29 06:38:23 PM PDT 24
Finished Jun 29 06:38:25 PM PDT 24
Peak memory 206276 kb
Host smart-d1b5aa9d-eb35-4955-b641-fc882f72aa02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29726
48659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2972648659
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2010762224
Short name T2064
Test name
Test status
Simulation time 247779901 ps
CPU time 1 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206200 kb
Host smart-416bb471-2dad-4c9a-a98f-2a99ca67678e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20107
62224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2010762224
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.4002289330
Short name T1640
Test name
Test status
Simulation time 144201335 ps
CPU time 0.8 seconds
Started Jun 29 06:38:20 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206212 kb
Host smart-879a035b-d459-4942-804f-cd773031e2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40022
89330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.4002289330
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2067475250
Short name T1260
Test name
Test status
Simulation time 234105436 ps
CPU time 0.86 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:19 PM PDT 24
Peak memory 206216 kb
Host smart-28c595bf-699b-4e47-8016-ce595c2f7c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20674
75250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2067475250
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.1015461162
Short name T2461
Test name
Test status
Simulation time 8242866542 ps
CPU time 78.08 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:39:34 PM PDT 24
Peak memory 206444 kb
Host smart-9bf94521-11c6-4865-ad9a-f207e2212563
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1015461162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.1015461162
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.811961470
Short name T358
Test name
Test status
Simulation time 243506531 ps
CPU time 0.88 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206196 kb
Host smart-af18ca29-e38c-4efa-9afb-8b157c48b09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81196
1470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.811961470
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1201373523
Short name T1929
Test name
Test status
Simulation time 23276425271 ps
CPU time 27.85 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:46 PM PDT 24
Peak memory 206492 kb
Host smart-669d3d10-b0f3-40c5-95a2-3f7f89341a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12013
73523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1201373523
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2990623525
Short name T701
Test name
Test status
Simulation time 3318646132 ps
CPU time 4.32 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206252 kb
Host smart-a78db68b-3535-4ffb-b938-af60d89e029a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29906
23525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2990623525
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.1190137051
Short name T1181
Test name
Test status
Simulation time 11287149508 ps
CPU time 101.32 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:39:57 PM PDT 24
Peak memory 206484 kb
Host smart-c5a61e60-0d42-4a12-b809-922e1ae39b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11901
37051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.1190137051
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.1671569224
Short name T742
Test name
Test status
Simulation time 3012228153 ps
CPU time 80.03 seconds
Started Jun 29 06:38:28 PM PDT 24
Finished Jun 29 06:39:49 PM PDT 24
Peak memory 206404 kb
Host smart-ecaaf19b-83fc-4abb-83c4-018fb1e96143
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1671569224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.1671569224
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.2258329313
Short name T769
Test name
Test status
Simulation time 235286592 ps
CPU time 1.01 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:19 PM PDT 24
Peak memory 206220 kb
Host smart-bb768b04-52c1-4129-9fd2-fc915b939d18
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2258329313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.2258329313
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2093106141
Short name T498
Test name
Test status
Simulation time 218073163 ps
CPU time 0.89 seconds
Started Jun 29 06:38:15 PM PDT 24
Finished Jun 29 06:38:18 PM PDT 24
Peak memory 206204 kb
Host smart-9ade465b-3135-4d5b-87e4-4702d36758e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20931
06141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2093106141
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1692483873
Short name T2023
Test name
Test status
Simulation time 6491482983 ps
CPU time 48.21 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206484 kb
Host smart-4cbf7612-bbff-4668-816d-2df8039159fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16924
83873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1692483873
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.1833853793
Short name T1464
Test name
Test status
Simulation time 7915932868 ps
CPU time 57.96 seconds
Started Jun 29 06:38:21 PM PDT 24
Finished Jun 29 06:39:20 PM PDT 24
Peak memory 206484 kb
Host smart-b7cf4a4a-933e-489f-9803-a80409885927
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1833853793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.1833853793
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.3200210071
Short name T1554
Test name
Test status
Simulation time 180872532 ps
CPU time 0.77 seconds
Started Jun 29 06:38:12 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206172 kb
Host smart-7eee3e96-fb3f-48d2-9670-12a2f38d2e0d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3200210071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.3200210071
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2363370184
Short name T585
Test name
Test status
Simulation time 167434276 ps
CPU time 0.9 seconds
Started Jun 29 06:38:08 PM PDT 24
Finished Jun 29 06:38:12 PM PDT 24
Peak memory 206216 kb
Host smart-066f0c5f-bfd7-4688-935a-5738fef2eaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23633
70184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2363370184
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1143489213
Short name T137
Test name
Test status
Simulation time 239902993 ps
CPU time 0.93 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206188 kb
Host smart-c842556c-d892-4777-98f0-e261bfb1a23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11434
89213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1143489213
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.4204317898
Short name T2451
Test name
Test status
Simulation time 157078322 ps
CPU time 0.83 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206204 kb
Host smart-24930554-6d3a-44e4-92d3-a218fa409598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42043
17898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.4204317898
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3157997582
Short name T1815
Test name
Test status
Simulation time 182596047 ps
CPU time 0.87 seconds
Started Jun 29 06:38:20 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206196 kb
Host smart-3acdd25c-1dbe-40d0-aa4f-cb02bed6e3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31579
97582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3157997582
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2324937279
Short name T2033
Test name
Test status
Simulation time 164062973 ps
CPU time 0.83 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:19 PM PDT 24
Peak memory 206208 kb
Host smart-15e985d0-c103-4a08-bd2b-75b4fe0e23e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23249
37279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2324937279
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3022609008
Short name T190
Test name
Test status
Simulation time 200636534 ps
CPU time 0.85 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206200 kb
Host smart-d30884f8-a04a-49cb-b632-3a5a003dfdc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30226
09008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3022609008
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2200933847
Short name T2354
Test name
Test status
Simulation time 221353969 ps
CPU time 0.95 seconds
Started Jun 29 06:38:21 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206224 kb
Host smart-9f492029-8c60-49d8-aad0-0697d170abab
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2200933847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2200933847
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3101815724
Short name T1149
Test name
Test status
Simulation time 147512410 ps
CPU time 0.76 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206212 kb
Host smart-680d43d4-1e49-4731-abe9-b54263de8084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31018
15724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3101815724
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1692701390
Short name T43
Test name
Test status
Simulation time 42526317 ps
CPU time 0.64 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:18 PM PDT 24
Peak memory 206212 kb
Host smart-286b0892-b76a-476b-82e2-f76a0e4c47f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16927
01390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1692701390
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2590235781
Short name T2128
Test name
Test status
Simulation time 13590975310 ps
CPU time 33.27 seconds
Started Jun 29 06:38:15 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206488 kb
Host smart-e70e04b3-b92e-4ffe-8e57-ed68e0f8d55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25902
35781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2590235781
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.641035157
Short name T1840
Test name
Test status
Simulation time 219449158 ps
CPU time 0.95 seconds
Started Jun 29 06:38:20 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206204 kb
Host smart-511da191-3ca6-4c5e-a331-eeb17e1b1e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64103
5157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.641035157
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.4167820156
Short name T1959
Test name
Test status
Simulation time 192187832 ps
CPU time 0.83 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206216 kb
Host smart-ce22a8c5-b81c-4919-ba5a-f6444fcb1546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41678
20156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.4167820156
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2086159758
Short name T1466
Test name
Test status
Simulation time 221799295 ps
CPU time 0.87 seconds
Started Jun 29 06:38:20 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206168 kb
Host smart-1fb51a3d-5c44-47d6-8465-43cce34880cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20861
59758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2086159758
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2217823201
Short name T1348
Test name
Test status
Simulation time 153011604 ps
CPU time 0.75 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:20 PM PDT 24
Peak memory 206196 kb
Host smart-d7dd44ac-f3a9-4e8a-9c59-0d86cbd86a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22178
23201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2217823201
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3339236219
Short name T379
Test name
Test status
Simulation time 151952145 ps
CPU time 0.8 seconds
Started Jun 29 06:38:12 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206112 kb
Host smart-0fbe28ba-d058-4655-8495-633f775009fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33392
36219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3339236219
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1426658186
Short name T1613
Test name
Test status
Simulation time 157368819 ps
CPU time 0.79 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206196 kb
Host smart-30a68b8d-8ec8-4081-abed-b5fc674e64f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14266
58186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1426658186
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2201044721
Short name T2503
Test name
Test status
Simulation time 167809897 ps
CPU time 0.79 seconds
Started Jun 29 06:38:13 PM PDT 24
Finished Jun 29 06:38:15 PM PDT 24
Peak memory 206172 kb
Host smart-c5f11bec-f6a9-4087-afd6-3623668543a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22010
44721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2201044721
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2964796076
Short name T1725
Test name
Test status
Simulation time 205051157 ps
CPU time 0.85 seconds
Started Jun 29 06:38:13 PM PDT 24
Finished Jun 29 06:38:15 PM PDT 24
Peak memory 206216 kb
Host smart-a51e3c3e-e6d0-4b16-a62f-30e86fba07c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29647
96076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2964796076
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2736826603
Short name T2568
Test name
Test status
Simulation time 5702980716 ps
CPU time 150.37 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:40:46 PM PDT 24
Peak memory 206488 kb
Host smart-84e71855-5af2-4a5d-83d0-158620d97615
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2736826603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2736826603
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2186108238
Short name T956
Test name
Test status
Simulation time 167680437 ps
CPU time 0.79 seconds
Started Jun 29 06:38:14 PM PDT 24
Finished Jun 29 06:38:16 PM PDT 24
Peak memory 206224 kb
Host smart-23da5ce0-1c35-402a-8e74-2008eef38c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21861
08238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2186108238
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1067727430
Short name T1303
Test name
Test status
Simulation time 165686407 ps
CPU time 0.76 seconds
Started Jun 29 06:38:12 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 206192 kb
Host smart-ab46dea8-4313-4cbf-a4e3-ae334a5af64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10677
27430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1067727430
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.805475920
Short name T967
Test name
Test status
Simulation time 7705773529 ps
CPU time 220.74 seconds
Started Jun 29 06:38:21 PM PDT 24
Finished Jun 29 06:42:03 PM PDT 24
Peak memory 206440 kb
Host smart-f37b8e2f-4ffe-4108-a574-9e4899068ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80547
5920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.805475920
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.1548021728
Short name T1612
Test name
Test status
Simulation time 48723700 ps
CPU time 0.66 seconds
Started Jun 29 06:38:26 PM PDT 24
Finished Jun 29 06:38:27 PM PDT 24
Peak memory 206212 kb
Host smart-e2ebc595-f800-4968-9e64-be083461bd08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1548021728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.1548021728
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.206379329
Short name T1622
Test name
Test status
Simulation time 3783501531 ps
CPU time 4.26 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206280 kb
Host smart-0ae2a82d-c86e-4c87-be48-2cbf830234bf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=206379329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.206379329
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2534238196
Short name T1644
Test name
Test status
Simulation time 13364973878 ps
CPU time 13 seconds
Started Jun 29 06:38:32 PM PDT 24
Finished Jun 29 06:38:45 PM PDT 24
Peak memory 206328 kb
Host smart-8d5b8691-9933-400b-9666-c9d570c3df23
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2534238196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2534238196
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.4150890194
Short name T569
Test name
Test status
Simulation time 23310792779 ps
CPU time 23.3 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:41 PM PDT 24
Peak memory 206320 kb
Host smart-879fc6c5-83fd-4a9a-8bf3-0dca46d90e80
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4150890194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.4150890194
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2327113400
Short name T519
Test name
Test status
Simulation time 155347090 ps
CPU time 0.79 seconds
Started Jun 29 06:38:15 PM PDT 24
Finished Jun 29 06:38:17 PM PDT 24
Peak memory 206196 kb
Host smart-373551c6-f591-4610-91e9-fc879970bf6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23271
13400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2327113400
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1914451810
Short name T2088
Test name
Test status
Simulation time 143548097 ps
CPU time 0.76 seconds
Started Jun 29 06:38:11 PM PDT 24
Finished Jun 29 06:38:13 PM PDT 24
Peak memory 206196 kb
Host smart-698d8da6-529c-4058-be7a-f7a7d5dea98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19144
51810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1914451810
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.936608573
Short name T1594
Test name
Test status
Simulation time 208640251 ps
CPU time 0.89 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:18 PM PDT 24
Peak memory 206200 kb
Host smart-e10c89f8-1304-4971-bb04-36d9c21b5cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93660
8573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.936608573
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1435023288
Short name T1456
Test name
Test status
Simulation time 403303846 ps
CPU time 1.18 seconds
Started Jun 29 06:38:25 PM PDT 24
Finished Jun 29 06:38:26 PM PDT 24
Peak memory 206192 kb
Host smart-180147dd-b064-472b-9f35-8d4d3f2008a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14350
23288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1435023288
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.2434248398
Short name T114
Test name
Test status
Simulation time 6039932240 ps
CPU time 11.76 seconds
Started Jun 29 06:38:21 PM PDT 24
Finished Jun 29 06:38:34 PM PDT 24
Peak memory 206408 kb
Host smart-2527f3d7-51b0-4c6f-8e66-a44211700b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24342
48398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.2434248398
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1556096090
Short name T1101
Test name
Test status
Simulation time 474586757 ps
CPU time 1.45 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206200 kb
Host smart-2134bd66-db75-45d2-8f7e-9f737c1ca380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15560
96090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1556096090
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.947037761
Short name T662
Test name
Test status
Simulation time 171946781 ps
CPU time 0.78 seconds
Started Jun 29 06:38:25 PM PDT 24
Finished Jun 29 06:38:26 PM PDT 24
Peak memory 206188 kb
Host smart-416afa68-2430-4e91-95c1-3e5af266ef5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94703
7761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.947037761
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.404902775
Short name T990
Test name
Test status
Simulation time 74228182 ps
CPU time 0.7 seconds
Started Jun 29 06:38:35 PM PDT 24
Finished Jun 29 06:38:36 PM PDT 24
Peak memory 206208 kb
Host smart-7e0dad66-7a8c-48e0-a85b-9dc1ce923fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40490
2775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.404902775
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2942726439
Short name T319
Test name
Test status
Simulation time 849163246 ps
CPU time 2.05 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:20 PM PDT 24
Peak memory 206272 kb
Host smart-c49900b7-4cf8-4480-ab9b-2339859c7958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29427
26439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2942726439
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.501217581
Short name T2401
Test name
Test status
Simulation time 311439685 ps
CPU time 2.44 seconds
Started Jun 29 06:38:34 PM PDT 24
Finished Jun 29 06:38:37 PM PDT 24
Peak memory 206236 kb
Host smart-b16cb116-bf1e-46f2-ba92-19c5f58ad28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50121
7581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.501217581
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2217315488
Short name T711
Test name
Test status
Simulation time 208639181 ps
CPU time 0.84 seconds
Started Jun 29 06:38:21 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206148 kb
Host smart-d0a73000-0201-4871-aefd-c6e1368730b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22173
15488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2217315488
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1283724231
Short name T1029
Test name
Test status
Simulation time 142677597 ps
CPU time 0.74 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206208 kb
Host smart-43b57a42-6620-4bd9-b306-3bf57416b105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12837
24231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1283724231
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.4120529132
Short name T1044
Test name
Test status
Simulation time 287238178 ps
CPU time 0.95 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:20 PM PDT 24
Peak memory 206216 kb
Host smart-1f565693-139a-4ea6-8cf7-f89acecb5088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41205
29132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.4120529132
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.4106354316
Short name T1377
Test name
Test status
Simulation time 7225208647 ps
CPU time 52.21 seconds
Started Jun 29 06:38:20 PM PDT 24
Finished Jun 29 06:39:14 PM PDT 24
Peak memory 206384 kb
Host smart-2c080979-4578-4b7f-94ce-2cb5df828890
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4106354316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.4106354316
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1212074500
Short name T515
Test name
Test status
Simulation time 188915972 ps
CPU time 0.86 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206196 kb
Host smart-0b9eda6d-4336-4f2c-b9a1-4e93a64f764c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12120
74500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1212074500
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.2020033334
Short name T1647
Test name
Test status
Simulation time 23331326171 ps
CPU time 24.61 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:44 PM PDT 24
Peak memory 206316 kb
Host smart-4f95e016-73a4-4a78-9a83-6710e7745470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20200
33334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.2020033334
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.3220929254
Short name T2390
Test name
Test status
Simulation time 3301878737 ps
CPU time 3.75 seconds
Started Jun 29 06:38:28 PM PDT 24
Finished Jun 29 06:38:32 PM PDT 24
Peak memory 206256 kb
Host smart-71986c48-16b2-419f-b7ae-447a0ebb0139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32209
29254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3220929254
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1884126456
Short name T2449
Test name
Test status
Simulation time 6644013040 ps
CPU time 62.54 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:39:25 PM PDT 24
Peak memory 206424 kb
Host smart-ed2b22d9-373e-4b06-a070-a3d199bb042e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18841
26456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1884126456
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3070533722
Short name T2264
Test name
Test status
Simulation time 4937707596 ps
CPU time 36.7 seconds
Started Jun 29 06:38:32 PM PDT 24
Finished Jun 29 06:39:09 PM PDT 24
Peak memory 206500 kb
Host smart-15fdd50b-0464-409b-b6c1-23cddeedcbfd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3070533722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3070533722
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1550886626
Short name T2126
Test name
Test status
Simulation time 262015679 ps
CPU time 0.95 seconds
Started Jun 29 06:38:20 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206216 kb
Host smart-edd4ed16-a883-41dd-bbc8-f457dcd61c7a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1550886626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1550886626
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3609044749
Short name T1758
Test name
Test status
Simulation time 206109161 ps
CPU time 0.85 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206216 kb
Host smart-17ffc201-97fa-46fb-982e-69e4609a35c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36090
44749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3609044749
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2317506407
Short name T718
Test name
Test status
Simulation time 6086162374 ps
CPU time 58.45 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206504 kb
Host smart-d56d8b6b-0387-4366-9d3a-67e562adc1f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23175
06407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2317506407
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.1286253622
Short name T2450
Test name
Test status
Simulation time 3273854640 ps
CPU time 89.8 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206452 kb
Host smart-f0bc9b02-d602-480c-a37f-c49ffa4c02a0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1286253622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1286253622
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2684348129
Short name T954
Test name
Test status
Simulation time 163329399 ps
CPU time 0.8 seconds
Started Jun 29 06:38:26 PM PDT 24
Finished Jun 29 06:38:27 PM PDT 24
Peak memory 206220 kb
Host smart-0aa858ba-51ce-42e6-b6f6-3d678f1415dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2684348129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2684348129
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3265461030
Short name T1953
Test name
Test status
Simulation time 211518241 ps
CPU time 0.81 seconds
Started Jun 29 06:38:22 PM PDT 24
Finished Jun 29 06:38:24 PM PDT 24
Peak memory 206216 kb
Host smart-2561e977-3c90-44f1-aa7e-33baa454c37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32654
61030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3265461030
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1663853913
Short name T150
Test name
Test status
Simulation time 219049201 ps
CPU time 0.89 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206196 kb
Host smart-33fa85ac-8b9e-4fb8-a5c6-f0579fad115c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16638
53913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1663853913
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.587055082
Short name T933
Test name
Test status
Simulation time 203816606 ps
CPU time 0.9 seconds
Started Jun 29 06:38:30 PM PDT 24
Finished Jun 29 06:38:32 PM PDT 24
Peak memory 206204 kb
Host smart-844d8aae-e816-4aa7-985f-e05fd99d78ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58705
5082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.587055082
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3344199112
Short name T107
Test name
Test status
Simulation time 159056616 ps
CPU time 0.86 seconds
Started Jun 29 06:38:37 PM PDT 24
Finished Jun 29 06:38:38 PM PDT 24
Peak memory 206196 kb
Host smart-eb359c86-61cc-412c-90c5-f045818adc0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33441
99112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3344199112
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.208431191
Short name T1389
Test name
Test status
Simulation time 170595984 ps
CPU time 0.8 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206196 kb
Host smart-6d8a429d-f504-4397-91ea-3a6d879e63aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20843
1191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.208431191
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.462895450
Short name T2386
Test name
Test status
Simulation time 152676149 ps
CPU time 0.79 seconds
Started Jun 29 06:38:32 PM PDT 24
Finished Jun 29 06:38:33 PM PDT 24
Peak memory 206220 kb
Host smart-70531553-c0e6-4315-a1d9-eb0c0ee789ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46289
5450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.462895450
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.981348581
Short name T1954
Test name
Test status
Simulation time 300934908 ps
CPU time 1.08 seconds
Started Jun 29 06:38:24 PM PDT 24
Finished Jun 29 06:38:26 PM PDT 24
Peak memory 206200 kb
Host smart-75be29be-ae4a-4aef-88fb-2460de85b382
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=981348581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.981348581
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2224092389
Short name T1246
Test name
Test status
Simulation time 147017955 ps
CPU time 0.84 seconds
Started Jun 29 06:38:38 PM PDT 24
Finished Jun 29 06:38:40 PM PDT 24
Peak memory 206208 kb
Host smart-19ab90b0-28d7-451d-af9d-28a6f221a7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22240
92389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2224092389
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1989423435
Short name T2329
Test name
Test status
Simulation time 42137115 ps
CPU time 0.73 seconds
Started Jun 29 06:38:28 PM PDT 24
Finished Jun 29 06:38:29 PM PDT 24
Peak memory 206212 kb
Host smart-b6ac9500-7be6-43f2-92b9-de9750fc547d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19894
23435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1989423435
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.755315701
Short name T2025
Test name
Test status
Simulation time 21397001243 ps
CPU time 54.21 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:39:13 PM PDT 24
Peak memory 206444 kb
Host smart-f3a1c1c6-9438-46d3-8fa5-758b87869547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75531
5701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.755315701
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2746502035
Short name T1584
Test name
Test status
Simulation time 183773045 ps
CPU time 0.85 seconds
Started Jun 29 06:38:28 PM PDT 24
Finished Jun 29 06:38:29 PM PDT 24
Peak memory 206196 kb
Host smart-f30e7979-ac64-4e7a-aef5-6ad61d1567de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27465
02035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2746502035
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3278641821
Short name T2199
Test name
Test status
Simulation time 194262590 ps
CPU time 0.84 seconds
Started Jun 29 06:38:22 PM PDT 24
Finished Jun 29 06:38:24 PM PDT 24
Peak memory 206204 kb
Host smart-39e50bb0-b89a-4f9a-95e2-15cd704e2eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32786
41821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3278641821
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1584474371
Short name T451
Test name
Test status
Simulation time 231160274 ps
CPU time 0.88 seconds
Started Jun 29 06:38:30 PM PDT 24
Finished Jun 29 06:38:31 PM PDT 24
Peak memory 206212 kb
Host smart-fbe1f9bf-c42f-425c-9177-2f4eb7ecd5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
74371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1584474371
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3075802519
Short name T1496
Test name
Test status
Simulation time 181149211 ps
CPU time 0.9 seconds
Started Jun 29 06:38:24 PM PDT 24
Finished Jun 29 06:38:25 PM PDT 24
Peak memory 206200 kb
Host smart-3e8561b7-c0ba-4cab-8fad-31539be21e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30758
02519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3075802519
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3489285121
Short name T1932
Test name
Test status
Simulation time 146475469 ps
CPU time 0.75 seconds
Started Jun 29 06:38:20 PM PDT 24
Finished Jun 29 06:38:23 PM PDT 24
Peak memory 206200 kb
Host smart-8f50f8d7-fbfa-4a87-815b-f1d81430dc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34892
85121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3489285121
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.172741839
Short name T2301
Test name
Test status
Simulation time 158814085 ps
CPU time 0.82 seconds
Started Jun 29 06:38:19 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206192 kb
Host smart-efb1efa5-d14f-4b1f-b240-d65728014fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17274
1839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.172741839
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2530229707
Short name T360
Test name
Test status
Simulation time 152062416 ps
CPU time 0.79 seconds
Started Jun 29 06:38:17 PM PDT 24
Finished Jun 29 06:38:20 PM PDT 24
Peak memory 206196 kb
Host smart-18ac2cd9-1ea8-44a5-8fa1-beac3c1e138e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25302
29707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2530229707
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1710204590
Short name T1662
Test name
Test status
Simulation time 253014228 ps
CPU time 1.01 seconds
Started Jun 29 06:38:18 PM PDT 24
Finished Jun 29 06:38:21 PM PDT 24
Peak memory 206216 kb
Host smart-ca6b0217-0e1a-4a8f-b4d0-93f8a65f3d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17102
04590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1710204590
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1449441394
Short name T2618
Test name
Test status
Simulation time 4704350573 ps
CPU time 126.55 seconds
Started Jun 29 06:38:24 PM PDT 24
Finished Jun 29 06:40:31 PM PDT 24
Peak memory 206444 kb
Host smart-6bd15a30-c573-4146-97af-0d815128df5f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1449441394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1449441394
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1548376525
Short name T1602
Test name
Test status
Simulation time 199985545 ps
CPU time 0.92 seconds
Started Jun 29 06:38:20 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 206224 kb
Host smart-6bed17d0-3814-4875-8dfd-8f504fbc4c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15483
76525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1548376525
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1692779307
Short name T1139
Test name
Test status
Simulation time 192073964 ps
CPU time 0.85 seconds
Started Jun 29 06:38:16 PM PDT 24
Finished Jun 29 06:38:19 PM PDT 24
Peak memory 206164 kb
Host smart-8565a6ec-1b84-4691-ace9-01bc5047e351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16927
79307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1692779307
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3924538122
Short name T341
Test name
Test status
Simulation time 3775224293 ps
CPU time 99.8 seconds
Started Jun 29 06:38:23 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206472 kb
Host smart-c87fd676-627f-42a3-a5ea-2aaf3343d506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39245
38122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3924538122
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.964231772
Short name T333
Test name
Test status
Simulation time 44643310 ps
CPU time 0.69 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206212 kb
Host smart-c2126948-b8c1-4f53-812c-5997706e3ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=964231772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.964231772
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2318338009
Short name T55
Test name
Test status
Simulation time 4082116900 ps
CPU time 4.79 seconds
Started Jun 29 06:38:32 PM PDT 24
Finished Jun 29 06:38:37 PM PDT 24
Peak memory 206256 kb
Host smart-19d1eb54-3653-4ae0-a71c-793d11cab233
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2318338009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2318338009
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3184569801
Short name T758
Test name
Test status
Simulation time 13336222932 ps
CPU time 12.7 seconds
Started Jun 29 06:38:46 PM PDT 24
Finished Jun 29 06:38:59 PM PDT 24
Peak memory 206292 kb
Host smart-c56306ce-5fb1-4060-b730-cb223e6fb9e8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3184569801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3184569801
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.4219193664
Short name T2388
Test name
Test status
Simulation time 23512851470 ps
CPU time 22.55 seconds
Started Jun 29 06:38:30 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206400 kb
Host smart-9f3de375-6f14-4c6a-b11f-dd1ba2c9f851
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4219193664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.4219193664
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.30475559
Short name T1188
Test name
Test status
Simulation time 162648355 ps
CPU time 0.83 seconds
Started Jun 29 06:38:42 PM PDT 24
Finished Jun 29 06:38:43 PM PDT 24
Peak memory 206212 kb
Host smart-b593fd0b-855e-4f56-a7f7-d2f706274a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30475
559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.30475559
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.4050412358
Short name T450
Test name
Test status
Simulation time 143688746 ps
CPU time 0.78 seconds
Started Jun 29 06:38:31 PM PDT 24
Finished Jun 29 06:38:32 PM PDT 24
Peak memory 206196 kb
Host smart-6a8783f3-381e-4f46-8036-812bfd600a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40504
12358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.4050412358
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.915940594
Short name T1638
Test name
Test status
Simulation time 281639896 ps
CPU time 1.04 seconds
Started Jun 29 06:38:25 PM PDT 24
Finished Jun 29 06:38:27 PM PDT 24
Peak memory 206200 kb
Host smart-e43764b0-9a56-4eb8-93f8-429e7f93e12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91594
0594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.915940594
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3362002832
Short name T2368
Test name
Test status
Simulation time 431482015 ps
CPU time 1.25 seconds
Started Jun 29 06:38:26 PM PDT 24
Finished Jun 29 06:38:28 PM PDT 24
Peak memory 206164 kb
Host smart-e9f2666f-2177-4c42-863a-c58bdeedfa46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33620
02832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3362002832
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.4007377336
Short name T100
Test name
Test status
Simulation time 18332014684 ps
CPU time 31.96 seconds
Started Jun 29 06:38:40 PM PDT 24
Finished Jun 29 06:39:13 PM PDT 24
Peak memory 206384 kb
Host smart-2f8eb4a2-222c-4fc6-b29d-aaba7a0c5c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40073
77336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.4007377336
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2452727572
Short name T760
Test name
Test status
Simulation time 449766045 ps
CPU time 1.33 seconds
Started Jun 29 06:38:43 PM PDT 24
Finished Jun 29 06:38:45 PM PDT 24
Peak memory 206200 kb
Host smart-b7639c4f-1723-479c-a5c8-91f96259f682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24527
27572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2452727572
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1998958676
Short name T1299
Test name
Test status
Simulation time 193359317 ps
CPU time 0.8 seconds
Started Jun 29 06:38:42 PM PDT 24
Finished Jun 29 06:38:43 PM PDT 24
Peak memory 206192 kb
Host smart-b56c5f7e-a43b-462f-96ad-a646f384f9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19989
58676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1998958676
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.2829687937
Short name T919
Test name
Test status
Simulation time 57188882 ps
CPU time 0.7 seconds
Started Jun 29 06:38:40 PM PDT 24
Finished Jun 29 06:38:42 PM PDT 24
Peak memory 206192 kb
Host smart-8cafba78-0d12-492a-82e7-ef072b6092fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28296
87937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2829687937
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.875067114
Short name T1804
Test name
Test status
Simulation time 886624404 ps
CPU time 2.34 seconds
Started Jun 29 06:38:25 PM PDT 24
Finished Jun 29 06:38:28 PM PDT 24
Peak memory 206300 kb
Host smart-d03b7f87-c6f2-41ad-b54d-1b366e2fa57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87506
7114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.875067114
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1832574219
Short name T1197
Test name
Test status
Simulation time 285864440 ps
CPU time 1.61 seconds
Started Jun 29 06:38:36 PM PDT 24
Finished Jun 29 06:38:39 PM PDT 24
Peak memory 206264 kb
Host smart-5a6cf490-bc0a-43bd-97b7-213c26e54d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18325
74219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1832574219
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2262058760
Short name T2389
Test name
Test status
Simulation time 167860945 ps
CPU time 0.84 seconds
Started Jun 29 06:38:40 PM PDT 24
Finished Jun 29 06:38:42 PM PDT 24
Peak memory 206200 kb
Host smart-bb102a38-b605-461f-8537-84d8702d0e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620
58760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2262058760
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.804396575
Short name T1545
Test name
Test status
Simulation time 153852776 ps
CPU time 0.77 seconds
Started Jun 29 06:38:36 PM PDT 24
Finished Jun 29 06:38:37 PM PDT 24
Peak memory 206212 kb
Host smart-2112d4e2-bbc4-4158-844f-ca4e022449ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80439
6575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.804396575
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.871085424
Short name T2582
Test name
Test status
Simulation time 209087770 ps
CPU time 0.89 seconds
Started Jun 29 06:38:27 PM PDT 24
Finished Jun 29 06:38:28 PM PDT 24
Peak memory 206124 kb
Host smart-2e6a1f38-c895-44ed-b315-e06f0876272b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87108
5424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.871085424
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.124170892
Short name T2380
Test name
Test status
Simulation time 203811624 ps
CPU time 0.92 seconds
Started Jun 29 06:38:39 PM PDT 24
Finished Jun 29 06:38:41 PM PDT 24
Peak memory 206196 kb
Host smart-f95fefdd-336f-4891-9159-f8ee9fd6ce06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12417
0892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.124170892
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.2663933702
Short name T1297
Test name
Test status
Simulation time 23290383565 ps
CPU time 22.42 seconds
Started Jun 29 06:38:24 PM PDT 24
Finished Jun 29 06:38:47 PM PDT 24
Peak memory 206316 kb
Host smart-a78f5194-25e9-40b0-a66b-a0a3571ecfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26639
33702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.2663933702
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3209072151
Short name T606
Test name
Test status
Simulation time 3347949038 ps
CPU time 3.56 seconds
Started Jun 29 06:38:36 PM PDT 24
Finished Jun 29 06:38:40 PM PDT 24
Peak memory 206256 kb
Host smart-a7ab3e52-5029-423c-b80d-704f1089a5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32090
72151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3209072151
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.3053058694
Short name T1664
Test name
Test status
Simulation time 8654392120 ps
CPU time 61.66 seconds
Started Jun 29 06:38:28 PM PDT 24
Finished Jun 29 06:39:30 PM PDT 24
Peak memory 206484 kb
Host smart-7d8560da-912f-4888-a0d3-088a31f8cd1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530
58694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.3053058694
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.930309479
Short name T1956
Test name
Test status
Simulation time 7042664987 ps
CPU time 201.55 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:42:13 PM PDT 24
Peak memory 206460 kb
Host smart-7afb71bc-81b1-48b4-9296-09b0535f2244
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=930309479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.930309479
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2056892875
Short name T1489
Test name
Test status
Simulation time 242233486 ps
CPU time 1 seconds
Started Jun 29 06:38:31 PM PDT 24
Finished Jun 29 06:38:32 PM PDT 24
Peak memory 206180 kb
Host smart-7e048389-3b6f-4749-8225-3518b6cf020b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2056892875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2056892875
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2807584840
Short name T2123
Test name
Test status
Simulation time 237104347 ps
CPU time 0.9 seconds
Started Jun 29 06:38:32 PM PDT 24
Finished Jun 29 06:38:34 PM PDT 24
Peak memory 206216 kb
Host smart-ab8d900e-8e97-43ba-9370-0cc9f6294105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28075
84840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2807584840
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1673885758
Short name T2289
Test name
Test status
Simulation time 6988037587 ps
CPU time 48.42 seconds
Started Jun 29 06:38:26 PM PDT 24
Finished Jun 29 06:39:15 PM PDT 24
Peak memory 206456 kb
Host smart-5e6b151c-5c2f-4a21-ae0d-5701937264f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16738
85758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1673885758
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1828776785
Short name T2623
Test name
Test status
Simulation time 4232664463 ps
CPU time 39.53 seconds
Started Jun 29 06:38:38 PM PDT 24
Finished Jun 29 06:39:18 PM PDT 24
Peak memory 206416 kb
Host smart-33e87d3c-fdbb-4c6d-9433-790e67db8026
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1828776785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1828776785
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3633865765
Short name T20
Test name
Test status
Simulation time 211016114 ps
CPU time 0.84 seconds
Started Jun 29 06:38:25 PM PDT 24
Finished Jun 29 06:38:26 PM PDT 24
Peak memory 206216 kb
Host smart-37ea0714-f7d2-4395-a63d-b68b14732461
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3633865765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3633865765
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2951215998
Short name T2326
Test name
Test status
Simulation time 158444468 ps
CPU time 0.79 seconds
Started Jun 29 06:38:26 PM PDT 24
Finished Jun 29 06:38:27 PM PDT 24
Peak memory 206192 kb
Host smart-0239a174-e090-4a38-a1b9-ddb518d342a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29512
15998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2951215998
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.859440201
Short name T1761
Test name
Test status
Simulation time 194034561 ps
CPU time 0.84 seconds
Started Jun 29 06:38:40 PM PDT 24
Finished Jun 29 06:38:41 PM PDT 24
Peak memory 206216 kb
Host smart-b9b44eb1-4959-4c8d-8523-26bbfb0baf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85944
0201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.859440201
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3513769264
Short name T666
Test name
Test status
Simulation time 202244615 ps
CPU time 0.88 seconds
Started Jun 29 06:38:27 PM PDT 24
Finished Jun 29 06:38:28 PM PDT 24
Peak memory 206204 kb
Host smart-00b30e66-55e4-42e5-a62d-0dc27fbb1174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35137
69264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3513769264
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2115954555
Short name T2579
Test name
Test status
Simulation time 218500625 ps
CPU time 0.87 seconds
Started Jun 29 06:38:42 PM PDT 24
Finished Jun 29 06:38:43 PM PDT 24
Peak memory 206196 kb
Host smart-ee0ed172-2c2f-4f03-ac8c-d0104db0b8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21159
54555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2115954555
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.364790488
Short name T1742
Test name
Test status
Simulation time 179497442 ps
CPU time 0.82 seconds
Started Jun 29 06:38:41 PM PDT 24
Finished Jun 29 06:38:42 PM PDT 24
Peak memory 206224 kb
Host smart-bc7e83a6-0f0d-4932-9488-73b8ae3e7e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36479
0488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.364790488
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1787447602
Short name T2154
Test name
Test status
Simulation time 152347738 ps
CPU time 0.81 seconds
Started Jun 29 06:38:27 PM PDT 24
Finished Jun 29 06:38:28 PM PDT 24
Peak memory 206200 kb
Host smart-54be7686-72ce-4a0d-a904-f965bbe53b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17874
47602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1787447602
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3955388532
Short name T2296
Test name
Test status
Simulation time 223633749 ps
CPU time 0.95 seconds
Started Jun 29 06:38:45 PM PDT 24
Finished Jun 29 06:38:47 PM PDT 24
Peak memory 206188 kb
Host smart-4ae0fdd1-c768-45f9-ab44-f2cbdae7eb5d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3955388532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3955388532
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2525308300
Short name T2112
Test name
Test status
Simulation time 163833540 ps
CPU time 0.82 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:48 PM PDT 24
Peak memory 206212 kb
Host smart-2876bd98-1220-433b-9cce-c58b2349fd52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25253
08300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2525308300
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2932435108
Short name T1307
Test name
Test status
Simulation time 27888864 ps
CPU time 0.71 seconds
Started Jun 29 06:38:43 PM PDT 24
Finished Jun 29 06:38:44 PM PDT 24
Peak memory 206216 kb
Host smart-d9795233-a3fd-4967-a611-6e9c763befb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29324
35108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2932435108
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1814017305
Short name T95
Test name
Test status
Simulation time 15542038751 ps
CPU time 35.94 seconds
Started Jun 29 06:38:26 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206348 kb
Host smart-ec855217-0acc-40a0-bb36-d368629a460b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18140
17305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1814017305
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1040622294
Short name T1201
Test name
Test status
Simulation time 212823790 ps
CPU time 0.9 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:51 PM PDT 24
Peak memory 206140 kb
Host smart-6895e944-1c38-4842-8601-794ade88c1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10406
22294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1040622294
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3586319468
Short name T1301
Test name
Test status
Simulation time 195762908 ps
CPU time 0.92 seconds
Started Jun 29 06:38:44 PM PDT 24
Finished Jun 29 06:38:45 PM PDT 24
Peak memory 206212 kb
Host smart-bba3e208-6b90-49c2-bf3e-ff3d44f956d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35863
19468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3586319468
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.688530879
Short name T2448
Test name
Test status
Simulation time 225369560 ps
CPU time 0.97 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:48 PM PDT 24
Peak memory 206192 kb
Host smart-d34a2108-2ec8-487a-9612-d6063836d5b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68853
0879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.688530879
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2899882922
Short name T1421
Test name
Test status
Simulation time 154455853 ps
CPU time 0.84 seconds
Started Jun 29 06:38:39 PM PDT 24
Finished Jun 29 06:38:40 PM PDT 24
Peak memory 206200 kb
Host smart-041ec010-7e30-41f0-9cd8-776fe1ce58d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28998
82922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2899882922
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3422271258
Short name T589
Test name
Test status
Simulation time 135622095 ps
CPU time 0.78 seconds
Started Jun 29 06:38:45 PM PDT 24
Finished Jun 29 06:38:46 PM PDT 24
Peak memory 206200 kb
Host smart-a750ed3d-1671-4c96-8ce5-97c6d051622b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34222
71258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3422271258
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3623708423
Short name T2613
Test name
Test status
Simulation time 154046380 ps
CPU time 0.78 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:49 PM PDT 24
Peak memory 206192 kb
Host smart-96edd486-3a05-4e3c-90de-7936299f0354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237
08423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3623708423
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3054059603
Short name T2586
Test name
Test status
Simulation time 209877333 ps
CPU time 0.88 seconds
Started Jun 29 06:38:45 PM PDT 24
Finished Jun 29 06:38:46 PM PDT 24
Peak memory 206196 kb
Host smart-d0403e73-d514-45c9-8950-1e7a1959bfd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30540
59603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3054059603
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.875606631
Short name T1161
Test name
Test status
Simulation time 243080498 ps
CPU time 0.96 seconds
Started Jun 29 06:38:45 PM PDT 24
Finished Jun 29 06:38:46 PM PDT 24
Peak memory 206216 kb
Host smart-f521549f-6ead-4fac-b1df-f723e203fa1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87560
6631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.875606631
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.710585308
Short name T1911
Test name
Test status
Simulation time 4715866512 ps
CPU time 132.73 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:41:03 PM PDT 24
Peak memory 206504 kb
Host smart-4cabc4d9-1cdc-471f-bcde-04d20d3a823e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=710585308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.710585308
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.370408074
Short name T1154
Test name
Test status
Simulation time 155156875 ps
CPU time 0.82 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206220 kb
Host smart-b1c1b3eb-6d55-4a95-9991-bf3b2a039745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37040
8074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.370408074
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2938064467
Short name T2279
Test name
Test status
Simulation time 181723652 ps
CPU time 0.82 seconds
Started Jun 29 06:38:41 PM PDT 24
Finished Jun 29 06:38:42 PM PDT 24
Peak memory 206196 kb
Host smart-e5aedb1a-98f2-4f47-b383-9d287f469ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29380
64467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2938064467
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1817634882
Short name T2392
Test name
Test status
Simulation time 5967167742 ps
CPU time 43.49 seconds
Started Jun 29 06:38:46 PM PDT 24
Finished Jun 29 06:39:30 PM PDT 24
Peak memory 206440 kb
Host smart-27f59c23-676b-49ad-b780-1aeb9135a793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18176
34882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1817634882
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.1387253385
Short name T2492
Test name
Test status
Simulation time 50288294 ps
CPU time 0.69 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:01 PM PDT 24
Peak memory 206212 kb
Host smart-69054b6d-8626-4d8f-920e-812c0c6a1ea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1387253385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.1387253385
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2955326260
Short name T1999
Test name
Test status
Simulation time 3679326248 ps
CPU time 4.46 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:52 PM PDT 24
Peak memory 206276 kb
Host smart-58981a3d-1dca-43e5-b11d-1048032e443f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2955326260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.2955326260
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3848907581
Short name T1618
Test name
Test status
Simulation time 13495319351 ps
CPU time 12.86 seconds
Started Jun 29 06:38:48 PM PDT 24
Finished Jun 29 06:39:01 PM PDT 24
Peak memory 206448 kb
Host smart-f7e2f417-f275-4bf2-b616-ad82ac781d2d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3848907581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3848907581
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.1308449996
Short name T1193
Test name
Test status
Simulation time 23466870547 ps
CPU time 23.77 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:39:11 PM PDT 24
Peak memory 206328 kb
Host smart-1aafb9ad-fd3c-49dc-afac-b88dcb3810ad
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1308449996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.1308449996
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3153739753
Short name T1983
Test name
Test status
Simulation time 189944018 ps
CPU time 0.89 seconds
Started Jun 29 06:38:46 PM PDT 24
Finished Jun 29 06:38:48 PM PDT 24
Peak memory 206196 kb
Host smart-5a1f299c-ed90-4588-8310-9842ac99aa0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31537
39753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3153739753
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.438764984
Short name T815
Test name
Test status
Simulation time 144428499 ps
CPU time 0.84 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:49 PM PDT 24
Peak memory 206204 kb
Host smart-65c88d18-8a90-4f81-9892-2af7a0d61508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43876
4984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.438764984
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3426308225
Short name T1230
Test name
Test status
Simulation time 249972543 ps
CPU time 0.95 seconds
Started Jun 29 06:38:42 PM PDT 24
Finished Jun 29 06:38:43 PM PDT 24
Peak memory 206196 kb
Host smart-710b1159-0fa3-4f7d-9cda-a943c72dcde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34263
08225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3426308225
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.4153880506
Short name T186
Test name
Test status
Simulation time 1054548550 ps
CPU time 2.59 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:52 PM PDT 24
Peak memory 206300 kb
Host smart-aadf25f3-5842-43c0-a59e-769275d0539b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41538
80506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.4153880506
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3930833991
Short name T714
Test name
Test status
Simulation time 7466755803 ps
CPU time 15.69 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206504 kb
Host smart-36f20f97-1d33-4a16-a422-72bcab859241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39308
33991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3930833991
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.3305530044
Short name T1357
Test name
Test status
Simulation time 420255907 ps
CPU time 1.28 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:49 PM PDT 24
Peak memory 206200 kb
Host smart-badfeb67-c6f6-4b11-ab13-d9e672f1331f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33055
30044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3305530044
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2186394354
Short name T1819
Test name
Test status
Simulation time 146100125 ps
CPU time 0.76 seconds
Started Jun 29 06:38:43 PM PDT 24
Finished Jun 29 06:38:44 PM PDT 24
Peak memory 206192 kb
Host smart-f690bc74-8feb-48e1-a91c-a40fff2d179c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21863
94354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2186394354
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3828624554
Short name T1829
Test name
Test status
Simulation time 34129709 ps
CPU time 0.65 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:51 PM PDT 24
Peak memory 206196 kb
Host smart-a95baab8-68cd-49cc-9089-67dfde1bedbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38286
24554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3828624554
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.1151393386
Short name T1796
Test name
Test status
Simulation time 923271322 ps
CPU time 2.08 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206312 kb
Host smart-c85ad760-5528-42e2-a971-474929524106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11513
93386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1151393386
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1792803129
Short name T2048
Test name
Test status
Simulation time 302618273 ps
CPU time 2.03 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:52 PM PDT 24
Peak memory 206288 kb
Host smart-cc2a555f-fce1-4d1a-8468-1a3d76438804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17928
03129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1792803129
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.1597799223
Short name T907
Test name
Test status
Simulation time 191033582 ps
CPU time 0.84 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206148 kb
Host smart-3a2b7d53-ba4c-4df7-a4e4-f412f6ad6426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15977
99223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1597799223
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.4255445224
Short name T827
Test name
Test status
Simulation time 156598781 ps
CPU time 0.76 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:48 PM PDT 24
Peak memory 206216 kb
Host smart-cfffdceb-6ae5-47d9-99e9-70ede8a2a76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42554
45224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.4255445224
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.337327929
Short name T586
Test name
Test status
Simulation time 249817685 ps
CPU time 0.95 seconds
Started Jun 29 06:38:48 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206188 kb
Host smart-2118b6c6-7745-40cc-900e-39e681a5afdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33732
7929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.337327929
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1645917169
Short name T761
Test name
Test status
Simulation time 193089484 ps
CPU time 0.91 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 206196 kb
Host smart-4d374688-50a8-4572-b98d-1067da3e1225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16459
17169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1645917169
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.3919900810
Short name T1770
Test name
Test status
Simulation time 23298687460 ps
CPU time 24.6 seconds
Started Jun 29 06:38:51 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206316 kb
Host smart-93628d2d-4101-404b-af68-fd6072cbc874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39199
00810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.3919900810
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2607357181
Short name T886
Test name
Test status
Simulation time 3333057578 ps
CPU time 4.04 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206204 kb
Host smart-c072feae-4869-49ba-84e7-c737bce0bbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26073
57181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2607357181
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1632841991
Short name T2560
Test name
Test status
Simulation time 8986080418 ps
CPU time 61.09 seconds
Started Jun 29 06:38:57 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206416 kb
Host smart-037b9473-f813-4111-814d-5748f15972e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16328
41991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1632841991
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3929095044
Short name T424
Test name
Test status
Simulation time 3956162820 ps
CPU time 38.72 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:39:29 PM PDT 24
Peak memory 206452 kb
Host smart-2ff72e47-0b5e-48d4-a617-a415d2eaffc6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3929095044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3929095044
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.3125736257
Short name T670
Test name
Test status
Simulation time 244281405 ps
CPU time 0.92 seconds
Started Jun 29 06:38:51 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206184 kb
Host smart-c3688c60-7172-4e62-901d-67536edf8265
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3125736257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.3125736257
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.950711269
Short name T2233
Test name
Test status
Simulation time 210150792 ps
CPU time 0.89 seconds
Started Jun 29 06:38:56 PM PDT 24
Finished Jun 29 06:38:57 PM PDT 24
Peak memory 206216 kb
Host smart-9d369d45-3862-4c67-b095-6310d1a11886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95071
1269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.950711269
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.625657048
Short name T1563
Test name
Test status
Simulation time 6088805273 ps
CPU time 170.61 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:41:51 PM PDT 24
Peak memory 206464 kb
Host smart-f1a7d5e6-1c20-4734-a66b-1dcabfe0ebee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62565
7048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.625657048
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1409932561
Short name T1852
Test name
Test status
Simulation time 3723361489 ps
CPU time 33.37 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:39:23 PM PDT 24
Peak memory 206376 kb
Host smart-4db7a3f6-b449-432f-a4e4-2c42197857d7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1409932561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1409932561
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.91477920
Short name T2212
Test name
Test status
Simulation time 167431437 ps
CPU time 0.83 seconds
Started Jun 29 06:38:48 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206200 kb
Host smart-51680441-9912-4a77-9c89-ca03dc31daa5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=91477920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.91477920
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.394125419
Short name T720
Test name
Test status
Simulation time 144804875 ps
CPU time 0.79 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206044 kb
Host smart-7c212ded-a452-4621-94b5-ea2f26bfb047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39412
5419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.394125419
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3963014488
Short name T134
Test name
Test status
Simulation time 246997502 ps
CPU time 0.87 seconds
Started Jun 29 06:38:46 PM PDT 24
Finished Jun 29 06:38:47 PM PDT 24
Peak memory 206208 kb
Host smart-e160fefa-35a5-48ad-ade2-13f0216a799e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39630
14488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3963014488
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2415019709
Short name T2375
Test name
Test status
Simulation time 172154369 ps
CPU time 0.83 seconds
Started Jun 29 06:38:45 PM PDT 24
Finished Jun 29 06:38:46 PM PDT 24
Peak memory 206204 kb
Host smart-f41b0e67-253a-4537-baff-1a505d8a5d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24150
19709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2415019709
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.467906258
Short name T668
Test name
Test status
Simulation time 217373051 ps
CPU time 0.9 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206216 kb
Host smart-fffb74e4-cd17-4f13-a61f-80b5df956f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46790
6258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.467906258
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.4072242379
Short name T1186
Test name
Test status
Simulation time 203278255 ps
CPU time 0.89 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:48 PM PDT 24
Peak memory 206196 kb
Host smart-750445f9-de65-4851-8da5-5364af2c4c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40722
42379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.4072242379
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.4151600007
Short name T1558
Test name
Test status
Simulation time 228711149 ps
CPU time 0.86 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:38:52 PM PDT 24
Peak memory 206200 kb
Host smart-d2ea63e8-283a-4349-ad8a-153c2881b279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41516
00007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.4151600007
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.3341103458
Short name T1779
Test name
Test status
Simulation time 227943919 ps
CPU time 0.96 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206224 kb
Host smart-cfc48711-327c-42fc-b8a3-0b66d3272d46
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3341103458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.3341103458
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1643048387
Short name T1836
Test name
Test status
Simulation time 159574495 ps
CPU time 0.79 seconds
Started Jun 29 06:38:51 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206184 kb
Host smart-bb906727-cb10-465e-b549-961f7464f382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16430
48387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1643048387
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3698934716
Short name T2576
Test name
Test status
Simulation time 88053459 ps
CPU time 0.76 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:38:52 PM PDT 24
Peak memory 206124 kb
Host smart-645f92b5-df54-490a-8cd4-ea3d7f257da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36989
34716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3698934716
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2425758661
Short name T256
Test name
Test status
Simulation time 9086025895 ps
CPU time 21.22 seconds
Started Jun 29 06:39:02 PM PDT 24
Finished Jun 29 06:39:24 PM PDT 24
Peak memory 206508 kb
Host smart-725fd41f-59e6-4713-93fb-4157b4a0b95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24257
58661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2425758661
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.184227954
Short name T1792
Test name
Test status
Simulation time 213929216 ps
CPU time 0.89 seconds
Started Jun 29 06:38:44 PM PDT 24
Finished Jun 29 06:38:45 PM PDT 24
Peak memory 206156 kb
Host smart-fd23d79c-b5fe-477d-9353-e843e9c06522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422
7954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.184227954
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2074290054
Short name T2348
Test name
Test status
Simulation time 221742880 ps
CPU time 0.88 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206212 kb
Host smart-5af6119f-52a5-4b0b-9575-506a64cba3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20742
90054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2074290054
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.3299415875
Short name T1615
Test name
Test status
Simulation time 176293159 ps
CPU time 0.84 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:38:52 PM PDT 24
Peak memory 206212 kb
Host smart-f8e0d36e-9cd8-4ec4-b678-487414897c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32994
15875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.3299415875
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.392858019
Short name T1010
Test name
Test status
Simulation time 185378938 ps
CPU time 0.91 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:39:01 PM PDT 24
Peak memory 206176 kb
Host smart-135c18bf-f85d-464e-8ef6-ba21ada5291c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39285
8019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.392858019
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3902858640
Short name T594
Test name
Test status
Simulation time 142744069 ps
CPU time 0.75 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:51 PM PDT 24
Peak memory 206196 kb
Host smart-3e19eb34-3442-4d57-8ed5-2a91a9414366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39028
58640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3902858640
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.855196188
Short name T1225
Test name
Test status
Simulation time 147200148 ps
CPU time 0.87 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:51 PM PDT 24
Peak memory 206196 kb
Host smart-821a826a-665e-41b9-8665-87cd3be385c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85519
6188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.855196188
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.70240965
Short name T1060
Test name
Test status
Simulation time 146696219 ps
CPU time 0.78 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206200 kb
Host smart-bc578e53-7d5e-47e0-aa52-79eb71ba52b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70240
965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.70240965
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.820153928
Short name T1716
Test name
Test status
Simulation time 191658044 ps
CPU time 0.87 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 206216 kb
Host smart-98fcac1f-f293-480f-836e-c60435978e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82015
3928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.820153928
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.3025421348
Short name T2069
Test name
Test status
Simulation time 6063486999 ps
CPU time 170.52 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:41:50 PM PDT 24
Peak memory 206440 kb
Host smart-520982dc-c4bd-4fd2-8f83-7c5b17c66b50
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3025421348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.3025421348
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2618134090
Short name T2254
Test name
Test status
Simulation time 151954973 ps
CPU time 0.81 seconds
Started Jun 29 06:38:48 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206224 kb
Host smart-1fc3ec1c-6827-4ad6-a694-70ff61d95834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26181
34090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2618134090
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.2898109096
Short name T577
Test name
Test status
Simulation time 151350582 ps
CPU time 0.77 seconds
Started Jun 29 06:38:51 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206140 kb
Host smart-1c0246e2-0ad0-48bc-93dc-b4ef0d2a00fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28981
09096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2898109096
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2374719813
Short name T1393
Test name
Test status
Simulation time 6113539900 ps
CPU time 167.07 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:41:38 PM PDT 24
Peak memory 206472 kb
Host smart-1bb2337d-60ea-488f-99c7-80a37fef1d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23747
19813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2374719813
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.200282541
Short name T1755
Test name
Test status
Simulation time 47907456 ps
CPU time 0.67 seconds
Started Jun 29 06:38:53 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 206212 kb
Host smart-fadf9dab-4db7-4691-ba52-cbd25a560434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=200282541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.200282541
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2369392861
Short name T1585
Test name
Test status
Simulation time 3626320750 ps
CPU time 4.45 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206352 kb
Host smart-6e45c5b6-9142-4199-b2d1-2ea2648b2608
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2369392861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.2369392861
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.3105355633
Short name T2490
Test name
Test status
Simulation time 13402834353 ps
CPU time 12.77 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 206412 kb
Host smart-9c5b260a-dc3d-44e0-ac14-bfe96c473bf2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3105355633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.3105355633
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.2866458357
Short name T822
Test name
Test status
Simulation time 23392382527 ps
CPU time 23.52 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:39:17 PM PDT 24
Peak memory 206288 kb
Host smart-d948590f-ce95-46bd-b2b6-fc3e43ef8d12
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2866458357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.2866458357
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3543592757
Short name T759
Test name
Test status
Simulation time 157244810 ps
CPU time 0.83 seconds
Started Jun 29 06:38:44 PM PDT 24
Finished Jun 29 06:38:45 PM PDT 24
Peak memory 206208 kb
Host smart-c207aecf-ba0b-4ede-a780-880e6ec9178f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35435
92757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3543592757
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.619661895
Short name T2298
Test name
Test status
Simulation time 161603616 ps
CPU time 0.82 seconds
Started Jun 29 06:38:53 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 206224 kb
Host smart-64e2432b-c635-4e25-9cda-2923121a4a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61966
1895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.619661895
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2101810534
Short name T2349
Test name
Test status
Simulation time 363441285 ps
CPU time 1.17 seconds
Started Jun 29 06:38:53 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 206196 kb
Host smart-170ed4a4-f271-43f8-8013-de66d78867a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21018
10534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2101810534
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.139814817
Short name T1208
Test name
Test status
Simulation time 387124075 ps
CPU time 1.21 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:38:52 PM PDT 24
Peak memory 206192 kb
Host smart-dba96b29-3db1-4d1c-98e9-55132af662d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13981
4817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.139814817
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3945245536
Short name T696
Test name
Test status
Simulation time 16245827526 ps
CPU time 30.59 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:30 PM PDT 24
Peak memory 206400 kb
Host smart-50f89d1b-dcca-4b6e-82c7-13a4c27a97f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39452
45536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3945245536
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.522568128
Short name T404
Test name
Test status
Simulation time 472409328 ps
CPU time 1.4 seconds
Started Jun 29 06:38:48 PM PDT 24
Finished Jun 29 06:38:50 PM PDT 24
Peak memory 206168 kb
Host smart-c657115a-7fe4-4862-a4b9-1d32c21fc8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52256
8128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.522568128
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.365715135
Short name T47
Test name
Test status
Simulation time 179698517 ps
CPU time 0.78 seconds
Started Jun 29 06:38:53 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 206200 kb
Host smart-e01205bf-797d-4d90-9828-82ecd7e8104b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36571
5135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.365715135
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.153449475
Short name T1682
Test name
Test status
Simulation time 66025258 ps
CPU time 0.73 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:48 PM PDT 24
Peak memory 206204 kb
Host smart-7f8fabd2-4660-492b-aa66-56f0e0661060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15344
9475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.153449475
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3076509698
Short name T2439
Test name
Test status
Simulation time 893828763 ps
CPU time 2.25 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206324 kb
Host smart-34ed9201-46fb-4017-8019-9c7ba71618a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30765
09698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3076509698
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1266039338
Short name T1604
Test name
Test status
Simulation time 277302860 ps
CPU time 1.96 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206320 kb
Host smart-0e5c4ddc-88f1-4f3c-b791-b02ab9b59281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12660
39338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1266039338
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2537533442
Short name T1011
Test name
Test status
Simulation time 286876191 ps
CPU time 0.95 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 206204 kb
Host smart-110cb1c0-50aa-48f9-8f7c-3947babde75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25375
33442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2537533442
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2337497313
Short name T1839
Test name
Test status
Simulation time 183563883 ps
CPU time 0.79 seconds
Started Jun 29 06:38:47 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206216 kb
Host smart-34eec8eb-837c-4b72-be74-6204e4e0dcef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23374
97313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2337497313
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2094630027
Short name T2110
Test name
Test status
Simulation time 282536007 ps
CPU time 1.12 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206368 kb
Host smart-0986b0d2-3f4f-4ebc-8bf8-c18a32091119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20946
30027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2094630027
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.4007734787
Short name T2161
Test name
Test status
Simulation time 6873071262 ps
CPU time 65.11 seconds
Started Jun 29 06:38:42 PM PDT 24
Finished Jun 29 06:39:47 PM PDT 24
Peak memory 206416 kb
Host smart-5ac4ac32-8267-4df1-98f0-54f6a76385a1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4007734787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.4007734787
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.897160873
Short name T110
Test name
Test status
Simulation time 225377607 ps
CPU time 0.89 seconds
Started Jun 29 06:38:51 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206196 kb
Host smart-b6c22cfa-2ece-4254-bbe4-bbca24af4341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89716
0873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.897160873
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1529419684
Short name T2013
Test name
Test status
Simulation time 23338144401 ps
CPU time 27.55 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:26 PM PDT 24
Peak memory 206316 kb
Host smart-5af2b4f4-3cc7-4417-ba99-4d9db35f9588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15294
19684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1529419684
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.306935872
Short name T3
Test name
Test status
Simulation time 3254662744 ps
CPU time 3.72 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 206260 kb
Host smart-21c48931-8740-4cfe-a4a6-e417647f3303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30693
5872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.306935872
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2233680515
Short name T846
Test name
Test status
Simulation time 6378713819 ps
CPU time 44.05 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:39:34 PM PDT 24
Peak memory 206428 kb
Host smart-1bb5d5fe-4f8c-4731-aa85-f6a7ebdf5099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22336
80515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2233680515
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2286479848
Short name T2237
Test name
Test status
Simulation time 5969907152 ps
CPU time 159.53 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:41:33 PM PDT 24
Peak memory 206460 kb
Host smart-5ac7026e-cb9c-4b84-ae7c-5909f0bc873d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2286479848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2286479848
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2162554590
Short name T1309
Test name
Test status
Simulation time 246503867 ps
CPU time 0.92 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:39:01 PM PDT 24
Peak memory 206220 kb
Host smart-041eb567-2c4a-4b1a-a69e-8348ada984ff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2162554590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2162554590
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.741674910
Short name T951
Test name
Test status
Simulation time 229878384 ps
CPU time 0.89 seconds
Started Jun 29 06:38:51 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206208 kb
Host smart-f91ba337-4eed-4f12-85f8-1fe03ec85409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74167
4910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.741674910
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3761017669
Short name T2287
Test name
Test status
Simulation time 3467682971 ps
CPU time 95.9 seconds
Started Jun 29 06:38:49 PM PDT 24
Finished Jun 29 06:40:25 PM PDT 24
Peak memory 206636 kb
Host smart-7640b02e-883c-4467-899a-d65caccea92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37610
17669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3761017669
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2681494148
Short name T963
Test name
Test status
Simulation time 3383687341 ps
CPU time 32.24 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:39:24 PM PDT 24
Peak memory 206416 kb
Host smart-bddfe113-3b5b-493d-a0d9-ca1130d1e0c5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2681494148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2681494148
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1738853900
Short name T2612
Test name
Test status
Simulation time 151847781 ps
CPU time 0.76 seconds
Started Jun 29 06:38:55 PM PDT 24
Finished Jun 29 06:38:56 PM PDT 24
Peak memory 206220 kb
Host smart-7f9e6c1d-0d8b-4caf-b2d9-c43f5364e3a1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1738853900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1738853900
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2226227384
Short name T2404
Test name
Test status
Simulation time 155454638 ps
CPU time 0.79 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206212 kb
Host smart-6729470d-5f21-47f1-a806-0e16a08948e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22262
27384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2226227384
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.682202885
Short name T124
Test name
Test status
Simulation time 215385112 ps
CPU time 0.93 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206216 kb
Host smart-4eb748ea-d933-43d9-808e-f6c2db2dd538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68220
2885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.682202885
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2090174838
Short name T434
Test name
Test status
Simulation time 169650263 ps
CPU time 0.88 seconds
Started Jun 29 06:39:02 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206200 kb
Host smart-552c1cf4-3875-4f1f-ba73-61b1d6629dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20901
74838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2090174838
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2334868577
Short name T779
Test name
Test status
Simulation time 170422649 ps
CPU time 0.79 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:39:01 PM PDT 24
Peak memory 206196 kb
Host smart-97c05c6e-b60d-4424-8208-6d7d1502b43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23348
68577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2334868577
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3209461503
Short name T30
Test name
Test status
Simulation time 176963676 ps
CPU time 0.91 seconds
Started Jun 29 06:39:02 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206172 kb
Host smart-dcc4fc96-262d-4590-9028-0f45fa0e9300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32094
61503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3209461503
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3842916469
Short name T1366
Test name
Test status
Simulation time 190583730 ps
CPU time 0.85 seconds
Started Jun 29 06:38:57 PM PDT 24
Finished Jun 29 06:38:59 PM PDT 24
Peak memory 206200 kb
Host smart-53459a91-bf2b-4602-b29c-4403e16a7383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38429
16469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3842916469
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2230403822
Short name T1388
Test name
Test status
Simulation time 231405643 ps
CPU time 1.01 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 206224 kb
Host smart-ea80994e-8c2d-45e4-96e4-0cd4e4749d33
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2230403822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2230403822
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3068693294
Short name T1486
Test name
Test status
Simulation time 138761381 ps
CPU time 0.77 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206204 kb
Host smart-8f91fcc3-d227-4b6d-8919-f94350947472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30686
93294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3068693294
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3455667358
Short name T2495
Test name
Test status
Simulation time 64912682 ps
CPU time 0.68 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:38:52 PM PDT 24
Peak memory 206216 kb
Host smart-05967c23-5523-4807-b586-dc7359429360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34556
67358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3455667358
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2091944125
Short name T261
Test name
Test status
Simulation time 23539436499 ps
CPU time 54.43 seconds
Started Jun 29 06:38:55 PM PDT 24
Finished Jun 29 06:39:50 PM PDT 24
Peak memory 206452 kb
Host smart-bf2e0103-7659-43a5-9f2b-b4c548887dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20919
44125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2091944125
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1782992239
Short name T1135
Test name
Test status
Simulation time 227721005 ps
CPU time 0.86 seconds
Started Jun 29 06:38:53 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 206196 kb
Host smart-72a0ab27-0140-4082-9e01-36e5f61ebd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17829
92239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1782992239
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1441936592
Short name T469
Test name
Test status
Simulation time 218112088 ps
CPU time 0.89 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 206124 kb
Host smart-017d4e89-35bc-4e56-b117-9777974169d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14419
36592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1441936592
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.865679521
Short name T2257
Test name
Test status
Simulation time 204775851 ps
CPU time 0.9 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206180 kb
Host smart-7cd1e218-a455-4685-8cfb-6c49e820d991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86567
9521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.865679521
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3439692224
Short name T730
Test name
Test status
Simulation time 244144157 ps
CPU time 0.96 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206200 kb
Host smart-546930c7-b354-45ed-bc33-c9d7767ae557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34396
92224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3439692224
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1451659037
Short name T80
Test name
Test status
Simulation time 188505998 ps
CPU time 0.93 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206188 kb
Host smart-7dfb56a1-5570-40d1-9b6b-8b09fb073e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14516
59037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1451659037
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2005717767
Short name T2464
Test name
Test status
Simulation time 192283244 ps
CPU time 0.82 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206172 kb
Host smart-b2aafbf2-83b4-4a9c-a95a-94f7555f6019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20057
17767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2005717767
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.406280191
Short name T1530
Test name
Test status
Simulation time 154738819 ps
CPU time 0.79 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206192 kb
Host smart-758403b5-6bd9-43c4-8bb7-ee51b96954fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40628
0191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.406280191
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.903118664
Short name T2626
Test name
Test status
Simulation time 238420862 ps
CPU time 0.99 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:11 PM PDT 24
Peak memory 206216 kb
Host smart-6a7f555f-62c6-404b-88a8-eb6eecdce955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90311
8664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.903118664
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.3126273729
Short name T2139
Test name
Test status
Simulation time 5909964595 ps
CPU time 44.56 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:49 PM PDT 24
Peak memory 206368 kb
Host smart-36e9c82f-9a33-48de-b366-e309620a62cc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3126273729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.3126273729
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2430102997
Short name T1964
Test name
Test status
Simulation time 213634973 ps
CPU time 0.9 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206224 kb
Host smart-18257fd9-b7d2-48fc-b5d3-f743e3ca105b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24301
02997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2430102997
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1807326168
Short name T431
Test name
Test status
Simulation time 196465584 ps
CPU time 0.85 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 206148 kb
Host smart-46522516-2147-4878-b8cd-626a44f28672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18073
26168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1807326168
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.68621709
Short name T1659
Test name
Test status
Simulation time 5344014693 ps
CPU time 143.59 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:41:26 PM PDT 24
Peak memory 206440 kb
Host smart-9411ede5-70d2-4524-997d-9f73041ed404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68621
709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.68621709
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.3426012420
Short name T1362
Test name
Test status
Simulation time 46245854 ps
CPU time 0.7 seconds
Started Jun 29 06:38:57 PM PDT 24
Finished Jun 29 06:38:58 PM PDT 24
Peak memory 206212 kb
Host smart-c1f615c6-315b-463e-a7c1-bebc57110ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3426012420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3426012420
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2538000643
Short name T889
Test name
Test status
Simulation time 4112524216 ps
CPU time 4.93 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206276 kb
Host smart-6a0e11ec-6cde-47de-adfe-5982a0884774
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2538000643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.2538000643
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1328195567
Short name T2374
Test name
Test status
Simulation time 13418139029 ps
CPU time 16.1 seconds
Started Jun 29 06:38:51 PM PDT 24
Finished Jun 29 06:39:08 PM PDT 24
Peak memory 206404 kb
Host smart-c023404b-48c0-4347-9dba-203d5d4f104a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1328195567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1328195567
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3389579833
Short name T1570
Test name
Test status
Simulation time 23329956189 ps
CPU time 21.39 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:22 PM PDT 24
Peak memory 206396 kb
Host smart-e8777639-6bf6-46c1-aa7e-d46563fbb7e3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3389579833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.3389579833
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2137228747
Short name T1494
Test name
Test status
Simulation time 162725194 ps
CPU time 0.84 seconds
Started Jun 29 06:38:57 PM PDT 24
Finished Jun 29 06:38:58 PM PDT 24
Peak memory 206196 kb
Host smart-0f6176fa-3a22-466a-8b5c-5205ee107b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21372
28747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2137228747
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1576600552
Short name T1734
Test name
Test status
Simulation time 165089098 ps
CPU time 0.8 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206172 kb
Host smart-9a690186-ee3b-4f66-bcdf-9107083b28a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15766
00552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1576600552
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.2792865916
Short name T546
Test name
Test status
Simulation time 178672827 ps
CPU time 0.84 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:08 PM PDT 24
Peak memory 206200 kb
Host smart-5a44f4cf-47cb-47e7-87eb-514f49893e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27928
65916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.2792865916
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.29072631
Short name T176
Test name
Test status
Simulation time 1144330426 ps
CPU time 2.51 seconds
Started Jun 29 06:38:56 PM PDT 24
Finished Jun 29 06:38:58 PM PDT 24
Peak memory 206272 kb
Host smart-c7d2b2c4-9d9e-4e73-acb0-8c85d9787d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29072
631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.29072631
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3101237213
Short name T2148
Test name
Test status
Simulation time 7076617779 ps
CPU time 13.17 seconds
Started Jun 29 06:38:57 PM PDT 24
Finished Jun 29 06:39:11 PM PDT 24
Peak memory 206444 kb
Host smart-726caaf7-e2e1-4fbf-9c3a-f4e1ad3fdfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31012
37213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3101237213
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.4203167051
Short name T1553
Test name
Test status
Simulation time 332436064 ps
CPU time 1.15 seconds
Started Jun 29 06:38:51 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206208 kb
Host smart-a2b39df5-c5eb-461a-9e33-960d8a76c65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42031
67051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.4203167051
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.567097267
Short name T1908
Test name
Test status
Simulation time 147230170 ps
CPU time 0.78 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206196 kb
Host smart-e943a740-5ef9-49b4-a936-54f7b59ea43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56709
7267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.567097267
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3823870699
Short name T1666
Test name
Test status
Simulation time 43220185 ps
CPU time 0.74 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206172 kb
Host smart-4d08067d-73c6-4e97-8c4a-6b4be8ba8183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38238
70699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3823870699
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1119348564
Short name T826
Test name
Test status
Simulation time 874537895 ps
CPU time 2.33 seconds
Started Jun 29 06:38:50 PM PDT 24
Finished Jun 29 06:38:53 PM PDT 24
Peak memory 206312 kb
Host smart-3b5e9735-e930-40de-b834-d9a8168d1000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11193
48564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1119348564
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1677079739
Short name T646
Test name
Test status
Simulation time 186383599 ps
CPU time 1.83 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 206372 kb
Host smart-a1a05562-aa21-4f0e-b12a-6a375c4c8809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16770
79739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1677079739
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2147634573
Short name T676
Test name
Test status
Simulation time 199731898 ps
CPU time 0.88 seconds
Started Jun 29 06:39:07 PM PDT 24
Finished Jun 29 06:39:09 PM PDT 24
Peak memory 206204 kb
Host smart-f3159b38-f322-468b-ad4b-10ccd4fc1193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21476
34573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2147634573
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2646813770
Short name T2387
Test name
Test status
Simulation time 162374334 ps
CPU time 0.78 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206160 kb
Host smart-83cd9fb3-a529-4aa6-a834-8a4e66518ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26468
13770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2646813770
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.899787977
Short name T228
Test name
Test status
Simulation time 210138042 ps
CPU time 0.92 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206180 kb
Host smart-2bf1681d-d3b2-4624-b102-48c60ada707d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89978
7977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.899787977
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.703352221
Short name T896
Test name
Test status
Simulation time 5018910305 ps
CPU time 141.31 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:41:35 PM PDT 24
Peak memory 206488 kb
Host smart-b0af9f25-9d01-43db-9537-75279f0f30e6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=703352221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.703352221
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.1978751730
Short name T489
Test name
Test status
Simulation time 288996288 ps
CPU time 1 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206148 kb
Host smart-a4b40f57-31e6-4762-ac99-e9f1682d7976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19787
51730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1978751730
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.1279755544
Short name T1173
Test name
Test status
Simulation time 23342561809 ps
CPU time 22.83 seconds
Started Jun 29 06:38:53 PM PDT 24
Finished Jun 29 06:39:17 PM PDT 24
Peak memory 206316 kb
Host smart-aae24af0-01b7-4d64-a884-ed62fca6cb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12797
55544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1279755544
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3013689461
Short name T2225
Test name
Test status
Simulation time 3361163684 ps
CPU time 4 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206256 kb
Host smart-2fdba7c9-bb9a-4a43-9383-271eb9f37bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30136
89461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3013689461
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.1819342038
Short name T2018
Test name
Test status
Simulation time 10362044782 ps
CPU time 100.45 seconds
Started Jun 29 06:38:53 PM PDT 24
Finished Jun 29 06:40:35 PM PDT 24
Peak memory 206424 kb
Host smart-d0408ac4-1059-4279-ba2a-2c06da91c1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18193
42038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.1819342038
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.1170443770
Short name T1431
Test name
Test status
Simulation time 3564130373 ps
CPU time 99.09 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:40:43 PM PDT 24
Peak memory 206344 kb
Host smart-bdd07604-4820-461c-bbb6-1876403a9da6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1170443770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.1170443770
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3796281006
Short name T363
Test name
Test status
Simulation time 263775631 ps
CPU time 0.99 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206216 kb
Host smart-9fe80c92-e51c-4809-bb24-2fcb213669a2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3796281006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3796281006
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.298161190
Short name T1394
Test name
Test status
Simulation time 207715619 ps
CPU time 0.88 seconds
Started Jun 29 06:38:52 PM PDT 24
Finished Jun 29 06:38:54 PM PDT 24
Peak memory 206116 kb
Host smart-65ed9e3a-c31a-4e3a-b0b2-212e8aafbe53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29816
1190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.298161190
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1095701778
Short name T1561
Test name
Test status
Simulation time 6433754148 ps
CPU time 61.75 seconds
Started Jun 29 06:39:04 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206420 kb
Host smart-77461cb9-2783-428f-a0d2-3b849c517560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10957
01778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1095701778
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.531615856
Short name T1949
Test name
Test status
Simulation time 5167563585 ps
CPU time 44.32 seconds
Started Jun 29 06:38:53 PM PDT 24
Finished Jun 29 06:39:39 PM PDT 24
Peak memory 206464 kb
Host smart-fa0ad1cd-d151-4d31-a646-4a21ef5a4bb4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=531615856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.531615856
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2884157847
Short name T1791
Test name
Test status
Simulation time 199094617 ps
CPU time 0.87 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206220 kb
Host smart-2e3a4479-a777-425d-af67-517322637b96
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2884157847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2884157847
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2142330995
Short name T2517
Test name
Test status
Simulation time 168379145 ps
CPU time 0.82 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206216 kb
Host smart-02ff7e8e-510c-421c-bade-cd2b63fb81f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21423
30995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2142330995
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2173533140
Short name T152
Test name
Test status
Simulation time 198392904 ps
CPU time 0.79 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 206196 kb
Host smart-4666ad2c-9883-4d07-9a79-0cbc9f533d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21735
33140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2173533140
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.675495242
Short name T465
Test name
Test status
Simulation time 161309420 ps
CPU time 0.83 seconds
Started Jun 29 06:38:53 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 206200 kb
Host smart-0fb22175-976a-4d29-93cb-421d1d943bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67549
5242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.675495242
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3974807455
Short name T2216
Test name
Test status
Simulation time 199198812 ps
CPU time 0.82 seconds
Started Jun 29 06:39:02 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206172 kb
Host smart-4288cc37-ef20-43e5-8c87-cb2cec622784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39748
07455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3974807455
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3114200834
Short name T1458
Test name
Test status
Simulation time 145309044 ps
CPU time 0.78 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:07 PM PDT 24
Peak memory 206196 kb
Host smart-c7e8c25b-a6dd-41ba-b62f-7ea748016708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31142
00834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3114200834
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1956953120
Short name T1872
Test name
Test status
Simulation time 157563233 ps
CPU time 0.8 seconds
Started Jun 29 06:39:09 PM PDT 24
Finished Jun 29 06:39:10 PM PDT 24
Peak memory 206200 kb
Host smart-c73731c7-2779-4287-adb3-85d6c18dbc7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19569
53120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1956953120
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.645755243
Short name T2051
Test name
Test status
Simulation time 186942654 ps
CPU time 0.86 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:14 PM PDT 24
Peak memory 206372 kb
Host smart-b604de8f-2a5e-4786-9ea0-efc675be563a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=645755243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.645755243
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1131339688
Short name T1121
Test name
Test status
Simulation time 151897795 ps
CPU time 0.79 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:38:59 PM PDT 24
Peak memory 206212 kb
Host smart-0dbc5f09-27b7-4011-8906-f5bbc5e470cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11313
39688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1131339688
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.13629606
Short name T1113
Test name
Test status
Simulation time 33112374 ps
CPU time 0.67 seconds
Started Jun 29 06:38:55 PM PDT 24
Finished Jun 29 06:38:56 PM PDT 24
Peak memory 206188 kb
Host smart-91d7468c-5305-4b95-ac11-36740f1b375d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13629
606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.13629606
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.123120938
Short name T257
Test name
Test status
Simulation time 7096134801 ps
CPU time 16.51 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:19 PM PDT 24
Peak memory 206448 kb
Host smart-8fb81409-4f02-41ce-9351-4a4a7a0be5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12312
0938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.123120938
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.372809682
Short name T845
Test name
Test status
Simulation time 157881656 ps
CPU time 0.83 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206204 kb
Host smart-f03128ed-9966-4079-a81e-56b8bfeaab33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37280
9682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.372809682
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2481599176
Short name T1875
Test name
Test status
Simulation time 181323059 ps
CPU time 0.85 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206212 kb
Host smart-2611d8d9-630b-4ab0-9ac4-1c1e17626569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24815
99176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2481599176
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.349398582
Short name T392
Test name
Test status
Simulation time 235420151 ps
CPU time 0.94 seconds
Started Jun 29 06:38:57 PM PDT 24
Finished Jun 29 06:38:59 PM PDT 24
Peak memory 206216 kb
Host smart-5de46006-f92c-42ad-8270-7b63e35005db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34939
8582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.349398582
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2438968798
Short name T1438
Test name
Test status
Simulation time 220807121 ps
CPU time 0.87 seconds
Started Jun 29 06:39:07 PM PDT 24
Finished Jun 29 06:39:09 PM PDT 24
Peak memory 206200 kb
Host smart-3c87a77c-10fa-4f8e-b8e7-ce2d547f9059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24389
68798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2438968798
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.4154099153
Short name T1776
Test name
Test status
Simulation time 177669093 ps
CPU time 0.8 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 206200 kb
Host smart-bdaf808f-8c90-4dab-97fd-90f1400450d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41540
99153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.4154099153
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2490701228
Short name T2149
Test name
Test status
Simulation time 150296804 ps
CPU time 0.8 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206192 kb
Host smart-db855f39-23c8-443d-9a95-ec2562734af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24907
01228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2490701228
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1356141843
Short name T697
Test name
Test status
Simulation time 159099420 ps
CPU time 0.88 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206216 kb
Host smart-bd1ca8bc-73c3-4fb1-870e-5799f4a916fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13561
41843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1356141843
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2756955003
Short name T2120
Test name
Test status
Simulation time 212948671 ps
CPU time 0.89 seconds
Started Jun 29 06:39:04 PM PDT 24
Finished Jun 29 06:39:06 PM PDT 24
Peak memory 206160 kb
Host smart-c669350b-0c01-4149-a93c-0118453681af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27569
55003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2756955003
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.277509391
Short name T157
Test name
Test status
Simulation time 3571211577 ps
CPU time 96.71 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:40:41 PM PDT 24
Peak memory 206504 kb
Host smart-5892ec33-ffc3-4787-aed6-87a655a1d95c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=277509391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.277509391
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2696563615
Short name T782
Test name
Test status
Simulation time 178097621 ps
CPU time 0.85 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:12 PM PDT 24
Peak memory 206188 kb
Host smart-7cb3f2b1-2bf6-4872-9445-d298278d57fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26965
63615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2696563615
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3399893631
Short name T1826
Test name
Test status
Simulation time 179084576 ps
CPU time 0.83 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:07 PM PDT 24
Peak memory 206196 kb
Host smart-936807ad-ec5a-4b2a-a1f3-ebe534e04be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33998
93631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3399893631
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.812128543
Short name T464
Test name
Test status
Simulation time 5523411442 ps
CPU time 38.96 seconds
Started Jun 29 06:39:08 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206424 kb
Host smart-de26134d-68ef-40d8-a763-8de249eb8860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81212
8543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.812128543
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.845365537
Short name T1738
Test name
Test status
Simulation time 49345973 ps
CPU time 0.71 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:27 PM PDT 24
Peak memory 206212 kb
Host smart-8b28866d-3180-48b0-8f85-f3dccfaf4f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=845365537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.845365537
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3611403626
Short name T220
Test name
Test status
Simulation time 3939053804 ps
CPU time 5.11 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:22 PM PDT 24
Peak memory 206280 kb
Host smart-d2b3e81a-e2f7-43cf-894e-e3b84d726df6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3611403626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.3611403626
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.392690395
Short name T1835
Test name
Test status
Simulation time 13381665792 ps
CPU time 13.09 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:32 PM PDT 24
Peak memory 206504 kb
Host smart-d4ba8a14-19d7-4727-a419-8954e0c42773
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=392690395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.392690395
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.2021990467
Short name T1002
Test name
Test status
Simulation time 23336156408 ps
CPU time 22.25 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 206404 kb
Host smart-5bc515ca-a3bf-4100-a72b-ab2e9f1e7dd4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2021990467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.2021990467
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2746617043
Short name T950
Test name
Test status
Simulation time 167300051 ps
CPU time 0.88 seconds
Started Jun 29 06:34:15 PM PDT 24
Finished Jun 29 06:34:17 PM PDT 24
Peak memory 206216 kb
Host smart-28d9dc3e-2ae6-469d-ac62-13903c484480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27466
17043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2746617043
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.2365140616
Short name T60
Test name
Test status
Simulation time 180113420 ps
CPU time 0.85 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 205676 kb
Host smart-8d5eabc3-991c-47ea-8048-597a7870a469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23651
40616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.2365140616
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2252689110
Short name T74
Test name
Test status
Simulation time 137533424 ps
CPU time 0.73 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 206216 kb
Host smart-7061d13f-ec55-48a4-b60f-323a3813579b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
89110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2252689110
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.646845307
Short name T604
Test name
Test status
Simulation time 144181490 ps
CPU time 0.85 seconds
Started Jun 29 06:34:17 PM PDT 24
Finished Jun 29 06:34:19 PM PDT 24
Peak memory 206196 kb
Host smart-b3b04ee7-3271-4adb-a5b3-5b8cc92c0aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64684
5307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.646845307
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.3211670168
Short name T871
Test name
Test status
Simulation time 365970311 ps
CPU time 1.38 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:19 PM PDT 24
Peak memory 206196 kb
Host smart-21507a6f-e0d3-4e22-b36b-46ea43e3bb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32116
70168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.3211670168
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2087179014
Short name T1726
Test name
Test status
Simulation time 995679937 ps
CPU time 2.15 seconds
Started Jun 29 06:34:17 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 206272 kb
Host smart-adbbf3a7-0787-4a38-9844-52c3d242a810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20871
79014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2087179014
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2235034928
Short name T1400
Test name
Test status
Simulation time 8724890527 ps
CPU time 16.14 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:33 PM PDT 24
Peak memory 206504 kb
Host smart-c127208d-cf71-4159-8ec3-0ed32ee3c169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22350
34928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2235034928
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1293418667
Short name T971
Test name
Test status
Simulation time 517231198 ps
CPU time 1.51 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 206220 kb
Host smart-e9768843-1b18-48f5-ab18-335a72040450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12934
18667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1293418667
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2495862852
Short name T805
Test name
Test status
Simulation time 140798694 ps
CPU time 0.84 seconds
Started Jun 29 06:34:17 PM PDT 24
Finished Jun 29 06:34:19 PM PDT 24
Peak memory 206192 kb
Host smart-b3530ee8-ed48-4e2b-bbaf-752ff65aff1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24958
62852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2495862852
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.655207594
Short name T359
Test name
Test status
Simulation time 37696665 ps
CPU time 0.69 seconds
Started Jun 29 06:34:15 PM PDT 24
Finished Jun 29 06:34:16 PM PDT 24
Peak memory 206208 kb
Host smart-e56d796f-ea12-4427-a459-413d56ae8fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65520
7594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.655207594
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3985220891
Short name T1800
Test name
Test status
Simulation time 929316405 ps
CPU time 2.39 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:22 PM PDT 24
Peak memory 206384 kb
Host smart-c8755755-ebf6-46be-af1d-61c5e10b46c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39852
20891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3985220891
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.4163806933
Short name T909
Test name
Test status
Simulation time 327031392 ps
CPU time 2.21 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:22 PM PDT 24
Peak memory 206356 kb
Host smart-e75e1ee6-32fa-40fa-b68c-6e9c3c2859e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41638
06933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.4163806933
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.357787793
Short name T1086
Test name
Test status
Simulation time 222844343 ps
CPU time 0.96 seconds
Started Jun 29 06:34:17 PM PDT 24
Finished Jun 29 06:34:19 PM PDT 24
Peak memory 206216 kb
Host smart-5d6cfd58-490b-459a-8200-5f5df4c443e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35778
7793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.357787793
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3947074989
Short name T745
Test name
Test status
Simulation time 171682352 ps
CPU time 0.78 seconds
Started Jun 29 06:34:15 PM PDT 24
Finished Jun 29 06:34:16 PM PDT 24
Peak memory 206212 kb
Host smart-639dd895-0acc-42d3-b923-e91481aab90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39470
74989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3947074989
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.977468956
Short name T1510
Test name
Test status
Simulation time 237729958 ps
CPU time 0.92 seconds
Started Jun 29 06:34:14 PM PDT 24
Finished Jun 29 06:34:16 PM PDT 24
Peak memory 206204 kb
Host smart-b97de1c7-8f04-4921-baf9-821806d6b3f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97746
8956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.977468956
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2121097480
Short name T2305
Test name
Test status
Simulation time 214417521 ps
CPU time 0.88 seconds
Started Jun 29 06:34:17 PM PDT 24
Finished Jun 29 06:34:19 PM PDT 24
Peak memory 206192 kb
Host smart-579dafd6-44f9-4642-948a-f4e0a78a5a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21210
97480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2121097480
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.254455975
Short name T1026
Test name
Test status
Simulation time 23282241748 ps
CPU time 28.77 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:48 PM PDT 24
Peak memory 206320 kb
Host smart-2f285313-b1e2-4555-97a6-e54588f16d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25445
5975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.254455975
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1189844900
Short name T634
Test name
Test status
Simulation time 3303125146 ps
CPU time 4.39 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:21 PM PDT 24
Peak memory 206264 kb
Host smart-8f9e4c56-66cf-42c6-9f18-2630fd5825a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11898
44900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1189844900
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3474366528
Short name T1520
Test name
Test status
Simulation time 6684570428 ps
CPU time 66.06 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:35:24 PM PDT 24
Peak memory 206420 kb
Host smart-4e3d7429-66ae-4121-a4af-d8e42e9088d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34743
66528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3474366528
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.4241192954
Short name T5
Test name
Test status
Simulation time 4671002979 ps
CPU time 132.08 seconds
Started Jun 29 06:34:19 PM PDT 24
Finished Jun 29 06:36:32 PM PDT 24
Peak memory 206464 kb
Host smart-73b1cea8-41d6-4d28-833f-562eddbfedd1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4241192954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.4241192954
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.1286092302
Short name T2159
Test name
Test status
Simulation time 235905898 ps
CPU time 0.91 seconds
Started Jun 29 06:34:17 PM PDT 24
Finished Jun 29 06:34:19 PM PDT 24
Peak memory 206212 kb
Host smart-851b093d-84b8-4eb5-9efa-97776d038c4c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1286092302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.1286092302
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2477283175
Short name T1296
Test name
Test status
Simulation time 189376185 ps
CPU time 0.83 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 206212 kb
Host smart-610583e7-4d4a-4a1d-a9a0-e37c82ebea98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24772
83175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2477283175
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2843564873
Short name T1159
Test name
Test status
Simulation time 3849327267 ps
CPU time 26.42 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:46 PM PDT 24
Peak memory 206396 kb
Host smart-ce35b06d-9303-4932-8d90-6a690081d17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28435
64873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2843564873
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2644165132
Short name T1894
Test name
Test status
Simulation time 3287264291 ps
CPU time 24.54 seconds
Started Jun 29 06:34:15 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 206428 kb
Host smart-1462b4cd-e4c1-49ba-b808-6bf7bd22586a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2644165132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2644165132
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1848977454
Short name T1559
Test name
Test status
Simulation time 153977446 ps
CPU time 0.83 seconds
Started Jun 29 06:34:17 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 206220 kb
Host smart-c03ba286-a25e-4887-ac51-3afb3d82843a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1848977454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1848977454
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.342218978
Short name T439
Test name
Test status
Simulation time 153575235 ps
CPU time 0.79 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 205876 kb
Host smart-17c59647-4237-42cb-a60d-b51fb985af1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34221
8978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.342218978
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.316330178
Short name T128
Test name
Test status
Simulation time 241245331 ps
CPU time 0.9 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 206216 kb
Host smart-3c138c58-8a75-468d-afe8-c2c262596c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31633
0178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.316330178
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1064506763
Short name T1523
Test name
Test status
Simulation time 220242408 ps
CPU time 0.9 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 206228 kb
Host smart-859e5e95-8a83-45e9-a047-77912563cf98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10645
06763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1064506763
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2903769622
Short name T1595
Test name
Test status
Simulation time 195424009 ps
CPU time 0.87 seconds
Started Jun 29 06:34:17 PM PDT 24
Finished Jun 29 06:34:19 PM PDT 24
Peak memory 206216 kb
Host smart-22aa95ee-94d0-4219-b462-5e9a16f4558d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29037
69622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2903769622
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2895376609
Short name T1984
Test name
Test status
Simulation time 221193900 ps
CPU time 0.93 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 206196 kb
Host smart-46540895-5f4b-43f2-bf7a-66a9c2658fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28953
76609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2895376609
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2105064546
Short name T2497
Test name
Test status
Simulation time 162572275 ps
CPU time 0.85 seconds
Started Jun 29 06:34:17 PM PDT 24
Finished Jun 29 06:34:19 PM PDT 24
Peak memory 206220 kb
Host smart-962162cc-236b-4d7e-a221-fa65854238f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21050
64546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2105064546
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3641914759
Short name T1414
Test name
Test status
Simulation time 282494067 ps
CPU time 1.01 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 206204 kb
Host smart-84aaf218-c4f7-4ca4-a316-b19886f9fac6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3641914759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3641914759
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2870490324
Short name T549
Test name
Test status
Simulation time 190160990 ps
CPU time 0.91 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 205968 kb
Host smart-1fcf8af0-3a91-4640-bdb6-36f9694c9c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28704
90324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2870490324
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1733082541
Short name T1624
Test name
Test status
Simulation time 156051270 ps
CPU time 0.8 seconds
Started Jun 29 06:34:15 PM PDT 24
Finished Jun 29 06:34:17 PM PDT 24
Peak memory 206212 kb
Host smart-ed222793-23d0-4cb4-863a-2d169d506129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17330
82541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1733082541
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2706523304
Short name T2344
Test name
Test status
Simulation time 38912979 ps
CPU time 0.65 seconds
Started Jun 29 06:34:19 PM PDT 24
Finished Jun 29 06:34:21 PM PDT 24
Peak memory 206188 kb
Host smart-36c66f0a-5d09-4b98-9af6-b5ec3d6ff104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27065
23304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2706523304
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.684389772
Short name T1978
Test name
Test status
Simulation time 18761193141 ps
CPU time 39.73 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:56 PM PDT 24
Peak memory 206480 kb
Host smart-e7a23783-25a0-423c-9387-7acff75ed49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68438
9772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.684389772
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1015185458
Short name T1721
Test name
Test status
Simulation time 187737308 ps
CPU time 0.89 seconds
Started Jun 29 06:34:20 PM PDT 24
Finished Jun 29 06:34:21 PM PDT 24
Peak memory 206156 kb
Host smart-07ec127b-e63c-41d6-bce8-f05097402a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10151
85458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1015185458
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3445051167
Short name T941
Test name
Test status
Simulation time 219280387 ps
CPU time 0.93 seconds
Started Jun 29 06:34:16 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 206180 kb
Host smart-342bdde2-9998-47e8-802c-d7c6cafe6e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34450
51167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3445051167
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.4257685857
Short name T2564
Test name
Test status
Simulation time 9221543779 ps
CPU time 226.52 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:38:13 PM PDT 24
Peak memory 206500 kb
Host smart-7938f941-2b7d-4561-b509-5e8a8dd30e66
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4257685857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.4257685857
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3608494729
Short name T162
Test name
Test status
Simulation time 7628221169 ps
CPU time 195.12 seconds
Started Jun 29 06:34:24 PM PDT 24
Finished Jun 29 06:37:39 PM PDT 24
Peak memory 206500 kb
Host smart-e58c49a9-dd24-43bf-a4bb-6ea21d0d2686
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3608494729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3608494729
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.416565517
Short name T624
Test name
Test status
Simulation time 11318633882 ps
CPU time 71.95 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:35:39 PM PDT 24
Peak memory 206440 kb
Host smart-0575b190-c189-4c1c-9e21-9cee42e357c6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=416565517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.416565517
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1227669501
Short name T2121
Test name
Test status
Simulation time 240614158 ps
CPU time 0.96 seconds
Started Jun 29 06:34:18 PM PDT 24
Finished Jun 29 06:34:21 PM PDT 24
Peak memory 206192 kb
Host smart-b5933b64-5edc-4c3b-a245-257d0fb60ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12276
69501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1227669501
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.4126746313
Short name T1233
Test name
Test status
Simulation time 171125853 ps
CPU time 0.82 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206200 kb
Host smart-686b1fe8-3da2-4ac3-831c-6d55cc3692db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41267
46313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.4126746313
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1319932593
Short name T2397
Test name
Test status
Simulation time 152736502 ps
CPU time 0.74 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206196 kb
Host smart-0f072ee7-64c5-4f85-b50f-be8578bf33cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13199
32593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1319932593
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2438638653
Short name T86
Test name
Test status
Simulation time 178705961 ps
CPU time 0.8 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:26 PM PDT 24
Peak memory 206200 kb
Host smart-84752ece-8746-44fb-b016-ce62beb1f8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24386
38653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2438638653
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.207112325
Short name T209
Test name
Test status
Simulation time 223816462 ps
CPU time 1.01 seconds
Started Jun 29 06:34:28 PM PDT 24
Finished Jun 29 06:34:30 PM PDT 24
Peak memory 224016 kb
Host smart-b752f3f7-34a9-46f1-8284-70d831ec6941
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=207112325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.207112325
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.3863354669
Short name T2284
Test name
Test status
Simulation time 424299576 ps
CPU time 1.34 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206220 kb
Host smart-419ee0ea-496f-4f53-bcec-a271e6a2f7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38633
54669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.3863354669
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3944660469
Short name T2573
Test name
Test status
Simulation time 221297713 ps
CPU time 0.94 seconds
Started Jun 29 06:34:29 PM PDT 24
Finished Jun 29 06:34:30 PM PDT 24
Peak memory 206180 kb
Host smart-b024acf4-f94f-4eb7-95cd-95c93e069594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
60469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3944660469
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.920934517
Short name T653
Test name
Test status
Simulation time 141606969 ps
CPU time 0.81 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206200 kb
Host smart-74d1ab5e-79dc-4f67-b5eb-01fc26a4b3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92093
4517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.920934517
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1479537177
Short name T2166
Test name
Test status
Simulation time 199428154 ps
CPU time 0.81 seconds
Started Jun 29 06:34:24 PM PDT 24
Finished Jun 29 06:34:25 PM PDT 24
Peak memory 206196 kb
Host smart-847680a9-57e9-4aec-b32b-b6db76a8b7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14795
37177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1479537177
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3657845489
Short name T700
Test name
Test status
Simulation time 261748199 ps
CPU time 1 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206216 kb
Host smart-3ce10e31-9ece-4258-af42-96982f643f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36578
45489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3657845489
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.687343588
Short name T442
Test name
Test status
Simulation time 4093541411 ps
CPU time 111.25 seconds
Started Jun 29 06:34:24 PM PDT 24
Finished Jun 29 06:36:15 PM PDT 24
Peak memory 206504 kb
Host smart-4a9ccc8b-5149-459e-b4b1-a8456d65e8ae
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=687343588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.687343588
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3980648935
Short name T1717
Test name
Test status
Simulation time 179492369 ps
CPU time 0.84 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:26 PM PDT 24
Peak memory 206224 kb
Host smart-13ec233e-c547-4452-a5a4-7a6a504242f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39806
48935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3980648935
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2451412604
Short name T1614
Test name
Test status
Simulation time 158261204 ps
CPU time 0.79 seconds
Started Jun 29 06:34:27 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206204 kb
Host smart-c88a03d5-7a09-4425-9eee-ef04a28d1206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24514
12604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2451412604
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.665406848
Short name T1967
Test name
Test status
Simulation time 5292605784 ps
CPU time 152 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:36:59 PM PDT 24
Peak memory 206440 kb
Host smart-baa01016-d531-47f8-bdc9-7375c9660f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66540
6848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.665406848
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.804496913
Short name T2543
Test name
Test status
Simulation time 10023628860 ps
CPU time 60.63 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:35:28 PM PDT 24
Peak memory 206520 kb
Host smart-27a1347f-f068-400d-adfd-184c0539951a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=804496913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.804496913
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.862054204
Short name T517
Test name
Test status
Simulation time 35196478 ps
CPU time 0.68 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206212 kb
Host smart-ac2b4a3a-e6ea-463c-bf5f-cde2020e1fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=862054204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.862054204
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.273389718
Short name T630
Test name
Test status
Simulation time 3438053663 ps
CPU time 4.07 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:10 PM PDT 24
Peak memory 206256 kb
Host smart-5f32b7a2-54a9-40e1-bb81-9c1f8c72b3bb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=273389718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.273389718
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2684124944
Short name T1492
Test name
Test status
Simulation time 13330357538 ps
CPU time 12.45 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:19 PM PDT 24
Peak memory 206500 kb
Host smart-37a04447-7956-4c7b-b6f6-4be3b578bceb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2684124944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2684124944
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2900759669
Short name T16
Test name
Test status
Simulation time 23295116491 ps
CPU time 25.18 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:27 PM PDT 24
Peak memory 206320 kb
Host smart-5df72dca-a21a-4309-9a43-7c5de381fe71
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2900759669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.2900759669
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1389178461
Short name T1945
Test name
Test status
Simulation time 174707029 ps
CPU time 0.89 seconds
Started Jun 29 06:39:02 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206176 kb
Host smart-1883ac45-d7ef-4e02-a089-4541a79158cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13891
78461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1389178461
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.111227884
Short name T868
Test name
Test status
Simulation time 226816573 ps
CPU time 0.86 seconds
Started Jun 29 06:39:04 PM PDT 24
Finished Jun 29 06:39:06 PM PDT 24
Peak memory 206200 kb
Host smart-ccfd75c9-3082-4b74-b074-d312630bf0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11122
7884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.111227884
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3365084261
Short name T2274
Test name
Test status
Simulation time 219987269 ps
CPU time 0.88 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206172 kb
Host smart-b244caf3-acf8-46f9-abfb-56c58689575b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33650
84261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3365084261
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.454083135
Short name T178
Test name
Test status
Simulation time 933584358 ps
CPU time 2.21 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:15 PM PDT 24
Peak memory 206296 kb
Host smart-cb148073-a07c-4c33-bb9d-939b22affa8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45408
3135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.454083135
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.688865956
Short name T763
Test name
Test status
Simulation time 18858100772 ps
CPU time 33.22 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:35 PM PDT 24
Peak memory 206484 kb
Host smart-f53650e5-1d20-4c44-b29e-6b722aeb6840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68886
5956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.688865956
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2447270752
Short name T486
Test name
Test status
Simulation time 498201436 ps
CPU time 1.56 seconds
Started Jun 29 06:39:02 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206176 kb
Host smart-a0f1601d-2934-45ee-9066-2144424eff51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24472
70752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2447270752
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2182266262
Short name T1617
Test name
Test status
Simulation time 151617042 ps
CPU time 0.8 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:08 PM PDT 24
Peak memory 206196 kb
Host smart-7b23e46d-8007-4e07-bb3a-a31d44161525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21822
66262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2182266262
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2965437384
Short name T2574
Test name
Test status
Simulation time 43521336 ps
CPU time 0.69 seconds
Started Jun 29 06:39:07 PM PDT 24
Finished Jun 29 06:39:09 PM PDT 24
Peak memory 206196 kb
Host smart-15fcc8ea-feaf-4ba6-bf88-2b81adbba1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29654
37384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2965437384
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3401379239
Short name T1426
Test name
Test status
Simulation time 888974454 ps
CPU time 2.14 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:12 PM PDT 24
Peak memory 206260 kb
Host smart-09f5bbcd-56ab-45ba-8188-1d9a98142e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34013
79239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3401379239
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3803659039
Short name T197
Test name
Test status
Simulation time 207677630 ps
CPU time 1.18 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 206288 kb
Host smart-d43cb07a-7cd5-4e0e-a5e1-025ebd6bff8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38036
59039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3803659039
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.2950687193
Short name T1138
Test name
Test status
Simulation time 235239771 ps
CPU time 0.92 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206204 kb
Host smart-3132c5a3-2937-4e9c-bb5b-4dfd4fc21724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29506
87193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2950687193
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.700380134
Short name T2629
Test name
Test status
Simulation time 169126967 ps
CPU time 0.81 seconds
Started Jun 29 06:39:04 PM PDT 24
Finished Jun 29 06:39:06 PM PDT 24
Peak memory 206208 kb
Host smart-07de8a19-e305-44a0-9611-f2344641f26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70038
0134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.700380134
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1298186266
Short name T1824
Test name
Test status
Simulation time 170305913 ps
CPU time 0.83 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206208 kb
Host smart-88bddaf3-75c8-4d2c-b58e-4e47c07a0e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12981
86266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1298186266
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.344694453
Short name T231
Test name
Test status
Simulation time 10325009751 ps
CPU time 97.8 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:40:44 PM PDT 24
Peak memory 206344 kb
Host smart-6ac83b22-d9e1-4f61-af38-b48d46ca7131
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=344694453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.344694453
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2626063903
Short name T2086
Test name
Test status
Simulation time 188534450 ps
CPU time 0.84 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206196 kb
Host smart-ad9f0228-52fe-4de5-b6e2-218a6e175a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26260
63903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2626063903
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.2382167779
Short name T1286
Test name
Test status
Simulation time 23342708092 ps
CPU time 24.47 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:36 PM PDT 24
Peak memory 206316 kb
Host smart-b0578cb4-55f0-41e4-87c3-19a1f1386b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23821
67779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.2382167779
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3365929024
Short name T44
Test name
Test status
Simulation time 3293675062 ps
CPU time 3.94 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:08 PM PDT 24
Peak memory 206132 kb
Host smart-a4338524-89df-4c41-ad8b-d4d75f1c4750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33659
29024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3365929024
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.3540449107
Short name T1332
Test name
Test status
Simulation time 8015909987 ps
CPU time 230.26 seconds
Started Jun 29 06:39:19 PM PDT 24
Finished Jun 29 06:43:09 PM PDT 24
Peak memory 206468 kb
Host smart-d38725bf-0aab-46e9-be9d-f57984f9993e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35404
49107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.3540449107
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.4021665756
Short name T2001
Test name
Test status
Simulation time 4078928045 ps
CPU time 37.5 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:44 PM PDT 24
Peak memory 206408 kb
Host smart-1a5c7b0f-ad6d-462b-b144-37972c04f584
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4021665756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.4021665756
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2318717592
Short name T1204
Test name
Test status
Simulation time 265820906 ps
CPU time 0.93 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:11 PM PDT 24
Peak memory 206220 kb
Host smart-ea6dda05-9d9a-4c68-8a7c-6d1ed6899913
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2318717592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2318717592
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3833430426
Short name T518
Test name
Test status
Simulation time 191719573 ps
CPU time 0.81 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:39:01 PM PDT 24
Peak memory 206216 kb
Host smart-d703fe31-5c59-49e5-839e-acec3af79fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38334
30426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3833430426
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.3056516041
Short name T332
Test name
Test status
Simulation time 7007707406 ps
CPU time 69.47 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:40:14 PM PDT 24
Peak memory 206464 kb
Host smart-05182597-8463-4aee-af77-61402eded90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30565
16041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.3056516041
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.767271056
Short name T1847
Test name
Test status
Simulation time 6296047385 ps
CPU time 43.53 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:51 PM PDT 24
Peak memory 206460 kb
Host smart-5fc4f6db-38e5-4e33-a5fa-305e53bce459
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=767271056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.767271056
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3538678541
Short name T2143
Test name
Test status
Simulation time 169248292 ps
CPU time 0.85 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206172 kb
Host smart-b8be07aa-334d-454e-9c01-ba66474ff620
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3538678541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3538678541
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2605834994
Short name T1515
Test name
Test status
Simulation time 191669593 ps
CPU time 0.82 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206216 kb
Host smart-33f01e69-42ed-45b7-b095-b93392335c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26058
34994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2605834994
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3405097443
Short name T831
Test name
Test status
Simulation time 183941645 ps
CPU time 0.81 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:07 PM PDT 24
Peak memory 206040 kb
Host smart-7ab64498-2ce0-4813-8419-84dc4183b7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34050
97443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3405097443
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3945610883
Short name T579
Test name
Test status
Simulation time 179576722 ps
CPU time 0.84 seconds
Started Jun 29 06:39:00 PM PDT 24
Finished Jun 29 06:39:02 PM PDT 24
Peak memory 206204 kb
Host smart-ab3d5e12-b240-44cd-a3b0-54471330d032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39456
10883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3945610883
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.748286016
Short name T2049
Test name
Test status
Simulation time 163305579 ps
CPU time 0.82 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206192 kb
Host smart-37f61e96-aa0c-4e15-9c58-97a2a0dd6486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74828
6016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.748286016
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2289372009
Short name T2514
Test name
Test status
Simulation time 143459398 ps
CPU time 0.78 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:07 PM PDT 24
Peak memory 206196 kb
Host smart-db4d143e-2a88-4ee3-823d-817903c52123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22893
72009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2289372009
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3616045534
Short name T1946
Test name
Test status
Simulation time 184084908 ps
CPU time 0.86 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:08 PM PDT 24
Peak memory 206152 kb
Host smart-26f258fd-fd47-4db0-b7fa-9c8a89651b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36160
45534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3616045534
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.1783156876
Short name T334
Test name
Test status
Simulation time 239809690 ps
CPU time 0.92 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:08 PM PDT 24
Peak memory 206224 kb
Host smart-800e9084-75b2-4bd2-97a8-200b391ae993
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1783156876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.1783156876
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2087963824
Short name T1568
Test name
Test status
Simulation time 156086187 ps
CPU time 0.75 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206212 kb
Host smart-1aea4d59-ea0d-4ce0-9d40-63a62e8f2244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20879
63824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2087963824
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.298096049
Short name T1018
Test name
Test status
Simulation time 38437168 ps
CPU time 0.74 seconds
Started Jun 29 06:39:02 PM PDT 24
Finished Jun 29 06:39:04 PM PDT 24
Peak memory 206204 kb
Host smart-b6930c7c-488a-450b-8c04-c042598e92dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29809
6049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.298096049
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3606436562
Short name T2487
Test name
Test status
Simulation time 19141619885 ps
CPU time 43.43 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:50 PM PDT 24
Peak memory 206512 kb
Host smart-f9fbd6b3-c34c-482a-8b41-d61ff08e176d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36064
36562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3606436562
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3882406144
Short name T1989
Test name
Test status
Simulation time 184554243 ps
CPU time 0.87 seconds
Started Jun 29 06:39:30 PM PDT 24
Finished Jun 29 06:39:31 PM PDT 24
Peak memory 206196 kb
Host smart-926f29b7-f4ec-400b-a254-004b185e887c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38824
06144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3882406144
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3219068711
Short name T2399
Test name
Test status
Simulation time 168976891 ps
CPU time 0.81 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:07 PM PDT 24
Peak memory 206368 kb
Host smart-56c4e162-95b6-4ae1-b816-eb4a2df8971d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32190
68711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3219068711
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1141176240
Short name T1054
Test name
Test status
Simulation time 252437387 ps
CPU time 0.92 seconds
Started Jun 29 06:39:02 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206196 kb
Host smart-55a8cb5f-486d-4533-969f-2b74eacf0913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11411
76240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1141176240
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1928920132
Short name T2229
Test name
Test status
Simulation time 192654031 ps
CPU time 0.92 seconds
Started Jun 29 06:39:01 PM PDT 24
Finished Jun 29 06:39:03 PM PDT 24
Peak memory 206368 kb
Host smart-a22faff6-3cc3-4399-ac6a-5ac53098faf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19289
20132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1928920132
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.427843075
Short name T562
Test name
Test status
Simulation time 161205722 ps
CPU time 0.75 seconds
Started Jun 29 06:39:15 PM PDT 24
Finished Jun 29 06:39:17 PM PDT 24
Peak memory 206184 kb
Host smart-531f0ede-3e1b-4e06-8eba-6bfdaa2b1aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42784
3075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.427843075
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2671731659
Short name T365
Test name
Test status
Simulation time 159059172 ps
CPU time 0.84 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:15 PM PDT 24
Peak memory 206196 kb
Host smart-9bce2ed1-d39b-404c-af8c-68490d05617e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26717
31659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2671731659
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.854718778
Short name T1920
Test name
Test status
Simulation time 156615754 ps
CPU time 0.8 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:13 PM PDT 24
Peak memory 206184 kb
Host smart-3bd276d3-be0c-4ad0-8da4-c51376361302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85471
8778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.854718778
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3621705696
Short name T1566
Test name
Test status
Simulation time 217780855 ps
CPU time 0.9 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:07 PM PDT 24
Peak memory 206216 kb
Host smart-081b0288-8cfb-4d4f-b365-de0510d84e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36217
05696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3621705696
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.3056312928
Short name T784
Test name
Test status
Simulation time 6003406484 ps
CPU time 56.24 seconds
Started Jun 29 06:39:08 PM PDT 24
Finished Jun 29 06:40:05 PM PDT 24
Peak memory 206572 kb
Host smart-5f40bde4-91cd-452c-a96f-81a8182a748d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3056312928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3056312928
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.689791833
Short name T1221
Test name
Test status
Simulation time 149531661 ps
CPU time 0.81 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:07 PM PDT 24
Peak memory 206220 kb
Host smart-85e33f6b-ce09-4c6d-a543-d75d2c1e3491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68979
1833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.689791833
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2577379670
Short name T1532
Test name
Test status
Simulation time 220286777 ps
CPU time 0.92 seconds
Started Jun 29 06:39:04 PM PDT 24
Finished Jun 29 06:39:06 PM PDT 24
Peak memory 206196 kb
Host smart-0d31e15b-6904-4ff3-96b6-106bc77ee31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25773
79670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2577379670
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2504074100
Short name T914
Test name
Test status
Simulation time 5233973110 ps
CPU time 37.84 seconds
Started Jun 29 06:38:58 PM PDT 24
Finished Jun 29 06:39:36 PM PDT 24
Peak memory 206336 kb
Host smart-b0ed33ed-ef0d-418f-8bf9-045faf1f2310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25040
74100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2504074100
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3742190467
Short name T1180
Test name
Test status
Simulation time 83553981 ps
CPU time 0.71 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206160 kb
Host smart-db83203a-f298-4e43-8022-8f023679ab92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3742190467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3742190467
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2401003975
Short name T1470
Test name
Test status
Simulation time 4262714793 ps
CPU time 5.1 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:39:20 PM PDT 24
Peak memory 206356 kb
Host smart-e4cf94c0-de8f-43e2-add5-8853170c0d4c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2401003975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.2401003975
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1525968921
Short name T1643
Test name
Test status
Simulation time 13369785521 ps
CPU time 12.26 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:22 PM PDT 24
Peak memory 206440 kb
Host smart-5ea9bb2d-9efe-4bac-8b37-3161653d4276
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1525968921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1525968921
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2357831707
Short name T900
Test name
Test status
Simulation time 23332958054 ps
CPU time 21.54 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:34 PM PDT 24
Peak memory 206488 kb
Host smart-05ea563d-58ff-4e92-bc84-ab76da309e92
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2357831707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.2357831707
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1734114448
Short name T2538
Test name
Test status
Simulation time 168046784 ps
CPU time 0.85 seconds
Started Jun 29 06:38:59 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 206192 kb
Host smart-0376c267-68a3-4db5-8bfd-716b2073b8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17341
14448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1734114448
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.389959143
Short name T648
Test name
Test status
Simulation time 182759462 ps
CPU time 0.84 seconds
Started Jun 29 06:39:02 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206204 kb
Host smart-32526dab-b4f5-47ac-a2cd-eb8d4780b5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38995
9143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.389959143
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.1701577048
Short name T1271
Test name
Test status
Simulation time 396106264 ps
CPU time 1.28 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:08 PM PDT 24
Peak memory 206108 kb
Host smart-a9bbdcf8-bef9-49f3-9cc2-36083e2236b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17015
77048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1701577048
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1355616756
Short name T111
Test name
Test status
Simulation time 661133557 ps
CPU time 1.69 seconds
Started Jun 29 06:39:07 PM PDT 24
Finished Jun 29 06:39:10 PM PDT 24
Peak memory 206196 kb
Host smart-aac9e099-370e-487e-acbb-baedbe3a3c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13556
16756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1355616756
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.3412229752
Short name T1521
Test name
Test status
Simulation time 13125792941 ps
CPU time 22.57 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:34 PM PDT 24
Peak memory 206416 kb
Host smart-f0a6a484-0751-4b57-b638-514a325976bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34122
29752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.3412229752
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.3792551484
Short name T503
Test name
Test status
Simulation time 415083061 ps
CPU time 1.32 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:13 PM PDT 24
Peak memory 206200 kb
Host smart-29653171-7deb-4959-8e18-f1fd03468933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37925
51484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3792551484
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.3105562551
Short name T1196
Test name
Test status
Simulation time 149032060 ps
CPU time 0.78 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:39:06 PM PDT 24
Peak memory 206196 kb
Host smart-4c9c1cb6-feeb-466a-9ac4-a991182e4d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31055
62551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3105562551
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2232871893
Short name T859
Test name
Test status
Simulation time 61930294 ps
CPU time 0.69 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:12 PM PDT 24
Peak memory 206168 kb
Host smart-c429b670-9d5b-4f11-9eeb-1615ba79bf97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22328
71893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2232871893
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3955806600
Short name T1505
Test name
Test status
Simulation time 945553287 ps
CPU time 2.11 seconds
Started Jun 29 06:39:22 PM PDT 24
Finished Jun 29 06:39:24 PM PDT 24
Peak memory 206296 kb
Host smart-a57420f5-45e3-4a85-a189-2e088e0ab513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39558
06600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3955806600
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.4178384857
Short name T780
Test name
Test status
Simulation time 278835575 ps
CPU time 2.2 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:09 PM PDT 24
Peak memory 206332 kb
Host smart-754f8c4a-6498-4eba-89d7-47f0d3955223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41783
84857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.4178384857
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3655671489
Short name T1507
Test name
Test status
Simulation time 216929535 ps
CPU time 0.9 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:14 PM PDT 24
Peak memory 206200 kb
Host smart-d023b4e7-8104-446f-bc7b-176a0676be34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36556
71489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3655671489
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3196735526
Short name T323
Test name
Test status
Simulation time 186253256 ps
CPU time 0.8 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:15 PM PDT 24
Peak memory 206212 kb
Host smart-c9df93e4-ab9f-443f-a54d-ad1fbba2887a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31967
35526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3196735526
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3376356371
Short name T2133
Test name
Test status
Simulation time 177359456 ps
CPU time 0.86 seconds
Started Jun 29 06:39:03 PM PDT 24
Finished Jun 29 06:39:05 PM PDT 24
Peak memory 206220 kb
Host smart-653c2551-2171-4c6a-8804-01bd0a8af86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33763
56371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3376356371
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2080315096
Short name T504
Test name
Test status
Simulation time 218626057 ps
CPU time 0.84 seconds
Started Jun 29 06:39:30 PM PDT 24
Finished Jun 29 06:39:31 PM PDT 24
Peak memory 206148 kb
Host smart-213529b6-0744-4d4d-a8f3-8c173e82ab9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20803
15096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2080315096
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.2464927729
Short name T2432
Test name
Test status
Simulation time 23310691641 ps
CPU time 23.96 seconds
Started Jun 29 06:39:17 PM PDT 24
Finished Jun 29 06:39:42 PM PDT 24
Peak memory 206320 kb
Host smart-241e9585-2494-4a80-88cd-eceb5bd858f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24649
27729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.2464927729
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1676060255
Short name T2283
Test name
Test status
Simulation time 3278598565 ps
CPU time 4.3 seconds
Started Jun 29 06:39:17 PM PDT 24
Finished Jun 29 06:39:22 PM PDT 24
Peak memory 206248 kb
Host smart-deb518e4-327e-4952-861d-e4c6455091f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16760
60255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1676060255
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.735401870
Short name T488
Test name
Test status
Simulation time 8778117055 ps
CPU time 69.36 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:40:22 PM PDT 24
Peak memory 206428 kb
Host smart-27c49211-c891-426f-b39f-af3f6bc88a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73540
1870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.735401870
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.868440246
Short name T1526
Test name
Test status
Simulation time 4604440292 ps
CPU time 33.14 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206500 kb
Host smart-fe9700d2-7bbc-487f-9a54-16868be39a73
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=868440246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.868440246
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1152353766
Short name T2243
Test name
Test status
Simulation time 240875575 ps
CPU time 0.95 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:13 PM PDT 24
Peak memory 206220 kb
Host smart-bdb19a90-4606-4b40-82d7-59e51d69d901
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1152353766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1152353766
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1007711740
Short name T89
Test name
Test status
Simulation time 182346787 ps
CPU time 0.85 seconds
Started Jun 29 06:39:20 PM PDT 24
Finished Jun 29 06:39:21 PM PDT 24
Peak memory 206136 kb
Host smart-eb8b2d79-8939-4bf2-9e9f-eb0e90fb86fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10077
11740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1007711740
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.466419841
Short name T1593
Test name
Test status
Simulation time 5958904499 ps
CPU time 56.34 seconds
Started Jun 29 06:39:05 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206412 kb
Host smart-1b07aefa-a4e6-4405-b414-a24ae07963ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46641
9841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.466419841
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.1113556172
Short name T1216
Test name
Test status
Simulation time 5156548951 ps
CPU time 138.62 seconds
Started Jun 29 06:39:09 PM PDT 24
Finished Jun 29 06:41:28 PM PDT 24
Peak memory 206464 kb
Host smart-2c91db06-f1b9-40ad-b190-94449c27f34b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1113556172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.1113556172
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2855756098
Short name T612
Test name
Test status
Simulation time 195133215 ps
CPU time 0.87 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:14 PM PDT 24
Peak memory 206216 kb
Host smart-2ac53ba1-e86b-44af-9d65-05995dafddbd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2855756098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2855756098
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.4096139327
Short name T636
Test name
Test status
Simulation time 157498585 ps
CPU time 0.85 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:12 PM PDT 24
Peak memory 206184 kb
Host smart-99b734fe-a9c3-4770-9aae-1a30ffa22e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40961
39327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.4096139327
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2396964269
Short name T1176
Test name
Test status
Simulation time 201517750 ps
CPU time 0.85 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:12 PM PDT 24
Peak memory 206196 kb
Host smart-c4783882-bdcf-4688-9b0e-5b7e2c40bb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23969
64269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2396964269
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1523015603
Short name T2505
Test name
Test status
Simulation time 180148338 ps
CPU time 0.8 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:15 PM PDT 24
Peak memory 206204 kb
Host smart-1612f66d-1a22-49f2-a60b-e3613ee6d6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15230
15603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1523015603
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2535698409
Short name T1429
Test name
Test status
Simulation time 146149967 ps
CPU time 0.83 seconds
Started Jun 29 06:39:16 PM PDT 24
Finished Jun 29 06:39:17 PM PDT 24
Peak memory 206188 kb
Host smart-999e0258-e971-4843-a7da-8c2c183165b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25356
98409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2535698409
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2347153017
Short name T1425
Test name
Test status
Simulation time 189448824 ps
CPU time 0.82 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206188 kb
Host smart-b727d367-87c6-4d28-88e7-ff62a7a7b859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23471
53017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2347153017
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.93782586
Short name T2116
Test name
Test status
Simulation time 184746023 ps
CPU time 0.87 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:08 PM PDT 24
Peak memory 206220 kb
Host smart-c3bf08c3-8c68-4dc1-b35a-bb60d04cc0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93782
586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.93782586
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.3950931000
Short name T354
Test name
Test status
Simulation time 242444734 ps
CPU time 0.99 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:15 PM PDT 24
Peak memory 206224 kb
Host smart-e1eea2c8-ca99-4a58-bea1-2d5fc203da77
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3950931000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3950931000
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.4021033304
Short name T2171
Test name
Test status
Simulation time 146947791 ps
CPU time 0.86 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:13 PM PDT 24
Peak memory 206212 kb
Host smart-a90ec516-a0b4-4e45-a7ee-bd15b7602f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40210
33304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.4021033304
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.1933625353
Short name T28
Test name
Test status
Simulation time 78015252 ps
CPU time 0.72 seconds
Started Jun 29 06:39:17 PM PDT 24
Finished Jun 29 06:39:18 PM PDT 24
Peak memory 206212 kb
Host smart-dd5b404f-e6c1-4742-b0de-bcca7178a589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19336
25353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.1933625353
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1561174264
Short name T1354
Test name
Test status
Simulation time 11329427968 ps
CPU time 24.63 seconds
Started Jun 29 06:39:17 PM PDT 24
Finished Jun 29 06:39:42 PM PDT 24
Peak memory 206472 kb
Host smart-ef1b1522-4b29-4285-acb9-d19a0b16bcbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15611
74264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1561174264
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2301502068
Short name T1305
Test name
Test status
Simulation time 197034474 ps
CPU time 0.86 seconds
Started Jun 29 06:39:15 PM PDT 24
Finished Jun 29 06:39:17 PM PDT 24
Peak memory 206188 kb
Host smart-19700b3e-39ee-4118-853d-42995e234e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23015
02068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2301502068
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2239878973
Short name T1862
Test name
Test status
Simulation time 174198779 ps
CPU time 0.83 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206216 kb
Host smart-55dc294c-c27c-4e29-8702-aa3c2848f2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22398
78973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2239878973
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1318383160
Short name T1004
Test name
Test status
Simulation time 206189104 ps
CPU time 0.86 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:15 PM PDT 24
Peak memory 206216 kb
Host smart-de8ff021-c65f-43e8-8c50-35a92c936369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13183
83160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1318383160
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3963381378
Short name T2548
Test name
Test status
Simulation time 241518174 ps
CPU time 0.89 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:11 PM PDT 24
Peak memory 206200 kb
Host smart-3386b83e-3c92-486d-a1eb-7601ef56018c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39633
81378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3963381378
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1472911238
Short name T446
Test name
Test status
Simulation time 190941473 ps
CPU time 0.81 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206192 kb
Host smart-d27466f1-c8d0-4161-b5be-6e165929edfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14729
11238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1472911238
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.465598379
Short name T2008
Test name
Test status
Simulation time 152486147 ps
CPU time 0.82 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:11 PM PDT 24
Peak memory 206192 kb
Host smart-c7a2a976-8c9a-489e-97fe-e1b01ca15915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46559
8379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.465598379
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.179094854
Short name T706
Test name
Test status
Simulation time 191944138 ps
CPU time 0.85 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:13 PM PDT 24
Peak memory 206192 kb
Host smart-1ef5fea5-ae19-4ab4-b392-abe21c9d1b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17909
4854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.179094854
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1266089633
Short name T1544
Test name
Test status
Simulation time 238413112 ps
CPU time 0.99 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:14 PM PDT 24
Peak memory 206196 kb
Host smart-e6f04b63-70a2-4203-9f21-442b4dd3d520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12660
89633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1266089633
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3935113065
Short name T647
Test name
Test status
Simulation time 5017864102 ps
CPU time 44.11 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:57 PM PDT 24
Peak memory 206408 kb
Host smart-b60f50d5-a6ed-4731-9a0c-765943d4dcb2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3935113065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3935113065
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.668192505
Short name T974
Test name
Test status
Simulation time 193738929 ps
CPU time 0.85 seconds
Started Jun 29 06:39:07 PM PDT 24
Finished Jun 29 06:39:09 PM PDT 24
Peak memory 206220 kb
Host smart-fd52769d-56df-4f14-bcab-95350f687fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66819
2505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.668192505
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.4040041098
Short name T1672
Test name
Test status
Simulation time 188328371 ps
CPU time 0.82 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:13 PM PDT 24
Peak memory 206196 kb
Host smart-a6147450-d443-40ff-8ee7-c46c5967ea7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40400
41098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.4040041098
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2154469897
Short name T669
Test name
Test status
Simulation time 5197534319 ps
CPU time 149.12 seconds
Started Jun 29 06:39:09 PM PDT 24
Finished Jun 29 06:41:39 PM PDT 24
Peak memory 206440 kb
Host smart-f047026e-2347-4e63-a395-73d3f4df2a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21544
69897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2154469897
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1191192551
Short name T2591
Test name
Test status
Simulation time 61736916 ps
CPU time 0.7 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:15 PM PDT 24
Peak memory 206212 kb
Host smart-4340be65-5b09-4ab9-a2f6-0f6b3a25c557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1191192551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1191192551
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1091252036
Short name T2079
Test name
Test status
Simulation time 3792099171 ps
CPU time 5.25 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:19 PM PDT 24
Peak memory 206280 kb
Host smart-5a7f0242-3ac7-4cc9-a068-477a9a145a48
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1091252036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.1091252036
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2562724346
Short name T1165
Test name
Test status
Simulation time 13353210313 ps
CPU time 12.63 seconds
Started Jun 29 06:39:09 PM PDT 24
Finished Jun 29 06:39:22 PM PDT 24
Peak memory 206292 kb
Host smart-9451c3f9-7c12-48b1-a2cb-315586a1d2c7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2562724346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2562724346
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1832543975
Short name T2379
Test name
Test status
Simulation time 23421918071 ps
CPU time 24.08 seconds
Started Jun 29 06:39:08 PM PDT 24
Finished Jun 29 06:39:32 PM PDT 24
Peak memory 206328 kb
Host smart-c5136cac-371c-4963-adfc-c3b0db6bc9b2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1832543975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1832543975
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3834757617
Short name T1828
Test name
Test status
Simulation time 172356277 ps
CPU time 0.83 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:15 PM PDT 24
Peak memory 206196 kb
Host smart-981dd447-1ba6-4473-a984-6e1f0c635f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38347
57617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3834757617
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2565205693
Short name T1049
Test name
Test status
Simulation time 147442986 ps
CPU time 0.79 seconds
Started Jun 29 06:39:19 PM PDT 24
Finished Jun 29 06:39:20 PM PDT 24
Peak memory 206116 kb
Host smart-0c18120e-4243-426d-b939-bf514e5e695a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25652
05693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2565205693
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.184635433
Short name T1374
Test name
Test status
Simulation time 291734519 ps
CPU time 1.13 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:08 PM PDT 24
Peak memory 206200 kb
Host smart-79deac45-d5e1-4d11-860e-37e68910e00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18463
5433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.184635433
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.249580081
Short name T181
Test name
Test status
Simulation time 1217677184 ps
CPU time 2.91 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:17 PM PDT 24
Peak memory 206268 kb
Host smart-82940098-286d-4bd4-a1dc-8e9ab17c770a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24958
0081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.249580081
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.316134486
Short name T1905
Test name
Test status
Simulation time 17104357848 ps
CPU time 31.45 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:45 PM PDT 24
Peak memory 206420 kb
Host smart-5784e7a0-8086-41da-98c8-9a5e3201dbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31613
4486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.316134486
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3664524022
Short name T369
Test name
Test status
Simulation time 307718924 ps
CPU time 1.13 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:09 PM PDT 24
Peak memory 206208 kb
Host smart-95f3d3cf-f9c9-4bb0-8e11-e736ddd5198c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36645
24022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3664524022
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3741297915
Short name T1878
Test name
Test status
Simulation time 180468570 ps
CPU time 0.82 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:14 PM PDT 24
Peak memory 206172 kb
Host smart-d1d368b4-5ae2-4c7f-8be3-a7fd6c41cbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37412
97915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3741297915
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.23930298
Short name T2042
Test name
Test status
Simulation time 34452725 ps
CPU time 0.65 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206212 kb
Host smart-09528a7d-4358-46f4-b09f-2793649b40bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23930
298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.23930298
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.565120388
Short name T1239
Test name
Test status
Simulation time 1053528215 ps
CPU time 2.45 seconds
Started Jun 29 06:39:07 PM PDT 24
Finished Jun 29 06:39:10 PM PDT 24
Peak memory 206296 kb
Host smart-293cd9eb-da42-49d0-94a2-502f9330fd1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56512
0388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.565120388
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1509270049
Short name T1938
Test name
Test status
Simulation time 237350309 ps
CPU time 1.3 seconds
Started Jun 29 06:39:22 PM PDT 24
Finished Jun 29 06:39:24 PM PDT 24
Peak memory 206332 kb
Host smart-dc52d4e2-7307-4302-ad0b-a9a9367faa14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15092
70049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1509270049
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1539151054
Short name T644
Test name
Test status
Simulation time 207463238 ps
CPU time 0.83 seconds
Started Jun 29 06:39:06 PM PDT 24
Finished Jun 29 06:39:07 PM PDT 24
Peak memory 206180 kb
Host smart-e14e19f9-28b5-441a-8592-5d663c5be91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15391
51054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1539151054
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2961513527
Short name T34
Test name
Test status
Simulation time 142159064 ps
CPU time 0.79 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:13 PM PDT 24
Peak memory 206216 kb
Host smart-2b03fc7a-42aa-4170-8a9a-92982d912886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29615
13527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2961513527
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1348790122
Short name T1293
Test name
Test status
Simulation time 172175444 ps
CPU time 0.84 seconds
Started Jun 29 06:39:19 PM PDT 24
Finished Jun 29 06:39:20 PM PDT 24
Peak memory 206212 kb
Host smart-727aa8a9-ac8b-4df5-8762-31065aaa3ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13487
90122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1348790122
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.2548972137
Short name T890
Test name
Test status
Simulation time 7623336303 ps
CPU time 52.34 seconds
Started Jun 29 06:39:07 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206476 kb
Host smart-3f7863ff-aa1d-46bd-aa66-ce640cdbbb26
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2548972137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.2548972137
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2939211865
Short name T1922
Test name
Test status
Simulation time 214611389 ps
CPU time 0.86 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:12 PM PDT 24
Peak memory 206188 kb
Host smart-5182b587-5c14-44b0-b413-a988bca12aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29392
11865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2939211865
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.439963202
Short name T959
Test name
Test status
Simulation time 23334021113 ps
CPU time 21.63 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:33 PM PDT 24
Peak memory 206312 kb
Host smart-3f4ae00b-b1c7-4130-be73-843df9ce2be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43996
3202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.439963202
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1932955978
Short name T1768
Test name
Test status
Simulation time 3345237035 ps
CPU time 3.88 seconds
Started Jun 29 06:39:04 PM PDT 24
Finished Jun 29 06:39:09 PM PDT 24
Peak memory 206232 kb
Host smart-78719b48-1aa4-4e0d-b9f2-dacba8a7e95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19329
55978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1932955978
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2974893012
Short name T2616
Test name
Test status
Simulation time 8378945110 ps
CPU time 221.12 seconds
Started Jun 29 06:39:07 PM PDT 24
Finished Jun 29 06:42:49 PM PDT 24
Peak memory 206436 kb
Host smart-3111ec36-688c-466c-9bc8-4c7a05f928b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29748
93012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2974893012
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.2304064173
Short name T1008
Test name
Test status
Simulation time 4944367871 ps
CPU time 48.05 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206416 kb
Host smart-32947dc4-db95-4daa-a45e-4b79b56b19c7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2304064173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.2304064173
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.41087345
Short name T1741
Test name
Test status
Simulation time 249922358 ps
CPU time 1 seconds
Started Jun 29 06:39:20 PM PDT 24
Finished Jun 29 06:39:21 PM PDT 24
Peak memory 206120 kb
Host smart-a0fb8811-b0d1-4b99-bf95-1f11195a71eb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=41087345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.41087345
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2033789952
Short name T732
Test name
Test status
Simulation time 191334005 ps
CPU time 0.89 seconds
Started Jun 29 06:39:19 PM PDT 24
Finished Jun 29 06:39:20 PM PDT 24
Peak memory 206136 kb
Host smart-6f89baf9-13b4-4944-9ad8-dc3f1ca0c0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20337
89952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2033789952
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.2618509337
Short name T2303
Test name
Test status
Simulation time 3936273846 ps
CPU time 29.48 seconds
Started Jun 29 06:39:33 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206464 kb
Host smart-b930b738-1e7d-4df4-af08-3185262c8380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26185
09337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.2618509337
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.923802309
Short name T1137
Test name
Test status
Simulation time 7131733046 ps
CPU time 52.17 seconds
Started Jun 29 06:39:33 PM PDT 24
Finished Jun 29 06:40:26 PM PDT 24
Peak memory 206420 kb
Host smart-9431ee76-b70b-431a-b7a7-ab423f5e9fa8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=923802309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.923802309
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3717197361
Short name T1410
Test name
Test status
Simulation time 200732290 ps
CPU time 0.85 seconds
Started Jun 29 06:39:38 PM PDT 24
Finished Jun 29 06:39:40 PM PDT 24
Peak memory 206196 kb
Host smart-4c37135c-b12d-4d76-86b9-d74a648e564d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3717197361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3717197361
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2953096104
Short name T828
Test name
Test status
Simulation time 147942650 ps
CPU time 0.84 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206204 kb
Host smart-9ef6244c-7131-4b3e-9c37-389fe533c915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29530
96104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2953096104
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.827755829
Short name T129
Test name
Test status
Simulation time 225843205 ps
CPU time 0.84 seconds
Started Jun 29 06:39:17 PM PDT 24
Finished Jun 29 06:39:18 PM PDT 24
Peak memory 206216 kb
Host smart-b453dfcb-e7bd-44c4-93c9-66969903ea26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82775
5829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.827755829
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2834060465
Short name T2338
Test name
Test status
Simulation time 162487090 ps
CPU time 0.78 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:14 PM PDT 24
Peak memory 206200 kb
Host smart-a7e46177-8a31-4c3e-a7ad-97d80dd56f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28340
60465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2834060465
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3052784546
Short name T2256
Test name
Test status
Simulation time 146874181 ps
CPU time 0.8 seconds
Started Jun 29 06:39:47 PM PDT 24
Finished Jun 29 06:39:50 PM PDT 24
Peak memory 206196 kb
Host smart-42b6ab5c-6428-408c-8d48-6cbd0806f469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30527
84546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3052784546
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1655280711
Short name T2405
Test name
Test status
Simulation time 182665437 ps
CPU time 0.8 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206160 kb
Host smart-2a32c06d-ed8c-4528-a65d-f2bf27eac5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16552
80711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1655280711
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1366087523
Short name T33
Test name
Test status
Simulation time 154111447 ps
CPU time 0.75 seconds
Started Jun 29 06:39:27 PM PDT 24
Finished Jun 29 06:39:28 PM PDT 24
Peak memory 206200 kb
Host smart-da015643-c6d9-4433-bc7c-21946ddaf9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13660
87523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1366087523
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.895769217
Short name T1671
Test name
Test status
Simulation time 208093590 ps
CPU time 0.93 seconds
Started Jun 29 06:39:32 PM PDT 24
Finished Jun 29 06:39:34 PM PDT 24
Peak memory 206176 kb
Host smart-612d2f1c-26ea-4379-a28d-8f2392b4b329
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=895769217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.895769217
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1287615773
Short name T2585
Test name
Test status
Simulation time 190455013 ps
CPU time 0.76 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:12 PM PDT 24
Peak memory 206212 kb
Host smart-fa790a3b-eacc-4140-aeb6-053be7fb078d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12876
15773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1287615773
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1273247215
Short name T1930
Test name
Test status
Simulation time 39792728 ps
CPU time 0.66 seconds
Started Jun 29 06:39:30 PM PDT 24
Finished Jun 29 06:39:32 PM PDT 24
Peak memory 206212 kb
Host smart-f94a78be-8325-4f3b-aee7-2bae3ab8f24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732
47215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1273247215
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3396581220
Short name T1021
Test name
Test status
Simulation time 19140351440 ps
CPU time 44.65 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206432 kb
Host smart-d9e1670a-3ae8-458d-ba1a-c4b60f963825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33965
81220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3396581220
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3414273130
Short name T2540
Test name
Test status
Simulation time 177396386 ps
CPU time 0.83 seconds
Started Jun 29 06:39:50 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206196 kb
Host smart-ddcc60f5-19d3-4ea4-a29e-c792b323907f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34142
73130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3414273130
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.816982945
Short name T1469
Test name
Test status
Simulation time 239916639 ps
CPU time 0.98 seconds
Started Jun 29 06:39:13 PM PDT 24
Finished Jun 29 06:39:15 PM PDT 24
Peak memory 206212 kb
Host smart-1de60e41-ec3c-44bb-a3f9-abf454923143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81698
2945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.816982945
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2230222474
Short name T315
Test name
Test status
Simulation time 184144021 ps
CPU time 0.82 seconds
Started Jun 29 06:39:44 PM PDT 24
Finished Jun 29 06:39:46 PM PDT 24
Peak memory 206164 kb
Host smart-20d871b4-a89e-4fc6-a29b-5db1097c1d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22302
22474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2230222474
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.2812177626
Short name T384
Test name
Test status
Simulation time 148457482 ps
CPU time 0.8 seconds
Started Jun 29 06:39:10 PM PDT 24
Finished Jun 29 06:39:12 PM PDT 24
Peak memory 206200 kb
Host smart-dc7de64b-8dec-42cd-82f6-33429598c66c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28121
77626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.2812177626
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2441557467
Short name T783
Test name
Test status
Simulation time 193172257 ps
CPU time 0.81 seconds
Started Jun 29 06:39:41 PM PDT 24
Finished Jun 29 06:39:43 PM PDT 24
Peak memory 206192 kb
Host smart-318a9c29-f50a-46df-8a6c-74e237734f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24415
57467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2441557467
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.490447669
Short name T24
Test name
Test status
Simulation time 193546310 ps
CPU time 0.87 seconds
Started Jun 29 06:39:30 PM PDT 24
Finished Jun 29 06:39:31 PM PDT 24
Peak memory 206196 kb
Host smart-4511fe5e-e511-41ab-9ce6-f838e47a8eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49044
7669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.490447669
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.602855664
Short name T866
Test name
Test status
Simulation time 151226924 ps
CPU time 0.75 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206192 kb
Host smart-a9fff464-29cf-409d-a2fc-172b8a603dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60285
5664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.602855664
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2922290125
Short name T1940
Test name
Test status
Simulation time 290416741 ps
CPU time 0.99 seconds
Started Jun 29 06:39:34 PM PDT 24
Finished Jun 29 06:39:35 PM PDT 24
Peak memory 206216 kb
Host smart-8de66797-dbb4-47cc-bcfc-89275abcd449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29222
90125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2922290125
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2146769067
Short name T2102
Test name
Test status
Simulation time 3857092682 ps
CPU time 27.84 seconds
Started Jun 29 06:39:11 PM PDT 24
Finished Jun 29 06:39:40 PM PDT 24
Peak memory 206428 kb
Host smart-be124f94-d94e-4a8b-b48e-be6937c1a89b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2146769067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2146769067
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1063357323
Short name T2493
Test name
Test status
Simulation time 168680447 ps
CPU time 0.82 seconds
Started Jun 29 06:39:33 PM PDT 24
Finished Jun 29 06:39:34 PM PDT 24
Peak memory 206224 kb
Host smart-dbd0d3f4-8182-4edb-bff1-a1a816cbad9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10633
57323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1063357323
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2101333585
Short name T1355
Test name
Test status
Simulation time 172094709 ps
CPU time 0.8 seconds
Started Jun 29 06:39:16 PM PDT 24
Finished Jun 29 06:39:17 PM PDT 24
Peak memory 206172 kb
Host smart-aa6a2c14-28dd-4f23-90bc-6ab2ffaf9178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21013
33585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2101333585
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.421602941
Short name T1120
Test name
Test status
Simulation time 5998742614 ps
CPU time 161.95 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:42:41 PM PDT 24
Peak memory 206440 kb
Host smart-419c2bef-6d9f-444a-af98-7b4a01357ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42160
2941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.421602941
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.4006121552
Short name T1155
Test name
Test status
Simulation time 60283508 ps
CPU time 0.72 seconds
Started Jun 29 06:39:27 PM PDT 24
Finished Jun 29 06:39:28 PM PDT 24
Peak memory 206176 kb
Host smart-1b2c86bd-e6a1-4a08-b77a-f81d58f73c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4006121552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.4006121552
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3878493753
Short name T814
Test name
Test status
Simulation time 4149574511 ps
CPU time 5.43 seconds
Started Jun 29 06:39:15 PM PDT 24
Finished Jun 29 06:39:21 PM PDT 24
Peak memory 206396 kb
Host smart-52f6fbf4-e298-4073-bccf-278416f50266
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3878493753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.3878493753
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1838773672
Short name T716
Test name
Test status
Simulation time 13358405218 ps
CPU time 14.38 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:39:29 PM PDT 24
Peak memory 206252 kb
Host smart-f708669c-63d1-4332-b149-364430f9de38
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1838773672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1838773672
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1707576070
Short name T2232
Test name
Test status
Simulation time 23421828338 ps
CPU time 23.05 seconds
Started Jun 29 06:39:12 PM PDT 24
Finished Jun 29 06:39:36 PM PDT 24
Peak memory 206328 kb
Host smart-de9a93c3-7ba7-4e71-afee-a535373a8056
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1707576070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.1707576070
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3566867187
Short name T2280
Test name
Test status
Simulation time 247280697 ps
CPU time 0.97 seconds
Started Jun 29 06:39:39 PM PDT 24
Finished Jun 29 06:39:40 PM PDT 24
Peak memory 206196 kb
Host smart-5a7875b4-fcb2-4dd5-b531-5505f4f4766d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35668
67187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3566867187
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1546207186
Short name T2343
Test name
Test status
Simulation time 147554750 ps
CPU time 0.81 seconds
Started Jun 29 06:39:32 PM PDT 24
Finished Jun 29 06:39:33 PM PDT 24
Peak memory 206196 kb
Host smart-ea0e3255-f6c8-49e1-a0ee-0a6905f017e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15462
07186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1546207186
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.1360866932
Short name T2429
Test name
Test status
Simulation time 429857500 ps
CPU time 1.4 seconds
Started Jun 29 06:39:34 PM PDT 24
Finished Jun 29 06:39:36 PM PDT 24
Peak memory 206192 kb
Host smart-0a93744d-abe5-4d93-b3d4-cc2ea2932fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13608
66932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.1360866932
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_device_address.4155227641
Short name T1629
Test name
Test status
Simulation time 14442088193 ps
CPU time 27.36 seconds
Started Jun 29 06:39:38 PM PDT 24
Finished Jun 29 06:40:06 PM PDT 24
Peak memory 206572 kb
Host smart-8e8e7e1b-5bdb-46db-873f-ac33f7242e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41552
27641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.4155227641
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1009311241
Short name T970
Test name
Test status
Simulation time 355563151 ps
CPU time 1.15 seconds
Started Jun 29 06:39:37 PM PDT 24
Finished Jun 29 06:39:39 PM PDT 24
Peak memory 206212 kb
Host smart-487ad873-c287-4b42-903a-a06b1209ac9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
11241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1009311241
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3323633785
Short name T2034
Test name
Test status
Simulation time 141055501 ps
CPU time 0.78 seconds
Started Jun 29 06:39:31 PM PDT 24
Finished Jun 29 06:39:33 PM PDT 24
Peak memory 206192 kb
Host smart-0c0b24f3-6f39-46e0-b035-688b8d9665d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33236
33785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3323633785
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.2421065649
Short name T314
Test name
Test status
Simulation time 65923958 ps
CPU time 0.74 seconds
Started Jun 29 06:39:37 PM PDT 24
Finished Jun 29 06:39:38 PM PDT 24
Peak memory 206192 kb
Host smart-b2960b8c-5049-4936-88dd-7fb348476708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24210
65649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2421065649
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.461821579
Short name T382
Test name
Test status
Simulation time 803140676 ps
CPU time 1.82 seconds
Started Jun 29 06:39:38 PM PDT 24
Finished Jun 29 06:39:41 PM PDT 24
Peak memory 206284 kb
Host smart-b857d4f4-cfc1-4352-b156-ca5befe613e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46182
1579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.461821579
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.4200852214
Short name T1982
Test name
Test status
Simulation time 385997949 ps
CPU time 2.32 seconds
Started Jun 29 06:39:16 PM PDT 24
Finished Jun 29 06:39:19 PM PDT 24
Peak memory 206372 kb
Host smart-027d6627-0d5f-419e-ab39-1976926c276e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42008
52214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.4200852214
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2831042940
Short name T1066
Test name
Test status
Simulation time 198081783 ps
CPU time 0.83 seconds
Started Jun 29 06:39:37 PM PDT 24
Finished Jun 29 06:39:38 PM PDT 24
Peak memory 206208 kb
Host smart-24698689-63aa-4194-82f3-0e5c8c57d200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28310
42940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2831042940
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2595390934
Short name T1269
Test name
Test status
Simulation time 152971998 ps
CPU time 0.77 seconds
Started Jun 29 06:39:17 PM PDT 24
Finished Jun 29 06:39:18 PM PDT 24
Peak memory 206208 kb
Host smart-12d56454-7957-4fb6-85de-9c20b17e41b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25953
90934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2595390934
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3374806058
Short name T741
Test name
Test status
Simulation time 210579915 ps
CPU time 0.94 seconds
Started Jun 29 06:39:18 PM PDT 24
Finished Jun 29 06:39:19 PM PDT 24
Peak memory 206184 kb
Host smart-36fdddb3-5b45-4c03-8a6f-0970a5af2e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33748
06058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3374806058
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.2694151081
Short name T908
Test name
Test status
Simulation time 6009950225 ps
CPU time 47.72 seconds
Started Jun 29 06:39:40 PM PDT 24
Finished Jun 29 06:40:28 PM PDT 24
Peak memory 206396 kb
Host smart-bcaa38b5-e5d4-4cbf-a22b-9bbaffb2288e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2694151081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.2694151081
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2077538569
Short name T2398
Test name
Test status
Simulation time 215060062 ps
CPU time 0.98 seconds
Started Jun 29 06:39:18 PM PDT 24
Finished Jun 29 06:39:19 PM PDT 24
Peak memory 206160 kb
Host smart-55c4cd7a-f7f0-4ff5-a26a-a92320c941d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20775
38569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2077538569
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.370307092
Short name T633
Test name
Test status
Simulation time 23340849991 ps
CPU time 28.16 seconds
Started Jun 29 06:39:44 PM PDT 24
Finished Jun 29 06:40:14 PM PDT 24
Peak memory 206324 kb
Host smart-694499d1-63d9-4d6e-a6cb-b6d34cd9f791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37030
7092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.370307092
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3606073353
Short name T1270
Test name
Test status
Simulation time 3347271665 ps
CPU time 4.51 seconds
Started Jun 29 06:39:40 PM PDT 24
Finished Jun 29 06:39:45 PM PDT 24
Peak memory 206256 kb
Host smart-a76931e8-bf55-417d-a6bd-b908ec8ab85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36060
73353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3606073353
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3754326034
Short name T1537
Test name
Test status
Simulation time 7150667324 ps
CPU time 54.97 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:40:43 PM PDT 24
Peak memory 206420 kb
Host smart-ae36d4c5-7b5c-4e2b-82b1-9b5eab7bc0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37543
26034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3754326034
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.4114866120
Short name T1933
Test name
Test status
Simulation time 4702077344 ps
CPU time 35.07 seconds
Started Jun 29 06:39:38 PM PDT 24
Finished Jun 29 06:40:13 PM PDT 24
Peak memory 206460 kb
Host smart-cba8fc78-cc01-4bcc-a039-7878a25c373e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4114866120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.4114866120
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.1160463115
Short name T2427
Test name
Test status
Simulation time 292632490 ps
CPU time 0.94 seconds
Started Jun 29 06:39:16 PM PDT 24
Finished Jun 29 06:39:18 PM PDT 24
Peak memory 206220 kb
Host smart-4b907a54-512a-4091-95db-d820a3d4a4c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1160463115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.1160463115
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1848447277
Short name T509
Test name
Test status
Simulation time 200459661 ps
CPU time 0.86 seconds
Started Jun 29 06:39:14 PM PDT 24
Finished Jun 29 06:39:16 PM PDT 24
Peak memory 206216 kb
Host smart-55a1e0ae-4ce6-477e-bbe6-62ea28b2e153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18484
47277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1848447277
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.3533475032
Short name T1287
Test name
Test status
Simulation time 3034910574 ps
CPU time 21.51 seconds
Started Jun 29 06:39:17 PM PDT 24
Finished Jun 29 06:39:39 PM PDT 24
Peak memory 206392 kb
Host smart-ddacd929-d5f9-476f-9bd1-30aa9fa370b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35334
75032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.3533475032
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.2957919367
Short name T2415
Test name
Test status
Simulation time 4469235343 ps
CPU time 41.07 seconds
Started Jun 29 06:39:17 PM PDT 24
Finished Jun 29 06:39:59 PM PDT 24
Peak memory 206484 kb
Host smart-c0293ca2-1533-44c1-a2b7-4f9e15005a0d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2957919367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.2957919367
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2742179797
Short name T2572
Test name
Test status
Simulation time 169057396 ps
CPU time 0.84 seconds
Started Jun 29 06:39:17 PM PDT 24
Finished Jun 29 06:39:18 PM PDT 24
Peak memory 206220 kb
Host smart-638d817d-b608-486c-924a-20b14a2845f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2742179797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2742179797
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.4103822354
Short name T1447
Test name
Test status
Simulation time 148211330 ps
CPU time 0.79 seconds
Started Jun 29 06:39:50 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206216 kb
Host smart-bf242758-242e-4861-a9e2-b0ebfce031d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41038
22354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.4103822354
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1127802736
Short name T2628
Test name
Test status
Simulation time 188666614 ps
CPU time 0.87 seconds
Started Jun 29 06:39:40 PM PDT 24
Finished Jun 29 06:39:41 PM PDT 24
Peak memory 206196 kb
Host smart-b4f22611-e2ca-46eb-a383-2c49f93d7f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11278
02736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1127802736
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.633922005
Short name T1071
Test name
Test status
Simulation time 167389050 ps
CPU time 0.81 seconds
Started Jun 29 06:39:28 PM PDT 24
Finished Jun 29 06:39:30 PM PDT 24
Peak memory 206100 kb
Host smart-528ec6a9-f3d6-4ecf-b454-e16cb53a2b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63392
2005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.633922005
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.744451828
Short name T1579
Test name
Test status
Simulation time 160478189 ps
CPU time 0.79 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:49 PM PDT 24
Peak memory 206216 kb
Host smart-cc45c031-e1ac-4c08-bdb0-7a5273cbfc9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74445
1828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.744451828
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3575523009
Short name T1103
Test name
Test status
Simulation time 234689643 ps
CPU time 0.87 seconds
Started Jun 29 06:39:34 PM PDT 24
Finished Jun 29 06:39:35 PM PDT 24
Peak memory 206196 kb
Host smart-01f4973f-06b7-41e5-ac52-fac8334fb637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35755
23009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3575523009
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3866411677
Short name T1557
Test name
Test status
Simulation time 156033113 ps
CPU time 0.81 seconds
Started Jun 29 06:39:37 PM PDT 24
Finished Jun 29 06:39:38 PM PDT 24
Peak memory 206164 kb
Host smart-1c2f7d72-8f69-4002-b8f5-aaebb775aab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38664
11677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3866411677
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.541413627
Short name T1441
Test name
Test status
Simulation time 185874541 ps
CPU time 0.88 seconds
Started Jun 29 06:39:35 PM PDT 24
Finished Jun 29 06:39:36 PM PDT 24
Peak memory 206212 kb
Host smart-f4d2639e-cf8f-4067-ab33-ac7d44d014cc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=541413627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.541413627
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1392661726
Short name T2085
Test name
Test status
Simulation time 145716921 ps
CPU time 0.75 seconds
Started Jun 29 06:39:34 PM PDT 24
Finished Jun 29 06:39:35 PM PDT 24
Peak memory 206212 kb
Host smart-86a28859-c7a0-4493-aa22-8ba97c3729a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13926
61726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1392661726
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1056587074
Short name T2245
Test name
Test status
Simulation time 51724857 ps
CPU time 0.66 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206212 kb
Host smart-0254987b-63b3-4c13-a761-dc39789a1fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10565
87074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1056587074
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1078791997
Short name T1524
Test name
Test status
Simulation time 8313525924 ps
CPU time 20.16 seconds
Started Jun 29 06:39:44 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206460 kb
Host smart-fb5ed62e-e81b-4219-8a32-f807c518db17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10787
91997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1078791997
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2718030869
Short name T368
Test name
Test status
Simulation time 174633182 ps
CPU time 0.86 seconds
Started Jun 29 06:39:28 PM PDT 24
Finished Jun 29 06:39:30 PM PDT 24
Peak memory 206068 kb
Host smart-9053a27e-0889-4dfc-ad8e-2e14217ebddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27180
30869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2718030869
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3815814591
Short name T2017
Test name
Test status
Simulation time 227954626 ps
CPU time 0.9 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:39:44 PM PDT 24
Peak memory 206208 kb
Host smart-0260ecd5-ee9f-4092-8097-452cbed14002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38158
14591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3815814591
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3607372308
Short name T688
Test name
Test status
Simulation time 254015425 ps
CPU time 0.85 seconds
Started Jun 29 06:39:49 PM PDT 24
Finished Jun 29 06:39:51 PM PDT 24
Peak memory 206216 kb
Host smart-c4ed05aa-cd98-49fc-a257-c7da455e9fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36073
72308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3607372308
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2374189670
Short name T2474
Test name
Test status
Simulation time 216230627 ps
CPU time 0.9 seconds
Started Jun 29 06:39:36 PM PDT 24
Finished Jun 29 06:39:38 PM PDT 24
Peak memory 206200 kb
Host smart-37b724da-8e55-48d6-9932-f62d523a6db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23741
89670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2374189670
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2857288249
Short name T1145
Test name
Test status
Simulation time 137830903 ps
CPU time 0.77 seconds
Started Jun 29 06:39:43 PM PDT 24
Finished Jun 29 06:39:46 PM PDT 24
Peak memory 206196 kb
Host smart-9fce7a8b-c1f8-448b-bc83-4588677941f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28572
88249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2857288249
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3483282879
Short name T1330
Test name
Test status
Simulation time 175518700 ps
CPU time 0.79 seconds
Started Jun 29 06:39:35 PM PDT 24
Finished Jun 29 06:39:36 PM PDT 24
Peak memory 206180 kb
Host smart-0f39ec80-aaa6-4a46-a9fa-ae71279273e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34832
82879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3483282879
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.683247295
Short name T1369
Test name
Test status
Simulation time 192352819 ps
CPU time 0.79 seconds
Started Jun 29 06:39:48 PM PDT 24
Finished Jun 29 06:39:50 PM PDT 24
Peak memory 206184 kb
Host smart-95b03d04-f29c-43bc-b251-211fea777773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68324
7295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.683247295
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1016535085
Short name T595
Test name
Test status
Simulation time 202407620 ps
CPU time 0.92 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206216 kb
Host smart-cc70f51a-f7fd-4940-bf79-123a9d59b22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10165
35085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1016535085
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2238891022
Short name T4
Test name
Test status
Simulation time 4165504558 ps
CPU time 31.18 seconds
Started Jun 29 06:39:32 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206404 kb
Host smart-f8acb9a7-9457-40b0-96fd-31644ae62c03
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2238891022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2238891022
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1552170487
Short name T1017
Test name
Test status
Simulation time 176793060 ps
CPU time 0.82 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:39:44 PM PDT 24
Peak memory 206228 kb
Host smart-b7876c20-e8f7-4409-abb1-1678322ecb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15521
70487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1552170487
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.769451028
Short name T31
Test name
Test status
Simulation time 163917932 ps
CPU time 0.78 seconds
Started Jun 29 06:39:28 PM PDT 24
Finished Jun 29 06:39:29 PM PDT 24
Peak memory 206196 kb
Host smart-7cdd9a3a-7188-4016-9c62-3d14ec337108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76945
1028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.769451028
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1063656120
Short name T399
Test name
Test status
Simulation time 5477768597 ps
CPU time 150.38 seconds
Started Jun 29 06:39:38 PM PDT 24
Finished Jun 29 06:42:15 PM PDT 24
Peak memory 206440 kb
Host smart-4d91be83-e8dd-4851-97ba-1108cea22754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10636
56120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1063656120
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.4068919559
Short name T430
Test name
Test status
Simulation time 53187023 ps
CPU time 0.67 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206212 kb
Host smart-1478b2cc-019a-4658-aea9-f55925d1e850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4068919559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.4068919559
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3025957219
Short name T2203
Test name
Test status
Simulation time 3804803854 ps
CPU time 4.64 seconds
Started Jun 29 06:39:41 PM PDT 24
Finished Jun 29 06:39:47 PM PDT 24
Peak memory 206384 kb
Host smart-e2964c66-2b8c-480e-82cb-96150e0d14dc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3025957219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3025957219
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.195867302
Short name T1265
Test name
Test status
Simulation time 23305484847 ps
CPU time 23.12 seconds
Started Jun 29 06:39:41 PM PDT 24
Finished Jun 29 06:40:04 PM PDT 24
Peak memory 206584 kb
Host smart-2f43daca-d118-4d7b-847c-85b594016c85
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=195867302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.195867302
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3940693966
Short name T1870
Test name
Test status
Simulation time 151599888 ps
CPU time 0.83 seconds
Started Jun 29 06:39:35 PM PDT 24
Finished Jun 29 06:39:36 PM PDT 24
Peak memory 206196 kb
Host smart-bf2e1392-bba7-4246-928e-c86e58de9dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39406
93966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3940693966
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3484701685
Short name T891
Test name
Test status
Simulation time 165580005 ps
CPU time 0.82 seconds
Started Jun 29 06:39:45 PM PDT 24
Finished Jun 29 06:39:47 PM PDT 24
Peak memory 206196 kb
Host smart-eb257275-fe27-40d5-a7fe-918461d33b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34847
01685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3484701685
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.4251525603
Short name T2228
Test name
Test status
Simulation time 195541228 ps
CPU time 0.85 seconds
Started Jun 29 06:39:41 PM PDT 24
Finished Jun 29 06:39:43 PM PDT 24
Peak memory 206188 kb
Host smart-42111bad-263b-4841-ba22-dce3e4b3f537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42515
25603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.4251525603
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.632788661
Short name T1085
Test name
Test status
Simulation time 481112908 ps
CPU time 1.33 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:39:44 PM PDT 24
Peak memory 206168 kb
Host smart-153369da-5a76-429f-9025-7302e588dc56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63278
8661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.632788661
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1900363649
Short name T655
Test name
Test status
Simulation time 18479443752 ps
CPU time 34.68 seconds
Started Jun 29 06:39:34 PM PDT 24
Finished Jun 29 06:40:09 PM PDT 24
Peak memory 206412 kb
Host smart-089e8bbb-f0f7-48cc-8c7f-851f2e20cd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19003
63649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1900363649
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.1201357197
Short name T2615
Test name
Test status
Simulation time 397200070 ps
CPU time 1.28 seconds
Started Jun 29 06:39:43 PM PDT 24
Finished Jun 29 06:39:46 PM PDT 24
Peak memory 206220 kb
Host smart-b289beee-10e1-49b2-9a82-efbf040a3bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12013
57197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.1201357197
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.1864038952
Short name T542
Test name
Test status
Simulation time 141061597 ps
CPU time 0.77 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:39:44 PM PDT 24
Peak memory 206196 kb
Host smart-fea79d45-a03c-47b1-a01e-6c0f3cf9788a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18640
38952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.1864038952
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.212269510
Short name T1106
Test name
Test status
Simulation time 50246738 ps
CPU time 0.67 seconds
Started Jun 29 06:39:41 PM PDT 24
Finished Jun 29 06:39:43 PM PDT 24
Peak memory 206204 kb
Host smart-88236baf-0a21-42bf-b0bc-447609da621d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21226
9510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.212269510
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1967844329
Short name T229
Test name
Test status
Simulation time 848035836 ps
CPU time 2.07 seconds
Started Jun 29 06:39:32 PM PDT 24
Finished Jun 29 06:39:34 PM PDT 24
Peak memory 206312 kb
Host smart-c9bc278e-5a35-463c-a8c0-be84b51afa7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19678
44329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1967844329
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3914883287
Short name T1479
Test name
Test status
Simulation time 291486789 ps
CPU time 2.12 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:39:45 PM PDT 24
Peak memory 206360 kb
Host smart-b5dfaa94-71f0-4695-85e8-baaa6a83c0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148
83287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3914883287
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3617607952
Short name T2043
Test name
Test status
Simulation time 225572631 ps
CPU time 0.89 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:49 PM PDT 24
Peak memory 206224 kb
Host smart-52ebf12a-c847-45ff-89c9-ad3b2be56a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36176
07952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3617607952
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2378728
Short name T1212
Test name
Test status
Simulation time 143478623 ps
CPU time 0.77 seconds
Started Jun 29 06:39:43 PM PDT 24
Finished Jun 29 06:39:46 PM PDT 24
Peak memory 206212 kb
Host smart-759da252-e81a-460b-b23f-be9c168fee72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23787
28 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2378728
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2757662093
Short name T1248
Test name
Test status
Simulation time 282717974 ps
CPU time 0.98 seconds
Started Jun 29 06:39:44 PM PDT 24
Finished Jun 29 06:39:47 PM PDT 24
Peak memory 206216 kb
Host smart-e400a456-3deb-4d15-9ba5-ec11b74e8e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27576
62093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2757662093
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1878722097
Short name T2556
Test name
Test status
Simulation time 237649981 ps
CPU time 0.92 seconds
Started Jun 29 06:39:41 PM PDT 24
Finished Jun 29 06:39:42 PM PDT 24
Peak memory 206172 kb
Host smart-0f1e5234-c810-4632-be43-2a7993711c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18787
22097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1878722097
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.2113539627
Short name T823
Test name
Test status
Simulation time 23337545480 ps
CPU time 23.41 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206320 kb
Host smart-c3a0c09e-6399-48e5-972b-429abf7c5dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21135
39627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2113539627
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3501562254
Short name T1341
Test name
Test status
Simulation time 3299183295 ps
CPU time 4.05 seconds
Started Jun 29 06:39:50 PM PDT 24
Finished Jun 29 06:39:55 PM PDT 24
Peak memory 206204 kb
Host smart-35218fec-9565-4d87-8e5c-47218f3cdc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35015
62254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3501562254
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.529612781
Short name T1272
Test name
Test status
Simulation time 9794429563 ps
CPU time 70.74 seconds
Started Jun 29 06:39:49 PM PDT 24
Finished Jun 29 06:41:01 PM PDT 24
Peak memory 206472 kb
Host smart-97d3c483-f17a-4ea4-ab94-56321e98924c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52961
2781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.529612781
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.2613430798
Short name T1157
Test name
Test status
Simulation time 5342197142 ps
CPU time 150.49 seconds
Started Jun 29 06:39:43 PM PDT 24
Finished Jun 29 06:42:16 PM PDT 24
Peak memory 206444 kb
Host smart-3c2e1357-a43c-47b0-b77a-f85d94be5dd8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2613430798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.2613430798
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.1716828211
Short name T421
Test name
Test status
Simulation time 264630043 ps
CPU time 0.9 seconds
Started Jun 29 06:39:39 PM PDT 24
Finished Jun 29 06:39:40 PM PDT 24
Peak memory 206220 kb
Host smart-8f6ebc1a-70d6-4b4a-882e-a9a63e5b3195
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1716828211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1716828211
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2847612834
Short name T1295
Test name
Test status
Simulation time 234320997 ps
CPU time 0.91 seconds
Started Jun 29 06:39:37 PM PDT 24
Finished Jun 29 06:39:38 PM PDT 24
Peak memory 206192 kb
Host smart-7dbf0142-ffb5-4281-8b1f-a81ceff75c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28476
12834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2847612834
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1126047341
Short name T1443
Test name
Test status
Simulation time 5897220142 ps
CPU time 163.65 seconds
Started Jun 29 06:39:40 PM PDT 24
Finished Jun 29 06:42:24 PM PDT 24
Peak memory 206464 kb
Host smart-7eed6a58-4b0a-4abb-a32e-70cedfd408a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11260
47341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1126047341
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.3319683072
Short name T527
Test name
Test status
Simulation time 7430423861 ps
CPU time 211.66 seconds
Started Jun 29 06:39:39 PM PDT 24
Finished Jun 29 06:43:11 PM PDT 24
Peak memory 206460 kb
Host smart-29ea2ae7-b244-4134-baec-3b0f8a2c0cb2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3319683072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.3319683072
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2386350755
Short name T29
Test name
Test status
Simulation time 164320526 ps
CPU time 0.9 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:39:44 PM PDT 24
Peak memory 206220 kb
Host smart-19d67372-c933-4b63-9d42-842124931cc6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2386350755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2386350755
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3921123899
Short name T331
Test name
Test status
Simulation time 148231809 ps
CPU time 0.83 seconds
Started Jun 29 06:39:45 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206216 kb
Host smart-5f0ce83b-8eae-4fdb-b969-a4de915ecc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39211
23899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3921123899
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1092746502
Short name T2536
Test name
Test status
Simulation time 204337586 ps
CPU time 0.88 seconds
Started Jun 29 06:39:47 PM PDT 24
Finished Jun 29 06:39:50 PM PDT 24
Peak memory 206196 kb
Host smart-15084c38-1e84-4e42-9512-8a875d5d78d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10927
46502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1092746502
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3641325293
Short name T2082
Test name
Test status
Simulation time 195447480 ps
CPU time 0.88 seconds
Started Jun 29 06:39:44 PM PDT 24
Finished Jun 29 06:39:46 PM PDT 24
Peak memory 206180 kb
Host smart-2ce0e578-2486-4d18-90e8-621c08157647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36413
25293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3641325293
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2671419428
Short name T764
Test name
Test status
Simulation time 157926608 ps
CPU time 0.8 seconds
Started Jun 29 06:39:45 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206208 kb
Host smart-9941a3e0-2851-4192-9faa-ed22eaa2975e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26714
19428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2671419428
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2933367671
Short name T1626
Test name
Test status
Simulation time 164980346 ps
CPU time 0.84 seconds
Started Jun 29 06:39:44 PM PDT 24
Finished Jun 29 06:39:47 PM PDT 24
Peak memory 206216 kb
Host smart-cb6e25ae-eb66-4458-9b32-558210309c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29333
67671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2933367671
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.4234966712
Short name T192
Test name
Test status
Simulation time 151993801 ps
CPU time 0.79 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206144 kb
Host smart-34371e9f-ae57-408e-b1dd-f0ca2dc4d081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42349
66712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.4234966712
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3394799073
Short name T804
Test name
Test status
Simulation time 187444013 ps
CPU time 0.94 seconds
Started Jun 29 06:39:45 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206224 kb
Host smart-3b3a4ec1-52b5-4364-aeef-5b8d88ef072a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3394799073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3394799073
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3281376800
Short name T1380
Test name
Test status
Simulation time 162149396 ps
CPU time 0.8 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:49 PM PDT 24
Peak memory 206200 kb
Host smart-09d37cf5-fa2a-44f5-a55c-99d302526bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32813
76800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3281376800
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2456718570
Short name T2165
Test name
Test status
Simulation time 29915709 ps
CPU time 0.66 seconds
Started Jun 29 06:39:44 PM PDT 24
Finished Jun 29 06:39:47 PM PDT 24
Peak memory 206212 kb
Host smart-89560bfd-651b-4e6a-a185-ac8de42dc40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24567
18570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2456718570
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3701245161
Short name T1680
Test name
Test status
Simulation time 18856330552 ps
CPU time 46.73 seconds
Started Jun 29 06:39:43 PM PDT 24
Finished Jun 29 06:40:31 PM PDT 24
Peak memory 206476 kb
Host smart-e6cc54a0-f13d-47d8-bcab-f24c41aa7962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37012
45161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3701245161
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.736650314
Short name T1090
Test name
Test status
Simulation time 192404391 ps
CPU time 0.86 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206204 kb
Host smart-f808aa41-96a5-464b-bac9-e658ddc108d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73665
0314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.736650314
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3846503717
Short name T1914
Test name
Test status
Simulation time 231521397 ps
CPU time 0.94 seconds
Started Jun 29 06:39:56 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206212 kb
Host smart-84f843f7-e50c-4f7b-a75a-50802265f1fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38465
03717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3846503717
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.757498505
Short name T2247
Test name
Test status
Simulation time 191514958 ps
CPU time 0.87 seconds
Started Jun 29 06:39:50 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206216 kb
Host smart-704ce4ef-2da5-4c42-bfc5-b5efa32136ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75749
8505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.757498505
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.4049611689
Short name T2248
Test name
Test status
Simulation time 184080821 ps
CPU time 0.88 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:39:44 PM PDT 24
Peak memory 206164 kb
Host smart-2edbe4b4-e56d-48ca-b650-0481582bd2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40496
11689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.4049611689
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.660977247
Short name T491
Test name
Test status
Simulation time 158346528 ps
CPU time 0.81 seconds
Started Jun 29 06:39:48 PM PDT 24
Finished Jun 29 06:39:50 PM PDT 24
Peak memory 206196 kb
Host smart-7dba36d8-542b-4154-8658-79417ab47b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66097
7247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.660977247
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3470999875
Short name T704
Test name
Test status
Simulation time 166935740 ps
CPU time 0.85 seconds
Started Jun 29 06:39:52 PM PDT 24
Finished Jun 29 06:39:53 PM PDT 24
Peak memory 206196 kb
Host smart-8b06a0ea-bf31-49b1-9cc5-25176578b062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34709
99875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3470999875
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3244303561
Short name T1934
Test name
Test status
Simulation time 191839891 ps
CPU time 0.82 seconds
Started Jun 29 06:39:40 PM PDT 24
Finished Jun 29 06:39:41 PM PDT 24
Peak memory 206196 kb
Host smart-c75c199b-7ab9-4972-82cc-ebdb53b96637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32443
03561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3244303561
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1043698084
Short name T2504
Test name
Test status
Simulation time 219224503 ps
CPU time 0.98 seconds
Started Jun 29 06:39:41 PM PDT 24
Finished Jun 29 06:39:43 PM PDT 24
Peak memory 206128 kb
Host smart-49f9b398-75b3-4d13-b623-dc0fcb8b0cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10436
98084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1043698084
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.883782666
Short name T675
Test name
Test status
Simulation time 5330629363 ps
CPU time 39.29 seconds
Started Jun 29 06:39:49 PM PDT 24
Finished Jun 29 06:40:30 PM PDT 24
Peak memory 206412 kb
Host smart-b9addf35-8bcc-4e94-ab63-2e7c7ffffe12
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=883782666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.883782666
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1931087061
Short name T1358
Test name
Test status
Simulation time 200664323 ps
CPU time 0.87 seconds
Started Jun 29 06:39:40 PM PDT 24
Finished Jun 29 06:39:41 PM PDT 24
Peak memory 206228 kb
Host smart-bd710904-7e1d-44ba-b269-ce1ea813a7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19310
87061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1931087061
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3814844809
Short name T2249
Test name
Test status
Simulation time 181897551 ps
CPU time 0.79 seconds
Started Jun 29 06:39:51 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206200 kb
Host smart-a4718c34-b70e-4662-a39a-9e54b26ca5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38148
44809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3814844809
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.191905019
Short name T321
Test name
Test status
Simulation time 4422409319 ps
CPU time 32.67 seconds
Started Jun 29 06:39:43 PM PDT 24
Finished Jun 29 06:40:18 PM PDT 24
Peak memory 206420 kb
Host smart-03232789-a77a-4c02-b1bf-919cd22ad69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19190
5019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.191905019
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.1847788490
Short name T1944
Test name
Test status
Simulation time 68518726 ps
CPU time 0.7 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206164 kb
Host smart-64a3a240-cd29-4444-a495-81621e099396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1847788490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.1847788490
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2060025630
Short name T1533
Test name
Test status
Simulation time 3798223545 ps
CPU time 4.76 seconds
Started Jun 29 06:39:38 PM PDT 24
Finished Jun 29 06:39:43 PM PDT 24
Peak memory 206380 kb
Host smart-e6acbec2-dc73-4133-9851-baf3166c76c0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2060025630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.2060025630
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.367648591
Short name T614
Test name
Test status
Simulation time 13469295817 ps
CPU time 12.5 seconds
Started Jun 29 06:39:40 PM PDT 24
Finished Jun 29 06:39:53 PM PDT 24
Peak memory 206444 kb
Host smart-e61974e4-4706-42e1-9216-59f5cd06398d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=367648591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.367648591
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1916814487
Short name T11
Test name
Test status
Simulation time 23365113050 ps
CPU time 26.19 seconds
Started Jun 29 06:39:43 PM PDT 24
Finished Jun 29 06:40:12 PM PDT 24
Peak memory 206324 kb
Host smart-201fd362-1e36-4145-94ca-2e62a555db68
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1916814487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.1916814487
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3024451445
Short name T698
Test name
Test status
Simulation time 210822931 ps
CPU time 0.98 seconds
Started Jun 29 06:39:45 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206196 kb
Host smart-0a701d1e-3fa1-4890-8ae3-b6e3a57d7401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
51445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3024451445
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3970570024
Short name T1147
Test name
Test status
Simulation time 621950773 ps
CPU time 1.74 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:39:45 PM PDT 24
Peak memory 206288 kb
Host smart-412b9ae3-266e-4fca-8a21-f1ed04b20f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39705
70024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3970570024
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1909034302
Short name T182
Test name
Test status
Simulation time 926555758 ps
CPU time 2.34 seconds
Started Jun 29 06:39:40 PM PDT 24
Finished Jun 29 06:39:42 PM PDT 24
Peak memory 206300 kb
Host smart-af3e6140-2b80-472d-99a7-3e8017db78c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19090
34302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1909034302
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.3936685881
Short name T414
Test name
Test status
Simulation time 9416338681 ps
CPU time 21.25 seconds
Started Jun 29 06:39:50 PM PDT 24
Finished Jun 29 06:40:12 PM PDT 24
Peak memory 206452 kb
Host smart-f872419c-43cc-4509-890b-693ed2821a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39366
85881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3936685881
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.379930832
Short name T1052
Test name
Test status
Simulation time 366481535 ps
CPU time 1.36 seconds
Started Jun 29 06:39:43 PM PDT 24
Finished Jun 29 06:39:46 PM PDT 24
Peak memory 206216 kb
Host smart-ec649bc3-033b-4c2d-88b3-fb05dd16e239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37993
0832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.379930832
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.3258076011
Short name T2175
Test name
Test status
Simulation time 144683488 ps
CPU time 0.76 seconds
Started Jun 29 06:39:44 PM PDT 24
Finished Jun 29 06:39:46 PM PDT 24
Peak memory 206196 kb
Host smart-cf54adde-41a5-41d2-865c-6e925a0f2d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32580
76011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3258076011
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.843291038
Short name T2440
Test name
Test status
Simulation time 86998632 ps
CPU time 0.67 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:39:45 PM PDT 24
Peak memory 206156 kb
Host smart-245e4f17-70a7-47a5-a6d1-9a06d14020db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84329
1038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.843291038
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1064951682
Short name T1117
Test name
Test status
Simulation time 1060357780 ps
CPU time 2.58 seconds
Started Jun 29 06:39:44 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206260 kb
Host smart-b6c0dfbe-a1b7-44da-9e2a-b54cb274d0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10649
51682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1064951682
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2935028868
Short name T1059
Test name
Test status
Simulation time 332940328 ps
CPU time 2.38 seconds
Started Jun 29 06:39:47 PM PDT 24
Finished Jun 29 06:39:51 PM PDT 24
Peak memory 206304 kb
Host smart-cb7cc81c-a75a-43e9-b195-8fdd69af862f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29350
28868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2935028868
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2386761275
Short name T1182
Test name
Test status
Simulation time 200651463 ps
CPU time 0.85 seconds
Started Jun 29 06:39:45 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206216 kb
Host smart-37016244-4a87-4697-b52c-bd64c78f73ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23867
61275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2386761275
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1208849391
Short name T2273
Test name
Test status
Simulation time 168289820 ps
CPU time 0.83 seconds
Started Jun 29 06:39:44 PM PDT 24
Finished Jun 29 06:39:47 PM PDT 24
Peak memory 206124 kb
Host smart-5d83264b-c000-471f-a733-71593a15d153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12088
49391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1208849391
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1415742769
Short name T1856
Test name
Test status
Simulation time 173966568 ps
CPU time 0.85 seconds
Started Jun 29 06:39:52 PM PDT 24
Finished Jun 29 06:39:53 PM PDT 24
Peak memory 206216 kb
Host smart-2453b459-4c25-4c84-8dd3-e3f7d7720f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14157
42769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1415742769
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.1702503991
Short name T2003
Test name
Test status
Simulation time 7954344122 ps
CPU time 73.23 seconds
Started Jun 29 06:39:47 PM PDT 24
Finished Jun 29 06:41:02 PM PDT 24
Peak memory 206372 kb
Host smart-8c0c105d-e850-4ef1-aec3-c5eb69a14223
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1702503991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.1702503991
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.973247050
Short name T1957
Test name
Test status
Simulation time 234205848 ps
CPU time 0.86 seconds
Started Jun 29 06:39:42 PM PDT 24
Finished Jun 29 06:39:45 PM PDT 24
Peak memory 206192 kb
Host smart-e92f1f18-c8ae-440f-a955-c8829d8ec27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97324
7050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.973247050
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2947305436
Short name T2410
Test name
Test status
Simulation time 23395391293 ps
CPU time 23.68 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:40:12 PM PDT 24
Peak memory 206308 kb
Host smart-56f84387-c23f-4a6c-8774-edba381cd27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29473
05436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2947305436
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2761218599
Short name T600
Test name
Test status
Simulation time 3288568133 ps
CPU time 3.48 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206204 kb
Host smart-e672a634-46d4-4521-a060-85bfb743a586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27612
18599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2761218599
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.2816353823
Short name T22
Test name
Test status
Simulation time 9972801048 ps
CPU time 98.35 seconds
Started Jun 29 06:39:51 PM PDT 24
Finished Jun 29 06:41:30 PM PDT 24
Peak memory 206464 kb
Host smart-bbf85863-fcee-434d-a106-e691b9e2402c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28163
53823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.2816353823
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2302855885
Short name T1578
Test name
Test status
Simulation time 8003948815 ps
CPU time 221.84 seconds
Started Jun 29 06:39:51 PM PDT 24
Finished Jun 29 06:43:33 PM PDT 24
Peak memory 206456 kb
Host smart-9e86e728-2f52-407d-bba9-b9d130920ba2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2302855885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2302855885
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.982082232
Short name T1928
Test name
Test status
Simulation time 266054838 ps
CPU time 0.97 seconds
Started Jun 29 06:39:53 PM PDT 24
Finished Jun 29 06:39:54 PM PDT 24
Peak memory 206220 kb
Host smart-898a47d9-dec8-4b2c-b754-f5f4c74da65c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=982082232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.982082232
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.401821951
Short name T1923
Test name
Test status
Simulation time 212207690 ps
CPU time 0.84 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:48 PM PDT 24
Peak memory 206216 kb
Host smart-5ad71140-6f31-4f33-aef4-76aca2de67c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40182
1951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.401821951
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.645986534
Short name T664
Test name
Test status
Simulation time 4076575351 ps
CPU time 109.73 seconds
Started Jun 29 06:39:45 PM PDT 24
Finished Jun 29 06:41:36 PM PDT 24
Peak memory 206464 kb
Host smart-42105b48-ff30-4e71-88d4-7c6a2dc256f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64598
6534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.645986534
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.961164204
Short name T1601
Test name
Test status
Simulation time 4949724830 ps
CPU time 136.66 seconds
Started Jun 29 06:39:50 PM PDT 24
Finished Jun 29 06:42:07 PM PDT 24
Peak memory 206464 kb
Host smart-9b7327b6-bad8-46d4-bca7-25b0743aa68e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=961164204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.961164204
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1267622807
Short name T2157
Test name
Test status
Simulation time 155696461 ps
CPU time 0.88 seconds
Started Jun 29 06:39:45 PM PDT 24
Finished Jun 29 06:39:47 PM PDT 24
Peak memory 206216 kb
Host smart-4123ed4c-52c4-4979-b014-8bcf37e0d895
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1267622807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1267622807
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.270090021
Short name T983
Test name
Test status
Simulation time 144427003 ps
CPU time 0.79 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:49 PM PDT 24
Peak memory 206216 kb
Host smart-9f5281ff-742c-4dfd-8ce4-cfad848afdbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27009
0021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.270090021
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.118260256
Short name T126
Test name
Test status
Simulation time 187039300 ps
CPU time 0.95 seconds
Started Jun 29 06:39:49 PM PDT 24
Finished Jun 29 06:39:51 PM PDT 24
Peak memory 206216 kb
Host smart-0cf711fa-a72d-4999-a758-0813c9d73767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11826
0256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.118260256
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.4154509898
Short name T2292
Test name
Test status
Simulation time 156483235 ps
CPU time 0.8 seconds
Started Jun 29 06:39:48 PM PDT 24
Finished Jun 29 06:39:50 PM PDT 24
Peak memory 206200 kb
Host smart-fdb2e4ce-eab2-45c2-8e9b-8814a9bd280e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41545
09898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.4154509898
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3761559802
Short name T2510
Test name
Test status
Simulation time 151735898 ps
CPU time 0.76 seconds
Started Jun 29 06:39:53 PM PDT 24
Finished Jun 29 06:39:54 PM PDT 24
Peak memory 206196 kb
Host smart-4a9b4c82-6b1e-4f68-b33e-9e7281ea3c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37615
59802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3761559802
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.127167309
Short name T1590
Test name
Test status
Simulation time 164619358 ps
CPU time 0.86 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:39:57 PM PDT 24
Peak memory 205900 kb
Host smart-5fc0fc33-3a1c-4a00-bc3f-fc3d48b9e868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12716
7309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.127167309
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.698387391
Short name T1471
Test name
Test status
Simulation time 160832763 ps
CPU time 0.83 seconds
Started Jun 29 06:40:14 PM PDT 24
Finished Jun 29 06:40:15 PM PDT 24
Peak memory 206220 kb
Host smart-c9198af7-86cf-4048-9cab-48ccfc9b619f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69838
7391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.698387391
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.669207312
Short name T496
Test name
Test status
Simulation time 247462482 ps
CPU time 0.99 seconds
Started Jun 29 06:40:01 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206188 kb
Host smart-bea6a7ab-e442-4a1f-a0c5-472320094eb2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=669207312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.669207312
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1985844065
Short name T2489
Test name
Test status
Simulation time 146908461 ps
CPU time 0.78 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206188 kb
Host smart-05957696-61c8-4864-b6b8-2959c4270150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19858
44065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1985844065
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2965541417
Short name T42
Test name
Test status
Simulation time 42429061 ps
CPU time 0.66 seconds
Started Jun 29 06:40:00 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206032 kb
Host smart-b43f943a-44ac-4081-9463-be9b67230c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29655
41417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2965541417
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1185681754
Short name T1190
Test name
Test status
Simulation time 9959414693 ps
CPU time 22.02 seconds
Started Jun 29 06:39:45 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206480 kb
Host smart-5cff1321-e6e8-4f9f-9555-d656e8dbc851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11856
81754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1185681754
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2761328409
Short name T628
Test name
Test status
Simulation time 175716572 ps
CPU time 0.85 seconds
Started Jun 29 06:40:08 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206116 kb
Host smart-0826cf0b-db2d-4675-b7ef-7d3976e3ecc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27613
28409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2761328409
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2760925845
Short name T883
Test name
Test status
Simulation time 205348078 ps
CPU time 0.93 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:39:57 PM PDT 24
Peak memory 206212 kb
Host smart-43676933-2f2e-4fa3-b16a-c1fe6db8f075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27609
25845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2760925845
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.2537503100
Short name T645
Test name
Test status
Simulation time 245725469 ps
CPU time 0.94 seconds
Started Jun 29 06:40:00 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206216 kb
Host smart-93319f67-0099-4dd9-9e77-03b71d4f88e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25375
03100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.2537503100
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3266960457
Short name T1888
Test name
Test status
Simulation time 175208765 ps
CPU time 0.82 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:09 PM PDT 24
Peak memory 206200 kb
Host smart-15ce425c-ae24-4521-bfb9-a5e083c2eb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32669
60457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3266960457
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2928266537
Short name T2530
Test name
Test status
Simulation time 179758275 ps
CPU time 0.84 seconds
Started Jun 29 06:39:50 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206200 kb
Host smart-a259add0-9e19-406a-a7e0-dc6a29c78138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29282
66537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2928266537
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3628576424
Short name T1633
Test name
Test status
Simulation time 176075471 ps
CPU time 0.83 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:59 PM PDT 24
Peak memory 206196 kb
Host smart-4eb06f53-4d2a-4c3c-88cb-f71c2d6d6e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36285
76424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3628576424
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.813291542
Short name T544
Test name
Test status
Simulation time 174745096 ps
CPU time 0.85 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:39:57 PM PDT 24
Peak memory 206192 kb
Host smart-93f9b247-b1e9-4d17-bafb-8b060194d5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81329
1542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.813291542
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1605573694
Short name T1363
Test name
Test status
Simulation time 203807421 ps
CPU time 0.9 seconds
Started Jun 29 06:39:52 PM PDT 24
Finished Jun 29 06:39:54 PM PDT 24
Peak memory 206216 kb
Host smart-db5c919a-22ea-4301-b159-81f86f08034c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16055
73694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1605573694
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.2218723019
Short name T1718
Test name
Test status
Simulation time 4649777206 ps
CPU time 131.5 seconds
Started Jun 29 06:39:51 PM PDT 24
Finished Jun 29 06:42:03 PM PDT 24
Peak memory 206488 kb
Host smart-7557cf98-ca19-49c6-a46b-7914baaf1799
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2218723019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.2218723019
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1866925535
Short name T1687
Test name
Test status
Simulation time 208157260 ps
CPU time 0.85 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206224 kb
Host smart-0ab18246-8a34-400a-9880-00d56bf55064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18669
25535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1866925535
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1483752655
Short name T1897
Test name
Test status
Simulation time 201842221 ps
CPU time 0.86 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:40:04 PM PDT 24
Peak memory 206196 kb
Host smart-451e2037-9c23-4770-a9e7-1d2c414beddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14837
52655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1483752655
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3609567080
Short name T1658
Test name
Test status
Simulation time 7450190293 ps
CPU time 197.36 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:43:16 PM PDT 24
Peak memory 206440 kb
Host smart-e1543879-8788-4126-9b8d-ef4ed40f66e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36095
67080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3609567080
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.2363601895
Short name T2458
Test name
Test status
Simulation time 37431937 ps
CPU time 0.69 seconds
Started Jun 29 06:40:01 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206180 kb
Host smart-b1d623c1-4054-40e5-8eea-3ef5a43a3f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2363601895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.2363601895
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1417192325
Short name T1152
Test name
Test status
Simulation time 3410522149 ps
CPU time 4 seconds
Started Jun 29 06:39:51 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206352 kb
Host smart-942bf9a3-14b1-41dd-bf24-7da81883873c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1417192325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.1417192325
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.4019669376
Short name T1192
Test name
Test status
Simulation time 13384331065 ps
CPU time 14.84 seconds
Started Jun 29 06:39:48 PM PDT 24
Finished Jun 29 06:40:04 PM PDT 24
Peak memory 206456 kb
Host smart-d7e75a24-042d-45df-845d-ac86c18eea7f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4019669376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.4019669376
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.4211830208
Short name T2347
Test name
Test status
Simulation time 185351439 ps
CPU time 0.87 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:59 PM PDT 24
Peak memory 206196 kb
Host smart-350d7fe4-7968-4d5f-9c7f-70f164de855f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42118
30208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.4211830208
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3187755894
Short name T1887
Test name
Test status
Simulation time 165646507 ps
CPU time 0.78 seconds
Started Jun 29 06:39:52 PM PDT 24
Finished Jun 29 06:39:54 PM PDT 24
Peak memory 206196 kb
Host smart-6ccb7ed4-c06d-4ebf-8460-ba2889bc89d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31877
55894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3187755894
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3068381046
Short name T975
Test name
Test status
Simulation time 147214119 ps
CPU time 0.78 seconds
Started Jun 29 06:39:51 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206188 kb
Host smart-80d73eba-c82d-42e0-8915-26ba6a975697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30683
81046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3068381046
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_device_address.3685539166
Short name T2400
Test name
Test status
Simulation time 13556528746 ps
CPU time 27.87 seconds
Started Jun 29 06:39:45 PM PDT 24
Finished Jun 29 06:40:14 PM PDT 24
Peak memory 206436 kb
Host smart-bd9b876f-d11c-4934-891f-caf48c871848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36855
39166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.3685539166
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.1478449824
Short name T1487
Test name
Test status
Simulation time 384287646 ps
CPU time 1.15 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206192 kb
Host smart-9190246a-21d6-455d-a9ab-67aa2cb4c2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14784
49824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.1478449824
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.222433471
Short name T1124
Test name
Test status
Simulation time 137843960 ps
CPU time 0.82 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206200 kb
Host smart-4e6e7150-de17-44fc-811d-78c42a52e987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22243
3471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.222433471
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.769779635
Short name T1808
Test name
Test status
Simulation time 33056251 ps
CPU time 0.65 seconds
Started Jun 29 06:39:46 PM PDT 24
Finished Jun 29 06:39:49 PM PDT 24
Peak memory 206208 kb
Host smart-46be2723-34ab-4e4e-ab37-c61196b29188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76977
9635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.769779635
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.1272392395
Short name T1115
Test name
Test status
Simulation time 1059689926 ps
CPU time 2.86 seconds
Started Jun 29 06:39:53 PM PDT 24
Finished Jun 29 06:39:57 PM PDT 24
Peak memory 206312 kb
Host smart-b6344533-da14-45f1-a70a-a0a022268d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12723
92395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.1272392395
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.748789344
Short name T1961
Test name
Test status
Simulation time 170288249 ps
CPU time 1.95 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206132 kb
Host smart-8474bc50-04d2-4e6d-95f9-6038926926a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74878
9344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.748789344
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1872209343
Short name T590
Test name
Test status
Simulation time 174637023 ps
CPU time 0.82 seconds
Started Jun 29 06:39:51 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206200 kb
Host smart-e069f8ed-cc39-462d-b249-d68d7cfc0f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18722
09343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1872209343
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1107135642
Short name T407
Test name
Test status
Simulation time 143217194 ps
CPU time 0.77 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206132 kb
Host smart-c43d81de-b2b9-4651-bc9b-2756f8be8519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11071
35642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1107135642
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.842338646
Short name T912
Test name
Test status
Simulation time 212350844 ps
CPU time 0.9 seconds
Started Jun 29 06:40:01 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206188 kb
Host smart-d4337ce2-fb92-428f-be67-6808d83b4339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84233
8646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.842338646
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.915629746
Short name T1753
Test name
Test status
Simulation time 183214299 ps
CPU time 0.85 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:59 PM PDT 24
Peak memory 206192 kb
Host smart-24686441-0c3c-462c-91f3-e313c5352f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91562
9746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.915629746
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.1285873799
Short name T739
Test name
Test status
Simulation time 23334538277 ps
CPU time 21.26 seconds
Started Jun 29 06:39:48 PM PDT 24
Finished Jun 29 06:40:11 PM PDT 24
Peak memory 206316 kb
Host smart-7fb05010-cc51-4ee4-a9ef-e3f76497e618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12858
73799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.1285873799
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3145770171
Short name T2523
Test name
Test status
Simulation time 3286099233 ps
CPU time 4.12 seconds
Started Jun 29 06:39:47 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206232 kb
Host smart-f5b49b8b-9eac-41df-98b3-ea332e86472e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31457
70171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3145770171
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.2626463893
Short name T1864
Test name
Test status
Simulation time 7581649857 ps
CPU time 211.94 seconds
Started Jun 29 06:39:48 PM PDT 24
Finished Jun 29 06:43:21 PM PDT 24
Peak memory 206504 kb
Host smart-bbfd8da2-1a18-4e6c-b682-c3bab99a149c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26264
63893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.2626463893
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3342237456
Short name T1927
Test name
Test status
Simulation time 3666125764 ps
CPU time 101.14 seconds
Started Jun 29 06:40:01 PM PDT 24
Finished Jun 29 06:41:43 PM PDT 24
Peak memory 206432 kb
Host smart-945d4c20-9b35-4a6d-940d-661de472a615
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3342237456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3342237456
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3730932251
Short name T351
Test name
Test status
Simulation time 314499335 ps
CPU time 1 seconds
Started Jun 29 06:39:48 PM PDT 24
Finished Jun 29 06:39:50 PM PDT 24
Peak memory 206220 kb
Host smart-ad25497d-b02a-4c91-a5d0-f749627f94c0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3730932251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3730932251
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1198654469
Short name T1241
Test name
Test status
Simulation time 197240231 ps
CPU time 0.87 seconds
Started Jun 29 06:40:08 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206204 kb
Host smart-0fc33aa1-07bb-4614-90bd-c2241dfc1cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986
54469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1198654469
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2448572856
Short name T396
Test name
Test status
Simulation time 4478989798 ps
CPU time 33.55 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:40:28 PM PDT 24
Peak memory 206504 kb
Host smart-df28cb3e-db27-42d3-9e18-dce141958392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24485
72856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2448572856
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1299128850
Short name T91
Test name
Test status
Simulation time 4353197700 ps
CPU time 117.82 seconds
Started Jun 29 06:39:50 PM PDT 24
Finished Jun 29 06:41:49 PM PDT 24
Peak memory 206468 kb
Host smart-457e9108-6151-4e53-91b5-2e4471997ce4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1299128850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1299128850
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.3991687038
Short name T573
Test name
Test status
Simulation time 157464577 ps
CPU time 0.79 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206220 kb
Host smart-95789cac-453c-439b-b63a-5d962b261e69
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3991687038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3991687038
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3528511381
Short name T695
Test name
Test status
Simulation time 161640058 ps
CPU time 0.83 seconds
Started Jun 29 06:39:49 PM PDT 24
Finished Jun 29 06:39:51 PM PDT 24
Peak memory 206184 kb
Host smart-01f1a1be-d56b-4542-b1d2-c50edc076ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35285
11381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3528511381
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3829898930
Short name T2522
Test name
Test status
Simulation time 168969920 ps
CPU time 0.8 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206200 kb
Host smart-b027bc2c-f304-4834-b965-11dcdbd8df7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38298
98930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3829898930
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.291097054
Short name T1588
Test name
Test status
Simulation time 193896981 ps
CPU time 0.88 seconds
Started Jun 29 06:39:52 PM PDT 24
Finished Jun 29 06:39:54 PM PDT 24
Peak memory 206168 kb
Host smart-8506cf82-63b0-4c28-9a00-81600a010964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29109
7054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.291097054
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3434944648
Short name T371
Test name
Test status
Simulation time 175107587 ps
CPU time 0.82 seconds
Started Jun 29 06:39:53 PM PDT 24
Finished Jun 29 06:39:54 PM PDT 24
Peak memory 206196 kb
Host smart-0c1c7758-376d-4c28-8b08-dd36557d704a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34349
44648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3434944648
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2244355834
Short name T639
Test name
Test status
Simulation time 192284160 ps
CPU time 0.84 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206180 kb
Host smart-06dea001-876d-4bb6-988a-dac0c1a6b083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22443
55834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2244355834
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3965486461
Short name T1581
Test name
Test status
Simulation time 153826474 ps
CPU time 0.82 seconds
Started Jun 29 06:39:49 PM PDT 24
Finished Jun 29 06:39:51 PM PDT 24
Peak memory 206200 kb
Host smart-d01a6455-8f79-43a4-9e37-2d0f5963c43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39654
86461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3965486461
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.2038696009
Short name T1785
Test name
Test status
Simulation time 218929024 ps
CPU time 0.96 seconds
Started Jun 29 06:39:50 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 206224 kb
Host smart-29735322-f85b-4908-9b9d-dd78d1d9a7a4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2038696009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.2038696009
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.1228882132
Short name T1462
Test name
Test status
Simulation time 155236234 ps
CPU time 0.75 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206132 kb
Host smart-359eb025-25e2-433f-a946-5286fb6b1f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12288
82132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.1228882132
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.855780689
Short name T1277
Test name
Test status
Simulation time 37288894 ps
CPU time 0.65 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:06 PM PDT 24
Peak memory 206216 kb
Host smart-189a3cb1-ee5b-4233-8fba-dc4c13b25957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85578
0689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.855780689
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1703995320
Short name T882
Test name
Test status
Simulation time 18194880474 ps
CPU time 44.94 seconds
Started Jun 29 06:39:48 PM PDT 24
Finished Jun 29 06:40:34 PM PDT 24
Peak memory 206436 kb
Host smart-c1809e8e-c5c0-4c7f-a2bb-3e5055c78f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17039
95320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1703995320
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1991335874
Short name T962
Test name
Test status
Simulation time 164189463 ps
CPU time 0.82 seconds
Started Jun 29 06:39:56 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206184 kb
Host smart-00a05b1b-d910-4c64-b5a0-5e573253d910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19913
35874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1991335874
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2024731432
Short name T1868
Test name
Test status
Simulation time 244738125 ps
CPU time 0.99 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206188 kb
Host smart-832f6f0f-59f9-48ec-961d-0bd6cbe6655e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20247
31432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2024731432
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3482497425
Short name T349
Test name
Test status
Simulation time 197076573 ps
CPU time 0.87 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206212 kb
Host smart-be63d04c-9989-4bb6-a872-6a935dd40e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34824
97425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3482497425
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.132445358
Short name T878
Test name
Test status
Simulation time 197222287 ps
CPU time 0.89 seconds
Started Jun 29 06:40:00 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206012 kb
Host smart-993e86b3-220a-49b4-b246-4936d9394802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13244
5358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.132445358
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3771983999
Short name T474
Test name
Test status
Simulation time 179228370 ps
CPU time 0.82 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206164 kb
Host smart-45adfef1-96c8-4be4-a667-440f72474650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37719
83999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3771983999
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2491424817
Short name T2524
Test name
Test status
Simulation time 149232673 ps
CPU time 0.8 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206192 kb
Host smart-ce8b3387-1957-48b8-96f2-6c7b5a502628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24914
24817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2491424817
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1044825153
Short name T1988
Test name
Test status
Simulation time 151434505 ps
CPU time 0.8 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206196 kb
Host smart-2f4bfad0-d271-4130-8e98-122e8e66811c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10448
25153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1044825153
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3594405490
Short name T1327
Test name
Test status
Simulation time 263234527 ps
CPU time 1.04 seconds
Started Jun 29 06:39:53 PM PDT 24
Finished Jun 29 06:39:55 PM PDT 24
Peak memory 206216 kb
Host smart-e19b6102-e5b0-4ca8-bbd2-055415ff7ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35944
05490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3594405490
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.4222663615
Short name T2002
Test name
Test status
Simulation time 3969723319 ps
CPU time 37.21 seconds
Started Jun 29 06:40:09 PM PDT 24
Finished Jun 29 06:40:47 PM PDT 24
Peak memory 206352 kb
Host smart-61abde6e-abef-4ca5-af71-ef73faa20c74
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4222663615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.4222663615
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3116746582
Short name T1183
Test name
Test status
Simulation time 196520897 ps
CPU time 0.82 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 205828 kb
Host smart-e5a3bfe3-0232-43d5-84bb-13d5370bea88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31167
46582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3116746582
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1011841427
Short name T2207
Test name
Test status
Simulation time 178210576 ps
CPU time 0.82 seconds
Started Jun 29 06:40:13 PM PDT 24
Finished Jun 29 06:40:15 PM PDT 24
Peak memory 206196 kb
Host smart-33fae2fb-f7f7-4d10-9537-1b6e782f0668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10118
41427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1011841427
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.2506888672
Short name T437
Test name
Test status
Simulation time 5396026758 ps
CPU time 152.67 seconds
Started Jun 29 06:39:59 PM PDT 24
Finished Jun 29 06:42:33 PM PDT 24
Peak memory 206612 kb
Host smart-66098c44-6cd8-4d96-8eeb-4f81ce07eaaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25068
88672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2506888672
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.2069439962
Short name T2463
Test name
Test status
Simulation time 62251090 ps
CPU time 0.73 seconds
Started Jun 29 06:40:01 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206192 kb
Host smart-c7daafdf-27df-4a75-a744-a0870f4b7709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2069439962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.2069439962
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3484265751
Short name T9
Test name
Test status
Simulation time 3607379576 ps
CPU time 4.21 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206280 kb
Host smart-f5e6be2c-8628-4a23-8f6d-c393921e8f70
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3484265751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.3484265751
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3610902887
Short name T1845
Test name
Test status
Simulation time 13396754223 ps
CPU time 12.62 seconds
Started Jun 29 06:39:59 PM PDT 24
Finished Jun 29 06:40:13 PM PDT 24
Peak memory 206328 kb
Host smart-0f0cdf72-7f0d-46aa-9271-36056501b89d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3610902887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3610902887
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1827739187
Short name T1769
Test name
Test status
Simulation time 23364396821 ps
CPU time 23.82 seconds
Started Jun 29 06:40:00 PM PDT 24
Finished Jun 29 06:40:25 PM PDT 24
Peak memory 206328 kb
Host smart-d25843f2-85e8-468c-b05e-ee13748dec01
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1827739187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1827739187
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.807933843
Short name T1411
Test name
Test status
Simulation time 146355961 ps
CPU time 0.77 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:09 PM PDT 24
Peak memory 206216 kb
Host smart-b55e22ae-7332-4cb5-a4dd-ca0714bf69fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80793
3843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.807933843
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2799637528
Short name T72
Test name
Test status
Simulation time 142718166 ps
CPU time 0.76 seconds
Started Jun 29 06:40:09 PM PDT 24
Finished Jun 29 06:40:11 PM PDT 24
Peak memory 206372 kb
Host smart-1f03c651-bb41-43ef-92dd-4ca7f6f39927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27996
37528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2799637528
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.1876918058
Short name T985
Test name
Test status
Simulation time 160821930 ps
CPU time 0.8 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206172 kb
Host smart-e02196db-32bd-4c8e-aad5-e9a5cdaebe84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18769
18058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.1876918058
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3228817735
Short name T1497
Test name
Test status
Simulation time 991807987 ps
CPU time 2.1 seconds
Started Jun 29 06:40:11 PM PDT 24
Finished Jun 29 06:40:14 PM PDT 24
Peak memory 206300 kb
Host smart-933e6f50-f434-4386-8a5e-9a03c9486c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32288
17735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3228817735
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.4283685758
Short name T911
Test name
Test status
Simulation time 21149894653 ps
CPU time 36.54 seconds
Started Jun 29 06:39:49 PM PDT 24
Finished Jun 29 06:40:26 PM PDT 24
Peak memory 206444 kb
Host smart-fa073b54-52f3-4db7-97c4-7d993a7e52d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42836
85758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.4283685758
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.96230798
Short name T448
Test name
Test status
Simulation time 401146832 ps
CPU time 1.22 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206220 kb
Host smart-f8e132cc-fd6f-4243-b6f7-d992eaa27a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96230
798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.96230798
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2277847250
Short name T2466
Test name
Test status
Simulation time 142212361 ps
CPU time 0.77 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206092 kb
Host smart-18b1e0aa-fa1d-4e0d-98e8-cf27ec5aa2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22778
47250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2277847250
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.1256691153
Short name T2376
Test name
Test status
Simulation time 123528130 ps
CPU time 0.74 seconds
Started Jun 29 06:40:02 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206380 kb
Host smart-b18590e9-21ba-4232-accd-3c88d80fa989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12566
91153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1256691153
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.3220103242
Short name T1488
Test name
Test status
Simulation time 864174646 ps
CPU time 2.3 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:11 PM PDT 24
Peak memory 206292 kb
Host smart-f40cdc14-6e6d-48ff-b46c-f45987109fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32201
03242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.3220103242
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1036229750
Short name T872
Test name
Test status
Simulation time 220156951 ps
CPU time 1.56 seconds
Started Jun 29 06:39:53 PM PDT 24
Finished Jun 29 06:39:55 PM PDT 24
Peak memory 206288 kb
Host smart-9cab7a71-5551-40b4-bf09-5ed7756f4129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10362
29750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1036229750
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2709152002
Short name T1274
Test name
Test status
Simulation time 240786151 ps
CPU time 0.91 seconds
Started Jun 29 06:40:11 PM PDT 24
Finished Jun 29 06:40:13 PM PDT 24
Peak memory 206392 kb
Host smart-b381e176-d645-4848-a452-bf52dd0d336d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27091
52002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2709152002
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.666596182
Short name T656
Test name
Test status
Simulation time 144815432 ps
CPU time 0.75 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:39:55 PM PDT 24
Peak memory 206172 kb
Host smart-9771d4d6-4155-4148-a353-9cfc7cde44cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66659
6182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.666596182
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3302728662
Short name T673
Test name
Test status
Simulation time 216960149 ps
CPU time 0.95 seconds
Started Jun 29 06:39:59 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206192 kb
Host smart-72a5421a-8006-441e-8f91-94ea81370300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33027
28662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3302728662
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.1882640759
Short name T1981
Test name
Test status
Simulation time 227937562 ps
CPU time 0.87 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:06 PM PDT 24
Peak memory 206172 kb
Host smart-6a7b2ab2-a10a-4969-8a9e-743a16a8d4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18826
40759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1882640759
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.3372031683
Short name T2093
Test name
Test status
Simulation time 23385981338 ps
CPU time 26.49 seconds
Started Jun 29 06:39:48 PM PDT 24
Finished Jun 29 06:40:16 PM PDT 24
Peak memory 206312 kb
Host smart-c755bc8c-bc85-4a37-8908-017e8a5f213a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33720
31683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.3372031683
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1738466295
Short name T1187
Test name
Test status
Simulation time 3316440782 ps
CPU time 3.88 seconds
Started Jun 29 06:39:59 PM PDT 24
Finished Jun 29 06:40:04 PM PDT 24
Peak memory 206256 kb
Host smart-4de5f1b5-ffb2-48dc-999e-e020bda8b934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17384
66295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1738466295
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.1001459899
Short name T493
Test name
Test status
Simulation time 5356974276 ps
CPU time 47.39 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:40:42 PM PDT 24
Peak memory 206428 kb
Host smart-e556ce49-baa1-427a-81e0-c6ceb51b6632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10014
59899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.1001459899
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.1241415766
Short name T1315
Test name
Test status
Simulation time 3427912630 ps
CPU time 90.71 seconds
Started Jun 29 06:40:15 PM PDT 24
Finished Jun 29 06:41:46 PM PDT 24
Peak memory 206452 kb
Host smart-b6f1da43-96d1-47d8-b4b2-05babaa302ab
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1241415766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.1241415766
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.354510158
Short name T2324
Test name
Test status
Simulation time 291428243 ps
CPU time 0.98 seconds
Started Jun 29 06:40:01 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206172 kb
Host smart-d6b9d4b8-19b6-47b2-a212-27ab99f2e840
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=354510158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.354510158
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.421722828
Short name T427
Test name
Test status
Simulation time 187283146 ps
CPU time 0.86 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206184 kb
Host smart-d029f4ae-9e8c-4edc-a9bd-0c22e9e2e559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42172
2828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.421722828
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.26436127
Short name T2580
Test name
Test status
Simulation time 3798361619 ps
CPU time 29.12 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:38 PM PDT 24
Peak memory 206376 kb
Host smart-27a4cbc7-b63f-4e75-945b-86546949164f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26436
127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.26436127
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.2834689735
Short name T1676
Test name
Test status
Simulation time 3602243462 ps
CPU time 27.15 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:33 PM PDT 24
Peak memory 206400 kb
Host smart-b3dc5ca3-6c6b-481b-9191-2b49428e2e6c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2834689735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.2834689735
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.1654704939
Short name T1763
Test name
Test status
Simulation time 156359369 ps
CPU time 0.79 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:59 PM PDT 24
Peak memory 206220 kb
Host smart-2adc976b-9cd5-4361-8ce5-ffdafd56e63b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1654704939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.1654704939
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.815144746
Short name T1971
Test name
Test status
Simulation time 140486865 ps
CPU time 0.83 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:40:05 PM PDT 24
Peak memory 206216 kb
Host smart-b24d3cc0-fe44-437f-97b5-0f5f349a4d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81514
4746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.815144746
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.716436241
Short name T130
Test name
Test status
Simulation time 211631627 ps
CPU time 0.89 seconds
Started Jun 29 06:40:08 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206216 kb
Host smart-9d93c2e4-e448-4df3-9d9e-4ecd47caf565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71643
6241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.716436241
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.1904929029
Short name T1284
Test name
Test status
Simulation time 171448875 ps
CPU time 0.83 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206200 kb
Host smart-3c55c973-d8b1-494c-8eaa-4cde9a758b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19049
29029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1904929029
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3591681764
Short name T875
Test name
Test status
Simulation time 142190739 ps
CPU time 0.77 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206192 kb
Host smart-0291690c-4641-4397-8b79-f77678427b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35916
81764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3591681764
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3615876152
Short name T1838
Test name
Test status
Simulation time 249436003 ps
CPU time 0.94 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206172 kb
Host smart-abc48316-5602-4b39-833c-45275c482d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36158
76152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3615876152
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2602024528
Short name T177
Test name
Test status
Simulation time 158661791 ps
CPU time 0.76 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206216 kb
Host smart-6a2fbcce-b414-40eb-8fd2-e298ddae65a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26020
24528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2602024528
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.4121609280
Short name T1282
Test name
Test status
Simulation time 199282701 ps
CPU time 0.92 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:06 PM PDT 24
Peak memory 206224 kb
Host smart-062226d7-ccc7-44f3-ab14-230a38043c40
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4121609280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.4121609280
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3945162090
Short name T574
Test name
Test status
Simulation time 148633955 ps
CPU time 0.82 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206212 kb
Host smart-187818a2-022e-4c6b-93ea-c9abe1bd1f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39451
62090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3945162090
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1867772497
Short name T27
Test name
Test status
Simulation time 54344624 ps
CPU time 0.68 seconds
Started Jun 29 06:40:00 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206216 kb
Host smart-89cf4859-3200-4f55-a350-ed56e317b504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18677
72497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1867772497
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1475779190
Short name T2136
Test name
Test status
Simulation time 17206135135 ps
CPU time 38.36 seconds
Started Jun 29 06:39:53 PM PDT 24
Finished Jun 29 06:40:32 PM PDT 24
Peak memory 206484 kb
Host smart-171d2a11-5a80-467a-8937-d2b2cf4834c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14757
79190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1475779190
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.21569316
Short name T1110
Test name
Test status
Simulation time 236194555 ps
CPU time 0.95 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:39:55 PM PDT 24
Peak memory 206204 kb
Host smart-29002d90-0312-4e50-9343-654f66fa59b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21569
316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.21569316
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1829334433
Short name T774
Test name
Test status
Simulation time 182811947 ps
CPU time 0.85 seconds
Started Jun 29 06:40:02 PM PDT 24
Finished Jun 29 06:40:04 PM PDT 24
Peak memory 206212 kb
Host smart-0fa5bd06-efc2-4281-924e-966ff58f06a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18293
34433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1829334433
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1454918359
Short name T1298
Test name
Test status
Simulation time 151729084 ps
CPU time 0.81 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206120 kb
Host smart-b9f959b2-8fcf-4dcc-820a-f5ea71735e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14549
18359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1454918359
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3561529536
Short name T2096
Test name
Test status
Simulation time 191874397 ps
CPU time 0.9 seconds
Started Jun 29 06:39:54 PM PDT 24
Finished Jun 29 06:39:55 PM PDT 24
Peak memory 206176 kb
Host smart-28936389-8758-4cb0-9e3c-68f231cc831f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35615
29536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3561529536
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2034480014
Short name T58
Test name
Test status
Simulation time 168597578 ps
CPU time 0.8 seconds
Started Jun 29 06:40:12 PM PDT 24
Finished Jun 29 06:40:14 PM PDT 24
Peak memory 206196 kb
Host smart-d8c935f3-9522-43f0-b6de-6a49d779cc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20344
80014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2034480014
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1160451020
Short name T1094
Test name
Test status
Simulation time 190743765 ps
CPU time 0.85 seconds
Started Jun 29 06:40:01 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206196 kb
Host smart-bb778c8f-b6ec-467b-89af-3eec7d9e06c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11604
51020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1160451020
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2649685665
Short name T1432
Test name
Test status
Simulation time 192302260 ps
CPU time 0.83 seconds
Started Jun 29 06:40:00 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206196 kb
Host smart-bdd996ef-59f8-4165-9366-f943ebc10d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26496
85665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2649685665
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2743479771
Short name T1185
Test name
Test status
Simulation time 228985721 ps
CPU time 0.91 seconds
Started Jun 29 06:39:53 PM PDT 24
Finished Jun 29 06:39:54 PM PDT 24
Peak memory 206192 kb
Host smart-f9183d2e-d7e0-436e-8c21-c6899cb3e1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27434
79771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2743479771
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2307379231
Short name T2363
Test name
Test status
Simulation time 6068059417 ps
CPU time 173.59 seconds
Started Jun 29 06:40:02 PM PDT 24
Finished Jun 29 06:42:56 PM PDT 24
Peak memory 206488 kb
Host smart-8de0bffd-300f-4aa1-b6b3-6f0d54be4f26
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2307379231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2307379231
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3230080127
Short name T2124
Test name
Test status
Simulation time 185553206 ps
CPU time 0.83 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206172 kb
Host smart-f1d1fa5f-6447-48fa-92c0-09e449c9d39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
80127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3230080127
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1923593179
Short name T1370
Test name
Test status
Simulation time 156066752 ps
CPU time 0.86 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:39:57 PM PDT 24
Peak memory 206196 kb
Host smart-ad12580e-4237-41bd-9baf-9208ed82b49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19235
93179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1923593179
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2143467654
Short name T2443
Test name
Test status
Simulation time 5291909144 ps
CPU time 47.64 seconds
Started Jun 29 06:40:00 PM PDT 24
Finished Jun 29 06:40:48 PM PDT 24
Peak memory 206440 kb
Host smart-1f304079-f3dc-4439-aca7-0828d3885232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21434
67654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2143467654
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.857866843
Short name T2322
Test name
Test status
Simulation time 45422937 ps
CPU time 0.7 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:59 PM PDT 24
Peak memory 206180 kb
Host smart-76de59e4-0302-452f-8350-4482dab34971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=857866843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.857866843
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.193100532
Short name T1151
Test name
Test status
Simulation time 4329149674 ps
CPU time 5.01 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:40:01 PM PDT 24
Peak memory 206340 kb
Host smart-e92ca28d-4781-4a05-8806-09e1a129d64a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=193100532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.193100532
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1992771784
Short name T1605
Test name
Test status
Simulation time 13352016296 ps
CPU time 13.28 seconds
Started Jun 29 06:40:16 PM PDT 24
Finished Jun 29 06:40:30 PM PDT 24
Peak memory 206408 kb
Host smart-e9f1d010-5fd1-48cd-b639-930a52a77d29
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1992771784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1992771784
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.1946880884
Short name T936
Test name
Test status
Simulation time 23389808108 ps
CPU time 22.79 seconds
Started Jun 29 06:39:56 PM PDT 24
Finished Jun 29 06:40:20 PM PDT 24
Peak memory 206324 kb
Host smart-bcaa1955-e841-40a9-ba2f-daea30839c13
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1946880884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.1946880884
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1017693887
Short name T2053
Test name
Test status
Simulation time 185053776 ps
CPU time 0.87 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:06 PM PDT 24
Peak memory 206192 kb
Host smart-c63f6585-3606-4bc3-a34d-423c5b9614f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10176
93887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1017693887
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.3325330580
Short name T1781
Test name
Test status
Simulation time 143460316 ps
CPU time 0.77 seconds
Started Jun 29 06:40:14 PM PDT 24
Finished Jun 29 06:40:16 PM PDT 24
Peak memory 206196 kb
Host smart-3f071989-6575-48d5-ac3e-574a8a64cef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33253
30580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.3325330580
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.700062030
Short name T2445
Test name
Test status
Simulation time 251377347 ps
CPU time 0.94 seconds
Started Jun 29 06:39:59 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206200 kb
Host smart-e5c64d01-3ab5-47eb-950a-acff87939b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70006
2030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.700062030
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1105101693
Short name T1506
Test name
Test status
Simulation time 564965831 ps
CPU time 1.52 seconds
Started Jun 29 06:40:06 PM PDT 24
Finished Jun 29 06:40:09 PM PDT 24
Peak memory 206196 kb
Host smart-51d81524-a055-4537-b65e-0c891423908c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11051
01693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1105101693
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.4063799215
Short name T1206
Test name
Test status
Simulation time 14090677860 ps
CPU time 25.6 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:34 PM PDT 24
Peak memory 206504 kb
Host smart-7bdf9604-39a5-482a-bfd5-2e643c4bd4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40637
99215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.4063799215
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.3059152015
Short name T1811
Test name
Test status
Simulation time 310947101 ps
CPU time 1.08 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206208 kb
Host smart-2238619f-8a17-4d5c-bdf7-856a2b81255a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30591
52015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.3059152015
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.32951680
Short name T1300
Test name
Test status
Simulation time 156318014 ps
CPU time 0.81 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:39:56 PM PDT 24
Peak memory 206204 kb
Host smart-077918dd-b97f-4fe1-9d5f-92b480313852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32951
680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.32951680
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.4064061232
Short name T2056
Test name
Test status
Simulation time 30593421 ps
CPU time 0.69 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:59 PM PDT 24
Peak memory 205832 kb
Host smart-b3937963-c9ba-430a-83ab-54912e3ffe95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40640
61232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.4064061232
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3849275340
Short name T580
Test name
Test status
Simulation time 784008290 ps
CPU time 2.16 seconds
Started Jun 29 06:39:59 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206324 kb
Host smart-cf95f798-946f-4d5b-9437-fad650a7f4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38492
75340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3849275340
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2958402849
Short name T958
Test name
Test status
Simulation time 166592765 ps
CPU time 1.96 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206372 kb
Host smart-dedbadcc-f462-4d88-a586-999cb9b00220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29584
02849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2958402849
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3757794911
Short name T794
Test name
Test status
Simulation time 201911997 ps
CPU time 0.88 seconds
Started Jun 29 06:40:06 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206144 kb
Host smart-caa16778-2704-44ab-9663-083ff11a5b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37577
94911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3757794911
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1079954957
Short name T1786
Test name
Test status
Simulation time 158445275 ps
CPU time 0.79 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206180 kb
Host smart-65d81642-9d60-4228-9a4f-976b6516932b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10799
54957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1079954957
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4097813160
Short name T522
Test name
Test status
Simulation time 239057352 ps
CPU time 0.89 seconds
Started Jun 29 06:40:01 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206216 kb
Host smart-8a9d7e48-f4bb-4928-ad22-728b8400ef06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40978
13160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4097813160
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.1752948721
Short name T1813
Test name
Test status
Simulation time 7998231863 ps
CPU time 229.34 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:43:56 PM PDT 24
Peak memory 206480 kb
Host smart-f5eb69c7-70fc-42ba-8606-c7cf9b8f7b53
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1752948721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1752948721
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3079795681
Short name T520
Test name
Test status
Simulation time 236487226 ps
CPU time 0.91 seconds
Started Jun 29 06:40:11 PM PDT 24
Finished Jun 29 06:40:13 PM PDT 24
Peak memory 206196 kb
Host smart-4057025b-53a6-4128-9866-266514324983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30797
95681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3079795681
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.1545903037
Short name T476
Test name
Test status
Simulation time 23331164149 ps
CPU time 26.09 seconds
Started Jun 29 06:40:02 PM PDT 24
Finished Jun 29 06:40:29 PM PDT 24
Peak memory 206312 kb
Host smart-8fd73cdd-c8ab-411f-8f4f-6bc97d691f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15459
03037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.1545903037
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1468710903
Short name T1936
Test name
Test status
Simulation time 3271076998 ps
CPU time 3.73 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206256 kb
Host smart-05ecc494-7fb7-49d2-8ad6-242484538dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14687
10903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1468710903
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1662460603
Short name T1142
Test name
Test status
Simulation time 6089513435 ps
CPU time 58.04 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:41:04 PM PDT 24
Peak memory 206428 kb
Host smart-c9881033-c5a3-4bf6-90e7-98d5fd1c3ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16624
60603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1662460603
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3891699205
Short name T472
Test name
Test status
Simulation time 4756085901 ps
CPU time 131.43 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:42:08 PM PDT 24
Peak memory 206372 kb
Host smart-58baaa25-f1cb-441a-af35-327b10cb8e59
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3891699205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3891699205
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.7926326
Short name T556
Test name
Test status
Simulation time 258066638 ps
CPU time 0.92 seconds
Started Jun 29 06:40:01 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206180 kb
Host smart-3ec98863-970d-4e61-a004-7581c4c2b51a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=7926326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.7926326
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2395927544
Short name T2563
Test name
Test status
Simulation time 208921957 ps
CPU time 0.86 seconds
Started Jun 29 06:40:08 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206136 kb
Host smart-86b27739-e308-4d42-b663-bdf3d20b9cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23959
27544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2395927544
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.1049099472
Short name T996
Test name
Test status
Simulation time 6003929532 ps
CPU time 160.67 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:42:48 PM PDT 24
Peak memory 206408 kb
Host smart-d885132c-0f4f-4359-8b3c-d755dd47627a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10490
99472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.1049099472
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.34632366
Short name T1373
Test name
Test status
Simulation time 7521990181 ps
CPU time 56.37 seconds
Started Jun 29 06:40:01 PM PDT 24
Finished Jun 29 06:40:58 PM PDT 24
Peak memory 206504 kb
Host smart-47271a05-f1ba-4b55-8af6-ec49c4ddffe5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=34632366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.34632366
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2694059435
Short name T855
Test name
Test status
Simulation time 150878060 ps
CPU time 0.78 seconds
Started Jun 29 06:40:02 PM PDT 24
Finished Jun 29 06:40:03 PM PDT 24
Peak memory 206220 kb
Host smart-8ab9ab57-a9e5-4bab-abd2-e4f6b3184c16
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2694059435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2694059435
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2638061829
Short name T1728
Test name
Test status
Simulation time 163431067 ps
CPU time 0.77 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:40:05 PM PDT 24
Peak memory 206216 kb
Host smart-43cc4e44-e1de-4865-86ad-c2272c8825d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26380
61829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2638061829
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1203356679
Short name T127
Test name
Test status
Simulation time 246831998 ps
CPU time 0.92 seconds
Started Jun 29 06:40:17 PM PDT 24
Finished Jun 29 06:40:19 PM PDT 24
Peak memory 206196 kb
Host smart-16c56de7-5c0f-41e1-b23c-83113489780f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12033
56679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1203356679
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.817664475
Short name T23
Test name
Test status
Simulation time 163036316 ps
CPU time 0.83 seconds
Started Jun 29 06:40:25 PM PDT 24
Finished Jun 29 06:40:26 PM PDT 24
Peak memory 206120 kb
Host smart-ed7e8ae6-a6ff-49d3-9ec9-df3303207621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81766
4475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.817664475
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1608852460
Short name T2101
Test name
Test status
Simulation time 174943233 ps
CPU time 0.81 seconds
Started Jun 29 06:40:13 PM PDT 24
Finished Jun 29 06:40:14 PM PDT 24
Peak memory 206116 kb
Host smart-b0d0c47b-c371-4c2b-a7de-663edbdd43e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16088
52460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1608852460
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1054703258
Short name T2412
Test name
Test status
Simulation time 167204094 ps
CPU time 0.78 seconds
Started Jun 29 06:40:06 PM PDT 24
Finished Jun 29 06:40:09 PM PDT 24
Peak memory 206188 kb
Host smart-04417158-2890-4e0c-a3b8-e5e0b4221713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10547
03258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1054703258
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1359442051
Short name T789
Test name
Test status
Simulation time 154759319 ps
CPU time 0.78 seconds
Started Jun 29 06:40:11 PM PDT 24
Finished Jun 29 06:40:12 PM PDT 24
Peak memory 206200 kb
Host smart-eee26cb1-ffe9-44d5-a22f-b5ff99463a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13594
42051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1359442051
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3340440433
Short name T684
Test name
Test status
Simulation time 179239539 ps
CPU time 0.88 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206224 kb
Host smart-e9b40189-b1d3-4629-b47d-87150bcad25c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3340440433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3340440433
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3403259533
Short name T460
Test name
Test status
Simulation time 158145544 ps
CPU time 0.81 seconds
Started Jun 29 06:40:08 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206212 kb
Host smart-030cf57a-d172-4a80-92ba-89b4ac5a589c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34032
59533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3403259533
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3666135101
Short name T1235
Test name
Test status
Simulation time 74120578 ps
CPU time 0.69 seconds
Started Jun 29 06:39:59 PM PDT 24
Finished Jun 29 06:40:01 PM PDT 24
Peak memory 206212 kb
Host smart-1a91f526-7425-4493-8f48-9fcc7759ded2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36661
35101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3666135101
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2312638445
Short name T834
Test name
Test status
Simulation time 6538107706 ps
CPU time 16.54 seconds
Started Jun 29 06:40:27 PM PDT 24
Finished Jun 29 06:40:44 PM PDT 24
Peak memory 206452 kb
Host smart-933149ba-56e7-496b-b196-5e48f294a535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23126
38445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2312638445
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3148356120
Short name T2250
Test name
Test status
Simulation time 161199807 ps
CPU time 0.81 seconds
Started Jun 29 06:39:56 PM PDT 24
Finished Jun 29 06:39:57 PM PDT 24
Peak memory 206220 kb
Host smart-a748c57e-e9b0-4559-871f-434ce274d783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31483
56120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3148356120
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.495472464
Short name T375
Test name
Test status
Simulation time 152490454 ps
CPU time 0.78 seconds
Started Jun 29 06:40:06 PM PDT 24
Finished Jun 29 06:40:09 PM PDT 24
Peak memory 206212 kb
Host smart-b35df311-41f1-48d6-8841-a1660371c2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49547
2464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.495472464
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.3890206067
Short name T1243
Test name
Test status
Simulation time 189683313 ps
CPU time 0.81 seconds
Started Jun 29 06:40:10 PM PDT 24
Finished Jun 29 06:40:12 PM PDT 24
Peak memory 206132 kb
Host smart-eaff6b4f-4cc1-4d6f-82f9-e91c6fb22c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38902
06067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.3890206067
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.777876384
Short name T693
Test name
Test status
Simulation time 178771634 ps
CPU time 0.89 seconds
Started Jun 29 06:40:14 PM PDT 24
Finished Jun 29 06:40:15 PM PDT 24
Peak memory 206200 kb
Host smart-0328d43d-0811-4ad2-a184-66ad6462ff78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77787
6384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.777876384
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2005569818
Short name T1392
Test name
Test status
Simulation time 173537683 ps
CPU time 0.87 seconds
Started Jun 29 06:40:13 PM PDT 24
Finished Jun 29 06:40:15 PM PDT 24
Peak memory 206196 kb
Host smart-5468e35b-3113-4802-b693-24e0c7c146e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20055
69818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2005569818
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2167069274
Short name T2366
Test name
Test status
Simulation time 178541019 ps
CPU time 0.83 seconds
Started Jun 29 06:39:56 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206196 kb
Host smart-615cc264-134c-405f-946e-edf44a789bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21670
69274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2167069274
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.4109214469
Short name T1503
Test name
Test status
Simulation time 172321199 ps
CPU time 0.78 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:09 PM PDT 24
Peak memory 206196 kb
Host smart-b9b576b6-f151-4b58-9efa-c6434c8bae86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41092
14469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.4109214469
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2920334835
Short name T2484
Test name
Test status
Simulation time 243178662 ps
CPU time 1.08 seconds
Started Jun 29 06:39:56 PM PDT 24
Finished Jun 29 06:39:58 PM PDT 24
Peak memory 206220 kb
Host smart-be91eeee-bcb6-422c-989c-b437538609d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29203
34835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2920334835
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.4104180716
Short name T461
Test name
Test status
Simulation time 3814071753 ps
CPU time 26.29 seconds
Started Jun 29 06:40:06 PM PDT 24
Finished Jun 29 06:40:34 PM PDT 24
Peak memory 206424 kb
Host smart-d7f3d546-fc46-4919-8870-01c8dc8f425f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4104180716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.4104180716
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1050627080
Short name T154
Test name
Test status
Simulation time 158946530 ps
CPU time 0.8 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:09 PM PDT 24
Peak memory 206216 kb
Host smart-faac3a08-b88d-40ab-bf0c-33258df4cd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
27080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1050627080
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2971508525
Short name T1457
Test name
Test status
Simulation time 209724659 ps
CPU time 0.84 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 206188 kb
Host smart-85311cd7-4bba-4faa-bdeb-8da2a6b14e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29715
08525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2971508525
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1254820036
Short name T1093
Test name
Test status
Simulation time 3046038619 ps
CPU time 88.63 seconds
Started Jun 29 06:39:55 PM PDT 24
Finished Jun 29 06:41:25 PM PDT 24
Peak memory 206412 kb
Host smart-6d773f2e-bc31-4da6-85a8-5087ce356e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12548
20036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1254820036
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.115750052
Short name T2507
Test name
Test status
Simulation time 32857796 ps
CPU time 0.74 seconds
Started Jun 29 06:40:07 PM PDT 24
Finished Jun 29 06:40:09 PM PDT 24
Peak memory 206212 kb
Host smart-3d15c64e-e56f-4944-82cb-e3b7a22ab4d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=115750052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.115750052
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1264340538
Short name T757
Test name
Test status
Simulation time 4160945080 ps
CPU time 4.96 seconds
Started Jun 29 06:39:56 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206356 kb
Host smart-cacb9061-7eec-4f82-9251-7cf387603858
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1264340538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.1264340538
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.733578653
Short name T2151
Test name
Test status
Simulation time 13338130754 ps
CPU time 11.49 seconds
Started Jun 29 06:40:22 PM PDT 24
Finished Jun 29 06:40:34 PM PDT 24
Peak memory 206408 kb
Host smart-e886dac9-408a-4bcb-9c34-f9f4530ca31b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=733578653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.733578653
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1387993083
Short name T2293
Test name
Test status
Simulation time 23355488042 ps
CPU time 24.66 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:31 PM PDT 24
Peak memory 206284 kb
Host smart-34b1afbf-be5e-4e80-b718-3a1937c0418a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1387993083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1387993083
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.4086273989
Short name T1539
Test name
Test status
Simulation time 149449024 ps
CPU time 0.79 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206196 kb
Host smart-f6a6edd4-c091-4276-97a0-e6225bd8f53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40862
73989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.4086273989
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.3767271573
Short name T2520
Test name
Test status
Simulation time 201519719 ps
CPU time 0.83 seconds
Started Jun 29 06:40:00 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206196 kb
Host smart-5f845e23-96f8-4d01-b1c9-63ccf40a2034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37672
71573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.3767271573
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.3837553086
Short name T173
Test name
Test status
Simulation time 483454232 ps
CPU time 1.54 seconds
Started Jun 29 06:40:33 PM PDT 24
Finished Jun 29 06:40:35 PM PDT 24
Peak memory 206144 kb
Host smart-8885c339-af24-4dee-99a5-dd7bc8cf0f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38375
53086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.3837553086
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2160828877
Short name T1478
Test name
Test status
Simulation time 380340074 ps
CPU time 1.1 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:40:05 PM PDT 24
Peak memory 206196 kb
Host smart-57a02377-f062-4f71-8bc7-01125427a646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21608
28877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2160828877
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2004857202
Short name T945
Test name
Test status
Simulation time 14145745854 ps
CPU time 26.89 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:40:31 PM PDT 24
Peak memory 206436 kb
Host smart-ae0425d0-a964-4aa8-8002-ccd5960adfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20048
57202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2004857202
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1772995069
Short name T1325
Test name
Test status
Simulation time 437954680 ps
CPU time 1.51 seconds
Started Jun 29 06:40:26 PM PDT 24
Finished Jun 29 06:40:28 PM PDT 24
Peak memory 206188 kb
Host smart-6edb78b1-6fd3-4425-b1af-15a638e2c923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17729
95069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1772995069
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3554648932
Short name T746
Test name
Test status
Simulation time 150873579 ps
CPU time 0.8 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:00 PM PDT 24
Peak memory 206192 kb
Host smart-499d4b45-1135-469c-bc98-92740544d9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35546
48932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3554648932
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3436305969
Short name T1413
Test name
Test status
Simulation time 36301028 ps
CPU time 0.74 seconds
Started Jun 29 06:40:17 PM PDT 24
Finished Jun 29 06:40:18 PM PDT 24
Peak memory 206188 kb
Host smart-32e14809-9c3e-4567-9325-c3233904c609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34363
05969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3436305969
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2460777908
Short name T1382
Test name
Test status
Simulation time 1101983156 ps
CPU time 2.62 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 206284 kb
Host smart-407f309c-e03c-44ef-971a-90151329d26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24607
77908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2460777908
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3451554227
Short name T199
Test name
Test status
Simulation time 232164475 ps
CPU time 1.39 seconds
Started Jun 29 06:39:58 PM PDT 24
Finished Jun 29 06:40:01 PM PDT 24
Peak memory 206316 kb
Host smart-87f58369-8910-4479-b950-957a2f67914c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34515
54227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3451554227
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2116585868
Short name T1096
Test name
Test status
Simulation time 192205118 ps
CPU time 0.91 seconds
Started Jun 29 06:40:18 PM PDT 24
Finished Jun 29 06:40:20 PM PDT 24
Peak memory 206120 kb
Host smart-2c46685a-68bd-48b2-915c-96cb6522e5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21165
85868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2116585868
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.665559264
Short name T937
Test name
Test status
Simulation time 145119630 ps
CPU time 0.82 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:40:05 PM PDT 24
Peak memory 206208 kb
Host smart-f897830b-625d-450a-89a2-e880d1c14d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66555
9264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.665559264
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1079766997
Short name T318
Test name
Test status
Simulation time 211077537 ps
CPU time 0.9 seconds
Started Jun 29 06:40:09 PM PDT 24
Finished Jun 29 06:40:11 PM PDT 24
Peak memory 206208 kb
Host smart-d475af7b-85ef-45d5-9253-c4713af32a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10797
66997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1079766997
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3706893808
Short name T2027
Test name
Test status
Simulation time 254209101 ps
CPU time 0.93 seconds
Started Jun 29 06:39:57 PM PDT 24
Finished Jun 29 06:39:59 PM PDT 24
Peak memory 206192 kb
Host smart-b2b64d59-e92e-42bf-b2ab-76b8c8a3ad6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37068
93808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3706893808
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.202509581
Short name T632
Test name
Test status
Simulation time 23282836954 ps
CPU time 26.65 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:32 PM PDT 24
Peak memory 206308 kb
Host smart-db094f1f-44b5-4f15-b74a-7d725c14f3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20250
9581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.202509581
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2266623007
Short name T679
Test name
Test status
Simulation time 3336510867 ps
CPU time 3.63 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206256 kb
Host smart-8b5fe3c3-52d1-4480-8161-043205fb7ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22666
23007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2266623007
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1949880997
Short name T1896
Test name
Test status
Simulation time 9760654878 ps
CPU time 97.53 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:41:42 PM PDT 24
Peak memory 206428 kb
Host smart-b1208299-2b65-4c2e-a674-11b08b399bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19498
80997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1949880997
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.512458804
Short name T602
Test name
Test status
Simulation time 4307572355 ps
CPU time 116.37 seconds
Started Jun 29 06:40:00 PM PDT 24
Finished Jun 29 06:41:57 PM PDT 24
Peak memory 206456 kb
Host smart-536e4078-fe76-4ba2-ac3e-864b20f59427
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=512458804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.512458804
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3508958811
Short name T1427
Test name
Test status
Simulation time 245056794 ps
CPU time 0.94 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:40:05 PM PDT 24
Peak memory 206220 kb
Host smart-bfde25d6-0c07-481e-aedc-1015132c9c50
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3508958811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3508958811
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3766186857
Short name T810
Test name
Test status
Simulation time 180646728 ps
CPU time 0.92 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:40:05 PM PDT 24
Peak memory 206216 kb
Host smart-08317d64-eb15-4a40-abf0-a4958abe25fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37661
86857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3766186857
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.2157885488
Short name T1752
Test name
Test status
Simulation time 6007030554 ps
CPU time 167.61 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:42:51 PM PDT 24
Peak memory 206432 kb
Host smart-ba964390-d2d7-4519-ad00-c4cb7650df8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21578
85488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.2157885488
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.2158342450
Short name T1228
Test name
Test status
Simulation time 4096325833 ps
CPU time 115.01 seconds
Started Jun 29 06:40:06 PM PDT 24
Finished Jun 29 06:42:03 PM PDT 24
Peak memory 206460 kb
Host smart-9f70dac0-d4fd-4abe-a0ac-dad7b1487e7e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2158342450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.2158342450
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1996407432
Short name T2409
Test name
Test status
Simulation time 157765725 ps
CPU time 0.83 seconds
Started Jun 29 06:40:28 PM PDT 24
Finished Jun 29 06:40:29 PM PDT 24
Peak memory 206220 kb
Host smart-c53ac8e3-5901-4d5d-9f75-e80c4b277c0d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1996407432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1996407432
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1992297177
Short name T692
Test name
Test status
Simulation time 159768102 ps
CPU time 0.84 seconds
Started Jun 29 06:40:03 PM PDT 24
Finished Jun 29 06:40:06 PM PDT 24
Peak memory 206216 kb
Host smart-ae9e66e5-a240-467a-9d0e-2bdc90032899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19922
97177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1992297177
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3172098371
Short name T2358
Test name
Test status
Simulation time 225967548 ps
CPU time 0.91 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:06 PM PDT 24
Peak memory 206196 kb
Host smart-52a1ccf2-fdb3-4c4d-ac48-807f9f9b6f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31720
98371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3172098371
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2421554637
Short name T560
Test name
Test status
Simulation time 216591464 ps
CPU time 0.91 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206184 kb
Host smart-3c571e32-a849-4ce5-82b4-977c481e1ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24215
54637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2421554637
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.944986292
Short name T851
Test name
Test status
Simulation time 182127228 ps
CPU time 0.79 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206216 kb
Host smart-49e98785-89d1-42a8-9b92-8eb8dea922bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94498
6292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.944986292
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.198151451
Short name T1082
Test name
Test status
Simulation time 189374522 ps
CPU time 0.83 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206196 kb
Host smart-581dd49b-48c9-4a52-bee7-79cee05053f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815
1451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.198151451
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.295513225
Short name T2455
Test name
Test status
Simulation time 149232491 ps
CPU time 0.75 seconds
Started Jun 29 06:40:09 PM PDT 24
Finished Jun 29 06:40:11 PM PDT 24
Peak memory 206220 kb
Host smart-48137bf3-3722-4494-8421-e0ae2cbcf3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29551
3225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.295513225
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.963387369
Short name T1943
Test name
Test status
Simulation time 258231492 ps
CPU time 0.92 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:06 PM PDT 24
Peak memory 206224 kb
Host smart-a84b7b39-5ad2-4a63-ba7b-bab9a21f54d4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=963387369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.963387369
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3895709299
Short name T2472
Test name
Test status
Simulation time 143278632 ps
CPU time 0.77 seconds
Started Jun 29 06:40:06 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206188 kb
Host smart-8f33fd43-9963-450d-8188-133205b04b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
09299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3895709299
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1483091926
Short name T1167
Test name
Test status
Simulation time 73209504 ps
CPU time 0.7 seconds
Started Jun 29 06:40:25 PM PDT 24
Finished Jun 29 06:40:26 PM PDT 24
Peak memory 206212 kb
Host smart-b6b989e7-0c02-4aeb-9f60-3a65f422291b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14830
91926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1483091926
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2996897893
Short name T259
Test name
Test status
Simulation time 11488960015 ps
CPU time 24.24 seconds
Started Jun 29 06:40:29 PM PDT 24
Finished Jun 29 06:40:54 PM PDT 24
Peak memory 206420 kb
Host smart-c1c45921-938f-4e90-bcff-9064ac860206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29968
97893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2996897893
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3622716592
Short name T2435
Test name
Test status
Simulation time 162801441 ps
CPU time 0.83 seconds
Started Jun 29 06:40:27 PM PDT 24
Finished Jun 29 06:40:29 PM PDT 24
Peak memory 206192 kb
Host smart-a8411e1d-b038-4b63-9666-bde93c19e87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36227
16592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3622716592
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.994965476
Short name T2122
Test name
Test status
Simulation time 160959046 ps
CPU time 0.8 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206208 kb
Host smart-15cd9640-a8ac-4e88-8dad-f75d2971cb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99496
5476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.994965476
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.4277209469
Short name T678
Test name
Test status
Simulation time 225120552 ps
CPU time 0.9 seconds
Started Jun 29 06:40:05 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206216 kb
Host smart-2b82c004-49f4-4120-8d53-dd275d5decad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42772
09469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.4277209469
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.4084375069
Short name T1084
Test name
Test status
Simulation time 171109621 ps
CPU time 0.86 seconds
Started Jun 29 06:40:16 PM PDT 24
Finished Jun 29 06:40:18 PM PDT 24
Peak memory 206188 kb
Host smart-b57b6c00-d350-4075-9b58-21d7fac01647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40843
75069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.4084375069
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2409703927
Short name T1548
Test name
Test status
Simulation time 178818353 ps
CPU time 0.8 seconds
Started Jun 29 06:40:27 PM PDT 24
Finished Jun 29 06:40:28 PM PDT 24
Peak memory 206192 kb
Host smart-2c39a0f3-a99a-4956-b22f-98edbbe88bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24097
03927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2409703927
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.625720754
Short name T581
Test name
Test status
Simulation time 174787200 ps
CPU time 0.77 seconds
Started Jun 29 06:40:31 PM PDT 24
Finished Jun 29 06:40:32 PM PDT 24
Peak memory 206196 kb
Host smart-e8dcac67-9382-47f1-9567-88c8baf89bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62572
0754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.625720754
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.633756958
Short name T2114
Test name
Test status
Simulation time 158673321 ps
CPU time 0.8 seconds
Started Jun 29 06:40:25 PM PDT 24
Finished Jun 29 06:40:26 PM PDT 24
Peak memory 206192 kb
Host smart-85217fa1-1b57-4e71-bc01-f9656322f4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63375
6958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.633756958
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.288846631
Short name T1436
Test name
Test status
Simulation time 218910038 ps
CPU time 1.02 seconds
Started Jun 29 06:40:04 PM PDT 24
Finished Jun 29 06:40:07 PM PDT 24
Peak memory 206216 kb
Host smart-0e68fbe2-f399-43fe-b6ab-34185a652553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28884
6631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.288846631
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.2556480905
Short name T2067
Test name
Test status
Simulation time 2928102652 ps
CPU time 79.98 seconds
Started Jun 29 06:40:06 PM PDT 24
Finished Jun 29 06:41:28 PM PDT 24
Peak memory 206444 kb
Host smart-b6d8f054-d136-4a2c-8be7-93e729343fda
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2556480905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.2556480905
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1385665224
Short name T2554
Test name
Test status
Simulation time 173442067 ps
CPU time 0.81 seconds
Started Jun 29 06:40:14 PM PDT 24
Finished Jun 29 06:40:15 PM PDT 24
Peak memory 206224 kb
Host smart-f6aa0d0e-b6c4-4dab-9335-214a82c166d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
65224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1385665224
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.446550850
Short name T362
Test name
Test status
Simulation time 156071578 ps
CPU time 0.78 seconds
Started Jun 29 06:40:06 PM PDT 24
Finished Jun 29 06:40:08 PM PDT 24
Peak memory 206160 kb
Host smart-d01aacb2-86ad-4d62-92ab-acfbf12bd92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44655
0850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.446550850
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.971314147
Short name T1465
Test name
Test status
Simulation time 3100574803 ps
CPU time 22.53 seconds
Started Jun 29 06:40:08 PM PDT 24
Finished Jun 29 06:40:32 PM PDT 24
Peak memory 206468 kb
Host smart-97b9fd10-e447-43b8-bc61-14c8892a7c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97131
4147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.971314147
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.3540385946
Short name T979
Test name
Test status
Simulation time 50662928 ps
CPU time 0.67 seconds
Started Jun 29 06:34:33 PM PDT 24
Finished Jun 29 06:34:34 PM PDT 24
Peak memory 206212 kb
Host smart-ac4046b2-d95c-4eb1-b94f-0880c5550912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3540385946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3540385946
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2110482480
Short name T2373
Test name
Test status
Simulation time 4171972344 ps
CPU time 5.65 seconds
Started Jun 29 06:34:29 PM PDT 24
Finished Jun 29 06:34:35 PM PDT 24
Peak memory 206272 kb
Host smart-659408b7-18fe-4ff7-beea-8eebc549e3a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2110482480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.2110482480
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2020416490
Short name T1993
Test name
Test status
Simulation time 13356158099 ps
CPU time 16.21 seconds
Started Jun 29 06:34:23 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 206292 kb
Host smart-f833247b-6069-42db-aeb1-b75fbbea2a23
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2020416490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2020416490
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3391897833
Short name T15
Test name
Test status
Simulation time 23319491079 ps
CPU time 26.27 seconds
Started Jun 29 06:34:23 PM PDT 24
Finished Jun 29 06:34:50 PM PDT 24
Peak memory 206404 kb
Host smart-b370ba7d-7bd7-4d98-b597-eccfde2e3f99
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3391897833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.3391897833
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.437329068
Short name T1023
Test name
Test status
Simulation time 188625442 ps
CPU time 0.83 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:27 PM PDT 24
Peak memory 206120 kb
Host smart-15c619ae-670e-4f0f-9371-b6f4daf4e206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43732
9068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.437329068
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.472630589
Short name T543
Test name
Test status
Simulation time 184827905 ps
CPU time 0.83 seconds
Started Jun 29 06:34:27 PM PDT 24
Finished Jun 29 06:34:29 PM PDT 24
Peak memory 206196 kb
Host smart-27774d64-cba8-4a36-b6d8-102b7c83296c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47263
0589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.472630589
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.1910841323
Short name T1508
Test name
Test status
Simulation time 279546906 ps
CPU time 1 seconds
Started Jun 29 06:34:27 PM PDT 24
Finished Jun 29 06:34:29 PM PDT 24
Peak memory 206196 kb
Host smart-ae5f9203-c5a1-495b-8fa1-ac9ce2d928c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19108
41323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.1910841323
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2921968975
Short name T2593
Test name
Test status
Simulation time 658381168 ps
CPU time 1.52 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206196 kb
Host smart-8bba5dc3-e508-4fb4-8fce-b7590fd43a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29219
68975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2921968975
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.4124632127
Short name T2223
Test name
Test status
Simulation time 5981061053 ps
CPU time 10.55 seconds
Started Jun 29 06:34:27 PM PDT 24
Finished Jun 29 06:34:38 PM PDT 24
Peak memory 206448 kb
Host smart-3be0251c-948d-40cd-8bdd-1429a3e6d00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41246
32127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.4124632127
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.527774444
Short name T2185
Test name
Test status
Simulation time 379632737 ps
CPU time 1.62 seconds
Started Jun 29 06:34:24 PM PDT 24
Finished Jun 29 06:34:26 PM PDT 24
Peak memory 206164 kb
Host smart-b2a96106-31aa-4131-a329-2bfd6b62b1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52777
4444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.527774444
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.405522040
Short name T1424
Test name
Test status
Simulation time 205111243 ps
CPU time 0.86 seconds
Started Jun 29 06:34:27 PM PDT 24
Finished Jun 29 06:34:29 PM PDT 24
Peak memory 206368 kb
Host smart-214e12a9-356b-4b89-9c56-93d38dd97ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40552
2040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.405522040
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.4234861906
Short name T969
Test name
Test status
Simulation time 55129699 ps
CPU time 0.68 seconds
Started Jun 29 06:34:30 PM PDT 24
Finished Jun 29 06:34:31 PM PDT 24
Peak memory 206204 kb
Host smart-9dc36c6b-87f9-427d-8777-b170ce26134d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348
61906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.4234861906
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.791940463
Short name T2468
Test name
Test status
Simulation time 959232090 ps
CPU time 2.2 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:29 PM PDT 24
Peak memory 206376 kb
Host smart-d98165ef-3578-4905-8c78-c84a72549e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79194
0463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.791940463
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.4217129531
Short name T1976
Test name
Test status
Simulation time 182898010 ps
CPU time 1.97 seconds
Started Jun 29 06:34:27 PM PDT 24
Finished Jun 29 06:34:30 PM PDT 24
Peak memory 206272 kb
Host smart-a67f8341-9509-491d-9f2b-79ee58de3f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42171
29531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4217129531
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2960517415
Short name T2106
Test name
Test status
Simulation time 253584062 ps
CPU time 0.97 seconds
Started Jun 29 06:34:30 PM PDT 24
Finished Jun 29 06:34:31 PM PDT 24
Peak memory 206212 kb
Host smart-766b488c-798c-4147-8963-aa344407b0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29605
17415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2960517415
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.579578981
Short name T1597
Test name
Test status
Simulation time 152824228 ps
CPU time 0.84 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:26 PM PDT 24
Peak memory 206200 kb
Host smart-28d8d2e5-fa75-4ca1-a124-d3138e626aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57957
8981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.579578981
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3641817709
Short name T1203
Test name
Test status
Simulation time 228856545 ps
CPU time 0.9 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:27 PM PDT 24
Peak memory 206204 kb
Host smart-04afed71-b869-4ee4-9ce1-484022c7e762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36418
17709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3641817709
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3863735548
Short name T1055
Test name
Test status
Simulation time 211507031 ps
CPU time 0.87 seconds
Started Jun 29 06:34:27 PM PDT 24
Finished Jun 29 06:34:29 PM PDT 24
Peak memory 206140 kb
Host smart-6f5d6093-4c84-45f1-8d61-ce57c5b3fbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38637
35548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3863735548
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.3859241903
Short name T1401
Test name
Test status
Simulation time 23364569654 ps
CPU time 23.63 seconds
Started Jun 29 06:34:29 PM PDT 24
Finished Jun 29 06:34:53 PM PDT 24
Peak memory 206288 kb
Host smart-d977b956-a693-4dc4-a667-55290b2ba48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38592
41903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.3859241903
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1477117078
Short name T2297
Test name
Test status
Simulation time 3305771297 ps
CPU time 3.66 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:34:31 PM PDT 24
Peak memory 206264 kb
Host smart-0202f6ea-c285-4409-8a41-643f249a1579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14771
17078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1477117078
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.32794509
Short name T2465
Test name
Test status
Simulation time 10472685324 ps
CPU time 301.29 seconds
Started Jun 29 06:34:28 PM PDT 24
Finished Jun 29 06:39:30 PM PDT 24
Peak memory 206496 kb
Host smart-2dfc9d02-98c0-4b60-b06c-796de20f8044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32794
509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.32794509
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1186301072
Short name T2420
Test name
Test status
Simulation time 7527707962 ps
CPU time 53.12 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:35:19 PM PDT 24
Peak memory 206412 kb
Host smart-bca2a0f2-b850-44f9-a5b0-cb0d915405c3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1186301072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1186301072
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2437684688
Short name T610
Test name
Test status
Simulation time 239987944 ps
CPU time 0.98 seconds
Started Jun 29 06:34:29 PM PDT 24
Finished Jun 29 06:34:31 PM PDT 24
Peak memory 206212 kb
Host smart-2f6d799f-ef97-4d59-b135-1d0a7e1e0a71
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2437684688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2437684688
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3942907620
Short name T1468
Test name
Test status
Simulation time 202475577 ps
CPU time 0.96 seconds
Started Jun 29 06:34:29 PM PDT 24
Finished Jun 29 06:34:30 PM PDT 24
Peak memory 206164 kb
Host smart-c7321c3b-adb5-4ff2-9d06-dba1bb8cf6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39429
07620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3942907620
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1361555881
Short name T378
Test name
Test status
Simulation time 4199327802 ps
CPU time 39.58 seconds
Started Jun 29 06:34:23 PM PDT 24
Finished Jun 29 06:35:04 PM PDT 24
Peak memory 206416 kb
Host smart-3ddfa128-aaa9-457c-8043-5f28e700a70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
55881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1361555881
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.965442975
Short name T733
Test name
Test status
Simulation time 4680840509 ps
CPU time 121.22 seconds
Started Jun 29 06:34:28 PM PDT 24
Finished Jun 29 06:36:30 PM PDT 24
Peak memory 206456 kb
Host smart-38d4e308-ff3e-4a63-911b-f98e48691c8b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=965442975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.965442975
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.1254110728
Short name T1344
Test name
Test status
Simulation time 153483952 ps
CPU time 0.88 seconds
Started Jun 29 06:34:30 PM PDT 24
Finished Jun 29 06:34:32 PM PDT 24
Peak memory 206220 kb
Host smart-6fc96e01-5d52-4e94-9e04-51e417745755
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1254110728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.1254110728
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.279332321
Short name T1657
Test name
Test status
Simulation time 158768367 ps
CPU time 0.78 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206204 kb
Host smart-641f9e8e-b900-4d08-b0b5-95d2021bb63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27933
2321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.279332321
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.183985421
Short name T148
Test name
Test status
Simulation time 200521824 ps
CPU time 0.89 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206216 kb
Host smart-a4aec49c-1b6e-459b-97e8-b40220951d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18398
5421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.183985421
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.334940530
Short name T103
Test name
Test status
Simulation time 161062064 ps
CPU time 0.83 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:27 PM PDT 24
Peak memory 206216 kb
Host smart-44854a9f-bc0b-44b7-8b6e-a8ba51fa4c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33494
0530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.334940530
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2675331961
Short name T367
Test name
Test status
Simulation time 227696583 ps
CPU time 0.87 seconds
Started Jun 29 06:34:30 PM PDT 24
Finished Jun 29 06:34:31 PM PDT 24
Peak memory 206208 kb
Host smart-181cdca3-7207-46c8-9c20-8c3898ebc166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26753
31961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2675331961
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.4276579786
Short name T699
Test name
Test status
Simulation time 154716688 ps
CPU time 0.8 seconds
Started Jun 29 06:34:27 PM PDT 24
Finished Jun 29 06:34:29 PM PDT 24
Peak memory 206176 kb
Host smart-28596a1b-ecb6-4ac2-8727-ed1a5d367492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42765
79786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.4276579786
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2178605259
Short name T180
Test name
Test status
Simulation time 197568491 ps
CPU time 0.84 seconds
Started Jun 29 06:34:29 PM PDT 24
Finished Jun 29 06:34:30 PM PDT 24
Peak memory 206392 kb
Host smart-e399acf2-face-4ae0-8111-b20acb31d8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21786
05259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2178605259
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.3383254790
Short name T2590
Test name
Test status
Simulation time 234926110 ps
CPU time 1 seconds
Started Jun 29 06:34:23 PM PDT 24
Finished Jun 29 06:34:24 PM PDT 24
Peak memory 206224 kb
Host smart-e4e24d7e-32ab-4cf4-95fa-9036c258f572
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3383254790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.3383254790
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.753018801
Short name T1834
Test name
Test status
Simulation time 154638693 ps
CPU time 0.79 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:27 PM PDT 24
Peak memory 206196 kb
Host smart-f364e452-127e-4731-b4bc-3caa12652d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75301
8801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.753018801
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1697214418
Short name T1334
Test name
Test status
Simulation time 49690629 ps
CPU time 0.68 seconds
Started Jun 29 06:34:25 PM PDT 24
Finished Jun 29 06:34:26 PM PDT 24
Peak memory 206212 kb
Host smart-1cf619ba-a9cf-4f09-84fd-50e998a90cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16972
14418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1697214418
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1578172130
Short name T1551
Test name
Test status
Simulation time 22319300878 ps
CPU time 54.75 seconds
Started Jun 29 06:34:24 PM PDT 24
Finished Jun 29 06:35:19 PM PDT 24
Peak memory 206468 kb
Host smart-2ae97b3e-5917-4686-b3bb-78ded30662a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15781
72130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1578172130
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1148698508
Short name T881
Test name
Test status
Simulation time 194605381 ps
CPU time 0.86 seconds
Started Jun 29 06:34:26 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206212 kb
Host smart-cf7bcf97-aa92-4533-947b-97fbc7b7a91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11486
98508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1148698508
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.669602188
Short name T1385
Test name
Test status
Simulation time 243519185 ps
CPU time 0.96 seconds
Started Jun 29 06:34:28 PM PDT 24
Finished Jun 29 06:34:30 PM PDT 24
Peak memory 206204 kb
Host smart-082b3b30-7571-4e08-8339-efad7e9ed753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66960
2188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.669602188
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1195530050
Short name T1586
Test name
Test status
Simulation time 11480120722 ps
CPU time 74.95 seconds
Started Jun 29 06:34:32 PM PDT 24
Finished Jun 29 06:35:48 PM PDT 24
Peak memory 206420 kb
Host smart-e81c3231-9855-422d-84d9-d7cebdd803de
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1195530050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1195530050
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1138308935
Short name T376
Test name
Test status
Simulation time 12988837515 ps
CPU time 264.38 seconds
Started Jun 29 06:34:35 PM PDT 24
Finished Jun 29 06:38:59 PM PDT 24
Peak memory 206500 kb
Host smart-6696a949-8fec-4777-9650-fab88656e374
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1138308935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1138308935
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2061847917
Short name T1416
Test name
Test status
Simulation time 209828126 ps
CPU time 0.83 seconds
Started Jun 29 06:34:27 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 206192 kb
Host smart-09a7f917-a5bd-457c-84ff-1da446f74d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20618
47917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2061847917
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1350969940
Short name T2606
Test name
Test status
Simulation time 201864406 ps
CPU time 0.81 seconds
Started Jun 29 06:34:32 PM PDT 24
Finished Jun 29 06:34:33 PM PDT 24
Peak memory 206200 kb
Host smart-34a3c0c6-1861-4d0d-9211-d85e166ab25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13509
69940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1350969940
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.773328548
Short name T1540
Test name
Test status
Simulation time 146981249 ps
CPU time 0.83 seconds
Started Jun 29 06:34:33 PM PDT 24
Finished Jun 29 06:34:35 PM PDT 24
Peak memory 206192 kb
Host smart-06d68da1-9ec2-4196-a22e-3987bb00c208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77332
8548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.773328548
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3222477257
Short name T1552
Test name
Test status
Simulation time 166040070 ps
CPU time 0.78 seconds
Started Jun 29 06:34:31 PM PDT 24
Finished Jun 29 06:34:32 PM PDT 24
Peak memory 206196 kb
Host smart-24a16ce9-5f5a-4efa-a1cb-c290fd69e56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32224
77257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3222477257
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3230631136
Short name T1122
Test name
Test status
Simulation time 150785979 ps
CPU time 0.81 seconds
Started Jun 29 06:34:36 PM PDT 24
Finished Jun 29 06:34:37 PM PDT 24
Peak memory 206156 kb
Host smart-3bb33ca4-9d26-4925-ac1b-043c0c62328a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32306
31136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3230631136
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1122387400
Short name T2211
Test name
Test status
Simulation time 199614474 ps
CPU time 0.9 seconds
Started Jun 29 06:34:31 PM PDT 24
Finished Jun 29 06:34:33 PM PDT 24
Peak memory 206216 kb
Host smart-519b2d11-2a39-4c2b-89b3-0cf031e7ac9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11223
87400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1122387400
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.4075072035
Short name T423
Test name
Test status
Simulation time 4794377048 ps
CPU time 135.32 seconds
Started Jun 29 06:34:33 PM PDT 24
Finished Jun 29 06:36:49 PM PDT 24
Peak memory 206504 kb
Host smart-acc471f6-ef33-4173-b65f-5f49c0a193e4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4075072035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.4075072035
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.887758420
Short name T1729
Test name
Test status
Simulation time 190259996 ps
CPU time 0.86 seconds
Started Jun 29 06:34:34 PM PDT 24
Finished Jun 29 06:34:36 PM PDT 24
Peak memory 206220 kb
Host smart-ecc7c926-5658-405d-b611-a9c06da65c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88775
8420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.887758420
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3032269816
Short name T1693
Test name
Test status
Simulation time 171952018 ps
CPU time 0.79 seconds
Started Jun 29 06:34:31 PM PDT 24
Finished Jun 29 06:34:32 PM PDT 24
Peak memory 206196 kb
Host smart-82b8751e-c062-4453-bd59-6b867dc36908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30322
69816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3032269816
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3556271913
Short name T1841
Test name
Test status
Simulation time 4317280261 ps
CPU time 120.53 seconds
Started Jun 29 06:34:35 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206440 kb
Host smart-936bb86b-ee87-4092-98f5-c22a2b83519a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35562
71913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3556271913
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1260350874
Short name T923
Test name
Test status
Simulation time 36626051 ps
CPU time 0.71 seconds
Started Jun 29 06:34:41 PM PDT 24
Finished Jun 29 06:34:42 PM PDT 24
Peak memory 206204 kb
Host smart-4aea5f52-b7e7-4fc5-900b-e88731a4124b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1260350874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1260350874
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.966931651
Short name T565
Test name
Test status
Simulation time 4107751799 ps
CPU time 4.46 seconds
Started Jun 29 06:34:32 PM PDT 24
Finished Jun 29 06:34:38 PM PDT 24
Peak memory 206404 kb
Host smart-de81793e-b767-4650-80d6-ae09604590d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=966931651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.966931651
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.2047060240
Short name T1437
Test name
Test status
Simulation time 13334309516 ps
CPU time 12.74 seconds
Started Jun 29 06:34:36 PM PDT 24
Finished Jun 29 06:34:49 PM PDT 24
Peak memory 206460 kb
Host smart-8d745ba0-cc4c-4b23-9468-2d023156bcef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2047060240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.2047060240
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3759966136
Short name T715
Test name
Test status
Simulation time 23358103657 ps
CPU time 23.13 seconds
Started Jun 29 06:34:34 PM PDT 24
Finished Jun 29 06:34:57 PM PDT 24
Peak memory 206328 kb
Host smart-b047c45f-90c2-485b-a160-bb64c896d925
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3759966136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3759966136
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1108638314
Short name T641
Test name
Test status
Simulation time 153464146 ps
CPU time 0.8 seconds
Started Jun 29 06:34:38 PM PDT 24
Finished Jun 29 06:34:39 PM PDT 24
Peak memory 206208 kb
Host smart-c9cfe41f-9f22-4681-b52e-5560b93bf849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11086
38314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1108638314
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3535346588
Short name T1589
Test name
Test status
Simulation time 135242023 ps
CPU time 0.73 seconds
Started Jun 29 06:34:29 PM PDT 24
Finished Jun 29 06:34:30 PM PDT 24
Peak memory 206204 kb
Host smart-02507515-6fde-480f-91aa-dc6e2af8616f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35353
46588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3535346588
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.53304366
Short name T955
Test name
Test status
Simulation time 374569958 ps
CPU time 1.27 seconds
Started Jun 29 06:34:32 PM PDT 24
Finished Jun 29 06:34:34 PM PDT 24
Peak memory 206192 kb
Host smart-5199d58a-6ac7-4689-ac4f-56ac6185cc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53304
366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.53304366
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.395402359
Short name T164
Test name
Test status
Simulation time 1303300268 ps
CPU time 3.05 seconds
Started Jun 29 06:34:37 PM PDT 24
Finished Jun 29 06:34:41 PM PDT 24
Peak memory 206284 kb
Host smart-5a6494e8-0271-4e59-9b29-23ec519a43f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39540
2359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.395402359
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.982435098
Short name T2063
Test name
Test status
Simulation time 17580216946 ps
CPU time 34.15 seconds
Started Jun 29 06:34:35 PM PDT 24
Finished Jun 29 06:35:10 PM PDT 24
Peak memory 206456 kb
Host smart-f1849e8e-6909-4d9b-a5bb-56c79bbd924b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98243
5098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.982435098
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.310577203
Short name T1360
Test name
Test status
Simulation time 457446545 ps
CPU time 1.55 seconds
Started Jun 29 06:34:35 PM PDT 24
Finished Jun 29 06:34:37 PM PDT 24
Peak memory 206220 kb
Host smart-2142a447-56f4-499a-819f-f28ffbd94959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31057
7203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.310577203
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.1944706317
Short name T1244
Test name
Test status
Simulation time 143319117 ps
CPU time 0.77 seconds
Started Jun 29 06:34:32 PM PDT 24
Finished Jun 29 06:34:33 PM PDT 24
Peak memory 206200 kb
Host smart-c6d21b6d-39c9-4091-bae0-6d9a23f2ea00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19447
06317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.1944706317
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1376472199
Short name T1361
Test name
Test status
Simulation time 49843462 ps
CPU time 0.69 seconds
Started Jun 29 06:34:36 PM PDT 24
Finished Jun 29 06:34:37 PM PDT 24
Peak memory 206172 kb
Host smart-20fdbc46-f1d8-4415-a683-32c937f87507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13764
72199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1376472199
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.827028040
Short name T1455
Test name
Test status
Simulation time 861115360 ps
CPU time 2.06 seconds
Started Jun 29 06:34:35 PM PDT 24
Finished Jun 29 06:34:38 PM PDT 24
Peak memory 206340 kb
Host smart-e20b0094-c757-4dbb-978e-6c6b00dfa3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82702
8040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.827028040
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3343875
Short name T2077
Test name
Test status
Simulation time 219924512 ps
CPU time 1.44 seconds
Started Jun 29 06:34:30 PM PDT 24
Finished Jun 29 06:34:32 PM PDT 24
Peak memory 206300 kb
Host smart-4db8341d-d251-4957-972c-0482fcf0e5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33438
75 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3343875
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2477762582
Short name T2306
Test name
Test status
Simulation time 192286797 ps
CPU time 0.83 seconds
Started Jun 29 06:34:32 PM PDT 24
Finished Jun 29 06:34:34 PM PDT 24
Peak memory 206216 kb
Host smart-8116dcf1-7c70-470a-af6d-7e1dd8973249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24777
62582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2477762582
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3885370627
Short name T1543
Test name
Test status
Simulation time 181442745 ps
CPU time 0.8 seconds
Started Jun 29 06:34:36 PM PDT 24
Finished Jun 29 06:34:37 PM PDT 24
Peak memory 206176 kb
Host smart-bfd19ffd-6c8d-4087-9ca0-b269a6b521c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38853
70627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3885370627
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3980868132
Short name T1329
Test name
Test status
Simulation time 164277899 ps
CPU time 0.81 seconds
Started Jun 29 06:34:31 PM PDT 24
Finished Jun 29 06:34:32 PM PDT 24
Peak memory 206200 kb
Host smart-5600630b-55b6-4ec0-9902-c10c0a050d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39808
68132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3980868132
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.4192843444
Short name T1576
Test name
Test status
Simulation time 278723062 ps
CPU time 0.93 seconds
Started Jun 29 06:34:34 PM PDT 24
Finished Jun 29 06:34:35 PM PDT 24
Peak memory 206196 kb
Host smart-e85e7528-853a-4e04-996c-fef077be3f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41928
43444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.4192843444
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.1121716445
Short name T578
Test name
Test status
Simulation time 23322639402 ps
CPU time 21.37 seconds
Started Jun 29 06:34:32 PM PDT 24
Finished Jun 29 06:34:54 PM PDT 24
Peak memory 206316 kb
Host smart-41a44b5c-37be-4c60-9865-1e50e98ec6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11217
16445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.1121716445
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.2335617794
Short name T1013
Test name
Test status
Simulation time 3339343560 ps
CPU time 3.85 seconds
Started Jun 29 06:34:36 PM PDT 24
Finished Jun 29 06:34:41 PM PDT 24
Peak memory 206228 kb
Host smart-5b897fcc-ee1b-42e5-8677-3d10418e4a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23356
17794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.2335617794
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2297925753
Short name T1774
Test name
Test status
Simulation time 8108462522 ps
CPU time 79.67 seconds
Started Jun 29 06:34:36 PM PDT 24
Finished Jun 29 06:35:57 PM PDT 24
Peak memory 206428 kb
Host smart-3fde8db0-3b32-4565-9a9a-b98ff03d3ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22979
25753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2297925753
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.4133686887
Short name T1907
Test name
Test status
Simulation time 4562191222 ps
CPU time 125.92 seconds
Started Jun 29 06:34:30 PM PDT 24
Finished Jun 29 06:36:37 PM PDT 24
Peak memory 206460 kb
Host smart-a75cf9ec-426a-4548-836d-a01eb1a6d8c6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4133686887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.4133686887
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2434448317
Short name T1719
Test name
Test status
Simulation time 248196873 ps
CPU time 0.95 seconds
Started Jun 29 06:34:35 PM PDT 24
Finished Jun 29 06:34:36 PM PDT 24
Peak memory 206220 kb
Host smart-3cb947c6-3d1e-4117-8819-44687127972b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2434448317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2434448317
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2564894339
Short name T2437
Test name
Test status
Simulation time 186472447 ps
CPU time 0.87 seconds
Started Jun 29 06:34:33 PM PDT 24
Finished Jun 29 06:34:35 PM PDT 24
Peak memory 206216 kb
Host smart-d95277b9-3a78-4377-9ad6-326504948fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25648
94339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2564894339
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3213604195
Short name T558
Test name
Test status
Simulation time 3654576413 ps
CPU time 100.18 seconds
Started Jun 29 06:34:31 PM PDT 24
Finished Jun 29 06:36:12 PM PDT 24
Peak memory 206460 kb
Host smart-0d5f2bb9-09c9-4927-b2c3-c0104b4c3033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32136
04195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3213604195
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3353143611
Short name T1321
Test name
Test status
Simulation time 3535377566 ps
CPU time 97.05 seconds
Started Jun 29 06:34:35 PM PDT 24
Finished Jun 29 06:36:13 PM PDT 24
Peak memory 206460 kb
Host smart-5c38bfd9-99a7-4e71-9091-2e4e47e30d74
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3353143611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3353143611
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.1549518031
Short name T345
Test name
Test status
Simulation time 168988373 ps
CPU time 0.85 seconds
Started Jun 29 06:34:29 PM PDT 24
Finished Jun 29 06:34:31 PM PDT 24
Peak memory 206220 kb
Host smart-f95d6ab3-9854-4d17-a16d-3f6c4baac4a3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1549518031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.1549518031
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2331432322
Short name T21
Test name
Test status
Simulation time 146882764 ps
CPU time 0.77 seconds
Started Jun 29 06:34:33 PM PDT 24
Finished Jun 29 06:34:34 PM PDT 24
Peak memory 206216 kb
Host smart-2cfce72b-fada-49fc-8b27-372b76f73879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23314
32322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2331432322
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1139318055
Short name T2153
Test name
Test status
Simulation time 215624750 ps
CPU time 0.86 seconds
Started Jun 29 06:34:32 PM PDT 24
Finished Jun 29 06:34:33 PM PDT 24
Peak memory 206216 kb
Host smart-392501e9-7844-4152-a233-195971defc89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11393
18055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1139318055
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2384001663
Short name T989
Test name
Test status
Simulation time 191194427 ps
CPU time 0.82 seconds
Started Jun 29 06:34:31 PM PDT 24
Finished Jun 29 06:34:32 PM PDT 24
Peak memory 206204 kb
Host smart-16ab6513-7a3e-4d1f-b11d-e3d63b0fb3a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23840
01663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2384001663
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3239351156
Short name T352
Test name
Test status
Simulation time 166259619 ps
CPU time 0.83 seconds
Started Jun 29 06:34:29 PM PDT 24
Finished Jun 29 06:34:31 PM PDT 24
Peak memory 206216 kb
Host smart-4c87c9d7-0cd4-4e5e-a403-109f19d3a810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32393
51156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3239351156
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.536586903
Short name T2285
Test name
Test status
Simulation time 163035606 ps
CPU time 0.88 seconds
Started Jun 29 06:34:36 PM PDT 24
Finished Jun 29 06:34:38 PM PDT 24
Peak memory 206196 kb
Host smart-1bd17f8f-bb89-4934-b105-cef7f138b635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53658
6903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.536586903
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3356363986
Short name T877
Test name
Test status
Simulation time 170053169 ps
CPU time 0.88 seconds
Started Jun 29 06:34:41 PM PDT 24
Finished Jun 29 06:34:43 PM PDT 24
Peak memory 206212 kb
Host smart-6725a15a-e6a9-45fd-a90d-6a91403e1e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33563
63986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3356363986
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.550686875
Short name T1065
Test name
Test status
Simulation time 261866140 ps
CPU time 1.02 seconds
Started Jun 29 06:34:38 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 206200 kb
Host smart-6bf07943-d961-49ef-9617-cbbe3502d1c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=550686875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.550686875
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.781761963
Short name T205
Test name
Test status
Simulation time 165094464 ps
CPU time 0.75 seconds
Started Jun 29 06:34:41 PM PDT 24
Finished Jun 29 06:34:42 PM PDT 24
Peak memory 206184 kb
Host smart-910b578d-c16f-4194-9e5d-e6fc73dfb223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78176
1963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.781761963
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.512841833
Short name T1252
Test name
Test status
Simulation time 45858433 ps
CPU time 0.69 seconds
Started Jun 29 06:34:37 PM PDT 24
Finished Jun 29 06:34:39 PM PDT 24
Peak memory 206188 kb
Host smart-e213a5ba-74b7-480d-b0f0-b0747ecfcf53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51284
1833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.512841833
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2688662221
Short name T1921
Test name
Test status
Simulation time 14587457081 ps
CPU time 33.1 seconds
Started Jun 29 06:34:43 PM PDT 24
Finished Jun 29 06:35:17 PM PDT 24
Peak memory 206448 kb
Host smart-5ff87f9a-bf8b-43fc-8223-cc6e97861d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26886
62221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2688662221
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2904950832
Short name T1289
Test name
Test status
Simulation time 210425871 ps
CPU time 0.88 seconds
Started Jun 29 06:34:41 PM PDT 24
Finished Jun 29 06:34:43 PM PDT 24
Peak memory 206172 kb
Host smart-9c86f2f5-6f0f-4667-bef0-140850676f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29049
50832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2904950832
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2420277566
Short name T1893
Test name
Test status
Simulation time 193321688 ps
CPU time 0.83 seconds
Started Jun 29 06:34:40 PM PDT 24
Finished Jun 29 06:34:41 PM PDT 24
Peak memory 206208 kb
Host smart-c8cca5e6-e28c-4ee0-a1ef-4512647783bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24202
77566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2420277566
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.617203891
Short name T836
Test name
Test status
Simulation time 8421487346 ps
CPU time 221.09 seconds
Started Jun 29 06:34:38 PM PDT 24
Finished Jun 29 06:38:20 PM PDT 24
Peak memory 206500 kb
Host smart-15baff31-5cac-461c-a8bc-4f745bcf594d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=617203891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.617203891
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.757819025
Short name T2526
Test name
Test status
Simulation time 10266112230 ps
CPU time 64.24 seconds
Started Jun 29 06:34:37 PM PDT 24
Finished Jun 29 06:35:42 PM PDT 24
Peak memory 206456 kb
Host smart-c498a03d-46fa-4da5-b71d-62650e45bdfe
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=757819025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.757819025
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2823500402
Short name T2178
Test name
Test status
Simulation time 14324860231 ps
CPU time 94.5 seconds
Started Jun 29 06:34:42 PM PDT 24
Finished Jun 29 06:36:17 PM PDT 24
Peak memory 206496 kb
Host smart-e5a3087d-9468-4a57-8b27-198365d57c7a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2823500402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2823500402
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2906670173
Short name T2094
Test name
Test status
Simulation time 172115865 ps
CPU time 0.8 seconds
Started Jun 29 06:34:37 PM PDT 24
Finished Jun 29 06:34:39 PM PDT 24
Peak memory 206216 kb
Host smart-d42dd5f9-1d43-46c5-b95d-a45533080923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29066
70173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2906670173
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.656445959
Short name T982
Test name
Test status
Simulation time 184487633 ps
CPU time 0.9 seconds
Started Jun 29 06:34:36 PM PDT 24
Finished Jun 29 06:34:38 PM PDT 24
Peak memory 206196 kb
Host smart-b2722f9e-92a0-4e38-b432-ea5aed493d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65644
5959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.656445959
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1985618976
Short name T887
Test name
Test status
Simulation time 226078000 ps
CPU time 0.83 seconds
Started Jun 29 06:34:38 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 206196 kb
Host smart-ba520b14-5bc0-4ec4-a6ee-f81056b1634f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19856
18976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1985618976
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1012837117
Short name T2315
Test name
Test status
Simulation time 187898133 ps
CPU time 0.84 seconds
Started Jun 29 06:34:36 PM PDT 24
Finished Jun 29 06:34:38 PM PDT 24
Peak memory 206136 kb
Host smart-9d097a79-f10c-4e36-9680-4c857dd09505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10128
37117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1012837117
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2123308879
Short name T555
Test name
Test status
Simulation time 168243127 ps
CPU time 0.78 seconds
Started Jun 29 06:34:44 PM PDT 24
Finished Jun 29 06:34:45 PM PDT 24
Peak memory 206164 kb
Host smart-fc2084a2-3f06-4622-8fbf-08b41a9e9944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21233
08879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2123308879
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.341105185
Short name T452
Test name
Test status
Simulation time 259691775 ps
CPU time 0.94 seconds
Started Jun 29 06:34:38 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 206196 kb
Host smart-f9697216-6552-4750-bf8d-5f405be0fc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34110
5185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.341105185
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3599015778
Short name T1386
Test name
Test status
Simulation time 5682891158 ps
CPU time 149.48 seconds
Started Jun 29 06:34:41 PM PDT 24
Finished Jun 29 06:37:11 PM PDT 24
Peak memory 206508 kb
Host smart-4630e9b4-3f02-4705-9237-e16b36e8cf0f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3599015778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3599015778
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.91634895
Short name T2597
Test name
Test status
Simulation time 182710569 ps
CPU time 0.8 seconds
Started Jun 29 06:34:37 PM PDT 24
Finished Jun 29 06:34:38 PM PDT 24
Peak memory 206196 kb
Host smart-55e43be9-8430-4ef6-9ea2-34efc8dce687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91634
895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.91634895
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2730370602
Short name T806
Test name
Test status
Simulation time 163165421 ps
CPU time 0.86 seconds
Started Jun 29 06:34:38 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 206196 kb
Host smart-c7ecfb13-5a5c-44b1-a340-a73eb37895fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27303
70602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2730370602
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3189302436
Short name T2009
Test name
Test status
Simulation time 4139137957 ps
CPU time 39.59 seconds
Started Jun 29 06:34:38 PM PDT 24
Finished Jun 29 06:35:19 PM PDT 24
Peak memory 206396 kb
Host smart-1e58b751-c773-45f3-b0c2-8c733e304fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31893
02436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3189302436
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.1955595417
Short name T1582
Test name
Test status
Simulation time 45992479 ps
CPU time 0.72 seconds
Started Jun 29 06:34:51 PM PDT 24
Finished Jun 29 06:34:53 PM PDT 24
Peak memory 206124 kb
Host smart-25f37c79-86db-42cc-8264-768fa1111ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1955595417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1955595417
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1313000475
Short name T899
Test name
Test status
Simulation time 4075156017 ps
CPU time 4.94 seconds
Started Jun 29 06:34:47 PM PDT 24
Finished Jun 29 06:34:53 PM PDT 24
Peak memory 206268 kb
Host smart-5fb4206e-45e2-4bc5-bdcd-e57b4190ebf0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1313000475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1313000475
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3676726698
Short name T1857
Test name
Test status
Simulation time 13364164381 ps
CPU time 12.41 seconds
Started Jun 29 06:34:42 PM PDT 24
Finished Jun 29 06:34:54 PM PDT 24
Peak memory 206464 kb
Host smart-2eeac321-afc7-482e-8d44-788aad5f2dc2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3676726698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3676726698
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.4110420021
Short name T752
Test name
Test status
Simulation time 23383721673 ps
CPU time 22.04 seconds
Started Jun 29 06:34:37 PM PDT 24
Finished Jun 29 06:35:00 PM PDT 24
Peak memory 206436 kb
Host smart-c415b581-06f0-41f3-8db9-95a2b17359f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4110420021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.4110420021
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.972233114
Short name T689
Test name
Test status
Simulation time 196734345 ps
CPU time 0.86 seconds
Started Jun 29 06:34:38 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 206216 kb
Host smart-9db50f5a-53d3-4a32-8c6e-b6412c6ab8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97223
3114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.972233114
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1203356472
Short name T819
Test name
Test status
Simulation time 141499359 ps
CPU time 0.74 seconds
Started Jun 29 06:34:38 PM PDT 24
Finished Jun 29 06:34:39 PM PDT 24
Peak memory 206216 kb
Host smart-22b3e0fb-44db-49d4-8d21-264d0fc770f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12033
56472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1203356472
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2819093378
Short name T2045
Test name
Test status
Simulation time 508953901 ps
CPU time 1.53 seconds
Started Jun 29 06:34:37 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 206272 kb
Host smart-d8f7008a-8868-4cb0-bdfd-4640fe25a70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28190
93378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2819093378
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3345665062
Short name T1039
Test name
Test status
Simulation time 976348259 ps
CPU time 2.22 seconds
Started Jun 29 06:34:41 PM PDT 24
Finished Jun 29 06:34:43 PM PDT 24
Peak memory 206248 kb
Host smart-41f4e7f7-917f-46c7-a50c-df8c44708e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33456
65062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3345665062
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2894744884
Short name T169
Test name
Test status
Simulation time 9143420937 ps
CPU time 17.38 seconds
Started Jun 29 06:34:41 PM PDT 24
Finished Jun 29 06:34:59 PM PDT 24
Peak memory 206412 kb
Host smart-ea246baa-a2f3-463f-afd4-08527edd135c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28947
44884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2894744884
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.2339025956
Short name T2068
Test name
Test status
Simulation time 344615845 ps
CPU time 1.28 seconds
Started Jun 29 06:34:48 PM PDT 24
Finished Jun 29 06:34:50 PM PDT 24
Peak memory 206220 kb
Host smart-127469b7-53de-4436-9b23-f0eaef4ac8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23390
25956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.2339025956
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3425507876
Short name T1099
Test name
Test status
Simulation time 143184514 ps
CPU time 0.76 seconds
Started Jun 29 06:34:47 PM PDT 24
Finished Jun 29 06:34:49 PM PDT 24
Peak memory 206200 kb
Host smart-7f4214ab-0db0-494e-a626-0a8234147191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34255
07876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3425507876
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3115690385
Short name T529
Test name
Test status
Simulation time 41619410 ps
CPU time 0.66 seconds
Started Jun 29 06:34:48 PM PDT 24
Finished Jun 29 06:34:49 PM PDT 24
Peak memory 206208 kb
Host smart-c86bc319-50f5-470b-8adc-86970085e8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31156
90385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3115690385
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2916576314
Short name T749
Test name
Test status
Simulation time 810876850 ps
CPU time 2.48 seconds
Started Jun 29 06:34:49 PM PDT 24
Finished Jun 29 06:34:52 PM PDT 24
Peak memory 206356 kb
Host smart-7ac9e680-929f-41ff-ba82-52cab667da9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29165
76314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2916576314
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.317321171
Short name T1087
Test name
Test status
Simulation time 162610255 ps
CPU time 1.38 seconds
Started Jun 29 06:34:49 PM PDT 24
Finished Jun 29 06:34:51 PM PDT 24
Peak memory 206360 kb
Host smart-758dbabf-84c3-4577-a6d0-6e7deecbc487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31732
1171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.317321171
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3852965449
Short name T2132
Test name
Test status
Simulation time 181649525 ps
CPU time 0.83 seconds
Started Jun 29 06:34:46 PM PDT 24
Finished Jun 29 06:34:47 PM PDT 24
Peak memory 206192 kb
Host smart-02bc4b60-defe-4539-a28a-bb87a364d012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38529
65449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3852965449
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3659752672
Short name T2502
Test name
Test status
Simulation time 141575099 ps
CPU time 0.78 seconds
Started Jun 29 06:34:49 PM PDT 24
Finished Jun 29 06:34:50 PM PDT 24
Peak memory 206208 kb
Host smart-6f33822e-8bf7-4f7b-94fd-1c5f6a70d6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36597
52672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3659752672
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.4109391899
Short name T904
Test name
Test status
Simulation time 193313747 ps
CPU time 0.85 seconds
Started Jun 29 06:34:45 PM PDT 24
Finished Jun 29 06:34:47 PM PDT 24
Peak memory 206212 kb
Host smart-5593b114-3d52-4f74-a301-dab16365aaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41093
91899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.4109391899
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.379858394
Short name T1214
Test name
Test status
Simulation time 190034253 ps
CPU time 0.81 seconds
Started Jun 29 06:34:47 PM PDT 24
Finished Jun 29 06:34:48 PM PDT 24
Peak memory 206200 kb
Host smart-16675b6b-4e9e-429d-82cc-464133c6b6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37985
8394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.379858394
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2013932438
Short name T787
Test name
Test status
Simulation time 23309354112 ps
CPU time 29.66 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:35:20 PM PDT 24
Peak memory 206316 kb
Host smart-38a36b8c-6f54-45b9-a4f5-e7cc912200e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20139
32438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2013932438
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3137381960
Short name T1459
Test name
Test status
Simulation time 3284987544 ps
CPU time 3.6 seconds
Started Jun 29 06:34:51 PM PDT 24
Finished Jun 29 06:34:55 PM PDT 24
Peak memory 206264 kb
Host smart-b073a1cb-6ce6-432c-ae6c-9583f1700746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31373
81960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3137381960
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.552679935
Short name T1931
Test name
Test status
Simulation time 8836806255 ps
CPU time 81.41 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:36:12 PM PDT 24
Peak memory 206456 kb
Host smart-63d48d8b-91da-45c7-956c-3da8c37e38bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55267
9935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.552679935
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.1192354005
Short name T2010
Test name
Test status
Simulation time 5088521365 ps
CPU time 48.44 seconds
Started Jun 29 06:34:53 PM PDT 24
Finished Jun 29 06:35:42 PM PDT 24
Peak memory 206396 kb
Host smart-c80f865a-778e-4b7a-a404-3059329fafb4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1192354005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.1192354005
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.1245307015
Short name T1970
Test name
Test status
Simulation time 263010990 ps
CPU time 1.01 seconds
Started Jun 29 06:34:51 PM PDT 24
Finished Jun 29 06:34:53 PM PDT 24
Peak memory 206220 kb
Host smart-3475004a-7bcc-4a9d-9043-5aeb8be0b247
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1245307015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.1245307015
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2339897895
Short name T1635
Test name
Test status
Simulation time 192756115 ps
CPU time 0.95 seconds
Started Jun 29 06:34:45 PM PDT 24
Finished Jun 29 06:34:46 PM PDT 24
Peak memory 206216 kb
Host smart-e98ac06e-89b0-4d9f-873e-1aaf1c6d65fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23398
97895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2339897895
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1304649401
Short name T2588
Test name
Test status
Simulation time 3461467926 ps
CPU time 32.99 seconds
Started Jun 29 06:34:51 PM PDT 24
Finished Jun 29 06:35:25 PM PDT 24
Peak memory 206424 kb
Host smart-57b29a58-62a9-4f7e-aadc-f966ca5cf845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13046
49401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1304649401
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2421467586
Short name T482
Test name
Test status
Simulation time 4506490199 ps
CPU time 121.68 seconds
Started Jun 29 06:34:52 PM PDT 24
Finished Jun 29 06:36:54 PM PDT 24
Peak memory 206456 kb
Host smart-eec4a68d-0383-424f-8474-798afa4a219f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2421467586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2421467586
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1143789743
Short name T2459
Test name
Test status
Simulation time 168822675 ps
CPU time 0.79 seconds
Started Jun 29 06:34:49 PM PDT 24
Finished Jun 29 06:34:51 PM PDT 24
Peak memory 206216 kb
Host smart-31c734a7-dfed-4771-a43a-9d930ec8b1a4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1143789743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1143789743
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.13816093
Short name T1650
Test name
Test status
Simulation time 157062923 ps
CPU time 0.77 seconds
Started Jun 29 06:34:47 PM PDT 24
Finished Jun 29 06:34:48 PM PDT 24
Peak memory 206204 kb
Host smart-ea1fc1bd-9420-44cc-a0a1-bfd81067a017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13816
093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.13816093
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.124224792
Short name T143
Test name
Test status
Simulation time 234695902 ps
CPU time 0.92 seconds
Started Jun 29 06:34:51 PM PDT 24
Finished Jun 29 06:34:53 PM PDT 24
Peak memory 206184 kb
Host smart-66ca8830-d69f-4304-a48c-8042463b740e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12422
4792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.124224792
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.772807518
Short name T1076
Test name
Test status
Simulation time 175727191 ps
CPU time 0.8 seconds
Started Jun 29 06:34:47 PM PDT 24
Finished Jun 29 06:34:48 PM PDT 24
Peak memory 206220 kb
Host smart-8bf6cda7-a53a-410f-a7a3-b6d8196f8837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77280
7518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.772807518
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3327846174
Short name T1304
Test name
Test status
Simulation time 159554493 ps
CPU time 0.77 seconds
Started Jun 29 06:34:48 PM PDT 24
Finished Jun 29 06:34:49 PM PDT 24
Peak memory 206216 kb
Host smart-6a73e254-f594-457f-b6c1-235560b65e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33278
46174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3327846174
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1992908314
Short name T1916
Test name
Test status
Simulation time 185208268 ps
CPU time 0.82 seconds
Started Jun 29 06:34:51 PM PDT 24
Finished Jun 29 06:34:53 PM PDT 24
Peak memory 206196 kb
Host smart-8683f96b-3dda-4a81-8023-477db297e823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
08314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1992908314
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1892177430
Short name T1600
Test name
Test status
Simulation time 169859169 ps
CPU time 0.79 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:34:52 PM PDT 24
Peak memory 206220 kb
Host smart-fbb1b0cc-6876-498f-a539-93598c96591f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18921
77430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1892177430
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1629718845
Short name T1131
Test name
Test status
Simulation time 227356699 ps
CPU time 0.91 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:34:52 PM PDT 24
Peak memory 206224 kb
Host smart-47335d61-199a-4467-875d-aac94e8b3c9f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1629718845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1629718845
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2387837602
Short name T528
Test name
Test status
Simulation time 164429707 ps
CPU time 0.79 seconds
Started Jun 29 06:34:48 PM PDT 24
Finished Jun 29 06:34:49 PM PDT 24
Peak memory 206212 kb
Host smart-41c3907d-b428-4e79-a974-994b6bdff381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
37602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2387837602
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1858461815
Short name T888
Test name
Test status
Simulation time 63021627 ps
CPU time 0.65 seconds
Started Jun 29 06:34:45 PM PDT 24
Finished Jun 29 06:34:46 PM PDT 24
Peak memory 206224 kb
Host smart-292f7b42-782c-4d78-8339-e5b84d9a6dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18584
61815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1858461815
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2018803408
Short name T1119
Test name
Test status
Simulation time 16625047040 ps
CPU time 34.92 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:35:26 PM PDT 24
Peak memory 206420 kb
Host smart-2b860e37-72c1-4fc6-bbae-ca3044388b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20188
03408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2018803408
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1800335065
Short name T294
Test name
Test status
Simulation time 188942682 ps
CPU time 0.81 seconds
Started Jun 29 06:34:51 PM PDT 24
Finished Jun 29 06:34:53 PM PDT 24
Peak memory 206204 kb
Host smart-8e883ce8-c8a0-4e41-a430-5bdc2b35c031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18003
35065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1800335065
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3221929503
Short name T905
Test name
Test status
Simulation time 231529907 ps
CPU time 0.94 seconds
Started Jun 29 06:34:47 PM PDT 24
Finished Jun 29 06:34:49 PM PDT 24
Peak memory 206200 kb
Host smart-d276fbf5-83e9-421a-aa4a-36d12ba0965a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32219
29503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3221929503
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3410038185
Short name T2268
Test name
Test status
Simulation time 11312087260 ps
CPU time 58.74 seconds
Started Jun 29 06:34:48 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 206500 kb
Host smart-51dc8b5a-75aa-4b3b-81c7-dc710400b6ed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3410038185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3410038185
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.243742566
Short name T1756
Test name
Test status
Simulation time 5162187572 ps
CPU time 45.46 seconds
Started Jun 29 06:34:48 PM PDT 24
Finished Jun 29 06:35:34 PM PDT 24
Peak memory 206448 kb
Host smart-75c832c7-2354-4b42-bf7d-a7e05019c738
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=243742566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.243742566
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.3816445882
Short name T2332
Test name
Test status
Simulation time 16632494479 ps
CPU time 94.16 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:36:25 PM PDT 24
Peak memory 206432 kb
Host smart-afacfe23-277d-4c60-9cda-853f024692f6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3816445882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.3816445882
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3494779297
Short name T2456
Test name
Test status
Simulation time 165648450 ps
CPU time 0.84 seconds
Started Jun 29 06:34:52 PM PDT 24
Finished Jun 29 06:34:54 PM PDT 24
Peak memory 206160 kb
Host smart-51ae02b6-5f95-4e76-9f7c-5b65e59acd6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34947
79297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3494779297
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2571620364
Short name T1709
Test name
Test status
Simulation time 203390367 ps
CPU time 0.86 seconds
Started Jun 29 06:34:49 PM PDT 24
Finished Jun 29 06:34:50 PM PDT 24
Peak memory 206160 kb
Host smart-bdac21c4-fd0f-4e5d-a8a5-1f0e9d4dbd2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25716
20364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2571620364
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3017383537
Short name T373
Test name
Test status
Simulation time 132091325 ps
CPU time 0.8 seconds
Started Jun 29 06:34:47 PM PDT 24
Finished Jun 29 06:34:48 PM PDT 24
Peak memory 206172 kb
Host smart-6c5a43f2-6961-44a4-865c-d7e8a1fdfd98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30173
83537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3017383537
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2259761565
Short name T652
Test name
Test status
Simulation time 182635199 ps
CPU time 0.83 seconds
Started Jun 29 06:34:49 PM PDT 24
Finished Jun 29 06:34:50 PM PDT 24
Peak memory 206196 kb
Host smart-051e9051-6413-4d83-ade6-f8679869c542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22597
61565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2259761565
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2474762951
Short name T19
Test name
Test status
Simulation time 175505761 ps
CPU time 0.82 seconds
Started Jun 29 06:34:48 PM PDT 24
Finished Jun 29 06:34:49 PM PDT 24
Peak memory 206196 kb
Host smart-8a61b4f5-5de3-4bd2-a9ef-96a9fe3fa132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24747
62951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2474762951
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1271033479
Short name T2494
Test name
Test status
Simulation time 220100993 ps
CPU time 0.95 seconds
Started Jun 29 06:34:48 PM PDT 24
Finished Jun 29 06:34:50 PM PDT 24
Peak memory 206216 kb
Host smart-ba29d240-22e6-4953-8907-4bb7597ed241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12710
33479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1271033479
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3413996994
Short name T403
Test name
Test status
Simulation time 3475816444 ps
CPU time 91.06 seconds
Started Jun 29 06:34:48 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 206508 kb
Host smart-6d69a225-109e-4632-b2df-7874e11cc874
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3413996994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3413996994
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.522997005
Short name T840
Test name
Test status
Simulation time 164987385 ps
CPU time 0.79 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:34:52 PM PDT 24
Peak memory 206220 kb
Host smart-06645b5d-52c1-4a58-850c-361f95bf93d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52299
7005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.522997005
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.4090192286
Short name T1313
Test name
Test status
Simulation time 172244214 ps
CPU time 0.82 seconds
Started Jun 29 06:34:49 PM PDT 24
Finished Jun 29 06:34:51 PM PDT 24
Peak memory 206196 kb
Host smart-d9890bff-7fb5-484e-9f8f-0ba70f04c09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40901
92286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.4090192286
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2009866635
Short name T1766
Test name
Test status
Simulation time 5281202683 ps
CPU time 39.46 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:35:30 PM PDT 24
Peak memory 206356 kb
Host smart-7a2d688e-a241-4663-b597-12500ba32143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20098
66635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2009866635
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.3804600567
Short name T1495
Test name
Test status
Simulation time 33653655 ps
CPU time 0.68 seconds
Started Jun 29 06:35:00 PM PDT 24
Finished Jun 29 06:35:01 PM PDT 24
Peak memory 206192 kb
Host smart-2a45e2c5-728f-4f5c-8d7f-8ad3db13e6ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3804600567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.3804600567
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.1036825921
Short name T1242
Test name
Test status
Simulation time 3415043111 ps
CPU time 4.1 seconds
Started Jun 29 06:34:53 PM PDT 24
Finished Jun 29 06:34:58 PM PDT 24
Peak memory 206248 kb
Host smart-7daeac4b-c6d3-4bd0-b2de-a06956eb3b82
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1036825921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.1036825921
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.387012032
Short name T547
Test name
Test status
Simulation time 13313416286 ps
CPU time 12.96 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:35:05 PM PDT 24
Peak memory 206340 kb
Host smart-80fd195f-cada-4ef5-a47b-c938b74ff12c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=387012032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.387012032
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2291469605
Short name T1917
Test name
Test status
Simulation time 23521243474 ps
CPU time 25.83 seconds
Started Jun 29 06:35:12 PM PDT 24
Finished Jun 29 06:35:38 PM PDT 24
Peak memory 206404 kb
Host smart-bbcc1261-cb80-42cc-b0e4-176c44971299
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2291469605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2291469605
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3993504696
Short name T2611
Test name
Test status
Simulation time 147744920 ps
CPU time 0.78 seconds
Started Jun 29 06:34:53 PM PDT 24
Finished Jun 29 06:34:54 PM PDT 24
Peak memory 206212 kb
Host smart-14ece9f7-bc1e-45e7-b3f8-b28955f2ee7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39935
04696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3993504696
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1163968608
Short name T2462
Test name
Test status
Simulation time 177688338 ps
CPU time 0.84 seconds
Started Jun 29 06:34:52 PM PDT 24
Finished Jun 29 06:34:53 PM PDT 24
Peak memory 206204 kb
Host smart-9c459871-46b2-48b4-a4d4-56330272a383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11639
68608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1163968608
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.518432867
Short name T1172
Test name
Test status
Simulation time 465973704 ps
CPU time 1.46 seconds
Started Jun 29 06:34:58 PM PDT 24
Finished Jun 29 06:35:00 PM PDT 24
Peak memory 206216 kb
Host smart-59211369-3b92-4c81-8f96-e04169624f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51843
2867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.518432867
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3168512362
Short name T1806
Test name
Test status
Simulation time 1571431679 ps
CPU time 3.69 seconds
Started Jun 29 06:34:59 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 206272 kb
Host smart-a37cbe38-d80e-42ec-8c10-55fd352f578a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31685
12362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3168512362
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.1327202196
Short name T101
Test name
Test status
Simulation time 7086324161 ps
CPU time 14.31 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:35:05 PM PDT 24
Peak memory 206420 kb
Host smart-54dcc523-3f50-47c0-8857-97dbce6d829f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13272
02196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1327202196
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1370430137
Short name T501
Test name
Test status
Simulation time 391428956 ps
CPU time 1.24 seconds
Started Jun 29 06:34:56 PM PDT 24
Finished Jun 29 06:34:57 PM PDT 24
Peak memory 206220 kb
Host smart-0bed69f8-89b2-4378-ab1f-6e49e37be8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13704
30137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1370430137
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.3008599588
Short name T480
Test name
Test status
Simulation time 132967163 ps
CPU time 0.81 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:34:52 PM PDT 24
Peak memory 206204 kb
Host smart-408646b1-139c-4cb8-a3c8-1d26abde7b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30085
99588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.3008599588
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.807747657
Short name T2198
Test name
Test status
Simulation time 32461379 ps
CPU time 0.71 seconds
Started Jun 29 06:34:54 PM PDT 24
Finished Jun 29 06:34:55 PM PDT 24
Peak memory 206208 kb
Host smart-72284fef-2e4e-4f29-baed-96436040fe1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80774
7657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.807747657
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3882315074
Short name T2446
Test name
Test status
Simulation time 841231616 ps
CPU time 1.9 seconds
Started Jun 29 06:34:51 PM PDT 24
Finished Jun 29 06:34:54 PM PDT 24
Peak memory 206292 kb
Host smart-b992e203-158d-4070-9cd9-1c73c2397480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38823
15074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3882315074
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1033448352
Short name T534
Test name
Test status
Simulation time 223055971 ps
CPU time 1.74 seconds
Started Jun 29 06:34:52 PM PDT 24
Finished Jun 29 06:34:55 PM PDT 24
Peak memory 206328 kb
Host smart-46d1be3e-c9a2-472e-a0b6-0e113234a67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10334
48352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1033448352
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3052961841
Short name T999
Test name
Test status
Simulation time 211814986 ps
CPU time 0.92 seconds
Started Jun 29 06:34:53 PM PDT 24
Finished Jun 29 06:34:54 PM PDT 24
Peak memory 206204 kb
Host smart-3c7a7e9c-5e18-4870-82c5-6c31b1dbdcab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30529
61841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3052961841
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.747818855
Short name T2330
Test name
Test status
Simulation time 208086794 ps
CPU time 0.84 seconds
Started Jun 29 06:34:56 PM PDT 24
Finished Jun 29 06:34:57 PM PDT 24
Peak memory 206204 kb
Host smart-41f9d659-5c26-4806-8119-671f1f490720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74781
8855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.747818855
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.631892719
Short name T1253
Test name
Test status
Simulation time 245822936 ps
CPU time 0.98 seconds
Started Jun 29 06:34:53 PM PDT 24
Finished Jun 29 06:34:54 PM PDT 24
Peak memory 206204 kb
Host smart-6174868a-425c-4d9f-96cd-c3ed81f6319f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63189
2719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.631892719
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.42270689
Short name T104
Test name
Test status
Simulation time 5636618363 ps
CPU time 52.9 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:35:44 PM PDT 24
Peak memory 206428 kb
Host smart-f4a63a3c-da8c-403b-bf96-22bf4056d17a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=42270689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.42270689
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.2165577941
Short name T1628
Test name
Test status
Simulation time 230061739 ps
CPU time 0.97 seconds
Started Jun 29 06:34:59 PM PDT 24
Finished Jun 29 06:35:01 PM PDT 24
Peak memory 206192 kb
Host smart-a1bd5a89-836a-4213-ae94-b8117553b266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655
77941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.2165577941
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.1330940109
Short name T2557
Test name
Test status
Simulation time 23345739642 ps
CPU time 29.89 seconds
Started Jun 29 06:34:53 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 206304 kb
Host smart-27c4f425-4fda-499c-b961-059a8b198040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13309
40109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.1330940109
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.33943733
Short name T930
Test name
Test status
Simulation time 3283899056 ps
CPU time 3.66 seconds
Started Jun 29 06:34:55 PM PDT 24
Finished Jun 29 06:34:59 PM PDT 24
Peak memory 206252 kb
Host smart-7195b0f6-e423-4b0b-9dc5-e7b2f1eb118c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33943
733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.33943733
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3657610809
Short name T1006
Test name
Test status
Simulation time 10287498792 ps
CPU time 103.52 seconds
Started Jun 29 06:34:54 PM PDT 24
Finished Jun 29 06:36:38 PM PDT 24
Peak memory 206428 kb
Host smart-2897dc9b-904b-41e2-9d3a-7e87821d63c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36576
10809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3657610809
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.2896104096
Short name T635
Test name
Test status
Simulation time 5130664265 ps
CPU time 144.43 seconds
Started Jun 29 06:34:51 PM PDT 24
Finished Jun 29 06:37:17 PM PDT 24
Peak memory 206460 kb
Host smart-c5337242-a8d3-4f67-bf0f-67e246c3194a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2896104096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.2896104096
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1776276181
Short name T992
Test name
Test status
Simulation time 258400482 ps
CPU time 0.94 seconds
Started Jun 29 06:34:58 PM PDT 24
Finished Jun 29 06:34:59 PM PDT 24
Peak memory 206212 kb
Host smart-08f4a380-728d-40f3-b4f4-7232ac239a86
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1776276181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1776276181
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3327899447
Short name T2208
Test name
Test status
Simulation time 262119722 ps
CPU time 1.01 seconds
Started Jun 29 06:35:00 PM PDT 24
Finished Jun 29 06:35:01 PM PDT 24
Peak memory 206372 kb
Host smart-77b0109d-a549-4387-8723-56f133f0b7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33278
99447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3327899447
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.3071138281
Short name T1056
Test name
Test status
Simulation time 3946813392 ps
CPU time 28.1 seconds
Started Jun 29 06:34:52 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206460 kb
Host smart-6b14d06d-9cda-4d15-85fa-8908cb3f693d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30711
38281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.3071138281
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2042494836
Short name T525
Test name
Test status
Simulation time 4481648302 ps
CPU time 128.39 seconds
Started Jun 29 06:34:54 PM PDT 24
Finished Jun 29 06:37:03 PM PDT 24
Peak memory 206460 kb
Host smart-04e4eb09-2fcf-4a37-b908-85bfc4d5c829
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2042494836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2042494836
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1244080975
Short name T1080
Test name
Test status
Simulation time 156511956 ps
CPU time 0.79 seconds
Started Jun 29 06:34:50 PM PDT 24
Finished Jun 29 06:34:52 PM PDT 24
Peak memory 206216 kb
Host smart-000e4b5b-c41d-4cd1-b9c0-cf53b5a4b72c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1244080975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1244080975
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3550738971
Short name T946
Test name
Test status
Simulation time 161292901 ps
CPU time 0.79 seconds
Started Jun 29 06:35:02 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 206372 kb
Host smart-36e18250-fb1c-4f21-98e7-8f9b8e979ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35507
38971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3550738971
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1811227869
Short name T151
Test name
Test status
Simulation time 251899666 ps
CPU time 0.95 seconds
Started Jun 29 06:34:53 PM PDT 24
Finished Jun 29 06:34:54 PM PDT 24
Peak memory 206164 kb
Host smart-e917a9dd-206a-4e97-8ffa-cdacec1056d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18112
27869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1811227869
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2536722308
Short name T790
Test name
Test status
Simulation time 174222848 ps
CPU time 0.86 seconds
Started Jun 29 06:34:56 PM PDT 24
Finished Jun 29 06:34:57 PM PDT 24
Peak memory 206204 kb
Host smart-b674c817-001f-41f0-b20a-0e96aa58ab80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25367
22308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2536722308
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1183865685
Short name T785
Test name
Test status
Simulation time 189855943 ps
CPU time 0.85 seconds
Started Jun 29 06:34:59 PM PDT 24
Finished Jun 29 06:35:01 PM PDT 24
Peak memory 206216 kb
Host smart-c6ccfdb3-d902-4135-b92d-cd5c29db857a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11838
65685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1183865685
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.317518692
Short name T1102
Test name
Test status
Simulation time 185013951 ps
CPU time 0.84 seconds
Started Jun 29 06:34:59 PM PDT 24
Finished Jun 29 06:35:00 PM PDT 24
Peak memory 206368 kb
Host smart-c5f70f80-b611-42a3-8142-0d031550ebac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31751
8692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.317518692
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3072834450
Short name T895
Test name
Test status
Simulation time 183113407 ps
CPU time 0.78 seconds
Started Jun 29 06:34:56 PM PDT 24
Finished Jun 29 06:34:57 PM PDT 24
Peak memory 206220 kb
Host smart-be11bf69-b6a0-4f12-bd32-eb1b6c0d5b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30728
34450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3072834450
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.414834501
Short name T863
Test name
Test status
Simulation time 215112385 ps
CPU time 0.99 seconds
Started Jun 29 06:34:53 PM PDT 24
Finished Jun 29 06:34:54 PM PDT 24
Peak memory 206220 kb
Host smart-74f87011-8051-4b94-8aad-c2dcc336e06b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=414834501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.414834501
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.4292882037
Short name T801
Test name
Test status
Simulation time 144443459 ps
CPU time 0.75 seconds
Started Jun 29 06:35:00 PM PDT 24
Finished Jun 29 06:35:01 PM PDT 24
Peak memory 206204 kb
Host smart-50d0ff32-f8b2-4f30-9070-3cb5709a9749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42928
82037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.4292882037
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1698593176
Short name T2559
Test name
Test status
Simulation time 35607753 ps
CPU time 0.68 seconds
Started Jun 29 06:34:54 PM PDT 24
Finished Jun 29 06:34:55 PM PDT 24
Peak memory 206208 kb
Host smart-dc0da255-2d8b-4069-b68b-cc7b12db2e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16985
93176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1698593176
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1617631680
Short name T926
Test name
Test status
Simulation time 15951959989 ps
CPU time 35.98 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:38 PM PDT 24
Peak memory 206600 kb
Host smart-c936b7f3-a789-4cac-8106-3c9de8e93761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16176
31680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1617631680
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.546461705
Short name T1608
Test name
Test status
Simulation time 169421939 ps
CPU time 0.78 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:35:05 PM PDT 24
Peak memory 206192 kb
Host smart-55ce5dc3-201c-4156-b1f4-c77a0f79ca02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54646
1705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.546461705
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1085590133
Short name T2515
Test name
Test status
Simulation time 233495170 ps
CPU time 0.96 seconds
Started Jun 29 06:35:02 PM PDT 24
Finished Jun 29 06:35:04 PM PDT 24
Peak memory 206208 kb
Host smart-96500198-3591-4de9-8962-dc2757c6be8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10855
90133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1085590133
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1108690385
Short name T627
Test name
Test status
Simulation time 9863757713 ps
CPU time 279.49 seconds
Started Jun 29 06:35:02 PM PDT 24
Finished Jun 29 06:39:42 PM PDT 24
Peak memory 206500 kb
Host smart-cb97c0fa-d0e1-43c3-ab4f-c9a62d634309
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1108690385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1108690385
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.2879739217
Short name T2097
Test name
Test status
Simulation time 9387100573 ps
CPU time 79.23 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:36:23 PM PDT 24
Peak memory 206404 kb
Host smart-63c766f1-658a-4379-a90e-a808e0334ad3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2879739217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.2879739217
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.2074399696
Short name T1207
Test name
Test status
Simulation time 12122755565 ps
CPU time 82.89 seconds
Started Jun 29 06:35:04 PM PDT 24
Finished Jun 29 06:36:27 PM PDT 24
Peak memory 206484 kb
Host smart-e6230788-4373-41f2-b71b-c6299619c259
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2074399696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2074399696
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1028048876
Short name T935
Test name
Test status
Simulation time 222129347 ps
CPU time 0.92 seconds
Started Jun 29 06:35:02 PM PDT 24
Finished Jun 29 06:35:04 PM PDT 24
Peak memory 206184 kb
Host smart-1784f2be-8d32-4c3c-961c-9af58fb8b35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10280
48876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1028048876
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1464550564
Short name T1306
Test name
Test status
Simulation time 143401216 ps
CPU time 0.82 seconds
Started Jun 29 06:34:58 PM PDT 24
Finished Jun 29 06:34:59 PM PDT 24
Peak memory 206176 kb
Host smart-83e9aa78-29d9-42c5-957b-dc9dfeed3709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14645
50564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1464550564
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3602736851
Short name T2406
Test name
Test status
Simulation time 180491485 ps
CPU time 0.86 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:35:05 PM PDT 24
Peak memory 206200 kb
Host smart-930eaf7f-f56b-41e8-b8b3-628d6b6253c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36027
36851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3602736851
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.32782651
Short name T2414
Test name
Test status
Simulation time 149846253 ps
CPU time 0.74 seconds
Started Jun 29 06:35:11 PM PDT 24
Finished Jun 29 06:35:12 PM PDT 24
Peak memory 206184 kb
Host smart-b43c401b-1f69-4985-8824-6da77af1edaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32782
651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.32782651
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2532184618
Short name T1125
Test name
Test status
Simulation time 145532655 ps
CPU time 0.8 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:35:05 PM PDT 24
Peak memory 206196 kb
Host smart-a142a4eb-24cf-4c06-b798-7c40863063b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25321
84618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2532184618
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2754262272
Short name T1281
Test name
Test status
Simulation time 264081225 ps
CPU time 0.99 seconds
Started Jun 29 06:35:04 PM PDT 24
Finished Jun 29 06:35:05 PM PDT 24
Peak memory 206196 kb
Host smart-c9139673-4560-49a2-86b8-d5b0d343d08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27542
62272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2754262272
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1881848926
Short name T1195
Test name
Test status
Simulation time 5928097113 ps
CPU time 41.58 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:43 PM PDT 24
Peak memory 206424 kb
Host smart-e5158b92-5f3d-43af-95e4-fd0f9361fecd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1881848926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1881848926
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3918161754
Short name T410
Test name
Test status
Simulation time 159791219 ps
CPU time 0.75 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:02 PM PDT 24
Peak memory 206224 kb
Host smart-42dd9b20-b9d8-4cf6-bf89-f38f265f70c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39181
61754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3918161754
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.4019896745
Short name T2431
Test name
Test status
Simulation time 190536235 ps
CPU time 0.9 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 206192 kb
Host smart-fa422c6c-b48f-4ca1-a83f-c1d8b76ec4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40198
96745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.4019896745
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3226789481
Short name T1679
Test name
Test status
Simulation time 4916829724 ps
CPU time 36.69 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:38 PM PDT 24
Peak memory 206412 kb
Host smart-fa1a1947-3c68-4dc5-be3b-9b421247c9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32267
89481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3226789481
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.3948547379
Short name T2367
Test name
Test status
Simulation time 35766921 ps
CPU time 0.7 seconds
Started Jun 29 06:35:10 PM PDT 24
Finished Jun 29 06:35:11 PM PDT 24
Peak memory 206216 kb
Host smart-98192a2b-ec8f-4a65-8edd-01d8e1642e71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3948547379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.3948547379
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1554165816
Short name T777
Test name
Test status
Simulation time 4159350650 ps
CPU time 5.24 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:35:09 PM PDT 24
Peak memory 206356 kb
Host smart-d183dc77-511e-45f6-be60-0d5e9edd5349
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1554165816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.1554165816
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.581679537
Short name T1789
Test name
Test status
Simulation time 13379245503 ps
CPU time 13.65 seconds
Started Jun 29 06:35:00 PM PDT 24
Finished Jun 29 06:35:14 PM PDT 24
Peak memory 206340 kb
Host smart-b8374ac9-8148-4d5e-a160-00971dfdf34b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=581679537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.581679537
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.272254764
Short name T477
Test name
Test status
Simulation time 23374364904 ps
CPU time 21.8 seconds
Started Jun 29 06:35:05 PM PDT 24
Finished Jun 29 06:35:27 PM PDT 24
Peak memory 206460 kb
Host smart-4557e324-55de-4a53-b6fb-65595b98431f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=272254764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.272254764
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3258489903
Short name T2083
Test name
Test status
Simulation time 173792266 ps
CPU time 0.83 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 206216 kb
Host smart-ff8cf153-1f1f-465c-802b-7a99a0db712f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32584
89903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3258489903
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.3460804729
Short name T625
Test name
Test status
Simulation time 164576867 ps
CPU time 0.86 seconds
Started Jun 29 06:35:02 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 206152 kb
Host smart-feba9b5e-ce54-4c43-a9b9-47259a2e5244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34608
04729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3460804729
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2410050766
Short name T115
Test name
Test status
Simulation time 449342612 ps
CPU time 1.45 seconds
Started Jun 29 06:35:07 PM PDT 24
Finished Jun 29 06:35:09 PM PDT 24
Peak memory 206188 kb
Host smart-ebbadc9e-2fb7-4325-ab7b-7418f7060b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24100
50766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2410050766
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1101444843
Short name T195
Test name
Test status
Simulation time 10230121561 ps
CPU time 20.48 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:35:24 PM PDT 24
Peak memory 206456 kb
Host smart-139315a4-f2fc-48ec-af62-9a4aabdc7789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11014
44843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1101444843
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.410675284
Short name T1062
Test name
Test status
Simulation time 440075082 ps
CPU time 1.34 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:35:05 PM PDT 24
Peak memory 206220 kb
Host smart-f86192bf-249d-4f2f-a424-c4968670ddb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41067
5284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.410675284
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.3819933451
Short name T1365
Test name
Test status
Simulation time 138812345 ps
CPU time 0.82 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 206200 kb
Host smart-678be15f-9359-4de3-bea6-0592fa9ef0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38199
33451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.3819933451
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2379679557
Short name T435
Test name
Test status
Simulation time 33684246 ps
CPU time 0.68 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 206200 kb
Host smart-9d2a443e-1de9-4d02-94ae-8581fc7aee9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23796
79557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2379679557
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.743151373
Short name T1199
Test name
Test status
Simulation time 1030547770 ps
CPU time 2.41 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:35:06 PM PDT 24
Peak memory 206292 kb
Host smart-4e7e61c0-1ce1-461d-ad5f-c4aa1c05fa59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74315
1373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.743151373
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1623278704
Short name T1963
Test name
Test status
Simulation time 217272345 ps
CPU time 1.32 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:35:05 PM PDT 24
Peak memory 206284 kb
Host smart-3bf31dcf-531c-4974-8efa-35834d7eccf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16232
78704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1623278704
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.4037301921
Short name T744
Test name
Test status
Simulation time 245880225 ps
CPU time 0.99 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:35:04 PM PDT 24
Peak memory 206120 kb
Host smart-affbcb6b-8765-4fcb-a40d-3b0e35cf1def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
01921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.4037301921
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.292841833
Short name T2092
Test name
Test status
Simulation time 163982825 ps
CPU time 0.86 seconds
Started Jun 29 06:35:02 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 206116 kb
Host smart-6fcbab0d-63f7-4c88-9b0c-6b387541f829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29284
1833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.292841833
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.4273806650
Short name T416
Test name
Test status
Simulation time 147945339 ps
CPU time 0.84 seconds
Started Jun 29 06:35:00 PM PDT 24
Finished Jun 29 06:35:01 PM PDT 24
Peak memory 206208 kb
Host smart-a2f009f3-cb35-4b5c-8c43-97bab46a3986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42738
06650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.4273806650
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2487561988
Short name T1692
Test name
Test status
Simulation time 226036077 ps
CPU time 0.92 seconds
Started Jun 29 06:35:05 PM PDT 24
Finished Jun 29 06:35:07 PM PDT 24
Peak memory 206196 kb
Host smart-0223f1a9-436f-4844-9c56-bedd48ecca16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24875
61988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2487561988
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3636116316
Short name T342
Test name
Test status
Simulation time 23354471624 ps
CPU time 25.06 seconds
Started Jun 29 06:35:05 PM PDT 24
Finished Jun 29 06:35:31 PM PDT 24
Peak memory 206288 kb
Host smart-c024d11c-9bd0-4a97-bded-2d663099710b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36361
16316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3636116316
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.165209195
Short name T1346
Test name
Test status
Simulation time 3294882214 ps
CPU time 4.06 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:06 PM PDT 24
Peak memory 206264 kb
Host smart-dcd6c954-ce13-4994-91b2-a394d427c782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16520
9195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.165209195
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3628139732
Short name T1211
Test name
Test status
Simulation time 7387062417 ps
CPU time 51.51 seconds
Started Jun 29 06:35:05 PM PDT 24
Finished Jun 29 06:35:57 PM PDT 24
Peak memory 206484 kb
Host smart-fd2a942b-1f40-4e9e-bfdf-f36937e00f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36281
39732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3628139732
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.2103394280
Short name T381
Test name
Test status
Simulation time 3254956610 ps
CPU time 89.12 seconds
Started Jun 29 06:35:05 PM PDT 24
Finished Jun 29 06:36:35 PM PDT 24
Peak memory 206460 kb
Host smart-aa9063c5-034b-4b18-9cc1-447bf236febe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2103394280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.2103394280
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.1281108529
Short name T1502
Test name
Test status
Simulation time 269737625 ps
CPU time 0.98 seconds
Started Jun 29 06:34:59 PM PDT 24
Finished Jun 29 06:35:00 PM PDT 24
Peak memory 206172 kb
Host smart-599e9cda-3136-426a-9195-c663da8427a5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1281108529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.1281108529
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3978586933
Short name T1075
Test name
Test status
Simulation time 200213627 ps
CPU time 0.87 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:02 PM PDT 24
Peak memory 206216 kb
Host smart-e16f27f3-83ad-4f62-a557-147455236513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39785
86933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3978586933
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3596169912
Short name T1746
Test name
Test status
Simulation time 4654416956 ps
CPU time 46.75 seconds
Started Jun 29 06:35:04 PM PDT 24
Finished Jun 29 06:35:51 PM PDT 24
Peak memory 206392 kb
Host smart-fc3c2198-a940-4fe9-9a66-f661ba85c29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35961
69912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3596169912
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.850908720
Short name T1250
Test name
Test status
Simulation time 4046485392 ps
CPU time 36.52 seconds
Started Jun 29 06:35:04 PM PDT 24
Finished Jun 29 06:35:41 PM PDT 24
Peak memory 206400 kb
Host smart-c5307a8a-cb01-42f5-aff0-7675590c8d89
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=850908720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.850908720
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.742664217
Short name T1351
Test name
Test status
Simulation time 225441683 ps
CPU time 0.9 seconds
Started Jun 29 06:35:04 PM PDT 24
Finished Jun 29 06:35:06 PM PDT 24
Peak memory 206372 kb
Host smart-9152684e-656d-4531-9bcb-d13cb94ee6c6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=742664217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.742664217
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.203750781
Short name T2500
Test name
Test status
Simulation time 159163609 ps
CPU time 0.82 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:02 PM PDT 24
Peak memory 206212 kb
Host smart-b49817d6-0beb-4839-8816-05a0edbb5cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20375
0781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.203750781
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1644415414
Short name T147
Test name
Test status
Simulation time 257835711 ps
CPU time 0.98 seconds
Started Jun 29 06:35:05 PM PDT 24
Finished Jun 29 06:35:07 PM PDT 24
Peak memory 206216 kb
Host smart-dcc2ca41-31d0-4f10-8b6c-3518dde6355c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16444
15414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1644415414
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2624097365
Short name T2129
Test name
Test status
Simulation time 239256812 ps
CPU time 0.91 seconds
Started Jun 29 06:35:03 PM PDT 24
Finished Jun 29 06:35:05 PM PDT 24
Peak memory 206204 kb
Host smart-a0932d44-e4cf-4aa9-9f26-c14de195c80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26240
97365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2624097365
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1562524041
Short name T1740
Test name
Test status
Simulation time 192105578 ps
CPU time 0.94 seconds
Started Jun 29 06:35:00 PM PDT 24
Finished Jun 29 06:35:02 PM PDT 24
Peak memory 206192 kb
Host smart-232bb6fb-23bf-4253-9512-ad4e902f3202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15625
24041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1562524041
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3062508126
Short name T1919
Test name
Test status
Simulation time 188800016 ps
CPU time 0.85 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 206196 kb
Host smart-839f7476-913e-4ed5-a03e-ced033239526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30625
08126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3062508126
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.713858183
Short name T490
Test name
Test status
Simulation time 156192513 ps
CPU time 0.78 seconds
Started Jun 29 06:35:01 PM PDT 24
Finished Jun 29 06:35:02 PM PDT 24
Peak memory 206220 kb
Host smart-3e12a7e0-3157-4b13-add4-11f4638ebf93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71385
8183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.713858183
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.1003048200
Short name T523
Test name
Test status
Simulation time 195505203 ps
CPU time 0.97 seconds
Started Jun 29 06:35:13 PM PDT 24
Finished Jun 29 06:35:14 PM PDT 24
Peak memory 206224 kb
Host smart-8425c856-4a87-4bbe-af08-2154a9bef1ab
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1003048200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1003048200
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.435284180
Short name T1245
Test name
Test status
Simulation time 169054608 ps
CPU time 0.8 seconds
Started Jun 29 06:35:20 PM PDT 24
Finished Jun 29 06:35:22 PM PDT 24
Peak memory 206204 kb
Host smart-ee2fa7d7-905f-4e1f-ba6e-369c6d944f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43528
4180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.435284180
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1746858076
Short name T2383
Test name
Test status
Simulation time 56843316 ps
CPU time 0.71 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:19 PM PDT 24
Peak memory 206196 kb
Host smart-981966df-dec9-4e8d-a5e7-9284467b2f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17468
58076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1746858076
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3554463468
Short name T1759
Test name
Test status
Simulation time 10212380001 ps
CPU time 22.7 seconds
Started Jun 29 06:35:12 PM PDT 24
Finished Jun 29 06:35:35 PM PDT 24
Peak memory 206448 kb
Host smart-170b12b1-c592-47d6-aea8-ab8fb660c58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35544
63468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3554463468
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1288613831
Short name T1397
Test name
Test status
Simulation time 153011793 ps
CPU time 0.79 seconds
Started Jun 29 06:35:10 PM PDT 24
Finished Jun 29 06:35:12 PM PDT 24
Peak memory 206196 kb
Host smart-6aaf05e4-5a50-4240-a91a-93bfcecbaee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12886
13831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1288613831
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3385509151
Short name T478
Test name
Test status
Simulation time 245073962 ps
CPU time 0.98 seconds
Started Jun 29 06:35:16 PM PDT 24
Finished Jun 29 06:35:18 PM PDT 24
Peak memory 206212 kb
Host smart-720061f3-e553-479f-b49d-d85604921593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33855
09151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3385509151
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.4002286999
Short name T189
Test name
Test status
Simulation time 4329440955 ps
CPU time 24.89 seconds
Started Jun 29 06:35:08 PM PDT 24
Finished Jun 29 06:35:33 PM PDT 24
Peak memory 206460 kb
Host smart-0ba86532-1085-4d9d-a965-8243ac1d1afb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4002286999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.4002286999
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1523577147
Short name T161
Test name
Test status
Simulation time 9088098384 ps
CPU time 60.35 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 206448 kb
Host smart-2c9678f8-2b9d-444b-9889-33e88f6f04c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1523577147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1523577147
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.3106697218
Short name T45
Test name
Test status
Simulation time 20810596258 ps
CPU time 506.28 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:43:46 PM PDT 24
Peak memory 206532 kb
Host smart-4e328e03-1fd4-4be0-b41d-8af3d0117a09
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3106697218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.3106697218
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.85346713
Short name T2072
Test name
Test status
Simulation time 306332690 ps
CPU time 0.99 seconds
Started Jun 29 06:35:14 PM PDT 24
Finished Jun 29 06:35:16 PM PDT 24
Peak memory 206184 kb
Host smart-d7dc6140-3eea-4eb8-b72c-faa2a41ffef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85346
713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.85346713
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.3649612244
Short name T443
Test name
Test status
Simulation time 154800861 ps
CPU time 0.84 seconds
Started Jun 29 06:35:13 PM PDT 24
Finished Jun 29 06:35:14 PM PDT 24
Peak memory 206196 kb
Host smart-59a0d110-7673-4e2c-98a9-2f424cf8aea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36496
12244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3649612244
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.325873102
Short name T561
Test name
Test status
Simulation time 181926855 ps
CPU time 0.79 seconds
Started Jun 29 06:35:13 PM PDT 24
Finished Jun 29 06:35:15 PM PDT 24
Peak memory 206196 kb
Host smart-6090eeb3-de7e-4fe8-9a75-f52883fbb3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32587
3102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.325873102
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2896654704
Short name T353
Test name
Test status
Simulation time 152957135 ps
CPU time 0.76 seconds
Started Jun 29 06:35:09 PM PDT 24
Finished Jun 29 06:35:10 PM PDT 24
Peak memory 206192 kb
Host smart-41db8386-c48e-4a87-b765-73543a7557c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28966
54704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2896654704
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.462121391
Short name T1224
Test name
Test status
Simulation time 226201907 ps
CPU time 0.86 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:35:20 PM PDT 24
Peak memory 206192 kb
Host smart-ff3489a0-e54c-4409-90f6-699f12cde55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46212
1391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.462121391
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3357928237
Short name T1347
Test name
Test status
Simulation time 195170514 ps
CPU time 0.88 seconds
Started Jun 29 06:35:18 PM PDT 24
Finished Jun 29 06:35:21 PM PDT 24
Peak memory 206208 kb
Host smart-19a96ca2-e60d-49cc-81e0-165a04e7ec8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33579
28237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3357928237
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2741239373
Short name T1112
Test name
Test status
Simulation time 4567746381 ps
CPU time 33.91 seconds
Started Jun 29 06:35:15 PM PDT 24
Finished Jun 29 06:35:49 PM PDT 24
Peak memory 206424 kb
Host smart-d52d8163-9b0e-4a55-8880-0304291bb279
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2741239373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2741239373
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1024977065
Short name T2361
Test name
Test status
Simulation time 143584022 ps
CPU time 0.74 seconds
Started Jun 29 06:35:09 PM PDT 24
Finished Jun 29 06:35:10 PM PDT 24
Peak memory 206224 kb
Host smart-99653a76-36a6-4fa2-a4e3-e04affa34b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10249
77065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1024977065
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3072571241
Short name T813
Test name
Test status
Simulation time 177983137 ps
CPU time 0.82 seconds
Started Jun 29 06:35:15 PM PDT 24
Finished Jun 29 06:35:16 PM PDT 24
Peak memory 206172 kb
Host smart-52c4890d-9940-492c-ab12-af0e514cf1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30725
71241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3072571241
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.4244558775
Short name T2600
Test name
Test status
Simulation time 4886595684 ps
CPU time 134.89 seconds
Started Jun 29 06:35:17 PM PDT 24
Finished Jun 29 06:37:33 PM PDT 24
Peak memory 206420 kb
Host smart-a6f74fde-832c-44b6-97f6-c0cc0d27223e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42445
58775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.4244558775
Directory /workspace/9.usbdev_streaming_out/latest
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