Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	120599	1		T1	2		T2	2		T3	3
all_values[1]	120599	1		T1	2		T2	2		T3	3
all_values[2]	120599	1		T1	2		T2	2		T3	3
all_values[3]	120599	1		T1	2		T2	2		T3	3
all_values[4]	120599	1		T1	2		T2	2		T3	3
all_values[5]	120599	1		T1	2		T2	2		T3	3
all_values[6]	120599	1		T1	2		T2	2		T3	3
all_values[7]	120599	1		T1	2		T2	2		T3	3
all_values[8]	120599	1		T1	2		T2	2		T3	3
all_values[9]	120599	1		T1	2		T2	2		T3	3
all_values[10]	120599	1		T1	2		T2	2		T3	3
all_values[11]	120599	1		T1	2		T2	2		T3	3
all_values[12]	120599	1		T1	2		T2	2		T3	3
all_values[13]	120599	1		T1	2		T2	2		T3	3
all_values[14]	120599	1		T1	2		T2	2		T3	3
all_values[15]	120599	1		T1	2		T2	2		T3	3
all_values[16]	120599	1		T1	2		T2	2		T3	3
all_values[17]	120599	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2163872	1		T1	36		T2	36		T3	54
auto[1]	6910	1		T28	2		T32	3		T33	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2166049	1		T1	36		T2	36		T3	54
auto[1]	4733	1		T226	127		T227	128		T228	123

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	119639	1		T1	2		T2	2		T3	3
all_values[0]	auto[0]	auto[1]	138	1		T226	6		T227	6		T228	4
all_values[0]	auto[1]	auto[0]	693	1		T48	3		T49	4		T50	3
all_values[0]	auto[1]	auto[1]	129	1		T226	1		T227	1		T228	3
all_values[1]	auto[0]	auto[0]	118809	1		T1	2		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	146	1		T226	3		T227	2		T228	6
all_values[1]	auto[1]	auto[0]	1531	1		T28	2		T32	3		T33	3
all_values[1]	auto[1]	auto[1]	113	1		T226	5		T227	6		T228	2
all_values[2]	auto[0]	auto[0]	120199	1		T1	2		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	138	1		T226	5		T227	1		T228	2
all_values[2]	auto[1]	auto[0]	121	1		T41	2		T43	2		T44	2
all_values[2]	auto[1]	auto[1]	141	1		T226	2		T227	7		T228	4
all_values[3]	auto[0]	auto[0]	118822	1		T1	2		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	122	1		T226	5		T227	1		T228	2
all_values[3]	auto[1]	auto[0]	1524	1		T63	1485		T228	2		T308	1
all_values[3]	auto[1]	auto[1]	131	1		T226	3		T227	7		T228	3
all_values[4]	auto[0]	auto[0]	120299	1		T1	2		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	163	1		T226	1		T227	2		T228	6
all_values[4]	auto[1]	auto[0]	28	1		T64	2		T229	1		T303	2
all_values[4]	auto[1]	auto[1]	109	1		T226	5		T227	6		T228	2
all_values[5]	auto[0]	auto[0]	120299	1		T1	2		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	135	1		T226	2		T227	8		T228	3
all_values[5]	auto[1]	auto[0]	36	1		T226	2		T229	2		T309	1
all_values[5]	auto[1]	auto[1]	129	1		T226	4		T228	5		T229	3
all_values[6]	auto[0]	auto[0]	120308	1		T1	2		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	92	1		T226	1		T227	1		T228	4
all_values[6]	auto[1]	auto[0]	31	1		T227	1		T229	1		T302	1
all_values[6]	auto[1]	auto[1]	168	1		T226	7		T227	6		T228	2
all_values[7]	auto[0]	auto[0]	120300	1		T1	2		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	120	1		T226	2		T227	1		T228	1
all_values[7]	auto[1]	auto[0]	36	1		T51	2		T52	2		T53	2
all_values[7]	auto[1]	auto[1]	143	1		T226	6		T227	5		T228	3
all_values[8]	auto[0]	auto[0]	120294	1		T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	137	1		T226	6		T227	4		T228	2
all_values[8]	auto[1]	auto[0]	39	1		T57	11		T310	1		T304	4
all_values[8]	auto[1]	auto[1]	129	1		T226	2		T227	2		T228	6
all_values[9]	auto[0]	auto[0]	120282	1		T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	148	1		T226	2		T227	6		T228	6
all_values[9]	auto[1]	auto[0]	64	1		T47	5		T61	5		T62	5
all_values[9]	auto[1]	auto[1]	105	1		T226	3		T227	2		T228	2
all_values[10]	auto[0]	auto[0]	120300	1		T1	2		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	123	1		T226	3		T228	4		T229	4
all_values[10]	auto[1]	auto[0]	22	1		T227	3		T228	3		T311	1
all_values[10]	auto[1]	auto[1]	154	1		T226	5		T227	4		T229	4
all_values[11]	auto[0]	auto[0]	120211	1		T1	2		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	148	1		T226	5		T227	4		T228	3
all_values[11]	auto[1]	auto[0]	125	1		T46	2		T68	2		T69	2
all_values[11]	auto[1]	auto[1]	115	1		T226	3		T227	4		T228	4
all_values[12]	auto[0]	auto[0]	120301	1		T1	2		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	95	1		T226	4		T227	4		T228	6
all_values[12]	auto[1]	auto[0]	51	1		T71	3		T72	3		T73	3
all_values[12]	auto[1]	auto[1]	152	1		T226	2		T227	4		T228	1
all_values[13]	auto[0]	auto[0]	120302	1		T1	2		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	126	1		T226	6		T227	2		T228	1
all_values[13]	auto[1]	auto[0]	29	1		T228	1		T310	1		T303	1
all_values[13]	auto[1]	auto[1]	142	1		T226	2		T227	3		T228	6
all_values[14]	auto[0]	auto[0]	120307	1		T1	2		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	110	1		T227	5		T228	2		T310	4
all_values[14]	auto[1]	auto[0]	32	1		T311	3		T308	4		T304	4
all_values[14]	auto[1]	auto[1]	150	1		T226	7		T227	3		T228	6
all_values[15]	auto[0]	auto[0]	120302	1		T1	2		T2	2		T3	3
all_values[15]	auto[0]	auto[1]	116	1		T226	2		T227	1		T228	5
all_values[15]	auto[1]	auto[0]	37	1		T228	1		T229	2		T310	1
all_values[15]	auto[1]	auto[1]	144	1		T226	6		T227	6		T228	1
all_values[16]	auto[0]	auto[0]	120282	1		T1	2		T2	2		T3	3
all_values[16]	auto[0]	auto[1]	133	1		T226	5		T227	5		T228	4
all_values[16]	auto[1]	auto[0]	53	1		T65	8		T66	8		T67	8
all_values[16]	auto[1]	auto[1]	131	1		T226	3		T227	3		T228	4
all_values[17]	auto[0]	auto[0]	120309	1		T1	2		T2	2		T3	3
all_values[17]	auto[0]	auto[1]	117	1		T227	4		T228	4		T229	3
all_values[17]	auto[1]	auto[0]	32	1		T226	3		T229	1		T310	1
all_values[17]	auto[1]	auto[1]	141	1		T226	3		T227	2		T228	4