Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	120599	1		T1	2		T2	2		T3	3
all_pins[1]	120599	1		T1	2		T2	2		T3	3
all_pins[2]	120599	1		T1	2		T2	2		T3	3
all_pins[3]	120599	1		T1	2		T2	2		T3	3
all_pins[4]	120599	1		T1	2		T2	2		T3	3
all_pins[5]	120599	1		T1	2		T2	2		T3	3
all_pins[6]	120599	1		T1	2		T2	2		T3	3
all_pins[7]	120599	1		T1	2		T2	2		T3	3
all_pins[8]	120599	1		T1	2		T2	2		T3	3
all_pins[9]	120599	1		T1	2		T2	2		T3	3
all_pins[10]	120599	1		T1	2		T2	2		T3	3
all_pins[11]	120599	1		T1	2		T2	2		T3	3
all_pins[12]	120599	1		T1	2		T2	2		T3	3
all_pins[13]	120599	1		T1	2		T2	2		T3	3
all_pins[14]	120599	1		T1	2		T2	2		T3	3
all_pins[15]	120599	1		T1	2		T2	2		T3	3
all_pins[16]	120599	1		T1	2		T2	2		T3	3
all_pins[17]	120599	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2168498	1		T1	36		T2	36		T3	54
values[0x1]	2284	1		T28	1		T32	1		T33	1
transitions[0x0=>0x1]	1989	1		T28	1		T32	1		T33	1
transitions[0x1=>0x0]	2001	1		T28	1		T32	1		T33	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	120495	1		T1	2		T2	2		T3	3
all_pins[0]	values[0x1]	104	1		T49	1		T312	1		T313	1
all_pins[0]	transitions[0x0=>0x1]	90	1		T49	1		T312	1		T313	1
all_pins[0]	transitions[0x1=>0x0]	984	1		T28	1		T32	1		T33	1
all_pins[1]	values[0x0]	119601	1		T1	2		T2	2		T3	3
all_pins[1]	values[0x1]	998	1		T28	1		T32	1		T33	1
all_pins[1]	transitions[0x0=>0x1]	980	1		T28	1		T32	1		T33	1
all_pins[1]	transitions[0x1=>0x0]	119	1		T41	1		T43	1		T44	1
all_pins[2]	values[0x0]	120462	1		T1	2		T2	2		T3	3
all_pins[2]	values[0x1]	137	1		T41	1		T43	1		T44	1
all_pins[2]	transitions[0x0=>0x1]	115	1		T41	1		T43	1		T44	1
all_pins[2]	transitions[0x1=>0x0]	44	1		T63	2		T226	2		T227	1
all_pins[3]	values[0x0]	120533	1		T1	2		T2	2		T3	3
all_pins[3]	values[0x1]	66	1		T63	2		T226	3		T227	4
all_pins[3]	transitions[0x0=>0x1]	50	1		T63	2		T226	2		T227	1
all_pins[3]	transitions[0x1=>0x0]	33	1		T64	1		T226	3		T228	1
all_pins[4]	values[0x0]	120550	1		T1	2		T2	2		T3	3
all_pins[4]	values[0x1]	49	1		T64	1		T226	4		T227	3
all_pins[4]	transitions[0x0=>0x1]	41	1		T64	1		T226	4		T227	3
all_pins[4]	transitions[0x1=>0x0]	45	1		T228	1		T229	3		T311	1
all_pins[5]	values[0x0]	120546	1		T1	2		T2	2		T3	3
all_pins[5]	values[0x1]	53	1		T228	1		T229	3		T311	1
all_pins[5]	transitions[0x0=>0x1]	44	1		T228	1		T229	2		T308	2
all_pins[5]	transitions[0x1=>0x0]	77	1		T226	4		T227	3		T228	2
all_pins[6]	values[0x0]	120513	1		T1	2		T2	2		T3	3
all_pins[6]	values[0x1]	86	1		T226	4		T227	3		T228	2
all_pins[6]	transitions[0x0=>0x1]	69	1		T226	3		T227	2		T228	2
all_pins[6]	transitions[0x1=>0x0]	44	1		T51	1		T52	1		T53	1
all_pins[7]	values[0x0]	120538	1		T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	61	1		T51	1		T52	1		T53	1
all_pins[7]	transitions[0x0=>0x1]	44	1		T51	1		T52	1		T53	1
all_pins[7]	transitions[0x1=>0x0]	44	1		T57	1		T227	1		T228	3
all_pins[8]	values[0x0]	120538	1		T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	61	1		T57	1		T226	1		T227	1
all_pins[8]	transitions[0x0=>0x1]	53	1		T57	1		T226	1		T227	1
all_pins[8]	transitions[0x1=>0x0]	47	1		T47	2		T61	2		T62	2
all_pins[9]	values[0x0]	120544	1		T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	55	1		T47	2		T61	2		T62	2
all_pins[9]	transitions[0x0=>0x1]	40	1		T47	2		T61	2		T62	2
all_pins[9]	transitions[0x1=>0x0]	55	1		T226	2		T229	3		T302	1
all_pins[10]	values[0x0]	120529	1		T1	2		T2	2		T3	3
all_pins[10]	values[0x1]	70	1		T226	2		T229	3		T310	1
all_pins[10]	transitions[0x0=>0x1]	49	1		T226	2		T229	1		T310	1
all_pins[10]	transitions[0x1=>0x0]	95	1		T46	1		T68	1		T69	1
all_pins[11]	values[0x0]	120483	1		T1	2		T2	2		T3	3
all_pins[11]	values[0x1]	116	1		T46	1		T68	1		T69	1
all_pins[11]	transitions[0x0=>0x1]	102	1		T46	1		T68	1		T69	1
all_pins[11]	transitions[0x1=>0x0]	67	1		T71	1		T72	1		T73	1
all_pins[12]	values[0x0]	120518	1		T1	2		T2	2		T3	3
all_pins[12]	values[0x1]	81	1		T71	1		T72	1		T73	1
all_pins[12]	transitions[0x0=>0x1]	62	1		T71	1		T72	1		T73	1
all_pins[12]	transitions[0x1=>0x0]	38	1		T227	2		T228	1		T229	1
all_pins[13]	values[0x0]	120542	1		T1	2		T2	2		T3	3
all_pins[13]	values[0x1]	57	1		T227	2		T228	1		T229	1
all_pins[13]	transitions[0x0=>0x1]	36	1		T227	2		T302	1		T311	1
all_pins[13]	transitions[0x1=>0x0]	52	1		T226	1		T228	4		T229	3
all_pins[14]	values[0x0]	120526	1		T1	2		T2	2		T3	3
all_pins[14]	values[0x1]	73	1		T226	1		T228	5		T229	4
all_pins[14]	transitions[0x0=>0x1]	51	1		T228	4		T229	2		T311	2
all_pins[14]	transitions[0x1=>0x0]	59	1		T226	3		T227	2		T310	2
all_pins[15]	values[0x0]	120518	1		T1	2		T2	2		T3	3
all_pins[15]	values[0x1]	81	1		T226	4		T227	2		T228	1
all_pins[15]	transitions[0x0=>0x1]	62	1		T226	3		T227	2		T228	1
all_pins[15]	transitions[0x1=>0x0]	56	1		T65	4		T66	4		T67	4
all_pins[16]	values[0x0]	120524	1		T1	2		T2	2		T3	3
all_pins[16]	values[0x1]	75	1		T65	4		T66	4		T67	4
all_pins[16]	transitions[0x0=>0x1]	61	1		T65	4		T66	4		T67	4
all_pins[16]	transitions[0x1=>0x0]	47	1		T226	1		T227	1		T228	2
all_pins[17]	values[0x0]	120538	1		T1	2		T2	2		T3	3
all_pins[17]	values[0x1]	61	1		T226	1		T227	1		T228	3
all_pins[17]	transitions[0x0=>0x1]	40	1		T226	1		T227	1		T228	3
all_pins[17]	transitions[0x1=>0x0]	95	1		T49	1		T312	1		T313	1