Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T226	7		T227	7		T228	7
all_values[1]	269	1		T226	7		T227	7		T228	7
all_values[2]	269	1		T226	7		T227	7		T228	7
all_values[3]	269	1		T226	7		T227	7		T228	7
all_values[4]	269	1		T226	7		T227	7		T228	7
all_values[5]	269	1		T226	7		T227	7		T228	7
all_values[6]	269	1		T226	7		T227	7		T228	7
all_values[7]	269	1		T226	7		T227	7		T228	7
all_values[8]	269	1		T226	7		T227	7		T228	7
all_values[9]	269	1		T226	7		T227	7		T228	7
all_values[10]	269	1		T226	7		T227	7		T228	7
all_values[11]	269	1		T226	7		T227	7		T228	7
all_values[12]	269	1		T226	7		T227	7		T228	7
all_values[13]	269	1		T226	7		T227	7		T228	7
all_values[14]	269	1		T226	7		T227	7		T228	7
all_values[15]	269	1		T226	7		T227	7		T228	7
all_values[16]	269	1		T226	7		T227	7		T228	7
all_values[17]	269	1		T226	7		T227	7		T228	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2567	1		T226	65		T227	67		T228	62
auto[1]	2275	1		T226	61		T227	59		T228	64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	939	1		T226	17		T227	16		T228	21
auto[1]	3903	1		T226	109		T227	110		T228	105

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2864	1		T226	75		T227	67		T228	70
auto[1]	1978	1		T226	51		T227	59		T228	56

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1		T226	1		T227	1		T228	1
all_values[0]	auto[0]	auto[0]	auto[1]	57	1		T226	4		T227	3		T228	2
all_values[0]	auto[0]	auto[1]	auto[0]	15	1		T314	2		T315	2		T316	1
all_values[0]	auto[0]	auto[1]	auto[1]	55	1		T226	1		T228	1		T229	1
all_values[0]	auto[1]	auto[0]	auto[1]	55	1		T228	1		T229	3		T310	2
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T226	1		T227	3		T228	2
all_values[1]	auto[0]	auto[0]	auto[0]	33	1		T302	2		T303	3		T317	1
all_values[1]	auto[0]	auto[0]	auto[1]	65	1		T226	1		T227	1		T228	2
all_values[1]	auto[0]	auto[1]	auto[0]	22	1		T303	1		T318	3		T315	1
all_values[1]	auto[0]	auto[1]	auto[1]	44	1		T226	2		T227	3		T229	1
all_values[1]	auto[1]	auto[0]	auto[1]	64	1		T226	1		T227	2		T228	2
all_values[1]	auto[1]	auto[1]	auto[1]	41	1		T226	3		T227	1		T228	3
all_values[2]	auto[0]	auto[0]	auto[0]	28	1		T226	1		T228	2		T229	1
all_values[2]	auto[0]	auto[0]	auto[1]	62	1		T226	3		T228	1		T229	2
all_values[2]	auto[0]	auto[1]	auto[0]	10	1		T303	4		T309	2		T319	1
all_values[2]	auto[0]	auto[1]	auto[1]	66	1		T226	1		T227	4		T228	1
all_values[2]	auto[1]	auto[0]	auto[1]	57	1		T227	1		T228	2		T229	3
all_values[2]	auto[1]	auto[1]	auto[1]	46	1		T226	2		T227	2		T228	1
all_values[3]	auto[0]	auto[0]	auto[0]	34	1		T228	1		T308	1		T304	1
all_values[3]	auto[0]	auto[0]	auto[1]	48	1		T226	3		T228	1		T229	1
all_values[3]	auto[0]	auto[1]	auto[0]	25	1		T228	2		T320	3		T321	2
all_values[3]	auto[0]	auto[1]	auto[1]	45	1		T227	2		T228	1		T229	2
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T226	3		T227	1		T228	1
all_values[3]	auto[1]	auto[1]	auto[1]	57	1		T226	1		T227	4		T228	1
all_values[4]	auto[0]	auto[0]	auto[0]	23	1		T226	2		T309	1		T308	1
all_values[4]	auto[0]	auto[0]	auto[1]	65	1		T228	2		T229	3		T302	2
all_values[4]	auto[0]	auto[1]	auto[0]	20	1		T229	1		T303	2		T321	3
all_values[4]	auto[0]	auto[1]	auto[1]	51	1		T226	4		T227	1		T228	1
all_values[4]	auto[1]	auto[0]	auto[1]	67	1		T226	1		T227	2		T228	3
all_values[4]	auto[1]	auto[1]	auto[1]	43	1		T227	4		T228	1		T229	1
all_values[5]	auto[0]	auto[0]	auto[0]	27	1		T226	1		T308	1		T322	1
all_values[5]	auto[0]	auto[0]	auto[1]	62	1		T227	4		T228	1		T229	1
all_values[5]	auto[0]	auto[1]	auto[0]	23	1		T226	1		T229	2		T309	1
all_values[5]	auto[0]	auto[1]	auto[1]	51	1		T226	2		T228	4		T310	1
all_values[5]	auto[1]	auto[0]	auto[1]	57	1		T226	1		T227	3		T228	1
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T226	2		T228	1		T229	4
all_values[6]	auto[0]	auto[0]	auto[0]	33	1		T227	1		T228	2		T311	2
all_values[6]	auto[0]	auto[0]	auto[1]	44	1		T226	1		T228	1		T310	1
all_values[6]	auto[0]	auto[1]	auto[0]	22	1		T229	1		T302	1		T308	1
all_values[6]	auto[0]	auto[1]	auto[1]	62	1		T226	2		T227	2		T229	2
all_values[6]	auto[1]	auto[0]	auto[1]	50	1		T226	1		T227	1		T228	3
all_values[6]	auto[1]	auto[1]	auto[1]	58	1		T226	3		T227	3		T228	1
all_values[7]	auto[0]	auto[0]	auto[0]	35	1		T227	2		T228	1		T229	4
all_values[7]	auto[0]	auto[0]	auto[1]	48	1		T226	1		T310	1		T302	3
all_values[7]	auto[0]	auto[1]	auto[0]	18	1		T228	3		T320	2		T314	2
all_values[7]	auto[0]	auto[1]	auto[1]	55	1		T226	3		T227	3		T228	1
all_values[7]	auto[1]	auto[0]	auto[1]	57	1		T226	1		T228	2		T310	2
all_values[7]	auto[1]	auto[1]	auto[1]	56	1		T226	2		T227	2		T229	2
all_values[8]	auto[0]	auto[0]	auto[0]	34	1		T227	2		T229	1		T310	1
all_values[8]	auto[0]	auto[0]	auto[1]	57	1		T226	4		T227	4		T228	1
all_values[8]	auto[0]	auto[1]	auto[0]	16	1		T304	2		T322	3		T319	1
all_values[8]	auto[0]	auto[1]	auto[1]	47	1		T228	2		T229	2		T310	1
all_values[8]	auto[1]	auto[0]	auto[1]	70	1		T226	2		T227	1		T228	2
all_values[8]	auto[1]	auto[1]	auto[1]	45	1		T226	1		T228	2		T229	3
all_values[9]	auto[0]	auto[0]	auto[0]	34	1		T226	3		T229	2		T302	2
all_values[9]	auto[0]	auto[0]	auto[1]	59	1		T227	1		T228	2		T229	1
all_values[9]	auto[0]	auto[1]	auto[0]	27	1		T229	2		T302	2		T309	2
all_values[9]	auto[0]	auto[1]	auto[1]	47	1		T226	2		T227	2		T311	3
all_values[9]	auto[1]	auto[0]	auto[1]	56	1		T226	2		T227	3		T228	1
all_values[9]	auto[1]	auto[1]	auto[1]	46	1		T227	1		T228	4		T229	2
all_values[10]	auto[0]	auto[0]	auto[0]	24	1		T227	2		T310	1		T311	1
all_values[10]	auto[0]	auto[0]	auto[1]	54	1		T226	1		T228	1		T229	2
all_values[10]	auto[0]	auto[1]	auto[0]	17	1		T227	2		T228	4		T318	1
all_values[10]	auto[0]	auto[1]	auto[1]	55	1		T226	1		T227	2		T229	1
all_values[10]	auto[1]	auto[0]	auto[1]	55	1		T226	3		T228	2		T229	4
all_values[10]	auto[1]	auto[1]	auto[1]	64	1		T226	2		T227	1		T310	1
all_values[11]	auto[0]	auto[0]	auto[0]	34	1		T228	1		T310	2		T302	1
all_values[11]	auto[0]	auto[0]	auto[1]	54	1		T226	2		T227	2		T311	3
all_values[11]	auto[0]	auto[1]	auto[0]	18	1		T229	1		T310	2		T303	1
all_values[11]	auto[0]	auto[1]	auto[1]	38	1		T226	1		T227	1		T228	3
all_values[11]	auto[1]	auto[0]	auto[1]	74	1		T226	2		T227	2		T228	3
all_values[11]	auto[1]	auto[1]	auto[1]	51	1		T226	2		T227	2		T229	2
all_values[12]	auto[0]	auto[0]	auto[0]	38	1		T226	1		T310	1		T304	4
all_values[12]	auto[0]	auto[0]	auto[1]	43	1		T226	1		T227	3		T228	3
all_values[12]	auto[0]	auto[1]	auto[0]	27	1		T226	1		T228	1		T229	1
all_values[12]	auto[0]	auto[1]	auto[1]	64	1		T226	1		T227	2		T229	2
all_values[12]	auto[1]	auto[0]	auto[1]	41	1		T226	2		T227	1		T228	1
all_values[12]	auto[1]	auto[1]	auto[1]	56	1		T226	1		T227	1		T228	2
all_values[13]	auto[0]	auto[0]	auto[0]	28	1		T227	3		T310	1		T304	1
all_values[13]	auto[0]	auto[0]	auto[1]	51	1		T226	3		T227	1		T228	1
all_values[13]	auto[0]	auto[1]	auto[0]	20	1		T228	1		T303	1		T309	1
all_values[13]	auto[0]	auto[1]	auto[1]	63	1		T226	3		T227	1		T228	3
all_values[13]	auto[1]	auto[0]	auto[1]	50	1		T226	1		T227	1		T229	2
all_values[13]	auto[1]	auto[1]	auto[1]	57	1		T227	1		T228	2		T229	2
all_values[14]	auto[0]	auto[0]	auto[0]	32	1		T226	1		T302	1		T311	1
all_values[14]	auto[0]	auto[0]	auto[1]	34	1		T227	1		T310	1		T303	2
all_values[14]	auto[0]	auto[1]	auto[0]	23	1		T311	2		T308	3		T304	2
all_values[14]	auto[0]	auto[1]	auto[1]	70	1		T226	5		T227	2		T228	4
all_values[14]	auto[1]	auto[0]	auto[1]	63	1		T227	4		T228	3		T310	2
all_values[14]	auto[1]	auto[1]	auto[1]	47	1		T226	1		T229	3		T311	1
all_values[15]	auto[0]	auto[0]	auto[0]	30	1		T227	1		T228	2		T310	1
all_values[15]	auto[0]	auto[0]	auto[1]	42	1		T228	1		T229	1		T311	1
all_values[15]	auto[0]	auto[1]	auto[0]	25	1		T229	2		T309	1		T308	1
all_values[15]	auto[0]	auto[1]	auto[1]	55	1		T226	1		T227	2		T228	1
all_values[15]	auto[1]	auto[0]	auto[1]	59	1		T226	2		T227	3		T228	2
all_values[15]	auto[1]	auto[1]	auto[1]	58	1		T226	4		T227	1		T228	1
all_values[16]	auto[0]	auto[0]	auto[0]	35	1		T310	1		T311	4		T322	1
all_values[16]	auto[0]	auto[0]	auto[1]	53	1		T226	4		T227	1		T228	1
all_values[16]	auto[0]	auto[1]	auto[0]	17	1		T310	1		T309	2		T314	1
all_values[16]	auto[0]	auto[1]	auto[1]	52	1		T228	4		T229	2		T311	1
all_values[16]	auto[1]	auto[0]	auto[1]	62	1		T226	2		T227	4		T229	2
all_values[16]	auto[1]	auto[1]	auto[1]	50	1		T226	1		T227	2		T228	2
all_values[17]	auto[0]	auto[0]	auto[0]	39	1		T226	3		T227	2		T310	1
all_values[17]	auto[0]	auto[0]	auto[1]	51	1		T227	1		T228	1		T229	4
all_values[17]	auto[0]	auto[1]	auto[0]	20	1		T226	2		T229	1		T309	1
all_values[17]	auto[0]	auto[1]	auto[1]	56	1		T226	1		T227	2		T228	2
all_values[17]	auto[1]	auto[0]	auto[1]	47	1		T227	2		T228	2		T310	1
all_values[17]	auto[1]	auto[1]	auto[1]	56	1		T226	1		T228	2		T229	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal