Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.31 97.82 93.72 97.44 73.44 96.21 98.17 96.40


Total test records in report: 2737
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T2574 /workspace/coverage/default/31.usbdev_min_length_in_transaction.4244068827 Jun 30 06:24:38 PM PDT 24 Jun 30 06:24:46 PM PDT 24 148860439 ps
T2575 /workspace/coverage/default/11.usbdev_aon_wake_disconnect.64877062 Jun 30 06:21:53 PM PDT 24 Jun 30 06:21:59 PM PDT 24 3571148233 ps
T2576 /workspace/coverage/default/36.usbdev_pending_in_trans.1263052150 Jun 30 06:25:24 PM PDT 24 Jun 30 06:25:28 PM PDT 24 174021975 ps
T2577 /workspace/coverage/default/4.usbdev_device_address.1354924363 Jun 30 06:20:40 PM PDT 24 Jun 30 06:21:08 PM PDT 24 13489432037 ps
T2578 /workspace/coverage/default/36.usbdev_device_address.2307210781 Jun 30 06:25:22 PM PDT 24 Jun 30 06:26:05 PM PDT 24 22415479595 ps
T2579 /workspace/coverage/default/15.usbdev_max_usb_traffic.1168771275 Jun 30 06:22:31 PM PDT 24 Jun 30 06:23:15 PM PDT 24 6311226113 ps
T2580 /workspace/coverage/default/15.usbdev_in_trans.2839236799 Jun 30 06:22:25 PM PDT 24 Jun 30 06:22:26 PM PDT 24 227820704 ps
T2581 /workspace/coverage/default/38.usbdev_in_trans.71374837 Jun 30 06:25:33 PM PDT 24 Jun 30 06:25:37 PM PDT 24 270035899 ps
T2582 /workspace/coverage/default/16.usbdev_in_iso.2117639780 Jun 30 06:22:39 PM PDT 24 Jun 30 06:22:41 PM PDT 24 155474270 ps
T2583 /workspace/coverage/default/18.usbdev_data_toggle_restore.3520747289 Jun 30 06:22:55 PM PDT 24 Jun 30 06:22:58 PM PDT 24 1211042994 ps
T2584 /workspace/coverage/default/19.usbdev_random_length_out_transaction.3406556036 Jun 30 06:23:02 PM PDT 24 Jun 30 06:23:04 PM PDT 24 157089493 ps
T2585 /workspace/coverage/default/5.usbdev_phy_config_pinflip.667137867 Jun 30 06:21:02 PM PDT 24 Jun 30 06:21:04 PM PDT 24 191474927 ps
T2586 /workspace/coverage/default/35.usbdev_random_length_out_transaction.3861114423 Jun 30 06:25:20 PM PDT 24 Jun 30 06:25:23 PM PDT 24 157385870 ps
T2587 /workspace/coverage/default/46.usbdev_streaming_out.41451649 Jun 30 06:26:26 PM PDT 24 Jun 30 06:29:41 PM PDT 24 6725058378 ps
T2588 /workspace/coverage/default/0.usbdev_pkt_received.2920579851 Jun 30 06:20:23 PM PDT 24 Jun 30 06:20:26 PM PDT 24 184038180 ps
T2589 /workspace/coverage/default/17.usbdev_alert_test.519860507 Jun 30 06:22:55 PM PDT 24 Jun 30 06:22:56 PM PDT 24 36646598 ps
T2590 /workspace/coverage/default/30.usbdev_alert_test.2879276365 Jun 30 06:24:37 PM PDT 24 Jun 30 06:24:40 PM PDT 24 40253758 ps
T2591 /workspace/coverage/default/32.usbdev_link_resume.569782468 Jun 30 06:24:36 PM PDT 24 Jun 30 06:25:02 PM PDT 24 23264585847 ps
T2592 /workspace/coverage/default/17.usbdev_max_length_out_transaction.3256664890 Jun 30 06:22:48 PM PDT 24 Jun 30 06:22:50 PM PDT 24 192148548 ps
T2593 /workspace/coverage/default/36.usbdev_random_length_out_transaction.170567553 Jun 30 06:25:26 PM PDT 24 Jun 30 06:25:29 PM PDT 24 158658870 ps
T2594 /workspace/coverage/default/31.usbdev_min_length_out_transaction.483021252 Jun 30 06:24:42 PM PDT 24 Jun 30 06:24:45 PM PDT 24 144915381 ps
T2595 /workspace/coverage/default/38.usbdev_out_trans_nak.2530076670 Jun 30 06:25:23 PM PDT 24 Jun 30 06:25:26 PM PDT 24 178373324 ps
T2596 /workspace/coverage/default/17.usbdev_out_stall.3222867025 Jun 30 06:22:45 PM PDT 24 Jun 30 06:22:46 PM PDT 24 184619201 ps
T2597 /workspace/coverage/default/2.usbdev_out_stall.1484112800 Jun 30 06:20:26 PM PDT 24 Jun 30 06:20:29 PM PDT 24 182183249 ps
T2598 /workspace/coverage/default/17.usbdev_enable.4161691269 Jun 30 06:22:48 PM PDT 24 Jun 30 06:22:50 PM PDT 24 45535747 ps
T2599 /workspace/coverage/default/21.usbdev_phy_config_pinflip.3521397150 Jun 30 06:23:24 PM PDT 24 Jun 30 06:23:25 PM PDT 24 205498981 ps
T2600 /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1540316140 Jun 30 06:20:34 PM PDT 24 Jun 30 06:21:16 PM PDT 24 4323124713 ps
T2601 /workspace/coverage/default/31.usbdev_max_length_in_transaction.2123336747 Jun 30 06:24:38 PM PDT 24 Jun 30 06:24:41 PM PDT 24 248649804 ps
T2602 /workspace/coverage/default/6.usbdev_stall_trans.3983607453 Jun 30 06:21:09 PM PDT 24 Jun 30 06:21:11 PM PDT 24 166493574 ps
T2603 /workspace/coverage/default/2.usbdev_rx_pid_err.3263159430 Jun 30 06:20:32 PM PDT 24 Jun 30 06:20:34 PM PDT 24 164006306 ps
T2604 /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1326040542 Jun 30 06:26:12 PM PDT 24 Jun 30 06:27:23 PM PDT 24 7664330472 ps
T2605 /workspace/coverage/default/18.usbdev_alert_test.1230358099 Jun 30 06:23:03 PM PDT 24 Jun 30 06:23:04 PM PDT 24 41783951 ps
T2606 /workspace/coverage/default/25.usbdev_in_trans.4080407151 Jun 30 06:23:54 PM PDT 24 Jun 30 06:23:57 PM PDT 24 236069488 ps
T2607 /workspace/coverage/default/10.usbdev_in_stall.4035344265 Jun 30 06:21:49 PM PDT 24 Jun 30 06:21:50 PM PDT 24 177663064 ps
T2608 /workspace/coverage/default/22.usbdev_link_resume.3298388977 Jun 30 06:23:33 PM PDT 24 Jun 30 06:23:56 PM PDT 24 23318729827 ps
T2609 /workspace/coverage/default/31.usbdev_data_toggle_restore.524838454 Jun 30 06:24:40 PM PDT 24 Jun 30 06:24:45 PM PDT 24 709191614 ps
T2610 /workspace/coverage/default/14.usbdev_pending_in_trans.2811015972 Jun 30 06:22:19 PM PDT 24 Jun 30 06:22:21 PM PDT 24 147051046 ps
T2611 /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1254392889 Jun 30 06:20:09 PM PDT 24 Jun 30 06:20:10 PM PDT 24 257632778 ps
T2612 /workspace/coverage/default/34.usbdev_out_stall.2883695772 Jun 30 06:25:13 PM PDT 24 Jun 30 06:25:14 PM PDT 24 148530051 ps
T2613 /workspace/coverage/default/2.usbdev_phy_config_pinflip.3555219432 Jun 30 06:20:33 PM PDT 24 Jun 30 06:20:35 PM PDT 24 194629333 ps
T2614 /workspace/coverage/default/22.usbdev_rx_crc_err.3641834502 Jun 30 06:23:28 PM PDT 24 Jun 30 06:23:29 PM PDT 24 140714990 ps
T2615 /workspace/coverage/default/27.usbdev_max_length_out_transaction.249960746 Jun 30 06:24:08 PM PDT 24 Jun 30 06:24:09 PM PDT 24 286476814 ps
T2616 /workspace/coverage/default/4.usbdev_setup_stage.3292242772 Jun 30 06:20:56 PM PDT 24 Jun 30 06:20:58 PM PDT 24 144881600 ps
T2617 /workspace/coverage/default/4.usbdev_min_length_in_transaction.129417174 Jun 30 06:20:47 PM PDT 24 Jun 30 06:20:48 PM PDT 24 173238000 ps
T2618 /workspace/coverage/default/27.usbdev_av_buffer.1015065140 Jun 30 06:24:06 PM PDT 24 Jun 30 06:24:07 PM PDT 24 152531212 ps
T123 /workspace/coverage/default/23.usbdev_nak_trans.4158336446 Jun 30 06:23:39 PM PDT 24 Jun 30 06:23:41 PM PDT 24 232340634 ps
T2619 /workspace/coverage/default/38.usbdev_link_resume.1578565999 Jun 30 06:25:26 PM PDT 24 Jun 30 06:25:55 PM PDT 24 23387935951 ps
T2620 /workspace/coverage/default/23.usbdev_alert_test.2277358974 Jun 30 06:23:39 PM PDT 24 Jun 30 06:23:40 PM PDT 24 40308626 ps
T2621 /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3461128059 Jun 30 06:21:03 PM PDT 24 Jun 30 06:21:05 PM PDT 24 233462730 ps
T2622 /workspace/coverage/default/29.usbdev_link_in_err.818803377 Jun 30 06:24:22 PM PDT 24 Jun 30 06:24:23 PM PDT 24 215312608 ps
T2623 /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.631357442 Jun 30 06:25:28 PM PDT 24 Jun 30 06:25:32 PM PDT 24 146025771 ps
T2624 /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1549899257 Jun 30 06:22:54 PM PDT 24 Jun 30 06:24:13 PM PDT 24 7730289798 ps
T2625 /workspace/coverage/default/3.usbdev_fifo_rst.3840721933 Jun 30 06:20:39 PM PDT 24 Jun 30 06:20:41 PM PDT 24 226130853 ps
T2626 /workspace/coverage/default/1.usbdev_setup_stage.4107013787 Jun 30 06:20:25 PM PDT 24 Jun 30 06:20:29 PM PDT 24 156325573 ps
T2627 /workspace/coverage/default/10.usbdev_in_trans.1676147227 Jun 30 06:21:45 PM PDT 24 Jun 30 06:21:47 PM PDT 24 233034409 ps
T2628 /workspace/coverage/default/12.usbdev_rx_crc_err.887826858 Jun 30 06:22:07 PM PDT 24 Jun 30 06:22:09 PM PDT 24 188200937 ps
T2629 /workspace/coverage/default/18.usbdev_endpoint_access.1636794494 Jun 30 06:22:58 PM PDT 24 Jun 30 06:23:01 PM PDT 24 829142470 ps
T2630 /workspace/coverage/default/48.usbdev_smoke.2684269889 Jun 30 06:27:09 PM PDT 24 Jun 30 06:27:12 PM PDT 24 176122238 ps
T2631 /workspace/coverage/default/1.usbdev_enable.1688211571 Jun 30 06:20:27 PM PDT 24 Jun 30 06:20:30 PM PDT 24 57026022 ps
T2632 /workspace/coverage/default/27.usbdev_setup_trans_ignored.213672190 Jun 30 06:24:11 PM PDT 24 Jun 30 06:24:12 PM PDT 24 147082065 ps
T2633 /workspace/coverage/default/19.usbdev_nak_trans.1256819537 Jun 30 06:23:03 PM PDT 24 Jun 30 06:23:05 PM PDT 24 203550488 ps
T2634 /workspace/coverage/default/4.usbdev_data_toggle_clear.4194093756 Jun 30 06:20:43 PM PDT 24 Jun 30 06:20:44 PM PDT 24 184609949 ps
T226 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.583351475 Jun 30 05:43:16 PM PDT 24 Jun 30 05:43:18 PM PDT 24 42208954 ps
T217 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.726202618 Jun 30 05:43:04 PM PDT 24 Jun 30 05:43:07 PM PDT 24 181297361 ps
T227 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3472225326 Jun 30 05:43:28 PM PDT 24 Jun 30 05:43:29 PM PDT 24 53607954 ps
T228 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2371449532 Jun 30 05:43:28 PM PDT 24 Jun 30 05:43:30 PM PDT 24 45971869 ps
T218 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.221708353 Jun 30 05:42:51 PM PDT 24 Jun 30 05:42:54 PM PDT 24 180918294 ps
T229 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1126353060 Jun 30 05:43:10 PM PDT 24 Jun 30 05:43:11 PM PDT 24 46866740 ps
T220 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.42490263 Jun 30 05:43:04 PM PDT 24 Jun 30 05:43:07 PM PDT 24 303915433 ps
T221 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3320037533 Jun 30 05:42:41 PM PDT 24 Jun 30 05:42:46 PM PDT 24 674536687 ps
T219 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.117115590 Jun 30 05:43:23 PM PDT 24 Jun 30 05:43:25 PM PDT 24 112853665 ps
T222 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.514415491 Jun 30 05:43:15 PM PDT 24 Jun 30 05:43:18 PM PDT 24 121372675 ps
T310 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.531991298 Jun 30 05:43:30 PM PDT 24 Jun 30 05:43:32 PM PDT 24 41044069 ps
T302 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2109138939 Jun 30 05:43:08 PM PDT 24 Jun 30 05:43:09 PM PDT 24 69470928 ps
T2635 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1257407212 Jun 30 05:42:43 PM PDT 24 Jun 30 05:42:47 PM PDT 24 136366819 ps
T241 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1063721511 Jun 30 05:43:22 PM PDT 24 Jun 30 05:43:25 PM PDT 24 102378356 ps
T286 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.421091252 Jun 30 05:42:55 PM PDT 24 Jun 30 05:42:56 PM PDT 24 66079437 ps
T311 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3782445546 Jun 30 05:42:49 PM PDT 24 Jun 30 05:42:51 PM PDT 24 72136244 ps
T272 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2675487248 Jun 30 05:42:42 PM PDT 24 Jun 30 05:42:46 PM PDT 24 188333618 ps
T273 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1429067813 Jun 30 05:42:49 PM PDT 24 Jun 30 05:42:51 PM PDT 24 49011394 ps
T303 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3153063807 Jun 30 05:43:34 PM PDT 24 Jun 30 05:43:36 PM PDT 24 62988518 ps
T256 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.526238649 Jun 30 05:43:15 PM PDT 24 Jun 30 05:43:17 PM PDT 24 152828147 ps
T287 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.736331891 Jun 30 05:42:49 PM PDT 24 Jun 30 05:42:51 PM PDT 24 53735059 ps
T309 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1745082490 Jun 30 05:43:31 PM PDT 24 Jun 30 05:43:32 PM PDT 24 49739184 ps
T2636 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.968148989 Jun 30 05:42:56 PM PDT 24 Jun 30 05:42:59 PM PDT 24 412127804 ps
T240 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4106451498 Jun 30 05:43:16 PM PDT 24 Jun 30 05:43:22 PM PDT 24 975833056 ps
T288 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1118239365 Jun 30 05:43:22 PM PDT 24 Jun 30 05:43:24 PM PDT 24 78430679 ps
T308 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.246997057 Jun 30 05:43:21 PM PDT 24 Jun 30 05:43:22 PM PDT 24 43597215 ps
T245 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4187057410 Jun 30 05:42:47 PM PDT 24 Jun 30 05:42:50 PM PDT 24 158478932 ps
T264 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2622039346 Jun 30 05:43:28 PM PDT 24 Jun 30 05:43:32 PM PDT 24 132252829 ps
T289 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1650467411 Jun 30 05:43:31 PM PDT 24 Jun 30 05:43:33 PM PDT 24 89269620 ps
T246 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4216800106 Jun 30 05:43:34 PM PDT 24 Jun 30 05:43:38 PM PDT 24 400283735 ps
T304 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.289152930 Jun 30 05:43:29 PM PDT 24 Jun 30 05:43:30 PM PDT 24 36943444 ps
T247 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1368496573 Jun 30 05:42:43 PM PDT 24 Jun 30 05:42:48 PM PDT 24 681111280 ps
T265 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.647224834 Jun 30 05:43:09 PM PDT 24 Jun 30 05:43:14 PM PDT 24 713542232 ps
T253 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2153991686 Jun 30 05:43:09 PM PDT 24 Jun 30 05:43:11 PM PDT 24 82607578 ps
T274 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2670459361 Jun 30 05:42:56 PM PDT 24 Jun 30 05:42:59 PM PDT 24 116649163 ps
T290 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3506942568 Jun 30 05:43:15 PM PDT 24 Jun 30 05:43:17 PM PDT 24 64975400 ps
T322 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.298753202 Jun 30 05:43:04 PM PDT 24 Jun 30 05:43:05 PM PDT 24 68913681 ps
T251 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2590329662 Jun 30 05:43:08 PM PDT 24 Jun 30 05:43:11 PM PDT 24 141811806 ps
T275 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2859437389 Jun 30 05:42:52 PM PDT 24 Jun 30 05:43:00 PM PDT 24 1051444197 ps
T276 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3242920648 Jun 30 05:43:09 PM PDT 24 Jun 30 05:43:10 PM PDT 24 66373871 ps
T252 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2052296144 Jun 30 05:42:51 PM PDT 24 Jun 30 05:42:55 PM PDT 24 100698713 ps
T319 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1758878734 Jun 30 05:43:23 PM PDT 24 Jun 30 05:43:24 PM PDT 24 92466818 ps
T295 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.88080495 Jun 30 05:43:04 PM PDT 24 Jun 30 05:43:08 PM PDT 24 391275150 ps
T301 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3400314725 Jun 30 05:43:22 PM PDT 24 Jun 30 05:43:24 PM PDT 24 57206598 ps
T320 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1205273218 Jun 30 05:43:28 PM PDT 24 Jun 30 05:43:30 PM PDT 24 74058276 ps
T296 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4204723409 Jun 30 05:43:04 PM PDT 24 Jun 30 05:43:06 PM PDT 24 159585007 ps
T2637 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1288650236 Jun 30 05:42:50 PM PDT 24 Jun 30 05:42:53 PM PDT 24 102567841 ps
T321 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.951454817 Jun 30 05:43:05 PM PDT 24 Jun 30 05:43:06 PM PDT 24 49817974 ps
T2638 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4058093043 Jun 30 05:42:57 PM PDT 24 Jun 30 05:43:00 PM PDT 24 305061260 ps
T277 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2224285490 Jun 30 05:43:16 PM PDT 24 Jun 30 05:43:18 PM PDT 24 91926161 ps
T278 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2463541923 Jun 30 05:42:50 PM PDT 24 Jun 30 05:42:51 PM PDT 24 76318532 ps
T279 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.160444398 Jun 30 05:42:54 PM PDT 24 Jun 30 05:42:55 PM PDT 24 89272712 ps
T314 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.322532407 Jun 30 05:43:01 PM PDT 24 Jun 30 05:43:02 PM PDT 24 35194829 ps
T2639 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1649053040 Jun 30 05:43:30 PM PDT 24 Jun 30 05:43:33 PM PDT 24 92338963 ps
T297 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2488301909 Jun 30 05:43:10 PM PDT 24 Jun 30 05:43:12 PM PDT 24 207530483 ps
T2640 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1262324500 Jun 30 05:42:41 PM PDT 24 Jun 30 05:42:43 PM PDT 24 79052865 ps
T317 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.537085745 Jun 30 05:43:33 PM PDT 24 Jun 30 05:43:34 PM PDT 24 44482020 ps
T2641 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1963028802 Jun 30 05:43:35 PM PDT 24 Jun 30 05:43:36 PM PDT 24 65355607 ps
T298 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3014430319 Jun 30 05:42:49 PM PDT 24 Jun 30 05:42:55 PM PDT 24 894976616 ps
T299 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3160028570 Jun 30 05:43:23 PM PDT 24 Jun 30 05:43:26 PM PDT 24 501900672 ps
T323 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.577747338 Jun 30 05:43:04 PM PDT 24 Jun 30 05:43:10 PM PDT 24 812353426 ps
T2642 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.378017515 Jun 30 05:43:28 PM PDT 24 Jun 30 05:43:29 PM PDT 24 78867814 ps
T318 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2753102423 Jun 30 05:43:29 PM PDT 24 Jun 30 05:43:31 PM PDT 24 38027014 ps
T2643 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2882835630 Jun 30 05:43:27 PM PDT 24 Jun 30 05:43:28 PM PDT 24 38952165 ps
T2644 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.897071411 Jun 30 05:42:57 PM PDT 24 Jun 30 05:43:06 PM PDT 24 1221439938 ps
T325 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.695323806 Jun 30 05:43:22 PM PDT 24 Jun 30 05:43:30 PM PDT 24 2311430374 ps
T254 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3951894364 Jun 30 05:43:32 PM PDT 24 Jun 30 05:43:34 PM PDT 24 130487533 ps
T2645 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.947896989 Jun 30 05:42:50 PM PDT 24 Jun 30 05:42:53 PM PDT 24 272621813 ps
T2646 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2007961104 Jun 30 05:43:29 PM PDT 24 Jun 30 05:43:31 PM PDT 24 50949152 ps
T2647 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3135896850 Jun 30 05:43:08 PM PDT 24 Jun 30 05:43:10 PM PDT 24 126611451 ps
T305 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2314065201 Jun 30 05:42:55 PM PDT 24 Jun 30 05:43:01 PM PDT 24 1355358179 ps
T306 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3686995002 Jun 30 05:43:10 PM PDT 24 Jun 30 05:43:16 PM PDT 24 2195846832 ps
T2648 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1603568051 Jun 30 05:42:43 PM PDT 24 Jun 30 05:42:49 PM PDT 24 763995133 ps
T2649 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2017929836 Jun 30 05:43:33 PM PDT 24 Jun 30 05:43:38 PM PDT 24 787030927 ps
T2650 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.69530693 Jun 30 05:43:03 PM PDT 24 Jun 30 05:43:05 PM PDT 24 123004869 ps
T2651 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.218638934 Jun 30 05:43:35 PM PDT 24 Jun 30 05:43:36 PM PDT 24 64875152 ps
T300 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.850790950 Jun 30 05:43:30 PM PDT 24 Jun 30 05:43:33 PM PDT 24 393963415 ps
T315 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3877961576 Jun 30 05:43:30 PM PDT 24 Jun 30 05:43:32 PM PDT 24 34395136 ps
T2652 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1096700545 Jun 30 05:43:27 PM PDT 24 Jun 30 05:43:29 PM PDT 24 178992273 ps
T2653 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1095735598 Jun 30 05:43:15 PM PDT 24 Jun 30 05:43:17 PM PDT 24 60204870 ps
T280 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1607067446 Jun 30 05:42:54 PM PDT 24 Jun 30 05:42:59 PM PDT 24 512825530 ps
T281 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1160877822 Jun 30 05:42:50 PM PDT 24 Jun 30 05:42:54 PM PDT 24 95736285 ps
T2654 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3703710617 Jun 30 05:43:33 PM PDT 24 Jun 30 05:43:34 PM PDT 24 56743005 ps
T316 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2474074943 Jun 30 05:42:49 PM PDT 24 Jun 30 05:42:51 PM PDT 24 40440858 ps
T2655 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3553288081 Jun 30 05:42:43 PM PDT 24 Jun 30 05:42:45 PM PDT 24 125964420 ps
T2656 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.393294423 Jun 30 05:43:22 PM PDT 24 Jun 30 05:43:24 PM PDT 24 167253818 ps
T2657 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2433034925 Jun 30 05:43:04 PM PDT 24 Jun 30 05:43:05 PM PDT 24 82030978 ps
T2658 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2898838169 Jun 30 05:42:41 PM PDT 24 Jun 30 05:42:46 PM PDT 24 583406390 ps
T307 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1447078048 Jun 30 05:43:15 PM PDT 24 Jun 30 05:43:21 PM PDT 24 777386625 ps
T2659 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4291389092 Jun 30 05:43:04 PM PDT 24 Jun 30 05:43:06 PM PDT 24 177301382 ps
T284 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.361284991 Jun 30 05:43:02 PM PDT 24 Jun 30 05:43:03 PM PDT 24 75934011 ps
T258 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.539457069 Jun 30 05:43:15 PM PDT 24 Jun 30 05:43:19 PM PDT 24 266985272 ps
T2660 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1443309614 Jun 30 05:43:02 PM PDT 24 Jun 30 05:43:04 PM PDT 24 159422161 ps
T2661 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3460286765 Jun 30 05:42:51 PM PDT 24 Jun 30 05:42:55 PM PDT 24 304479208 ps
T2662 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3798511668 Jun 30 05:43:28 PM PDT 24 Jun 30 05:43:30 PM PDT 24 45521272 ps
T285 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3965940544 Jun 30 05:43:32 PM PDT 24 Jun 30 05:43:33 PM PDT 24 74445818 ps
T2663 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3202027768 Jun 30 05:43:09 PM PDT 24 Jun 30 05:43:12 PM PDT 24 285862398 ps
T255 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2670972987 Jun 30 05:43:10 PM PDT 24 Jun 30 05:43:13 PM PDT 24 327496538 ps
T2664 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2443732266 Jun 30 05:43:21 PM PDT 24 Jun 30 05:43:22 PM PDT 24 70510144 ps
T2665 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.408137849 Jun 30 05:43:16 PM PDT 24 Jun 30 05:43:21 PM PDT 24 947293623 ps
T2666 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3417951068 Jun 30 05:43:13 PM PDT 24 Jun 30 05:43:15 PM PDT 24 110286819 ps
T2667 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2892136623 Jun 30 05:42:56 PM PDT 24 Jun 30 05:42:58 PM PDT 24 104230548 ps
T2668 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.143045239 Jun 30 05:42:50 PM PDT 24 Jun 30 05:42:53 PM PDT 24 168558713 ps
T2669 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3720375 Jun 30 05:43:31 PM PDT 24 Jun 30 05:43:32 PM PDT 24 36778603 ps
T2670 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.794736296 Jun 30 05:43:33 PM PDT 24 Jun 30 05:43:34 PM PDT 24 46091590 ps
T2671 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1328754776 Jun 30 05:43:15 PM PDT 24 Jun 30 05:43:16 PM PDT 24 69987724 ps
T282 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2573911110 Jun 30 05:42:42 PM PDT 24 Jun 30 05:42:43 PM PDT 24 78458830 ps
T2672 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3309723303 Jun 30 05:42:46 PM PDT 24 Jun 30 05:42:48 PM PDT 24 64781807 ps
T2673 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3415872676 Jun 30 05:42:48 PM PDT 24 Jun 30 05:42:49 PM PDT 24 37880443 ps
T283 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.326109723 Jun 30 05:43:32 PM PDT 24 Jun 30 05:43:34 PM PDT 24 72063273 ps
T2674 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.358128737 Jun 30 05:42:56 PM PDT 24 Jun 30 05:42:58 PM PDT 24 173780896 ps
T2675 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1090394920 Jun 30 05:43:28 PM PDT 24 Jun 30 05:43:29 PM PDT 24 41518506 ps
T2676 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3561456921 Jun 30 05:42:48 PM PDT 24 Jun 30 05:42:50 PM PDT 24 99952187 ps
T2677 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1222439718 Jun 30 05:43:04 PM PDT 24 Jun 30 05:43:07 PM PDT 24 245416154 ps
T2678 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4230903602 Jun 30 05:43:30 PM PDT 24 Jun 30 05:43:32 PM PDT 24 38063075 ps
T2679 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2347278978 Jun 30 05:42:47 PM PDT 24 Jun 30 05:42:49 PM PDT 24 148925643 ps
T2680 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.47941515 Jun 30 05:43:29 PM PDT 24 Jun 30 05:43:31 PM PDT 24 47202749 ps
T2681 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.112273447 Jun 30 05:43:16 PM PDT 24 Jun 30 05:43:18 PM PDT 24 104595477 ps
T2682 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1403624741 Jun 30 05:43:15 PM PDT 24 Jun 30 05:43:17 PM PDT 24 92928193 ps
T2683 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1471087012 Jun 30 05:43:04 PM PDT 24 Jun 30 05:43:06 PM PDT 24 41042659 ps
T2684 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1684966788 Jun 30 05:43:34 PM PDT 24 Jun 30 05:43:35 PM PDT 24 54387544 ps
T2685 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.111945644 Jun 30 05:43:01 PM PDT 24 Jun 30 05:43:05 PM PDT 24 300669122 ps
T324 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2040147922 Jun 30 05:42:43 PM PDT 24 Jun 30 05:42:49 PM PDT 24 872884626 ps
T2686 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4287924419 Jun 30 05:43:22 PM PDT 24 Jun 30 05:43:26 PM PDT 24 252102658 ps
T2687 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1026546549 Jun 30 05:43:29 PM PDT 24 Jun 30 05:43:32 PM PDT 24 114547410 ps
T2688 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2655453132 Jun 30 05:43:16 PM PDT 24 Jun 30 05:43:19 PM PDT 24 310601668 ps
T2689 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1894034514 Jun 30 05:43:23 PM PDT 24 Jun 30 05:43:24 PM PDT 24 73047069 ps
T2690 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1621206056 Jun 30 05:42:49 PM PDT 24 Jun 30 05:42:51 PM PDT 24 58596778 ps
T2691 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3275112652 Jun 30 05:43:23 PM PDT 24 Jun 30 05:43:27 PM PDT 24 472277677 ps
T2692 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2764740198 Jun 30 05:43:13 PM PDT 24 Jun 30 05:43:15 PM PDT 24 66157650 ps
T2693 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2237378990 Jun 30 05:43:16 PM PDT 24 Jun 30 05:43:19 PM PDT 24 121865798 ps
T2694 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4162047568 Jun 30 05:43:33 PM PDT 24 Jun 30 05:43:35 PM PDT 24 49291430 ps
T2695 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2395410115 Jun 30 05:42:57 PM PDT 24 Jun 30 05:43:00 PM PDT 24 259906425 ps
T2696 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3346962651 Jun 30 05:43:09 PM PDT 24 Jun 30 05:43:11 PM PDT 24 97714074 ps
T2697 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.426509526 Jun 30 05:43:33 PM PDT 24 Jun 30 05:43:34 PM PDT 24 35872933 ps
T2698 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1708808263 Jun 30 05:43:15 PM PDT 24 Jun 30 05:43:19 PM PDT 24 340616312 ps
T2699 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1833745970 Jun 30 05:43:03 PM PDT 24 Jun 30 05:43:04 PM PDT 24 47632167 ps
T2700 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.752876287 Jun 30 05:42:42 PM PDT 24 Jun 30 05:42:44 PM PDT 24 45730949 ps
T2701 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.527457296 Jun 30 05:42:54 PM PDT 24 Jun 30 05:42:56 PM PDT 24 186937198 ps
T2702 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2519461625 Jun 30 05:42:55 PM PDT 24 Jun 30 05:42:59 PM PDT 24 231124316 ps
T2703 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2350983115 Jun 30 05:42:56 PM PDT 24 Jun 30 05:42:57 PM PDT 24 61190745 ps
T2704 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1899046280 Jun 30 05:43:22 PM PDT 24 Jun 30 05:43:25 PM PDT 24 149242649 ps
T2705 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.845631140 Jun 30 05:43:06 PM PDT 24 Jun 30 05:43:08 PM PDT 24 223874927 ps
T2706 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3410825217 Jun 30 05:43:11 PM PDT 24 Jun 30 05:43:13 PM PDT 24 252766702 ps
T2707 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1618712107 Jun 30 05:42:50 PM PDT 24 Jun 30 05:42:53 PM PDT 24 259843321 ps
T2708 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.935785103 Jun 30 05:43:08 PM PDT 24 Jun 30 05:43:10 PM PDT 24 39739328 ps
T2709 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3696173315 Jun 30 05:43:11 PM PDT 24 Jun 30 05:43:13 PM PDT 24 63645822 ps
T2710 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3108625840 Jun 30 05:43:29 PM PDT 24 Jun 30 05:43:31 PM PDT 24 58737127 ps
T2711 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3481434418 Jun 30 05:43:32 PM PDT 24 Jun 30 05:43:34 PM PDT 24 102524344 ps
T2712 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4157902318 Jun 30 05:43:16 PM PDT 24 Jun 30 05:43:19 PM PDT 24 178992807 ps
T2713 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.452640709 Jun 30 05:43:08 PM PDT 24 Jun 30 05:43:10 PM PDT 24 103565096 ps
T2714 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2416904907 Jun 30 05:43:22 PM PDT 24 Jun 30 05:43:23 PM PDT 24 139574919 ps
T2715 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1149955683 Jun 30 05:43:22 PM PDT 24 Jun 30 05:43:24 PM PDT 24 98798930 ps
T2716 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.142896693 Jun 30 05:42:43 PM PDT 24 Jun 30 05:42:45 PM PDT 24 167149544 ps
T2717 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3108887495 Jun 30 05:43:28 PM PDT 24 Jun 30 05:43:29 PM PDT 24 37995189 ps
T2718 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2632704713 Jun 30 05:43:02 PM PDT 24 Jun 30 05:43:06 PM PDT 24 558039837 ps
T2719 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2415101861 Jun 30 05:43:15 PM PDT 24 Jun 30 05:43:18 PM PDT 24 154639626 ps
T2720 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.319699406 Jun 30 05:43:29 PM PDT 24 Jun 30 05:43:30 PM PDT 24 35779672 ps
T2721 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.605509515 Jun 30 05:43:24 PM PDT 24 Jun 30 05:43:26 PM PDT 24 171839699 ps
T2722 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3640374419 Jun 30 05:42:55 PM PDT 24 Jun 30 05:42:57 PM PDT 24 118751263 ps
T2723 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.594828090 Jun 30 05:43:33 PM PDT 24 Jun 30 05:43:34 PM PDT 24 103766427 ps
T2724 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.135020066 Jun 30 05:42:50 PM PDT 24 Jun 30 05:42:54 PM PDT 24 181620160 ps
T2725 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3921528490 Jun 30 05:42:55 PM PDT 24 Jun 30 05:42:57 PM PDT 24 264350106 ps
T2726 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3631297334 Jun 30 05:43:22 PM PDT 24 Jun 30 05:43:26 PM PDT 24 265864104 ps
T2727 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4201935312 Jun 30 05:43:29 PM PDT 24 Jun 30 05:43:30 PM PDT 24 44447722 ps
T2728 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3461734728 Jun 30 05:43:27 PM PDT 24 Jun 30 05:43:31 PM PDT 24 267629156 ps
T2729 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.295514444 Jun 30 05:43:29 PM PDT 24 Jun 30 05:43:31 PM PDT 24 46819983 ps
T2730 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1559106016 Jun 30 05:43:14 PM PDT 24 Jun 30 05:43:16 PM PDT 24 39825140 ps
T2731 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1820591988 Jun 30 05:43:29 PM PDT 24 Jun 30 05:43:31 PM PDT 24 93198779 ps
T2732 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1967590086 Jun 30 05:42:44 PM PDT 24 Jun 30 05:42:53 PM PDT 24 970719238 ps
T2733 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3823840663 Jun 30 05:43:11 PM PDT 24 Jun 30 05:43:12 PM PDT 24 92025292 ps
T2734 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1430500854 Jun 30 05:43:30 PM PDT 24 Jun 30 05:43:34 PM PDT 24 354614678 ps
T2735 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1082259078 Jun 30 05:42:50 PM PDT 24 Jun 30 05:42:58 PM PDT 24 2021644724 ps
T2736 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3278409987 Jun 30 05:43:30 PM PDT 24 Jun 30 05:43:31 PM PDT 24 120066321 ps
T2737 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1094400006 Jun 30 05:43:16 PM PDT 24 Jun 30 05:43:18 PM PDT 24 49829490 ps

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3144656568
Short name T29
Test name
Test status
Simulation time 7200869546 ps
CPU time 16.83 seconds
Started Jun 30 06:21:18 PM PDT 24
Finished Jun 30 06:21:36 PM PDT 24
Peak memory 206420 kb
Host smart-afcea119-63b1-4ff8-9ddb-d0a63ef39de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31446
56568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3144656568
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.3699808161
Short name T5
Test name
Test status
Simulation time 13958959132 ps
CPU time 74.68 seconds
Started Jun 30 06:21:38 PM PDT 24
Finished Jun 30 06:22:53 PM PDT 24
Peak memory 206356 kb
Host smart-d8df2f45-b868-4c13-8f57-b350936c557a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3699808161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.3699808161
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1126353060
Short name T229
Test name
Test status
Simulation time 46866740 ps
CPU time 0.75 seconds
Started Jun 30 05:43:10 PM PDT 24
Finished Jun 30 05:43:11 PM PDT 24
Peak memory 205824 kb
Host smart-ced867c2-b280-4c3c-aefa-192560306edf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1126353060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1126353060
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.549526338
Short name T7
Test name
Test status
Simulation time 13359134119 ps
CPU time 13.91 seconds
Started Jun 30 06:20:15 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206328 kb
Host smart-bf581389-6705-459e-925c-7b269bc8ca9c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=549526338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.549526338
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4106451498
Short name T240
Test name
Test status
Simulation time 975833056 ps
CPU time 4.7 seconds
Started Jun 30 05:43:16 PM PDT 24
Finished Jun 30 05:43:22 PM PDT 24
Peak memory 205968 kb
Host smart-aa401add-1907-408c-b9cd-0287d1b0d41f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4106451498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.4106451498
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2138813034
Short name T83
Test name
Test status
Simulation time 18942682755 ps
CPU time 34.32 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:27:05 PM PDT 24
Peak memory 206420 kb
Host smart-30b6e507-d9f0-43d2-a7d7-163600fa5bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21388
13034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2138813034
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.778858779
Short name T424
Test name
Test status
Simulation time 158883182 ps
CPU time 0.8 seconds
Started Jun 30 06:20:07 PM PDT 24
Finished Jun 30 06:20:09 PM PDT 24
Peak memory 206200 kb
Host smart-34a44c47-81fd-4360-bbd7-51c4b8c721c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77885
8779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.778858779
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3782445546
Short name T311
Test name
Test status
Simulation time 72136244 ps
CPU time 0.7 seconds
Started Jun 30 05:42:49 PM PDT 24
Finished Jun 30 05:42:51 PM PDT 24
Peak memory 205788 kb
Host smart-bd66c1c5-a662-454f-9d31-53535778dd2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3782445546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3782445546
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1846493230
Short name T110
Test name
Test status
Simulation time 253221040 ps
CPU time 0.92 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:55 PM PDT 24
Peak memory 206184 kb
Host smart-c0ea831c-8595-43cb-90ac-460d6b78fc8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18464
93230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1846493230
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2926265457
Short name T390
Test name
Test status
Simulation time 153625887 ps
CPU time 0.75 seconds
Started Jun 30 06:22:25 PM PDT 24
Finished Jun 30 06:22:27 PM PDT 24
Peak memory 206180 kb
Host smart-fa92110c-8a0c-420a-bda7-b82bc805fb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29262
65457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2926265457
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2338405210
Short name T214
Test name
Test status
Simulation time 737422642 ps
CPU time 1.67 seconds
Started Jun 30 06:20:53 PM PDT 24
Finished Jun 30 06:20:55 PM PDT 24
Peak memory 225092 kb
Host smart-4ea5c16f-128f-48e8-bd82-b8ca2f5c440f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2338405210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2338405210
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1802777807
Short name T11
Test name
Test status
Simulation time 4418587919 ps
CPU time 5.48 seconds
Started Jun 30 06:23:10 PM PDT 24
Finished Jun 30 06:23:16 PM PDT 24
Peak memory 206404 kb
Host smart-d7d299bc-0f0f-4885-9a71-77571ac30239
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1802777807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.1802777807
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1468437970
Short name T108
Test name
Test status
Simulation time 435034116 ps
CPU time 1.41 seconds
Started Jun 30 06:24:03 PM PDT 24
Finished Jun 30 06:24:05 PM PDT 24
Peak memory 206168 kb
Host smart-69584c92-3c80-455e-9152-4236b7f3ffba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14684
37970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1468437970
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.726202618
Short name T217
Test name
Test status
Simulation time 181297361 ps
CPU time 2 seconds
Started Jun 30 05:43:04 PM PDT 24
Finished Jun 30 05:43:07 PM PDT 24
Peak memory 206080 kb
Host smart-240a50d7-3506-40ba-b9af-301c3c217113
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=726202618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.726202618
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1712733830
Short name T113
Test name
Test status
Simulation time 212730204 ps
CPU time 0.85 seconds
Started Jun 30 06:20:30 PM PDT 24
Finished Jun 30 06:20:32 PM PDT 24
Peak memory 206144 kb
Host smart-aadc7e19-0a88-4573-998c-c5232f24993a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17127
33830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1712733830
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.783949230
Short name T24
Test name
Test status
Simulation time 27236567 ps
CPU time 0.66 seconds
Started Jun 30 06:25:42 PM PDT 24
Finished Jun 30 06:25:43 PM PDT 24
Peak memory 206200 kb
Host smart-3b475e54-69f3-49cf-9252-00a0e27c5179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78394
9230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.783949230
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.699582028
Short name T46
Test name
Test status
Simulation time 230288160 ps
CPU time 0.87 seconds
Started Jun 30 06:23:35 PM PDT 24
Finished Jun 30 06:23:37 PM PDT 24
Peak memory 206152 kb
Host smart-feeb00ed-fdf9-4466-8a8d-0c9a6498cd30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69958
2028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.699582028
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2371449532
Short name T228
Test name
Test status
Simulation time 45971869 ps
CPU time 0.7 seconds
Started Jun 30 05:43:28 PM PDT 24
Finished Jun 30 05:43:30 PM PDT 24
Peak memory 205852 kb
Host smart-719adfd4-e485-46ef-852d-57245a855ec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2371449532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2371449532
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1162815223
Short name T75
Test name
Test status
Simulation time 306764724 ps
CPU time 0.91 seconds
Started Jun 30 06:20:07 PM PDT 24
Finished Jun 30 06:20:08 PM PDT 24
Peak memory 206168 kb
Host smart-c0568508-f363-4011-ad17-a226868d83cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11628
15223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.1162815223
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3320037533
Short name T221
Test name
Test status
Simulation time 674536687 ps
CPU time 4.53 seconds
Started Jun 30 05:42:41 PM PDT 24
Finished Jun 30 05:42:46 PM PDT 24
Peak memory 206188 kb
Host smart-651153ac-4b35-4bbf-8541-aec29090a0ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3320037533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3320037533
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.790824402
Short name T45
Test name
Test status
Simulation time 20209140473 ps
CPU time 21.55 seconds
Started Jun 30 06:20:15 PM PDT 24
Finished Jun 30 06:20:37 PM PDT 24
Peak memory 206308 kb
Host smart-1ec6b16d-6279-45be-ae0d-a1f6673e06e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79082
4402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.790824402
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3014430319
Short name T298
Test name
Test status
Simulation time 894976616 ps
CPU time 5.04 seconds
Started Jun 30 05:42:49 PM PDT 24
Finished Jun 30 05:42:55 PM PDT 24
Peak memory 206032 kb
Host smart-f2f35156-5c5a-45c7-841f-39ab85b716fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3014430319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3014430319
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2882835630
Short name T2643
Test name
Test status
Simulation time 38952165 ps
CPU time 0.64 seconds
Started Jun 30 05:43:27 PM PDT 24
Finished Jun 30 05:43:28 PM PDT 24
Peak memory 205816 kb
Host smart-5986e6d3-d4db-4e11-b22e-c3dcc3e25c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2882835630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2882835630
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2500780473
Short name T312
Test name
Test status
Simulation time 166038744 ps
CPU time 0.81 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:26 PM PDT 24
Peak memory 206164 kb
Host smart-541b098a-e7e2-4dd7-9418-3d7b18acce09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25007
80473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2500780473
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.3561852578
Short name T59
Test name
Test status
Simulation time 228295957 ps
CPU time 0.86 seconds
Started Jun 30 06:21:33 PM PDT 24
Finished Jun 30 06:21:35 PM PDT 24
Peak memory 206176 kb
Host smart-d92d1bf7-1d01-47f7-9e2c-6300a4e5b748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35618
52578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3561852578
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3415872676
Short name T2673
Test name
Test status
Simulation time 37880443 ps
CPU time 0.62 seconds
Started Jun 30 05:42:48 PM PDT 24
Finished Jun 30 05:42:49 PM PDT 24
Peak memory 205836 kb
Host smart-c6989bbc-6d45-451f-a14d-312d3787edf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3415872676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3415872676
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.4235718419
Short name T17
Test name
Test status
Simulation time 1002560159 ps
CPU time 2.31 seconds
Started Jun 30 06:22:09 PM PDT 24
Finished Jun 30 06:22:13 PM PDT 24
Peak memory 206304 kb
Host smart-d8b2e47d-f1a0-464f-b940-a08486615970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42357
18419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.4235718419
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.41183957
Short name T162
Test name
Test status
Simulation time 15068782455 ps
CPU time 313.35 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:25:41 PM PDT 24
Peak memory 206468 kb
Host smart-4e7adfd8-89ce-4be1-97b1-14445285e246
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=41183957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.41183957
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3686995002
Short name T306
Test name
Test status
Simulation time 2195846832 ps
CPU time 5.53 seconds
Started Jun 30 05:43:10 PM PDT 24
Finished Jun 30 05:43:16 PM PDT 24
Peak memory 206088 kb
Host smart-31343a52-ff94-4321-99f5-a5b7215c7b5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3686995002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3686995002
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.182007467
Short name T66
Test name
Test status
Simulation time 507499309 ps
CPU time 1.42 seconds
Started Jun 30 06:20:00 PM PDT 24
Finished Jun 30 06:20:02 PM PDT 24
Peak memory 206200 kb
Host smart-9da1bf69-2183-4b5c-bd78-7a06fbf575e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18200
7467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.182007467
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1090394920
Short name T2675
Test name
Test status
Simulation time 41518506 ps
CPU time 0.73 seconds
Started Jun 30 05:43:28 PM PDT 24
Finished Jun 30 05:43:29 PM PDT 24
Peak memory 205840 kb
Host smart-d68b9bdb-3d1a-4a67-a696-6dce3fe806d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1090394920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1090394920
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.3491663387
Short name T70
Test name
Test status
Simulation time 8834883245 ps
CPU time 244.72 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:27:37 PM PDT 24
Peak memory 206500 kb
Host smart-c50b186e-809e-44e2-92f0-7e02676ec6db
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3491663387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.3491663387
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1943138495
Short name T34
Test name
Test status
Simulation time 45148527 ps
CPU time 0.68 seconds
Started Jun 30 06:20:28 PM PDT 24
Finished Jun 30 06:20:30 PM PDT 24
Peak memory 206204 kb
Host smart-e12af9a8-7db3-47e6-a39b-fb48fa9715e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1943138495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1943138495
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1708808263
Short name T2698
Test name
Test status
Simulation time 340616312 ps
CPU time 3.51 seconds
Started Jun 30 05:43:15 PM PDT 24
Finished Jun 30 05:43:19 PM PDT 24
Peak memory 222132 kb
Host smart-2de262ff-495c-454c-9d81-48fa84430426
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1708808263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1708808263
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1214726662
Short name T89
Test name
Test status
Simulation time 18619911452 ps
CPU time 42.13 seconds
Started Jun 30 06:22:09 PM PDT 24
Finished Jun 30 06:22:53 PM PDT 24
Peak memory 206408 kb
Host smart-37c952f1-d921-4bb8-8836-a698f5f09e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12147
26662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1214726662
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.371405646
Short name T57
Test name
Test status
Simulation time 242882741 ps
CPU time 1.03 seconds
Started Jun 30 06:20:18 PM PDT 24
Finished Jun 30 06:20:20 PM PDT 24
Peak memory 206208 kb
Host smart-d081711d-8e52-470b-896b-828db0a9a62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37140
5646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.371405646
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1429067813
Short name T273
Test name
Test status
Simulation time 49011394 ps
CPU time 0.84 seconds
Started Jun 30 05:42:49 PM PDT 24
Finished Jun 30 05:42:51 PM PDT 24
Peak memory 205364 kb
Host smart-c8e13fca-b7f2-4529-831a-a3e123cd4c93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1429067813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1429067813
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.703745162
Short name T61
Test name
Test status
Simulation time 153844178 ps
CPU time 0.78 seconds
Started Jun 30 06:19:57 PM PDT 24
Finished Jun 30 06:19:59 PM PDT 24
Peak memory 206188 kb
Host smart-4de6ee5a-657b-41e2-99cd-34647ded9c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70374
5162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.703745162
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.130396176
Short name T260
Test name
Test status
Simulation time 6336453126 ps
CPU time 59.78 seconds
Started Jun 30 06:20:45 PM PDT 24
Finished Jun 30 06:21:45 PM PDT 24
Peak memory 206444 kb
Host smart-05132896-2f17-458d-aca7-a3577d783f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13039
6176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.130396176
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1894034514
Short name T2689
Test name
Test status
Simulation time 73047069 ps
CPU time 0.73 seconds
Started Jun 30 05:43:23 PM PDT 24
Finished Jun 30 05:43:24 PM PDT 24
Peak memory 205848 kb
Host smart-8fe21466-dbc4-4285-8db0-931df5b1e101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1894034514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1894034514
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2547020491
Short name T160
Test name
Test status
Simulation time 1395838500 ps
CPU time 3.07 seconds
Started Jun 30 06:21:11 PM PDT 24
Finished Jun 30 06:21:16 PM PDT 24
Peak memory 206260 kb
Host smart-86f3cb93-cacb-4e6a-a9ad-506c74651ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25470
20491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2547020491
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.461412608
Short name T91
Test name
Test status
Simulation time 143678655 ps
CPU time 0.74 seconds
Started Jun 30 06:22:54 PM PDT 24
Finished Jun 30 06:22:55 PM PDT 24
Peak memory 206208 kb
Host smart-65d023d8-2136-442e-978d-947e67b69ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46141
2608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.461412608
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.1592805925
Short name T212
Test name
Test status
Simulation time 23407929705 ps
CPU time 24.48 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206320 kb
Host smart-1df7312c-ce46-4d13-9509-48afa71bf009
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1592805925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.1592805925
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2960233235
Short name T426
Test name
Test status
Simulation time 197752498 ps
CPU time 1.24 seconds
Started Jun 30 06:20:00 PM PDT 24
Finished Jun 30 06:20:02 PM PDT 24
Peak memory 206192 kb
Host smart-09e3be8e-d36b-49c9-a016-84492af51b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29602
33235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2960233235
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1771759723
Short name T62
Test name
Test status
Simulation time 143414495 ps
CPU time 0.79 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:28 PM PDT 24
Peak memory 206164 kb
Host smart-1177f229-df63-4bcf-94ec-d396ee3f2f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17717
59723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1771759723
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.1473211566
Short name T98
Test name
Test status
Simulation time 8901271934 ps
CPU time 58.47 seconds
Started Jun 30 06:25:10 PM PDT 24
Finished Jun 30 06:26:09 PM PDT 24
Peak memory 206272 kb
Host smart-66335825-5d45-4d77-9fab-7e379337c84a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1473211566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.1473211566
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.1263815023
Short name T51
Test name
Test status
Simulation time 182382916 ps
CPU time 0.84 seconds
Started Jun 30 06:19:57 PM PDT 24
Finished Jun 30 06:19:59 PM PDT 24
Peak memory 206196 kb
Host smart-e1a957d1-1c35-44b8-a139-8da8e0652c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12638
15023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.1263815023
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1241395493
Short name T63
Test name
Test status
Simulation time 4175247826 ps
CPU time 8.87 seconds
Started Jun 30 06:19:55 PM PDT 24
Finished Jun 30 06:20:06 PM PDT 24
Peak memory 206364 kb
Host smart-170cfe22-5a10-4f1f-9a34-55fc053fad01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12413
95493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1241395493
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.2913083685
Short name T64
Test name
Test status
Simulation time 176587103 ps
CPU time 0.83 seconds
Started Jun 30 06:20:04 PM PDT 24
Finished Jun 30 06:20:05 PM PDT 24
Peak memory 206176 kb
Host smart-e3ba9ce6-2e2b-441d-9c01-b16c07c24542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29130
83685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.2913083685
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2665876746
Short name T157
Test name
Test status
Simulation time 9220188446 ps
CPU time 149.75 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:22:58 PM PDT 24
Peak memory 206484 kb
Host smart-752b4bc0-8c5d-478a-a87e-7c269efab749
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2665876746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2665876746
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1904096789
Short name T73
Test name
Test status
Simulation time 189025617 ps
CPU time 0.89 seconds
Started Jun 30 06:20:18 PM PDT 24
Finished Jun 30 06:20:20 PM PDT 24
Peak memory 206200 kb
Host smart-a7f91566-ef9c-4278-8009-45c907665749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19040
96789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1904096789
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2564472363
Short name T40
Test name
Test status
Simulation time 74818747 ps
CPU time 0.71 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:08 PM PDT 24
Peak memory 206192 kb
Host smart-48e72738-5aa2-4e1a-bcf6-bfbb6a46ca48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644
72363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2564472363
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.4041854845
Short name T1424
Test name
Test status
Simulation time 1246014914 ps
CPU time 3.03 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:36 PM PDT 24
Peak memory 206264 kb
Host smart-1336f836-ddcf-457b-8fb8-7810ce3caedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40418
54845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.4041854845
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4187057410
Short name T245
Test name
Test status
Simulation time 158478932 ps
CPU time 2.05 seconds
Started Jun 30 05:42:47 PM PDT 24
Finished Jun 30 05:42:50 PM PDT 24
Peak memory 222076 kb
Host smart-73067937-81da-48cb-8c5c-123eec727720
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4187057410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.4187057410
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.4230182139
Short name T119
Test name
Test status
Simulation time 196052160 ps
CPU time 0.93 seconds
Started Jun 30 06:20:02 PM PDT 24
Finished Jun 30 06:20:03 PM PDT 24
Peak memory 206192 kb
Host smart-266e5047-233c-4dcc-9685-8e50ffc0379d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42301
82139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.4230182139
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1697782583
Short name T180
Test name
Test status
Simulation time 172052160 ps
CPU time 0.9 seconds
Started Jun 30 06:20:09 PM PDT 24
Finished Jun 30 06:20:11 PM PDT 24
Peak memory 206208 kb
Host smart-73029b8b-280c-4721-9372-065a8d62c824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16977
82583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1697782583
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.781168105
Short name T55
Test name
Test status
Simulation time 416603959 ps
CPU time 1.34 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:27 PM PDT 24
Peak memory 206208 kb
Host smart-db22264e-c10e-408e-a408-c483eedc02ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78116
8105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.781168105
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3233138880
Short name T121
Test name
Test status
Simulation time 210390346 ps
CPU time 0.89 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:27 PM PDT 24
Peak memory 206172 kb
Host smart-2b6b41d4-43eb-428a-9f4d-338d8361e8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
38880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3233138880
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.293163905
Short name T158
Test name
Test status
Simulation time 344555443 ps
CPU time 0.97 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:25 PM PDT 24
Peak memory 206220 kb
Host smart-02661b87-f1a6-4954-bb00-fa1ac3e5dc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29316
3905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.293163905
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.4004227252
Short name T178
Test name
Test status
Simulation time 939893621 ps
CPU time 2.09 seconds
Started Jun 30 06:21:57 PM PDT 24
Finished Jun 30 06:22:00 PM PDT 24
Peak memory 206272 kb
Host smart-b9d24361-71c6-4103-ac56-2d9a3279fe4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042
27252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.4004227252
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1727248753
Short name T142
Test name
Test status
Simulation time 224188090 ps
CPU time 0.92 seconds
Started Jun 30 06:21:52 PM PDT 24
Finished Jun 30 06:21:55 PM PDT 24
Peak memory 206204 kb
Host smart-0d6968fe-e4ef-4a37-941f-b3e510bf5c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17272
48753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1727248753
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3832121156
Short name T134
Test name
Test status
Simulation time 210602336 ps
CPU time 1.01 seconds
Started Jun 30 06:22:01 PM PDT 24
Finished Jun 30 06:22:03 PM PDT 24
Peak memory 206164 kb
Host smart-e89e887e-2af2-45ae-b3f4-376614c3db10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38321
21156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3832121156
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_device_address.804112603
Short name T928
Test name
Test status
Simulation time 21198443695 ps
CPU time 42.47 seconds
Started Jun 30 06:22:10 PM PDT 24
Finished Jun 30 06:22:53 PM PDT 24
Peak memory 206404 kb
Host smart-e7e9cd8b-e174-4bd2-9120-37ececf7ebcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80411
2603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.804112603
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3918304197
Short name T127
Test name
Test status
Simulation time 213736405 ps
CPU time 0.83 seconds
Started Jun 30 06:22:16 PM PDT 24
Finished Jun 30 06:22:17 PM PDT 24
Peak memory 206192 kb
Host smart-ff810f88-72cb-402c-ae2c-40c7b114c1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39183
04197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3918304197
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.619116893
Short name T1571
Test name
Test status
Simulation time 181625200 ps
CPU time 0.83 seconds
Started Jun 30 06:22:33 PM PDT 24
Finished Jun 30 06:22:35 PM PDT 24
Peak memory 206212 kb
Host smart-8d7641d0-cf02-4c73-9f3d-0fc3eec7e038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61911
6893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.619116893
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2532304802
Short name T139
Test name
Test status
Simulation time 238125116 ps
CPU time 0.96 seconds
Started Jun 30 06:22:52 PM PDT 24
Finished Jun 30 06:22:53 PM PDT 24
Peak memory 206192 kb
Host smart-d56a2eb9-b4b7-4c5e-a57d-1cda1358add6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25323
04802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2532304802
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.603023188
Short name T21
Test name
Test status
Simulation time 188665067 ps
CPU time 0.85 seconds
Started Jun 30 06:23:07 PM PDT 24
Finished Jun 30 06:23:08 PM PDT 24
Peak memory 206192 kb
Host smart-2b7cb682-e66c-4e4e-8f85-f679cfb77686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60302
3188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.603023188
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4158336446
Short name T123
Test name
Test status
Simulation time 232340634 ps
CPU time 0.92 seconds
Started Jun 30 06:23:39 PM PDT 24
Finished Jun 30 06:23:41 PM PDT 24
Peak memory 206196 kb
Host smart-6d89c236-c4cc-45ac-aaee-93d01698c11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41583
36446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4158336446
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3307509838
Short name T196
Test name
Test status
Simulation time 8400879236 ps
CPU time 134.48 seconds
Started Jun 30 06:20:44 PM PDT 24
Finished Jun 30 06:22:59 PM PDT 24
Peak memory 206488 kb
Host smart-ea82e092-9575-4c4c-a62b-b6a879bbd385
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3307509838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3307509838
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3570766546
Short name T128
Test name
Test status
Simulation time 185913964 ps
CPU time 0.86 seconds
Started Jun 30 06:24:46 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 206196 kb
Host smart-dfba3ae8-5b46-4db2-866e-9a0b3a50ec15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35707
66546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3570766546
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3993988164
Short name T117
Test name
Test status
Simulation time 177768841 ps
CPU time 0.83 seconds
Started Jun 30 06:24:56 PM PDT 24
Finished Jun 30 06:24:58 PM PDT 24
Peak memory 206184 kb
Host smart-382142ee-14f4-42c4-993d-dbe1a5f5809c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39939
88164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3993988164
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1257407212
Short name T2635
Test name
Test status
Simulation time 136366819 ps
CPU time 3.23 seconds
Started Jun 30 05:42:43 PM PDT 24
Finished Jun 30 05:42:47 PM PDT 24
Peak memory 206084 kb
Host smart-92aea583-0188-4895-a7f1-3a62febf9ed3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1257407212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1257407212
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3309723303
Short name T2672
Test name
Test status
Simulation time 64781807 ps
CPU time 0.79 seconds
Started Jun 30 05:42:46 PM PDT 24
Finished Jun 30 05:42:48 PM PDT 24
Peak memory 205964 kb
Host smart-3c3f6006-ab58-4f28-83c8-9a791f2c30fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3309723303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3309723303
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1262324500
Short name T2640
Test name
Test status
Simulation time 79052865 ps
CPU time 1.86 seconds
Started Jun 30 05:42:41 PM PDT 24
Finished Jun 30 05:42:43 PM PDT 24
Peak memory 214244 kb
Host smart-cc7c1568-4303-4cf9-aab5-bb489b1d0c84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262324500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1262324500
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1621206056
Short name T2690
Test name
Test status
Simulation time 58596778 ps
CPU time 0.83 seconds
Started Jun 30 05:42:49 PM PDT 24
Finished Jun 30 05:42:51 PM PDT 24
Peak memory 205492 kb
Host smart-bdcbb64e-22ef-4932-b4c1-1e888f231c67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1621206056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1621206056
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.752876287
Short name T2700
Test name
Test status
Simulation time 45730949 ps
CPU time 0.65 seconds
Started Jun 30 05:42:42 PM PDT 24
Finished Jun 30 05:42:44 PM PDT 24
Peak memory 205828 kb
Host smart-0cd6a5a1-01a3-4694-946a-5db020897661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=752876287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.752876287
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2675487248
Short name T272
Test name
Test status
Simulation time 188333618 ps
CPU time 2.47 seconds
Started Jun 30 05:42:42 PM PDT 24
Finished Jun 30 05:42:46 PM PDT 24
Peak memory 215408 kb
Host smart-c9269b17-9be0-4e3a-85ff-43d29327eb6a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2675487248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2675487248
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2898838169
Short name T2658
Test name
Test status
Simulation time 583406390 ps
CPU time 4.43 seconds
Started Jun 30 05:42:41 PM PDT 24
Finished Jun 30 05:42:46 PM PDT 24
Peak memory 205984 kb
Host smart-f2cb14a5-814a-4ea7-876d-0013cd421701
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2898838169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2898838169
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3553288081
Short name T2655
Test name
Test status
Simulation time 125964420 ps
CPU time 1.22 seconds
Started Jun 30 05:42:43 PM PDT 24
Finished Jun 30 05:42:45 PM PDT 24
Peak memory 206008 kb
Host smart-ca3c4005-fa67-4246-af93-aadd1fadaf5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3553288081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3553288081
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.142896693
Short name T2716
Test name
Test status
Simulation time 167149544 ps
CPU time 1.89 seconds
Started Jun 30 05:42:43 PM PDT 24
Finished Jun 30 05:42:45 PM PDT 24
Peak memory 206148 kb
Host smart-94263d5f-254e-4d1f-89a4-fcf912b5f0fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=142896693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.142896693
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2040147922
Short name T324
Test name
Test status
Simulation time 872884626 ps
CPU time 5.5 seconds
Started Jun 30 05:42:43 PM PDT 24
Finished Jun 30 05:42:49 PM PDT 24
Peak memory 206004 kb
Host smart-ad638241-4ac3-436d-83fe-abeccafee49e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2040147922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2040147922
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3561456921
Short name T2676
Test name
Test status
Simulation time 99952187 ps
CPU time 2 seconds
Started Jun 30 05:42:48 PM PDT 24
Finished Jun 30 05:42:50 PM PDT 24
Peak memory 206016 kb
Host smart-8dc9534a-475a-4db4-8fa1-c1128ccb7bc6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3561456921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3561456921
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1967590086
Short name T2732
Test name
Test status
Simulation time 970719238 ps
CPU time 8.56 seconds
Started Jun 30 05:42:44 PM PDT 24
Finished Jun 30 05:42:53 PM PDT 24
Peak memory 206068 kb
Host smart-9098303b-f044-406a-85bb-de506598d593
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1967590086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1967590086
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2573911110
Short name T282
Test name
Test status
Simulation time 78458830 ps
CPU time 0.84 seconds
Started Jun 30 05:42:42 PM PDT 24
Finished Jun 30 05:42:43 PM PDT 24
Peak memory 205900 kb
Host smart-64a08e70-c9e5-45b8-9b19-0e1f29dfc946
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2573911110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2573911110
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.135020066
Short name T2724
Test name
Test status
Simulation time 181620160 ps
CPU time 2.31 seconds
Started Jun 30 05:42:50 PM PDT 24
Finished Jun 30 05:42:54 PM PDT 24
Peak memory 214212 kb
Host smart-18890eae-922d-4581-926e-545b9839fc7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135020066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.135020066
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2347278978
Short name T2679
Test name
Test status
Simulation time 148925643 ps
CPU time 1.58 seconds
Started Jun 30 05:42:47 PM PDT 24
Finished Jun 30 05:42:49 PM PDT 24
Peak memory 214252 kb
Host smart-78855125-8c76-4026-bf2c-23c932d6b0ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2347278978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2347278978
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1603568051
Short name T2648
Test name
Test status
Simulation time 763995133 ps
CPU time 5.4 seconds
Started Jun 30 05:42:43 PM PDT 24
Finished Jun 30 05:42:49 PM PDT 24
Peak memory 205992 kb
Host smart-dd47c7d3-fa81-4eaf-84d6-84f32f651473
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1603568051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1603568051
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.947896989
Short name T2645
Test name
Test status
Simulation time 272621813 ps
CPU time 1.71 seconds
Started Jun 30 05:42:50 PM PDT 24
Finished Jun 30 05:42:53 PM PDT 24
Peak memory 206044 kb
Host smart-f1e8b4ec-ec13-4eee-afff-aa7d27495bb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=947896989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.947896989
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1368496573
Short name T247
Test name
Test status
Simulation time 681111280 ps
CPU time 4.56 seconds
Started Jun 30 05:42:43 PM PDT 24
Finished Jun 30 05:42:48 PM PDT 24
Peak memory 206052 kb
Host smart-97c7cbba-b29e-4b89-8c09-8d20b09f1e28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1368496573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1368496573
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3346962651
Short name T2696
Test name
Test status
Simulation time 97714074 ps
CPU time 1.23 seconds
Started Jun 30 05:43:09 PM PDT 24
Finished Jun 30 05:43:11 PM PDT 24
Peak memory 214280 kb
Host smart-94432232-92a2-447a-8b22-5bdf62b3dd30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346962651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3346962651
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1094400006
Short name T2737
Test name
Test status
Simulation time 49829490 ps
CPU time 0.86 seconds
Started Jun 30 05:43:16 PM PDT 24
Finished Jun 30 05:43:18 PM PDT 24
Peak memory 205896 kb
Host smart-7b563ff5-fbcd-4439-a5b3-2979f20c3462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1094400006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1094400006
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.935785103
Short name T2708
Test name
Test status
Simulation time 39739328 ps
CPU time 0.68 seconds
Started Jun 30 05:43:08 PM PDT 24
Finished Jun 30 05:43:10 PM PDT 24
Peak memory 205828 kb
Host smart-0aac29cf-9c91-44e8-a2fb-9efb2faa9fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=935785103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.935785103
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3823840663
Short name T2733
Test name
Test status
Simulation time 92025292 ps
CPU time 1.03 seconds
Started Jun 30 05:43:11 PM PDT 24
Finished Jun 30 05:43:12 PM PDT 24
Peak memory 206000 kb
Host smart-8aba3856-3dfb-4057-b568-48153146c8e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3823840663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3823840663
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.539457069
Short name T258
Test name
Test status
Simulation time 266985272 ps
CPU time 2.85 seconds
Started Jun 30 05:43:15 PM PDT 24
Finished Jun 30 05:43:19 PM PDT 24
Peak memory 206120 kb
Host smart-38927b97-6b11-462f-b1af-9a9953d955dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=539457069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.539457069
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.526238649
Short name T256
Test name
Test status
Simulation time 152828147 ps
CPU time 1.77 seconds
Started Jun 30 05:43:15 PM PDT 24
Finished Jun 30 05:43:17 PM PDT 24
Peak memory 218008 kb
Host smart-16576fc9-0646-48ee-99f2-dded91191956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526238649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.526238649
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.112273447
Short name T2681
Test name
Test status
Simulation time 104595477 ps
CPU time 1.03 seconds
Started Jun 30 05:43:16 PM PDT 24
Finished Jun 30 05:43:18 PM PDT 24
Peak memory 206176 kb
Host smart-9a6b2e7e-cb62-4254-989f-81c32eac6bd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=112273447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.112273447
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1559106016
Short name T2730
Test name
Test status
Simulation time 39825140 ps
CPU time 0.68 seconds
Started Jun 30 05:43:14 PM PDT 24
Finished Jun 30 05:43:16 PM PDT 24
Peak memory 205876 kb
Host smart-aa505107-e148-41d1-9a4c-5d42a4d67ed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1559106016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1559106016
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2655453132
Short name T2688
Test name
Test status
Simulation time 310601668 ps
CPU time 1.96 seconds
Started Jun 30 05:43:16 PM PDT 24
Finished Jun 30 05:43:19 PM PDT 24
Peak memory 205980 kb
Host smart-d8949551-5226-476d-ba86-ccf89ac6d91b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2655453132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2655453132
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2590329662
Short name T251
Test name
Test status
Simulation time 141811806 ps
CPU time 1.71 seconds
Started Jun 30 05:43:08 PM PDT 24
Finished Jun 30 05:43:11 PM PDT 24
Peak memory 206128 kb
Host smart-4c69e004-15e2-4de9-a4a1-8ef658127b86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2590329662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2590329662
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1447078048
Short name T307
Test name
Test status
Simulation time 777386625 ps
CPU time 5.3 seconds
Started Jun 30 05:43:15 PM PDT 24
Finished Jun 30 05:43:21 PM PDT 24
Peak memory 205988 kb
Host smart-848451bc-5be5-4617-9097-ca482f94cf89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1447078048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1447078048
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4157902318
Short name T2712
Test name
Test status
Simulation time 178992807 ps
CPU time 2.24 seconds
Started Jun 30 05:43:16 PM PDT 24
Finished Jun 30 05:43:19 PM PDT 24
Peak memory 214292 kb
Host smart-b2476caa-0fea-4cb2-9008-af8b9507e07f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157902318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.4157902318
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1095735598
Short name T2653
Test name
Test status
Simulation time 60204870 ps
CPU time 0.93 seconds
Started Jun 30 05:43:15 PM PDT 24
Finished Jun 30 05:43:17 PM PDT 24
Peak memory 206088 kb
Host smart-970d3a23-9c3a-45ae-85ee-3ae310c5a77b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1095735598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1095735598
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.583351475
Short name T226
Test name
Test status
Simulation time 42208954 ps
CPU time 0.7 seconds
Started Jun 30 05:43:16 PM PDT 24
Finished Jun 30 05:43:18 PM PDT 24
Peak memory 206024 kb
Host smart-3da4e2ac-d452-4c0d-9e8a-13bb18513e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=583351475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.583351475
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3506942568
Short name T290
Test name
Test status
Simulation time 64975400 ps
CPU time 1.1 seconds
Started Jun 30 05:43:15 PM PDT 24
Finished Jun 30 05:43:17 PM PDT 24
Peak memory 206024 kb
Host smart-79c47cf6-e6ef-4a3a-9a1e-fd2bd847dee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3506942568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3506942568
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2237378990
Short name T2693
Test name
Test status
Simulation time 121865798 ps
CPU time 1.6 seconds
Started Jun 30 05:43:16 PM PDT 24
Finished Jun 30 05:43:19 PM PDT 24
Peak memory 214236 kb
Host smart-ea972c7e-7b27-48ef-92e0-a054179449db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2237378990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2237378990
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1403624741
Short name T2682
Test name
Test status
Simulation time 92928193 ps
CPU time 1.21 seconds
Started Jun 30 05:43:15 PM PDT 24
Finished Jun 30 05:43:17 PM PDT 24
Peak memory 214260 kb
Host smart-1fbad418-a45a-4172-9299-b4a05e55152b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403624741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1403624741
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2224285490
Short name T277
Test name
Test status
Simulation time 91926161 ps
CPU time 1.07 seconds
Started Jun 30 05:43:16 PM PDT 24
Finished Jun 30 05:43:18 PM PDT 24
Peak memory 206072 kb
Host smart-3fdc5fe9-34ee-4428-a135-003eeb7cbf80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2224285490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2224285490
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1328754776
Short name T2671
Test name
Test status
Simulation time 69987724 ps
CPU time 0.76 seconds
Started Jun 30 05:43:15 PM PDT 24
Finished Jun 30 05:43:16 PM PDT 24
Peak memory 205856 kb
Host smart-7fd3a798-a93c-472d-b73c-5cfb6ef4ff79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1328754776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1328754776
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.514415491
Short name T222
Test name
Test status
Simulation time 121372675 ps
CPU time 1.18 seconds
Started Jun 30 05:43:15 PM PDT 24
Finished Jun 30 05:43:18 PM PDT 24
Peak memory 206032 kb
Host smart-0c0cb272-5637-4b9b-bcf4-3bb504e010d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=514415491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.514415491
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.408137849
Short name T2665
Test name
Test status
Simulation time 947293623 ps
CPU time 4.62 seconds
Started Jun 30 05:43:16 PM PDT 24
Finished Jun 30 05:43:21 PM PDT 24
Peak memory 206024 kb
Host smart-8bbf3921-c69f-4cad-83c5-7ab1b90c8d07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=408137849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.408137849
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.117115590
Short name T219
Test name
Test status
Simulation time 112853665 ps
CPU time 1.27 seconds
Started Jun 30 05:43:23 PM PDT 24
Finished Jun 30 05:43:25 PM PDT 24
Peak memory 214264 kb
Host smart-bd1ef20c-63d1-47a3-b37b-5db69a2b9a12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117115590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.117115590
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1118239365
Short name T288
Test name
Test status
Simulation time 78430679 ps
CPU time 1.06 seconds
Started Jun 30 05:43:22 PM PDT 24
Finished Jun 30 05:43:24 PM PDT 24
Peak memory 206036 kb
Host smart-93159384-96e1-40b4-a31b-ddacda79cc83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1118239365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1118239365
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1758878734
Short name T319
Test name
Test status
Simulation time 92466818 ps
CPU time 0.72 seconds
Started Jun 30 05:43:23 PM PDT 24
Finished Jun 30 05:43:24 PM PDT 24
Peak memory 205832 kb
Host smart-502350a2-2f6c-4af5-a89f-fbdfa80f4fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1758878734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1758878734
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1149955683
Short name T2715
Test name
Test status
Simulation time 98798930 ps
CPU time 1.41 seconds
Started Jun 30 05:43:22 PM PDT 24
Finished Jun 30 05:43:24 PM PDT 24
Peak memory 206064 kb
Host smart-62a4c69a-891a-4d66-9f06-3df293348945
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1149955683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1149955683
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2415101861
Short name T2719
Test name
Test status
Simulation time 154639626 ps
CPU time 1.92 seconds
Started Jun 30 05:43:15 PM PDT 24
Finished Jun 30 05:43:18 PM PDT 24
Peak memory 206104 kb
Host smart-bbc998ad-bbf7-4d97-a252-bb24ff30b96b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2415101861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2415101861
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.695323806
Short name T325
Test name
Test status
Simulation time 2311430374 ps
CPU time 7.27 seconds
Started Jun 30 05:43:22 PM PDT 24
Finished Jun 30 05:43:30 PM PDT 24
Peak memory 206192 kb
Host smart-a49892e8-5977-4e52-b15b-3bcb10bd98e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=695323806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.695323806
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.393294423
Short name T2656
Test name
Test status
Simulation time 167253818 ps
CPU time 1.86 seconds
Started Jun 30 05:43:22 PM PDT 24
Finished Jun 30 05:43:24 PM PDT 24
Peak memory 214264 kb
Host smart-50fa8186-f953-4e43-9eec-5652d153bc14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393294423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.393294423
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3400314725
Short name T301
Test name
Test status
Simulation time 57206598 ps
CPU time 0.8 seconds
Started Jun 30 05:43:22 PM PDT 24
Finished Jun 30 05:43:24 PM PDT 24
Peak memory 205900 kb
Host smart-b3573213-6273-4385-898d-af2c1cde9b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3400314725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3400314725
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2416904907
Short name T2714
Test name
Test status
Simulation time 139574919 ps
CPU time 1.52 seconds
Started Jun 30 05:43:22 PM PDT 24
Finished Jun 30 05:43:23 PM PDT 24
Peak memory 206044 kb
Host smart-34a56fbd-3eb0-415e-a4c6-944926decf22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2416904907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2416904907
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4287924419
Short name T2686
Test name
Test status
Simulation time 252102658 ps
CPU time 3.13 seconds
Started Jun 30 05:43:22 PM PDT 24
Finished Jun 30 05:43:26 PM PDT 24
Peak memory 214324 kb
Host smart-d6833d39-8cd5-46ff-9c4f-4875813982be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4287924419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.4287924419
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3275112652
Short name T2691
Test name
Test status
Simulation time 472277677 ps
CPU time 2.91 seconds
Started Jun 30 05:43:23 PM PDT 24
Finished Jun 30 05:43:27 PM PDT 24
Peak memory 206028 kb
Host smart-7eb411ba-b892-4854-8633-9a92b2ad6fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3275112652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3275112652
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1063721511
Short name T241
Test name
Test status
Simulation time 102378356 ps
CPU time 2.42 seconds
Started Jun 30 05:43:22 PM PDT 24
Finished Jun 30 05:43:25 PM PDT 24
Peak memory 214276 kb
Host smart-d4f7eba9-4403-414a-b8c5-ba820df42cde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063721511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1063721511
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2443732266
Short name T2664
Test name
Test status
Simulation time 70510144 ps
CPU time 1.03 seconds
Started Jun 30 05:43:21 PM PDT 24
Finished Jun 30 05:43:22 PM PDT 24
Peak memory 206008 kb
Host smart-eed3e166-9f8a-481c-8b8c-2b0cdf235aaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2443732266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2443732266
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.246997057
Short name T308
Test name
Test status
Simulation time 43597215 ps
CPU time 0.67 seconds
Started Jun 30 05:43:21 PM PDT 24
Finished Jun 30 05:43:22 PM PDT 24
Peak memory 205812 kb
Host smart-92410f2f-d0ed-458e-b178-cfe648ac19fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=246997057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.246997057
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.605509515
Short name T2721
Test name
Test status
Simulation time 171839699 ps
CPU time 1.58 seconds
Started Jun 30 05:43:24 PM PDT 24
Finished Jun 30 05:43:26 PM PDT 24
Peak memory 205984 kb
Host smart-6a742ba0-f17f-47eb-addf-5e8c0e12a155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=605509515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.605509515
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1899046280
Short name T2704
Test name
Test status
Simulation time 149242649 ps
CPU time 1.79 seconds
Started Jun 30 05:43:22 PM PDT 24
Finished Jun 30 05:43:25 PM PDT 24
Peak memory 221952 kb
Host smart-5dc101e7-745e-48e8-8cab-18fab4c3e667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1899046280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1899046280
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3160028570
Short name T299
Test name
Test status
Simulation time 501900672 ps
CPU time 2.96 seconds
Started Jun 30 05:43:23 PM PDT 24
Finished Jun 30 05:43:26 PM PDT 24
Peak memory 206268 kb
Host smart-717f5102-cceb-4c35-b4e4-e532ccd6c9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3160028570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3160028570
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1096700545
Short name T2652
Test name
Test status
Simulation time 178992273 ps
CPU time 2.01 seconds
Started Jun 30 05:43:27 PM PDT 24
Finished Jun 30 05:43:29 PM PDT 24
Peak memory 214492 kb
Host smart-8b63ebee-1469-4893-9253-9e140e126910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096700545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1096700545
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.326109723
Short name T283
Test name
Test status
Simulation time 72063273 ps
CPU time 0.97 seconds
Started Jun 30 05:43:32 PM PDT 24
Finished Jun 30 05:43:34 PM PDT 24
Peak memory 206064 kb
Host smart-d72e1c01-03e9-4d4e-badb-37d8580968bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=326109723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.326109723
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1649053040
Short name T2639
Test name
Test status
Simulation time 92338963 ps
CPU time 1.56 seconds
Started Jun 30 05:43:30 PM PDT 24
Finished Jun 30 05:43:33 PM PDT 24
Peak memory 206028 kb
Host smart-1cc6b0b3-1246-41d9-a63f-069be0213ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1649053040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1649053040
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3631297334
Short name T2726
Test name
Test status
Simulation time 265864104 ps
CPU time 2.62 seconds
Started Jun 30 05:43:22 PM PDT 24
Finished Jun 30 05:43:26 PM PDT 24
Peak memory 221996 kb
Host smart-68da7038-aedd-4d25-adfb-af737f7cfcbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3631297334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3631297334
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1430500854
Short name T2734
Test name
Test status
Simulation time 354614678 ps
CPU time 2.73 seconds
Started Jun 30 05:43:30 PM PDT 24
Finished Jun 30 05:43:34 PM PDT 24
Peak memory 206068 kb
Host smart-de6916aa-8f7f-48a5-aa67-d0841ec0409c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1430500854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1430500854
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1026546549
Short name T2687
Test name
Test status
Simulation time 114547410 ps
CPU time 2.37 seconds
Started Jun 30 05:43:29 PM PDT 24
Finished Jun 30 05:43:32 PM PDT 24
Peak memory 214320 kb
Host smart-4c27ed72-8322-4703-a204-89cef7d61144
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026546549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1026546549
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3965940544
Short name T285
Test name
Test status
Simulation time 74445818 ps
CPU time 0.97 seconds
Started Jun 30 05:43:32 PM PDT 24
Finished Jun 30 05:43:33 PM PDT 24
Peak memory 206024 kb
Host smart-0c3d8165-4c47-4ec8-bcb3-a506898d1e90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3965940544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3965940544
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1650467411
Short name T289
Test name
Test status
Simulation time 89269620 ps
CPU time 1.09 seconds
Started Jun 30 05:43:31 PM PDT 24
Finished Jun 30 05:43:33 PM PDT 24
Peak memory 206020 kb
Host smart-1c644764-3e20-41ad-9b9f-1433163634ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1650467411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1650467411
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3951894364
Short name T254
Test name
Test status
Simulation time 130487533 ps
CPU time 1.59 seconds
Started Jun 30 05:43:32 PM PDT 24
Finished Jun 30 05:43:34 PM PDT 24
Peak memory 221772 kb
Host smart-8a0e1ea0-0081-435b-9e43-870db9cd4112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3951894364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3951894364
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2017929836
Short name T2649
Test name
Test status
Simulation time 787030927 ps
CPU time 4.51 seconds
Started Jun 30 05:43:33 PM PDT 24
Finished Jun 30 05:43:38 PM PDT 24
Peak memory 206004 kb
Host smart-b65ec7ce-5ca2-4ff6-b25f-7bde06f2d630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2017929836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2017929836
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2622039346
Short name T264
Test name
Test status
Simulation time 132252829 ps
CPU time 2.62 seconds
Started Jun 30 05:43:28 PM PDT 24
Finished Jun 30 05:43:32 PM PDT 24
Peak memory 214324 kb
Host smart-d9c4f9a1-c8f5-4223-950b-eac40b6b1fbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622039346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2622039346
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.378017515
Short name T2642
Test name
Test status
Simulation time 78867814 ps
CPU time 0.83 seconds
Started Jun 30 05:43:28 PM PDT 24
Finished Jun 30 05:43:29 PM PDT 24
Peak memory 205904 kb
Host smart-3605b977-6c59-4b91-a955-93955623d583
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=378017515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.378017515
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3798511668
Short name T2662
Test name
Test status
Simulation time 45521272 ps
CPU time 0.73 seconds
Started Jun 30 05:43:28 PM PDT 24
Finished Jun 30 05:43:30 PM PDT 24
Peak memory 205840 kb
Host smart-ba79772a-15ca-42f1-b3b7-a2fb2a27e08f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3798511668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3798511668
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.850790950
Short name T300
Test name
Test status
Simulation time 393963415 ps
CPU time 1.7 seconds
Started Jun 30 05:43:30 PM PDT 24
Finished Jun 30 05:43:33 PM PDT 24
Peak memory 206012 kb
Host smart-c7f61b82-29ae-4e17-8854-613eaff7dbcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=850790950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.850790950
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3461734728
Short name T2728
Test name
Test status
Simulation time 267629156 ps
CPU time 3.31 seconds
Started Jun 30 05:43:27 PM PDT 24
Finished Jun 30 05:43:31 PM PDT 24
Peak memory 214328 kb
Host smart-acb67669-fde7-4390-b4c4-0a12d9aa6353
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3461734728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3461734728
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4216800106
Short name T246
Test name
Test status
Simulation time 400283735 ps
CPU time 2.75 seconds
Started Jun 30 05:43:34 PM PDT 24
Finished Jun 30 05:43:38 PM PDT 24
Peak memory 206000 kb
Host smart-1c9f2aa4-88b4-4399-b980-fb8bcbe0192f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4216800106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.4216800106
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3460286765
Short name T2661
Test name
Test status
Simulation time 304479208 ps
CPU time 3.54 seconds
Started Jun 30 05:42:51 PM PDT 24
Finished Jun 30 05:42:55 PM PDT 24
Peak memory 206032 kb
Host smart-d5cbe9ef-3f81-49f6-8959-7600256bb254
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3460286765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3460286765
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2859437389
Short name T275
Test name
Test status
Simulation time 1051444197 ps
CPU time 8 seconds
Started Jun 30 05:42:52 PM PDT 24
Finished Jun 30 05:43:00 PM PDT 24
Peak memory 206016 kb
Host smart-4e348295-879a-4f8e-9be9-f104c09f125f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2859437389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2859437389
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2463541923
Short name T278
Test name
Test status
Simulation time 76318532 ps
CPU time 0.79 seconds
Started Jun 30 05:42:50 PM PDT 24
Finished Jun 30 05:42:51 PM PDT 24
Peak memory 205924 kb
Host smart-1340d98f-0cc5-4e7f-bec8-3087bfe4a4cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2463541923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2463541923
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.143045239
Short name T2668
Test name
Test status
Simulation time 168558713 ps
CPU time 1.72 seconds
Started Jun 30 05:42:50 PM PDT 24
Finished Jun 30 05:42:53 PM PDT 24
Peak memory 214240 kb
Host smart-3a379f31-4378-4fed-9d1f-f72d7c7294ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143045239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.143045239
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.736331891
Short name T287
Test name
Test status
Simulation time 53735059 ps
CPU time 0.95 seconds
Started Jun 30 05:42:49 PM PDT 24
Finished Jun 30 05:42:51 PM PDT 24
Peak memory 206028 kb
Host smart-90e52054-7247-4faf-acf2-9b6bb0b89c0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=736331891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.736331891
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1160877822
Short name T281
Test name
Test status
Simulation time 95736285 ps
CPU time 2.2 seconds
Started Jun 30 05:42:50 PM PDT 24
Finished Jun 30 05:42:54 PM PDT 24
Peak memory 215296 kb
Host smart-5f7c0a9b-8db4-4368-8f93-302c294793bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1160877822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1160877822
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1618712107
Short name T2707
Test name
Test status
Simulation time 259843321 ps
CPU time 2.7 seconds
Started Jun 30 05:42:50 PM PDT 24
Finished Jun 30 05:42:53 PM PDT 24
Peak memory 206184 kb
Host smart-20a32cfd-d302-42ed-9e36-670a35a3de70
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1618712107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1618712107
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1288650236
Short name T2637
Test name
Test status
Simulation time 102567841 ps
CPU time 1.45 seconds
Started Jun 30 05:42:50 PM PDT 24
Finished Jun 30 05:42:53 PM PDT 24
Peak memory 206080 kb
Host smart-acd29d08-3bea-4287-981e-31763c524477
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1288650236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1288650236
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2052296144
Short name T252
Test name
Test status
Simulation time 100698713 ps
CPU time 2.85 seconds
Started Jun 30 05:42:51 PM PDT 24
Finished Jun 30 05:42:55 PM PDT 24
Peak memory 222268 kb
Host smart-73271fa9-e7f1-4154-827e-abc03fc86e93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2052296144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2052296144
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.295514444
Short name T2729
Test name
Test status
Simulation time 46819983 ps
CPU time 0.71 seconds
Started Jun 30 05:43:29 PM PDT 24
Finished Jun 30 05:43:31 PM PDT 24
Peak memory 205832 kb
Host smart-91e48986-5b56-45b3-90f4-9c9d85fea3ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=295514444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.295514444
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.319699406
Short name T2720
Test name
Test status
Simulation time 35779672 ps
CPU time 0.66 seconds
Started Jun 30 05:43:29 PM PDT 24
Finished Jun 30 05:43:30 PM PDT 24
Peak memory 205824 kb
Host smart-9468ead6-584d-4fbb-a642-72c81217c928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=319699406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.319699406
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3108625840
Short name T2710
Test name
Test status
Simulation time 58737127 ps
CPU time 0.7 seconds
Started Jun 30 05:43:29 PM PDT 24
Finished Jun 30 05:43:31 PM PDT 24
Peak memory 205852 kb
Host smart-973ac033-a605-436a-b26e-25f3138ce9d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3108625840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3108625840
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1745082490
Short name T309
Test name
Test status
Simulation time 49739184 ps
CPU time 0.73 seconds
Started Jun 30 05:43:31 PM PDT 24
Finished Jun 30 05:43:32 PM PDT 24
Peak memory 205852 kb
Host smart-e936292a-63c7-4b5b-b7d4-2cc32ceaaaa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1745082490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1745082490
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2753102423
Short name T318
Test name
Test status
Simulation time 38027014 ps
CPU time 0.67 seconds
Started Jun 30 05:43:29 PM PDT 24
Finished Jun 30 05:43:31 PM PDT 24
Peak memory 205844 kb
Host smart-85f9c1ef-c7e6-4fef-8dee-089a77a3363e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2753102423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2753102423
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3153063807
Short name T303
Test name
Test status
Simulation time 62988518 ps
CPU time 0.71 seconds
Started Jun 30 05:43:34 PM PDT 24
Finished Jun 30 05:43:36 PM PDT 24
Peak memory 205848 kb
Host smart-c6fa8bc9-be92-4e3b-924e-3b79463d2f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3153063807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3153063807
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3108887495
Short name T2717
Test name
Test status
Simulation time 37995189 ps
CPU time 0.67 seconds
Started Jun 30 05:43:28 PM PDT 24
Finished Jun 30 05:43:29 PM PDT 24
Peak memory 205804 kb
Host smart-b91fd89c-ae16-4905-b002-5e77299b97be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3108887495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3108887495
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1820591988
Short name T2731
Test name
Test status
Simulation time 93198779 ps
CPU time 0.69 seconds
Started Jun 30 05:43:29 PM PDT 24
Finished Jun 30 05:43:31 PM PDT 24
Peak memory 205844 kb
Host smart-c863be81-ca03-4416-9b9d-2384b87dd9d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1820591988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1820591988
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3472225326
Short name T227
Test name
Test status
Simulation time 53607954 ps
CPU time 0.72 seconds
Started Jun 30 05:43:28 PM PDT 24
Finished Jun 30 05:43:29 PM PDT 24
Peak memory 205828 kb
Host smart-2a75290c-913a-48d6-b9ab-d816fe58aafd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3472225326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3472225326
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.537085745
Short name T317
Test name
Test status
Simulation time 44482020 ps
CPU time 0.67 seconds
Started Jun 30 05:43:33 PM PDT 24
Finished Jun 30 05:43:34 PM PDT 24
Peak memory 205828 kb
Host smart-e4d29d88-7ce7-4764-b1ea-985de93286fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=537085745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.537085745
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.111945644
Short name T2685
Test name
Test status
Simulation time 300669122 ps
CPU time 3.54 seconds
Started Jun 30 05:43:01 PM PDT 24
Finished Jun 30 05:43:05 PM PDT 24
Peak memory 206108 kb
Host smart-f04aea1d-99bf-4457-aa94-161ac1090ab0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=111945644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.111945644
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1607067446
Short name T280
Test name
Test status
Simulation time 512825530 ps
CPU time 4.07 seconds
Started Jun 30 05:42:54 PM PDT 24
Finished Jun 30 05:42:59 PM PDT 24
Peak memory 206012 kb
Host smart-9db3be1e-7167-4403-bd45-909a19bc41db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1607067446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1607067446
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3921528490
Short name T2725
Test name
Test status
Simulation time 264350106 ps
CPU time 1.05 seconds
Started Jun 30 05:42:55 PM PDT 24
Finished Jun 30 05:42:57 PM PDT 24
Peak memory 205900 kb
Host smart-94cc371c-7493-4753-81da-dfba8368edcd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3921528490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3921528490
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.527457296
Short name T2701
Test name
Test status
Simulation time 186937198 ps
CPU time 1.39 seconds
Started Jun 30 05:42:54 PM PDT 24
Finished Jun 30 05:42:56 PM PDT 24
Peak memory 214252 kb
Host smart-48be327d-277e-495d-b57e-cc1ef807221b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527457296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.527457296
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.160444398
Short name T279
Test name
Test status
Simulation time 89272712 ps
CPU time 0.81 seconds
Started Jun 30 05:42:54 PM PDT 24
Finished Jun 30 05:42:55 PM PDT 24
Peak memory 205936 kb
Host smart-0c5c931e-c502-4d62-abc2-4327658c9a18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=160444398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.160444398
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2474074943
Short name T316
Test name
Test status
Simulation time 40440858 ps
CPU time 0.64 seconds
Started Jun 30 05:42:49 PM PDT 24
Finished Jun 30 05:42:51 PM PDT 24
Peak memory 205800 kb
Host smart-f1b4cc82-1b54-4e73-9ffb-24b7d6ddd0a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2474074943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2474074943
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3640374419
Short name T2722
Test name
Test status
Simulation time 118751263 ps
CPU time 1.58 seconds
Started Jun 30 05:42:55 PM PDT 24
Finished Jun 30 05:42:57 PM PDT 24
Peak memory 214280 kb
Host smart-43b56b45-0c89-4360-849e-400c2b22c026
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3640374419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3640374419
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.968148989
Short name T2636
Test name
Test status
Simulation time 412127804 ps
CPU time 2.73 seconds
Started Jun 30 05:42:56 PM PDT 24
Finished Jun 30 05:42:59 PM PDT 24
Peak memory 205992 kb
Host smart-7f4e6951-ed49-4c6d-a9fe-e3fde5c209cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=968148989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.968148989
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2892136623
Short name T2667
Test name
Test status
Simulation time 104230548 ps
CPU time 1.18 seconds
Started Jun 30 05:42:56 PM PDT 24
Finished Jun 30 05:42:58 PM PDT 24
Peak memory 206024 kb
Host smart-54696bd6-3ffd-42e8-8b8d-a408fabc4719
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2892136623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2892136623
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.221708353
Short name T218
Test name
Test status
Simulation time 180918294 ps
CPU time 2.03 seconds
Started Jun 30 05:42:51 PM PDT 24
Finished Jun 30 05:42:54 PM PDT 24
Peak memory 206152 kb
Host smart-2027793e-98c4-4f68-b065-290374470fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=221708353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.221708353
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1082259078
Short name T2735
Test name
Test status
Simulation time 2021644724 ps
CPU time 6.94 seconds
Started Jun 30 05:42:50 PM PDT 24
Finished Jun 30 05:42:58 PM PDT 24
Peak memory 205992 kb
Host smart-aaeb11cf-f354-4298-a563-a496c6b01bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1082259078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1082259078
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.531991298
Short name T310
Test name
Test status
Simulation time 41044069 ps
CPU time 0.65 seconds
Started Jun 30 05:43:30 PM PDT 24
Finished Jun 30 05:43:32 PM PDT 24
Peak memory 205824 kb
Host smart-6921a5a3-52c3-47dc-bdfe-88b1baf35ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=531991298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.531991298
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3278409987
Short name T2736
Test name
Test status
Simulation time 120066321 ps
CPU time 0.71 seconds
Started Jun 30 05:43:30 PM PDT 24
Finished Jun 30 05:43:31 PM PDT 24
Peak memory 205832 kb
Host smart-6b328686-f020-484d-a72d-26b71c3fad60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3278409987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3278409987
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.289152930
Short name T304
Test name
Test status
Simulation time 36943444 ps
CPU time 0.67 seconds
Started Jun 30 05:43:29 PM PDT 24
Finished Jun 30 05:43:30 PM PDT 24
Peak memory 205836 kb
Host smart-474bafc9-4404-4091-a55a-b8aa852f1be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=289152930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.289152930
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1205273218
Short name T320
Test name
Test status
Simulation time 74058276 ps
CPU time 0.7 seconds
Started Jun 30 05:43:28 PM PDT 24
Finished Jun 30 05:43:30 PM PDT 24
Peak memory 205876 kb
Host smart-1aa5df89-2453-48f2-8037-449037124623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1205273218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1205273218
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3877961576
Short name T315
Test name
Test status
Simulation time 34395136 ps
CPU time 0.65 seconds
Started Jun 30 05:43:30 PM PDT 24
Finished Jun 30 05:43:32 PM PDT 24
Peak memory 205836 kb
Host smart-7057e2d1-4366-4e63-a54c-e620f8e90c45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3877961576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3877961576
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.594828090
Short name T2723
Test name
Test status
Simulation time 103766427 ps
CPU time 0.69 seconds
Started Jun 30 05:43:33 PM PDT 24
Finished Jun 30 05:43:34 PM PDT 24
Peak memory 205860 kb
Host smart-f3c69065-2503-4401-8609-78b254c54c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=594828090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.594828090
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.794736296
Short name T2670
Test name
Test status
Simulation time 46091590 ps
CPU time 0.72 seconds
Started Jun 30 05:43:33 PM PDT 24
Finished Jun 30 05:43:34 PM PDT 24
Peak memory 205824 kb
Host smart-ed5e1556-51bf-401a-ba91-818b478fc94c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=794736296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.794736296
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3703710617
Short name T2654
Test name
Test status
Simulation time 56743005 ps
CPU time 0.65 seconds
Started Jun 30 05:43:33 PM PDT 24
Finished Jun 30 05:43:34 PM PDT 24
Peak memory 205860 kb
Host smart-cc33b544-cb2c-4d3d-9097-329f8afe217a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3703710617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3703710617
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3720375
Short name T2669
Test name
Test status
Simulation time 36778603 ps
CPU time 0.68 seconds
Started Jun 30 05:43:31 PM PDT 24
Finished Jun 30 05:43:32 PM PDT 24
Peak memory 205852 kb
Host smart-88554f61-431f-4b5a-bc6c-88362859e9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3720375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3720375
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4058093043
Short name T2638
Test name
Test status
Simulation time 305061260 ps
CPU time 3.52 seconds
Started Jun 30 05:42:57 PM PDT 24
Finished Jun 30 05:43:00 PM PDT 24
Peak memory 206016 kb
Host smart-3b042a90-69a9-46bf-84e3-beaacd35bd13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4058093043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.4058093043
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.897071411
Short name T2644
Test name
Test status
Simulation time 1221439938 ps
CPU time 8.78 seconds
Started Jun 30 05:42:57 PM PDT 24
Finished Jun 30 05:43:06 PM PDT 24
Peak memory 206012 kb
Host smart-15c5c1a7-4fb6-446c-acc1-c1946c853ee3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=897071411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.897071411
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2350983115
Short name T2703
Test name
Test status
Simulation time 61190745 ps
CPU time 0.8 seconds
Started Jun 30 05:42:56 PM PDT 24
Finished Jun 30 05:42:57 PM PDT 24
Peak memory 205944 kb
Host smart-7cdde452-0084-45b0-acf7-8cabe2530824
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2350983115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2350983115
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4291389092
Short name T2659
Test name
Test status
Simulation time 177301382 ps
CPU time 1.96 seconds
Started Jun 30 05:43:04 PM PDT 24
Finished Jun 30 05:43:06 PM PDT 24
Peak memory 214256 kb
Host smart-44292b7c-d378-4a3d-98f3-2d279f2a79a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291389092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.4291389092
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.421091252
Short name T286
Test name
Test status
Simulation time 66079437 ps
CPU time 0.88 seconds
Started Jun 30 05:42:55 PM PDT 24
Finished Jun 30 05:42:56 PM PDT 24
Peak memory 205880 kb
Host smart-a124de94-e95e-4bb8-9c1c-bb9080a3f258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=421091252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.421091252
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.322532407
Short name T314
Test name
Test status
Simulation time 35194829 ps
CPU time 0.63 seconds
Started Jun 30 05:43:01 PM PDT 24
Finished Jun 30 05:43:02 PM PDT 24
Peak memory 205848 kb
Host smart-494d439f-840a-4af7-bbc4-70ea51b8c95a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=322532407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.322532407
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2670459361
Short name T274
Test name
Test status
Simulation time 116649163 ps
CPU time 2.27 seconds
Started Jun 30 05:42:56 PM PDT 24
Finished Jun 30 05:42:59 PM PDT 24
Peak memory 222516 kb
Host smart-188b40c6-7497-4f11-b4dc-71d869e10358
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2670459361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2670459361
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2395410115
Short name T2695
Test name
Test status
Simulation time 259906425 ps
CPU time 2.53 seconds
Started Jun 30 05:42:57 PM PDT 24
Finished Jun 30 05:43:00 PM PDT 24
Peak memory 205980 kb
Host smart-f6dcca9d-f10a-4381-a82f-fe9171b42648
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2395410115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2395410115
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.358128737
Short name T2674
Test name
Test status
Simulation time 173780896 ps
CPU time 1.56 seconds
Started Jun 30 05:42:56 PM PDT 24
Finished Jun 30 05:42:58 PM PDT 24
Peak memory 206020 kb
Host smart-2d7f3a21-7faf-44ec-8698-2db321f7fbb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=358128737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.358128737
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2519461625
Short name T2702
Test name
Test status
Simulation time 231124316 ps
CPU time 2.9 seconds
Started Jun 30 05:42:55 PM PDT 24
Finished Jun 30 05:42:59 PM PDT 24
Peak memory 221804 kb
Host smart-184e97df-a53b-41b9-9e64-384e8b842c78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2519461625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2519461625
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2314065201
Short name T305
Test name
Test status
Simulation time 1355358179 ps
CPU time 4.77 seconds
Started Jun 30 05:42:55 PM PDT 24
Finished Jun 30 05:43:01 PM PDT 24
Peak memory 205984 kb
Host smart-96c73140-d32a-42db-ac3e-18c45c8e1edc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2314065201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2314065201
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.426509526
Short name T2697
Test name
Test status
Simulation time 35872933 ps
CPU time 0.66 seconds
Started Jun 30 05:43:33 PM PDT 24
Finished Jun 30 05:43:34 PM PDT 24
Peak memory 205820 kb
Host smart-63444157-9738-4f4c-b96f-66fe753b9dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=426509526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.426509526
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3481434418
Short name T2711
Test name
Test status
Simulation time 102524344 ps
CPU time 0.72 seconds
Started Jun 30 05:43:32 PM PDT 24
Finished Jun 30 05:43:34 PM PDT 24
Peak memory 205832 kb
Host smart-7ffa434a-8ad3-4093-8302-bcfc5f2baadb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3481434418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3481434418
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4230903602
Short name T2678
Test name
Test status
Simulation time 38063075 ps
CPU time 0.65 seconds
Started Jun 30 05:43:30 PM PDT 24
Finished Jun 30 05:43:32 PM PDT 24
Peak memory 205856 kb
Host smart-3ca04173-53e8-4b7f-ac80-87a3df4a9c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4230903602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4230903602
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2007961104
Short name T2646
Test name
Test status
Simulation time 50949152 ps
CPU time 0.73 seconds
Started Jun 30 05:43:29 PM PDT 24
Finished Jun 30 05:43:31 PM PDT 24
Peak memory 205848 kb
Host smart-c079f111-ed2f-4eb9-b2ff-18f59416cc48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2007961104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2007961104
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4201935312
Short name T2727
Test name
Test status
Simulation time 44447722 ps
CPU time 0.68 seconds
Started Jun 30 05:43:29 PM PDT 24
Finished Jun 30 05:43:30 PM PDT 24
Peak memory 205840 kb
Host smart-36d01f86-6491-4721-9b90-48801b7e5081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4201935312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.4201935312
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.47941515
Short name T2680
Test name
Test status
Simulation time 47202749 ps
CPU time 0.71 seconds
Started Jun 30 05:43:29 PM PDT 24
Finished Jun 30 05:43:31 PM PDT 24
Peak memory 205856 kb
Host smart-36aa947c-61ef-4bb9-805f-91737ba6f11e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=47941515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.47941515
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4162047568
Short name T2694
Test name
Test status
Simulation time 49291430 ps
CPU time 0.66 seconds
Started Jun 30 05:43:33 PM PDT 24
Finished Jun 30 05:43:35 PM PDT 24
Peak memory 205876 kb
Host smart-616c3eaa-4056-4bc0-956d-ef602aac253d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4162047568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.4162047568
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.218638934
Short name T2651
Test name
Test status
Simulation time 64875152 ps
CPU time 0.72 seconds
Started Jun 30 05:43:35 PM PDT 24
Finished Jun 30 05:43:36 PM PDT 24
Peak memory 205812 kb
Host smart-fe70697c-7250-430c-a772-bff531f85c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=218638934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.218638934
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1684966788
Short name T2684
Test name
Test status
Simulation time 54387544 ps
CPU time 0.68 seconds
Started Jun 30 05:43:34 PM PDT 24
Finished Jun 30 05:43:35 PM PDT 24
Peak memory 205848 kb
Host smart-644d2657-462d-48c9-8a53-b74760395ae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1684966788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1684966788
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1963028802
Short name T2641
Test name
Test status
Simulation time 65355607 ps
CPU time 0.68 seconds
Started Jun 30 05:43:35 PM PDT 24
Finished Jun 30 05:43:36 PM PDT 24
Peak memory 205852 kb
Host smart-4790e62e-3978-417f-91c7-6c0fdeb7cb59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1963028802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1963028802
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1443309614
Short name T2660
Test name
Test status
Simulation time 159422161 ps
CPU time 1.24 seconds
Started Jun 30 05:43:02 PM PDT 24
Finished Jun 30 05:43:04 PM PDT 24
Peak memory 214312 kb
Host smart-e8876689-9afd-4f7b-988a-f5ecc5066130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443309614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1443309614
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1471087012
Short name T2683
Test name
Test status
Simulation time 41042659 ps
CPU time 0.95 seconds
Started Jun 30 05:43:04 PM PDT 24
Finished Jun 30 05:43:06 PM PDT 24
Peak memory 205988 kb
Host smart-fc4c31d3-9da0-468e-a9d2-bd176dabc788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1471087012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1471087012
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.298753202
Short name T322
Test name
Test status
Simulation time 68913681 ps
CPU time 0.74 seconds
Started Jun 30 05:43:04 PM PDT 24
Finished Jun 30 05:43:05 PM PDT 24
Peak memory 205848 kb
Host smart-34429a97-2d7f-42d5-876b-ae6570bcdb2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=298753202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.298753202
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4204723409
Short name T296
Test name
Test status
Simulation time 159585007 ps
CPU time 1.21 seconds
Started Jun 30 05:43:04 PM PDT 24
Finished Jun 30 05:43:06 PM PDT 24
Peak memory 206012 kb
Host smart-ce67ff4f-fa77-434d-8183-7f6c7232efb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4204723409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.4204723409
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.845631140
Short name T2705
Test name
Test status
Simulation time 223874927 ps
CPU time 2.21 seconds
Started Jun 30 05:43:06 PM PDT 24
Finished Jun 30 05:43:08 PM PDT 24
Peak memory 214320 kb
Host smart-227f27b7-6f98-4d22-9b6d-dccfc45b1bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=845631140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.845631140
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.577747338
Short name T323
Test name
Test status
Simulation time 812353426 ps
CPU time 4.75 seconds
Started Jun 30 05:43:04 PM PDT 24
Finished Jun 30 05:43:10 PM PDT 24
Peak memory 206036 kb
Host smart-101a44ef-4a8c-41c1-846f-2d6f72a6b3dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=577747338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.577747338
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1222439718
Short name T2677
Test name
Test status
Simulation time 245416154 ps
CPU time 2.67 seconds
Started Jun 30 05:43:04 PM PDT 24
Finished Jun 30 05:43:07 PM PDT 24
Peak memory 214260 kb
Host smart-7f3bc8de-f47d-4a16-a746-4a78a5bb5115
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222439718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1222439718
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.361284991
Short name T284
Test name
Test status
Simulation time 75934011 ps
CPU time 1.07 seconds
Started Jun 30 05:43:02 PM PDT 24
Finished Jun 30 05:43:03 PM PDT 24
Peak memory 205988 kb
Host smart-e5e5c88c-c463-4452-ac5d-64a95e2adc5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=361284991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.361284991
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.951454817
Short name T321
Test name
Test status
Simulation time 49817974 ps
CPU time 0.65 seconds
Started Jun 30 05:43:05 PM PDT 24
Finished Jun 30 05:43:06 PM PDT 24
Peak memory 205832 kb
Host smart-ec5d6f52-eae2-4b00-985f-e27f8448dd53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=951454817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.951454817
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.42490263
Short name T220
Test name
Test status
Simulation time 303915433 ps
CPU time 1.97 seconds
Started Jun 30 05:43:04 PM PDT 24
Finished Jun 30 05:43:07 PM PDT 24
Peak memory 206000 kb
Host smart-2b4a7240-ad48-4df7-81de-ae406591d4c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=42490263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.42490263
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.69530693
Short name T2650
Test name
Test status
Simulation time 123004869 ps
CPU time 1.65 seconds
Started Jun 30 05:43:03 PM PDT 24
Finished Jun 30 05:43:05 PM PDT 24
Peak memory 221880 kb
Host smart-fc9b4bdd-4874-4852-a16c-22dcdc6fdcbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=69530693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.69530693
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2632704713
Short name T2718
Test name
Test status
Simulation time 558039837 ps
CPU time 2.95 seconds
Started Jun 30 05:43:02 PM PDT 24
Finished Jun 30 05:43:06 PM PDT 24
Peak memory 206052 kb
Host smart-5b7a977e-d7a0-44b9-8346-79431d94adc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2632704713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2632704713
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3417951068
Short name T2666
Test name
Test status
Simulation time 110286819 ps
CPU time 1.26 seconds
Started Jun 30 05:43:13 PM PDT 24
Finished Jun 30 05:43:15 PM PDT 24
Peak memory 215924 kb
Host smart-8dfc6aed-ae4f-4814-be8f-9c875ed86faa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417951068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3417951068
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1833745970
Short name T2699
Test name
Test status
Simulation time 47632167 ps
CPU time 0.97 seconds
Started Jun 30 05:43:03 PM PDT 24
Finished Jun 30 05:43:04 PM PDT 24
Peak memory 206048 kb
Host smart-f07a3391-b881-46de-9152-e1c22ab90bb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1833745970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1833745970
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2433034925
Short name T2657
Test name
Test status
Simulation time 82030978 ps
CPU time 0.73 seconds
Started Jun 30 05:43:04 PM PDT 24
Finished Jun 30 05:43:05 PM PDT 24
Peak memory 205812 kb
Host smart-d3fa4a65-a42c-44ef-b177-687c76036d83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2433034925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2433034925
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2764740198
Short name T2692
Test name
Test status
Simulation time 66157650 ps
CPU time 1.02 seconds
Started Jun 30 05:43:13 PM PDT 24
Finished Jun 30 05:43:15 PM PDT 24
Peak memory 206012 kb
Host smart-7345a674-90d7-4e29-a936-f126073e25c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2764740198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2764740198
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.88080495
Short name T295
Test name
Test status
Simulation time 391275150 ps
CPU time 2.78 seconds
Started Jun 30 05:43:04 PM PDT 24
Finished Jun 30 05:43:08 PM PDT 24
Peak memory 206032 kb
Host smart-541b4a93-3dba-4da0-bf43-163d7a0f390c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=88080495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.88080495
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2153991686
Short name T253
Test name
Test status
Simulation time 82607578 ps
CPU time 1.79 seconds
Started Jun 30 05:43:09 PM PDT 24
Finished Jun 30 05:43:11 PM PDT 24
Peak memory 214300 kb
Host smart-affd77ef-01b5-4c73-9a68-740816d5b6c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153991686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2153991686
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3242920648
Short name T276
Test name
Test status
Simulation time 66373871 ps
CPU time 1.01 seconds
Started Jun 30 05:43:09 PM PDT 24
Finished Jun 30 05:43:10 PM PDT 24
Peak memory 205980 kb
Host smart-f161879b-4dd2-411b-a082-51518402fa92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3242920648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3242920648
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.452640709
Short name T2713
Test name
Test status
Simulation time 103565096 ps
CPU time 1.06 seconds
Started Jun 30 05:43:08 PM PDT 24
Finished Jun 30 05:43:10 PM PDT 24
Peak memory 206004 kb
Host smart-4a7fc921-a40a-45f2-a582-721912eb3488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=452640709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.452640709
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2670972987
Short name T255
Test name
Test status
Simulation time 327496538 ps
CPU time 2.76 seconds
Started Jun 30 05:43:10 PM PDT 24
Finished Jun 30 05:43:13 PM PDT 24
Peak memory 206104 kb
Host smart-11926152-b026-4967-87a6-2d2f7a9c6e81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2670972987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2670972987
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3202027768
Short name T2663
Test name
Test status
Simulation time 285862398 ps
CPU time 2.46 seconds
Started Jun 30 05:43:09 PM PDT 24
Finished Jun 30 05:43:12 PM PDT 24
Peak memory 205996 kb
Host smart-abbb925e-3d21-4d26-b749-b7b02c9a2244
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3202027768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3202027768
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2488301909
Short name T297
Test name
Test status
Simulation time 207530483 ps
CPU time 1.99 seconds
Started Jun 30 05:43:10 PM PDT 24
Finished Jun 30 05:43:12 PM PDT 24
Peak memory 214512 kb
Host smart-58b747a0-a468-4a2f-80ab-b479879d29b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488301909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2488301909
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3135896850
Short name T2647
Test name
Test status
Simulation time 126611451 ps
CPU time 0.92 seconds
Started Jun 30 05:43:08 PM PDT 24
Finished Jun 30 05:43:10 PM PDT 24
Peak memory 205904 kb
Host smart-e227d43e-b9e4-4009-8c58-85dfeab39c57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3135896850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3135896850
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2109138939
Short name T302
Test name
Test status
Simulation time 69470928 ps
CPU time 0.67 seconds
Started Jun 30 05:43:08 PM PDT 24
Finished Jun 30 05:43:09 PM PDT 24
Peak memory 205856 kb
Host smart-0e9926d3-1202-4044-8f08-41e4d47baa8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2109138939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2109138939
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3410825217
Short name T2706
Test name
Test status
Simulation time 252766702 ps
CPU time 1.8 seconds
Started Jun 30 05:43:11 PM PDT 24
Finished Jun 30 05:43:13 PM PDT 24
Peak memory 206040 kb
Host smart-b4b1b8a2-9129-40f7-af8a-cb8cefc3415a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3410825217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3410825217
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3696173315
Short name T2709
Test name
Test status
Simulation time 63645822 ps
CPU time 1.55 seconds
Started Jun 30 05:43:11 PM PDT 24
Finished Jun 30 05:43:13 PM PDT 24
Peak memory 206060 kb
Host smart-2bb194aa-2554-4fa8-ad5c-1a20311c0a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3696173315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3696173315
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.647224834
Short name T265
Test name
Test status
Simulation time 713542232 ps
CPU time 4.49 seconds
Started Jun 30 05:43:09 PM PDT 24
Finished Jun 30 05:43:14 PM PDT 24
Peak memory 206088 kb
Host smart-3b4ff946-2fdb-48e7-b1d9-32f326e018a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=647224834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.647224834
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2936612175
Short name T1046
Test name
Test status
Simulation time 4062224729 ps
CPU time 4.72 seconds
Started Jun 30 06:19:55 PM PDT 24
Finished Jun 30 06:20:02 PM PDT 24
Peak memory 206268 kb
Host smart-4dc10a88-a358-466d-b31a-3d8caa850505
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2936612175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.2936612175
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.1947191373
Short name T977
Test name
Test status
Simulation time 13441329341 ps
CPU time 13.21 seconds
Started Jun 30 06:19:54 PM PDT 24
Finished Jun 30 06:20:09 PM PDT 24
Peak memory 206524 kb
Host smart-825e595e-dbc7-41a8-9121-85a115f4eb50
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1947191373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1947191373
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3073436285
Short name T2321
Test name
Test status
Simulation time 23380564150 ps
CPU time 23.15 seconds
Started Jun 30 06:19:58 PM PDT 24
Finished Jun 30 06:20:22 PM PDT 24
Peak memory 206468 kb
Host smart-cc5a5995-60a7-4729-bc11-e5a269db459d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3073436285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3073436285
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1094328239
Short name T947
Test name
Test status
Simulation time 148527837 ps
CPU time 0.76 seconds
Started Jun 30 06:19:56 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 206148 kb
Host smart-912d50a3-d429-4987-8948-acbb9690cf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
28239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1094328239
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.2964558973
Short name T1252
Test name
Test status
Simulation time 158310868 ps
CPU time 0.79 seconds
Started Jun 30 06:19:56 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 206172 kb
Host smart-be0d0285-7175-4d47-95ab-0fb2c932eaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29645
58973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.2964558973
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3041118978
Short name T199
Test name
Test status
Simulation time 519669973 ps
CPU time 1.54 seconds
Started Jun 30 06:19:57 PM PDT 24
Finished Jun 30 06:20:00 PM PDT 24
Peak memory 206264 kb
Host smart-b0448682-8cef-4f24-98b9-23dfaf68e71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30411
18978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3041118978
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2729015175
Short name T174
Test name
Test status
Simulation time 1378924223 ps
CPU time 2.89 seconds
Started Jun 30 06:19:57 PM PDT 24
Finished Jun 30 06:20:01 PM PDT 24
Peak memory 206284 kb
Host smart-6d7b2a3c-707f-40fa-be96-817af86b3733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27290
15175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2729015175
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.898925124
Short name T188
Test name
Test status
Simulation time 21855537736 ps
CPU time 37.67 seconds
Started Jun 30 06:20:00 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206256 kb
Host smart-257a49d7-3922-4783-af02-e6c08949dcd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89892
5124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.898925124
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.4288378033
Short name T207
Test name
Test status
Simulation time 388627909 ps
CPU time 1.3 seconds
Started Jun 30 06:19:56 PM PDT 24
Finished Jun 30 06:19:59 PM PDT 24
Peak memory 206200 kb
Host smart-22eef859-2b29-4af7-82a7-89b4e9bd7675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42883
78033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.4288378033
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1403369949
Short name T1168
Test name
Test status
Simulation time 170101304 ps
CPU time 0.78 seconds
Started Jun 30 06:19:56 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 206164 kb
Host smart-c7ce4efa-00d7-45dc-b553-bacce72c6e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14033
69949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1403369949
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3269572060
Short name T1254
Test name
Test status
Simulation time 5108493488 ps
CPU time 129.86 seconds
Started Jun 30 06:19:54 PM PDT 24
Finished Jun 30 06:22:06 PM PDT 24
Peak memory 206472 kb
Host smart-64e36657-d30d-4b5d-bbd9-1f2fb8668371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32695
72060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3269572060
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.2139700073
Short name T332
Test name
Test status
Simulation time 54612507 ps
CPU time 0.64 seconds
Started Jun 30 06:19:55 PM PDT 24
Finished Jun 30 06:19:57 PM PDT 24
Peak memory 206192 kb
Host smart-57a5c196-4f75-40b6-9445-1700eb4f5919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21397
00073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2139700073
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2944879308
Short name T1107
Test name
Test status
Simulation time 1030309460 ps
CPU time 2.26 seconds
Started Jun 30 06:19:58 PM PDT 24
Finished Jun 30 06:20:01 PM PDT 24
Peak memory 206288 kb
Host smart-82a77da1-7bfb-4a90-a749-c656062be72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29448
79308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2944879308
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.781931652
Short name T111
Test name
Test status
Simulation time 205639101 ps
CPU time 0.83 seconds
Started Jun 30 06:19:58 PM PDT 24
Finished Jun 30 06:20:00 PM PDT 24
Peak memory 206204 kb
Host smart-c587f5bd-bcf7-43b9-a4f6-2d58e1ea5a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78193
1652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.781931652
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3914375738
Short name T1714
Test name
Test status
Simulation time 172675344 ps
CPU time 0.84 seconds
Started Jun 30 06:19:56 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 206200 kb
Host smart-aea073fa-8aff-4ac6-a783-42fa2391b93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39143
75738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3914375738
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.511675110
Short name T1093
Test name
Test status
Simulation time 193577912 ps
CPU time 0.93 seconds
Started Jun 30 06:19:55 PM PDT 24
Finished Jun 30 06:19:58 PM PDT 24
Peak memory 206184 kb
Host smart-ec80c6c8-07f1-477c-b710-86127ca152eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51167
5110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.511675110
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1566823113
Short name T104
Test name
Test status
Simulation time 5351848960 ps
CPU time 51.26 seconds
Started Jun 30 06:19:57 PM PDT 24
Finished Jun 30 06:20:50 PM PDT 24
Peak memory 206448 kb
Host smart-da1d8d5f-d559-4670-bc87-e7a080c4d298
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1566823113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1566823113
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3238948649
Short name T756
Test name
Test status
Simulation time 263563164 ps
CPU time 0.91 seconds
Started Jun 30 06:19:55 PM PDT 24
Finished Jun 30 06:19:57 PM PDT 24
Peak memory 206180 kb
Host smart-7df43fa5-d4d3-4279-903f-cb40c993c8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32389
48649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3238948649
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.809475113
Short name T65
Test name
Test status
Simulation time 494733884 ps
CPU time 1.36 seconds
Started Jun 30 06:20:00 PM PDT 24
Finished Jun 30 06:20:02 PM PDT 24
Peak memory 206188 kb
Host smart-78dee012-c472-48be-843e-38f0a2a5a23a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80947
5113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.809475113
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1797857760
Short name T1354
Test name
Test status
Simulation time 23339130207 ps
CPU time 23.77 seconds
Started Jun 30 06:20:02 PM PDT 24
Finished Jun 30 06:20:26 PM PDT 24
Peak memory 206280 kb
Host smart-35216fab-a7c6-4804-9d2c-7d563d5c248e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17978
57760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1797857760
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2782158688
Short name T435
Test name
Test status
Simulation time 3332704380 ps
CPU time 3.66 seconds
Started Jun 30 06:20:00 PM PDT 24
Finished Jun 30 06:20:04 PM PDT 24
Peak memory 206248 kb
Host smart-25f0ce07-7b8a-4d49-9a13-e7187ebf7dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27821
58688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2782158688
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3810980931
Short name T2260
Test name
Test status
Simulation time 10904084549 ps
CPU time 107.19 seconds
Started Jun 30 06:20:01 PM PDT 24
Finished Jun 30 06:21:49 PM PDT 24
Peak memory 206440 kb
Host smart-6d7c6795-dfc6-4856-8b39-5ceaffc77651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38109
80931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3810980931
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2052900006
Short name T1750
Test name
Test status
Simulation time 3060416479 ps
CPU time 30.69 seconds
Started Jun 30 06:20:01 PM PDT 24
Finished Jun 30 06:20:32 PM PDT 24
Peak memory 206456 kb
Host smart-9524ff75-70d3-4f57-b302-691579ff2960
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2052900006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2052900006
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3967917666
Short name T2447
Test name
Test status
Simulation time 257435891 ps
CPU time 0.93 seconds
Started Jun 30 06:20:01 PM PDT 24
Finished Jun 30 06:20:02 PM PDT 24
Peak memory 206208 kb
Host smart-bf4a51e3-e1c7-481b-b392-1ef7a20ee22e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3967917666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3967917666
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1557274289
Short name T1290
Test name
Test status
Simulation time 195738617 ps
CPU time 0.91 seconds
Started Jun 30 06:20:01 PM PDT 24
Finished Jun 30 06:20:03 PM PDT 24
Peak memory 206192 kb
Host smart-61279cfa-d537-4d6e-ab00-d27b5932d858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
74289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1557274289
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.1900843211
Short name T2526
Test name
Test status
Simulation time 5188384847 ps
CPU time 46.4 seconds
Started Jun 30 06:20:00 PM PDT 24
Finished Jun 30 06:20:47 PM PDT 24
Peak memory 206512 kb
Host smart-0ce792a7-b642-47b0-a0f1-5c9ba017a294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19008
43211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.1900843211
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.4096705944
Short name T1215
Test name
Test status
Simulation time 4571028004 ps
CPU time 36.13 seconds
Started Jun 30 06:20:02 PM PDT 24
Finished Jun 30 06:20:39 PM PDT 24
Peak memory 206432 kb
Host smart-bbfe2586-0582-4cc5-9593-5bef9b329900
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4096705944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.4096705944
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1625702082
Short name T453
Test name
Test status
Simulation time 164440644 ps
CPU time 0.81 seconds
Started Jun 30 06:20:01 PM PDT 24
Finished Jun 30 06:20:02 PM PDT 24
Peak memory 206200 kb
Host smart-12138aa3-57c6-4377-ad06-f3a3e3c0ef50
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1625702082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1625702082
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1826765011
Short name T2283
Test name
Test status
Simulation time 170242139 ps
CPU time 0.84 seconds
Started Jun 30 06:20:04 PM PDT 24
Finished Jun 30 06:20:05 PM PDT 24
Peak memory 206200 kb
Host smart-7ba96fdd-fa13-4745-ab77-9b4efa327813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18267
65011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1826765011
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.595255995
Short name T67
Test name
Test status
Simulation time 529193181 ps
CPU time 1.52 seconds
Started Jun 30 06:20:04 PM PDT 24
Finished Jun 30 06:20:06 PM PDT 24
Peak memory 206184 kb
Host smart-1208940a-0210-4ad1-baa8-e347cb95ef68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59525
5995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.595255995
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3862242277
Short name T1185
Test name
Test status
Simulation time 164494951 ps
CPU time 0.81 seconds
Started Jun 30 06:20:09 PM PDT 24
Finished Jun 30 06:20:10 PM PDT 24
Peak memory 206192 kb
Host smart-1d8e4dba-cd12-4544-b343-c0aed8b5bacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
42277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3862242277
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3688832025
Short name T1396
Test name
Test status
Simulation time 147517833 ps
CPU time 0.76 seconds
Started Jun 30 06:20:13 PM PDT 24
Finished Jun 30 06:20:14 PM PDT 24
Peak memory 206180 kb
Host smart-2011c724-a30d-4742-8e18-a88a1d127839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36888
32025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3688832025
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1842769675
Short name T1712
Test name
Test status
Simulation time 173446674 ps
CPU time 0.87 seconds
Started Jun 30 06:20:09 PM PDT 24
Finished Jun 30 06:20:10 PM PDT 24
Peak memory 206124 kb
Host smart-0d28fb1a-8ab0-4883-83b2-7abeef241511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18427
69675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1842769675
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2467545594
Short name T477
Test name
Test status
Simulation time 210296957 ps
CPU time 0.92 seconds
Started Jun 30 06:20:07 PM PDT 24
Finished Jun 30 06:20:08 PM PDT 24
Peak memory 206200 kb
Host smart-5117ff71-a563-48d3-9b89-438b068c8ebe
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2467545594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2467545594
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3195131497
Short name T1990
Test name
Test status
Simulation time 241942313 ps
CPU time 1 seconds
Started Jun 30 06:20:10 PM PDT 24
Finished Jun 30 06:20:11 PM PDT 24
Peak memory 206188 kb
Host smart-c637750b-b810-4ea3-a10b-1790f77051ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31951
31497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3195131497
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1254392889
Short name T2611
Test name
Test status
Simulation time 257632778 ps
CPU time 0.98 seconds
Started Jun 30 06:20:09 PM PDT 24
Finished Jun 30 06:20:10 PM PDT 24
Peak memory 206208 kb
Host smart-d62dc3f9-1acd-4295-83d7-d393b58aa36e
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1254392889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1254392889
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2497500287
Short name T225
Test name
Test status
Simulation time 195931861 ps
CPU time 0.97 seconds
Started Jun 30 06:20:08 PM PDT 24
Finished Jun 30 06:20:09 PM PDT 24
Peak memory 206168 kb
Host smart-1d58e7ed-45ab-4682-93d2-b3fa9170af77
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2497500287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.2497500287
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.625814401
Short name T2199
Test name
Test status
Simulation time 146074382 ps
CPU time 0.78 seconds
Started Jun 30 06:20:09 PM PDT 24
Finished Jun 30 06:20:10 PM PDT 24
Peak memory 206212 kb
Host smart-35c87c84-b1b9-4b2e-a0b5-05bfac315980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62581
4401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.625814401
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1697917929
Short name T37
Test name
Test status
Simulation time 77564673 ps
CPU time 0.75 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:27 PM PDT 24
Peak memory 206200 kb
Host smart-f6b141ec-3a21-4b2c-b825-e9c8605de2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16979
17929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1697917929
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.1469870689
Short name T2547
Test name
Test status
Simulation time 7548473501 ps
CPU time 15.86 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:20:39 PM PDT 24
Peak memory 206456 kb
Host smart-a4f74014-b1f1-460f-afd0-bb8f7c70fa0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14698
70689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1469870689
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2920579851
Short name T2588
Test name
Test status
Simulation time 184038180 ps
CPU time 0.9 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:26 PM PDT 24
Peak memory 206180 kb
Host smart-2af9392a-ca0d-4732-a6f6-20a6b8fdcc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29205
79851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2920579851
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2973243440
Short name T2402
Test name
Test status
Simulation time 266608602 ps
CPU time 0.96 seconds
Started Jun 30 06:20:21 PM PDT 24
Finished Jun 30 06:20:22 PM PDT 24
Peak memory 206200 kb
Host smart-e828db87-8b74-4fa5-9fc4-c9160e73ae4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29732
43440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2973243440
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1671485774
Short name T156
Test name
Test status
Simulation time 6654920457 ps
CPU time 185 seconds
Started Jun 30 06:20:16 PM PDT 24
Finished Jun 30 06:23:21 PM PDT 24
Peak memory 206480 kb
Host smart-97645eac-5681-4fcb-b176-fef4c3d8d4c5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1671485774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1671485774
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.742482407
Short name T878
Test name
Test status
Simulation time 12955724582 ps
CPU time 90.21 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:21:55 PM PDT 24
Peak memory 206420 kb
Host smart-4041ea7b-79cf-4cd1-946d-327d134692e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=742482407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.742482407
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1446101355
Short name T1776
Test name
Test status
Simulation time 189218307 ps
CPU time 0.87 seconds
Started Jun 30 06:20:17 PM PDT 24
Finished Jun 30 06:20:18 PM PDT 24
Peak memory 206344 kb
Host smart-9b186d4c-838c-41c1-9105-f993d6a4b576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14461
01355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1446101355
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3486154622
Short name T369
Test name
Test status
Simulation time 221060074 ps
CPU time 0.84 seconds
Started Jun 30 06:20:14 PM PDT 24
Finished Jun 30 06:20:16 PM PDT 24
Peak memory 206184 kb
Host smart-4fe3b06b-555a-4614-9184-6d058151915e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34861
54622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3486154622
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.947914142
Short name T1441
Test name
Test status
Simulation time 191961357 ps
CPU time 0.8 seconds
Started Jun 30 06:20:15 PM PDT 24
Finished Jun 30 06:20:16 PM PDT 24
Peak memory 206192 kb
Host smart-5aee2d78-0835-486b-88b5-b42290aaad82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94791
4142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.947914142
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.4204239673
Short name T231
Test name
Test status
Simulation time 1327977876 ps
CPU time 2.41 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:27 PM PDT 24
Peak memory 225112 kb
Host smart-2ec6388d-162e-436e-bf16-d4cf84c843b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4204239673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.4204239673
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.1398481343
Short name T181
Test name
Test status
Simulation time 180880399 ps
CPU time 0.86 seconds
Started Jun 30 06:20:17 PM PDT 24
Finished Jun 30 06:20:18 PM PDT 24
Peak memory 206360 kb
Host smart-c0f69f60-a957-44de-b908-e55e0df6042b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13984
81343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.1398481343
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2736665098
Short name T766
Test name
Test status
Simulation time 151883177 ps
CPU time 0.82 seconds
Started Jun 30 06:20:13 PM PDT 24
Finished Jun 30 06:20:15 PM PDT 24
Peak memory 206168 kb
Host smart-ba6d8c26-3aec-49ab-a2e4-936945e2bce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27366
65098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2736665098
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.578067024
Short name T2170
Test name
Test status
Simulation time 145549978 ps
CPU time 0.76 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:20:24 PM PDT 24
Peak memory 206164 kb
Host smart-88f7328d-0193-48f6-a9b4-178f7d702b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57806
7024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.578067024
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1502519115
Short name T2468
Test name
Test status
Simulation time 215963068 ps
CPU time 0.9 seconds
Started Jun 30 06:20:18 PM PDT 24
Finished Jun 30 06:20:20 PM PDT 24
Peak memory 206212 kb
Host smart-a9162da3-d97c-475a-b8b1-ef4389e53110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15025
19115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1502519115
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2794066575
Short name T2303
Test name
Test status
Simulation time 6670524398 ps
CPU time 204.31 seconds
Started Jun 30 06:20:14 PM PDT 24
Finished Jun 30 06:23:39 PM PDT 24
Peak memory 206472 kb
Host smart-313a9586-7bab-4788-a488-2656ee608553
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2794066575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2794066575
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.998500752
Short name T1204
Test name
Test status
Simulation time 168621029 ps
CPU time 0.83 seconds
Started Jun 30 06:20:15 PM PDT 24
Finished Jun 30 06:20:17 PM PDT 24
Peak memory 206204 kb
Host smart-be89b823-6d51-4f3f-a4da-789cf7a2ecfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99850
0752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.998500752
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.953261558
Short name T2407
Test name
Test status
Simulation time 189799095 ps
CPU time 0.85 seconds
Started Jun 30 06:20:21 PM PDT 24
Finished Jun 30 06:20:22 PM PDT 24
Peak memory 206200 kb
Host smart-1eb858f4-3c53-4531-b27f-4951e57857c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95326
1558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.953261558
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.2807734719
Short name T909
Test name
Test status
Simulation time 4335275394 ps
CPU time 38.74 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206456 kb
Host smart-d5b7aa68-8de3-41d2-a8e3-9bf8134c041f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28077
34719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.2807734719
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.149705512
Short name T2083
Test name
Test status
Simulation time 12425439226 ps
CPU time 230.38 seconds
Started Jun 30 06:20:15 PM PDT 24
Finished Jun 30 06:24:06 PM PDT 24
Peak memory 206496 kb
Host smart-1c985316-6350-44f8-afef-d1e736c81864
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=149705512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.149705512
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.4015294962
Short name T1753
Test name
Test status
Simulation time 37115476 ps
CPU time 0.7 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:28 PM PDT 24
Peak memory 206204 kb
Host smart-af9799a4-3e8f-46ed-bdfb-2cd8cf6c83ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4015294962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.4015294962
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3575264197
Short name T2263
Test name
Test status
Simulation time 3975437127 ps
CPU time 5.54 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206256 kb
Host smart-577cce94-9740-41b9-bc31-49ce7a37a668
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3575264197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.3575264197
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2999451050
Short name T931
Test name
Test status
Simulation time 23336621324 ps
CPU time 23.98 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:49 PM PDT 24
Peak memory 206268 kb
Host smart-f6f93388-f0ce-4bae-8bfd-aad76ce6f344
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2999451050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.2999451050
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2564748704
Short name T1123
Test name
Test status
Simulation time 174741685 ps
CPU time 0.8 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:27 PM PDT 24
Peak memory 206164 kb
Host smart-2ebb498f-53ef-4ffb-859b-5e7fb12433c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25647
48704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2564748704
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.3761933473
Short name T1969
Test name
Test status
Simulation time 198944193 ps
CPU time 0.82 seconds
Started Jun 30 06:20:14 PM PDT 24
Finished Jun 30 06:20:15 PM PDT 24
Peak memory 206208 kb
Host smart-af71ba00-5a1d-497b-b144-6773d3fc7c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37619
33473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.3761933473
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.436724203
Short name T47
Test name
Test status
Simulation time 141776007 ps
CPU time 0.79 seconds
Started Jun 30 06:20:16 PM PDT 24
Finished Jun 30 06:20:17 PM PDT 24
Peak memory 206188 kb
Host smart-49d1e403-e3d6-47b0-8dcc-9a4aac568ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43672
4203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.436724203
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.4076398523
Short name T559
Test name
Test status
Simulation time 147433727 ps
CPU time 0.81 seconds
Started Jun 30 06:20:16 PM PDT 24
Finished Jun 30 06:20:17 PM PDT 24
Peak memory 206192 kb
Host smart-abb93c79-dfe5-4aa1-9396-7084ee2d6ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40763
98523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.4076398523
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.3248582743
Short name T610
Test name
Test status
Simulation time 329452829 ps
CPU time 1.18 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:27 PM PDT 24
Peak memory 206144 kb
Host smart-45a2f35b-8113-4c11-8d8d-0641700d29a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32485
82743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.3248582743
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1425611829
Short name T170
Test name
Test status
Simulation time 817083042 ps
CPU time 2.22 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206292 kb
Host smart-8d2689fb-ccb4-49b5-963b-b2f9329b07e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14256
11829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1425611829
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2632505746
Short name T165
Test name
Test status
Simulation time 12466223226 ps
CPU time 23.1 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:20:46 PM PDT 24
Peak memory 206420 kb
Host smart-0dc610e3-80ea-40ce-b24d-bc8bff1e47e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26325
05746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2632505746
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2070468631
Short name T2363
Test name
Test status
Simulation time 297019527 ps
CPU time 1.16 seconds
Started Jun 30 06:20:15 PM PDT 24
Finished Jun 30 06:20:17 PM PDT 24
Peak memory 206148 kb
Host smart-d48f9d39-0663-4d66-80af-986e7946f014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20704
68631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2070468631
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1486709029
Short name T2546
Test name
Test status
Simulation time 172808228 ps
CPU time 0.8 seconds
Started Jun 30 06:20:14 PM PDT 24
Finished Jun 30 06:20:16 PM PDT 24
Peak memory 206192 kb
Host smart-2e85d588-8fc4-4a53-b5fc-4a2bea942235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14867
09029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1486709029
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1688211571
Short name T2631
Test name
Test status
Simulation time 57026022 ps
CPU time 0.68 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:30 PM PDT 24
Peak memory 206340 kb
Host smart-476f4a17-f3a8-4188-9271-50e134d71c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16882
11571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1688211571
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.307625686
Short name T518
Test name
Test status
Simulation time 929235714 ps
CPU time 2.02 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:28 PM PDT 24
Peak memory 206376 kb
Host smart-bd678ca2-c6e5-4492-b7e3-ab0b649a6b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30762
5686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.307625686
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1974210805
Short name T2451
Test name
Test status
Simulation time 208594590 ps
CPU time 1.33 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:26 PM PDT 24
Peak memory 206280 kb
Host smart-84284d22-4c93-4808-b432-48598cbaa754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19742
10805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1974210805
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.41597991
Short name T1432
Test name
Test status
Simulation time 165180721 ps
CPU time 0.79 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:27 PM PDT 24
Peak memory 206204 kb
Host smart-e9cff053-c273-471a-b392-833a96389334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41597
991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.41597991
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.850168911
Short name T608
Test name
Test status
Simulation time 149679279 ps
CPU time 0.78 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:27 PM PDT 24
Peak memory 206204 kb
Host smart-6e4d2453-13c8-4ff3-b43e-57e6de493426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85016
8911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.850168911
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.865981412
Short name T2425
Test name
Test status
Simulation time 207585356 ps
CPU time 0.91 seconds
Started Jun 30 06:20:26 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206200 kb
Host smart-ed3ef02e-4327-4225-b595-c93eb7712590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86598
1412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.865981412
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3945713711
Short name T401
Test name
Test status
Simulation time 262984182 ps
CPU time 0.99 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:30 PM PDT 24
Peak memory 206188 kb
Host smart-79b1c97d-a895-4c28-832f-ed13fdd5bf4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39457
13711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3945713711
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.963122164
Short name T232
Test name
Test status
Simulation time 23411331882 ps
CPU time 23.69 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:51 PM PDT 24
Peak memory 206300 kb
Host smart-28834d0a-4562-4617-9b45-b65aee4707e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96312
2164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.963122164
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3494869783
Short name T1409
Test name
Test status
Simulation time 3302249022 ps
CPU time 3.59 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:32 PM PDT 24
Peak memory 206240 kb
Host smart-45b44187-9a7b-4a39-b8a0-0f9936551d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34948
69783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3494869783
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.3916006370
Short name T1602
Test name
Test status
Simulation time 6676870982 ps
CPU time 186.39 seconds
Started Jun 30 06:20:26 PM PDT 24
Finished Jun 30 06:23:35 PM PDT 24
Peak memory 206420 kb
Host smart-d7973f12-2b99-4148-831e-cf3c738c9107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39160
06370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.3916006370
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1332029525
Short name T1905
Test name
Test status
Simulation time 7250484623 ps
CPU time 53.67 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:21:21 PM PDT 24
Peak memory 206376 kb
Host smart-f8250e68-b38a-4611-90d0-b3801abb6251
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1332029525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1332029525
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.4240151374
Short name T1138
Test name
Test status
Simulation time 255771870 ps
CPU time 0.92 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:28 PM PDT 24
Peak memory 206104 kb
Host smart-3d25c065-b9a6-4b79-af6a-700bd0d1af08
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4240151374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.4240151374
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.883602315
Short name T963
Test name
Test status
Simulation time 194446657 ps
CPU time 0.86 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206200 kb
Host smart-96018020-13ea-47c9-9c20-1845a2b67f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88360
2315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.883602315
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1476639144
Short name T460
Test name
Test status
Simulation time 6228480300 ps
CPU time 62.15 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:21:29 PM PDT 24
Peak memory 206388 kb
Host smart-5e7f1e16-6cae-4a33-a4b7-8870267a9bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14766
39144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1476639144
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.4069364712
Short name T1110
Test name
Test status
Simulation time 3765672899 ps
CPU time 99.7 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:22:07 PM PDT 24
Peak memory 206424 kb
Host smart-8bdaaee6-03d2-4598-9453-18b8d9e5e770
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4069364712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.4069364712
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1128555980
Short name T1112
Test name
Test status
Simulation time 155034808 ps
CPU time 0.81 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:28 PM PDT 24
Peak memory 206212 kb
Host smart-e8dec07d-caa5-46cc-8f57-d6600c01525e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1128555980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1128555980
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1150516814
Short name T1287
Test name
Test status
Simulation time 175369179 ps
CPU time 0.8 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:30 PM PDT 24
Peak memory 206208 kb
Host smart-d6ed47cf-ed2d-4619-a377-3df223992281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11505
16814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1150516814
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.2686723097
Short name T1446
Test name
Test status
Simulation time 226286523 ps
CPU time 0.86 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206192 kb
Host smart-6d25e2f9-3605-43a2-a0f4-5036e96506b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26867
23097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2686723097
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2193379165
Short name T2216
Test name
Test status
Simulation time 180595944 ps
CPU time 0.84 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:20:23 PM PDT 24
Peak memory 206188 kb
Host smart-7260cd1e-a21e-4561-b4f2-ae54d675dd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21933
79165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2193379165
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1122725495
Short name T1322
Test name
Test status
Simulation time 208068714 ps
CPU time 0.85 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:25 PM PDT 24
Peak memory 206192 kb
Host smart-ea12cf42-9928-4ee4-9abb-067ebac6fd1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11227
25495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1122725495
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3351620836
Short name T1041
Test name
Test status
Simulation time 194226976 ps
CPU time 0.84 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:20:24 PM PDT 24
Peak memory 206208 kb
Host smart-ba3aad85-664f-4943-b4f9-bf5618ca2528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33516
20836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3351620836
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2848672741
Short name T2098
Test name
Test status
Simulation time 242211249 ps
CPU time 1.04 seconds
Started Jun 30 06:20:26 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206156 kb
Host smart-8423329c-30fe-4d95-8ae1-98b88a8bb8f5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2848672741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2848672741
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.694461158
Short name T223
Test name
Test status
Simulation time 186783569 ps
CPU time 0.85 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:26 PM PDT 24
Peak memory 206180 kb
Host smart-ae53f7bc-469e-4dd0-b56a-6def69eb395d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69446
1158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.694461158
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3394587401
Short name T213
Test name
Test status
Simulation time 139975964 ps
CPU time 0.8 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:27 PM PDT 24
Peak memory 206212 kb
Host smart-65f0ea2b-a7ac-4c4f-b8cf-5949dec1732d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33945
87401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3394587401
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3074229554
Short name T1527
Test name
Test status
Simulation time 44454656 ps
CPU time 0.71 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206232 kb
Host smart-509a3af4-e006-4164-85ba-309d9b3a54fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30742
29554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3074229554
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.4155909833
Short name T1762
Test name
Test status
Simulation time 6815603797 ps
CPU time 16.17 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:41 PM PDT 24
Peak memory 206420 kb
Host smart-8ea1c439-c187-433e-a1c3-73f5c7fe383f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41559
09833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.4155909833
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2271197155
Short name T1794
Test name
Test status
Simulation time 199052024 ps
CPU time 0.97 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206236 kb
Host smart-685ddee8-5b4d-4c80-9ee6-ce6b1c2dfdc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22711
97155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2271197155
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2072696063
Short name T1037
Test name
Test status
Simulation time 254095158 ps
CPU time 0.99 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:28 PM PDT 24
Peak memory 206124 kb
Host smart-b13db317-7c7e-4dc1-961e-7bd07dfd9b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20726
96063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2072696063
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2779613815
Short name T1448
Test name
Test status
Simulation time 4909687484 ps
CPU time 108.37 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:22:13 PM PDT 24
Peak memory 206476 kb
Host smart-dedd41f4-46f2-4bf4-8887-bff0507c7652
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2779613815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2779613815
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2847376753
Short name T1914
Test name
Test status
Simulation time 14011516873 ps
CPU time 299.6 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:25:23 PM PDT 24
Peak memory 206480 kb
Host smart-50a49e2d-7306-493d-afc2-fbef4e0a0235
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2847376753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2847376753
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3233103064
Short name T2053
Test name
Test status
Simulation time 11198713582 ps
CPU time 216.06 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:24:01 PM PDT 24
Peak memory 206492 kb
Host smart-992db412-a112-4f75-a497-429d479c9369
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3233103064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3233103064
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3627734342
Short name T1022
Test name
Test status
Simulation time 196895340 ps
CPU time 0.83 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:26 PM PDT 24
Peak memory 206212 kb
Host smart-c7bb69b6-0776-479c-88ac-ef544f308715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36277
34342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3627734342
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.992928335
Short name T495
Test name
Test status
Simulation time 167473064 ps
CPU time 0.87 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206116 kb
Host smart-396c94fc-9452-4ea3-bf0d-6a3a3bdce214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99292
8335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.992928335
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3420801302
Short name T2130
Test name
Test status
Simulation time 153708557 ps
CPU time 0.8 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:28 PM PDT 24
Peak memory 206196 kb
Host smart-eed18320-9638-46ba-852d-0afe98c0c0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34208
01302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3420801302
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2823241704
Short name T71
Test name
Test status
Simulation time 183157315 ps
CPU time 0.86 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:28 PM PDT 24
Peak memory 206176 kb
Host smart-b65ef2fd-e007-42f2-a4d9-d00b4fb7fd7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28232
41704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2823241704
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2241103183
Short name T230
Test name
Test status
Simulation time 273068693 ps
CPU time 1.1 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:20:25 PM PDT 24
Peak memory 224004 kb
Host smart-a24c4500-bfdf-49cc-9123-e6dad2be5496
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2241103183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2241103183
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.64738273
Short name T56
Test name
Test status
Simulation time 437309987 ps
CPU time 1.23 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:20:25 PM PDT 24
Peak memory 206196 kb
Host smart-f5846aa8-f181-4039-b130-309aadf64581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64738
273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.64738273
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.4107013787
Short name T2626
Test name
Test status
Simulation time 156325573 ps
CPU time 0.84 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206232 kb
Host smart-e570854b-3742-43b1-9b8f-3fd8fbaedb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41070
13787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.4107013787
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.25657933
Short name T2175
Test name
Test status
Simulation time 160015767 ps
CPU time 0.8 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:26 PM PDT 24
Peak memory 206196 kb
Host smart-f32e5a16-306f-4e66-8a23-91b44b91a891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25657
933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.25657933
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.477447240
Short name T779
Test name
Test status
Simulation time 201130442 ps
CPU time 0.89 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206176 kb
Host smart-8253457d-3fc2-48a7-895b-028d5165ac6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47744
7240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.477447240
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2784869243
Short name T2374
Test name
Test status
Simulation time 5760807670 ps
CPU time 41.56 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206436 kb
Host smart-b9316ef0-6eec-4aa2-b456-4bbe763f3579
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2784869243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2784869243
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.4079444714
Short name T143
Test name
Test status
Simulation time 172072853 ps
CPU time 0.82 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:25 PM PDT 24
Peak memory 206224 kb
Host smart-6a8e9eaa-05f7-46fe-a55f-0c398da7b54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40794
44714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.4079444714
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2031637129
Short name T1019
Test name
Test status
Simulation time 179406152 ps
CPU time 0.83 seconds
Started Jun 30 06:20:21 PM PDT 24
Finished Jun 30 06:20:22 PM PDT 24
Peak memory 206172 kb
Host smart-3eed83da-8922-4ef3-a8e2-85d85b245fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20316
37129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2031637129
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3146510408
Short name T987
Test name
Test status
Simulation time 4977048038 ps
CPU time 46.88 seconds
Started Jun 30 06:20:22 PM PDT 24
Finished Jun 30 06:21:11 PM PDT 24
Peak memory 206368 kb
Host smart-62a59566-5295-4ae4-b825-f09384b5dd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31465
10408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3146510408
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.1435568004
Short name T1297
Test name
Test status
Simulation time 34966649 ps
CPU time 0.72 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206188 kb
Host smart-1e8bdd21-61d6-41f8-bcc7-e197730efbc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1435568004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.1435568004
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.807499350
Short name T2471
Test name
Test status
Simulation time 4157904350 ps
CPU time 4.74 seconds
Started Jun 30 06:21:42 PM PDT 24
Finished Jun 30 06:21:47 PM PDT 24
Peak memory 206360 kb
Host smart-6563d1a3-e267-46ad-9456-989f664e2efe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=807499350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.807499350
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2701279485
Short name T1433
Test name
Test status
Simulation time 13348010123 ps
CPU time 12.56 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:22:10 PM PDT 24
Peak memory 206276 kb
Host smart-59913d56-ce1c-481d-a9b9-4c214d675f23
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2701279485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2701279485
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.2735426317
Short name T474
Test name
Test status
Simulation time 23377484299 ps
CPU time 23.64 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206276 kb
Host smart-da1cd427-24ab-41e0-8c1b-0f9bcc65163a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2735426317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.2735426317
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1039858524
Short name T2464
Test name
Test status
Simulation time 173618074 ps
CPU time 0.86 seconds
Started Jun 30 06:21:42 PM PDT 24
Finished Jun 30 06:21:44 PM PDT 24
Peak memory 206176 kb
Host smart-3f17338a-25f5-4d92-a105-bd77c0b92e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
58524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1039858524
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3137889411
Short name T590
Test name
Test status
Simulation time 145917709 ps
CPU time 0.87 seconds
Started Jun 30 06:21:40 PM PDT 24
Finished Jun 30 06:21:42 PM PDT 24
Peak memory 206184 kb
Host smart-ee625101-030b-4d17-99a3-7428294d7835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31378
89411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3137889411
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3912279772
Short name T1241
Test name
Test status
Simulation time 444094964 ps
CPU time 1.41 seconds
Started Jun 30 06:21:39 PM PDT 24
Finished Jun 30 06:21:41 PM PDT 24
Peak memory 206232 kb
Host smart-5df22ad5-bc3d-4363-af97-f99a9f6de18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39122
79772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3912279772
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.822074630
Short name T183
Test name
Test status
Simulation time 855756953 ps
CPU time 2.2 seconds
Started Jun 30 06:21:45 PM PDT 24
Finished Jun 30 06:21:48 PM PDT 24
Peak memory 206308 kb
Host smart-9cb2b3ed-893f-4df9-8d21-ed989a2755cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82207
4630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.822074630
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.675675728
Short name T2513
Test name
Test status
Simulation time 7548489713 ps
CPU time 15.03 seconds
Started Jun 30 06:21:39 PM PDT 24
Finished Jun 30 06:21:54 PM PDT 24
Peak memory 206412 kb
Host smart-dd9f5351-abe5-4797-b5a0-60b3b43ecaf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67567
5728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.675675728
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.634063584
Short name T1389
Test name
Test status
Simulation time 445022256 ps
CPU time 1.34 seconds
Started Jun 30 06:21:38 PM PDT 24
Finished Jun 30 06:21:40 PM PDT 24
Peak memory 206224 kb
Host smart-b64762a7-f4a8-4265-a048-1d649e1a78e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63406
3584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.634063584
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2468583258
Short name T1319
Test name
Test status
Simulation time 139104384 ps
CPU time 0.73 seconds
Started Jun 30 06:21:42 PM PDT 24
Finished Jun 30 06:21:43 PM PDT 24
Peak memory 206212 kb
Host smart-0ef9c1d0-98f2-4697-a385-a29fb55c9ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24685
83258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2468583258
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.4139469518
Short name T2420
Test name
Test status
Simulation time 33070124 ps
CPU time 0.68 seconds
Started Jun 30 06:21:42 PM PDT 24
Finished Jun 30 06:21:43 PM PDT 24
Peak memory 206112 kb
Host smart-4e16e1ef-3e6d-467a-9fb8-d0ecd50b0e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41394
69518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.4139469518
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.864788746
Short name T423
Test name
Test status
Simulation time 831536048 ps
CPU time 1.94 seconds
Started Jun 30 06:21:41 PM PDT 24
Finished Jun 30 06:21:44 PM PDT 24
Peak memory 206288 kb
Host smart-f6b4c971-cc7d-414b-ba5d-5f059407d276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86478
8746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.864788746
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3622663060
Short name T1922
Test name
Test status
Simulation time 238753113 ps
CPU time 1.55 seconds
Started Jun 30 06:21:40 PM PDT 24
Finished Jun 30 06:21:42 PM PDT 24
Peak memory 206288 kb
Host smart-333f0e13-927e-48e1-951f-9b17cd734198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226
63060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3622663060
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1048113354
Short name T1462
Test name
Test status
Simulation time 185922119 ps
CPU time 0.88 seconds
Started Jun 30 06:21:41 PM PDT 24
Finished Jun 30 06:21:43 PM PDT 24
Peak memory 206184 kb
Host smart-0266dd32-4452-45fa-9d99-c07cd8169770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10481
13354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1048113354
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.4035344265
Short name T2607
Test name
Test status
Simulation time 177663064 ps
CPU time 0.82 seconds
Started Jun 30 06:21:49 PM PDT 24
Finished Jun 30 06:21:50 PM PDT 24
Peak memory 206204 kb
Host smart-09f20430-e37b-42cb-8998-3884bb6728f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40353
44265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.4035344265
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1676147227
Short name T2627
Test name
Test status
Simulation time 233034409 ps
CPU time 0.88 seconds
Started Jun 30 06:21:45 PM PDT 24
Finished Jun 30 06:21:47 PM PDT 24
Peak memory 206188 kb
Host smart-11d6532c-a70e-4734-b01f-2b4a1fb15cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16761
47227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1676147227
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.80389930
Short name T99
Test name
Test status
Simulation time 7099961873 ps
CPU time 50.34 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:22:47 PM PDT 24
Peak memory 206224 kb
Host smart-db6da01c-13f8-4eae-9f55-b56dd72cea4b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=80389930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.80389930
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3804888304
Short name T372
Test name
Test status
Simulation time 193485916 ps
CPU time 0.89 seconds
Started Jun 30 06:21:47 PM PDT 24
Finished Jun 30 06:21:49 PM PDT 24
Peak memory 206160 kb
Host smart-be8008ce-2c12-4934-aa87-d9d306281b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38048
88304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3804888304
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3300414223
Short name T880
Test name
Test status
Simulation time 23318812483 ps
CPU time 23.38 seconds
Started Jun 30 06:21:48 PM PDT 24
Finished Jun 30 06:22:12 PM PDT 24
Peak memory 206284 kb
Host smart-7cd58479-6132-4300-8bd6-1ce659897c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33004
14223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3300414223
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.4071134329
Short name T1090
Test name
Test status
Simulation time 3313829278 ps
CPU time 4.48 seconds
Started Jun 30 06:21:47 PM PDT 24
Finished Jun 30 06:21:52 PM PDT 24
Peak memory 206228 kb
Host smart-0e91ad0e-4164-43d1-abc4-1518cb455ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40711
34329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.4071134329
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2120980356
Short name T1192
Test name
Test status
Simulation time 10440617087 ps
CPU time 81.25 seconds
Started Jun 30 06:21:47 PM PDT 24
Finished Jun 30 06:23:09 PM PDT 24
Peak memory 206480 kb
Host smart-0d0fdbf6-77bd-4b10-af6b-d2e7d92065a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21209
80356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2120980356
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3100080843
Short name T1739
Test name
Test status
Simulation time 5346753890 ps
CPU time 37.44 seconds
Started Jun 30 06:21:45 PM PDT 24
Finished Jun 30 06:22:23 PM PDT 24
Peak memory 206480 kb
Host smart-4e87de7c-ac93-4cd1-9f51-a4067c3fe73b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3100080843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3100080843
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2857539532
Short name T2415
Test name
Test status
Simulation time 277934068 ps
CPU time 0.96 seconds
Started Jun 30 06:21:47 PM PDT 24
Finished Jun 30 06:21:49 PM PDT 24
Peak memory 206212 kb
Host smart-3fa2fdea-0de6-453f-b413-f51eab9727b2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2857539532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2857539532
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3030471131
Short name T551
Test name
Test status
Simulation time 195398765 ps
CPU time 0.84 seconds
Started Jun 30 06:21:45 PM PDT 24
Finished Jun 30 06:21:47 PM PDT 24
Peak memory 206220 kb
Host smart-7cfc4c0e-04b9-4377-a9c8-80495c32da35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30304
71131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3030471131
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1531355454
Short name T1598
Test name
Test status
Simulation time 5386269810 ps
CPU time 38.64 seconds
Started Jun 30 06:21:48 PM PDT 24
Finished Jun 30 06:22:28 PM PDT 24
Peak memory 206448 kb
Host smart-d17fd1dc-79f6-4982-af7e-012210b51377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15313
55454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1531355454
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.2942460853
Short name T1001
Test name
Test status
Simulation time 5585090617 ps
CPU time 39.14 seconds
Started Jun 30 06:21:47 PM PDT 24
Finished Jun 30 06:22:27 PM PDT 24
Peak memory 206452 kb
Host smart-7443fa60-1617-490c-98e7-df4a1a7dd10b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2942460853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.2942460853
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.4039619738
Short name T2008
Test name
Test status
Simulation time 217253154 ps
CPU time 0.89 seconds
Started Jun 30 06:21:47 PM PDT 24
Finished Jun 30 06:21:49 PM PDT 24
Peak memory 206164 kb
Host smart-04c61a2e-9d5a-4c30-a59c-2a16a544887b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4039619738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.4039619738
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.817043066
Short name T1091
Test name
Test status
Simulation time 163400133 ps
CPU time 0.78 seconds
Started Jun 30 06:21:45 PM PDT 24
Finished Jun 30 06:21:46 PM PDT 24
Peak memory 206200 kb
Host smart-1fea28cb-4234-44ab-ae53-5b63396cf923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81704
3066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.817043066
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1824878775
Short name T124
Test name
Test status
Simulation time 182683649 ps
CPU time 0.9 seconds
Started Jun 30 06:21:46 PM PDT 24
Finished Jun 30 06:21:48 PM PDT 24
Peak memory 206200 kb
Host smart-703d1363-78f8-45ba-9dd6-cbca2f6b8864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18248
78775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1824878775
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2775436958
Short name T463
Test name
Test status
Simulation time 148855220 ps
CPU time 0.74 seconds
Started Jun 30 06:21:46 PM PDT 24
Finished Jun 30 06:21:48 PM PDT 24
Peak memory 206184 kb
Host smart-4eab9ec5-469c-4c23-b81c-be31dbc84890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27754
36958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2775436958
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.309764309
Short name T918
Test name
Test status
Simulation time 201978037 ps
CPU time 0.86 seconds
Started Jun 30 06:21:46 PM PDT 24
Finished Jun 30 06:21:47 PM PDT 24
Peak memory 206192 kb
Host smart-f565cdfe-aa39-4859-a9e5-155a593ae181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30976
4309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.309764309
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1567138626
Short name T1236
Test name
Test status
Simulation time 181075554 ps
CPU time 0.82 seconds
Started Jun 30 06:21:48 PM PDT 24
Finished Jun 30 06:21:50 PM PDT 24
Peak memory 206192 kb
Host smart-6d2690cb-69a5-4e54-832d-b9c208b43022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15671
38626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1567138626
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1507152643
Short name T925
Test name
Test status
Simulation time 153141122 ps
CPU time 0.84 seconds
Started Jun 30 06:21:46 PM PDT 24
Finished Jun 30 06:21:48 PM PDT 24
Peak memory 206200 kb
Host smart-7ea5d97d-1bb7-4986-9426-b682c4390c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15071
52643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1507152643
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.2156561489
Short name T599
Test name
Test status
Simulation time 248917559 ps
CPU time 1.1 seconds
Started Jun 30 06:21:46 PM PDT 24
Finished Jun 30 06:21:48 PM PDT 24
Peak memory 206204 kb
Host smart-13ffca5c-2e63-4e5c-bd0b-50692b6ac801
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2156561489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.2156561489
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3420107866
Short name T818
Test name
Test status
Simulation time 155150154 ps
CPU time 0.79 seconds
Started Jun 30 06:21:45 PM PDT 24
Finished Jun 30 06:21:47 PM PDT 24
Peak memory 206184 kb
Host smart-9cbcd1ec-c492-40d0-a30b-63442ee49dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34201
07866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3420107866
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.4220733699
Short name T848
Test name
Test status
Simulation time 34824189 ps
CPU time 0.66 seconds
Started Jun 30 06:21:49 PM PDT 24
Finished Jun 30 06:21:50 PM PDT 24
Peak memory 206192 kb
Host smart-8fe92fe7-6884-40a8-bbb6-380d367d0cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42207
33699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.4220733699
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2637771370
Short name T269
Test name
Test status
Simulation time 6358400236 ps
CPU time 16.87 seconds
Started Jun 30 06:21:47 PM PDT 24
Finished Jun 30 06:22:05 PM PDT 24
Peak memory 206376 kb
Host smart-2cd1e734-f415-4f57-b4e3-13bb9fbb8bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26377
71370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2637771370
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3301564418
Short name T2497
Test name
Test status
Simulation time 180384188 ps
CPU time 0.85 seconds
Started Jun 30 06:21:50 PM PDT 24
Finished Jun 30 06:21:51 PM PDT 24
Peak memory 206200 kb
Host smart-055ce524-445a-420d-a993-6c7e9c14abc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33015
64418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3301564418
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1081223329
Short name T642
Test name
Test status
Simulation time 164542390 ps
CPU time 0.79 seconds
Started Jun 30 06:21:44 PM PDT 24
Finished Jun 30 06:21:45 PM PDT 24
Peak memory 206340 kb
Host smart-ae6a55b6-7e13-451a-b3c5-c01401648494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10812
23329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1081223329
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1689659014
Short name T2373
Test name
Test status
Simulation time 179544400 ps
CPU time 0.82 seconds
Started Jun 30 06:21:54 PM PDT 24
Finished Jun 30 06:21:57 PM PDT 24
Peak memory 206172 kb
Host smart-ffb657f0-0271-4900-8a7b-644a93879caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16896
59014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1689659014
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3185494993
Short name T2492
Test name
Test status
Simulation time 184239500 ps
CPU time 0.92 seconds
Started Jun 30 06:21:52 PM PDT 24
Finished Jun 30 06:21:53 PM PDT 24
Peak memory 206196 kb
Host smart-07d35386-c1be-4666-9a46-d3dba1e570bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31854
94993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3185494993
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3366449457
Short name T68
Test name
Test status
Simulation time 160448554 ps
CPU time 0.81 seconds
Started Jun 30 06:21:59 PM PDT 24
Finished Jun 30 06:22:00 PM PDT 24
Peak memory 206188 kb
Host smart-89ca656b-ec40-489b-980f-eb807566c937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33664
49457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3366449457
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3819473880
Short name T1574
Test name
Test status
Simulation time 159518132 ps
CPU time 0.75 seconds
Started Jun 30 06:21:52 PM PDT 24
Finished Jun 30 06:21:55 PM PDT 24
Peak memory 206188 kb
Host smart-76adc5be-8103-46c3-b82e-02fb49509e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38194
73880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3819473880
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.473957560
Short name T867
Test name
Test status
Simulation time 158980883 ps
CPU time 0.82 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:56 PM PDT 24
Peak memory 206176 kb
Host smart-d9172a12-5348-480d-875c-415063a2b283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47395
7560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.473957560
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.4156723387
Short name T1163
Test name
Test status
Simulation time 244257525 ps
CPU time 0.94 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206196 kb
Host smart-12a21392-9e80-4b78-8428-98dcaf4cccc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41567
23387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.4156723387
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.771948620
Short name T1423
Test name
Test status
Simulation time 3383201975 ps
CPU time 29.87 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:22:24 PM PDT 24
Peak memory 206376 kb
Host smart-50939bfa-2538-4f5f-8211-11e2629a284c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=771948620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.771948620
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2446360961
Short name T2131
Test name
Test status
Simulation time 207872237 ps
CPU time 0.96 seconds
Started Jun 30 06:21:54 PM PDT 24
Finished Jun 30 06:21:57 PM PDT 24
Peak memory 206196 kb
Host smart-8b175516-d7b2-4660-8137-5b24c3c30e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24463
60961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2446360961
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2023759257
Short name T2164
Test name
Test status
Simulation time 169698968 ps
CPU time 0.84 seconds
Started Jun 30 06:21:52 PM PDT 24
Finished Jun 30 06:21:53 PM PDT 24
Peak memory 206200 kb
Host smart-c96bf545-ccbd-49ad-8f52-5ce7b4cd9b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20237
59257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2023759257
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.2200585093
Short name T1951
Test name
Test status
Simulation time 3502929804 ps
CPU time 31.75 seconds
Started Jun 30 06:21:54 PM PDT 24
Finished Jun 30 06:22:28 PM PDT 24
Peak memory 206372 kb
Host smart-ad193d43-68e7-4067-993e-8c0a98ba70bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22005
85093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2200585093
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1821450038
Short name T2316
Test name
Test status
Simulation time 48419215 ps
CPU time 0.67 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:22:01 PM PDT 24
Peak memory 206188 kb
Host smart-cb8bc19f-45b5-4622-bb7d-ab2f0869008d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1821450038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1821450038
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.64877062
Short name T2575
Test name
Test status
Simulation time 3571148233 ps
CPU time 4.2 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:59 PM PDT 24
Peak memory 206264 kb
Host smart-511f5ee1-e672-40d6-887d-0db041e0f0f8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=64877062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.64877062
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1834691223
Short name T2150
Test name
Test status
Simulation time 13321447323 ps
CPU time 13.75 seconds
Started Jun 30 06:21:50 PM PDT 24
Finished Jun 30 06:22:05 PM PDT 24
Peak memory 206316 kb
Host smart-2ccf226f-8f4c-44c8-89b3-0b7958075396
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1834691223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1834691223
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1752845741
Short name T1355
Test name
Test status
Simulation time 23305448795 ps
CPU time 24.26 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206312 kb
Host smart-4ea4def5-d78d-4055-935b-51a051f08274
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1752845741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1752845741
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1812578654
Short name T2092
Test name
Test status
Simulation time 149523234 ps
CPU time 0.78 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:55 PM PDT 24
Peak memory 206168 kb
Host smart-ed53dc4c-9a22-4f67-b891-0a58e24b1cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18125
78654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1812578654
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.335673044
Short name T2443
Test name
Test status
Simulation time 148135706 ps
CPU time 0.88 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:56 PM PDT 24
Peak memory 206196 kb
Host smart-994c7fd6-ed77-4d4d-83e8-ee41ad26f3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33567
3044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.335673044
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.2371666002
Short name T1294
Test name
Test status
Simulation time 573592198 ps
CPU time 1.61 seconds
Started Jun 30 06:21:58 PM PDT 24
Finished Jun 30 06:22:00 PM PDT 24
Peak memory 206272 kb
Host smart-c8296a75-a97f-4eff-99f2-310971834efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23716
66002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2371666002
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1500839904
Short name T873
Test name
Test status
Simulation time 19822660255 ps
CPU time 41.48 seconds
Started Jun 30 06:21:52 PM PDT 24
Finished Jun 30 06:22:35 PM PDT 24
Peak memory 206384 kb
Host smart-b8913365-d48c-4e09-9d32-3a8f0b278062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15008
39904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1500839904
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.797376980
Short name T2247
Test name
Test status
Simulation time 382339948 ps
CPU time 1.2 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:55 PM PDT 24
Peak memory 206192 kb
Host smart-b035e0bc-8871-4780-97c7-76c398c99268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79737
6980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.797376980
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2965125253
Short name T2524
Test name
Test status
Simulation time 132754559 ps
CPU time 0.74 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206164 kb
Host smart-ce3cbd61-04f1-4589-aa11-86756eddeba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29651
25253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2965125253
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2153386273
Short name T1994
Test name
Test status
Simulation time 39077954 ps
CPU time 0.65 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206172 kb
Host smart-f590f3fd-7acc-4c2b-852b-0325b00ff714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21533
86273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2153386273
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3498477494
Short name T1476
Test name
Test status
Simulation time 944303816 ps
CPU time 2.19 seconds
Started Jun 30 06:21:54 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206360 kb
Host smart-03833004-a7bb-45da-8eaf-39619e648c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34984
77494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3498477494
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3704053653
Short name T717
Test name
Test status
Simulation time 208966774 ps
CPU time 1.88 seconds
Started Jun 30 06:21:52 PM PDT 24
Finished Jun 30 06:21:56 PM PDT 24
Peak memory 206300 kb
Host smart-e52f7850-6734-4d74-bc58-cb7b04f1a71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37040
53653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3704053653
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3228583815
Short name T1213
Test name
Test status
Simulation time 157477159 ps
CPU time 0.78 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206192 kb
Host smart-0d5f5e86-3922-4129-8119-a58e75ac8c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32285
83815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3228583815
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3407692965
Short name T1394
Test name
Test status
Simulation time 210159478 ps
CPU time 0.81 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206184 kb
Host smart-6dfe809c-f6cb-478d-9db5-72d8a0f29dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34076
92965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3407692965
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.751073970
Short name T2436
Test name
Test status
Simulation time 171404406 ps
CPU time 0.83 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:56 PM PDT 24
Peak memory 206152 kb
Host smart-09c52823-3b29-45ea-a353-a3f6a3c9e283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75107
3970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.751073970
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.2865434944
Short name T2048
Test name
Test status
Simulation time 23382990948 ps
CPU time 23.35 seconds
Started Jun 30 06:21:56 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206316 kb
Host smart-aa7a3423-7403-47aa-8810-867b005ca365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28654
34944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.2865434944
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.487173098
Short name T1610
Test name
Test status
Simulation time 3307151770 ps
CPU time 4 seconds
Started Jun 30 06:21:56 PM PDT 24
Finished Jun 30 06:22:02 PM PDT 24
Peak memory 206232 kb
Host smart-ecc9ae4c-35a9-4b82-a154-348e6d209ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48717
3098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.487173098
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2602119815
Short name T1444
Test name
Test status
Simulation time 11773348778 ps
CPU time 83.01 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:23:20 PM PDT 24
Peak memory 206436 kb
Host smart-3f584a82-4806-47b1-a74e-2954115ba601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26021
19815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2602119815
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3643208513
Short name T1782
Test name
Test status
Simulation time 4805636020 ps
CPU time 134.99 seconds
Started Jun 30 06:21:52 PM PDT 24
Finished Jun 30 06:24:09 PM PDT 24
Peak memory 206468 kb
Host smart-477aad45-f372-4969-8a31-eb6f5e40049c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3643208513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3643208513
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1250647287
Short name T2382
Test name
Test status
Simulation time 239196814 ps
CPU time 0.97 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:56 PM PDT 24
Peak memory 206216 kb
Host smart-aa574808-0476-4448-8e66-d7aa9f88bb1b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1250647287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1250647287
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1013544238
Short name T1060
Test name
Test status
Simulation time 192121892 ps
CPU time 0.92 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206192 kb
Host smart-fdd514af-87ad-4d78-a7bc-832b56d1544e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10135
44238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1013544238
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1295862028
Short name T533
Test name
Test status
Simulation time 5562847227 ps
CPU time 151.17 seconds
Started Jun 30 06:21:54 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206456 kb
Host smart-32bf3b00-2189-4a6f-b4c7-2d4151f08cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12958
62028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1295862028
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.3432885767
Short name T2060
Test name
Test status
Simulation time 6328711906 ps
CPU time 201.71 seconds
Started Jun 30 06:21:58 PM PDT 24
Finished Jun 30 06:25:20 PM PDT 24
Peak memory 206452 kb
Host smart-ee94b2cf-af35-4634-a4b9-1c6375e073d0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3432885767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3432885767
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.638017634
Short name T1438
Test name
Test status
Simulation time 175777700 ps
CPU time 0.8 seconds
Started Jun 30 06:21:51 PM PDT 24
Finished Jun 30 06:21:53 PM PDT 24
Peak memory 206180 kb
Host smart-47033783-27df-47a4-bc26-b97e56bb72c4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=638017634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.638017634
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2377623475
Short name T427
Test name
Test status
Simulation time 183412155 ps
CPU time 0.84 seconds
Started Jun 30 06:21:52 PM PDT 24
Finished Jun 30 06:21:54 PM PDT 24
Peak memory 206204 kb
Host smart-80fc5bdd-1ed3-4fbe-8f0a-a380412f97da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776
23475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2377623475
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2948018926
Short name T1272
Test name
Test status
Simulation time 168615041 ps
CPU time 0.83 seconds
Started Jun 30 06:21:54 PM PDT 24
Finished Jun 30 06:21:57 PM PDT 24
Peak memory 206200 kb
Host smart-4c1bf3fe-8a56-48b5-be9e-a0d93d94c605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29480
18926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2948018926
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2394301171
Short name T866
Test name
Test status
Simulation time 170597130 ps
CPU time 0.84 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206176 kb
Host smart-05bcd687-2dc9-469f-933e-3a5442e64f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23943
01171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2394301171
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3406807279
Short name T652
Test name
Test status
Simulation time 167052047 ps
CPU time 0.84 seconds
Started Jun 30 06:21:52 PM PDT 24
Finished Jun 30 06:21:54 PM PDT 24
Peak memory 206204 kb
Host smart-28ccddb8-ab4a-47ca-9c12-bd665c8fee0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34068
07279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3406807279
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.802647990
Short name T2435
Test name
Test status
Simulation time 172215268 ps
CPU time 0.83 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:56 PM PDT 24
Peak memory 206196 kb
Host smart-90bceccb-f99a-41cc-a910-c7fd2b217219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80264
7990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.802647990
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1554681195
Short name T1388
Test name
Test status
Simulation time 198857899 ps
CPU time 0.89 seconds
Started Jun 30 06:21:52 PM PDT 24
Finished Jun 30 06:21:54 PM PDT 24
Peak memory 206200 kb
Host smart-03f599cf-d79f-4824-971a-4da00199c24d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1554681195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1554681195
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1580087456
Short name T1873
Test name
Test status
Simulation time 179133126 ps
CPU time 0.85 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:55 PM PDT 24
Peak memory 206216 kb
Host smart-1761fc69-a066-493f-93a1-a549dbfb5918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15800
87456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1580087456
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2494189463
Short name T2554
Test name
Test status
Simulation time 31981344 ps
CPU time 0.68 seconds
Started Jun 30 06:21:56 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206184 kb
Host smart-b0f157bd-487e-4b62-9cf9-aad666554233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24941
89463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2494189463
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3678570652
Short name T1869
Test name
Test status
Simulation time 20852529533 ps
CPU time 47.67 seconds
Started Jun 30 06:21:58 PM PDT 24
Finished Jun 30 06:22:47 PM PDT 24
Peak memory 206448 kb
Host smart-761bf377-24fa-46b9-9ee7-404b6b6d479d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36785
70652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3678570652
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.4077678440
Short name T2225
Test name
Test status
Simulation time 181128358 ps
CPU time 0.87 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206156 kb
Host smart-7ecb9b95-3754-4c54-9d4a-0e04885a412e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40776
78440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.4077678440
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2649447595
Short name T1349
Test name
Test status
Simulation time 229480117 ps
CPU time 0.88 seconds
Started Jun 30 06:21:53 PM PDT 24
Finished Jun 30 06:21:55 PM PDT 24
Peak memory 206204 kb
Host smart-c88510cb-783c-4142-9ebe-6505a39f580e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26494
47595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2649447595
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.3660830460
Short name T742
Test name
Test status
Simulation time 219034177 ps
CPU time 0.86 seconds
Started Jun 30 06:21:57 PM PDT 24
Finished Jun 30 06:21:59 PM PDT 24
Peak memory 206224 kb
Host smart-73894f6d-3098-4673-b032-eee4acc4ebe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36608
30460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.3660830460
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.615842969
Short name T1853
Test name
Test status
Simulation time 242062735 ps
CPU time 0.86 seconds
Started Jun 30 06:22:02 PM PDT 24
Finished Jun 30 06:22:04 PM PDT 24
Peak memory 206236 kb
Host smart-18e7bcfb-50a8-4831-97c7-d43c6a0a511b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61584
2969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.615842969
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2824348200
Short name T960
Test name
Test status
Simulation time 140259330 ps
CPU time 0.74 seconds
Started Jun 30 06:21:58 PM PDT 24
Finished Jun 30 06:21:59 PM PDT 24
Peak memory 206152 kb
Host smart-d933762e-a981-40a9-8775-25179a21c7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28243
48200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2824348200
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1524921777
Short name T2172
Test name
Test status
Simulation time 151337856 ps
CPU time 0.85 seconds
Started Jun 30 06:22:04 PM PDT 24
Finished Jun 30 06:22:06 PM PDT 24
Peak memory 206172 kb
Host smart-ea100216-bb88-46c1-9605-c6d55551b0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15249
21777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1524921777
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.911779315
Short name T2318
Test name
Test status
Simulation time 141053249 ps
CPU time 0.77 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:22:01 PM PDT 24
Peak memory 206164 kb
Host smart-0cab3496-d764-4329-b5f8-879152a6967c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91177
9315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.911779315
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1739509889
Short name T1067
Test name
Test status
Simulation time 244396246 ps
CPU time 1.02 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:22:02 PM PDT 24
Peak memory 206236 kb
Host smart-d30a2936-3d3c-45c8-9b62-225d34e08040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17395
09889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1739509889
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.4270698620
Short name T508
Test name
Test status
Simulation time 4337617154 ps
CPU time 112.23 seconds
Started Jun 30 06:22:01 PM PDT 24
Finished Jun 30 06:23:54 PM PDT 24
Peak memory 206400 kb
Host smart-a9e71db3-5cd0-4c0e-b40d-c0717221b069
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4270698620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.4270698620
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.117785759
Short name T900
Test name
Test status
Simulation time 194612722 ps
CPU time 0.98 seconds
Started Jun 30 06:22:04 PM PDT 24
Finished Jun 30 06:22:06 PM PDT 24
Peak memory 206200 kb
Host smart-a181ad1b-499b-4cdb-9508-4e24fc395bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11778
5759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.117785759
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2707033253
Short name T409
Test name
Test status
Simulation time 151428691 ps
CPU time 0.82 seconds
Started Jun 30 06:22:03 PM PDT 24
Finished Jun 30 06:22:04 PM PDT 24
Peak memory 206192 kb
Host smart-5c6091d7-c2f0-4ff1-bdbf-deb1a5f98a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27070
33253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2707033253
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.220746426
Short name T1275
Test name
Test status
Simulation time 4774450391 ps
CPU time 43.6 seconds
Started Jun 30 06:22:04 PM PDT 24
Finished Jun 30 06:22:48 PM PDT 24
Peak memory 206468 kb
Host smart-617d4dec-f6ac-481a-ab41-df468e466551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22074
6426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.220746426
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.783806557
Short name T1864
Test name
Test status
Simulation time 45430720 ps
CPU time 0.64 seconds
Started Jun 30 06:22:09 PM PDT 24
Finished Jun 30 06:22:11 PM PDT 24
Peak memory 206180 kb
Host smart-12bd303e-fa58-4e6a-b479-bc5f13181b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=783806557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.783806557
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.4161319248
Short name T244
Test name
Test status
Simulation time 3714106565 ps
CPU time 4.53 seconds
Started Jun 30 06:22:01 PM PDT 24
Finished Jun 30 06:22:07 PM PDT 24
Peak memory 206404 kb
Host smart-fcdb6d50-27f8-4571-9e53-60e1de9084c8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4161319248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.4161319248
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3451907297
Short name T2219
Test name
Test status
Simulation time 13357682601 ps
CPU time 13.25 seconds
Started Jun 30 06:22:01 PM PDT 24
Finished Jun 30 06:22:16 PM PDT 24
Peak memory 206308 kb
Host smart-33bb32df-fc6f-4fa6-a94c-005988c03cd3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3451907297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3451907297
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1386750958
Short name T1191
Test name
Test status
Simulation time 23408736418 ps
CPU time 26.48 seconds
Started Jun 30 06:22:01 PM PDT 24
Finished Jun 30 06:22:29 PM PDT 24
Peak memory 206304 kb
Host smart-ace00b2b-e167-431a-a385-1f202a21e75e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1386750958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.1386750958
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2398581492
Short name T507
Test name
Test status
Simulation time 176634461 ps
CPU time 0.81 seconds
Started Jun 30 06:22:08 PM PDT 24
Finished Jun 30 06:22:10 PM PDT 24
Peak memory 206192 kb
Host smart-ef490aa5-1676-4049-9871-5afe6cf78a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23985
81492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2398581492
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.2751361263
Short name T1663
Test name
Test status
Simulation time 145555358 ps
CPU time 0.79 seconds
Started Jun 30 06:22:02 PM PDT 24
Finished Jun 30 06:22:04 PM PDT 24
Peak memory 206228 kb
Host smart-0f9badb2-407b-4d0e-b4b8-f79269a2fb72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27513
61263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.2751361263
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2236684771
Short name T2227
Test name
Test status
Simulation time 251883706 ps
CPU time 1.12 seconds
Started Jun 30 06:22:02 PM PDT 24
Finished Jun 30 06:22:04 PM PDT 24
Peak memory 206160 kb
Host smart-616e48da-fb3d-4049-b277-4ef91980f381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22366
84771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2236684771
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.156365170
Short name T2326
Test name
Test status
Simulation time 1468169201 ps
CPU time 3.22 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:22:04 PM PDT 24
Peak memory 206332 kb
Host smart-48d85f23-95a5-4de5-8525-f76410367700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15636
5170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.156365170
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1844174949
Short name T106
Test name
Test status
Simulation time 18276940956 ps
CPU time 37.3 seconds
Started Jun 30 06:22:03 PM PDT 24
Finished Jun 30 06:22:41 PM PDT 24
Peak memory 206424 kb
Host smart-1126b00f-398b-4320-8343-8e39c6d4fb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18441
74949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1844174949
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3435527209
Short name T810
Test name
Test status
Simulation time 406275232 ps
CPU time 1.31 seconds
Started Jun 30 06:21:59 PM PDT 24
Finished Jun 30 06:22:01 PM PDT 24
Peak memory 206204 kb
Host smart-97ec77e0-3b4f-45b7-9c77-a6e757b6e7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34355
27209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3435527209
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3708213786
Short name T2306
Test name
Test status
Simulation time 168484345 ps
CPU time 0.83 seconds
Started Jun 30 06:22:04 PM PDT 24
Finished Jun 30 06:22:06 PM PDT 24
Peak memory 206180 kb
Host smart-75766e4a-9c36-4cab-8647-18fd6e78bc5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37082
13786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3708213786
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.4146158366
Short name T1689
Test name
Test status
Simulation time 58819709 ps
CPU time 0.67 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:08 PM PDT 24
Peak memory 204980 kb
Host smart-6a1e13fd-c379-4990-9e49-378e17d4feb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41461
58366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.4146158366
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2066047367
Short name T1212
Test name
Test status
Simulation time 837453871 ps
CPU time 2.05 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:22:03 PM PDT 24
Peak memory 206372 kb
Host smart-2c4c621b-3131-487c-8a36-8dddfdfda783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20660
47367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2066047367
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.497656852
Short name T2370
Test name
Test status
Simulation time 180691394 ps
CPU time 2.07 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:10 PM PDT 24
Peak memory 206320 kb
Host smart-33f38db7-3679-42c8-b171-9e98d5dd6b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49765
6852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.497656852
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2790161630
Short name T1507
Test name
Test status
Simulation time 174404993 ps
CPU time 0.91 seconds
Started Jun 30 06:22:04 PM PDT 24
Finished Jun 30 06:22:06 PM PDT 24
Peak memory 206076 kb
Host smart-356d758c-b520-482b-82ed-6e8822ebae10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27901
61630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2790161630
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3982038548
Short name T1526
Test name
Test status
Simulation time 195741764 ps
CPU time 0.81 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:22:02 PM PDT 24
Peak memory 206196 kb
Host smart-870551cf-8c23-498b-9cbc-2f6e67527163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39820
38548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3982038548
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1178171319
Short name T1339
Test name
Test status
Simulation time 213043162 ps
CPU time 0.99 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:22:02 PM PDT 24
Peak memory 206208 kb
Host smart-d05b0ee0-ac19-4779-926a-cc4fca550044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11781
71319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1178171319
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.2256249530
Short name T1506
Test name
Test status
Simulation time 11030025769 ps
CPU time 102.47 seconds
Started Jun 30 06:22:01 PM PDT 24
Finished Jun 30 06:23:45 PM PDT 24
Peak memory 206440 kb
Host smart-1047c83e-79c4-4734-82bf-7c1d0a159236
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2256249530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.2256249530
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3557860698
Short name T1861
Test name
Test status
Simulation time 185430915 ps
CPU time 0.83 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:22:02 PM PDT 24
Peak memory 206184 kb
Host smart-11fbfbab-709d-43fd-ad53-b969ec9447a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35578
60698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3557860698
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2639679439
Short name T812
Test name
Test status
Simulation time 23372553519 ps
CPU time 28.37 seconds
Started Jun 30 06:22:08 PM PDT 24
Finished Jun 30 06:22:38 PM PDT 24
Peak memory 206304 kb
Host smart-ef0f27e4-c917-497c-a28c-979d899f4bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26396
79439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2639679439
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2231680969
Short name T946
Test name
Test status
Simulation time 3310955322 ps
CPU time 3.78 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:22:05 PM PDT 24
Peak memory 206248 kb
Host smart-35de214c-6be4-4b33-b174-3cd768a24ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22316
80969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2231680969
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.1502337028
Short name T2020
Test name
Test status
Simulation time 9026117076 ps
CPU time 86.02 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:23:28 PM PDT 24
Peak memory 206420 kb
Host smart-889ee90a-d9ad-4228-b663-7d8859e26883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15023
37028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1502337028
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3288813659
Short name T700
Test name
Test status
Simulation time 3693222626 ps
CPU time 34.37 seconds
Started Jun 30 06:21:59 PM PDT 24
Finished Jun 30 06:22:34 PM PDT 24
Peak memory 206484 kb
Host smart-25b84de4-cc70-4b2d-8d36-71c68694233b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3288813659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3288813659
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.4220485406
Short name T387
Test name
Test status
Simulation time 240354031 ps
CPU time 0.92 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:08 PM PDT 24
Peak memory 205024 kb
Host smart-0b909c69-7c13-46a6-8bb8-c5ea52152957
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4220485406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.4220485406
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1385151788
Short name T2354
Test name
Test status
Simulation time 187952402 ps
CPU time 0.86 seconds
Started Jun 30 06:22:01 PM PDT 24
Finished Jun 30 06:22:03 PM PDT 24
Peak memory 206128 kb
Host smart-9a37b651-fd52-4ab5-a436-2302bc9c7d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13851
51788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1385151788
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.4204128537
Short name T1450
Test name
Test status
Simulation time 5386429597 ps
CPU time 39.91 seconds
Started Jun 30 06:21:59 PM PDT 24
Finished Jun 30 06:22:40 PM PDT 24
Peak memory 206428 kb
Host smart-545379a3-be76-41b8-b95f-dfc19ca253be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42041
28537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.4204128537
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1970009313
Short name T462
Test name
Test status
Simulation time 7636754372 ps
CPU time 52.54 seconds
Started Jun 30 06:21:58 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 206420 kb
Host smart-759c8f87-73a8-4d84-896b-3f23cdff53ab
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1970009313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1970009313
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3982271114
Short name T1639
Test name
Test status
Simulation time 147227148 ps
CPU time 0.87 seconds
Started Jun 30 06:22:00 PM PDT 24
Finished Jun 30 06:22:02 PM PDT 24
Peak memory 206172 kb
Host smart-06b323b4-870c-48e1-a850-9df9479c568f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3982271114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3982271114
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1112501303
Short name T1661
Test name
Test status
Simulation time 176262728 ps
CPU time 0.85 seconds
Started Jun 30 06:22:03 PM PDT 24
Finished Jun 30 06:22:04 PM PDT 24
Peak memory 206200 kb
Host smart-a51b2787-b867-4ee7-8b06-0aac84de93bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11125
01303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1112501303
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3065607336
Short name T1054
Test name
Test status
Simulation time 216912382 ps
CPU time 0.87 seconds
Started Jun 30 06:22:02 PM PDT 24
Finished Jun 30 06:22:04 PM PDT 24
Peak memory 206160 kb
Host smart-70e3484b-303a-4a4c-b193-cfd08fbef818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30656
07336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3065607336
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1774215546
Short name T1669
Test name
Test status
Simulation time 169172841 ps
CPU time 0.8 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:08 PM PDT 24
Peak memory 206084 kb
Host smart-c92e4d1d-5415-473a-989c-c00573cb0fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17742
15546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1774215546
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1547660577
Short name T389
Test name
Test status
Simulation time 162355075 ps
CPU time 0.75 seconds
Started Jun 30 06:22:08 PM PDT 24
Finished Jun 30 06:22:11 PM PDT 24
Peak memory 206200 kb
Host smart-2edd38ae-1640-478e-87aa-5415b0662a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15476
60577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1547660577
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1737822195
Short name T1061
Test name
Test status
Simulation time 158975760 ps
CPU time 0.77 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:08 PM PDT 24
Peak memory 206208 kb
Host smart-89932aa3-974e-4485-8f8e-250b931c4856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17378
22195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1737822195
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.1883866551
Short name T1431
Test name
Test status
Simulation time 242919930 ps
CPU time 0.95 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:09 PM PDT 24
Peak memory 206196 kb
Host smart-0e9cd3b0-8cfc-451b-bc9e-5b204ef55247
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1883866551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.1883866551
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1349516264
Short name T1333
Test name
Test status
Simulation time 180780381 ps
CPU time 0.8 seconds
Started Jun 30 06:22:09 PM PDT 24
Finished Jun 30 06:22:11 PM PDT 24
Peak memory 206188 kb
Host smart-ff4ecf33-e59b-46d3-ad86-9b3509687e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13495
16264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1349516264
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2981336048
Short name T1096
Test name
Test status
Simulation time 167920923 ps
CPU time 0.84 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:08 PM PDT 24
Peak memory 206168 kb
Host smart-df33038f-2a72-418d-b6d6-1895e39c3cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29813
36048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2981336048
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1218363532
Short name T2079
Test name
Test status
Simulation time 222358265 ps
CPU time 0.91 seconds
Started Jun 30 06:22:08 PM PDT 24
Finished Jun 30 06:22:11 PM PDT 24
Peak memory 206212 kb
Host smart-43647d27-507f-4d7f-bd97-9f53fbd2d056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12183
63532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1218363532
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.143456945
Short name T365
Test name
Test status
Simulation time 247981260 ps
CPU time 1 seconds
Started Jun 30 06:22:05 PM PDT 24
Finished Jun 30 06:22:07 PM PDT 24
Peak memory 206216 kb
Host smart-ad53681e-08af-4020-81bb-3c10f1f9a82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14345
6945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.143456945
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.4083029256
Short name T1594
Test name
Test status
Simulation time 189082717 ps
CPU time 0.88 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:08 PM PDT 24
Peak memory 206188 kb
Host smart-492acea7-4a07-437a-b612-9d6e3538aaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40830
29256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.4083029256
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.887826858
Short name T2628
Test name
Test status
Simulation time 188200937 ps
CPU time 0.86 seconds
Started Jun 30 06:22:07 PM PDT 24
Finished Jun 30 06:22:09 PM PDT 24
Peak memory 206180 kb
Host smart-78371773-3c95-4d75-be3d-11d55ffb6de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88782
6858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.887826858
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3099026655
Short name T2320
Test name
Test status
Simulation time 206603402 ps
CPU time 0.84 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:09 PM PDT 24
Peak memory 206180 kb
Host smart-55f9ce06-5797-444e-aea3-e24b86e6f650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30990
26655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3099026655
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3674052088
Short name T1623
Test name
Test status
Simulation time 149704902 ps
CPU time 0.8 seconds
Started Jun 30 06:22:05 PM PDT 24
Finished Jun 30 06:22:06 PM PDT 24
Peak memory 206168 kb
Host smart-65821cab-03f7-4723-9b25-eb31ec0f9b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
52088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3674052088
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2358071660
Short name T737
Test name
Test status
Simulation time 221045797 ps
CPU time 0.9 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:08 PM PDT 24
Peak memory 206212 kb
Host smart-b841e4c5-c0f1-402b-b2d4-7c7abacf3820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23580
71660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2358071660
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.4136199102
Short name T1120
Test name
Test status
Simulation time 3664102130 ps
CPU time 35.01 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206432 kb
Host smart-e51a523a-7802-46aa-afae-3275e6500dbc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4136199102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.4136199102
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.34487025
Short name T1231
Test name
Test status
Simulation time 166455724 ps
CPU time 0.83 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:09 PM PDT 24
Peak memory 206192 kb
Host smart-80a9ec95-de1e-4bc7-8513-f43aa0342dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34487
025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.34487025
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1330542106
Short name T1181
Test name
Test status
Simulation time 191850879 ps
CPU time 0.88 seconds
Started Jun 30 06:22:04 PM PDT 24
Finished Jun 30 06:22:06 PM PDT 24
Peak memory 206192 kb
Host smart-e5c7e674-192c-4d39-91b2-e93700e9c363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13305
42106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1330542106
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.4057605681
Short name T2532
Test name
Test status
Simulation time 5938595309 ps
CPU time 44.19 seconds
Started Jun 30 06:22:09 PM PDT 24
Finished Jun 30 06:22:54 PM PDT 24
Peak memory 206428 kb
Host smart-2c67e0fe-42c5-420d-bc61-f17feb22ee9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40576
05681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.4057605681
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.1237236508
Short name T1992
Test name
Test status
Simulation time 27017991 ps
CPU time 0.66 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206200 kb
Host smart-dddf0339-0784-4f6b-86bb-d0dee7dd0e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1237236508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1237236508
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2403625871
Short name T982
Test name
Test status
Simulation time 4182625128 ps
CPU time 4.72 seconds
Started Jun 30 06:22:08 PM PDT 24
Finished Jun 30 06:22:14 PM PDT 24
Peak memory 206252 kb
Host smart-63e089f8-3504-4ca0-9379-c9592a836eab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2403625871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2403625871
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3831998108
Short name T1499
Test name
Test status
Simulation time 13410155074 ps
CPU time 12.35 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:20 PM PDT 24
Peak memory 206308 kb
Host smart-04773c67-a5b5-44c5-a927-337b160a0597
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3831998108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3831998108
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1863137642
Short name T1578
Test name
Test status
Simulation time 23334578458 ps
CPU time 22.94 seconds
Started Jun 30 06:22:09 PM PDT 24
Finished Jun 30 06:22:33 PM PDT 24
Peak memory 206300 kb
Host smart-e15ccd12-8b1c-4881-9d77-d4f139b71122
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1863137642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.1863137642
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3197578150
Short name T922
Test name
Test status
Simulation time 150884342 ps
CPU time 0.84 seconds
Started Jun 30 06:22:08 PM PDT 24
Finished Jun 30 06:22:11 PM PDT 24
Peak memory 206200 kb
Host smart-638ca15c-ea01-4565-95ab-f9d8271c2625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31975
78150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3197578150
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.4113234553
Short name T887
Test name
Test status
Simulation time 146480786 ps
CPU time 0.75 seconds
Started Jun 30 06:22:09 PM PDT 24
Finished Jun 30 06:22:11 PM PDT 24
Peak memory 206144 kb
Host smart-c1f3c5e6-c889-41cb-ae89-bdb392778caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41132
34553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.4113234553
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3948744636
Short name T167
Test name
Test status
Simulation time 333128330 ps
CPU time 1.14 seconds
Started Jun 30 06:22:09 PM PDT 24
Finished Jun 30 06:22:12 PM PDT 24
Peak memory 206184 kb
Host smart-af516a3a-7880-4294-8efb-481f59c3dc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
44636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3948744636
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.3828205897
Short name T2211
Test name
Test status
Simulation time 360790795 ps
CPU time 1.22 seconds
Started Jun 30 06:22:07 PM PDT 24
Finished Jun 30 06:22:10 PM PDT 24
Peak memory 206176 kb
Host smart-8a31fa0b-9090-4403-ac8c-c31bcab72d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38282
05897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.3828205897
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2469507133
Short name T2297
Test name
Test status
Simulation time 140178589 ps
CPU time 0.76 seconds
Started Jun 30 06:22:06 PM PDT 24
Finished Jun 30 06:22:09 PM PDT 24
Peak memory 206184 kb
Host smart-0e43e484-c48b-42b0-b45f-4d4c100f9b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24695
07133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2469507133
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.262642721
Short name T1412
Test name
Test status
Simulation time 53230731 ps
CPU time 0.66 seconds
Started Jun 30 06:22:08 PM PDT 24
Finished Jun 30 06:22:10 PM PDT 24
Peak memory 206172 kb
Host smart-fc4e0d7d-b71d-4da4-973b-247d90592edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26264
2721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.262642721
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.3645332764
Short name T86
Test name
Test status
Simulation time 1063147748 ps
CPU time 2.41 seconds
Started Jun 30 06:22:05 PM PDT 24
Finished Jun 30 06:22:08 PM PDT 24
Peak memory 206340 kb
Host smart-4764a9a2-f11b-4914-86a3-e89b7b3d7239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36453
32764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.3645332764
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1161622897
Short name T727
Test name
Test status
Simulation time 412271983 ps
CPU time 2.51 seconds
Started Jun 30 06:22:10 PM PDT 24
Finished Jun 30 06:22:14 PM PDT 24
Peak memory 206272 kb
Host smart-2dc662ab-2b92-43b2-aab0-7534b246bbfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11616
22897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1161622897
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2632269684
Short name T595
Test name
Test status
Simulation time 205959319 ps
CPU time 0.82 seconds
Started Jun 30 06:22:09 PM PDT 24
Finished Jun 30 06:22:11 PM PDT 24
Peak memory 206172 kb
Host smart-54aedc94-a31f-4d32-beff-29bef91835ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26322
69684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2632269684
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1941981909
Short name T751
Test name
Test status
Simulation time 149578603 ps
CPU time 0.8 seconds
Started Jun 30 06:22:09 PM PDT 24
Finished Jun 30 06:22:11 PM PDT 24
Peak memory 206208 kb
Host smart-8871a674-a47a-4dab-852e-593dfbbc4b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19419
81909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1941981909
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.45370162
Short name T589
Test name
Test status
Simulation time 212846669 ps
CPU time 0.89 seconds
Started Jun 30 06:22:07 PM PDT 24
Finished Jun 30 06:22:09 PM PDT 24
Peak memory 206204 kb
Host smart-91d242c8-9aa1-40f1-8859-fcf72ab9b3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45370
162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.45370162
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2021927788
Short name T355
Test name
Test status
Simulation time 259438687 ps
CPU time 0.99 seconds
Started Jun 30 06:22:07 PM PDT 24
Finished Jun 30 06:22:10 PM PDT 24
Peak memory 206172 kb
Host smart-541ad3e1-27c7-4dd1-82fe-71d8022276b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20219
27788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2021927788
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3821721793
Short name T1937
Test name
Test status
Simulation time 23364522057 ps
CPU time 24.46 seconds
Started Jun 30 06:22:11 PM PDT 24
Finished Jun 30 06:22:36 PM PDT 24
Peak memory 206304 kb
Host smart-4866b90f-3cd6-44da-b3fe-84f27c518dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38217
21793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3821721793
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.4211146370
Short name T447
Test name
Test status
Simulation time 3289673483 ps
CPU time 4.14 seconds
Started Jun 30 06:22:13 PM PDT 24
Finished Jun 30 06:22:17 PM PDT 24
Peak memory 206272 kb
Host smart-204471d3-39f6-447f-89fb-774f587244fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42111
46370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.4211146370
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2797029788
Short name T1528
Test name
Test status
Simulation time 8981689486 ps
CPU time 87.91 seconds
Started Jun 30 06:22:12 PM PDT 24
Finished Jun 30 06:23:40 PM PDT 24
Peak memory 206468 kb
Host smart-7dd6be59-88ae-4e3a-bc6c-9a7121015e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27970
29788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2797029788
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.2676418991
Short name T857
Test name
Test status
Simulation time 5135787688 ps
CPU time 38.42 seconds
Started Jun 30 06:22:13 PM PDT 24
Finished Jun 30 06:22:52 PM PDT 24
Peak memory 206488 kb
Host smart-7001dd4e-9bcb-42b5-83c8-93cc07da795b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2676418991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.2676418991
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.810531174
Short name T2039
Test name
Test status
Simulation time 236472186 ps
CPU time 0.92 seconds
Started Jun 30 06:22:16 PM PDT 24
Finished Jun 30 06:22:17 PM PDT 24
Peak memory 206204 kb
Host smart-19e1151c-2bb2-4705-bf01-18e08fb14a61
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=810531174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.810531174
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2215042265
Short name T1642
Test name
Test status
Simulation time 199010706 ps
CPU time 0.89 seconds
Started Jun 30 06:22:13 PM PDT 24
Finished Jun 30 06:22:15 PM PDT 24
Peak memory 206188 kb
Host smart-b6a37778-409f-42c6-a29c-a80362d7c605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22150
42265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2215042265
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1372895038
Short name T1463
Test name
Test status
Simulation time 3072394086 ps
CPU time 29.81 seconds
Started Jun 30 06:22:13 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206488 kb
Host smart-1a732d30-3223-4c64-8c81-90c13be81050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13728
95038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1372895038
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.2048200761
Short name T1943
Test name
Test status
Simulation time 6797765296 ps
CPU time 50.28 seconds
Started Jun 30 06:22:17 PM PDT 24
Finished Jun 30 06:23:07 PM PDT 24
Peak memory 206656 kb
Host smart-87c260bb-1b21-4500-b540-ff58839597c5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2048200761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.2048200761
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2078684509
Short name T2465
Test name
Test status
Simulation time 150231422 ps
CPU time 0.81 seconds
Started Jun 30 06:22:13 PM PDT 24
Finished Jun 30 06:22:14 PM PDT 24
Peak memory 206212 kb
Host smart-eab063f4-a853-4387-a7ad-500dd1a54d2f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2078684509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2078684509
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2757862352
Short name T1679
Test name
Test status
Simulation time 185345249 ps
CPU time 0.84 seconds
Started Jun 30 06:22:14 PM PDT 24
Finished Jun 30 06:22:15 PM PDT 24
Peak memory 206152 kb
Host smart-b473835d-8496-4371-9b3d-aedd364efce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27578
62352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2757862352
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.3091658586
Short name T2214
Test name
Test status
Simulation time 158779973 ps
CPU time 0.82 seconds
Started Jun 30 06:22:14 PM PDT 24
Finished Jun 30 06:22:16 PM PDT 24
Peak memory 206180 kb
Host smart-3eb5147f-eee8-4871-ae86-f585f9f2a82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30916
58586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3091658586
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1819273528
Short name T2352
Test name
Test status
Simulation time 179565894 ps
CPU time 0.85 seconds
Started Jun 30 06:22:16 PM PDT 24
Finished Jun 30 06:22:17 PM PDT 24
Peak memory 206348 kb
Host smart-6b74800f-19c6-4aa6-a36c-a1721049fbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18192
73528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1819273528
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2730234326
Short name T1557
Test name
Test status
Simulation time 165663941 ps
CPU time 0.78 seconds
Started Jun 30 06:22:11 PM PDT 24
Finished Jun 30 06:22:12 PM PDT 24
Peak memory 206208 kb
Host smart-a7c38084-ae98-4d29-9c39-8e7909fb95ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27302
34326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2730234326
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1946024984
Short name T1807
Test name
Test status
Simulation time 149104951 ps
CPU time 0.78 seconds
Started Jun 30 06:22:11 PM PDT 24
Finished Jun 30 06:22:12 PM PDT 24
Peak memory 206196 kb
Host smart-64f6ee73-96cd-4cc5-9143-a5cb8af15828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19460
24984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1946024984
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3705375576
Short name T580
Test name
Test status
Simulation time 242821101 ps
CPU time 1.02 seconds
Started Jun 30 06:22:15 PM PDT 24
Finished Jun 30 06:22:16 PM PDT 24
Peak memory 206180 kb
Host smart-9abc7596-01f4-449f-8e44-8fe8a860f741
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3705375576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3705375576
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1168649293
Short name T991
Test name
Test status
Simulation time 157759159 ps
CPU time 0.75 seconds
Started Jun 30 06:22:14 PM PDT 24
Finished Jun 30 06:22:15 PM PDT 24
Peak memory 206148 kb
Host smart-a05b1df3-d176-43b8-88fa-71bb118b3167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11686
49293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1168649293
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2539909797
Short name T1695
Test name
Test status
Simulation time 45150472 ps
CPU time 0.69 seconds
Started Jun 30 06:22:14 PM PDT 24
Finished Jun 30 06:22:15 PM PDT 24
Peak memory 206392 kb
Host smart-daf5834d-cd71-4258-b0de-46a35ee5dfb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25399
09797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2539909797
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3602026033
Short name T2481
Test name
Test status
Simulation time 7664373494 ps
CPU time 16.61 seconds
Started Jun 30 06:22:14 PM PDT 24
Finished Jun 30 06:22:32 PM PDT 24
Peak memory 206416 kb
Host smart-385540ce-472b-45a5-a39f-2155fbcf4cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36020
26033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3602026033
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1039551094
Short name T313
Test name
Test status
Simulation time 190652584 ps
CPU time 0.86 seconds
Started Jun 30 06:22:12 PM PDT 24
Finished Jun 30 06:22:13 PM PDT 24
Peak memory 206188 kb
Host smart-409ffb40-2915-4b2b-b1d1-bc5bf9a74eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10395
51094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1039551094
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.502058490
Short name T1384
Test name
Test status
Simulation time 237651914 ps
CPU time 1.01 seconds
Started Jun 30 06:22:15 PM PDT 24
Finished Jun 30 06:22:17 PM PDT 24
Peak memory 206176 kb
Host smart-f2412e57-8b56-42b7-87d4-61983b759432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50205
8490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.502058490
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.3267036210
Short name T2494
Test name
Test status
Simulation time 234185929 ps
CPU time 0.9 seconds
Started Jun 30 06:22:10 PM PDT 24
Finished Jun 30 06:22:12 PM PDT 24
Peak memory 206220 kb
Host smart-8b06bf63-3d16-4780-9f36-21b1cd154b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32670
36210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.3267036210
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.949960760
Short name T1613
Test name
Test status
Simulation time 181791893 ps
CPU time 0.82 seconds
Started Jun 30 06:22:11 PM PDT 24
Finished Jun 30 06:22:12 PM PDT 24
Peak memory 206192 kb
Host smart-b97831bd-e377-4f7f-b188-a9d44ef1a69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94996
0760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.949960760
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.541920272
Short name T2177
Test name
Test status
Simulation time 158673127 ps
CPU time 0.78 seconds
Started Jun 30 06:22:12 PM PDT 24
Finished Jun 30 06:22:14 PM PDT 24
Peak memory 206184 kb
Host smart-cf739d83-dfe0-4ec7-9479-6e7eba4e882e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54192
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.541920272
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.667238034
Short name T1831
Test name
Test status
Simulation time 155298119 ps
CPU time 0.78 seconds
Started Jun 30 06:22:14 PM PDT 24
Finished Jun 30 06:22:16 PM PDT 24
Peak memory 206176 kb
Host smart-950a0d89-2e62-4698-b31c-20dbf514ac6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66723
8034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.667238034
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1590908395
Short name T406
Test name
Test status
Simulation time 149610239 ps
CPU time 0.77 seconds
Started Jun 30 06:22:15 PM PDT 24
Finished Jun 30 06:22:16 PM PDT 24
Peak memory 206176 kb
Host smart-56438059-573d-4404-b928-d409f437a2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15909
08395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1590908395
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1597109583
Short name T689
Test name
Test status
Simulation time 247371457 ps
CPU time 0.98 seconds
Started Jun 30 06:22:14 PM PDT 24
Finished Jun 30 06:22:15 PM PDT 24
Peak memory 206164 kb
Host smart-9571053d-c7ae-4658-9441-34ead18bdeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15971
09583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1597109583
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.4095880175
Short name T2168
Test name
Test status
Simulation time 5533494329 ps
CPU time 155.54 seconds
Started Jun 30 06:22:11 PM PDT 24
Finished Jun 30 06:24:47 PM PDT 24
Peak memory 206472 kb
Host smart-4fdcf7d2-b2b0-4d37-9921-d285dacab88b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4095880175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.4095880175
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1566471756
Short name T1913
Test name
Test status
Simulation time 180121755 ps
CPU time 0.84 seconds
Started Jun 30 06:22:13 PM PDT 24
Finished Jun 30 06:22:14 PM PDT 24
Peak memory 206400 kb
Host smart-d5b8bcff-ffe1-451a-8520-1a17d19c3843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15664
71756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1566471756
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.260105690
Short name T2388
Test name
Test status
Simulation time 221979250 ps
CPU time 0.86 seconds
Started Jun 30 06:22:15 PM PDT 24
Finished Jun 30 06:22:16 PM PDT 24
Peak memory 206148 kb
Host smart-9e82dd60-883e-4d86-8fda-aa1606d8596f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26010
5690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.260105690
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2824361973
Short name T1148
Test name
Test status
Simulation time 5659499410 ps
CPU time 50.49 seconds
Started Jun 30 06:22:18 PM PDT 24
Finished Jun 30 06:23:09 PM PDT 24
Peak memory 206344 kb
Host smart-e0c121d8-41e7-4bd1-bd5a-90eb7cc1dd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28243
61973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2824361973
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.3188291931
Short name T1013
Test name
Test status
Simulation time 48328624 ps
CPU time 0.67 seconds
Started Jun 30 06:22:24 PM PDT 24
Finished Jun 30 06:22:26 PM PDT 24
Peak memory 206208 kb
Host smart-fd42b22d-bcd2-4c22-a2b9-ab01aea21304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3188291931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.3188291931
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.418133227
Short name T1300
Test name
Test status
Simulation time 3801984560 ps
CPU time 4.75 seconds
Started Jun 30 06:22:18 PM PDT 24
Finished Jun 30 06:22:23 PM PDT 24
Peak memory 206280 kb
Host smart-7dc8e0d8-2dbf-426c-ba27-826133d155ca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=418133227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.418133227
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2045682544
Short name T2549
Test name
Test status
Simulation time 13366986622 ps
CPU time 14.39 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:34 PM PDT 24
Peak memory 206480 kb
Host smart-e9a7e1d7-5f5a-4bed-a160-3b19ac65d05b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2045682544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2045682544
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.771896175
Short name T1159
Test name
Test status
Simulation time 23366661320 ps
CPU time 23.55 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206452 kb
Host smart-95865297-666c-4de2-903e-3397b37b1c7d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=771896175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.771896175
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2790009472
Short name T1460
Test name
Test status
Simulation time 231528596 ps
CPU time 0.91 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206180 kb
Host smart-94dc8696-d2c5-49c8-b5fd-af84a480e62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27900
09472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2790009472
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.1812833370
Short name T611
Test name
Test status
Simulation time 185462629 ps
CPU time 0.82 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:22:22 PM PDT 24
Peak memory 206192 kb
Host smart-bd6856e6-6240-4949-b817-69af443b555f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128
33370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.1812833370
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1822164776
Short name T31
Test name
Test status
Simulation time 384047232 ps
CPU time 1.32 seconds
Started Jun 30 06:22:18 PM PDT 24
Finished Jun 30 06:22:20 PM PDT 24
Peak memory 206196 kb
Host smart-1ccf3f83-73d8-4f69-ae3d-8b7359c1df1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18221
64776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1822164776
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.979741072
Short name T105
Test name
Test status
Simulation time 640374976 ps
CPU time 1.77 seconds
Started Jun 30 06:22:22 PM PDT 24
Finished Jun 30 06:22:24 PM PDT 24
Peak memory 206244 kb
Host smart-953c68ea-becd-4589-b1a6-7bdc0c57d565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97974
1072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.979741072
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.3045880325
Short name T1495
Test name
Test status
Simulation time 9587961271 ps
CPU time 18.65 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:38 PM PDT 24
Peak memory 206484 kb
Host smart-d8d6580e-722e-4631-93dc-dd16bb93e1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30458
80325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3045880325
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3892586870
Short name T490
Test name
Test status
Simulation time 382533426 ps
CPU time 1.3 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:22:22 PM PDT 24
Peak memory 206192 kb
Host smart-0bb66db1-37db-40b3-834d-52e1bbe31de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38925
86870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3892586870
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.1632942032
Short name T782
Test name
Test status
Simulation time 164331126 ps
CPU time 0.81 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:22:22 PM PDT 24
Peak memory 206188 kb
Host smart-1c46ef5e-2e2d-4315-93ff-d10c27b5c357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16329
42032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.1632942032
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2537185701
Short name T1219
Test name
Test status
Simulation time 46711610 ps
CPU time 0.69 seconds
Started Jun 30 06:22:18 PM PDT 24
Finished Jun 30 06:22:19 PM PDT 24
Peak memory 206192 kb
Host smart-ad01ee95-4299-4b6b-a05c-040ec48470e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25371
85701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2537185701
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.2595843095
Short name T1352
Test name
Test status
Simulation time 1099931167 ps
CPU time 2.46 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:22 PM PDT 24
Peak memory 206292 kb
Host smart-0318e458-af6c-4500-964c-5a8dc2a3dbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25958
43095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.2595843095
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.152139090
Short name T1131
Test name
Test status
Simulation time 173183585 ps
CPU time 1.81 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206384 kb
Host smart-a9de9cd6-8997-4aff-93fe-ecd9b36d78f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15213
9090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.152139090
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.915390959
Short name T941
Test name
Test status
Simulation time 196144251 ps
CPU time 0.87 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:22:22 PM PDT 24
Peak memory 206180 kb
Host smart-49efc6f0-4c77-46e3-910c-478ebf2409ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91539
0959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.915390959
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2791347604
Short name T2356
Test name
Test status
Simulation time 135224035 ps
CPU time 0.8 seconds
Started Jun 30 06:22:22 PM PDT 24
Finished Jun 30 06:22:23 PM PDT 24
Peak memory 206208 kb
Host smart-b972faf8-81d5-4b50-967b-04c22bfe6ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27913
47604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2791347604
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1044204381
Short name T2132
Test name
Test status
Simulation time 215922118 ps
CPU time 0.94 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206208 kb
Host smart-606e2489-9dcf-45b7-ab63-620a8f29bc96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10442
04381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1044204381
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.2606667073
Short name T100
Test name
Test status
Simulation time 6497984337 ps
CPU time 44.78 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206460 kb
Host smart-d55a61ee-9566-4cf3-9cdb-3b8368ceac51
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2606667073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.2606667073
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3924557214
Short name T1968
Test name
Test status
Simulation time 207800167 ps
CPU time 0.88 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:22:22 PM PDT 24
Peak memory 206008 kb
Host smart-c096d4af-dcc0-4046-8a13-2b3081f2a37d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39245
57214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3924557214
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.2794791730
Short name T2391
Test name
Test status
Simulation time 23289229530 ps
CPU time 20.64 seconds
Started Jun 30 06:22:22 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206312 kb
Host smart-eadd5c77-601b-40d5-a8ed-56442c1d4011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27947
91730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2794791730
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3331846733
Short name T2138
Test name
Test status
Simulation time 3295500112 ps
CPU time 3.9 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:22:25 PM PDT 24
Peak memory 206252 kb
Host smart-d0a998cc-1703-4865-9901-68d433c56264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33318
46733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3331846733
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.1752709860
Short name T986
Test name
Test status
Simulation time 13359922837 ps
CPU time 370.08 seconds
Started Jun 30 06:22:33 PM PDT 24
Finished Jun 30 06:28:44 PM PDT 24
Peak memory 206444 kb
Host smart-328f902d-cdfd-44d4-a5a3-792bfc731c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17527
09860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.1752709860
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.4001162217
Short name T2027
Test name
Test status
Simulation time 4889386684 ps
CPU time 136.12 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:24:36 PM PDT 24
Peak memory 206380 kb
Host smart-b502de34-3a0e-4622-a969-8e7ffe139e1f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4001162217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.4001162217
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.266646818
Short name T484
Test name
Test status
Simulation time 239228838 ps
CPU time 0.89 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:22:22 PM PDT 24
Peak memory 206236 kb
Host smart-807b14bb-7681-4b3c-b0b1-f5f8f30b6908
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=266646818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.266646818
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.24764663
Short name T1070
Test name
Test status
Simulation time 193100666 ps
CPU time 0.85 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206204 kb
Host smart-c43e84d7-d006-43c2-b2d1-4dc8a8288be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24764
663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.24764663
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.307846602
Short name T1931
Test name
Test status
Simulation time 3948873911 ps
CPU time 107.88 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:24:09 PM PDT 24
Peak memory 206448 kb
Host smart-2a6fc87e-55e2-44f7-bec2-ac072c355adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30784
6602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.307846602
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.1369017223
Short name T2389
Test name
Test status
Simulation time 6156314305 ps
CPU time 169.38 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:25:11 PM PDT 24
Peak memory 206448 kb
Host smart-d84a640c-09ab-41bb-8dbe-572dbcf1e5fc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1369017223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.1369017223
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3112571939
Short name T721
Test name
Test status
Simulation time 172722419 ps
CPU time 0.85 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206212 kb
Host smart-01e5bd7c-9c76-4977-be6e-127a0df828c7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3112571939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3112571939
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3855821163
Short name T2416
Test name
Test status
Simulation time 139001454 ps
CPU time 0.72 seconds
Started Jun 30 06:22:16 PM PDT 24
Finished Jun 30 06:22:18 PM PDT 24
Peak memory 206196 kb
Host smart-ccb375f1-25a0-4b77-83d4-e6e224a90774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38558
21163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3855821163
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3601783127
Short name T135
Test name
Test status
Simulation time 216287662 ps
CPU time 0.88 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:22:22 PM PDT 24
Peak memory 206200 kb
Host smart-407bbe6e-295c-4877-b389-16e3a37de408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36017
83127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3601783127
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.444540293
Short name T1190
Test name
Test status
Simulation time 229468120 ps
CPU time 0.86 seconds
Started Jun 30 06:22:20 PM PDT 24
Finished Jun 30 06:22:22 PM PDT 24
Peak memory 206204 kb
Host smart-0d5613b1-2bf4-4542-92f0-07ae1b2976cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44454
0293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.444540293
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1831496167
Short name T2058
Test name
Test status
Simulation time 243979692 ps
CPU time 0.81 seconds
Started Jun 30 06:22:18 PM PDT 24
Finished Jun 30 06:22:19 PM PDT 24
Peak memory 206160 kb
Host smart-315d5cef-da06-4ffa-9924-953ba9c6afb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18314
96167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1831496167
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1529651161
Short name T1778
Test name
Test status
Simulation time 179301589 ps
CPU time 0.85 seconds
Started Jun 30 06:22:17 PM PDT 24
Finished Jun 30 06:22:18 PM PDT 24
Peak memory 206200 kb
Host smart-a03401df-7ce1-41c3-8831-5191a2a0db14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15296
51161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1529651161
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2811015972
Short name T2610
Test name
Test status
Simulation time 147051046 ps
CPU time 0.84 seconds
Started Jun 30 06:22:19 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206244 kb
Host smart-e8fb92ff-6884-4b0f-8ede-78403125ba9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28110
15972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2811015972
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.483189305
Short name T2065
Test name
Test status
Simulation time 198810799 ps
CPU time 0.92 seconds
Started Jun 30 06:22:27 PM PDT 24
Finished Jun 30 06:22:28 PM PDT 24
Peak memory 206180 kb
Host smart-2d9e59d3-83cf-4ebc-a280-fe3c1772ef91
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=483189305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.483189305
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3901594933
Short name T1058
Test name
Test status
Simulation time 142471980 ps
CPU time 0.74 seconds
Started Jun 30 06:22:27 PM PDT 24
Finished Jun 30 06:22:28 PM PDT 24
Peak memory 206220 kb
Host smart-8b5b9c23-ef23-4c90-83ad-5b35d28bebf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39015
94933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3901594933
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3906069136
Short name T1494
Test name
Test status
Simulation time 71915148 ps
CPU time 0.72 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:33 PM PDT 24
Peak memory 206336 kb
Host smart-e197427c-64af-4ed2-864c-b7e7aebdf9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39060
69136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3906069136
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3145557631
Short name T740
Test name
Test status
Simulation time 6209418250 ps
CPU time 14.04 seconds
Started Jun 30 06:22:24 PM PDT 24
Finished Jun 30 06:22:39 PM PDT 24
Peak memory 206428 kb
Host smart-3a89305d-3ae2-4178-8bbc-b140ce9de295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31455
57631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3145557631
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3852000470
Short name T1895
Test name
Test status
Simulation time 154585086 ps
CPU time 0.87 seconds
Started Jun 30 06:22:25 PM PDT 24
Finished Jun 30 06:22:27 PM PDT 24
Peak memory 206160 kb
Host smart-e64d4c38-fe66-4632-8553-127705d667eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38520
00470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3852000470
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.773424566
Short name T2501
Test name
Test status
Simulation time 198396910 ps
CPU time 0.91 seconds
Started Jun 30 06:22:23 PM PDT 24
Finished Jun 30 06:22:24 PM PDT 24
Peak memory 206204 kb
Host smart-fae0871c-63be-457d-8ca9-d476036d4e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77342
4566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.773424566
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.346470582
Short name T1671
Test name
Test status
Simulation time 172830874 ps
CPU time 0.86 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:33 PM PDT 24
Peak memory 206376 kb
Host smart-c015d007-65ea-458e-9afa-b443280159e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34647
0582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.346470582
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.4055848552
Short name T744
Test name
Test status
Simulation time 143765638 ps
CPU time 0.8 seconds
Started Jun 30 06:22:27 PM PDT 24
Finished Jun 30 06:22:29 PM PDT 24
Peak memory 206172 kb
Host smart-03bd0c55-3e8a-4132-b26a-8eaf92c36980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40558
48552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.4055848552
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2004840402
Short name T1069
Test name
Test status
Simulation time 176375478 ps
CPU time 0.81 seconds
Started Jun 30 06:22:27 PM PDT 24
Finished Jun 30 06:22:28 PM PDT 24
Peak memory 206168 kb
Host smart-5f9e1a9d-562c-4870-916f-87f2e2119db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20048
40402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2004840402
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1633959759
Short name T575
Test name
Test status
Simulation time 177145622 ps
CPU time 0.81 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:33 PM PDT 24
Peak memory 206340 kb
Host smart-3f3c2e06-9a04-41c7-819b-08a456894841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16339
59759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1633959759
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2471757022
Short name T1034
Test name
Test status
Simulation time 220362944 ps
CPU time 0.83 seconds
Started Jun 30 06:22:24 PM PDT 24
Finished Jun 30 06:22:25 PM PDT 24
Peak memory 206188 kb
Host smart-a741efd5-02e4-44cb-b5f5-97011fbabccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24717
57022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2471757022
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.4240381492
Short name T1930
Test name
Test status
Simulation time 223955608 ps
CPU time 0.92 seconds
Started Jun 30 06:22:25 PM PDT 24
Finished Jun 30 06:22:26 PM PDT 24
Peak memory 206188 kb
Host smart-5ac31846-0d1c-45a8-a86b-af0f51d35034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403
81492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.4240381492
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2260934234
Short name T517
Test name
Test status
Simulation time 4317162422 ps
CPU time 119.64 seconds
Started Jun 30 06:22:27 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206448 kb
Host smart-cbd9b879-853f-48c8-8620-7912cd760d52
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2260934234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2260934234
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2649115646
Short name T2421
Test name
Test status
Simulation time 178351717 ps
CPU time 0.78 seconds
Started Jun 30 06:22:28 PM PDT 24
Finished Jun 30 06:22:29 PM PDT 24
Peak memory 206152 kb
Host smart-578950d7-1ff1-45ca-a425-23bf226afc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26491
15646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2649115646
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1395705259
Short name T1035
Test name
Test status
Simulation time 195943772 ps
CPU time 0.85 seconds
Started Jun 30 06:22:25 PM PDT 24
Finished Jun 30 06:22:27 PM PDT 24
Peak memory 206120 kb
Host smart-c761b5d5-17de-4b26-816f-fec4e7fe85e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13957
05259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1395705259
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2027611551
Short name T2485
Test name
Test status
Simulation time 4484802450 ps
CPU time 42.24 seconds
Started Jun 30 06:22:24 PM PDT 24
Finished Jun 30 06:23:07 PM PDT 24
Peak memory 206428 kb
Host smart-391ecd6f-f7d7-4d3d-8744-682d7454e215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20276
11551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2027611551
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.3606494185
Short name T2473
Test name
Test status
Simulation time 42557479 ps
CPU time 0.69 seconds
Started Jun 30 06:22:34 PM PDT 24
Finished Jun 30 06:22:36 PM PDT 24
Peak memory 206196 kb
Host smart-00dcce39-0683-4019-b3df-d60d3430a0be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3606494185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3606494185
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2048138429
Short name T1573
Test name
Test status
Simulation time 3990002476 ps
CPU time 5.36 seconds
Started Jun 30 06:22:23 PM PDT 24
Finished Jun 30 06:22:29 PM PDT 24
Peak memory 206276 kb
Host smart-e6c4f929-cbf0-4bd7-bc60-777bbedc0c32
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2048138429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2048138429
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3163511486
Short name T2186
Test name
Test status
Simulation time 13421535761 ps
CPU time 12.69 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:45 PM PDT 24
Peak memory 206560 kb
Host smart-6ee05893-8b41-440b-9880-74af09548595
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3163511486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3163511486
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2728357121
Short name T666
Test name
Test status
Simulation time 23315984138 ps
CPU time 21.98 seconds
Started Jun 30 06:22:27 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206360 kb
Host smart-a7ab7bd8-e787-45d9-a77e-402c0d969b3d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2728357121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.2728357121
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2506353706
Short name T1028
Test name
Test status
Simulation time 150563414 ps
CPU time 0.77 seconds
Started Jun 30 06:22:27 PM PDT 24
Finished Jun 30 06:22:28 PM PDT 24
Peak memory 206220 kb
Host smart-620e1c9f-fe77-4b42-88b5-b83957b4f3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
53706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2506353706
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3797396221
Short name T60
Test name
Test status
Simulation time 140758266 ps
CPU time 0.77 seconds
Started Jun 30 06:22:25 PM PDT 24
Finished Jun 30 06:22:26 PM PDT 24
Peak memory 206192 kb
Host smart-f3834d36-5811-4fc5-8469-7e13ae3a4ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37973
96221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3797396221
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.3878641334
Short name T1160
Test name
Test status
Simulation time 379642048 ps
CPU time 1.2 seconds
Started Jun 30 06:22:23 PM PDT 24
Finished Jun 30 06:22:24 PM PDT 24
Peak memory 206180 kb
Host smart-c157ce4c-b6a2-4ab7-86bc-510bcae5c8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38786
41334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.3878641334
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.173265283
Short name T2295
Test name
Test status
Simulation time 958593796 ps
CPU time 2.04 seconds
Started Jun 30 06:22:28 PM PDT 24
Finished Jun 30 06:22:30 PM PDT 24
Peak memory 206272 kb
Host smart-29262d1b-ddb0-4cf6-9f40-bfea413e557a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17326
5283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.173265283
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.862184137
Short name T1985
Test name
Test status
Simulation time 13798980697 ps
CPU time 24.85 seconds
Started Jun 30 06:22:25 PM PDT 24
Finished Jun 30 06:22:50 PM PDT 24
Peak memory 206448 kb
Host smart-65002920-0d4d-402c-9a87-83da761af2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86218
4137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.862184137
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3250323419
Short name T1406
Test name
Test status
Simulation time 456822065 ps
CPU time 1.52 seconds
Started Jun 30 06:22:24 PM PDT 24
Finished Jun 30 06:22:26 PM PDT 24
Peak memory 206176 kb
Host smart-c4d66f9a-6d7c-49da-9698-2706997c23c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32503
23419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3250323419
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_enable.2428590218
Short name T955
Test name
Test status
Simulation time 53292071 ps
CPU time 0.68 seconds
Started Jun 30 06:22:27 PM PDT 24
Finished Jun 30 06:22:28 PM PDT 24
Peak memory 206156 kb
Host smart-aa9708d1-0560-46b9-bc11-d6e394a0e045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24285
90218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2428590218
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3989228636
Short name T2235
Test name
Test status
Simulation time 1050061720 ps
CPU time 2.45 seconds
Started Jun 30 06:22:26 PM PDT 24
Finished Jun 30 06:22:29 PM PDT 24
Peak memory 206280 kb
Host smart-abdfe0cf-e872-4960-bac9-b8f3eebf11bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39892
28636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3989228636
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2364995378
Short name T2075
Test name
Test status
Simulation time 150994467 ps
CPU time 1.28 seconds
Started Jun 30 06:22:25 PM PDT 24
Finished Jun 30 06:22:27 PM PDT 24
Peak memory 206336 kb
Host smart-0a5852c5-dc26-4994-8769-89d768e9a081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23649
95378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2364995378
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.242781053
Short name T1456
Test name
Test status
Simulation time 211832726 ps
CPU time 0.91 seconds
Started Jun 30 06:22:25 PM PDT 24
Finished Jun 30 06:22:27 PM PDT 24
Peak memory 206200 kb
Host smart-bb2dd291-792f-4204-a0bb-a27eac64b4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24278
1053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.242781053
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3636080526
Short name T2533
Test name
Test status
Simulation time 161644183 ps
CPU time 0.85 seconds
Started Jun 30 06:22:24 PM PDT 24
Finished Jun 30 06:22:25 PM PDT 24
Peak memory 206204 kb
Host smart-e9e87bc7-fa4a-4f90-bc08-cbe1767fc4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36360
80526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3636080526
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2839236799
Short name T2580
Test name
Test status
Simulation time 227820704 ps
CPU time 0.96 seconds
Started Jun 30 06:22:25 PM PDT 24
Finished Jun 30 06:22:26 PM PDT 24
Peak memory 206204 kb
Host smart-73786ab2-b326-4373-9842-bd0b494c55bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28392
36799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2839236799
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3006877217
Short name T956
Test name
Test status
Simulation time 6839533005 ps
CPU time 183.27 seconds
Started Jun 30 06:22:25 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206520 kb
Host smart-dfe35180-4b6d-452b-a39c-b702f383460c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3006877217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3006877217
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.72939128
Short name T366
Test name
Test status
Simulation time 188945873 ps
CPU time 0.81 seconds
Started Jun 30 06:22:31 PM PDT 24
Finished Jun 30 06:22:32 PM PDT 24
Peak memory 206176 kb
Host smart-e2b9cbe4-c444-4d11-8e21-442634ecddd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72939
128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.72939128
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.8165024
Short name T820
Test name
Test status
Simulation time 23303512208 ps
CPU time 22.41 seconds
Started Jun 30 06:22:35 PM PDT 24
Finished Jun 30 06:22:59 PM PDT 24
Peak memory 206292 kb
Host smart-426262d6-64e8-488e-9da3-46fbb1df7650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81650
24 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.8165024
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.52893849
Short name T1728
Test name
Test status
Simulation time 3345193332 ps
CPU time 3.84 seconds
Started Jun 30 06:22:39 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206252 kb
Host smart-b75d32eb-1d63-45b6-93c5-954ec2433368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52893
849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.52893849
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.314857380
Short name T2115
Test name
Test status
Simulation time 10221975502 ps
CPU time 71.45 seconds
Started Jun 30 06:22:31 PM PDT 24
Finished Jun 30 06:23:43 PM PDT 24
Peak memory 206456 kb
Host smart-6d82e447-1ea7-42de-9522-a9f17200064d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31485
7380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.314857380
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.65566827
Short name T1232
Test name
Test status
Simulation time 3401902639 ps
CPU time 93.55 seconds
Started Jun 30 06:22:34 PM PDT 24
Finished Jun 30 06:24:09 PM PDT 24
Peak memory 206420 kb
Host smart-00f9d095-1dfa-493d-906a-0e9cdc590071
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=65566827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.65566827
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.4246668277
Short name T937
Test name
Test status
Simulation time 246534417 ps
CPU time 0.94 seconds
Started Jun 30 06:22:34 PM PDT 24
Finished Jun 30 06:22:36 PM PDT 24
Peak memory 206220 kb
Host smart-0ce24be9-17d0-4f6d-ace1-875e870880b4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4246668277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.4246668277
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.4118023834
Short name T824
Test name
Test status
Simulation time 215297428 ps
CPU time 0.87 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:33 PM PDT 24
Peak memory 206240 kb
Host smart-80c3ce69-ad87-4575-8561-07cb860bb145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
23834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.4118023834
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1168771275
Short name T2579
Test name
Test status
Simulation time 6311226113 ps
CPU time 43.33 seconds
Started Jun 30 06:22:31 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206436 kb
Host smart-9365d8e9-125e-4806-a79c-8d441151a65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11687
71275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1168771275
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.524724237
Short name T1426
Test name
Test status
Simulation time 4095747484 ps
CPU time 29.58 seconds
Started Jun 30 06:22:34 PM PDT 24
Finished Jun 30 06:23:05 PM PDT 24
Peak memory 206460 kb
Host smart-8f05c13a-5d70-4156-bad8-8d607ac6dd42
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=524724237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.524724237
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.913840063
Short name T1844
Test name
Test status
Simulation time 152559580 ps
CPU time 0.85 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:34 PM PDT 24
Peak memory 206208 kb
Host smart-0eb7fe6d-d794-4326-8884-51ed8210a9c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=913840063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.913840063
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.4128888223
Short name T1798
Test name
Test status
Simulation time 143904359 ps
CPU time 0.76 seconds
Started Jun 30 06:22:40 PM PDT 24
Finished Jun 30 06:22:42 PM PDT 24
Peak memory 206200 kb
Host smart-b98c9d46-2660-4da9-84e9-f7d0c7129fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41288
88223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.4128888223
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2989204468
Short name T1752
Test name
Test status
Simulation time 185020037 ps
CPU time 0.84 seconds
Started Jun 30 06:22:30 PM PDT 24
Finished Jun 30 06:22:32 PM PDT 24
Peak memory 206184 kb
Host smart-79a64096-82e2-44aa-87f9-b00b86e49f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29892
04468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2989204468
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2382198470
Short name T927
Test name
Test status
Simulation time 227536540 ps
CPU time 0.87 seconds
Started Jun 30 06:22:34 PM PDT 24
Finished Jun 30 06:22:36 PM PDT 24
Peak memory 206192 kb
Host smart-c39c57a4-49bb-4148-a2a0-8bca3f8ff39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23821
98470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2382198470
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1559070268
Short name T2330
Test name
Test status
Simulation time 175385455 ps
CPU time 0.89 seconds
Started Jun 30 06:22:33 PM PDT 24
Finished Jun 30 06:22:35 PM PDT 24
Peak memory 206208 kb
Host smart-55208a70-b7eb-476c-82aa-8efce2aeb3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15590
70268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1559070268
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1045424651
Short name T2100
Test name
Test status
Simulation time 185469918 ps
CPU time 0.87 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:34 PM PDT 24
Peak memory 206176 kb
Host smart-f504d6b1-b153-4305-96de-d29186491aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10454
24651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1045424651
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.858153800
Short name T1878
Test name
Test status
Simulation time 244039601 ps
CPU time 0.97 seconds
Started Jun 30 06:22:36 PM PDT 24
Finished Jun 30 06:22:38 PM PDT 24
Peak memory 206144 kb
Host smart-1981734a-ec06-4af5-a1aa-94a09cf7f9a0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=858153800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.858153800
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.306086036
Short name T1230
Test name
Test status
Simulation time 139219867 ps
CPU time 0.81 seconds
Started Jun 30 06:22:35 PM PDT 24
Finished Jun 30 06:22:37 PM PDT 24
Peak memory 206196 kb
Host smart-199a82f9-b417-4883-9db1-3f714ece7e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30608
6036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.306086036
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3495645669
Short name T1988
Test name
Test status
Simulation time 65782793 ps
CPU time 0.71 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:33 PM PDT 24
Peak memory 206208 kb
Host smart-7611056b-1167-4bb3-88b1-4ab82bef29d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34956
45669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3495645669
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1390961434
Short name T87
Test name
Test status
Simulation time 21721517673 ps
CPU time 49.19 seconds
Started Jun 30 06:22:34 PM PDT 24
Finished Jun 30 06:23:24 PM PDT 24
Peak memory 206392 kb
Host smart-c6f9329d-c1ad-46cf-9820-d7c6940076ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13909
61434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1390961434
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1563383015
Short name T2543
Test name
Test status
Simulation time 183482192 ps
CPU time 0.85 seconds
Started Jun 30 06:22:35 PM PDT 24
Finished Jun 30 06:22:37 PM PDT 24
Peak memory 206168 kb
Host smart-15f8d8dc-37c2-43f7-8762-165805ee894f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15633
83015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1563383015
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2506294893
Short name T785
Test name
Test status
Simulation time 171096275 ps
CPU time 0.85 seconds
Started Jun 30 06:22:33 PM PDT 24
Finished Jun 30 06:22:35 PM PDT 24
Peak memory 206208 kb
Host smart-76f31ca3-aec7-44b2-a2c1-a5c4149cd19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062
94893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2506294893
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2875570976
Short name T2084
Test name
Test status
Simulation time 200940123 ps
CPU time 0.85 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:34 PM PDT 24
Peak memory 206212 kb
Host smart-0fd47b5b-797e-46a1-9b34-1c992bd19e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755
70976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2875570976
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.3511407763
Short name T964
Test name
Test status
Simulation time 185202139 ps
CPU time 0.91 seconds
Started Jun 30 06:22:35 PM PDT 24
Finished Jun 30 06:22:37 PM PDT 24
Peak memory 206164 kb
Host smart-77f455f2-a4ef-490e-81ba-268545a9dd11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35114
07763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.3511407763
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3797395701
Short name T1779
Test name
Test status
Simulation time 147903336 ps
CPU time 0.76 seconds
Started Jun 30 06:22:35 PM PDT 24
Finished Jun 30 06:22:37 PM PDT 24
Peak memory 206196 kb
Host smart-b2ba3d4e-d732-467e-b8e6-1917279ce7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37973
95701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3797395701
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2104399096
Short name T1228
Test name
Test status
Simulation time 160569107 ps
CPU time 0.82 seconds
Started Jun 30 06:22:31 PM PDT 24
Finished Jun 30 06:22:32 PM PDT 24
Peak memory 206180 kb
Host smart-992de547-6768-4f63-892b-defddaa7817f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21043
99096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2104399096
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1525459769
Short name T1858
Test name
Test status
Simulation time 155732881 ps
CPU time 0.81 seconds
Started Jun 30 06:22:33 PM PDT 24
Finished Jun 30 06:22:35 PM PDT 24
Peak memory 206156 kb
Host smart-7bf21d6e-0538-415e-851b-7b60b83a3f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15254
59769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1525459769
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3585554340
Short name T1072
Test name
Test status
Simulation time 234750904 ps
CPU time 0.97 seconds
Started Jun 30 06:22:30 PM PDT 24
Finished Jun 30 06:22:31 PM PDT 24
Peak memory 206220 kb
Host smart-45d247ae-1c81-44ec-9284-131ac5e391bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35855
54340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3585554340
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.3318491032
Short name T2509
Test name
Test status
Simulation time 7076467706 ps
CPU time 208.25 seconds
Started Jun 30 06:22:33 PM PDT 24
Finished Jun 30 06:26:02 PM PDT 24
Peak memory 206480 kb
Host smart-966d856f-3efc-4216-81ee-dacb55a987b1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3318491032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.3318491032
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3491692033
Short name T1063
Test name
Test status
Simulation time 185676350 ps
CPU time 0.85 seconds
Started Jun 30 06:22:34 PM PDT 24
Finished Jun 30 06:22:36 PM PDT 24
Peak memory 206192 kb
Host smart-113ce2f2-40fe-4c7c-953b-6e67ae8fb058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34916
92033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3491692033
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.4259552411
Short name T1708
Test name
Test status
Simulation time 167038324 ps
CPU time 0.85 seconds
Started Jun 30 06:22:35 PM PDT 24
Finished Jun 30 06:22:37 PM PDT 24
Peak memory 206200 kb
Host smart-79730534-465e-4831-82f6-94926afa3235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42595
52411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.4259552411
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3450498828
Short name T505
Test name
Test status
Simulation time 6151660484 ps
CPU time 43.62 seconds
Started Jun 30 06:22:33 PM PDT 24
Finished Jun 30 06:23:18 PM PDT 24
Peak memory 206428 kb
Host smart-f1007875-7e38-4152-b55b-1af284feea38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34504
98828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3450498828
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.383504730
Short name T1480
Test name
Test status
Simulation time 84211576 ps
CPU time 0.76 seconds
Started Jun 30 06:22:42 PM PDT 24
Finished Jun 30 06:22:44 PM PDT 24
Peak memory 206192 kb
Host smart-04151dcb-5199-4a5c-b1b3-a06227cc6b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=383504730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.383504730
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2825818038
Short name T1763
Test name
Test status
Simulation time 3595952377 ps
CPU time 4.15 seconds
Started Jun 30 06:22:33 PM PDT 24
Finished Jun 30 06:22:38 PM PDT 24
Peak memory 206276 kb
Host smart-286ab28d-45e3-4d83-9e5b-4a0920940799
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2825818038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.2825818038
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.897852871
Short name T697
Test name
Test status
Simulation time 13375166475 ps
CPU time 13.09 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:46 PM PDT 24
Peak memory 206340 kb
Host smart-68d20db0-cf10-4095-a3c1-e9bf6da2bc3d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=897852871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.897852871
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.887230302
Short name T1977
Test name
Test status
Simulation time 23365678112 ps
CPU time 23.71 seconds
Started Jun 30 06:22:34 PM PDT 24
Finished Jun 30 06:22:59 PM PDT 24
Peak memory 206444 kb
Host smart-209eb3e2-55bc-4527-a4a0-c215dad4a5e3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=887230302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.887230302
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.4247703824
Short name T1258
Test name
Test status
Simulation time 153864254 ps
CPU time 0.82 seconds
Started Jun 30 06:22:32 PM PDT 24
Finished Jun 30 06:22:34 PM PDT 24
Peak memory 206160 kb
Host smart-e792ec51-bdf0-45b2-87ba-41cf8e55f601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42477
03824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.4247703824
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1930471631
Short name T448
Test name
Test status
Simulation time 148112423 ps
CPU time 0.8 seconds
Started Jun 30 06:22:33 PM PDT 24
Finished Jun 30 06:22:35 PM PDT 24
Peak memory 206188 kb
Host smart-aa709554-cb4e-4a2a-818e-78f050d41cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19304
71631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1930471631
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.3903316568
Short name T2069
Test name
Test status
Simulation time 350315320 ps
CPU time 1.22 seconds
Started Jun 30 06:22:33 PM PDT 24
Finished Jun 30 06:22:36 PM PDT 24
Peak memory 206192 kb
Host smart-99ede0b4-48dc-4001-9987-0018eb8c003e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39033
16568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.3903316568
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.448619110
Short name T1635
Test name
Test status
Simulation time 1614216369 ps
CPU time 3.54 seconds
Started Jun 30 06:22:39 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206276 kb
Host smart-14054dbb-7fbf-4089-a636-0a8f3f1e666f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44861
9110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.448619110
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.940634493
Short name T187
Test name
Test status
Simulation time 9092750060 ps
CPU time 17.86 seconds
Started Jun 30 06:22:40 PM PDT 24
Finished Jun 30 06:22:58 PM PDT 24
Peak memory 206392 kb
Host smart-c27eae91-0e57-4845-98f9-0fdd95973bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94063
4493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.940634493
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3292182679
Short name T516
Test name
Test status
Simulation time 462400374 ps
CPU time 1.42 seconds
Started Jun 30 06:22:41 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206192 kb
Host smart-1c4779a7-0e1c-4170-807b-97c81cc1bb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32921
82679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3292182679
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.151593057
Short name T1619
Test name
Test status
Simulation time 166442370 ps
CPU time 0.81 seconds
Started Jun 30 06:22:45 PM PDT 24
Finished Jun 30 06:22:47 PM PDT 24
Peak memory 206192 kb
Host smart-25532d97-9622-4503-b43e-b8eb317cfae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15159
3057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.151593057
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3591175945
Short name T1885
Test name
Test status
Simulation time 35934826 ps
CPU time 0.66 seconds
Started Jun 30 06:22:39 PM PDT 24
Finished Jun 30 06:22:40 PM PDT 24
Peak memory 206160 kb
Host smart-58f05db9-f278-4aef-9b3a-be9e5cd6fc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35911
75945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3591175945
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1710596067
Short name T1703
Test name
Test status
Simulation time 859008687 ps
CPU time 2.01 seconds
Started Jun 30 06:22:40 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206340 kb
Host smart-bbbfdb49-4eea-4ed9-91c3-a14f87b35d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17105
96067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1710596067
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3617496595
Short name T704
Test name
Test status
Simulation time 202209692 ps
CPU time 1.76 seconds
Started Jun 30 06:22:45 PM PDT 24
Finished Jun 30 06:22:48 PM PDT 24
Peak memory 206252 kb
Host smart-7cda44c6-0d5d-4066-bdb3-11035aaba157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36174
96595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3617496595
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.2117639780
Short name T2582
Test name
Test status
Simulation time 155474270 ps
CPU time 0.76 seconds
Started Jun 30 06:22:39 PM PDT 24
Finished Jun 30 06:22:41 PM PDT 24
Peak memory 206176 kb
Host smart-ebf4180c-9426-4135-ab62-59f0d7e6f9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21176
39780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.2117639780
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.236751784
Short name T874
Test name
Test status
Simulation time 144299759 ps
CPU time 0.74 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206164 kb
Host smart-b1786d37-3d17-48a0-8091-7f8da8d80d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
1784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.236751784
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1206206170
Short name T404
Test name
Test status
Simulation time 154280233 ps
CPU time 0.79 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:22:48 PM PDT 24
Peak memory 206164 kb
Host smart-e6f98b24-3f3f-4c06-985b-8f373888e3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12062
06170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1206206170
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.3185885723
Short name T1430
Test name
Test status
Simulation time 7098876817 ps
CPU time 200.62 seconds
Started Jun 30 06:22:41 PM PDT 24
Finished Jun 30 06:26:03 PM PDT 24
Peak memory 206452 kb
Host smart-f863020b-7845-4614-beb9-47ceaa450a52
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3185885723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.3185885723
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.4060017015
Short name T2290
Test name
Test status
Simulation time 222149795 ps
CPU time 0.92 seconds
Started Jun 30 06:22:47 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206148 kb
Host smart-74dfa845-90eb-4d84-8ef6-36c29f50fca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40600
17015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.4060017015
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3281997606
Short name T1667
Test name
Test status
Simulation time 23333015143 ps
CPU time 22.07 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:23:09 PM PDT 24
Peak memory 206312 kb
Host smart-bd2ce7ae-678d-489a-a847-16e5ea165e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32819
97606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3281997606
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.3807249671
Short name T440
Test name
Test status
Simulation time 3313378196 ps
CPU time 4.05 seconds
Started Jun 30 06:22:43 PM PDT 24
Finished Jun 30 06:22:47 PM PDT 24
Peak memory 206244 kb
Host smart-b69441b9-817c-4fa2-9e56-8178936802b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
49671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3807249671
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.2037579306
Short name T1187
Test name
Test status
Simulation time 9606274294 ps
CPU time 95.33 seconds
Started Jun 30 06:22:40 PM PDT 24
Finished Jun 30 06:24:17 PM PDT 24
Peak memory 206400 kb
Host smart-5ce4cf20-4eb0-43b9-9752-0cabd2fe8282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20375
79306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2037579306
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.2594875881
Short name T858
Test name
Test status
Simulation time 3897929121 ps
CPU time 104.34 seconds
Started Jun 30 06:22:42 PM PDT 24
Finished Jun 30 06:24:27 PM PDT 24
Peak memory 206456 kb
Host smart-786f2ff1-75d9-4206-8e5b-e4c97540b82d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2594875881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.2594875881
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1736077108
Short name T2558
Test name
Test status
Simulation time 255635745 ps
CPU time 0.91 seconds
Started Jun 30 06:22:45 PM PDT 24
Finished Jun 30 06:22:47 PM PDT 24
Peak memory 206212 kb
Host smart-db72dbfd-e252-4f8c-86e9-7bd2279d6691
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1736077108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1736077108
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1343934725
Short name T788
Test name
Test status
Simulation time 196410502 ps
CPU time 0.86 seconds
Started Jun 30 06:22:44 PM PDT 24
Finished Jun 30 06:22:45 PM PDT 24
Peak memory 206176 kb
Host smart-261ccafa-08cf-4f8d-b5e3-2f78b2c8944f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13439
34725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1343934725
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1706987117
Short name T1568
Test name
Test status
Simulation time 5125801341 ps
CPU time 37.61 seconds
Started Jun 30 06:22:39 PM PDT 24
Finished Jun 30 06:23:17 PM PDT 24
Peak memory 206464 kb
Host smart-8cb31260-f13d-419f-a770-02ae1bb9418c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17069
87117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1706987117
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1584801293
Short name T2085
Test name
Test status
Simulation time 7358209495 ps
CPU time 203.86 seconds
Started Jun 30 06:22:38 PM PDT 24
Finished Jun 30 06:26:03 PM PDT 24
Peak memory 206424 kb
Host smart-11264b49-c243-4675-be49-935668551d6f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1584801293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1584801293
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3910158964
Short name T1122
Test name
Test status
Simulation time 163970259 ps
CPU time 0.8 seconds
Started Jun 30 06:22:40 PM PDT 24
Finished Jun 30 06:22:41 PM PDT 24
Peak memory 206208 kb
Host smart-b9bf6a3f-a519-4b02-83e3-14f87d0eb421
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3910158964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3910158964
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3883657905
Short name T1243
Test name
Test status
Simulation time 161010122 ps
CPU time 0.78 seconds
Started Jun 30 06:22:40 PM PDT 24
Finished Jun 30 06:22:41 PM PDT 24
Peak memory 206196 kb
Host smart-b49633eb-da7d-4941-b9f7-60cf6582ea77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38836
57905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3883657905
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1985561192
Short name T115
Test name
Test status
Simulation time 245965160 ps
CPU time 0.95 seconds
Started Jun 30 06:22:44 PM PDT 24
Finished Jun 30 06:22:45 PM PDT 24
Peak memory 206176 kb
Host smart-f87f55b7-d542-4111-80cf-d020e0d6ade4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19855
61192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1985561192
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3005654647
Short name T1960
Test name
Test status
Simulation time 152924988 ps
CPU time 0.8 seconds
Started Jun 30 06:22:41 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206180 kb
Host smart-c4fda09a-2e0f-4641-9e5e-55865818db43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30056
54647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3005654647
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1092370672
Short name T2360
Test name
Test status
Simulation time 171937558 ps
CPU time 0.81 seconds
Started Jun 30 06:22:47 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206156 kb
Host smart-42fbe635-5684-4528-bf31-9a7b172a81e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10923
70672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1092370672
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3210357143
Short name T566
Test name
Test status
Simulation time 200204487 ps
CPU time 0.86 seconds
Started Jun 30 06:22:45 PM PDT 24
Finished Jun 30 06:22:46 PM PDT 24
Peak memory 206184 kb
Host smart-43dcd0a1-9a2b-4033-9ab7-f162df28ae64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32103
57143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3210357143
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.285305213
Short name T2523
Test name
Test status
Simulation time 160265316 ps
CPU time 0.84 seconds
Started Jun 30 06:22:45 PM PDT 24
Finished Jun 30 06:22:46 PM PDT 24
Peak memory 206188 kb
Host smart-14f9715b-7ff0-45d2-8cfa-0729f4fe6585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28530
5213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.285305213
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.1384300849
Short name T151
Test name
Test status
Simulation time 244563118 ps
CPU time 0.96 seconds
Started Jun 30 06:22:44 PM PDT 24
Finished Jun 30 06:22:46 PM PDT 24
Peak memory 206200 kb
Host smart-2bb7e2f8-6c8b-4457-b0d3-a040251af5fc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1384300849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.1384300849
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2194623994
Short name T1100
Test name
Test status
Simulation time 155140143 ps
CPU time 0.77 seconds
Started Jun 30 06:22:40 PM PDT 24
Finished Jun 30 06:22:41 PM PDT 24
Peak memory 206184 kb
Host smart-b8cf4f8c-fab3-4691-b769-b9967abaa692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21946
23994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2194623994
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1430338777
Short name T801
Test name
Test status
Simulation time 32894271 ps
CPU time 0.69 seconds
Started Jun 30 06:22:39 PM PDT 24
Finished Jun 30 06:22:40 PM PDT 24
Peak memory 206200 kb
Host smart-a8fdf518-4319-4eb9-9956-42c31ec883d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14303
38777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1430338777
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3098797759
Short name T916
Test name
Test status
Simulation time 11763404308 ps
CPU time 26.41 seconds
Started Jun 30 06:22:41 PM PDT 24
Finished Jun 30 06:23:08 PM PDT 24
Peak memory 206400 kb
Host smart-82f0d5dd-75ac-498a-bdff-d64559627e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30987
97759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3098797759
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.4171657726
Short name T1584
Test name
Test status
Simulation time 149302196 ps
CPU time 0.82 seconds
Started Jun 30 06:22:48 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 206144 kb
Host smart-5abacff3-2620-45bd-b993-16e3e258463e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41716
57726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.4171657726
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1861687047
Short name T714
Test name
Test status
Simulation time 273659766 ps
CPU time 1 seconds
Started Jun 30 06:22:45 PM PDT 24
Finished Jun 30 06:22:47 PM PDT 24
Peak memory 206172 kb
Host smart-29b72e62-17a5-4728-974e-a55c7ab6fe6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18616
87047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1861687047
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.3940350939
Short name T1126
Test name
Test status
Simulation time 245826040 ps
CPU time 0.98 seconds
Started Jun 30 06:22:41 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206200 kb
Host smart-fd5ff15c-9d0c-46fc-b5dd-87b4e70492b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39403
50939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.3940350939
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3176764188
Short name T1180
Test name
Test status
Simulation time 159040508 ps
CPU time 0.81 seconds
Started Jun 30 06:22:37 PM PDT 24
Finished Jun 30 06:22:39 PM PDT 24
Peak memory 206192 kb
Host smart-1420b124-bebc-4277-a9fe-7d847aa07997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31767
64188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3176764188
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1005861946
Short name T2167
Test name
Test status
Simulation time 141700435 ps
CPU time 0.79 seconds
Started Jun 30 06:22:38 PM PDT 24
Finished Jun 30 06:22:39 PM PDT 24
Peak memory 206228 kb
Host smart-d73b62de-3cb0-48a7-91ab-1e757edee007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10058
61946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1005861946
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.501857444
Short name T2542
Test name
Test status
Simulation time 162010995 ps
CPU time 0.79 seconds
Started Jun 30 06:22:42 PM PDT 24
Finished Jun 30 06:22:44 PM PDT 24
Peak memory 206180 kb
Host smart-a74aa7db-f7ff-425d-8023-88f187af86c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50185
7444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.501857444
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.301291446
Short name T437
Test name
Test status
Simulation time 177348796 ps
CPU time 0.81 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:22:48 PM PDT 24
Peak memory 206196 kb
Host smart-a084be01-2bdd-4302-a58a-b23d5186715b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30129
1446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.301291446
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2933904607
Short name T512
Test name
Test status
Simulation time 239857839 ps
CPU time 0.95 seconds
Started Jun 30 06:22:41 PM PDT 24
Finished Jun 30 06:22:43 PM PDT 24
Peak memory 206212 kb
Host smart-580f47aa-de84-4ee5-bbc1-a99d32e97a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29339
04607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2933904607
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.3561218571
Short name T907
Test name
Test status
Simulation time 6225809420 ps
CPU time 173.41 seconds
Started Jun 30 06:22:39 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206492 kb
Host smart-f65d3a02-6c1a-4c17-aa39-23da305d70f5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3561218571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.3561218571
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2358348098
Short name T1542
Test name
Test status
Simulation time 166260836 ps
CPU time 0.82 seconds
Started Jun 30 06:22:42 PM PDT 24
Finished Jun 30 06:22:44 PM PDT 24
Peak memory 206180 kb
Host smart-9f26ee66-1247-4bf7-b565-868c6ce2d7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23583
48098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2358348098
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1023577250
Short name T2159
Test name
Test status
Simulation time 215347443 ps
CPU time 0.85 seconds
Started Jun 30 06:22:40 PM PDT 24
Finished Jun 30 06:22:42 PM PDT 24
Peak memory 206192 kb
Host smart-1fbe3535-863d-4d07-af1c-10149a6a2277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10235
77250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1023577250
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2328042122
Short name T1755
Test name
Test status
Simulation time 6391380269 ps
CPU time 175.39 seconds
Started Jun 30 06:22:41 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206360 kb
Host smart-2e44ee0b-7eea-48e7-b105-d02130aa402c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23280
42122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2328042122
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.519860507
Short name T2589
Test name
Test status
Simulation time 36646598 ps
CPU time 0.7 seconds
Started Jun 30 06:22:55 PM PDT 24
Finished Jun 30 06:22:56 PM PDT 24
Peak memory 206208 kb
Host smart-f281f307-da2b-42c7-8b60-e51e7a471751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=519860507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.519860507
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2192130785
Short name T1957
Test name
Test status
Simulation time 3814679937 ps
CPU time 4.55 seconds
Started Jun 30 06:22:40 PM PDT 24
Finished Jun 30 06:22:46 PM PDT 24
Peak memory 206376 kb
Host smart-9a5afb6e-b9f6-48ca-a8b2-0ab0581e89bb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2192130785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.2192130785
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.719497653
Short name T1817
Test name
Test status
Simulation time 13432578860 ps
CPU time 12.82 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:23:00 PM PDT 24
Peak memory 206344 kb
Host smart-0ba4175c-46d8-4816-9dd9-db50a47a0be3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=719497653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.719497653
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3905897577
Short name T1530
Test name
Test status
Simulation time 186990516 ps
CPU time 0.89 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206184 kb
Host smart-829336fd-bd3e-4ff1-bee5-789dd91faf6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39058
97577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3905897577
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1997839543
Short name T1115
Test name
Test status
Simulation time 172890720 ps
CPU time 0.79 seconds
Started Jun 30 06:22:47 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206184 kb
Host smart-6f9c6096-53ee-4735-bf79-32ee7a40ed08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19978
39543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1997839543
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.649638579
Short name T549
Test name
Test status
Simulation time 568084432 ps
CPU time 1.88 seconds
Started Jun 30 06:22:47 PM PDT 24
Finished Jun 30 06:22:50 PM PDT 24
Peak memory 206288 kb
Host smart-6a180bdb-f604-4c34-9ddc-a03df7fa960c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64963
8579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.649638579
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1944431245
Short name T557
Test name
Test status
Simulation time 248686081 ps
CPU time 0.88 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206192 kb
Host smart-a0ec613e-3929-4e24-b513-0f5113ec53df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19444
31245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1944431245
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2211780803
Short name T2050
Test name
Test status
Simulation time 6255927368 ps
CPU time 12.77 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:23:03 PM PDT 24
Peak memory 206388 kb
Host smart-ff5a319c-b79b-48c4-9944-21c0acc7a00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22117
80803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2211780803
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1696295854
Short name T1223
Test name
Test status
Simulation time 370935624 ps
CPU time 1.17 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206180 kb
Host smart-57220e8e-204d-4950-8534-2d3c6875c418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16962
95854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1696295854
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1250695132
Short name T1665
Test name
Test status
Simulation time 157039774 ps
CPU time 0.75 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:22:47 PM PDT 24
Peak memory 206180 kb
Host smart-18f9dfa7-5b23-4ea9-a350-53b3c27348e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506
95132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1250695132
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.4161691269
Short name T2598
Test name
Test status
Simulation time 45535747 ps
CPU time 0.73 seconds
Started Jun 30 06:22:48 PM PDT 24
Finished Jun 30 06:22:50 PM PDT 24
Peak memory 206192 kb
Host smart-c7dc4862-c070-46a7-902f-e74248de3f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41616
91269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.4161691269
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.3914012335
Short name T1428
Test name
Test status
Simulation time 894489579 ps
CPU time 2.18 seconds
Started Jun 30 06:22:45 PM PDT 24
Finished Jun 30 06:22:48 PM PDT 24
Peak memory 206348 kb
Host smart-c1972e2a-d970-4549-94f8-9ae6ecc7ae50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39140
12335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3914012335
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1686653985
Short name T1376
Test name
Test status
Simulation time 188560045 ps
CPU time 1.94 seconds
Started Jun 30 06:22:48 PM PDT 24
Finished Jun 30 06:22:52 PM PDT 24
Peak memory 206324 kb
Host smart-800759e9-b21e-4858-8384-2258a0767bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16866
53985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1686653985
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2515441848
Short name T1541
Test name
Test status
Simulation time 162636894 ps
CPU time 0.81 seconds
Started Jun 30 06:22:50 PM PDT 24
Finished Jun 30 06:22:52 PM PDT 24
Peak memory 206188 kb
Host smart-aeb8f617-5ead-4419-bb59-09d0a740bb13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25154
41848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2515441848
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1503155166
Short name T1284
Test name
Test status
Simulation time 139787455 ps
CPU time 0.84 seconds
Started Jun 30 06:22:48 PM PDT 24
Finished Jun 30 06:22:50 PM PDT 24
Peak memory 206208 kb
Host smart-a0414eff-31c0-4b25-bd15-b992276330fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15031
55166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1503155166
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2558861081
Short name T367
Test name
Test status
Simulation time 206024115 ps
CPU time 0.9 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 206212 kb
Host smart-b8c71118-7ea2-46d1-aa78-eac38e74532c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25588
61081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2558861081
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3915567248
Short name T2032
Test name
Test status
Simulation time 191622003 ps
CPU time 0.93 seconds
Started Jun 30 06:22:48 PM PDT 24
Finished Jun 30 06:22:50 PM PDT 24
Peak memory 206196 kb
Host smart-a3fd794b-5ba5-44e8-b083-492d1271606b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39155
67248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3915567248
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.3699727519
Short name T1415
Test name
Test status
Simulation time 23335705535 ps
CPU time 21.92 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:23:09 PM PDT 24
Peak memory 206264 kb
Host smart-ee9d2ad1-dc96-45b9-b7c3-00d6bbba8329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36997
27519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.3699727519
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.4273323739
Short name T809
Test name
Test status
Simulation time 3323444225 ps
CPU time 3.48 seconds
Started Jun 30 06:22:47 PM PDT 24
Finished Jun 30 06:22:52 PM PDT 24
Peak memory 206204 kb
Host smart-bd9e1822-ae6c-499e-893e-0faf4ce6c498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42733
23739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.4273323739
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1279120261
Short name T1165
Test name
Test status
Simulation time 11494388108 ps
CPU time 330.74 seconds
Started Jun 30 06:22:48 PM PDT 24
Finished Jun 30 06:28:20 PM PDT 24
Peak memory 206476 kb
Host smart-b8979449-398b-4b90-9b4a-a04b9e43f834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12791
20261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1279120261
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.4023747009
Short name T843
Test name
Test status
Simulation time 3056105205 ps
CPU time 78.99 seconds
Started Jun 30 06:22:48 PM PDT 24
Finished Jun 30 06:24:08 PM PDT 24
Peak memory 206460 kb
Host smart-b1c61a83-70c6-430e-92ac-8f7034a5d9ae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4023747009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.4023747009
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2088328649
Short name T2236
Test name
Test status
Simulation time 241773908 ps
CPU time 0.9 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 206200 kb
Host smart-54f684af-bec7-4a16-a447-caf41763bafe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2088328649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2088328649
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3256664890
Short name T2592
Test name
Test status
Simulation time 192148548 ps
CPU time 0.89 seconds
Started Jun 30 06:22:48 PM PDT 24
Finished Jun 30 06:22:50 PM PDT 24
Peak memory 206184 kb
Host smart-c09b19d1-7268-483a-bc32-188394451801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32566
64890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3256664890
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.4065743689
Short name T872
Test name
Test status
Simulation time 5849264144 ps
CPU time 55.17 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:23:46 PM PDT 24
Peak memory 206488 kb
Host smart-e87168bd-0330-4ff3-bd8d-e0de0ab4dc8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40657
43689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.4065743689
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1760045980
Short name T461
Test name
Test status
Simulation time 4832796111 ps
CPU time 44.96 seconds
Started Jun 30 06:22:51 PM PDT 24
Finished Jun 30 06:23:37 PM PDT 24
Peak memory 206368 kb
Host smart-b2f0f1dc-5808-43b1-a0ce-a67b4f607e4e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1760045980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1760045980
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.4134428087
Short name T2457
Test name
Test status
Simulation time 214078154 ps
CPU time 0.81 seconds
Started Jun 30 06:22:47 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206184 kb
Host smart-e4c7c955-8029-42be-83c9-dec9a6c64974
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4134428087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.4134428087
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.846844153
Short name T510
Test name
Test status
Simulation time 147504388 ps
CPU time 0.81 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 206176 kb
Host smart-d9029db9-6493-4e2e-a0b6-484f816f59ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84684
4153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.846844153
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1070957112
Short name T1357
Test name
Test status
Simulation time 205623423 ps
CPU time 0.86 seconds
Started Jun 30 06:22:52 PM PDT 24
Finished Jun 30 06:22:53 PM PDT 24
Peak memory 206176 kb
Host smart-e73c59b1-ddad-4d93-a263-067e808b4cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10709
57112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1070957112
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2510242448
Short name T1514
Test name
Test status
Simulation time 197028382 ps
CPU time 0.85 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206160 kb
Host smart-269341e9-95f3-40e1-be2b-ec670b92b647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25102
42448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2510242448
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3222867025
Short name T2596
Test name
Test status
Simulation time 184619201 ps
CPU time 0.83 seconds
Started Jun 30 06:22:45 PM PDT 24
Finished Jun 30 06:22:46 PM PDT 24
Peak memory 206160 kb
Host smart-8b26235a-8fc4-471e-ab9f-70817b64ce59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32228
67025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3222867025
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3403445141
Short name T803
Test name
Test status
Simulation time 165068254 ps
CPU time 0.78 seconds
Started Jun 30 06:22:53 PM PDT 24
Finished Jun 30 06:22:54 PM PDT 24
Peak memory 206192 kb
Host smart-8054e890-4e9d-4aa0-9bc6-76fb366ee146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34034
45141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3403445141
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1307905507
Short name T868
Test name
Test status
Simulation time 207880394 ps
CPU time 0.84 seconds
Started Jun 30 06:22:47 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206172 kb
Host smart-7a548c30-639b-4806-be4b-fc2459e99c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13079
05507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1307905507
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3132838931
Short name T943
Test name
Test status
Simulation time 223710079 ps
CPU time 0.92 seconds
Started Jun 30 06:22:48 PM PDT 24
Finished Jun 30 06:22:50 PM PDT 24
Peak memory 206188 kb
Host smart-99eba68c-308d-48e3-954b-3f7f383f45a9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3132838931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3132838931
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1524005043
Short name T784
Test name
Test status
Simulation time 186749374 ps
CPU time 0.78 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:22:48 PM PDT 24
Peak memory 206196 kb
Host smart-f205ccef-c010-4689-bbac-9fd144fc82b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15240
05043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1524005043
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2365867095
Short name T2191
Test name
Test status
Simulation time 39021984 ps
CPU time 0.69 seconds
Started Jun 30 06:22:48 PM PDT 24
Finished Jun 30 06:22:50 PM PDT 24
Peak memory 206200 kb
Host smart-3be7c9ac-7f09-410b-862c-20bfc2a660ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23658
67095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2365867095
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2453723490
Short name T2245
Test name
Test status
Simulation time 21460727142 ps
CPU time 50.26 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:23:41 PM PDT 24
Peak memory 206388 kb
Host smart-39bc8f3b-5d1b-4f73-aaf8-1437cca67e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24537
23490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2453723490
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.4095118131
Short name T1830
Test name
Test status
Simulation time 194784155 ps
CPU time 0.91 seconds
Started Jun 30 06:22:53 PM PDT 24
Finished Jun 30 06:22:55 PM PDT 24
Peak memory 206164 kb
Host smart-92c48ab4-b42f-49fb-aebb-cb504444649a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40951
18131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.4095118131
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.943787099
Short name T431
Test name
Test status
Simulation time 182703695 ps
CPU time 0.85 seconds
Started Jun 30 06:22:51 PM PDT 24
Finished Jun 30 06:22:53 PM PDT 24
Peak memory 206196 kb
Host smart-c0a0a988-5394-4082-9a30-a0301ad42ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94378
7099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.943787099
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.949321738
Short name T2133
Test name
Test status
Simulation time 213962717 ps
CPU time 0.86 seconds
Started Jun 30 06:22:47 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206208 kb
Host smart-0ffe438e-c5a7-4486-9812-8dadcc00f59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94932
1738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.949321738
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1710794524
Short name T838
Test name
Test status
Simulation time 199732688 ps
CPU time 0.9 seconds
Started Jun 30 06:22:53 PM PDT 24
Finished Jun 30 06:22:54 PM PDT 24
Peak memory 206188 kb
Host smart-0fe01316-d81f-46a0-b162-06f85b8755a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17107
94524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1710794524
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.3154284274
Short name T1323
Test name
Test status
Simulation time 191957470 ps
CPU time 0.83 seconds
Started Jun 30 06:22:50 PM PDT 24
Finished Jun 30 06:22:52 PM PDT 24
Peak memory 206168 kb
Host smart-942027d9-ffdf-4198-a1b0-bb376b876399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31542
84274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3154284274
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2563123198
Short name T2302
Test name
Test status
Simulation time 148582513 ps
CPU time 0.77 seconds
Started Jun 30 06:22:53 PM PDT 24
Finished Jun 30 06:22:55 PM PDT 24
Peak memory 206172 kb
Host smart-45bcccca-c724-4f5e-a9cf-8645951c9afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25631
23198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2563123198
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2347233558
Short name T1082
Test name
Test status
Simulation time 148899040 ps
CPU time 0.78 seconds
Started Jun 30 06:22:46 PM PDT 24
Finished Jun 30 06:22:48 PM PDT 24
Peak memory 206180 kb
Host smart-d7fb694b-2499-4e3d-b323-f7ee5b37fd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23472
33558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2347233558
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.4269998133
Short name T1411
Test name
Test status
Simulation time 215717470 ps
CPU time 0.98 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 206212 kb
Host smart-0f9921c1-3ac9-4c5a-a3b8-b5a47e627ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42699
98133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.4269998133
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.4255613739
Short name T1073
Test name
Test status
Simulation time 3887242802 ps
CPU time 105.28 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206476 kb
Host smart-f3f9cd04-ae5b-486f-905e-688c037f1553
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4255613739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.4255613739
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.864932302
Short name T2366
Test name
Test status
Simulation time 245313269 ps
CPU time 0.91 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 206212 kb
Host smart-fa269e5f-a0f3-4569-b08e-252873655a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86493
2302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.864932302
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2864317787
Short name T1664
Test name
Test status
Simulation time 230789385 ps
CPU time 0.87 seconds
Started Jun 30 06:22:49 PM PDT 24
Finished Jun 30 06:22:52 PM PDT 24
Peak memory 206168 kb
Host smart-3f8fdc23-6253-4641-815a-a90aa2343600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28643
17787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2864317787
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.263293549
Short name T681
Test name
Test status
Simulation time 5283540426 ps
CPU time 149.75 seconds
Started Jun 30 06:22:53 PM PDT 24
Finished Jun 30 06:25:23 PM PDT 24
Peak memory 206424 kb
Host smart-6f00781a-97e8-4a05-9fba-4fb9adc22130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26329
3549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.263293549
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.1230358099
Short name T2605
Test name
Test status
Simulation time 41783951 ps
CPU time 0.69 seconds
Started Jun 30 06:23:03 PM PDT 24
Finished Jun 30 06:23:04 PM PDT 24
Peak memory 206200 kb
Host smart-3015dcdd-3c18-4425-b6a3-406dfec6a92d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1230358099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.1230358099
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.346074625
Short name T2520
Test name
Test status
Simulation time 3735927851 ps
CPU time 4.34 seconds
Started Jun 30 06:22:54 PM PDT 24
Finished Jun 30 06:22:59 PM PDT 24
Peak memory 206368 kb
Host smart-3934772e-08b9-4b10-8754-c97524efd4c9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=346074625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.346074625
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.3580357768
Short name T839
Test name
Test status
Simulation time 13363775924 ps
CPU time 12.09 seconds
Started Jun 30 06:22:56 PM PDT 24
Finished Jun 30 06:23:09 PM PDT 24
Peak memory 206644 kb
Host smart-729218cf-213e-4f74-9201-a9ee7f58dc43
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3580357768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.3580357768
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3046001845
Short name T1986
Test name
Test status
Simulation time 23346490548 ps
CPU time 21.28 seconds
Started Jun 30 06:22:53 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206452 kb
Host smart-7bcab628-e8e6-40a8-8a9a-bcfbffef0377
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3046001845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3046001845
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.168804893
Short name T445
Test name
Test status
Simulation time 257042309 ps
CPU time 0.95 seconds
Started Jun 30 06:22:53 PM PDT 24
Finished Jun 30 06:22:55 PM PDT 24
Peak memory 206180 kb
Host smart-a3033c05-4aa1-4922-9ef4-cccbad2cb435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16880
4893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.168804893
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1847635057
Short name T933
Test name
Test status
Simulation time 143020386 ps
CPU time 0.75 seconds
Started Jun 30 06:22:54 PM PDT 24
Finished Jun 30 06:22:56 PM PDT 24
Peak memory 206168 kb
Host smart-cf15e49c-f7ba-4b29-8a99-623e35c02c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18476
35057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1847635057
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3369533289
Short name T1454
Test name
Test status
Simulation time 336422101 ps
CPU time 1.15 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:22:59 PM PDT 24
Peak memory 206180 kb
Host smart-784c33b6-2eff-48d3-90f4-5d2c21714a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33695
33289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3369533289
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3520747289
Short name T2583
Test name
Test status
Simulation time 1211042994 ps
CPU time 2.57 seconds
Started Jun 30 06:22:55 PM PDT 24
Finished Jun 30 06:22:58 PM PDT 24
Peak memory 206360 kb
Host smart-6d1f442d-9a10-44a9-a36e-d9d88fd66beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35207
47289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3520747289
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.2387331425
Short name T832
Test name
Test status
Simulation time 17198183309 ps
CPU time 31.17 seconds
Started Jun 30 06:22:57 PM PDT 24
Finished Jun 30 06:23:29 PM PDT 24
Peak memory 206480 kb
Host smart-a578036f-c700-43a8-bfc2-6934bb85a5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23873
31425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.2387331425
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.139790961
Short name T828
Test name
Test status
Simulation time 434848701 ps
CPU time 1.37 seconds
Started Jun 30 06:22:55 PM PDT 24
Finished Jun 30 06:22:57 PM PDT 24
Peak memory 206176 kb
Host smart-6f15ccd3-be37-41c3-abdb-7470bc7bf58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13979
0961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.139790961
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.603304517
Short name T44
Test name
Test status
Simulation time 134866704 ps
CPU time 0.76 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:00 PM PDT 24
Peak memory 206144 kb
Host smart-521394e5-1d55-4d16-b6ea-4c92b76317fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60330
4517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.603304517
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2620227833
Short name T235
Test name
Test status
Simulation time 44650841 ps
CPU time 0.66 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:22:59 PM PDT 24
Peak memory 206156 kb
Host smart-4c990f70-e32f-4911-9865-3d7253f51bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26202
27833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2620227833
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1636794494
Short name T2629
Test name
Test status
Simulation time 829142470 ps
CPU time 2.1 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:01 PM PDT 24
Peak memory 206320 kb
Host smart-87b5faef-a1a9-4254-bede-9b82e9eccd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16367
94494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1636794494
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1941917079
Short name T1402
Test name
Test status
Simulation time 264280367 ps
CPU time 1.81 seconds
Started Jun 30 06:22:54 PM PDT 24
Finished Jun 30 06:22:57 PM PDT 24
Peak memory 206352 kb
Host smart-ceb9086d-9b32-4da4-850d-53eb16401b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19419
17079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1941917079
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2566407044
Short name T1827
Test name
Test status
Simulation time 210669751 ps
CPU time 0.86 seconds
Started Jun 30 06:22:56 PM PDT 24
Finished Jun 30 06:22:58 PM PDT 24
Peak memory 206188 kb
Host smart-cdaae568-03eb-4015-823f-9f12b41d98e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25664
07044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2566407044
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3389950461
Short name T23
Test name
Test status
Simulation time 171372148 ps
CPU time 0.76 seconds
Started Jun 30 06:22:53 PM PDT 24
Finished Jun 30 06:22:55 PM PDT 24
Peak memory 206172 kb
Host smart-f1e09d9a-23c7-4a7b-8aae-95a0fff03aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
50461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3389950461
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2407808266
Short name T687
Test name
Test status
Simulation time 204153557 ps
CPU time 0.85 seconds
Started Jun 30 06:22:57 PM PDT 24
Finished Jun 30 06:22:58 PM PDT 24
Peak memory 206200 kb
Host smart-36d3eca5-e4eb-420c-a476-c5ed451c2057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24078
08266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2407808266
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.4170567576
Short name T2037
Test name
Test status
Simulation time 6576789844 ps
CPU time 203.68 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:26:23 PM PDT 24
Peak memory 206492 kb
Host smart-07a09e5a-925e-42a7-8ee5-3dd8794b9969
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4170567576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.4170567576
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.106222446
Short name T1118
Test name
Test status
Simulation time 180273352 ps
CPU time 0.83 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:00 PM PDT 24
Peak memory 206172 kb
Host smart-6130e8c6-b2fa-461a-8bda-efdb20d12671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10622
2446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.106222446
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.3025851055
Short name T429
Test name
Test status
Simulation time 23346979260 ps
CPU time 21.94 seconds
Started Jun 30 06:22:55 PM PDT 24
Finished Jun 30 06:23:18 PM PDT 24
Peak memory 206264 kb
Host smart-449d5db3-4270-4d5a-b081-7744bd1ba9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30258
51055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.3025851055
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1612708215
Short name T758
Test name
Test status
Simulation time 3289988548 ps
CPU time 4.16 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:03 PM PDT 24
Peak memory 206204 kb
Host smart-54195de1-ac43-4cca-ae5f-7b26781c9dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16127
08215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1612708215
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.2055626812
Short name T1316
Test name
Test status
Simulation time 9085030876 ps
CPU time 249.17 seconds
Started Jun 30 06:22:53 PM PDT 24
Finished Jun 30 06:27:03 PM PDT 24
Peak memory 206468 kb
Host smart-97ab7f01-e8c0-45b1-8eec-ae69787cc760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20556
26812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.2055626812
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1230868768
Short name T145
Test name
Test status
Simulation time 4846198177 ps
CPU time 137.17 seconds
Started Jun 30 06:22:53 PM PDT 24
Finished Jun 30 06:25:10 PM PDT 24
Peak memory 206460 kb
Host smart-b4e6a276-2d70-40bb-9e6f-7046da5995dd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1230868768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1230868768
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.1832324204
Short name T2512
Test name
Test status
Simulation time 248992568 ps
CPU time 0.9 seconds
Started Jun 30 06:22:54 PM PDT 24
Finished Jun 30 06:22:56 PM PDT 24
Peak memory 206204 kb
Host smart-f7424237-f820-415f-be85-1e6434039e67
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1832324204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.1832324204
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.4007120894
Short name T1927
Test name
Test status
Simulation time 197306125 ps
CPU time 0.87 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:00 PM PDT 24
Peak memory 206168 kb
Host smart-086afd87-6567-4ecd-ba6a-64ad3d547520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40071
20894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.4007120894
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.1702782896
Short name T1819
Test name
Test status
Simulation time 6820068516 ps
CPU time 186.76 seconds
Started Jun 30 06:22:56 PM PDT 24
Finished Jun 30 06:26:04 PM PDT 24
Peak memory 206412 kb
Host smart-06f7fa8c-d1e8-45c2-bbbe-1f43db2a7965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17027
82896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.1702782896
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1549899257
Short name T2624
Test name
Test status
Simulation time 7730289798 ps
CPU time 78.81 seconds
Started Jun 30 06:22:54 PM PDT 24
Finished Jun 30 06:24:13 PM PDT 24
Peak memory 206408 kb
Host smart-de0d0d11-dcab-4132-b976-4e5b94300874
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1549899257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1549899257
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.2938131809
Short name T1839
Test name
Test status
Simulation time 168465018 ps
CPU time 0.83 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:00 PM PDT 24
Peak memory 206200 kb
Host smart-5375a194-05c0-4dc5-819a-67cbf76a21d1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2938131809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.2938131809
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3098263972
Short name T1268
Test name
Test status
Simulation time 147990846 ps
CPU time 0.75 seconds
Started Jun 30 06:22:57 PM PDT 24
Finished Jun 30 06:22:58 PM PDT 24
Peak memory 206188 kb
Host smart-74d68a7b-5a8d-4823-9cc0-9865f8ba7253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30982
63972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3098263972
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.408281260
Short name T542
Test name
Test status
Simulation time 212562657 ps
CPU time 0.86 seconds
Started Jun 30 06:22:57 PM PDT 24
Finished Jun 30 06:22:59 PM PDT 24
Peak memory 206184 kb
Host smart-5a30b189-8baa-4bbe-8d5d-33fc71b625af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40828
1260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.408281260
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1849733207
Short name T1627
Test name
Test status
Simulation time 183291178 ps
CPU time 0.88 seconds
Started Jun 30 06:22:56 PM PDT 24
Finished Jun 30 06:22:58 PM PDT 24
Peak memory 206400 kb
Host smart-d361ada0-eb30-4e6d-9265-4667332688b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18497
33207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1849733207
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1224383920
Short name T2328
Test name
Test status
Simulation time 206699939 ps
CPU time 0.85 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:00 PM PDT 24
Peak memory 206092 kb
Host smart-18250325-1b67-4b10-bcb8-0c5f043ef752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12243
83920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1224383920
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1190358349
Short name T147
Test name
Test status
Simulation time 172056206 ps
CPU time 0.79 seconds
Started Jun 30 06:22:56 PM PDT 24
Finished Jun 30 06:22:57 PM PDT 24
Peak memory 206192 kb
Host smart-4e429756-de9f-4295-8223-ddb871e0ce97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11903
58349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1190358349
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1172673886
Short name T1894
Test name
Test status
Simulation time 264961302 ps
CPU time 1 seconds
Started Jun 30 06:22:56 PM PDT 24
Finished Jun 30 06:22:57 PM PDT 24
Peak memory 206204 kb
Host smart-911b8b18-65f9-4467-8858-7cbc959776ac
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1172673886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1172673886
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.945748709
Short name T1783
Test name
Test status
Simulation time 36097105 ps
CPU time 0.65 seconds
Started Jun 30 06:22:56 PM PDT 24
Finished Jun 30 06:22:57 PM PDT 24
Peak memory 206188 kb
Host smart-2da3eb01-47c3-4481-a8d5-cc31c0348d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94574
8709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.945748709
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.297833116
Short name T2277
Test name
Test status
Simulation time 5509962285 ps
CPU time 13.2 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:12 PM PDT 24
Peak memory 206404 kb
Host smart-5785c1c4-59b5-445e-b18e-fa0287fee904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29783
3116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.297833116
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.981286427
Short name T2067
Test name
Test status
Simulation time 162379152 ps
CPU time 0.85 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:00 PM PDT 24
Peak memory 206188 kb
Host smart-6bc23540-3915-4175-8698-867a8d723a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98128
6427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.981286427
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.994820876
Short name T936
Test name
Test status
Simulation time 212831217 ps
CPU time 0.84 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:00 PM PDT 24
Peak memory 206172 kb
Host smart-1721ffd9-10ff-4ab2-a03f-e5d68f9bd3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99482
0876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.994820876
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3959143868
Short name T1942
Test name
Test status
Simulation time 169885601 ps
CPU time 0.82 seconds
Started Jun 30 06:22:54 PM PDT 24
Finished Jun 30 06:22:56 PM PDT 24
Peak memory 206196 kb
Host smart-3feaa4be-b37c-4b52-9db9-17ca92108702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39591
43868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3959143868
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2212806861
Short name T384
Test name
Test status
Simulation time 160082458 ps
CPU time 0.81 seconds
Started Jun 30 06:22:56 PM PDT 24
Finished Jun 30 06:22:58 PM PDT 24
Peak memory 206188 kb
Host smart-9d1fab2f-6651-4c01-ae7d-378bf366586d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22128
06861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2212806861
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2782274850
Short name T1483
Test name
Test status
Simulation time 208240666 ps
CPU time 0.86 seconds
Started Jun 30 06:22:56 PM PDT 24
Finished Jun 30 06:22:58 PM PDT 24
Peak memory 206392 kb
Host smart-5e1630f7-2e1d-4506-932f-05aa064657f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27822
74850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2782274850
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3302829551
Short name T865
Test name
Test status
Simulation time 145836115 ps
CPU time 0.79 seconds
Started Jun 30 06:22:57 PM PDT 24
Finished Jun 30 06:22:59 PM PDT 24
Peak memory 206184 kb
Host smart-dc3421ab-73b1-44d7-8c9c-78aa64740a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33028
29551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3302829551
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1314940912
Short name T699
Test name
Test status
Simulation time 147540184 ps
CPU time 0.77 seconds
Started Jun 30 06:22:56 PM PDT 24
Finished Jun 30 06:22:57 PM PDT 24
Peak memory 206396 kb
Host smart-87534706-67c4-4379-955e-cbffa460f5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13149
40912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1314940912
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2708542442
Short name T1385
Test name
Test status
Simulation time 260704155 ps
CPU time 1.02 seconds
Started Jun 30 06:22:54 PM PDT 24
Finished Jun 30 06:22:56 PM PDT 24
Peak memory 206200 kb
Host smart-04438a0c-0d1a-41ae-b4a1-e3ac092b0c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27085
42442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2708542442
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.4223439717
Short name T2398
Test name
Test status
Simulation time 4195481340 ps
CPU time 111.34 seconds
Started Jun 30 06:23:03 PM PDT 24
Finished Jun 30 06:24:56 PM PDT 24
Peak memory 206332 kb
Host smart-f0c1b33d-7a44-492a-8353-c67bedb012bb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4223439717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.4223439717
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2560311902
Short name T2278
Test name
Test status
Simulation time 150006004 ps
CPU time 0.83 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:02 PM PDT 24
Peak memory 206160 kb
Host smart-624959f9-ed28-4d60-a0cd-d061fbd38faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25603
11902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2560311902
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.4089415427
Short name T346
Test name
Test status
Simulation time 142105046 ps
CPU time 0.82 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:03 PM PDT 24
Peak memory 206156 kb
Host smart-73f19519-e58f-4199-b174-94f3cb0c8228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40894
15427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.4089415427
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.295961934
Short name T364
Test name
Test status
Simulation time 6424400877 ps
CPU time 51.34 seconds
Started Jun 30 06:23:03 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206320 kb
Host smart-edaba7c2-cb72-4eaa-a1aa-381a9aff32d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29596
1934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.295961934
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2063110470
Short name T397
Test name
Test status
Simulation time 46730771 ps
CPU time 0.65 seconds
Started Jun 30 06:23:08 PM PDT 24
Finished Jun 30 06:23:10 PM PDT 24
Peak memory 206184 kb
Host smart-bbdac503-952c-4b29-951b-b4deddaaf591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2063110470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2063110470
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2103450451
Short name T1647
Test name
Test status
Simulation time 4195983192 ps
CPU time 5.16 seconds
Started Jun 30 06:23:00 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206268 kb
Host smart-cdac1cc3-1800-4f43-b366-29988195797c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2103450451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.2103450451
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.4072315434
Short name T12
Test name
Test status
Simulation time 13411890323 ps
CPU time 13.4 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206396 kb
Host smart-9c42dda1-ad6c-4568-a188-a4d1cfb1d1e3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4072315434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.4072315434
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1719034195
Short name T1239
Test name
Test status
Simulation time 23404340894 ps
CPU time 24.46 seconds
Started Jun 30 06:23:00 PM PDT 24
Finished Jun 30 06:23:26 PM PDT 24
Peak memory 206436 kb
Host smart-f9fe5cf7-b64b-42bb-a6ed-ab890a1bfccc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1719034195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1719034195
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3574649317
Short name T455
Test name
Test status
Simulation time 146542620 ps
CPU time 0.84 seconds
Started Jun 30 06:23:02 PM PDT 24
Finished Jun 30 06:23:04 PM PDT 24
Peak memory 206196 kb
Host smart-8d913583-ebca-4d1e-aed1-2cbfe23e5ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35746
49317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3574649317
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3107314714
Short name T1621
Test name
Test status
Simulation time 146763901 ps
CPU time 0.78 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:03 PM PDT 24
Peak memory 206184 kb
Host smart-981e5f03-25e1-4cbb-844b-593905320b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31073
14714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3107314714
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1881038144
Short name T1248
Test name
Test status
Simulation time 408144202 ps
CPU time 1.33 seconds
Started Jun 30 06:23:03 PM PDT 24
Finished Jun 30 06:23:05 PM PDT 24
Peak memory 206184 kb
Host smart-065422a4-1d9e-46c8-a373-9b5d91a86c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18810
38144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1881038144
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3473517624
Short name T195
Test name
Test status
Simulation time 686801441 ps
CPU time 1.83 seconds
Started Jun 30 06:23:03 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206168 kb
Host smart-762fe925-d43a-4b7f-920e-d2e3abf819f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34735
17624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3473517624
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1621059990
Short name T1401
Test name
Test status
Simulation time 20041804244 ps
CPU time 37.63 seconds
Started Jun 30 06:23:04 PM PDT 24
Finished Jun 30 06:23:42 PM PDT 24
Peak memory 206356 kb
Host smart-7ade57cc-a51d-498a-a3af-687c0cb6af70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16210
59990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1621059990
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3187553040
Short name T671
Test name
Test status
Simulation time 444651072 ps
CPU time 1.37 seconds
Started Jun 30 06:23:00 PM PDT 24
Finished Jun 30 06:23:02 PM PDT 24
Peak memory 206196 kb
Host smart-59929cb5-96f5-4692-b59b-e8808d0563c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31875
53040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3187553040
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.710546289
Short name T2055
Test name
Test status
Simulation time 139322997 ps
CPU time 0.75 seconds
Started Jun 30 06:23:03 PM PDT 24
Finished Jun 30 06:23:04 PM PDT 24
Peak memory 206212 kb
Host smart-706427e9-2548-4733-9b43-1a09f45562f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71054
6289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.710546289
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2335106713
Short name T842
Test name
Test status
Simulation time 44604496 ps
CPU time 0.68 seconds
Started Jun 30 06:23:04 PM PDT 24
Finished Jun 30 06:23:05 PM PDT 24
Peak memory 206172 kb
Host smart-1c94a96e-1f2c-4413-a5b2-49c576e41d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23351
06713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2335106713
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2886347641
Short name T2076
Test name
Test status
Simulation time 936037185 ps
CPU time 2.14 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:04 PM PDT 24
Peak memory 206316 kb
Host smart-21ddea19-a78a-4863-9dff-b69f8c000af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28863
47641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2886347641
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2671642866
Short name T205
Test name
Test status
Simulation time 385721763 ps
CPU time 2.36 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:05 PM PDT 24
Peak memory 206280 kb
Host smart-4129375b-de6b-4c5c-8f76-43cf7a34b300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26716
42866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2671642866
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2915348275
Short name T983
Test name
Test status
Simulation time 198804446 ps
CPU time 0.84 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:03 PM PDT 24
Peak memory 206164 kb
Host smart-61bd8901-0389-41df-95c2-fb7c47bee3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29153
48275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2915348275
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.730433350
Short name T1493
Test name
Test status
Simulation time 139298310 ps
CPU time 0.75 seconds
Started Jun 30 06:23:04 PM PDT 24
Finished Jun 30 06:23:05 PM PDT 24
Peak memory 206068 kb
Host smart-67436a3b-9851-4a34-ab97-6f17d61b3497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73043
3350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.730433350
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3249663527
Short name T2090
Test name
Test status
Simulation time 195105913 ps
CPU time 0.78 seconds
Started Jun 30 06:23:05 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206192 kb
Host smart-ca253a6f-142b-4ba5-b9f6-53b694ab57bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32496
63527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3249663527
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.2159981497
Short name T719
Test name
Test status
Simulation time 9180783917 ps
CPU time 94.31 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206412 kb
Host smart-d90f4589-b12b-42b4-9103-753192b71e2e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2159981497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2159981497
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1470184284
Short name T103
Test name
Test status
Simulation time 185778749 ps
CPU time 0.84 seconds
Started Jun 30 06:23:04 PM PDT 24
Finished Jun 30 06:23:05 PM PDT 24
Peak memory 206080 kb
Host smart-32217d91-1b25-4acd-a9bf-69b0fa1f202c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14701
84284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1470184284
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3048849961
Short name T1955
Test name
Test status
Simulation time 23358080862 ps
CPU time 24.47 seconds
Started Jun 30 06:23:03 PM PDT 24
Finished Jun 30 06:23:28 PM PDT 24
Peak memory 206236 kb
Host smart-ee67ba8f-eed0-4a69-baf6-df202d5a1bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30488
49961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3048849961
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2473399850
Short name T2437
Test name
Test status
Simulation time 3283612433 ps
CPU time 4.42 seconds
Started Jun 30 06:23:03 PM PDT 24
Finished Jun 30 06:23:09 PM PDT 24
Peak memory 205356 kb
Host smart-a8f811f4-7500-4082-ae1f-8c5b70ea7871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24733
99850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2473399850
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.592155584
Short name T1883
Test name
Test status
Simulation time 5797883063 ps
CPU time 55.42 seconds
Started Jun 30 06:23:02 PM PDT 24
Finished Jun 30 06:23:58 PM PDT 24
Peak memory 206428 kb
Host smart-efb59bd7-3ff7-4194-88dd-40dcf23f74de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59215
5584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.592155584
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.746412909
Short name T1372
Test name
Test status
Simulation time 5896866937 ps
CPU time 170.86 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:25:53 PM PDT 24
Peak memory 206460 kb
Host smart-9308a8e4-4ec1-4a35-b760-8e5569983da0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=746412909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.746412909
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2452120965
Short name T698
Test name
Test status
Simulation time 238408376 ps
CPU time 0.9 seconds
Started Jun 30 06:23:04 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206216 kb
Host smart-32c0073b-a5c0-44dd-bb97-c85798b25d69
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2452120965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2452120965
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3630924941
Short name T78
Test name
Test status
Simulation time 189518482 ps
CPU time 0.88 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:02 PM PDT 24
Peak memory 206200 kb
Host smart-ec41ce7b-4edb-4116-a944-9c7510b7c3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36309
24941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3630924941
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1284327622
Short name T607
Test name
Test status
Simulation time 3995070388 ps
CPU time 26.85 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:29 PM PDT 24
Peak memory 206472 kb
Host smart-a8a1fde3-0f9a-4004-9d78-73a4c018e6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12843
27622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1284327622
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.4184000680
Short name T1780
Test name
Test status
Simulation time 4667754145 ps
CPU time 130.56 seconds
Started Jun 30 06:23:03 PM PDT 24
Finished Jun 30 06:25:14 PM PDT 24
Peak memory 206452 kb
Host smart-472fd682-09aa-4cb2-8f09-5a6e52da3942
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4184000680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.4184000680
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.4098783399
Short name T1866
Test name
Test status
Simulation time 170462678 ps
CPU time 0.79 seconds
Started Jun 30 06:23:04 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206200 kb
Host smart-da8e7743-3521-4a35-b62e-cf1a7fcac205
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4098783399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.4098783399
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3810184475
Short name T1509
Test name
Test status
Simulation time 139444583 ps
CPU time 0.74 seconds
Started Jun 30 06:23:05 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206180 kb
Host smart-c023c43d-ce72-45c4-a3d9-cd9911d2bdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38101
84475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3810184475
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1256819537
Short name T2633
Test name
Test status
Simulation time 203550488 ps
CPU time 0.95 seconds
Started Jun 30 06:23:03 PM PDT 24
Finished Jun 30 06:23:05 PM PDT 24
Peak memory 205312 kb
Host smart-a45121a1-e457-425b-8017-1d19878d7003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12568
19537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1256819537
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.670763648
Short name T2535
Test name
Test status
Simulation time 198839980 ps
CPU time 0.86 seconds
Started Jun 30 06:23:02 PM PDT 24
Finished Jun 30 06:23:03 PM PDT 24
Peak memory 206188 kb
Host smart-e5c923de-7e9a-464f-8d7f-461f084087d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67076
3648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.670763648
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1719844031
Short name T845
Test name
Test status
Simulation time 147846720 ps
CPU time 0.75 seconds
Started Jun 30 06:23:02 PM PDT 24
Finished Jun 30 06:23:04 PM PDT 24
Peak memory 206176 kb
Host smart-bcba15ec-4116-4cce-bebf-0c7abbfb4683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17198
44031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1719844031
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2271161234
Short name T969
Test name
Test status
Simulation time 200554964 ps
CPU time 0.87 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:03 PM PDT 24
Peak memory 206220 kb
Host smart-479d6740-ad6c-404e-a48a-51702eb87421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22711
61234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2271161234
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2394153423
Short name T169
Test name
Test status
Simulation time 143258293 ps
CPU time 0.83 seconds
Started Jun 30 06:23:02 PM PDT 24
Finished Jun 30 06:23:03 PM PDT 24
Peak memory 206244 kb
Host smart-f8dd5b3c-ffc5-4f5e-adca-87e2c5aede63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23941
53423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2394153423
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3656531031
Short name T762
Test name
Test status
Simulation time 180219728 ps
CPU time 0.86 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:03 PM PDT 24
Peak memory 206212 kb
Host smart-1b7601da-cee1-4978-ad05-54839098890c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3656531031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3656531031
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2000282472
Short name T1478
Test name
Test status
Simulation time 143576404 ps
CPU time 0.8 seconds
Started Jun 30 06:22:58 PM PDT 24
Finished Jun 30 06:23:00 PM PDT 24
Peak memory 206172 kb
Host smart-5fba9441-5c54-4dba-88ab-7a9037963bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20002
82472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2000282472
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2254381870
Short name T1575
Test name
Test status
Simulation time 32383136 ps
CPU time 0.68 seconds
Started Jun 30 06:23:01 PM PDT 24
Finished Jun 30 06:23:02 PM PDT 24
Peak memory 206188 kb
Host smart-e973f9a2-aaec-47f4-afbb-29120b3e2161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22543
81870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2254381870
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1119289515
Short name T88
Test name
Test status
Simulation time 20830328358 ps
CPU time 47.64 seconds
Started Jun 30 06:23:04 PM PDT 24
Finished Jun 30 06:23:53 PM PDT 24
Peak memory 206452 kb
Host smart-6efb4d64-e78f-4619-8fc4-eff449f37770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11192
89515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1119289515
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3002856555
Short name T1576
Test name
Test status
Simulation time 186520018 ps
CPU time 0.86 seconds
Started Jun 30 06:23:02 PM PDT 24
Finished Jun 30 06:23:04 PM PDT 24
Peak memory 206120 kb
Host smart-92cd365d-7096-44e9-bce9-be24e5e3fd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30028
56555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3002856555
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1884200009
Short name T862
Test name
Test status
Simulation time 234659202 ps
CPU time 0.9 seconds
Started Jun 30 06:23:04 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206200 kb
Host smart-9d8e9ab5-f8ff-4fdc-99da-c22388d0f643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18842
00009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1884200009
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3868127803
Short name T337
Test name
Test status
Simulation time 236400576 ps
CPU time 0.89 seconds
Started Jun 30 06:23:04 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206208 kb
Host smart-9904ddb1-6ee6-491a-9a56-3800206b30b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38681
27803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3868127803
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.3406556036
Short name T2584
Test name
Test status
Simulation time 157089493 ps
CPU time 0.81 seconds
Started Jun 30 06:23:02 PM PDT 24
Finished Jun 30 06:23:04 PM PDT 24
Peak memory 206180 kb
Host smart-6d132304-c470-4f1e-9946-9a1b85a8e9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34065
56036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.3406556036
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3333872035
Short name T487
Test name
Test status
Simulation time 136964858 ps
CPU time 0.73 seconds
Started Jun 30 06:23:08 PM PDT 24
Finished Jun 30 06:23:09 PM PDT 24
Peak memory 206184 kb
Host smart-57c3c0fd-47b9-4524-9d67-0d47a0f2a541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33338
72035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3333872035
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2684172981
Short name T989
Test name
Test status
Simulation time 168091863 ps
CPU time 0.82 seconds
Started Jun 30 06:23:05 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206200 kb
Host smart-2f46a163-2673-44cd-b77f-0df2baa6536e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26841
72981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2684172981
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1471092813
Short name T2241
Test name
Test status
Simulation time 189853418 ps
CPU time 0.81 seconds
Started Jun 30 06:23:08 PM PDT 24
Finished Jun 30 06:23:10 PM PDT 24
Peak memory 206188 kb
Host smart-bfcd4e0e-a40f-49c2-9255-d0b8eb1635dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14710
92813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1471092813
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3581509567
Short name T539
Test name
Test status
Simulation time 302439772 ps
CPU time 1.06 seconds
Started Jun 30 06:23:04 PM PDT 24
Finished Jun 30 06:23:06 PM PDT 24
Peak memory 206188 kb
Host smart-edf54940-249a-4cff-becd-05365a0f9e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35815
09567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3581509567
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1871185244
Short name T1551
Test name
Test status
Simulation time 4315403760 ps
CPU time 29.77 seconds
Started Jun 30 06:23:08 PM PDT 24
Finished Jun 30 06:23:39 PM PDT 24
Peak memory 206416 kb
Host smart-bc427389-6eb7-470a-afb9-d3fc9095f488
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1871185244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1871185244
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1919040721
Short name T605
Test name
Test status
Simulation time 202160356 ps
CPU time 0.86 seconds
Started Jun 30 06:23:06 PM PDT 24
Finished Jun 30 06:23:08 PM PDT 24
Peak memory 206152 kb
Host smart-5aba13d0-f83a-4dfc-b0a9-3a61293542bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19190
40721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1919040721
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1822656072
Short name T1790
Test name
Test status
Simulation time 184997680 ps
CPU time 0.83 seconds
Started Jun 30 06:23:09 PM PDT 24
Finished Jun 30 06:23:11 PM PDT 24
Peak memory 206168 kb
Host smart-b8480dbb-0c54-4a89-b4ed-6f5fc2dad295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18226
56072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1822656072
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1300354365
Short name T541
Test name
Test status
Simulation time 4408218092 ps
CPU time 38.9 seconds
Started Jun 30 06:23:13 PM PDT 24
Finished Jun 30 06:23:52 PM PDT 24
Peak memory 206476 kb
Host smart-259f130b-195f-40a9-82be-14f7595f669f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13003
54365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1300354365
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.349343570
Short name T472
Test name
Test status
Simulation time 50340059 ps
CPU time 0.67 seconds
Started Jun 30 06:20:33 PM PDT 24
Finished Jun 30 06:20:35 PM PDT 24
Peak memory 206228 kb
Host smart-f87daf34-6ad0-4854-858d-eb421b9c6357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=349343570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.349343570
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1836474875
Short name T1842
Test name
Test status
Simulation time 3682758508 ps
CPU time 4.18 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:33 PM PDT 24
Peak memory 206436 kb
Host smart-52cceff2-5608-479d-9c26-5aaba3c3a5de
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1836474875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.1836474875
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1671370089
Short name T540
Test name
Test status
Simulation time 13352759922 ps
CPU time 13.59 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:41 PM PDT 24
Peak memory 206356 kb
Host smart-27639a48-2a04-4495-beb5-31d71aeafca2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1671370089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1671370089
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2116003571
Short name T1211
Test name
Test status
Simulation time 23300689000 ps
CPU time 21.77 seconds
Started Jun 30 06:20:25 PM PDT 24
Finished Jun 30 06:20:50 PM PDT 24
Peak memory 206360 kb
Host smart-73587735-058b-4a27-8fe4-5c3dfe4fd190
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2116003571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.2116003571
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.87888773
Short name T2206
Test name
Test status
Simulation time 165906283 ps
CPU time 0.82 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:25 PM PDT 24
Peak memory 206200 kb
Host smart-e659deb9-88ab-4f58-bbcf-20d7968e5481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87888
773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.87888773
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.492450115
Short name T52
Test name
Test status
Simulation time 189716742 ps
CPU time 0.89 seconds
Started Jun 30 06:20:23 PM PDT 24
Finished Jun 30 06:20:25 PM PDT 24
Peak memory 206204 kb
Host smart-5d4beb89-7821-4745-80b1-a08598c9e8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49245
0115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.492450115
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1584734029
Short name T732
Test name
Test status
Simulation time 168378871 ps
CPU time 0.79 seconds
Started Jun 30 06:20:24 PM PDT 24
Finished Jun 30 06:20:28 PM PDT 24
Peak memory 206168 kb
Host smart-9ec48da8-1566-481f-b0f0-c7a0fbe85913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15847
34029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1584734029
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3774943640
Short name T2553
Test name
Test status
Simulation time 160003854 ps
CPU time 0.83 seconds
Started Jun 30 06:20:29 PM PDT 24
Finished Jun 30 06:20:31 PM PDT 24
Peak memory 206184 kb
Host smart-66aeb05f-359e-4e28-b962-849e9bc89df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37749
43640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3774943640
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.4209682512
Short name T897
Test name
Test status
Simulation time 599213841 ps
CPU time 1.48 seconds
Started Jun 30 06:20:29 PM PDT 24
Finished Jun 30 06:20:32 PM PDT 24
Peak memory 206188 kb
Host smart-319395b4-65f4-4535-96ca-55732267de6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42096
82512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.4209682512
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.325721567
Short name T1360
Test name
Test status
Simulation time 16331307974 ps
CPU time 30.47 seconds
Started Jun 30 06:20:28 PM PDT 24
Finished Jun 30 06:21:00 PM PDT 24
Peak memory 206412 kb
Host smart-d855fb90-ace0-43e9-8884-26cbbaaa0a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32572
1567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.325721567
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1063751765
Short name T972
Test name
Test status
Simulation time 396811529 ps
CPU time 1.2 seconds
Started Jun 30 06:20:28 PM PDT 24
Finished Jun 30 06:20:31 PM PDT 24
Peak memory 206212 kb
Host smart-e1387656-ab1d-4ad3-90e5-bc767ec560fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10637
51765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1063751765
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2351774349
Short name T2498
Test name
Test status
Simulation time 214289250 ps
CPU time 0.86 seconds
Started Jun 30 06:20:32 PM PDT 24
Finished Jun 30 06:20:34 PM PDT 24
Peak memory 206144 kb
Host smart-dcf7adf9-c6be-40e1-aa4f-04e61482fc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23517
74349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2351774349
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1567587536
Short name T1405
Test name
Test status
Simulation time 32544943 ps
CPU time 0.66 seconds
Started Jun 30 06:20:31 PM PDT 24
Finished Jun 30 06:20:33 PM PDT 24
Peak memory 206176 kb
Host smart-05c40ba3-8601-4cc7-9407-9d0e612dc38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15675
87536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1567587536
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3767069848
Short name T1754
Test name
Test status
Simulation time 950790030 ps
CPU time 2.16 seconds
Started Jun 30 06:20:31 PM PDT 24
Finished Jun 30 06:20:34 PM PDT 24
Peak memory 206440 kb
Host smart-66bc70cd-3527-431d-99ca-6a459d6ce114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37670
69848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3767069848
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1853216578
Short name T1373
Test name
Test status
Simulation time 206913500 ps
CPU time 1.42 seconds
Started Jun 30 06:20:28 PM PDT 24
Finished Jun 30 06:20:31 PM PDT 24
Peak memory 206280 kb
Host smart-10170cdf-8e78-44d7-bd5d-93754a880f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18532
16578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1853216578
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3061629937
Short name T604
Test name
Test status
Simulation time 170735538 ps
CPU time 0.78 seconds
Started Jun 30 06:20:31 PM PDT 24
Finished Jun 30 06:20:32 PM PDT 24
Peak memory 206204 kb
Host smart-4a8e16f2-166d-42c8-af61-00b78166485b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30616
29937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3061629937
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3654849410
Short name T1518
Test name
Test status
Simulation time 178580353 ps
CPU time 0.82 seconds
Started Jun 30 06:20:29 PM PDT 24
Finished Jun 30 06:20:32 PM PDT 24
Peak memory 206212 kb
Host smart-d1ef9db5-678a-4485-abe6-fd6df4fbd9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36548
49410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3654849410
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2998532104
Short name T77
Test name
Test status
Simulation time 235316040 ps
CPU time 0.98 seconds
Started Jun 30 06:20:29 PM PDT 24
Finished Jun 30 06:20:32 PM PDT 24
Peak memory 206208 kb
Host smart-81f693b0-b825-4624-8bb8-fcaef747bf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29985
32104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2998532104
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.4134588781
Short name T2054
Test name
Test status
Simulation time 9899322298 ps
CPU time 92.44 seconds
Started Jun 30 06:20:31 PM PDT 24
Finished Jun 30 06:22:04 PM PDT 24
Peak memory 206368 kb
Host smart-d09f9116-cc3f-46a7-90e3-9c398a982a33
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4134588781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.4134588781
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2178116022
Short name T482
Test name
Test status
Simulation time 224596262 ps
CPU time 0.9 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:36 PM PDT 24
Peak memory 206040 kb
Host smart-b5711251-ad7b-4b50-9145-a3b99ea9feb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21781
16022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2178116022
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1163132018
Short name T1656
Test name
Test status
Simulation time 23325857523 ps
CPU time 25.61 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:55 PM PDT 24
Peak memory 206312 kb
Host smart-6f62e459-895c-4a63-b4e0-cbce23db8913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11631
32018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1163132018
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3607264214
Short name T1080
Test name
Test status
Simulation time 3329119657 ps
CPU time 3.74 seconds
Started Jun 30 06:20:33 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206236 kb
Host smart-049b6cf0-f220-4155-b0f2-e1e901772239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36072
64214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3607264214
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.1543290188
Short name T2119
Test name
Test status
Simulation time 5439257034 ps
CPU time 39.7 seconds
Started Jun 30 06:20:32 PM PDT 24
Finished Jun 30 06:21:13 PM PDT 24
Peak memory 206404 kb
Host smart-33081572-960a-4381-a698-9fef48265e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15432
90188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.1543290188
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3522022728
Short name T1111
Test name
Test status
Simulation time 5642270230 ps
CPU time 148.88 seconds
Started Jun 30 06:20:29 PM PDT 24
Finished Jun 30 06:22:59 PM PDT 24
Peak memory 206456 kb
Host smart-143df1dc-b24a-44ce-818c-7cb3cfa002d3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3522022728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3522022728
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2859345724
Short name T1963
Test name
Test status
Simulation time 263471658 ps
CPU time 0.93 seconds
Started Jun 30 06:20:29 PM PDT 24
Finished Jun 30 06:20:31 PM PDT 24
Peak memory 206168 kb
Host smart-0e3df180-d40d-40f2-b459-a96f11b52f39
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2859345724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2859345724
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2110576389
Short name T1909
Test name
Test status
Simulation time 190491380 ps
CPU time 0.86 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:30 PM PDT 24
Peak memory 206208 kb
Host smart-00604e87-f82f-4a05-a8f5-4101bd3f3e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21105
76389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2110576389
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.4252540207
Short name T1056
Test name
Test status
Simulation time 3852167276 ps
CPU time 34.72 seconds
Started Jun 30 06:20:31 PM PDT 24
Finished Jun 30 06:21:07 PM PDT 24
Peak memory 206508 kb
Host smart-29ceb95d-e1bb-49b3-9044-d9f061b93d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42525
40207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.4252540207
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3087522971
Short name T4
Test name
Test status
Simulation time 4075569438 ps
CPU time 114.43 seconds
Started Jun 30 06:20:29 PM PDT 24
Finished Jun 30 06:22:25 PM PDT 24
Peak memory 206452 kb
Host smart-ed9732f9-2b74-4f11-80da-0a84da74aec7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3087522971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3087522971
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.376585048
Short name T2096
Test name
Test status
Simulation time 158003992 ps
CPU time 0.76 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:30 PM PDT 24
Peak memory 206188 kb
Host smart-63054bfc-b12c-4aab-9aa9-581047250535
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=376585048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.376585048
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3909976367
Short name T731
Test name
Test status
Simulation time 149212119 ps
CPU time 0.76 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:30 PM PDT 24
Peak memory 206200 kb
Host smart-075ea190-6457-456e-b75e-c70c88c9f3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39099
76367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3909976367
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2580880395
Short name T1904
Test name
Test status
Simulation time 192825772 ps
CPU time 0.82 seconds
Started Jun 30 06:20:31 PM PDT 24
Finished Jun 30 06:20:33 PM PDT 24
Peak memory 206160 kb
Host smart-79a81d6f-c6d2-40cc-bef7-8fcc31d8b987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25808
80395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2580880395
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1484112800
Short name T2597
Test name
Test status
Simulation time 182183249 ps
CPU time 0.85 seconds
Started Jun 30 06:20:26 PM PDT 24
Finished Jun 30 06:20:29 PM PDT 24
Peak memory 206176 kb
Host smart-1010959d-cb4d-4933-91b8-d118139ede10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14841
12800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1484112800
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1760343162
Short name T374
Test name
Test status
Simulation time 169157420 ps
CPU time 0.81 seconds
Started Jun 30 06:20:30 PM PDT 24
Finished Jun 30 06:20:32 PM PDT 24
Peak memory 206176 kb
Host smart-89cbf3fd-5da1-4805-97da-7c59385e5d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17603
43162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1760343162
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1927173685
Short name T2276
Test name
Test status
Simulation time 154431928 ps
CPU time 0.83 seconds
Started Jun 30 06:20:32 PM PDT 24
Finished Jun 30 06:20:34 PM PDT 24
Peak memory 206176 kb
Host smart-20d514ad-9757-451d-a129-ed94834b647b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19271
73685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1927173685
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3555219432
Short name T2613
Test name
Test status
Simulation time 194629333 ps
CPU time 0.93 seconds
Started Jun 30 06:20:33 PM PDT 24
Finished Jun 30 06:20:35 PM PDT 24
Peak memory 206196 kb
Host smart-41d51944-d080-4a8c-a164-aa1e40a1fb31
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3555219432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3555219432
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1854182605
Short name T224
Test name
Test status
Simulation time 221378413 ps
CPU time 0.95 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:30 PM PDT 24
Peak memory 206200 kb
Host smart-fab3650e-7eae-4de6-9a9d-145323b1d112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18541
82605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1854182605
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2976473235
Short name T1524
Test name
Test status
Simulation time 182386426 ps
CPU time 0.84 seconds
Started Jun 30 06:20:33 PM PDT 24
Finished Jun 30 06:20:35 PM PDT 24
Peak memory 206196 kb
Host smart-ea7bab0b-b294-460c-9d00-1eff473ceff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29764
73235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2976473235
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3285296329
Short name T2210
Test name
Test status
Simulation time 48622376 ps
CPU time 0.66 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:36 PM PDT 24
Peak memory 206004 kb
Host smart-c7a7106f-28d9-4ed5-9d74-24654377e0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32852
96329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3285296329
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3985761120
Short name T2160
Test name
Test status
Simulation time 11865948927 ps
CPU time 25.54 seconds
Started Jun 30 06:20:27 PM PDT 24
Finished Jun 30 06:20:55 PM PDT 24
Peak memory 206468 kb
Host smart-eccdda00-cafd-4905-9aed-184cfca65e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39857
61120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3985761120
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.116922157
Short name T2078
Test name
Test status
Simulation time 167315427 ps
CPU time 0.93 seconds
Started Jun 30 06:20:31 PM PDT 24
Finished Jun 30 06:20:33 PM PDT 24
Peak memory 206180 kb
Host smart-dc76e632-da53-4d07-a1e4-81b1f0623284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11692
2157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.116922157
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2136406764
Short name T712
Test name
Test status
Simulation time 247519938 ps
CPU time 0.91 seconds
Started Jun 30 06:20:32 PM PDT 24
Finished Jun 30 06:20:34 PM PDT 24
Peak memory 206176 kb
Host smart-5dfd0ce9-4513-4343-afcc-1be1d0f499a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21364
06764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2136406764
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.870053725
Short name T554
Test name
Test status
Simulation time 11968881850 ps
CPU time 59.09 seconds
Started Jun 30 06:20:32 PM PDT 24
Finished Jun 30 06:21:32 PM PDT 24
Peak memory 206388 kb
Host smart-156809a0-c10c-418d-9da4-a9f01aad20ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=870053725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.870053725
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2263303981
Short name T163
Test name
Test status
Simulation time 10288629238 ps
CPU time 174.35 seconds
Started Jun 30 06:20:33 PM PDT 24
Finished Jun 30 06:23:28 PM PDT 24
Peak memory 206460 kb
Host smart-05821115-2491-482d-a6f2-b279fea5efea
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2263303981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2263303981
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3909976009
Short name T1099
Test name
Test status
Simulation time 17326350272 ps
CPU time 102.85 seconds
Started Jun 30 06:20:31 PM PDT 24
Finished Jun 30 06:22:15 PM PDT 24
Peak memory 206484 kb
Host smart-630453ff-0710-4a4f-aaec-fd3c931b8c86
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3909976009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3909976009
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.940456905
Short name T1722
Test name
Test status
Simulation time 172643630 ps
CPU time 0.77 seconds
Started Jun 30 06:20:30 PM PDT 24
Finished Jun 30 06:20:32 PM PDT 24
Peak memory 206184 kb
Host smart-e01beeea-882b-4790-86d6-1ff6791d881d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94045
6905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.940456905
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1179544235
Short name T1150
Test name
Test status
Simulation time 179919761 ps
CPU time 0.82 seconds
Started Jun 30 06:20:31 PM PDT 24
Finished Jun 30 06:20:33 PM PDT 24
Peak memory 206180 kb
Host smart-e5f35b2d-6831-4efd-8cc7-35b11a2f8c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11795
44235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1179544235
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2729116449
Short name T1773
Test name
Test status
Simulation time 171287110 ps
CPU time 0.8 seconds
Started Jun 30 06:20:32 PM PDT 24
Finished Jun 30 06:20:34 PM PDT 24
Peak memory 206164 kb
Host smart-4c9b6bd2-38b1-4838-a8eb-696a4a996a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27291
16449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2729116449
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.3263159430
Short name T2603
Test name
Test status
Simulation time 164006306 ps
CPU time 0.79 seconds
Started Jun 30 06:20:32 PM PDT 24
Finished Jun 30 06:20:34 PM PDT 24
Peak memory 206204 kb
Host smart-3b816542-be22-436e-875d-d4458b9aca2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32631
59430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3263159430
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1453532906
Short name T215
Test name
Test status
Simulation time 798770031 ps
CPU time 1.61 seconds
Started Jun 30 06:20:41 PM PDT 24
Finished Jun 30 06:20:43 PM PDT 24
Peak memory 225088 kb
Host smart-77b400a0-fff6-48e5-8cee-e80b8dfd729a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1453532906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1453532906
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3174058441
Short name T54
Test name
Test status
Simulation time 341456754 ps
CPU time 1.21 seconds
Started Jun 30 06:20:32 PM PDT 24
Finished Jun 30 06:20:34 PM PDT 24
Peak memory 206176 kb
Host smart-95c60c21-6397-48c5-84ef-d43a615de2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31740
58441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3174058441
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3761515128
Short name T718
Test name
Test status
Simulation time 349775521 ps
CPU time 1.06 seconds
Started Jun 30 06:20:29 PM PDT 24
Finished Jun 30 06:20:32 PM PDT 24
Peak memory 206360 kb
Host smart-f35d022d-6694-4b42-bd50-18a605727829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37615
15128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3761515128
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.158838256
Short name T1876
Test name
Test status
Simulation time 151415665 ps
CPU time 0.78 seconds
Started Jun 30 06:20:29 PM PDT 24
Finished Jun 30 06:20:31 PM PDT 24
Peak memory 206188 kb
Host smart-18d8ff7f-c216-4a47-b9ab-7b187d806b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15883
8256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.158838256
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3201076774
Short name T1057
Test name
Test status
Simulation time 156065916 ps
CPU time 0.81 seconds
Started Jun 30 06:20:32 PM PDT 24
Finished Jun 30 06:20:34 PM PDT 24
Peak memory 206160 kb
Host smart-236be325-b01e-4cb3-bb92-94179fa18108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32010
76774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3201076774
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.942344673
Short name T408
Test name
Test status
Simulation time 260458497 ps
CPU time 1.03 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:37 PM PDT 24
Peak memory 206160 kb
Host smart-5ac50a40-d506-4720-8e82-ca163a076fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94234
4673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.942344673
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1540316140
Short name T2600
Test name
Test status
Simulation time 4323124713 ps
CPU time 40.42 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:21:16 PM PDT 24
Peak memory 206336 kb
Host smart-880184f9-ecb4-43c8-bb95-2d9c34bff0b0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1540316140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1540316140
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3386798335
Short name T1811
Test name
Test status
Simulation time 171215159 ps
CPU time 0.84 seconds
Started Jun 30 06:20:35 PM PDT 24
Finished Jun 30 06:20:37 PM PDT 24
Peak memory 206220 kb
Host smart-76713f6b-89fb-49d7-90ce-9c00b7cc9e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33867
98335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3386798335
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2376981343
Short name T1263
Test name
Test status
Simulation time 196906647 ps
CPU time 0.85 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206164 kb
Host smart-40be33b3-b2e3-4554-8e3e-94081490a77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23769
81343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2376981343
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.3175774027
Short name T381
Test name
Test status
Simulation time 3442890005 ps
CPU time 25.39 seconds
Started Jun 30 06:20:35 PM PDT 24
Finished Jun 30 06:21:02 PM PDT 24
Peak memory 206436 kb
Host smart-4e4a164c-8011-4ece-8cfe-6889dddcbec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31757
74027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.3175774027
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2268813351
Short name T262
Test name
Test status
Simulation time 17133174913 ps
CPU time 362.02 seconds
Started Jun 30 06:20:35 PM PDT 24
Finished Jun 30 06:26:39 PM PDT 24
Peak memory 206500 kb
Host smart-81700d5d-5598-429c-83fe-0ee0a57dadf0
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2268813351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2268813351
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3829782914
Short name T1993
Test name
Test status
Simulation time 61785307 ps
CPU time 0.69 seconds
Started Jun 30 06:23:16 PM PDT 24
Finished Jun 30 06:23:17 PM PDT 24
Peak memory 206208 kb
Host smart-5fd6d299-2e48-411a-92a9-fa97fa27242f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3829782914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3829782914
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2851667041
Short name T2418
Test name
Test status
Simulation time 13371109527 ps
CPU time 11.86 seconds
Started Jun 30 06:23:07 PM PDT 24
Finished Jun 30 06:23:19 PM PDT 24
Peak memory 206400 kb
Host smart-753fa4c6-1e37-4070-a562-e3883894c137
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2851667041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2851667041
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1210542301
Short name T1479
Test name
Test status
Simulation time 23332729639 ps
CPU time 22.92 seconds
Started Jun 30 06:23:07 PM PDT 24
Finished Jun 30 06:23:35 PM PDT 24
Peak memory 206384 kb
Host smart-2458f596-6dac-4c45-96ca-6194cbfa7410
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1210542301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1210542301
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2987585771
Short name T2521
Test name
Test status
Simulation time 156630186 ps
CPU time 0.77 seconds
Started Jun 30 06:23:09 PM PDT 24
Finished Jun 30 06:23:10 PM PDT 24
Peak memory 206192 kb
Host smart-898ab887-d759-4948-95d8-eb356a99cc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29875
85771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2987585771
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3191264905
Short name T856
Test name
Test status
Simulation time 166472405 ps
CPU time 0.82 seconds
Started Jun 30 06:23:10 PM PDT 24
Finished Jun 30 06:23:11 PM PDT 24
Peak memory 206196 kb
Host smart-6ff6592b-4c2b-42a7-b787-3577593abce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31912
64905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3191264905
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3259760827
Short name T710
Test name
Test status
Simulation time 303152187 ps
CPU time 1.16 seconds
Started Jun 30 06:23:06 PM PDT 24
Finished Jun 30 06:23:08 PM PDT 24
Peak memory 206168 kb
Host smart-e64de702-0eef-49dd-b33c-96bd3ee7a586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32597
60827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3259760827
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2492782757
Short name T179
Test name
Test status
Simulation time 748849235 ps
CPU time 1.86 seconds
Started Jun 30 06:23:07 PM PDT 24
Finished Jun 30 06:23:09 PM PDT 24
Peak memory 206332 kb
Host smart-c6241c9b-972e-425b-bc4a-689d1fbf72e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24927
82757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2492782757
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.332909138
Short name T2551
Test name
Test status
Simulation time 13772076662 ps
CPU time 24.45 seconds
Started Jun 30 06:23:06 PM PDT 24
Finished Jun 30 06:23:31 PM PDT 24
Peak memory 206492 kb
Host smart-52687cff-4615-4a2b-8b71-0591ef580969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33290
9138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.332909138
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.963476119
Short name T819
Test name
Test status
Simulation time 379780033 ps
CPU time 1.2 seconds
Started Jun 30 06:23:09 PM PDT 24
Finished Jun 30 06:23:11 PM PDT 24
Peak memory 206216 kb
Host smart-1e42c1ab-b39e-473d-bfcf-73052f1b6524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96347
6119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.963476119
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2712638131
Short name T829
Test name
Test status
Simulation time 136602030 ps
CPU time 0.73 seconds
Started Jun 30 06:23:08 PM PDT 24
Finished Jun 30 06:23:09 PM PDT 24
Peak memory 206180 kb
Host smart-af7df405-85eb-41fc-a8f1-e10012ff2adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27126
38131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2712638131
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.2805371742
Short name T386
Test name
Test status
Simulation time 56943692 ps
CPU time 0.71 seconds
Started Jun 30 06:23:08 PM PDT 24
Finished Jun 30 06:23:10 PM PDT 24
Peak memory 206184 kb
Host smart-0151372d-a302-4969-b9f9-a9dd3c10a609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053
71742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2805371742
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2182808584
Short name T1789
Test name
Test status
Simulation time 940828287 ps
CPU time 2.37 seconds
Started Jun 30 06:23:09 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206176 kb
Host smart-183f4614-6401-4bae-adfc-51929011339f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21828
08584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2182808584
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.930678151
Short name T898
Test name
Test status
Simulation time 348506497 ps
CPU time 2.22 seconds
Started Jun 30 06:23:11 PM PDT 24
Finished Jun 30 06:23:14 PM PDT 24
Peak memory 206324 kb
Host smart-8ff946fb-4baf-4149-8cb0-a974796948ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93067
8151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.930678151
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.257208439
Short name T2155
Test name
Test status
Simulation time 187491360 ps
CPU time 0.9 seconds
Started Jun 30 06:23:08 PM PDT 24
Finished Jun 30 06:23:10 PM PDT 24
Peak memory 206132 kb
Host smart-149412b4-4a93-4fff-a5f4-39ab641c5e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25720
8439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.257208439
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1754270553
Short name T1002
Test name
Test status
Simulation time 145248470 ps
CPU time 0.78 seconds
Started Jun 30 06:23:06 PM PDT 24
Finished Jun 30 06:23:07 PM PDT 24
Peak memory 206184 kb
Host smart-10d042c3-04d4-4001-bc12-f3910cd2c26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17542
70553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1754270553
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3461474603
Short name T1416
Test name
Test status
Simulation time 171821428 ps
CPU time 0.87 seconds
Started Jun 30 06:23:07 PM PDT 24
Finished Jun 30 06:23:08 PM PDT 24
Peak memory 206168 kb
Host smart-51038fb8-1829-48af-b361-47593aadb36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34614
74603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3461474603
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.4130843647
Short name T1455
Test name
Test status
Simulation time 212649281 ps
CPU time 0.83 seconds
Started Jun 30 06:23:09 PM PDT 24
Finished Jun 30 06:23:14 PM PDT 24
Peak memory 206164 kb
Host smart-e241bd52-3e59-41ca-8512-66005ad60daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41308
43647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.4130843647
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.1751842417
Short name T1849
Test name
Test status
Simulation time 23294326198 ps
CPU time 22.44 seconds
Started Jun 30 06:23:07 PM PDT 24
Finished Jun 30 06:23:30 PM PDT 24
Peak memory 206284 kb
Host smart-a288c5ed-8e5e-4650-a1a7-aeb9cbb0a51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17518
42417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1751842417
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.443229334
Short name T1828
Test name
Test status
Simulation time 3343760298 ps
CPU time 3.59 seconds
Started Jun 30 06:23:07 PM PDT 24
Finished Jun 30 06:23:11 PM PDT 24
Peak memory 206228 kb
Host smart-62f8e336-cec3-4bbc-9caa-de32bccadb9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44322
9334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.443229334
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.2986415719
Short name T2449
Test name
Test status
Simulation time 7143873040 ps
CPU time 201.06 seconds
Started Jun 30 06:23:12 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206468 kb
Host smart-981ed89f-6fe6-4e0a-8973-8cf498d93bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29864
15719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.2986415719
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.1940168972
Short name T2107
Test name
Test status
Simulation time 3572457719 ps
CPU time 96.07 seconds
Started Jun 30 06:23:06 PM PDT 24
Finished Jun 30 06:24:43 PM PDT 24
Peak memory 206440 kb
Host smart-cada9fb5-f576-48ba-a672-20f555185e42
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1940168972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.1940168972
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.749558819
Short name T370
Test name
Test status
Simulation time 242699681 ps
CPU time 0.9 seconds
Started Jun 30 06:23:09 PM PDT 24
Finished Jun 30 06:23:11 PM PDT 24
Peak memory 206072 kb
Host smart-54c2103b-9538-458e-9758-47bc52f64c7c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=749558819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.749558819
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.38257235
Short name T1280
Test name
Test status
Simulation time 212450210 ps
CPU time 0.89 seconds
Started Jun 30 06:23:10 PM PDT 24
Finished Jun 30 06:23:16 PM PDT 24
Peak memory 206196 kb
Host smart-e2234df0-be08-49c7-9589-716c306b377e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38257
235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.38257235
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.4120272047
Short name T1188
Test name
Test status
Simulation time 6363860514 ps
CPU time 43.43 seconds
Started Jun 30 06:23:06 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206516 kb
Host smart-b39f9506-e24a-4d9c-aec9-7f7fa91edc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41202
72047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.4120272047
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1645186666
Short name T1006
Test name
Test status
Simulation time 3555589988 ps
CPU time 33.24 seconds
Started Jun 30 06:23:10 PM PDT 24
Finished Jun 30 06:23:43 PM PDT 24
Peak memory 206416 kb
Host smart-cba8613a-7a36-47e1-8395-35987da7c63b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1645186666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1645186666
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1778108863
Short name T2129
Test name
Test status
Simulation time 169636623 ps
CPU time 0.78 seconds
Started Jun 30 06:23:08 PM PDT 24
Finished Jun 30 06:23:09 PM PDT 24
Peak memory 206236 kb
Host smart-40797047-472e-4ce9-a532-8e049b5c9f8d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1778108863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1778108863
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.994591568
Short name T577
Test name
Test status
Simulation time 159288725 ps
CPU time 0.76 seconds
Started Jun 30 06:23:09 PM PDT 24
Finished Jun 30 06:23:14 PM PDT 24
Peak memory 206180 kb
Host smart-1f13c4b2-b307-4594-afa4-cc351516b09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99459
1568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.994591568
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.776802541
Short name T2059
Test name
Test status
Simulation time 184149485 ps
CPU time 0.79 seconds
Started Jun 30 06:23:08 PM PDT 24
Finished Jun 30 06:23:10 PM PDT 24
Peak memory 206048 kb
Host smart-be6367af-28ad-43a6-9771-dc62ea6dbcd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77680
2541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.776802541
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3844099345
Short name T20
Test name
Test status
Simulation time 212233338 ps
CPU time 0.87 seconds
Started Jun 30 06:23:09 PM PDT 24
Finished Jun 30 06:23:11 PM PDT 24
Peak memory 206200 kb
Host smart-426f2ffe-f103-45d5-87c1-fba88de56012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38440
99345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3844099345
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3359304967
Short name T340
Test name
Test status
Simulation time 176002025 ps
CPU time 0.82 seconds
Started Jun 30 06:23:28 PM PDT 24
Finished Jun 30 06:23:29 PM PDT 24
Peak memory 206204 kb
Host smart-6f4ce5e5-79ca-4c4b-a1b8-d8fa3ffc2dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33593
04967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3359304967
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.601592472
Short name T1429
Test name
Test status
Simulation time 184517108 ps
CPU time 0.82 seconds
Started Jun 30 06:23:18 PM PDT 24
Finished Jun 30 06:23:19 PM PDT 24
Peak memory 206380 kb
Host smart-7469d185-0747-490c-866b-c5ab169b9219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60159
2472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.601592472
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1706278115
Short name T747
Test name
Test status
Simulation time 199677049 ps
CPU time 0.85 seconds
Started Jun 30 06:23:13 PM PDT 24
Finished Jun 30 06:23:14 PM PDT 24
Peak memory 206204 kb
Host smart-5a0fc69c-856c-4a7e-957e-ac1348566a5e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1706278115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1706278115
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1152195835
Short name T2224
Test name
Test status
Simulation time 156364710 ps
CPU time 0.8 seconds
Started Jun 30 06:23:28 PM PDT 24
Finished Jun 30 06:23:29 PM PDT 24
Peak memory 206052 kb
Host smart-42447582-1a72-4347-9524-48ec687bb8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11521
95835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1152195835
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3339861821
Short name T793
Test name
Test status
Simulation time 75086255 ps
CPU time 0.72 seconds
Started Jun 30 06:23:14 PM PDT 24
Finished Jun 30 06:23:16 PM PDT 24
Peak memory 206188 kb
Host smart-b1199474-4a48-4d93-a20b-beeddd5c0ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33398
61821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3339861821
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.402193194
Short name T263
Test name
Test status
Simulation time 8688825488 ps
CPU time 19.88 seconds
Started Jun 30 06:23:15 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 214620 kb
Host smart-2e5347c4-a5a4-4d76-bebb-2193671ed03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40219
3194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.402193194
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3130788387
Short name T1312
Test name
Test status
Simulation time 197052451 ps
CPU time 0.85 seconds
Started Jun 30 06:23:14 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206180 kb
Host smart-82fa34c9-3d6b-4847-a629-a48cebf13093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31307
88387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3130788387
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1915621851
Short name T2142
Test name
Test status
Simulation time 204098260 ps
CPU time 0.89 seconds
Started Jun 30 06:23:12 PM PDT 24
Finished Jun 30 06:23:13 PM PDT 24
Peak memory 206212 kb
Host smart-7ec55208-c0eb-41b3-8141-4d0085235c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19156
21851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1915621851
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.2415557877
Short name T422
Test name
Test status
Simulation time 184733192 ps
CPU time 0.85 seconds
Started Jun 30 06:23:13 PM PDT 24
Finished Jun 30 06:23:14 PM PDT 24
Peak memory 206212 kb
Host smart-b9ee397b-b233-4077-8c96-028d67de2bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24155
57877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.2415557877
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3650820893
Short name T1570
Test name
Test status
Simulation time 193994956 ps
CPU time 0.88 seconds
Started Jun 30 06:23:15 PM PDT 24
Finished Jun 30 06:23:17 PM PDT 24
Peak memory 206184 kb
Host smart-c0b3b0cb-56db-4466-b340-a59c695a2a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36508
20893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3650820893
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3149078171
Short name T2258
Test name
Test status
Simulation time 181190968 ps
CPU time 0.81 seconds
Started Jun 30 06:23:13 PM PDT 24
Finished Jun 30 06:23:14 PM PDT 24
Peak memory 206168 kb
Host smart-b1921b0b-d8a9-4373-a93e-05ce9c23eb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31490
78171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3149078171
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1352814981
Short name T2213
Test name
Test status
Simulation time 247283779 ps
CPU time 0.85 seconds
Started Jun 30 06:23:17 PM PDT 24
Finished Jun 30 06:23:18 PM PDT 24
Peak memory 206188 kb
Host smart-4a568730-f41c-47df-9c8f-aa3bcbfc3db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13528
14981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1352814981
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2372437337
Short name T1966
Test name
Test status
Simulation time 170554492 ps
CPU time 0.8 seconds
Started Jun 30 06:23:19 PM PDT 24
Finished Jun 30 06:23:20 PM PDT 24
Peak memory 206152 kb
Host smart-9e4d1922-4be7-4922-8937-b25d67134902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23724
37337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2372437337
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2211168209
Short name T2568
Test name
Test status
Simulation time 204696998 ps
CPU time 0.92 seconds
Started Jun 30 06:23:28 PM PDT 24
Finished Jun 30 06:23:29 PM PDT 24
Peak memory 206352 kb
Host smart-a48e1980-30f0-4758-989a-830ef86c6106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22111
68209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2211168209
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.3302280173
Short name T1537
Test name
Test status
Simulation time 5100495089 ps
CPU time 39.41 seconds
Started Jun 30 06:23:15 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206428 kb
Host smart-ffd57049-1c5f-4373-bfcb-d21b0d71c12f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3302280173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.3302280173
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.4043934168
Short name T2006
Test name
Test status
Simulation time 224282969 ps
CPU time 0.85 seconds
Started Jun 30 06:23:15 PM PDT 24
Finished Jun 30 06:23:16 PM PDT 24
Peak memory 206188 kb
Host smart-879eacd3-74fc-473a-a2ec-e279a3f7267d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40439
34168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.4043934168
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3847048547
Short name T1774
Test name
Test status
Simulation time 212707914 ps
CPU time 0.8 seconds
Started Jun 30 06:23:23 PM PDT 24
Finished Jun 30 06:23:24 PM PDT 24
Peak memory 206192 kb
Host smart-eda05e42-284a-4a05-b4bc-5e978a9e5d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38470
48547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3847048547
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2737416913
Short name T875
Test name
Test status
Simulation time 3823775473 ps
CPU time 103.28 seconds
Started Jun 30 06:23:15 PM PDT 24
Finished Jun 30 06:24:59 PM PDT 24
Peak memory 206400 kb
Host smart-7a237e22-42ae-42d3-9b9d-31983377a6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27374
16913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2737416913
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.881334309
Short name T2005
Test name
Test status
Simulation time 39264644 ps
CPU time 0.67 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:33 PM PDT 24
Peak memory 206204 kb
Host smart-7fc480ec-7c05-4a92-9688-f48aa27acca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=881334309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.881334309
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3452702058
Short name T2081
Test name
Test status
Simulation time 4158015468 ps
CPU time 6.12 seconds
Started Jun 30 06:23:29 PM PDT 24
Finished Jun 30 06:23:37 PM PDT 24
Peak memory 206400 kb
Host smart-c902c467-fa93-4a1f-aa64-ae8ff8ed31e6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3452702058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3452702058
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3580410756
Short name T243
Test name
Test status
Simulation time 13358488348 ps
CPU time 15.21 seconds
Started Jun 30 06:23:14 PM PDT 24
Finished Jun 30 06:23:30 PM PDT 24
Peak memory 206396 kb
Host smart-ebd4ece3-89fd-4eb6-b97c-b5c4b3c939c9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3580410756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3580410756
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2702873955
Short name T1917
Test name
Test status
Simulation time 23401568150 ps
CPU time 22.59 seconds
Started Jun 30 06:23:30 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206308 kb
Host smart-667a0c9a-c9e2-4228-aebe-b06bb403f6a9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2702873955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2702873955
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2060011183
Short name T1209
Test name
Test status
Simulation time 152808151 ps
CPU time 0.78 seconds
Started Jun 30 06:23:13 PM PDT 24
Finished Jun 30 06:23:14 PM PDT 24
Peak memory 206240 kb
Host smart-6ffc534a-6331-4028-81bb-5f8166dd40ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20600
11183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2060011183
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3445272966
Short name T2486
Test name
Test status
Simulation time 150014779 ps
CPU time 0.8 seconds
Started Jun 30 06:23:13 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206188 kb
Host smart-4299c03d-029d-4d2b-bad7-4ca6becb00a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34452
72966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3445272966
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1189931004
Short name T847
Test name
Test status
Simulation time 253336487 ps
CPU time 0.97 seconds
Started Jun 30 06:23:28 PM PDT 24
Finished Jun 30 06:23:30 PM PDT 24
Peak memory 206184 kb
Host smart-04f9ec3d-fdb3-45ed-a1d5-a6afcc6294f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11899
31004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1189931004
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2376312676
Short name T159
Test name
Test status
Simulation time 831437594 ps
CPU time 2.1 seconds
Started Jun 30 06:23:14 PM PDT 24
Finished Jun 30 06:23:17 PM PDT 24
Peak memory 206472 kb
Host smart-64253694-af94-4488-84e8-b2c0b029d367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23763
12676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2376312676
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.2514775092
Short name T1892
Test name
Test status
Simulation time 19032515061 ps
CPU time 36.31 seconds
Started Jun 30 06:23:16 PM PDT 24
Finished Jun 30 06:23:52 PM PDT 24
Peak memory 206476 kb
Host smart-74be0639-3e59-4f86-ac25-72ba815cda21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25147
75092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2514775092
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.28891964
Short name T2230
Test name
Test status
Simulation time 411990116 ps
CPU time 1.31 seconds
Started Jun 30 06:23:24 PM PDT 24
Finished Jun 30 06:23:26 PM PDT 24
Peak memory 206216 kb
Host smart-e1ee1eb7-9224-47f3-ae62-1654c8c644b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28891
964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.28891964
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.636871056
Short name T1375
Test name
Test status
Simulation time 200595642 ps
CPU time 0.82 seconds
Started Jun 30 06:23:29 PM PDT 24
Finished Jun 30 06:23:31 PM PDT 24
Peak memory 206356 kb
Host smart-8177a47f-1900-4dbc-aca0-1f9c5d2c991e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63687
1056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.636871056
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1521960223
Short name T357
Test name
Test status
Simulation time 57332327 ps
CPU time 0.68 seconds
Started Jun 30 06:23:14 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206188 kb
Host smart-b9d698a2-caf2-4f35-bbd7-20233272fcf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15219
60223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1521960223
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3996527273
Short name T467
Test name
Test status
Simulation time 874604381 ps
CPU time 2.38 seconds
Started Jun 30 06:23:13 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206280 kb
Host smart-792b384a-2189-44cf-80b6-826f67fa3523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39965
27273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3996527273
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1939051262
Short name T1121
Test name
Test status
Simulation time 171701848 ps
CPU time 1.87 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:34 PM PDT 24
Peak memory 206320 kb
Host smart-08b37568-eb41-4145-9eec-16fe4b3919af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19390
51262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1939051262
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2128133630
Short name T1834
Test name
Test status
Simulation time 187017913 ps
CPU time 0.86 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:33 PM PDT 24
Peak memory 206180 kb
Host smart-a88563cd-eefb-450f-844d-618a0b9d426e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21281
33630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2128133630
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.4192401163
Short name T1933
Test name
Test status
Simulation time 208892943 ps
CPU time 0.82 seconds
Started Jun 30 06:23:14 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206152 kb
Host smart-4592ffa8-39e3-4615-9ffd-6b2b766018af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41924
01163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.4192401163
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2206668604
Short name T419
Test name
Test status
Simulation time 162492499 ps
CPU time 0.84 seconds
Started Jun 30 06:23:21 PM PDT 24
Finished Jun 30 06:23:22 PM PDT 24
Peak memory 206204 kb
Host smart-b8682352-d178-4f93-8311-27c64966d8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22066
68604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2206668604
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1867163076
Short name T1170
Test name
Test status
Simulation time 168328352 ps
CPU time 0.82 seconds
Started Jun 30 06:23:14 PM PDT 24
Finished Jun 30 06:23:15 PM PDT 24
Peak memory 206228 kb
Host smart-0660f3b8-e88f-4bee-9e04-72d2eb39b4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18671
63076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1867163076
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.549354228
Short name T1281
Test name
Test status
Simulation time 23330957665 ps
CPU time 24.91 seconds
Started Jun 30 06:23:15 PM PDT 24
Finished Jun 30 06:23:41 PM PDT 24
Peak memory 206276 kb
Host smart-82431a4e-fe0d-4fe8-a7fe-aa05540c188c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54935
4228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.549354228
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3261526914
Short name T452
Test name
Test status
Simulation time 3329322985 ps
CPU time 4.47 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:39 PM PDT 24
Peak memory 206248 kb
Host smart-e7cace6b-3771-493e-bb03-62f89403e291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32615
26914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3261526914
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.3500723639
Short name T148
Test name
Test status
Simulation time 11593680540 ps
CPU time 82.83 seconds
Started Jun 30 06:23:24 PM PDT 24
Finished Jun 30 06:24:48 PM PDT 24
Peak memory 206472 kb
Host smart-8d1c9ddc-7d65-4f70-bb00-03353ea41d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35007
23639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.3500723639
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2594582240
Short name T363
Test name
Test status
Simulation time 3445699450 ps
CPU time 24.47 seconds
Started Jun 30 06:23:23 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206428 kb
Host smart-a1608529-c991-40c9-b2d6-fc77b779b3a3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2594582240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2594582240
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3194622823
Short name T992
Test name
Test status
Simulation time 247008833 ps
CPU time 0.93 seconds
Started Jun 30 06:23:24 PM PDT 24
Finished Jun 30 06:23:25 PM PDT 24
Peak memory 206216 kb
Host smart-23a29a13-b724-4df5-b957-51ad3222d7b9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3194622823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3194622823
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.713827503
Short name T1901
Test name
Test status
Simulation time 181325950 ps
CPU time 0.86 seconds
Started Jun 30 06:23:29 PM PDT 24
Finished Jun 30 06:23:30 PM PDT 24
Peak memory 206208 kb
Host smart-bff074b4-0d9d-4ff2-b0ce-37ad52800bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71382
7503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.713827503
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.4271778059
Short name T411
Test name
Test status
Simulation time 6451898923 ps
CPU time 63.33 seconds
Started Jun 30 06:23:32 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206496 kb
Host smart-70ec66eb-6d2c-4852-a93b-f58593ff1797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42717
78059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.4271778059
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1255485140
Short name T723
Test name
Test status
Simulation time 6455368814 ps
CPU time 171.38 seconds
Started Jun 30 06:23:30 PM PDT 24
Finished Jun 30 06:26:23 PM PDT 24
Peak memory 206432 kb
Host smart-6dee99fe-751c-4497-bf3c-09d59cd2ca01
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1255485140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1255485140
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.425291027
Short name T2452
Test name
Test status
Simulation time 180087779 ps
CPU time 0.9 seconds
Started Jun 30 06:23:22 PM PDT 24
Finished Jun 30 06:23:24 PM PDT 24
Peak memory 206200 kb
Host smart-f1919525-f38f-4010-9d1d-ddc329a7a766
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=425291027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.425291027
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.188398148
Short name T1721
Test name
Test status
Simulation time 165744667 ps
CPU time 0.81 seconds
Started Jun 30 06:23:21 PM PDT 24
Finished Jun 30 06:23:23 PM PDT 24
Peak memory 206212 kb
Host smart-b86d7e6c-9cc6-4545-bdd1-6de24afa6b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18839
8148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.188398148
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1565223066
Short name T2440
Test name
Test status
Simulation time 265699816 ps
CPU time 0.9 seconds
Started Jun 30 06:23:21 PM PDT 24
Finished Jun 30 06:23:23 PM PDT 24
Peak memory 206176 kb
Host smart-122537d7-1408-442c-98a4-990b30e71183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15652
23066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1565223066
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.1202828017
Short name T1925
Test name
Test status
Simulation time 224235348 ps
CPU time 0.89 seconds
Started Jun 30 06:23:22 PM PDT 24
Finished Jun 30 06:23:23 PM PDT 24
Peak memory 206204 kb
Host smart-9d2ee5d0-f4f8-4c99-812e-92d9c96239c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12028
28017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1202828017
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2052357774
Short name T1882
Test name
Test status
Simulation time 206030297 ps
CPU time 0.82 seconds
Started Jun 30 06:23:22 PM PDT 24
Finished Jun 30 06:23:24 PM PDT 24
Peak memory 206196 kb
Host smart-03f3df08-e24f-417c-a4a5-e4dd780e5152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20523
57774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2052357774
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3014243747
Short name T2559
Test name
Test status
Simulation time 187310627 ps
CPU time 0.83 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:34 PM PDT 24
Peak memory 206184 kb
Host smart-20cc0698-e166-43f8-85f3-dadab7a8498c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30142
43747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3014243747
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.519541686
Short name T2309
Test name
Test status
Simulation time 165419498 ps
CPU time 0.85 seconds
Started Jun 30 06:23:21 PM PDT 24
Finished Jun 30 06:23:22 PM PDT 24
Peak memory 206144 kb
Host smart-bbf61673-774a-4186-be84-f59832d822ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51954
1686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.519541686
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3521397150
Short name T2599
Test name
Test status
Simulation time 205498981 ps
CPU time 0.94 seconds
Started Jun 30 06:23:24 PM PDT 24
Finished Jun 30 06:23:25 PM PDT 24
Peak memory 206224 kb
Host smart-fa2cc086-2e79-4eaf-abf2-94a426bafe7f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3521397150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3521397150
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1020718315
Short name T1911
Test name
Test status
Simulation time 147309091 ps
CPU time 0.79 seconds
Started Jun 30 06:23:20 PM PDT 24
Finished Jun 30 06:23:22 PM PDT 24
Peak memory 206172 kb
Host smart-223e4524-ab1d-4cb9-b405-aee58e822fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10207
18315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1020718315
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.4087246002
Short name T25
Test name
Test status
Simulation time 48742458 ps
CPU time 0.65 seconds
Started Jun 30 06:23:32 PM PDT 24
Finished Jun 30 06:23:35 PM PDT 24
Peak memory 206208 kb
Host smart-b7887b13-3691-4914-ad44-cd649f0d6245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40872
46002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.4087246002
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3905735841
Short name T292
Test name
Test status
Simulation time 20170341109 ps
CPU time 49.86 seconds
Started Jun 30 06:23:24 PM PDT 24
Finished Jun 30 06:24:14 PM PDT 24
Peak memory 206440 kb
Host smart-b648d0bc-eac4-45ef-898d-5200f9083547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39057
35841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3905735841
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3813237612
Short name T2243
Test name
Test status
Simulation time 166552077 ps
CPU time 0.8 seconds
Started Jun 30 06:23:39 PM PDT 24
Finished Jun 30 06:23:41 PM PDT 24
Peak memory 206180 kb
Host smart-7ba60024-4b56-4eba-b573-183d54e1bb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38132
37612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3813237612
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.898651117
Short name T519
Test name
Test status
Simulation time 219074140 ps
CPU time 0.93 seconds
Started Jun 30 06:23:23 PM PDT 24
Finished Jun 30 06:23:25 PM PDT 24
Peak memory 206208 kb
Host smart-be75b14d-b813-4921-bfc8-90e7bbecc9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89865
1117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.898651117
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1352285791
Short name T1592
Test name
Test status
Simulation time 197256405 ps
CPU time 0.84 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206184 kb
Host smart-c2142855-fdf9-413e-b334-b916a4730d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13522
85791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1352285791
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3516147010
Short name T2516
Test name
Test status
Simulation time 180732779 ps
CPU time 0.86 seconds
Started Jun 30 06:23:23 PM PDT 24
Finished Jun 30 06:23:25 PM PDT 24
Peak memory 206212 kb
Host smart-56f039d2-39a4-4eb3-857b-9af097730ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35161
47010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3516147010
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2417297727
Short name T592
Test name
Test status
Simulation time 136356122 ps
CPU time 0.77 seconds
Started Jun 30 06:23:21 PM PDT 24
Finished Jun 30 06:23:22 PM PDT 24
Peak memory 206188 kb
Host smart-5886eabb-3954-49d7-b9fb-c1172cb5639a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24172
97727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2417297727
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1460762933
Short name T1249
Test name
Test status
Simulation time 195853408 ps
CPU time 0.78 seconds
Started Jun 30 06:23:32 PM PDT 24
Finished Jun 30 06:23:34 PM PDT 24
Peak memory 206180 kb
Host smart-8cddfdf6-185b-442e-a42a-ab118a87adf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14607
62933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1460762933
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3797674918
Short name T475
Test name
Test status
Simulation time 148868278 ps
CPU time 0.89 seconds
Started Jun 30 06:23:22 PM PDT 24
Finished Jun 30 06:23:24 PM PDT 24
Peak memory 206176 kb
Host smart-f552b2f4-744e-41b8-b9ef-de5ea198a677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37976
74918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3797674918
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1090656723
Short name T619
Test name
Test status
Simulation time 239678085 ps
CPU time 0.99 seconds
Started Jun 30 06:23:32 PM PDT 24
Finished Jun 30 06:23:35 PM PDT 24
Peak memory 206216 kb
Host smart-b4837d72-98a5-4868-b1d2-01c70383df1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10906
56723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1090656723
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3363068854
Short name T362
Test name
Test status
Simulation time 4841569868 ps
CPU time 139.32 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:25:54 PM PDT 24
Peak memory 206464 kb
Host smart-1dacc4dd-8f24-4168-b6c6-5a0794a3bb44
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3363068854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3363068854
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3273122858
Short name T800
Test name
Test status
Simulation time 180322368 ps
CPU time 0.8 seconds
Started Jun 30 06:23:34 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206192 kb
Host smart-28dd8f51-f25a-494a-8f3c-c118c86f8bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32731
22858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3273122858
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2315229697
Short name T2004
Test name
Test status
Simulation time 196632279 ps
CPU time 0.82 seconds
Started Jun 30 06:23:30 PM PDT 24
Finished Jun 30 06:23:32 PM PDT 24
Peak memory 206180 kb
Host smart-bec05d14-8e81-49fd-b7a3-191fd4983236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23152
29697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2315229697
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.3900466684
Short name T2221
Test name
Test status
Simulation time 5366322510 ps
CPU time 148.71 seconds
Started Jun 30 06:23:24 PM PDT 24
Finished Jun 30 06:25:53 PM PDT 24
Peak memory 206408 kb
Host smart-2a1348b5-4c5d-4763-a30b-ed4fcda706bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39004
66684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3900466684
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.1431459529
Short name T569
Test name
Test status
Simulation time 48719500 ps
CPU time 0.69 seconds
Started Jun 30 06:23:46 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206168 kb
Host smart-496fa50c-6573-43b6-b1b8-97fc2484567e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1431459529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1431459529
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3266010641
Short name T1648
Test name
Test status
Simulation time 4132998945 ps
CPU time 4.65 seconds
Started Jun 30 06:23:25 PM PDT 24
Finished Jun 30 06:23:30 PM PDT 24
Peak memory 206264 kb
Host smart-dbab220d-a639-472e-9509-6a4b41411f22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3266010641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.3266010641
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3887133695
Short name T9
Test name
Test status
Simulation time 13399365133 ps
CPU time 15 seconds
Started Jun 30 06:23:34 PM PDT 24
Finished Jun 30 06:23:51 PM PDT 24
Peak memory 206424 kb
Host smart-2a34518b-f441-4661-a6c1-87cb08eae79a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3887133695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3887133695
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.559513066
Short name T2571
Test name
Test status
Simulation time 23311963235 ps
CPU time 25.18 seconds
Started Jun 30 06:23:29 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206408 kb
Host smart-41df9194-2331-4cd8-b648-b40e735945ca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=559513066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.559513066
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2673133438
Short name T2386
Test name
Test status
Simulation time 214254746 ps
CPU time 0.83 seconds
Started Jun 30 06:23:39 PM PDT 24
Finished Jun 30 06:23:41 PM PDT 24
Peak memory 206188 kb
Host smart-7ce6bee1-50a6-4298-825d-984008f15827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26731
33438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2673133438
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2177779071
Short name T1513
Test name
Test status
Simulation time 151084873 ps
CPU time 0.78 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206172 kb
Host smart-186fe0ff-0df1-4284-bbcd-a5c5d032af36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21777
79071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2177779071
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1537677826
Short name T190
Test name
Test status
Simulation time 545323350 ps
CPU time 1.51 seconds
Started Jun 30 06:23:29 PM PDT 24
Finished Jun 30 06:23:32 PM PDT 24
Peak memory 206348 kb
Host smart-b9925818-e9e3-4975-a054-3e7ecc013cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15376
77826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1537677826
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3385716786
Short name T1310
Test name
Test status
Simulation time 1537667262 ps
CPU time 3.52 seconds
Started Jun 30 06:23:37 PM PDT 24
Finished Jun 30 06:23:41 PM PDT 24
Peak memory 206292 kb
Host smart-6960538f-f368-4415-87f8-a13a9af1ab96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33857
16786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3385716786
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1338785422
Short name T2482
Test name
Test status
Simulation time 20664145527 ps
CPU time 38.52 seconds
Started Jun 30 06:23:27 PM PDT 24
Finished Jun 30 06:24:05 PM PDT 24
Peak memory 206428 kb
Host smart-5d2188d5-6e68-4975-b3a0-8ac105e0580c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13387
85422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1338785422
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2577020127
Short name T2477
Test name
Test status
Simulation time 449634064 ps
CPU time 1.44 seconds
Started Jun 30 06:23:29 PM PDT 24
Finished Jun 30 06:23:32 PM PDT 24
Peak memory 206196 kb
Host smart-f593e9e5-8733-441c-ac88-323e149ae65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25770
20127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2577020127
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2609867828
Short name T1307
Test name
Test status
Simulation time 143792632 ps
CPU time 0.79 seconds
Started Jun 30 06:23:32 PM PDT 24
Finished Jun 30 06:23:34 PM PDT 24
Peak memory 206168 kb
Host smart-842c09c4-59a1-43b0-87c0-f72ab692a42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26098
67828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2609867828
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1137343595
Short name T1351
Test name
Test status
Simulation time 67117616 ps
CPU time 0.7 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:33 PM PDT 24
Peak memory 206148 kb
Host smart-6270de9c-552f-4b3a-acdc-366d43c231c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11373
43595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1137343595
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.819490949
Short name T1952
Test name
Test status
Simulation time 841331815 ps
CPU time 1.98 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:37 PM PDT 24
Peak memory 206508 kb
Host smart-3fb6e2b4-91df-4812-aa0e-138e1f312e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81949
0949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.819490949
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3520774063
Short name T596
Test name
Test status
Simulation time 307574839 ps
CPU time 1.87 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:35 PM PDT 24
Peak memory 206280 kb
Host smart-98312c67-9369-4f95-9087-b9a5e4127549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35207
74063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3520774063
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3191840221
Short name T1906
Test name
Test status
Simulation time 229347380 ps
CPU time 1.01 seconds
Started Jun 30 06:23:34 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206184 kb
Host smart-16f94fde-4ff6-4313-8a57-8423195ad5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31918
40221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3191840221
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2733867950
Short name T1803
Test name
Test status
Simulation time 159741547 ps
CPU time 0.88 seconds
Started Jun 30 06:23:27 PM PDT 24
Finished Jun 30 06:23:28 PM PDT 24
Peak memory 206200 kb
Host smart-369b3906-5a8b-4eba-bec7-07ad3fa2de50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27338
67950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2733867950
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1739623404
Short name T1552
Test name
Test status
Simulation time 245728755 ps
CPU time 0.96 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:33 PM PDT 24
Peak memory 206208 kb
Host smart-5c0ce51c-4fcf-43ee-a6e3-ee92b2b11915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17396
23404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1739623404
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2852191814
Short name T556
Test name
Test status
Simulation time 223035685 ps
CPU time 0.9 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206160 kb
Host smart-dd85c4cf-764d-4a3a-a546-1e67fdc266ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28521
91814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2852191814
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3298388977
Short name T2608
Test name
Test status
Simulation time 23318729827 ps
CPU time 21.2 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206312 kb
Host smart-2276088c-a521-4265-ab76-3a8b763c8541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32983
88977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3298388977
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.437593234
Short name T1422
Test name
Test status
Simulation time 3307022108 ps
CPU time 4.03 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206256 kb
Host smart-4ed883a1-dd38-4025-81b9-3421e86f50c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43759
3234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.437593234
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.337488731
Short name T817
Test name
Test status
Simulation time 8067879338 ps
CPU time 222.85 seconds
Started Jun 30 06:23:29 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 206460 kb
Host smart-1081f795-12d8-4ddc-9f35-ecf5ff20cfaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33748
8731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.337488731
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1247421744
Short name T2187
Test name
Test status
Simulation time 3462869950 ps
CPU time 92.99 seconds
Started Jun 30 06:23:27 PM PDT 24
Finished Jun 30 06:25:00 PM PDT 24
Peak memory 206460 kb
Host smart-ccd70ea0-4244-4bcd-b107-39febe41d960
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1247421744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1247421744
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1936321446
Short name T2529
Test name
Test status
Simulation time 241000272 ps
CPU time 0.9 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:34 PM PDT 24
Peak memory 206208 kb
Host smart-014a3305-f281-4e7f-a6b8-37b80f92d086
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1936321446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1936321446
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1257288628
Short name T914
Test name
Test status
Simulation time 189128232 ps
CPU time 0.8 seconds
Started Jun 30 06:23:26 PM PDT 24
Finished Jun 30 06:23:27 PM PDT 24
Peak memory 206200 kb
Host smart-f10365eb-64fd-491a-b559-7442062a1ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12572
88628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1257288628
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3593127534
Short name T2082
Test name
Test status
Simulation time 4731353321 ps
CPU time 146.01 seconds
Started Jun 30 06:23:30 PM PDT 24
Finished Jun 30 06:25:57 PM PDT 24
Peak memory 206456 kb
Host smart-c296c7ec-5718-43c5-ab5c-0acfba543502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35931
27534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3593127534
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3490307338
Short name T1102
Test name
Test status
Simulation time 3771009964 ps
CPU time 26.58 seconds
Started Jun 30 06:23:38 PM PDT 24
Finished Jun 30 06:24:05 PM PDT 24
Peak memory 206440 kb
Host smart-8e5dd98e-d0e9-4edb-8225-af69abf393d9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3490307338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3490307338
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.697096529
Short name T976
Test name
Test status
Simulation time 194111665 ps
CPU time 0.82 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:35 PM PDT 24
Peak memory 206176 kb
Host smart-792d0a42-d139-41a0-904b-081b6d73b5f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=697096529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.697096529
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2348225621
Short name T2135
Test name
Test status
Simulation time 140444957 ps
CPU time 0.78 seconds
Started Jun 30 06:23:27 PM PDT 24
Finished Jun 30 06:23:28 PM PDT 24
Peak memory 206176 kb
Host smart-d1ac0ccc-174f-455a-aea4-5ebfe4474895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23482
25621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2348225621
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2556490075
Short name T859
Test name
Test status
Simulation time 183593152 ps
CPU time 0.8 seconds
Started Jun 30 06:23:29 PM PDT 24
Finished Jun 30 06:23:32 PM PDT 24
Peak memory 206156 kb
Host smart-145d723c-b8d9-4a54-8542-10b5eda789f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25564
90075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2556490075
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3180138365
Short name T1764
Test name
Test status
Simulation time 160899344 ps
CPU time 0.82 seconds
Started Jun 30 06:23:34 PM PDT 24
Finished Jun 30 06:23:37 PM PDT 24
Peak memory 206160 kb
Host smart-c2d62b36-58cd-4769-8736-ac43c04698b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31801
38365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3180138365
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2135698692
Short name T1539
Test name
Test status
Simulation time 161581429 ps
CPU time 0.77 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:33 PM PDT 24
Peak memory 206168 kb
Host smart-65419e42-1505-4957-932d-030858daa8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21356
98692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2135698692
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.164094158
Short name T1387
Test name
Test status
Simulation time 165280198 ps
CPU time 0.83 seconds
Started Jun 30 06:23:36 PM PDT 24
Finished Jun 30 06:23:38 PM PDT 24
Peak memory 206192 kb
Host smart-28a24400-d79d-47da-ac09-0decec36fe57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16409
4158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.164094158
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1335116011
Short name T1259
Test name
Test status
Simulation time 194524453 ps
CPU time 0.85 seconds
Started Jun 30 06:23:37 PM PDT 24
Finished Jun 30 06:23:38 PM PDT 24
Peak memory 206200 kb
Host smart-56fe58d1-efc5-48ce-b5e2-a9cc0fec5379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13351
16011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1335116011
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1105597945
Short name T76
Test name
Test status
Simulation time 223131525 ps
CPU time 0.9 seconds
Started Jun 30 06:23:26 PM PDT 24
Finished Jun 30 06:23:27 PM PDT 24
Peak memory 206212 kb
Host smart-516c9ea9-881b-4710-898e-c2a5e6b16e59
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1105597945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1105597945
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2596156584
Short name T2151
Test name
Test status
Simulation time 155350470 ps
CPU time 0.77 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:33 PM PDT 24
Peak memory 206196 kb
Host smart-43591609-0063-4e7b-b4e3-31e456a06b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25961
56584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2596156584
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1521763749
Short name T1418
Test name
Test status
Simulation time 49826632 ps
CPU time 0.67 seconds
Started Jun 30 06:23:29 PM PDT 24
Finished Jun 30 06:23:30 PM PDT 24
Peak memory 206208 kb
Host smart-cf6eb6e8-19fa-4d74-a8d6-ec7895c9441c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15217
63749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1521763749
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1171585465
Short name T2280
Test name
Test status
Simulation time 13199519695 ps
CPU time 33.52 seconds
Started Jun 30 06:23:29 PM PDT 24
Finished Jun 30 06:24:04 PM PDT 24
Peak memory 206432 kb
Host smart-7bbc99f6-9ae1-4940-8a02-80f64ecfdf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11715
85465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1171585465
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.4111607484
Short name T1018
Test name
Test status
Simulation time 154167012 ps
CPU time 0.89 seconds
Started Jun 30 06:23:42 PM PDT 24
Finished Jun 30 06:23:43 PM PDT 24
Peak memory 206180 kb
Host smart-741acdb6-7f87-427b-b41f-197606a8c291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41116
07484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.4111607484
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.164671256
Short name T2357
Test name
Test status
Simulation time 212544890 ps
CPU time 0.85 seconds
Started Jun 30 06:23:35 PM PDT 24
Finished Jun 30 06:23:37 PM PDT 24
Peak memory 206204 kb
Host smart-2576286f-59a9-4af1-ba65-b5274bc0151d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16467
1256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.164671256
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.992041042
Short name T1595
Test name
Test status
Simulation time 161254375 ps
CPU time 0.79 seconds
Started Jun 30 06:23:28 PM PDT 24
Finished Jun 30 06:23:29 PM PDT 24
Peak memory 206196 kb
Host smart-c7a3a117-a530-42c2-969b-aeae238feb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99204
1042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.992041042
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1888073404
Short name T18
Test name
Test status
Simulation time 188118023 ps
CPU time 0.79 seconds
Started Jun 30 06:23:38 PM PDT 24
Finished Jun 30 06:23:40 PM PDT 24
Peak memory 206156 kb
Host smart-bba96758-2719-4c08-8927-ab62aacbe351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18880
73404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1888073404
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.3641834502
Short name T2614
Test name
Test status
Simulation time 140714990 ps
CPU time 0.74 seconds
Started Jun 30 06:23:28 PM PDT 24
Finished Jun 30 06:23:29 PM PDT 24
Peak memory 206172 kb
Host smart-8bfc528b-889c-4269-b882-8abc7538c30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36418
34502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.3641834502
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.517184688
Short name T1953
Test name
Test status
Simulation time 146443637 ps
CPU time 0.79 seconds
Started Jun 30 06:23:30 PM PDT 24
Finished Jun 30 06:23:32 PM PDT 24
Peak memory 206196 kb
Host smart-91c37c32-c015-4277-bc4c-f576d0bdd3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51718
4688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.517184688
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3416976649
Short name T1283
Test name
Test status
Simulation time 214545908 ps
CPU time 0.85 seconds
Started Jun 30 06:23:30 PM PDT 24
Finished Jun 30 06:23:32 PM PDT 24
Peak memory 206188 kb
Host smart-af140760-d142-408c-a1b0-527fe23fdc7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34169
76649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3416976649
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.909420564
Short name T631
Test name
Test status
Simulation time 233007222 ps
CPU time 0.96 seconds
Started Jun 30 06:23:38 PM PDT 24
Finished Jun 30 06:23:39 PM PDT 24
Peak memory 206208 kb
Host smart-c4089aa9-7235-4613-845c-f43c031fc9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90942
0564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.909420564
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.785456281
Short name T1801
Test name
Test status
Simulation time 4388518293 ps
CPU time 31.77 seconds
Started Jun 30 06:23:36 PM PDT 24
Finished Jun 30 06:24:09 PM PDT 24
Peak memory 206432 kb
Host smart-1a87efe9-a305-4b11-9eb3-f5d9ab1117f2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=785456281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.785456281
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2514515413
Short name T2257
Test name
Test status
Simulation time 193809545 ps
CPU time 0.83 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:33 PM PDT 24
Peak memory 206168 kb
Host smart-3d8c7629-03da-4809-ac9c-1887b7b97be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25145
15413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2514515413
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1281194886
Short name T2194
Test name
Test status
Simulation time 175666281 ps
CPU time 0.8 seconds
Started Jun 30 06:23:31 PM PDT 24
Finished Jun 30 06:23:33 PM PDT 24
Peak memory 206160 kb
Host smart-51caaee4-fc4f-4df8-a63f-c5c7cc564c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12811
94886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1281194886
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2880773599
Short name T250
Test name
Test status
Simulation time 6762992875 ps
CPU time 62.84 seconds
Started Jun 30 06:23:30 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206360 kb
Host smart-a1dca983-ea14-4663-a8e7-d1548edee68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28807
73599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2880773599
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2277358974
Short name T2620
Test name
Test status
Simulation time 40308626 ps
CPU time 0.68 seconds
Started Jun 30 06:23:39 PM PDT 24
Finished Jun 30 06:23:40 PM PDT 24
Peak memory 205972 kb
Host smart-47995143-9ec1-44c0-812a-4ab9ba9bfda5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2277358974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2277358974
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1889658715
Short name T2146
Test name
Test status
Simulation time 4283813018 ps
CPU time 5.28 seconds
Started Jun 30 06:23:43 PM PDT 24
Finished Jun 30 06:23:49 PM PDT 24
Peak memory 206232 kb
Host smart-69f87fb3-d3e0-49a7-9cb3-24aad8943935
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1889658715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.1889658715
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.512780479
Short name T958
Test name
Test status
Simulation time 13464842122 ps
CPU time 16.5 seconds
Started Jun 30 06:23:39 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206416 kb
Host smart-6d327f5f-d3f0-4eb4-8813-55537e74bb79
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=512780479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.512780479
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1462515573
Short name T1589
Test name
Test status
Simulation time 23356401610 ps
CPU time 25.29 seconds
Started Jun 30 06:23:32 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206292 kb
Host smart-f46a7527-a67d-402d-aec7-c0999e9f6439
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1462515573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.1462515573
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2612435102
Short name T1400
Test name
Test status
Simulation time 152699269 ps
CPU time 0.86 seconds
Started Jun 30 06:23:32 PM PDT 24
Finished Jun 30 06:23:34 PM PDT 24
Peak memory 206176 kb
Host smart-372e2ce8-be37-4831-a5fb-6c4f30999e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26124
35102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2612435102
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.844454428
Short name T2097
Test name
Test status
Simulation time 147999984 ps
CPU time 0.76 seconds
Started Jun 30 06:23:42 PM PDT 24
Finished Jun 30 06:23:44 PM PDT 24
Peak memory 206152 kb
Host smart-8a5f9b6a-26b8-4d69-a86b-e91059bc9113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84445
4428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.844454428
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2925675453
Short name T1759
Test name
Test status
Simulation time 412216595 ps
CPU time 1.4 seconds
Started Jun 30 06:23:34 PM PDT 24
Finished Jun 30 06:23:37 PM PDT 24
Peak memory 206176 kb
Host smart-02c0b02e-3317-4727-b8b6-3a03f06b8619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29256
75453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2925675453
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3448097359
Short name T2298
Test name
Test status
Simulation time 517131794 ps
CPU time 1.45 seconds
Started Jun 30 06:23:34 PM PDT 24
Finished Jun 30 06:23:37 PM PDT 24
Peak memory 206176 kb
Host smart-08c8322e-f72b-47de-84fb-eec94c5df591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34480
97359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3448097359
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2358429107
Short name T90
Test name
Test status
Simulation time 18873430787 ps
CPU time 34.7 seconds
Started Jun 30 06:23:42 PM PDT 24
Finished Jun 30 06:24:18 PM PDT 24
Peak memory 206368 kb
Host smart-6886a73a-a6af-4394-84f0-1a5abc6dd5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23584
29107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2358429107
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.750674103
Short name T1653
Test name
Test status
Simulation time 369358747 ps
CPU time 1.22 seconds
Started Jun 30 06:23:44 PM PDT 24
Finished Jun 30 06:23:46 PM PDT 24
Peak memory 206176 kb
Host smart-9c772eb4-74e3-4f52-9868-c4ef5f4e5960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75067
4103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.750674103
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2263707859
Short name T1021
Test name
Test status
Simulation time 141674755 ps
CPU time 0.73 seconds
Started Jun 30 06:23:42 PM PDT 24
Finished Jun 30 06:23:43 PM PDT 24
Peak memory 206044 kb
Host smart-1ea076a3-5e7c-4e38-9fa4-9f48ca475931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22637
07859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2263707859
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.4028429264
Short name T2123
Test name
Test status
Simulation time 35753649 ps
CPU time 0.66 seconds
Started Jun 30 06:23:37 PM PDT 24
Finished Jun 30 06:23:38 PM PDT 24
Peak memory 206148 kb
Host smart-a2c0b47b-210a-45e3-be03-a9be260f33dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40284
29264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.4028429264
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.4204260066
Short name T1580
Test name
Test status
Simulation time 1013725618 ps
CPU time 2.31 seconds
Started Jun 30 06:23:42 PM PDT 24
Finished Jun 30 06:23:45 PM PDT 24
Peak memory 206288 kb
Host smart-06c16fa3-b8b6-4b23-b746-3ee241b12de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42042
60066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.4204260066
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2599342057
Short name T2540
Test name
Test status
Simulation time 201605552 ps
CPU time 1.96 seconds
Started Jun 30 06:23:28 PM PDT 24
Finished Jun 30 06:23:31 PM PDT 24
Peak memory 206312 kb
Host smart-b2a2221e-f8cf-4eb0-a320-5f6ff47dec8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25993
42057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2599342057
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1784327135
Short name T772
Test name
Test status
Simulation time 227524459 ps
CPU time 0.87 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206120 kb
Host smart-d7ba0e75-c5c2-422d-b74c-7142ea3657f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17843
27135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1784327135
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1633307736
Short name T333
Test name
Test status
Simulation time 146707499 ps
CPU time 0.76 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206204 kb
Host smart-c7b2e216-ee12-4ba0-89d0-d9dd9c7d908c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16333
07736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1633307736
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1770143323
Short name T2470
Test name
Test status
Simulation time 202506589 ps
CPU time 0.96 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:39 PM PDT 24
Peak memory 205900 kb
Host smart-e8835a22-de6f-4c11-9809-b3e2685771cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17701
43323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1770143323
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.1398395226
Short name T261
Test name
Test status
Simulation time 6685256368 ps
CPU time 45.39 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:24:20 PM PDT 24
Peak memory 206428 kb
Host smart-cc9523bb-e5cd-43c2-bc6b-fb18255c315a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1398395226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.1398395226
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.82606299
Short name T326
Test name
Test status
Simulation time 226599714 ps
CPU time 0.9 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206188 kb
Host smart-fc5e7843-7bdd-421c-99ec-664091e24af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82606
299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.82606299
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2272372101
Short name T1515
Test name
Test status
Simulation time 23313531318 ps
CPU time 25.79 seconds
Started Jun 30 06:23:47 PM PDT 24
Finished Jun 30 06:24:15 PM PDT 24
Peak memory 206284 kb
Host smart-45c39049-9fef-42e3-a53a-cc67aaf0d5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22723
72101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2272372101
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3094544965
Short name T1672
Test name
Test status
Simulation time 3257772468 ps
CPU time 3.69 seconds
Started Jun 30 06:23:38 PM PDT 24
Finished Jun 30 06:23:42 PM PDT 24
Peak memory 205992 kb
Host smart-82258b7f-cc45-4303-a0d0-546eb3969abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30945
44965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3094544965
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.4254457758
Short name T1558
Test name
Test status
Simulation time 7811274106 ps
CPU time 74.78 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:25:02 PM PDT 24
Peak memory 206448 kb
Host smart-70de4cd1-66f8-432c-b024-e5c731dd9488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42544
57758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.4254457758
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2547054709
Short name T609
Test name
Test status
Simulation time 4572065413 ps
CPU time 125.38 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:25:52 PM PDT 24
Peak memory 206436 kb
Host smart-1524babb-b55e-4a82-a46d-16d38793cac9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2547054709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2547054709
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2500358632
Short name T1184
Test name
Test status
Simulation time 233485012 ps
CPU time 0.84 seconds
Started Jun 30 06:23:47 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206192 kb
Host smart-6df1cd6d-6632-4a0f-abd7-d8238782f54f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2500358632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2500358632
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3452956219
Short name T734
Test name
Test status
Simulation time 194371562 ps
CPU time 0.93 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206176 kb
Host smart-822a5777-f4a1-4e45-8cdc-0bfacd951fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529
56219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3452956219
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.3700654557
Short name T2395
Test name
Test status
Simulation time 3755833831 ps
CPU time 27.85 seconds
Started Jun 30 06:23:35 PM PDT 24
Finished Jun 30 06:24:04 PM PDT 24
Peak memory 206644 kb
Host smart-2d09d363-91b0-40eb-8852-88166ac2499c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37006
54557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.3700654557
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.3602256725
Short name T690
Test name
Test status
Simulation time 3808539464 ps
CPU time 105.48 seconds
Started Jun 30 06:23:43 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206452 kb
Host smart-5f2fdcfd-5c75-4821-aec1-b0fca4ef394f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3602256725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.3602256725
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.4270000188
Short name T1726
Test name
Test status
Simulation time 153719403 ps
CPU time 0.78 seconds
Started Jun 30 06:23:47 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206192 kb
Host smart-8e305319-056e-458f-a81d-e7db7ec1551a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4270000188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.4270000188
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3320343421
Short name T2475
Test name
Test status
Simulation time 146383025 ps
CPU time 0.75 seconds
Started Jun 30 06:23:39 PM PDT 24
Finished Jun 30 06:23:40 PM PDT 24
Peak memory 206188 kb
Host smart-3ed09966-a610-4298-b604-e16e64c66fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33203
43421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3320343421
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.1608315993
Short name T1285
Test name
Test status
Simulation time 169929071 ps
CPU time 0.78 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:54 PM PDT 24
Peak memory 206184 kb
Host smart-caa6af62-f21a-4271-aaaf-a4ea561df046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16083
15993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.1608315993
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3183398517
Short name T1007
Test name
Test status
Simulation time 166265093 ps
CPU time 0.84 seconds
Started Jun 30 06:23:36 PM PDT 24
Finished Jun 30 06:23:38 PM PDT 24
Peak memory 206400 kb
Host smart-b025dc8c-1e6d-4b50-ada5-51ff045d73f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31833
98517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3183398517
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.49157582
Short name T930
Test name
Test status
Simulation time 160803389 ps
CPU time 0.79 seconds
Started Jun 30 06:23:34 PM PDT 24
Finished Jun 30 06:23:37 PM PDT 24
Peak memory 206196 kb
Host smart-1c07f9dd-d75f-4f70-9231-668fd323bab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49157
582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.49157582
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2047212916
Short name T1775
Test name
Test status
Simulation time 169800032 ps
CPU time 0.81 seconds
Started Jun 30 06:23:48 PM PDT 24
Finished Jun 30 06:23:51 PM PDT 24
Peak memory 206056 kb
Host smart-4b027e25-c7e7-4719-b17c-8d69deb3efc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20472
12916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2047212916
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.2081404204
Short name T2476
Test name
Test status
Simulation time 262110691 ps
CPU time 0.96 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:35 PM PDT 24
Peak memory 206176 kb
Host smart-2f1098c4-6524-4e35-889a-35cb691ce44f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2081404204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.2081404204
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3895568921
Short name T511
Test name
Test status
Simulation time 188542442 ps
CPU time 0.79 seconds
Started Jun 30 06:23:33 PM PDT 24
Finished Jun 30 06:23:36 PM PDT 24
Peak memory 206216 kb
Host smart-ca6cf59b-3a4b-4bd3-ba39-45e185c56afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38955
68921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3895568921
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1401328314
Short name T770
Test name
Test status
Simulation time 35620366 ps
CPU time 0.66 seconds
Started Jun 30 06:23:34 PM PDT 24
Finished Jun 30 06:23:37 PM PDT 24
Peak memory 206204 kb
Host smart-13a606c3-9821-4c2b-a087-7942ae850cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14013
28314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1401328314
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3616700011
Short name T1875
Test name
Test status
Simulation time 12182623429 ps
CPU time 27.13 seconds
Started Jun 30 06:23:44 PM PDT 24
Finished Jun 30 06:24:12 PM PDT 24
Peak memory 206456 kb
Host smart-c2da325c-e9f0-42f0-a645-e437b4d69412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36167
00011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3616700011
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3668487260
Short name T2089
Test name
Test status
Simulation time 199867977 ps
CPU time 0.83 seconds
Started Jun 30 06:23:47 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206044 kb
Host smart-ec54905d-76d9-4ed3-8d59-03e836036cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36684
87260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3668487260
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.4257429621
Short name T2446
Test name
Test status
Simulation time 260103727 ps
CPU time 0.94 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206184 kb
Host smart-2718dd41-d9c7-4452-b379-855965160197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42574
29621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.4257429621
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1283791845
Short name T1833
Test name
Test status
Simulation time 203388375 ps
CPU time 0.85 seconds
Started Jun 30 06:23:39 PM PDT 24
Finished Jun 30 06:23:40 PM PDT 24
Peak memory 206000 kb
Host smart-f32d67a2-9f37-4b38-88f4-ae182e7fefae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12837
91845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1283791845
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.4245637392
Short name T520
Test name
Test status
Simulation time 193937453 ps
CPU time 0.85 seconds
Started Jun 30 06:23:41 PM PDT 24
Finished Jun 30 06:23:42 PM PDT 24
Peak memory 206192 kb
Host smart-177af070-0346-48b5-a08a-33d614bb1b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42456
37392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.4245637392
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.300516497
Short name T2301
Test name
Test status
Simulation time 161608960 ps
CPU time 0.76 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206172 kb
Host smart-48f4c62c-749b-45fb-8ca7-cd3261647bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30051
6497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.300516497
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.14702881
Short name T1516
Test name
Test status
Simulation time 150571844 ps
CPU time 0.77 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206172 kb
Host smart-f6334435-6fe8-4432-afd1-f2e1313cb8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14702
881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.14702881
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.725812087
Short name T2478
Test name
Test status
Simulation time 228412711 ps
CPU time 0.95 seconds
Started Jun 30 06:23:39 PM PDT 24
Finished Jun 30 06:23:40 PM PDT 24
Peak memory 206212 kb
Host smart-c330784e-631f-49d9-aea2-0a06710e62f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72581
2087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.725812087
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3747669228
Short name T450
Test name
Test status
Simulation time 3695726593 ps
CPU time 27.18 seconds
Started Jun 30 06:23:43 PM PDT 24
Finished Jun 30 06:24:12 PM PDT 24
Peak memory 206380 kb
Host smart-f43c8307-694a-4c31-8872-0b5656d66710
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3747669228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3747669228
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.340174418
Short name T798
Test name
Test status
Simulation time 160219560 ps
CPU time 0.79 seconds
Started Jun 30 06:23:46 PM PDT 24
Finished Jun 30 06:23:49 PM PDT 24
Peak memory 206068 kb
Host smart-1b912ff4-12b9-4dd7-92b0-4fc042955f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34017
4418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.340174418
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1482986332
Short name T1262
Test name
Test status
Simulation time 204629176 ps
CPU time 0.85 seconds
Started Jun 30 06:23:43 PM PDT 24
Finished Jun 30 06:23:45 PM PDT 24
Peak memory 206168 kb
Host smart-0e5e1b68-0893-474b-aee8-4156f04d172b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14829
86332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1482986332
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2116012368
Short name T2038
Test name
Test status
Simulation time 4478585153 ps
CPU time 43.96 seconds
Started Jun 30 06:23:34 PM PDT 24
Finished Jun 30 06:24:20 PM PDT 24
Peak memory 206388 kb
Host smart-6243d7c7-a75d-4732-88df-b741b7d702ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21160
12368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2116012368
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3082761402
Short name T1965
Test name
Test status
Simulation time 50616571 ps
CPU time 0.7 seconds
Started Jun 30 06:23:48 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206208 kb
Host smart-5a413945-a060-4dfc-8e7e-18084e194db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3082761402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3082761402
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.817067692
Short name T1392
Test name
Test status
Simulation time 4187601594 ps
CPU time 5.17 seconds
Started Jun 30 06:23:44 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206272 kb
Host smart-6214cdd6-b093-4da2-afba-4404b6a4839c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=817067692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.817067692
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.705237895
Short name T1178
Test name
Test status
Simulation time 13402995497 ps
CPU time 12.23 seconds
Started Jun 30 06:23:48 PM PDT 24
Finished Jun 30 06:24:02 PM PDT 24
Peak memory 206196 kb
Host smart-a21e6be5-dfa3-4ad2-ad62-5b4033ad14bb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=705237895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.705237895
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2923153490
Short name T852
Test name
Test status
Simulation time 23346702042 ps
CPU time 23.85 seconds
Started Jun 30 06:23:44 PM PDT 24
Finished Jun 30 06:24:08 PM PDT 24
Peak memory 206384 kb
Host smart-ff774834-8574-4bcd-8945-8e1888ce0be0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2923153490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.2923153490
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.996803776
Short name T2015
Test name
Test status
Simulation time 192294503 ps
CPU time 0.82 seconds
Started Jun 30 06:23:44 PM PDT 24
Finished Jun 30 06:23:47 PM PDT 24
Peak memory 206172 kb
Host smart-c1255076-c95c-43fa-ae43-f71556359341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99680
3776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.996803776
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.4165200858
Short name T491
Test name
Test status
Simulation time 209585696 ps
CPU time 0.83 seconds
Started Jun 30 06:23:47 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206048 kb
Host smart-44120420-57c9-4e1e-9cc9-dd8c29d3d9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41652
00858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.4165200858
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1708194837
Short name T1332
Test name
Test status
Simulation time 177514828 ps
CPU time 0.83 seconds
Started Jun 30 06:23:50 PM PDT 24
Finished Jun 30 06:23:52 PM PDT 24
Peak memory 206188 kb
Host smart-fb2cc088-c4ef-474c-8dec-c137c4846551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17081
94837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1708194837
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2703272461
Short name T555
Test name
Test status
Simulation time 260614660 ps
CPU time 0.9 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:49 PM PDT 24
Peak memory 206048 kb
Host smart-de7c948a-62ca-416f-ad6b-1e1cfef959a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27032
72461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2703272461
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3755480546
Short name T1250
Test name
Test status
Simulation time 9453558953 ps
CPU time 21.02 seconds
Started Jun 30 06:23:36 PM PDT 24
Finished Jun 30 06:23:58 PM PDT 24
Peak memory 206684 kb
Host smart-fa655950-1b5a-4587-94c0-02c3a9726c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37554
80546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3755480546
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3849048522
Short name T2345
Test name
Test status
Simulation time 308374170 ps
CPU time 1.09 seconds
Started Jun 30 06:23:46 PM PDT 24
Finished Jun 30 06:23:49 PM PDT 24
Peak memory 206172 kb
Host smart-dbf1c347-f60b-4f0f-8c27-11d7dc1089b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38490
48522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3849048522
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1785046711
Short name T1309
Test name
Test status
Simulation time 150531504 ps
CPU time 0.75 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206188 kb
Host smart-43ed2b26-1fc1-469b-9b9b-227c072d15fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17850
46711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1785046711
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.500106326
Short name T1567
Test name
Test status
Simulation time 35720056 ps
CPU time 0.64 seconds
Started Jun 30 06:23:57 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206196 kb
Host smart-9a396da6-a539-44ab-82c5-3356d01057a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50010
6326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.500106326
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.72563226
Short name T667
Test name
Test status
Simulation time 898590148 ps
CPU time 2.08 seconds
Started Jun 30 06:23:47 PM PDT 24
Finished Jun 30 06:23:51 PM PDT 24
Peak memory 206332 kb
Host smart-e9f22504-bd9e-4da2-863f-59cd88c0c492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72563
226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.72563226
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2933869893
Short name T2319
Test name
Test status
Simulation time 160645710 ps
CPU time 1.28 seconds
Started Jun 30 06:23:55 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206124 kb
Host smart-80b08a2f-aa70-4ebe-b1bb-6950e5efbbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29338
69893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2933869893
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.547421584
Short name T1984
Test name
Test status
Simulation time 206707525 ps
CPU time 0.93 seconds
Started Jun 30 06:23:48 PM PDT 24
Finished Jun 30 06:23:51 PM PDT 24
Peak memory 206180 kb
Host smart-8594a1f3-b859-475e-ab59-963c0bb89980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54742
1584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.547421584
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2496540980
Short name T473
Test name
Test status
Simulation time 141973642 ps
CPU time 0.8 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206220 kb
Host smart-e0dac2ca-db48-43fc-a760-7efefdcc5b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24965
40980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2496540980
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3110198195
Short name T392
Test name
Test status
Simulation time 182460093 ps
CPU time 0.86 seconds
Started Jun 30 06:23:42 PM PDT 24
Finished Jun 30 06:23:43 PM PDT 24
Peak memory 206200 kb
Host smart-9c551f78-73d5-48a3-8ea9-26cf0d1e5766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31101
98195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3110198195
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.1031477485
Short name T1083
Test name
Test status
Simulation time 6492406054 ps
CPU time 47.73 seconds
Started Jun 30 06:23:43 PM PDT 24
Finished Jun 30 06:24:31 PM PDT 24
Peak memory 206408 kb
Host smart-77ed1c6c-07c8-4b22-bfc1-adbaef1bd30e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1031477485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1031477485
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3499040515
Short name T2445
Test name
Test status
Simulation time 205019166 ps
CPU time 0.88 seconds
Started Jun 30 06:23:47 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206168 kb
Host smart-11bde89a-f33c-4372-a009-0223c9e802d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34990
40515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3499040515
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.3114912001
Short name T593
Test name
Test status
Simulation time 23311474516 ps
CPU time 21.67 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:24:17 PM PDT 24
Peak memory 206312 kb
Host smart-90edb016-badd-4a76-a908-4e5a025f220b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31149
12001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.3114912001
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.3286335554
Short name T583
Test name
Test status
Simulation time 3296977455 ps
CPU time 3.87 seconds
Started Jun 30 06:23:44 PM PDT 24
Finished Jun 30 06:23:49 PM PDT 24
Peak memory 206296 kb
Host smart-55529596-dfcd-4869-b2e8-1dea977d1240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32863
35554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3286335554
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.1018032153
Short name T634
Test name
Test status
Simulation time 9210908210 ps
CPU time 243.45 seconds
Started Jun 30 06:23:40 PM PDT 24
Finished Jun 30 06:27:45 PM PDT 24
Peak memory 206468 kb
Host smart-a114ac69-bff6-4ed1-9c90-083d62fdd64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10180
32153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1018032153
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.252190570
Short name T361
Test name
Test status
Simulation time 6801200949 ps
CPU time 182.79 seconds
Started Jun 30 06:23:55 PM PDT 24
Finished Jun 30 06:27:00 PM PDT 24
Peak memory 206276 kb
Host smart-0be8acc1-81ee-4515-a997-f2e2a51cc648
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=252190570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.252190570
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.2627048751
Short name T686
Test name
Test status
Simulation time 243108630 ps
CPU time 0.89 seconds
Started Jun 30 06:23:41 PM PDT 24
Finished Jun 30 06:23:43 PM PDT 24
Peak memory 206216 kb
Host smart-04255e01-6a84-49c2-82c4-156d10a7b837
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2627048751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.2627048751
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.847139236
Short name T371
Test name
Test status
Simulation time 236137871 ps
CPU time 0.91 seconds
Started Jun 30 06:23:48 PM PDT 24
Finished Jun 30 06:23:51 PM PDT 24
Peak memory 206204 kb
Host smart-ca7cc789-bb59-4f75-a361-a4e4efa0701a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84713
9236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.847139236
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.1425427360
Short name T1009
Test name
Test status
Simulation time 4763633810 ps
CPU time 33.55 seconds
Started Jun 30 06:23:44 PM PDT 24
Finished Jun 30 06:24:18 PM PDT 24
Peak memory 206492 kb
Host smart-66bfdc73-a2c3-421b-ac7f-b643ea757f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14254
27360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.1425427360
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3304049403
Short name T2113
Test name
Test status
Simulation time 5275836440 ps
CPU time 143.11 seconds
Started Jun 30 06:23:39 PM PDT 24
Finished Jun 30 06:26:03 PM PDT 24
Peak memory 206456 kb
Host smart-841f6e25-9aaa-4a7b-8a3a-efe7d3fdebc2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3304049403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3304049403
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.2524683208
Short name T1214
Test name
Test status
Simulation time 165517456 ps
CPU time 0.94 seconds
Started Jun 30 06:23:40 PM PDT 24
Finished Jun 30 06:23:42 PM PDT 24
Peak memory 206192 kb
Host smart-5012a092-e34f-4802-994d-fe0769910523
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2524683208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.2524683208
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1548794329
Short name T2340
Test name
Test status
Simulation time 191966216 ps
CPU time 0.82 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:53 PM PDT 24
Peak memory 206200 kb
Host smart-9efbcb29-730b-4fbd-84b9-234ca3ef27fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15487
94329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1548794329
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.578907172
Short name T1152
Test name
Test status
Simulation time 213665389 ps
CPU time 0.88 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206212 kb
Host smart-4e6461d3-039e-4d89-ab42-5ec15c25072f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57890
7172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.578907172
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.1943876877
Short name T2178
Test name
Test status
Simulation time 215234778 ps
CPU time 0.83 seconds
Started Jun 30 06:23:54 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206032 kb
Host smart-0ff49c05-c14b-419a-b8a3-4b114a9b2925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19438
76877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1943876877
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3712018120
Short name T957
Test name
Test status
Simulation time 193877607 ps
CPU time 0.82 seconds
Started Jun 30 06:23:47 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206188 kb
Host smart-46a67812-08e7-4b7b-ae51-5afdf701d9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37120
18120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3712018120
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3940756188
Short name T415
Test name
Test status
Simulation time 181630434 ps
CPU time 0.83 seconds
Started Jun 30 06:23:48 PM PDT 24
Finished Jun 30 06:23:51 PM PDT 24
Peak memory 206192 kb
Host smart-5793ee1a-ca15-45a1-8cb7-f43e4b145c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39407
56188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3940756188
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3952412685
Short name T1420
Test name
Test status
Simulation time 161656421 ps
CPU time 0.8 seconds
Started Jun 30 06:23:40 PM PDT 24
Finished Jun 30 06:23:41 PM PDT 24
Peak memory 206200 kb
Host smart-05985f36-618f-4077-80d8-5f9f6eeb6a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39524
12685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3952412685
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.2501299628
Short name T1893
Test name
Test status
Simulation time 243427186 ps
CPU time 0.91 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:54 PM PDT 24
Peak memory 206212 kb
Host smart-d1690cb9-c7c7-467d-8d8b-696cbc4e635e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2501299628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.2501299628
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2302610073
Short name T1199
Test name
Test status
Simulation time 168567795 ps
CPU time 0.8 seconds
Started Jun 30 06:23:54 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206036 kb
Host smart-e972fd4a-358a-4ac9-8264-b60f3d1ccd53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23026
10073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2302610073
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1809353860
Short name T794
Test name
Test status
Simulation time 47284345 ps
CPU time 0.68 seconds
Started Jun 30 06:23:40 PM PDT 24
Finished Jun 30 06:23:41 PM PDT 24
Peak memory 206164 kb
Host smart-01d5f2a3-d2e4-4dbc-89bd-0aee0b44fb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18093
53860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1809353860
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.889150585
Short name T267
Test name
Test status
Simulation time 11125465253 ps
CPU time 23.31 seconds
Started Jun 30 06:23:54 PM PDT 24
Finished Jun 30 06:24:20 PM PDT 24
Peak memory 206280 kb
Host smart-dc388d6a-627c-4624-ad14-a14ca79ceff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88915
0585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.889150585
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1319654575
Short name T1130
Test name
Test status
Simulation time 187255878 ps
CPU time 0.83 seconds
Started Jun 30 06:23:48 PM PDT 24
Finished Jun 30 06:23:51 PM PDT 24
Peak memory 206188 kb
Host smart-16bf905b-de2e-4a3e-bbb5-8a4a2290c448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13196
54575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1319654575
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3630674062
Short name T458
Test name
Test status
Simulation time 226494215 ps
CPU time 0.88 seconds
Started Jun 30 06:23:50 PM PDT 24
Finished Jun 30 06:23:52 PM PDT 24
Peak memory 206204 kb
Host smart-5c62b0b9-eecf-4088-8849-074dcc30f72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36306
74062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3630674062
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.2079683711
Short name T2018
Test name
Test status
Simulation time 226057891 ps
CPU time 0.87 seconds
Started Jun 30 06:23:55 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206060 kb
Host smart-ed3d8d81-6ab1-4548-a7f2-9ec82b7e3253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20796
83711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.2079683711
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3882916699
Short name T1638
Test name
Test status
Simulation time 152732539 ps
CPU time 0.8 seconds
Started Jun 30 06:23:40 PM PDT 24
Finished Jun 30 06:23:42 PM PDT 24
Peak memory 206164 kb
Host smart-d6dba87c-76ba-4e18-b862-09247e80488d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38829
16699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3882916699
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.2260892711
Short name T2207
Test name
Test status
Simulation time 183958927 ps
CPU time 0.82 seconds
Started Jun 30 06:23:40 PM PDT 24
Finished Jun 30 06:23:41 PM PDT 24
Peak memory 206176 kb
Host smart-ee0cdee0-0c40-43fa-a867-b350ddba82ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22608
92711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.2260892711
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1220723165
Short name T2099
Test name
Test status
Simulation time 165353167 ps
CPU time 0.8 seconds
Started Jun 30 06:23:43 PM PDT 24
Finished Jun 30 06:23:44 PM PDT 24
Peak memory 206148 kb
Host smart-baa43b4a-4e40-4b80-a7a9-2bbbb59f759d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12207
23165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1220723165
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.52323810
Short name T1011
Test name
Test status
Simulation time 156950790 ps
CPU time 0.78 seconds
Started Jun 30 06:23:54 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206032 kb
Host smart-b244b5f1-5b8f-455c-8b81-edb5c7488007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52323
810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.52323810
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.4123802785
Short name T627
Test name
Test status
Simulation time 211099707 ps
CPU time 0.87 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:53 PM PDT 24
Peak memory 206212 kb
Host smart-d71766b8-0fbd-4815-91c6-49a4e757293b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41238
02785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.4123802785
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.2444459441
Short name T728
Test name
Test status
Simulation time 5569220205 ps
CPU time 139.78 seconds
Started Jun 30 06:23:54 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206296 kb
Host smart-ca0f4aac-e032-4769-a57a-48c33ebc54de
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2444459441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.2444459441
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.4155638710
Short name T1156
Test name
Test status
Simulation time 189688823 ps
CPU time 0.86 seconds
Started Jun 30 06:23:49 PM PDT 24
Finished Jun 30 06:23:51 PM PDT 24
Peak memory 206168 kb
Host smart-e7ec91e1-53ab-4265-be30-a7cb62608222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41556
38710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.4155638710
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1100208433
Short name T1343
Test name
Test status
Simulation time 186698602 ps
CPU time 0.8 seconds
Started Jun 30 06:23:50 PM PDT 24
Finished Jun 30 06:23:52 PM PDT 24
Peak memory 206188 kb
Host smart-5f17d4b2-d5f4-4d0b-bcdd-9c3fc43128fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11002
08433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1100208433
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2299411258
Short name T1276
Test name
Test status
Simulation time 5456376152 ps
CPU time 151.52 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206368 kb
Host smart-0c2f9040-5f31-4c63-b697-c85b0ffc9fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22994
11258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2299411258
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2776151745
Short name T899
Test name
Test status
Simulation time 62009879 ps
CPU time 0.67 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:54 PM PDT 24
Peak memory 206208 kb
Host smart-e4b56dd4-2a6e-493f-8b7e-831c91397204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2776151745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2776151745
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2987283844
Short name T1919
Test name
Test status
Simulation time 4208940719 ps
CPU time 5.5 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206284 kb
Host smart-60e28a4c-5c5b-42a8-b386-89ad80f8adeb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2987283844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.2987283844
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.292054557
Short name T1684
Test name
Test status
Simulation time 13468679776 ps
CPU time 15.58 seconds
Started Jun 30 06:23:50 PM PDT 24
Finished Jun 30 06:24:07 PM PDT 24
Peak memory 206428 kb
Host smart-e90a8f5f-ef04-4e7b-80d5-38593692a307
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=292054557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.292054557
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.4051713365
Short name T536
Test name
Test status
Simulation time 23388437840 ps
CPU time 28.72 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:24:16 PM PDT 24
Peak memory 206440 kb
Host smart-83cd3a65-ea89-402b-8555-7feb2d01b16c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4051713365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.4051713365
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.4097479775
Short name T403
Test name
Test status
Simulation time 151435602 ps
CPU time 0.81 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206184 kb
Host smart-987b114d-2571-4adb-b869-d1c0086192f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40974
79775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.4097479775
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.3228253906
Short name T2173
Test name
Test status
Simulation time 149645168 ps
CPU time 0.77 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:54 PM PDT 24
Peak memory 206148 kb
Host smart-5d41d63f-dd88-498a-90c8-45a00b8a4d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32282
53906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.3228253906
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.2765915002
Short name T1871
Test name
Test status
Simulation time 321677951 ps
CPU time 1.11 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:49 PM PDT 24
Peak memory 206168 kb
Host smart-acccb280-750b-4761-9ccb-ad97cdf45b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27659
15002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.2765915002
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.384295109
Short name T193
Test name
Test status
Simulation time 946713102 ps
CPU time 2.14 seconds
Started Jun 30 06:23:48 PM PDT 24
Finished Jun 30 06:23:52 PM PDT 24
Peak memory 206296 kb
Host smart-846a14cb-e558-40c1-9ef7-31a8167e287d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38429
5109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.384295109
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.3948925883
Short name T1366
Test name
Test status
Simulation time 8126910785 ps
CPU time 17.7 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:24:14 PM PDT 24
Peak memory 206468 kb
Host smart-a7072bf8-93ba-4b2d-a6c8-8fc0b9982c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39489
25883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.3948925883
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3305415495
Short name T1756
Test name
Test status
Simulation time 469411918 ps
CPU time 1.46 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206184 kb
Host smart-a6959d56-48e4-4f5e-b434-7ee685a2f2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33054
15495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3305415495
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.4058103064
Short name T1995
Test name
Test status
Simulation time 185586471 ps
CPU time 0.8 seconds
Started Jun 30 06:23:47 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206156 kb
Host smart-778d9082-b3ee-42e3-bcd5-e7c03a06a04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40581
03064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.4058103064
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1575095519
Short name T1543
Test name
Test status
Simulation time 45688420 ps
CPU time 0.65 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:54 PM PDT 24
Peak memory 206172 kb
Host smart-30e918b3-9d84-43c0-bdd1-a185eda6afb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15750
95519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1575095519
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1697723150
Short name T967
Test name
Test status
Simulation time 773808222 ps
CPU time 1.88 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206280 kb
Host smart-b3835d09-3acc-4430-b9aa-e6e75e403d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16977
23150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1697723150
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3583495122
Short name T1616
Test name
Test status
Simulation time 229848235 ps
CPU time 2.1 seconds
Started Jun 30 06:23:46 PM PDT 24
Finished Jun 30 06:23:50 PM PDT 24
Peak memory 206316 kb
Host smart-dcf826f4-7b8d-4982-970a-47246cac5e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35834
95122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3583495122
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.451190561
Short name T1330
Test name
Test status
Simulation time 169156862 ps
CPU time 0.8 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206156 kb
Host smart-ac714d13-526b-4471-860a-212d97a64f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45119
0561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.451190561
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1262559079
Short name T1062
Test name
Test status
Simulation time 183908218 ps
CPU time 0.83 seconds
Started Jun 30 06:23:55 PM PDT 24
Finished Jun 30 06:23:58 PM PDT 24
Peak memory 206024 kb
Host smart-7fed732e-af52-40d5-82cc-f93a3df8ee4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12625
59079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1262559079
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.4080407151
Short name T2606
Test name
Test status
Simulation time 236069488 ps
CPU time 0.88 seconds
Started Jun 30 06:23:54 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206224 kb
Host smart-4dc113f2-a77f-4703-96fc-a741d5167da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40804
07151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.4080407151
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.4162428100
Short name T1719
Test name
Test status
Simulation time 5187945005 ps
CPU time 36.78 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:24:29 PM PDT 24
Peak memory 206376 kb
Host smart-058fd05a-7be1-437d-95d8-6f92c2360f0b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4162428100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.4162428100
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2718232681
Short name T1891
Test name
Test status
Simulation time 171476405 ps
CPU time 0.78 seconds
Started Jun 30 06:23:50 PM PDT 24
Finished Jun 30 06:23:52 PM PDT 24
Peak memory 206188 kb
Host smart-bf8c1640-e530-4f36-b490-f5624a49beea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27182
32681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2718232681
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.304900510
Short name T2066
Test name
Test status
Simulation time 23319980956 ps
CPU time 27.08 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:24:26 PM PDT 24
Peak memory 206304 kb
Host smart-ed07f043-60a7-4bdd-8c91-8b56a078bfcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30490
0510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.304900510
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1303417458
Short name T1202
Test name
Test status
Simulation time 3332038160 ps
CPU time 3.64 seconds
Started Jun 30 06:23:49 PM PDT 24
Finished Jun 30 06:23:54 PM PDT 24
Peak memory 206248 kb
Host smart-b390e9d6-264c-46ab-8428-8eca1071fa57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13034
17458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1303417458
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.2964200280
Short name T1897
Test name
Test status
Simulation time 6463804539 ps
CPU time 176.3 seconds
Started Jun 30 06:23:50 PM PDT 24
Finished Jun 30 06:26:48 PM PDT 24
Peak memory 206468 kb
Host smart-6aec85d8-76b5-4865-8710-6691ab1f6295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29642
00280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.2964200280
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.433276375
Short name T657
Test name
Test status
Simulation time 5213598369 ps
CPU time 38.06 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:24:25 PM PDT 24
Peak memory 206456 kb
Host smart-3343d145-d08e-4cce-8250-1e90d1396ec6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=433276375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.433276375
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1537000065
Short name T2002
Test name
Test status
Simulation time 237678136 ps
CPU time 0.9 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206212 kb
Host smart-9510b6fc-f175-4178-8f75-dfa3f64e5d64
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1537000065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1537000065
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1094717628
Short name T483
Test name
Test status
Simulation time 184908369 ps
CPU time 0.83 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:47 PM PDT 24
Peak memory 206184 kb
Host smart-b210b131-067d-4fd3-8055-94ec05b70545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10947
17628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1094717628
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.73795818
Short name T1313
Test name
Test status
Simulation time 5790684130 ps
CPU time 168.29 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:26:42 PM PDT 24
Peak memory 206448 kb
Host smart-31100202-85b9-4d40-8120-b808f2b6639e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73795
818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.73795818
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1621614830
Short name T1585
Test name
Test status
Simulation time 5467561070 ps
CPU time 42.08 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206436 kb
Host smart-b408598e-414f-4d27-8569-3c4f87711f94
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1621614830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1621614830
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2774883445
Short name T2127
Test name
Test status
Simulation time 162148742 ps
CPU time 0.83 seconds
Started Jun 30 06:23:54 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206228 kb
Host smart-1d91f06b-7c43-49c3-9659-2b4af8ce3d95
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2774883445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2774883445
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1493636113
Short name T1912
Test name
Test status
Simulation time 168700661 ps
CPU time 0.76 seconds
Started Jun 30 06:23:55 PM PDT 24
Finished Jun 30 06:23:58 PM PDT 24
Peak memory 206040 kb
Host smart-126f6da1-8ce2-439f-b730-3016326332e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14936
36113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1493636113
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.889007895
Short name T130
Test name
Test status
Simulation time 216651298 ps
CPU time 0.84 seconds
Started Jun 30 06:23:46 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206180 kb
Host smart-64e16654-ae14-474f-af83-94081783e0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88900
7895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.889007895
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.2683830089
Short name T2537
Test name
Test status
Simulation time 181381356 ps
CPU time 0.83 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:48 PM PDT 24
Peak memory 206200 kb
Host smart-2f6ffabf-f789-49d7-b229-dc472fa36381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26838
30089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2683830089
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2458203914
Short name T2570
Test name
Test status
Simulation time 145213741 ps
CPU time 0.77 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206172 kb
Host smart-6159a257-d748-4721-95f5-9e65204c126c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24582
03914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2458203914
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3226455910
Short name T1233
Test name
Test status
Simulation time 205717373 ps
CPU time 0.8 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206204 kb
Host smart-558e64a6-585d-4046-a897-4d74800f8825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32264
55910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3226455910
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3039722076
Short name T192
Test name
Test status
Simulation time 168265634 ps
CPU time 0.77 seconds
Started Jun 30 06:23:44 PM PDT 24
Finished Jun 30 06:23:46 PM PDT 24
Peak memory 206204 kb
Host smart-ed287594-801c-42db-8899-62d22e203d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30397
22076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3039722076
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.421215545
Short name T1029
Test name
Test status
Simulation time 230871863 ps
CPU time 0.94 seconds
Started Jun 30 06:23:45 PM PDT 24
Finished Jun 30 06:23:47 PM PDT 24
Peak memory 206212 kb
Host smart-a8ec3559-cf3d-4342-988e-508e6ce2b773
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=421215545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.421215545
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3552093784
Short name T1604
Test name
Test status
Simulation time 149687979 ps
CPU time 0.8 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206176 kb
Host smart-a28c4817-2cb1-4e70-b45e-91574ba82171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35520
93784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3552093784
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.938281313
Short name T1404
Test name
Test status
Simulation time 38835703 ps
CPU time 0.65 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206200 kb
Host smart-a4c09f56-e9ac-45d1-89ca-d5f223ea15f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93828
1313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.938281313
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2625307880
Short name T268
Test name
Test status
Simulation time 23356894701 ps
CPU time 55 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 206488 kb
Host smart-2bb2e3aa-1023-4a11-860d-ef350adbcba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26253
07880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2625307880
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.153526966
Short name T2396
Test name
Test status
Simulation time 198417875 ps
CPU time 0.84 seconds
Started Jun 30 06:23:48 PM PDT 24
Finished Jun 30 06:23:51 PM PDT 24
Peak memory 206184 kb
Host smart-9a7d5bd4-4623-41ef-9bd4-974610fbe0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15352
6966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.153526966
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2402199249
Short name T797
Test name
Test status
Simulation time 208169967 ps
CPU time 0.87 seconds
Started Jun 30 06:23:55 PM PDT 24
Finished Jun 30 06:23:58 PM PDT 24
Peak memory 206040 kb
Host smart-7e5d9f21-45c6-4504-98e2-258553e8a90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24021
99249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2402199249
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3432893320
Short name T1003
Test name
Test status
Simulation time 224830174 ps
CPU time 0.87 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206240 kb
Host smart-f9964b5d-c1a1-41f0-be6c-723ff24fdc89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34328
93320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3432893320
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2962890964
Short name T2394
Test name
Test status
Simulation time 180643408 ps
CPU time 0.87 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:54 PM PDT 24
Peak memory 206196 kb
Host smart-24155c9b-c66b-4521-b608-56e2e48f5a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29628
90964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2962890964
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.2443489713
Short name T2156
Test name
Test status
Simulation time 223182111 ps
CPU time 0.85 seconds
Started Jun 30 06:23:54 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206188 kb
Host smart-382b6d60-d719-4384-a228-6563d998c528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24434
89713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.2443489713
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2647879076
Short name T2293
Test name
Test status
Simulation time 145115141 ps
CPU time 0.83 seconds
Started Jun 30 06:23:59 PM PDT 24
Finished Jun 30 06:24:01 PM PDT 24
Peak memory 206184 kb
Host smart-7cd26355-c412-4f67-a118-27685ce7ef22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26478
79076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2647879076
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1296283929
Short name T95
Test name
Test status
Simulation time 166536006 ps
CPU time 0.78 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206156 kb
Host smart-7064562c-8e46-449e-9cdb-80d59749671a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12962
83929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1296283929
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3297644686
Short name T962
Test name
Test status
Simulation time 211839975 ps
CPU time 0.93 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206232 kb
Host smart-b0db198a-7c66-48bb-91e2-bf5505a61353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32976
44686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3297644686
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.416095165
Short name T2009
Test name
Test status
Simulation time 5693710329 ps
CPU time 157.37 seconds
Started Jun 30 06:23:54 PM PDT 24
Finished Jun 30 06:26:34 PM PDT 24
Peak memory 206476 kb
Host smart-6c0889f6-eb67-4950-b7c1-40c34319008b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=416095165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.416095165
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2817973158
Short name T778
Test name
Test status
Simulation time 176306958 ps
CPU time 0.83 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206176 kb
Host smart-363a215f-9c28-4397-9b7f-3c5d44d71c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28179
73158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2817973158
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1918365634
Short name T811
Test name
Test status
Simulation time 178906269 ps
CPU time 0.82 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206192 kb
Host smart-ab8b125a-3b2e-438c-a92a-4b56f1444616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19183
65634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1918365634
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3558238967
Short name T695
Test name
Test status
Simulation time 3260841057 ps
CPU time 32.65 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206448 kb
Host smart-1c86c0e0-8120-490d-b855-fc46992f4492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35582
38967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3558238967
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.815271102
Short name T2120
Test name
Test status
Simulation time 76391741 ps
CPU time 0.72 seconds
Started Jun 30 06:24:05 PM PDT 24
Finished Jun 30 06:24:06 PM PDT 24
Peak memory 206208 kb
Host smart-42e712af-269d-4961-9230-1ce5eb0126b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=815271102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.815271102
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3538210413
Short name T2369
Test name
Test status
Simulation time 3672065307 ps
CPU time 4.3 seconds
Started Jun 30 06:23:56 PM PDT 24
Finished Jun 30 06:24:01 PM PDT 24
Peak memory 206356 kb
Host smart-a66a91a9-f09b-4a44-be6c-6c4f72abc9ad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3538210413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.3538210413
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2104931415
Short name T1980
Test name
Test status
Simulation time 13367185873 ps
CPU time 11.86 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:24:06 PM PDT 24
Peak memory 206428 kb
Host smart-eaa70093-95d7-4810-8ced-f51cca520a78
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2104931415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2104931415
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.3472513183
Short name T1641
Test name
Test status
Simulation time 23315731585 ps
CPU time 25.03 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:24:20 PM PDT 24
Peak memory 206292 kb
Host smart-6a3f8eae-446f-4323-b4da-a27d03efa9ca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3472513183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.3472513183
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2300932927
Short name T1047
Test name
Test status
Simulation time 153689008 ps
CPU time 0.79 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:24:00 PM PDT 24
Peak memory 206188 kb
Host smart-0484d067-3a59-4d14-87f2-285215ffdb33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23009
32927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2300932927
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3136952999
Short name T870
Test name
Test status
Simulation time 170261766 ps
CPU time 0.85 seconds
Started Jun 30 06:23:59 PM PDT 24
Finished Jun 30 06:24:00 PM PDT 24
Peak memory 206168 kb
Host smart-eb8c75de-b20d-4891-b667-becc8e2e3277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31369
52999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3136952999
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.70414311
Short name T1203
Test name
Test status
Simulation time 208096935 ps
CPU time 0.87 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206204 kb
Host smart-439bba80-ff42-4dcf-90f7-b4fb7310ed54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70414
311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.70414311
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3489766434
Short name T1915
Test name
Test status
Simulation time 1448017035 ps
CPU time 3.21 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:23:58 PM PDT 24
Peak memory 206268 kb
Host smart-6e82e7a9-3901-45dd-a0da-a54ec915c6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34897
66434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3489766434
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.3399359930
Short name T1245
Test name
Test status
Simulation time 13569238276 ps
CPU time 30.76 seconds
Started Jun 30 06:23:57 PM PDT 24
Finished Jun 30 06:24:29 PM PDT 24
Peak memory 206412 kb
Host smart-126b01c2-8a4f-427c-be70-ab2cba00d5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33993
59930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3399359930
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.844658017
Short name T1295
Test name
Test status
Simulation time 489448189 ps
CPU time 1.4 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206204 kb
Host smart-da8070cc-586f-4869-b72c-e4ebafcace72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84465
8017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.844658017
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1551624363
Short name T1161
Test name
Test status
Simulation time 157649402 ps
CPU time 0.73 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206156 kb
Host smart-5af65e24-3681-4df6-9a67-d1d81a455033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15516
24363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1551624363
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.819170426
Short name T439
Test name
Test status
Simulation time 42951470 ps
CPU time 0.7 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:23:55 PM PDT 24
Peak memory 206148 kb
Host smart-c906a87b-c76e-4f59-9a0c-0c08baa88a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81917
0426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.819170426
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2962705969
Short name T1468
Test name
Test status
Simulation time 600765081 ps
CPU time 1.67 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206268 kb
Host smart-72497063-5961-4a58-9222-6b87d026f320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29627
05969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2962705969
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2044361277
Short name T2557
Test name
Test status
Simulation time 195315951 ps
CPU time 1.9 seconds
Started Jun 30 06:23:56 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206136 kb
Host smart-64b10a7c-6c03-4185-bba4-a048bd17c1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443
61277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2044361277
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1531351400
Short name T1856
Test name
Test status
Simulation time 243296477 ps
CPU time 0.91 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:54 PM PDT 24
Peak memory 206120 kb
Host smart-8adafb6e-ed06-40aa-b164-b41afb190874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15313
51400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1531351400
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.4012512382
Short name T1079
Test name
Test status
Simulation time 146758071 ps
CPU time 0.81 seconds
Started Jun 30 06:23:55 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206212 kb
Host smart-a55d5501-30fb-4a05-b7d2-b5e0dfcffab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40125
12382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.4012512382
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3526595221
Short name T1504
Test name
Test status
Simulation time 203064757 ps
CPU time 0.89 seconds
Started Jun 30 06:23:51 PM PDT 24
Finished Jun 30 06:23:54 PM PDT 24
Peak memory 206212 kb
Host smart-17709955-7318-42a5-a46e-731eba358255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35265
95221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3526595221
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.3961423278
Short name T2410
Test name
Test status
Simulation time 10315645317 ps
CPU time 104.21 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206396 kb
Host smart-d15c1baa-b804-4253-bc8a-7109502d7a93
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3961423278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.3961423278
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1704630114
Short name T2439
Test name
Test status
Simulation time 185051025 ps
CPU time 0.79 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206144 kb
Host smart-2c9c0979-3938-48ec-92f0-c9cd0e4aa95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17046
30114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1704630114
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.1309439473
Short name T2139
Test name
Test status
Simulation time 23356533842 ps
CPU time 25.47 seconds
Started Jun 30 06:23:50 PM PDT 24
Finished Jun 30 06:24:17 PM PDT 24
Peak memory 206296 kb
Host smart-9bee7c31-8a11-41a2-a1ae-a2aaeba07bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13094
39473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.1309439473
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2706216320
Short name T428
Test name
Test status
Simulation time 3343324052 ps
CPU time 3.9 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:24:02 PM PDT 24
Peak memory 206240 kb
Host smart-60fab9eb-77d9-42d9-aee1-0bb8d2d6ce93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27062
16320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2706216320
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.429485230
Short name T2317
Test name
Test status
Simulation time 7109686027 ps
CPU time 197.52 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 206548 kb
Host smart-ef1b577e-0ee0-4841-8540-3fd001796580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42948
5230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.429485230
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2499267365
Short name T6
Test name
Test status
Simulation time 5240035581 ps
CPU time 50.9 seconds
Started Jun 30 06:23:56 PM PDT 24
Finished Jun 30 06:24:48 PM PDT 24
Peak memory 206484 kb
Host smart-270356ca-e792-40b9-bd00-79032fd7da3b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2499267365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2499267365
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1326196391
Short name T996
Test name
Test status
Simulation time 240608490 ps
CPU time 0.92 seconds
Started Jun 30 06:23:53 PM PDT 24
Finished Jun 30 06:23:57 PM PDT 24
Peak memory 206356 kb
Host smart-d75984f0-6520-40ac-8e5f-1b023094af89
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1326196391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1326196391
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2059316789
Short name T572
Test name
Test status
Simulation time 196465407 ps
CPU time 0.85 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206192 kb
Host smart-45bf25ce-5770-404c-a779-069b387d53ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20593
16789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2059316789
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.837140768
Short name T1484
Test name
Test status
Simulation time 6284215413 ps
CPU time 175.38 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:26:54 PM PDT 24
Peak memory 206432 kb
Host smart-83bdd817-a6e2-427d-a8c0-bcbec7ec984a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83714
0768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.837140768
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.4207223779
Short name T1177
Test name
Test status
Simulation time 6321763688 ps
CPU time 62.57 seconds
Started Jun 30 06:23:52 PM PDT 24
Finished Jun 30 06:24:58 PM PDT 24
Peak memory 206408 kb
Host smart-9f42e1cd-5618-4431-bd35-fc35a76df304
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4207223779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.4207223779
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.194543292
Short name T438
Test name
Test status
Simulation time 165134542 ps
CPU time 0.82 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206212 kb
Host smart-390b4c9c-f8b6-4af3-90f0-13b21a7e25c9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=194543292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.194543292
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2950327000
Short name T2339
Test name
Test status
Simulation time 150959078 ps
CPU time 0.73 seconds
Started Jun 30 06:23:56 PM PDT 24
Finished Jun 30 06:23:58 PM PDT 24
Peak memory 206196 kb
Host smart-5d67a6c5-5799-450c-aa1d-96352500a97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29503
27000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2950327000
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2727186652
Short name T120
Test name
Test status
Simulation time 196458415 ps
CPU time 0.88 seconds
Started Jun 30 06:24:03 PM PDT 24
Finished Jun 30 06:24:04 PM PDT 24
Peak memory 206188 kb
Host smart-55a5a703-50b5-4e99-8560-f84527799737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27271
86652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2727186652
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.4212435834
Short name T1903
Test name
Test status
Simulation time 179987279 ps
CPU time 0.77 seconds
Started Jun 30 06:23:57 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206172 kb
Host smart-cd7518d5-d729-477d-a6cb-ab0939ba95a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42124
35834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.4212435834
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3730504962
Short name T2118
Test name
Test status
Simulation time 201025046 ps
CPU time 0.82 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:24:00 PM PDT 24
Peak memory 206152 kb
Host smart-2891e61a-0e7a-4b3f-b4a3-9afe26a59455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37305
04962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3730504962
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1392765513
Short name T2052
Test name
Test status
Simulation time 176827117 ps
CPU time 0.86 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206216 kb
Host smart-72bf2fdd-69ae-482f-9a95-3a2d7dcaa69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13927
65513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1392765513
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.94167668
Short name T201
Test name
Test status
Simulation time 160099879 ps
CPU time 0.79 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206208 kb
Host smart-331483fa-94ea-4721-b06c-bf4fe587d55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94167
668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.94167668
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2138429949
Short name T153
Test name
Test status
Simulation time 266717464 ps
CPU time 0.98 seconds
Started Jun 30 06:24:04 PM PDT 24
Finished Jun 30 06:24:06 PM PDT 24
Peak memory 206208 kb
Host smart-68a043f0-6a40-4c6d-9d6a-af31cb4380e4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2138429949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2138429949
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.647584737
Short name T929
Test name
Test status
Simulation time 156790145 ps
CPU time 0.73 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206192 kb
Host smart-e75f45e6-a254-4d86-9eb9-091913286492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64758
4737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.647584737
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3184544359
Short name T1810
Test name
Test status
Simulation time 43593965 ps
CPU time 0.64 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206176 kb
Host smart-d7331edc-5508-4e78-8921-d1b2c715ca26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31845
44359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3184544359
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3773642134
Short name T2511
Test name
Test status
Simulation time 20060212445 ps
CPU time 43.76 seconds
Started Jun 30 06:24:02 PM PDT 24
Finished Jun 30 06:24:47 PM PDT 24
Peak memory 206652 kb
Host smart-2ea0daf0-46ae-4856-97fa-6f266b3b3e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37736
42134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3773642134
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3144451102
Short name T622
Test name
Test status
Simulation time 165077083 ps
CPU time 0.84 seconds
Started Jun 30 06:23:58 PM PDT 24
Finished Jun 30 06:24:00 PM PDT 24
Peak memory 206196 kb
Host smart-65745187-9848-48e7-a6b8-474a6683e990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31444
51102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3144451102
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1773267696
Short name T2171
Test name
Test status
Simulation time 206264386 ps
CPU time 0.84 seconds
Started Jun 30 06:23:59 PM PDT 24
Finished Jun 30 06:24:01 PM PDT 24
Peak memory 206196 kb
Host smart-58bfc5b3-6324-4850-8093-1af6b293a63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17732
67696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1773267696
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1481249686
Short name T1451
Test name
Test status
Simulation time 232227256 ps
CPU time 0.89 seconds
Started Jun 30 06:24:02 PM PDT 24
Finished Jun 30 06:24:03 PM PDT 24
Peak memory 206172 kb
Host smart-d16a3e27-56a6-4899-a21f-acc24ef50743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14812
49686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1481249686
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.1777748837
Short name T2313
Test name
Test status
Simulation time 197637324 ps
CPU time 0.81 seconds
Started Jun 30 06:24:02 PM PDT 24
Finished Jun 30 06:24:03 PM PDT 24
Peak memory 206156 kb
Host smart-9e5217d4-49ff-4cab-9330-7dd2f5dc96a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17777
48837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.1777748837
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.55327534
Short name T896
Test name
Test status
Simulation time 191191797 ps
CPU time 0.81 seconds
Started Jun 30 06:24:00 PM PDT 24
Finished Jun 30 06:24:01 PM PDT 24
Peak memory 206172 kb
Host smart-ec2f07de-663f-4000-b6e1-aad88bb2c1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55327
534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.55327534
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3396152883
Short name T1730
Test name
Test status
Simulation time 151927043 ps
CPU time 0.75 seconds
Started Jun 30 06:23:57 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206188 kb
Host smart-6619722d-e025-4f36-9596-7522f6a7464c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33961
52883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3396152883
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3573827768
Short name T2371
Test name
Test status
Simulation time 167403906 ps
CPU time 0.78 seconds
Started Jun 30 06:23:57 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206180 kb
Host smart-741a0d56-cf20-4a2d-94d0-9af32183c28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35738
27768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3573827768
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3257025415
Short name T50
Test name
Test status
Simulation time 256104381 ps
CPU time 0.98 seconds
Started Jun 30 06:24:03 PM PDT 24
Finished Jun 30 06:24:04 PM PDT 24
Peak memory 206188 kb
Host smart-61f85b7c-6ae7-4e46-8f24-15bcf90c45b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32570
25415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3257025415
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.537387808
Short name T765
Test name
Test status
Simulation time 6092414265 ps
CPU time 172.39 seconds
Started Jun 30 06:24:00 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206464 kb
Host smart-e89b07c0-eabd-421d-b7e3-d9fa0bc9edc4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=537387808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.537387808
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.618725744
Short name T1278
Test name
Test status
Simulation time 207554009 ps
CPU time 0.88 seconds
Started Jun 30 06:24:00 PM PDT 24
Finished Jun 30 06:24:02 PM PDT 24
Peak memory 206212 kb
Host smart-e82f7f88-73be-4108-ac4d-d9a47c6c4f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61872
5744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.618725744
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.4202181887
Short name T2233
Test name
Test status
Simulation time 159992379 ps
CPU time 0.78 seconds
Started Jun 30 06:23:57 PM PDT 24
Finished Jun 30 06:23:59 PM PDT 24
Peak memory 206156 kb
Host smart-3a9a634a-6ae8-47f7-af60-7f7e82b2ead8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42021
81887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.4202181887
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1254805542
Short name T1265
Test name
Test status
Simulation time 4511253791 ps
CPU time 121.96 seconds
Started Jun 30 06:24:04 PM PDT 24
Finished Jun 30 06:26:07 PM PDT 24
Peak memory 206388 kb
Host smart-633d23cd-d5d1-42fd-ab03-b22269b50867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12548
05542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1254805542
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.1738533361
Short name T2279
Test name
Test status
Simulation time 55050915 ps
CPU time 0.7 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206140 kb
Host smart-e0792898-b349-462f-a58c-7c84fbb90393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1738533361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.1738533361
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3444251819
Short name T1049
Test name
Test status
Simulation time 4246299398 ps
CPU time 5.4 seconds
Started Jun 30 06:24:07 PM PDT 24
Finished Jun 30 06:24:13 PM PDT 24
Peak memory 206580 kb
Host smart-b713c3bd-7cec-4fe2-8a0c-d3ca76a6eed4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3444251819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.3444251819
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.3453788682
Short name T1948
Test name
Test status
Simulation time 13366177694 ps
CPU time 13.35 seconds
Started Jun 30 06:24:04 PM PDT 24
Finished Jun 30 06:24:18 PM PDT 24
Peak memory 206320 kb
Host smart-ec6b50a5-63aa-43c4-9ed6-28e6f12d3484
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3453788682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.3453788682
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.244237469
Short name T1880
Test name
Test status
Simulation time 23459214439 ps
CPU time 22.66 seconds
Started Jun 30 06:24:05 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206372 kb
Host smart-36a46633-d3e4-4b01-a86f-e415b06546f2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=244237469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.244237469
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1015065140
Short name T2618
Test name
Test status
Simulation time 152531212 ps
CPU time 0.8 seconds
Started Jun 30 06:24:06 PM PDT 24
Finished Jun 30 06:24:07 PM PDT 24
Peak memory 206176 kb
Host smart-d5b7c06a-c722-478a-a33b-e5bbdfd934b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10150
65140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1015065140
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2932573449
Short name T775
Test name
Test status
Simulation time 160297098 ps
CPU time 0.79 seconds
Started Jun 30 06:24:04 PM PDT 24
Finished Jun 30 06:24:05 PM PDT 24
Peak memory 206192 kb
Host smart-93c2ebc0-1755-4812-92c9-e7d3b87a5991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29325
73449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2932573449
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2161704282
Short name T2141
Test name
Test status
Simulation time 354466973 ps
CPU time 1.14 seconds
Started Jun 30 06:24:06 PM PDT 24
Finished Jun 30 06:24:08 PM PDT 24
Peak memory 205968 kb
Host smart-cdf295b5-73e3-43ac-a3ac-77460b5bb47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21617
04282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2161704282
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.834457869
Short name T2000
Test name
Test status
Simulation time 18050318515 ps
CPU time 33.48 seconds
Started Jun 30 06:24:04 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206372 kb
Host smart-75b89336-172b-49a3-853b-6aa707a3ff6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83445
7869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.834457869
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3817234007
Short name T2335
Test name
Test status
Simulation time 445235114 ps
CPU time 1.41 seconds
Started Jun 30 06:24:06 PM PDT 24
Finished Jun 30 06:24:08 PM PDT 24
Peak memory 206200 kb
Host smart-7823ce8d-b6d0-4709-a5e0-51611aa90e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38172
34007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3817234007
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.2620559868
Short name T514
Test name
Test status
Simulation time 149612511 ps
CPU time 0.8 seconds
Started Jun 30 06:24:06 PM PDT 24
Finished Jun 30 06:24:07 PM PDT 24
Peak memory 206200 kb
Host smart-acc0e2fc-f7ba-4d6d-b654-352fa26df9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26205
59868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2620559868
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3523874866
Short name T2539
Test name
Test status
Simulation time 61885164 ps
CPU time 0.7 seconds
Started Jun 30 06:24:04 PM PDT 24
Finished Jun 30 06:24:05 PM PDT 24
Peak memory 206156 kb
Host smart-605499b0-ed41-4e81-b11b-0ce8646f77fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35238
74866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3523874866
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1855672703
Short name T1371
Test name
Test status
Simulation time 934451501 ps
CPU time 2.24 seconds
Started Jun 30 06:24:04 PM PDT 24
Finished Jun 30 06:24:07 PM PDT 24
Peak memory 206284 kb
Host smart-2def9389-aedf-47ec-898c-cd8ba66f53d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18556
72703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1855672703
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.259788260
Short name T821
Test name
Test status
Simulation time 194072208 ps
CPU time 1.73 seconds
Started Jun 30 06:24:08 PM PDT 24
Finished Jun 30 06:24:10 PM PDT 24
Peak memory 206264 kb
Host smart-102b003f-6d07-4aa0-98e8-b76316e6c4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25978
8260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.259788260
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.4052036673
Short name T629
Test name
Test status
Simulation time 256050970 ps
CPU time 0.9 seconds
Started Jun 30 06:24:06 PM PDT 24
Finished Jun 30 06:24:07 PM PDT 24
Peak memory 206180 kb
Host smart-5faf394e-95c9-498a-ad3e-1f7cd4e90044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40520
36673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.4052036673
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1777039103
Short name T1440
Test name
Test status
Simulation time 135718065 ps
CPU time 0.76 seconds
Started Jun 30 06:24:02 PM PDT 24
Finished Jun 30 06:24:03 PM PDT 24
Peak memory 206136 kb
Host smart-9acc2612-8d5d-427f-8801-4b2299c8bd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17770
39103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1777039103
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.193391703
Short name T2390
Test name
Test status
Simulation time 202691103 ps
CPU time 0.89 seconds
Started Jun 30 06:24:05 PM PDT 24
Finished Jun 30 06:24:06 PM PDT 24
Peak memory 206208 kb
Host smart-dc869725-1e63-4bfa-9f23-72bb13690c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19339
1703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.193391703
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.4220841291
Short name T1916
Test name
Test status
Simulation time 6171292523 ps
CPU time 166.85 seconds
Started Jun 30 06:24:04 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206464 kb
Host smart-0dba5fb8-ac9b-489d-89a2-8b3c562fab31
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4220841291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.4220841291
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3710288093
Short name T754
Test name
Test status
Simulation time 240911257 ps
CPU time 0.94 seconds
Started Jun 30 06:24:07 PM PDT 24
Finished Jun 30 06:24:08 PM PDT 24
Peak memory 206340 kb
Host smart-e5813f63-17d3-4273-8908-ac0016b7aa2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37102
88093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3710288093
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.1768044000
Short name T1841
Test name
Test status
Simulation time 23269634185 ps
CPU time 27.72 seconds
Started Jun 30 06:24:06 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206320 kb
Host smart-e65b8a6b-da79-4ad8-93c7-14a4cf625d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17680
44000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.1768044000
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2465109790
Short name T640
Test name
Test status
Simulation time 3314380916 ps
CPU time 3.9 seconds
Started Jun 30 06:24:05 PM PDT 24
Finished Jun 30 06:24:10 PM PDT 24
Peak memory 206228 kb
Host smart-6575f58c-7315-4ff6-ad89-c905b531defd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24651
09790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2465109790
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2099306730
Short name T1128
Test name
Test status
Simulation time 8801922838 ps
CPU time 60.07 seconds
Started Jun 30 06:24:06 PM PDT 24
Finished Jun 30 06:25:07 PM PDT 24
Peak memory 206264 kb
Host smart-4534c87e-fce6-43ea-a8f3-2930f2bbcfa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20993
06730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2099306730
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.69928407
Short name T335
Test name
Test status
Simulation time 7119484379 ps
CPU time 199.51 seconds
Started Jun 30 06:24:04 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 206424 kb
Host smart-1318626b-ca9e-4d6c-a24a-c23eae2836a9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=69928407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.69928407
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1925536219
Short name T2249
Test name
Test status
Simulation time 236518959 ps
CPU time 0.89 seconds
Started Jun 30 06:24:04 PM PDT 24
Finished Jun 30 06:24:06 PM PDT 24
Peak memory 206216 kb
Host smart-8b74e2e5-b227-4551-b878-2a88bc8780f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1925536219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1925536219
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.249960746
Short name T2615
Test name
Test status
Simulation time 286476814 ps
CPU time 1.03 seconds
Started Jun 30 06:24:08 PM PDT 24
Finished Jun 30 06:24:09 PM PDT 24
Peak memory 206380 kb
Host smart-e144eafb-9528-4b31-941e-0c2a5e2933f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24996
0746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.249960746
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.1479375537
Short name T2226
Test name
Test status
Simulation time 4570277578 ps
CPU time 33.74 seconds
Started Jun 30 06:24:06 PM PDT 24
Finished Jun 30 06:24:40 PM PDT 24
Peak memory 206472 kb
Host smart-3e703584-16e8-4a97-bec3-9b115c4e6896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14793
75537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.1479375537
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1827759789
Short name T1809
Test name
Test status
Simulation time 3439376848 ps
CPU time 32.96 seconds
Started Jun 30 06:24:02 PM PDT 24
Finished Jun 30 06:24:36 PM PDT 24
Peak memory 206408 kb
Host smart-447915da-f237-42c3-923a-0d358600ed9e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1827759789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1827759789
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.4021933358
Short name T1857
Test name
Test status
Simulation time 155524318 ps
CPU time 0.76 seconds
Started Jun 30 06:24:08 PM PDT 24
Finished Jun 30 06:24:09 PM PDT 24
Peak memory 206200 kb
Host smart-4b30146c-3fd2-48ed-8391-6c1a2eeb57ba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4021933358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.4021933358
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2583048468
Short name T2336
Test name
Test status
Simulation time 150940264 ps
CPU time 0.78 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:29 PM PDT 24
Peak memory 206176 kb
Host smart-084fea9c-e5af-4681-b5d7-513424c2370f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25830
48468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2583048468
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2388146066
Short name T1
Test name
Test status
Simulation time 243793866 ps
CPU time 0.87 seconds
Started Jun 30 06:24:35 PM PDT 24
Finished Jun 30 06:24:39 PM PDT 24
Peak memory 206056 kb
Host smart-80b67661-a070-4c27-a44a-287182256108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23881
46066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2388146066
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2320887053
Short name T2488
Test name
Test status
Simulation time 168603252 ps
CPU time 0.8 seconds
Started Jun 30 06:24:23 PM PDT 24
Finished Jun 30 06:24:26 PM PDT 24
Peak memory 206212 kb
Host smart-80494497-cc45-4d14-b7ad-7bbab14f0ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23208
87053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2320887053
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.825843098
Short name T430
Test name
Test status
Simulation time 172947349 ps
CPU time 0.85 seconds
Started Jun 30 06:24:21 PM PDT 24
Finished Jun 30 06:24:23 PM PDT 24
Peak memory 206180 kb
Host smart-4fd63a41-23fa-4b39-99c0-d9c2a4b87b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82584
3098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.825843098
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.396275036
Short name T2350
Test name
Test status
Simulation time 146918851 ps
CPU time 0.76 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:24 PM PDT 24
Peak memory 206232 kb
Host smart-03a2e897-d410-4549-aa08-521ff9a0aa7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39627
5036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.396275036
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.4230644100
Short name T1106
Test name
Test status
Simulation time 166514744 ps
CPU time 0.8 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206196 kb
Host smart-821b9204-deb2-43e6-a753-e6bf0bf5515e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306
44100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.4230644100
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2730450963
Short name T464
Test name
Test status
Simulation time 228193208 ps
CPU time 0.95 seconds
Started Jun 30 06:24:21 PM PDT 24
Finished Jun 30 06:24:24 PM PDT 24
Peak memory 206208 kb
Host smart-a8c4f036-671c-4c71-972c-e523e2cc5e9d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2730450963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2730450963
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.4174510070
Short name T1716
Test name
Test status
Simulation time 137978637 ps
CPU time 0.75 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:24 PM PDT 24
Peak memory 206200 kb
Host smart-07a65273-d705-40b0-9750-4185538069ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41745
10070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.4174510070
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.644222731
Short name T1586
Test name
Test status
Simulation time 36274869 ps
CPU time 0.65 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:25 PM PDT 24
Peak memory 206188 kb
Host smart-2994c8fc-5ae5-4109-b0e6-96d59fc072df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64422
2731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.644222731
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1649317907
Short name T2201
Test name
Test status
Simulation time 21877633946 ps
CPU time 47.29 seconds
Started Jun 30 06:24:23 PM PDT 24
Finished Jun 30 06:25:11 PM PDT 24
Peak memory 206416 kb
Host smart-3e0eb93b-2223-4df5-be7f-880a92a48a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16493
17907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1649317907
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.4248705507
Short name T755
Test name
Test status
Simulation time 221657871 ps
CPU time 0.9 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:27 PM PDT 24
Peak memory 206192 kb
Host smart-f27c65cf-bea7-4d8a-9909-d489bf7d5b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
05507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.4248705507
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2485068171
Short name T1363
Test name
Test status
Simulation time 224861106 ps
CPU time 0.92 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206216 kb
Host smart-8215c14f-c8f6-4c05-a7c6-8b75baac47cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24850
68171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2485068171
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.76822894
Short name T1517
Test name
Test status
Simulation time 177288386 ps
CPU time 0.85 seconds
Started Jun 30 06:24:11 PM PDT 24
Finished Jun 30 06:24:13 PM PDT 24
Peak memory 206188 kb
Host smart-d99e5e62-0016-40e4-830c-61597feac397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76822
894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.76822894
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.2356202308
Short name T2080
Test name
Test status
Simulation time 171505001 ps
CPU time 0.81 seconds
Started Jun 30 06:24:23 PM PDT 24
Finished Jun 30 06:24:26 PM PDT 24
Peak memory 206204 kb
Host smart-36931f10-e77d-4ba1-9011-0ed29a645b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23562
02308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.2356202308
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1277653270
Short name T2188
Test name
Test status
Simulation time 150279872 ps
CPU time 0.75 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:27 PM PDT 24
Peak memory 206184 kb
Host smart-4d098324-bdaf-4ffa-bcf3-02b77a3bec6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12776
53270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1277653270
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.2620191548
Short name T643
Test name
Test status
Simulation time 142484257 ps
CPU time 0.8 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:27 PM PDT 24
Peak memory 206192 kb
Host smart-6107240c-bccf-461c-9c04-604f6571e6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26201
91548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.2620191548
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.213672190
Short name T2632
Test name
Test status
Simulation time 147082065 ps
CPU time 0.77 seconds
Started Jun 30 06:24:11 PM PDT 24
Finished Jun 30 06:24:12 PM PDT 24
Peak memory 206164 kb
Host smart-b6817f74-8a84-404c-9435-458e0aa65e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21367
2190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.213672190
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3631779582
Short name T1896
Test name
Test status
Simulation time 226955327 ps
CPU time 0.95 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:29 PM PDT 24
Peak memory 206208 kb
Host smart-ea608021-814a-4b9f-94ed-3fdda0e61695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36317
79582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3631779582
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.1857936618
Short name T2265
Test name
Test status
Simulation time 5006749989 ps
CPU time 33.63 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:56 PM PDT 24
Peak memory 206432 kb
Host smart-843b8c27-bd0f-4e78-87d9-4bc24858bbfe
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1857936618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.1857936618
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.4204264331
Short name T509
Test name
Test status
Simulation time 185638859 ps
CPU time 0.81 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:29 PM PDT 24
Peak memory 206196 kb
Host smart-c635912f-be4a-405d-8cfb-cd8a490fe544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42042
64331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.4204264331
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1480336931
Short name T752
Test name
Test status
Simulation time 221254898 ps
CPU time 0.82 seconds
Started Jun 30 06:24:13 PM PDT 24
Finished Jun 30 06:24:14 PM PDT 24
Peak memory 206188 kb
Host smart-5d13c620-735d-4aec-aeea-f9aa614397c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14803
36931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1480336931
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.4273985624
Short name T1797
Test name
Test status
Simulation time 7870942138 ps
CPU time 68.61 seconds
Started Jun 30 06:24:12 PM PDT 24
Finished Jun 30 06:25:21 PM PDT 24
Peak memory 206408 kb
Host smart-90c5e1b9-7bf5-4fd9-a92d-d68762c536ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42739
85624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.4273985624
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.268220363
Short name T1210
Test name
Test status
Simulation time 30838574 ps
CPU time 0.68 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:24 PM PDT 24
Peak memory 206216 kb
Host smart-30dc714a-64fb-4ec7-aa01-edb97c2751e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=268220363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.268220363
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.442763717
Short name T2491
Test name
Test status
Simulation time 4242808585 ps
CPU time 5.23 seconds
Started Jun 30 06:24:10 PM PDT 24
Finished Jun 30 06:24:16 PM PDT 24
Peak memory 206408 kb
Host smart-1a5d7d0a-6d8b-4799-8b17-164185cfc34c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=442763717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.442763717
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.985878868
Short name T855
Test name
Test status
Simulation time 13442896333 ps
CPU time 12.53 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:40 PM PDT 24
Peak memory 206416 kb
Host smart-f38e143a-ec24-4eb7-a0dc-816bdba73a49
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=985878868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.985878868
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.696345878
Short name T2531
Test name
Test status
Simulation time 23325976226 ps
CPU time 25.46 seconds
Started Jun 30 06:24:11 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206324 kb
Host smart-22ed12d0-97fa-4522-869f-5ddbf120b826
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=696345878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.696345878
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3996944794
Short name T738
Test name
Test status
Simulation time 186076630 ps
CPU time 0.9 seconds
Started Jun 30 06:24:32 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206056 kb
Host smart-c1b80411-3644-43ae-b7ff-4696c34087e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39969
44794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3996944794
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3114870524
Short name T1030
Test name
Test status
Simulation time 167126404 ps
CPU time 0.84 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206108 kb
Host smart-85ace891-d377-4877-bd69-b9fb12c388a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31148
70524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3114870524
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.4239488589
Short name T107
Test name
Test status
Simulation time 467392081 ps
CPU time 1.54 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:31 PM PDT 24
Peak memory 206288 kb
Host smart-91a80be5-3e60-4dbd-8be5-a0b39e8e188c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42394
88589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.4239488589
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1604998203
Short name T2093
Test name
Test status
Simulation time 498444062 ps
CPU time 1.35 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206192 kb
Host smart-edf9d9f1-e4c8-4108-9796-f76f27b98fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16049
98203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1604998203
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.1717825247
Short name T164
Test name
Test status
Simulation time 22611304580 ps
CPU time 41.52 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:25:08 PM PDT 24
Peak memory 206412 kb
Host smart-1dd552ee-f4b3-4b84-8f2e-7d779b16ac99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17178
25247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1717825247
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1826899445
Short name T2503
Test name
Test status
Simulation time 408719045 ps
CPU time 1.26 seconds
Started Jun 30 06:24:30 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206196 kb
Host smart-b59169f2-eb93-4ae4-839f-746e21645a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18268
99445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1826899445
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1126354816
Short name T1151
Test name
Test status
Simulation time 173858821 ps
CPU time 0.8 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206176 kb
Host smart-6cfeb86f-abae-4742-8c69-63e0dff27421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11263
54816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1126354816
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1976823627
Short name T1490
Test name
Test status
Simulation time 55388440 ps
CPU time 0.68 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:30 PM PDT 24
Peak memory 206160 kb
Host smart-07ea7e6f-4b0e-4fc4-887d-4a8e666c5e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19768
23627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1976823627
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1418846446
Short name T2253
Test name
Test status
Simulation time 889771304 ps
CPU time 2 seconds
Started Jun 30 06:24:32 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206372 kb
Host smart-c49ff21e-4e70-447a-8a6a-8acc43b2923a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14188
46446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1418846446
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2137442761
Short name T2212
Test name
Test status
Simulation time 230493231 ps
CPU time 1.42 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206328 kb
Host smart-4abcecc9-22a6-40e0-9253-3d53a9123acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21374
42761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2137442761
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1166309414
Short name T2409
Test name
Test status
Simulation time 240718284 ps
CPU time 0.88 seconds
Started Jun 30 06:24:32 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206184 kb
Host smart-1b4efdf4-b9d2-4a65-a5ba-62e76990b15d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11663
09414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1166309414
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.4220573032
Short name T2462
Test name
Test status
Simulation time 149383526 ps
CPU time 0.79 seconds
Started Jun 30 06:24:31 PM PDT 24
Finished Jun 30 06:24:36 PM PDT 24
Peak memory 206208 kb
Host smart-7c1aefcc-c4e5-417e-aa39-9966e97500eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42205
73032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.4220573032
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2603148378
Short name T1899
Test name
Test status
Simulation time 213931359 ps
CPU time 0.87 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206144 kb
Host smart-9b2f5a84-81f5-4711-ab2e-529847d1ef7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26031
48378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2603148378
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.1539982658
Short name T1220
Test name
Test status
Simulation time 8163889780 ps
CPU time 77.22 seconds
Started Jun 30 06:24:23 PM PDT 24
Finished Jun 30 06:25:42 PM PDT 24
Peak memory 206444 kb
Host smart-dc1015fe-9008-450f-bfb6-6803f92e8227
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1539982658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.1539982658
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2842617883
Short name T1633
Test name
Test status
Simulation time 214223754 ps
CPU time 0.9 seconds
Started Jun 30 06:24:30 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206188 kb
Host smart-86c66305-ef5e-43f9-afd1-bc4fe5400632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28426
17883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2842617883
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.1284458299
Short name T1998
Test name
Test status
Simulation time 23289399091 ps
CPU time 20.7 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:52 PM PDT 24
Peak memory 206284 kb
Host smart-bbacba84-c5b5-4e5f-bc09-feda1906cd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12844
58299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1284458299
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.858883108
Short name T1734
Test name
Test status
Simulation time 3370526930 ps
CPU time 4.06 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206228 kb
Host smart-5a8189d6-47f2-404f-a299-eed12425b843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85888
3108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.858883108
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1111722749
Short name T949
Test name
Test status
Simulation time 9355112673 ps
CPU time 257.48 seconds
Started Jun 30 06:24:31 PM PDT 24
Finished Jun 30 06:28:53 PM PDT 24
Peak memory 206464 kb
Host smart-27ef1a93-cde6-48e1-a588-fbcf1d018ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11117
22749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1111722749
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.15764766
Short name T2292
Test name
Test status
Simulation time 2775715734 ps
CPU time 26.05 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:59 PM PDT 24
Peak memory 206396 kb
Host smart-05dc8580-f72b-4bc4-8627-d65499e05cd4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=15764766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.15764766
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1630800791
Short name T1812
Test name
Test status
Simulation time 250476279 ps
CPU time 0.9 seconds
Started Jun 30 06:24:32 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206212 kb
Host smart-20d6cd95-c906-4a6e-8703-5779314ef4dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1630800791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1630800791
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2652769993
Short name T1597
Test name
Test status
Simulation time 217691253 ps
CPU time 0.86 seconds
Started Jun 30 06:24:33 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206196 kb
Host smart-a2aefb54-5aec-4346-b6ef-c8b124873acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26527
69993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2652769993
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.1174501125
Short name T1488
Test name
Test status
Simulation time 5289450770 ps
CPU time 50.2 seconds
Started Jun 30 06:24:33 PM PDT 24
Finished Jun 30 06:25:26 PM PDT 24
Peak memory 206356 kb
Host smart-429d8792-3898-4d08-b0a5-c5b6f28b325f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11745
01125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.1174501125
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3756720766
Short name T1659
Test name
Test status
Simulation time 3005811598 ps
CPU time 27.31 seconds
Started Jun 30 06:24:33 PM PDT 24
Finished Jun 30 06:25:04 PM PDT 24
Peak memory 206452 kb
Host smart-4de173e0-10b9-467a-95ec-40180a4c04b9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3756720766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3756720766
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2695966756
Short name T1435
Test name
Test status
Simulation time 179725236 ps
CPU time 0.82 seconds
Started Jun 30 06:24:32 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206212 kb
Host smart-7361c65d-5d59-4c3f-ae0d-9481b8a5f414
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2695966756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2695966756
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.4040242457
Short name T396
Test name
Test status
Simulation time 148016652 ps
CPU time 0.77 seconds
Started Jun 30 06:24:30 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206196 kb
Host smart-84893ec8-a1c2-4bc9-89d5-c0765980e4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40402
42457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.4040242457
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2611287605
Short name T138
Test name
Test status
Simulation time 207101875 ps
CPU time 0.9 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:40 PM PDT 24
Peak memory 206188 kb
Host smart-de56cf82-5004-45d8-af1e-c728befb30d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26112
87605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2611287605
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.4248049689
Short name T1182
Test name
Test status
Simulation time 189282476 ps
CPU time 0.85 seconds
Started Jun 30 06:24:23 PM PDT 24
Finished Jun 30 06:24:26 PM PDT 24
Peak memory 206208 kb
Host smart-c1bb8186-b9b9-4735-ba46-274ab3a0ab8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42480
49689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.4248049689
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3453580415
Short name T1617
Test name
Test status
Simulation time 173341106 ps
CPU time 0.8 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:24 PM PDT 24
Peak memory 206400 kb
Host smart-72b08761-6759-498e-8e2d-f5a8e70c6265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34535
80415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3453580415
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.442964779
Short name T2463
Test name
Test status
Simulation time 168626007 ps
CPU time 0.79 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206188 kb
Host smart-2cf69eec-2f39-4052-b74b-6a3627dbd3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44296
4779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.442964779
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2476019549
Short name T783
Test name
Test status
Simulation time 157752438 ps
CPU time 0.8 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206188 kb
Host smart-5abbb073-9606-41a8-9774-3aea4f71b3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24760
19549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2476019549
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1154228768
Short name T1218
Test name
Test status
Simulation time 225442573 ps
CPU time 0.99 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:27 PM PDT 24
Peak memory 206212 kb
Host smart-8f4f96d1-fee1-4d33-a2b7-85b4758ac036
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1154228768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1154228768
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3924202740
Short name T1336
Test name
Test status
Simulation time 150510179 ps
CPU time 0.74 seconds
Started Jun 30 06:24:21 PM PDT 24
Finished Jun 30 06:24:23 PM PDT 24
Peak memory 206196 kb
Host smart-cc71983c-f015-47bd-88e5-49ee8666650d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39242
02740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3924202740
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.81022094
Short name T39
Test name
Test status
Simulation time 112427134 ps
CPU time 0.69 seconds
Started Jun 30 06:24:21 PM PDT 24
Finished Jun 30 06:24:23 PM PDT 24
Peak memory 206180 kb
Host smart-7e5a6488-9655-4451-bcf2-ba443e157c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81022
094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.81022094
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1900258733
Short name T1632
Test name
Test status
Simulation time 22342002786 ps
CPU time 49.19 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:25:18 PM PDT 24
Peak memory 206420 kb
Host smart-2f48a376-9ba7-417b-80dc-18e26b70eb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19002
58733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1900258733
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2894486886
Short name T1036
Test name
Test status
Simulation time 162649531 ps
CPU time 0.86 seconds
Started Jun 30 06:24:23 PM PDT 24
Finished Jun 30 06:24:25 PM PDT 24
Peak memory 206188 kb
Host smart-a099ab60-14d5-4bf6-8b07-51e24e5ce390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28944
86886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2894486886
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3743548597
Short name T1291
Test name
Test status
Simulation time 243051118 ps
CPU time 0.97 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:30 PM PDT 24
Peak memory 206336 kb
Host smart-43e3c96f-2ea9-4283-be4d-e37a5aa02f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37435
48597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3743548597
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1841148291
Short name T2347
Test name
Test status
Simulation time 210079365 ps
CPU time 0.87 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206208 kb
Host smart-cf4c6769-7b77-4630-a3f1-c1d63b411e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18411
48291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1841148291
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.2781101880
Short name T1105
Test name
Test status
Simulation time 150379647 ps
CPU time 0.84 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:25 PM PDT 24
Peak memory 206204 kb
Host smart-d3834eb9-b38f-4ae5-a792-ef9ab2156e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27811
01880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.2781101880
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.879352258
Short name T632
Test name
Test status
Simulation time 215480936 ps
CPU time 0.86 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206176 kb
Host smart-939fba61-aaa6-452e-9606-ae96df6b56f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87935
2258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.879352258
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2259400735
Short name T2134
Test name
Test status
Simulation time 168309216 ps
CPU time 0.79 seconds
Started Jun 30 06:24:23 PM PDT 24
Finished Jun 30 06:24:26 PM PDT 24
Peak memory 206196 kb
Host smart-719f84c1-d086-46f2-b905-986aa57a5f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22594
00735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2259400735
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.484694379
Short name T2288
Test name
Test status
Simulation time 155147047 ps
CPU time 0.78 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:24 PM PDT 24
Peak memory 206168 kb
Host smart-8fb0dd6d-642e-4027-a4bc-b88d699686a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48469
4379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.484694379
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.300051339
Short name T1686
Test name
Test status
Simulation time 256536524 ps
CPU time 1.04 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206200 kb
Host smart-42414b94-e632-4939-976a-a83942177d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30005
1339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.300051339
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1383172743
Short name T420
Test name
Test status
Simulation time 3780065963 ps
CPU time 33.94 seconds
Started Jun 30 06:24:21 PM PDT 24
Finished Jun 30 06:24:56 PM PDT 24
Peak memory 206616 kb
Host smart-7e0016a0-d670-445d-99f9-46e13cc9a473
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1383172743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1383172743
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.412312796
Short name T377
Test name
Test status
Simulation time 190871252 ps
CPU time 0.83 seconds
Started Jun 30 06:24:21 PM PDT 24
Finished Jun 30 06:24:22 PM PDT 24
Peak memory 206188 kb
Host smart-d100ba94-cc7a-4665-85fe-af1bf44e1326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41231
2796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.412312796
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2274652397
Short name T578
Test name
Test status
Simulation time 182848988 ps
CPU time 0.83 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:31 PM PDT 24
Peak memory 206340 kb
Host smart-ec957858-9eb8-4da5-803f-3cba2437393c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22746
52397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2274652397
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3726982773
Short name T707
Test name
Test status
Simulation time 6495550040 ps
CPU time 42.96 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:25:10 PM PDT 24
Peak memory 206412 kb
Host smart-b7c90496-27a5-4daf-9523-753c601bd14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37269
82773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3726982773
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3139211784
Short name T1877
Test name
Test status
Simulation time 38600789 ps
CPU time 0.69 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206208 kb
Host smart-965ef728-7f5b-4490-99f1-f2c64c6a04ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3139211784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3139211784
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.3369471990
Short name T1173
Test name
Test status
Simulation time 4475750218 ps
CPU time 5.07 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206496 kb
Host smart-9bbd4ec0-f706-4d3e-98fb-35cfc983fc01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3369471990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.3369471990
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1207910940
Short name T1629
Test name
Test status
Simulation time 13361250656 ps
CPU time 12.26 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:44 PM PDT 24
Peak memory 206316 kb
Host smart-1da2c941-7c8d-425c-a067-70ba3a1c540e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1207910940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1207910940
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.689025405
Short name T926
Test name
Test status
Simulation time 23304305620 ps
CPU time 28.17 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:59 PM PDT 24
Peak memory 206416 kb
Host smart-88b12a54-5186-468c-894e-38d4f81d47fd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=689025405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.689025405
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.962980832
Short name T348
Test name
Test status
Simulation time 160008029 ps
CPU time 0.81 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206180 kb
Host smart-5d4155ac-5539-47ac-8cbd-7217f979e93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96298
0832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.962980832
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.177880416
Short name T2165
Test name
Test status
Simulation time 182116289 ps
CPU time 0.85 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206192 kb
Host smart-92629b77-bf90-46e4-be6a-0ad43e06cad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17788
0416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.177880416
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.4056636420
Short name T109
Test name
Test status
Simulation time 257549054 ps
CPU time 1.1 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206092 kb
Host smart-d7a85f42-bbec-4db5-939c-9b5a3d2573b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40566
36420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.4056636420
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2775302791
Short name T1052
Test name
Test status
Simulation time 1541851376 ps
CPU time 3.32 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206468 kb
Host smart-451d0ee7-813a-42f7-abce-56198ec648b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27753
02791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2775302791
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.4049544283
Short name T684
Test name
Test status
Simulation time 19916805337 ps
CPU time 38.09 seconds
Started Jun 30 06:24:21 PM PDT 24
Finished Jun 30 06:25:00 PM PDT 24
Peak memory 206420 kb
Host smart-70063833-9f07-4eba-af9d-1bd0cd947b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40495
44283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.4049544283
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.472540144
Short name T1660
Test name
Test status
Simulation time 407015735 ps
CPU time 1.43 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206192 kb
Host smart-182c7492-720b-49fa-890b-8934476869e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47254
0144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.472540144
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2391877846
Short name T691
Test name
Test status
Simulation time 158427293 ps
CPU time 0.81 seconds
Started Jun 30 06:24:23 PM PDT 24
Finished Jun 30 06:24:26 PM PDT 24
Peak memory 206188 kb
Host smart-abcba9c7-6df3-4d5e-9db0-e9e510caa1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23918
77846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2391877846
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.881944452
Short name T378
Test name
Test status
Simulation time 55643040 ps
CPU time 0.64 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:24 PM PDT 24
Peak memory 206156 kb
Host smart-79e60b80-3dd1-4646-9c1f-8fbfb22d4b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88194
4452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.881944452
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.4191858517
Short name T1566
Test name
Test status
Simulation time 951655534 ps
CPU time 2.13 seconds
Started Jun 30 06:24:23 PM PDT 24
Finished Jun 30 06:24:26 PM PDT 24
Peak memory 206288 kb
Host smart-1a3c1468-04f9-4934-867e-bc2b061220a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41918
58517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.4191858517
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1249976342
Short name T1538
Test name
Test status
Simulation time 286783870 ps
CPU time 2.13 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206308 kb
Host smart-6bcc8cf7-dca3-4683-8dd8-a03531d4a8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12499
76342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1249976342
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1589451181
Short name T1094
Test name
Test status
Simulation time 194747672 ps
CPU time 0.85 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:31 PM PDT 24
Peak memory 206188 kb
Host smart-fd5492be-0d3e-4b24-9dc7-7cc650726290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15894
51181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1589451181
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.784542464
Short name T802
Test name
Test status
Simulation time 142097202 ps
CPU time 0.75 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206200 kb
Host smart-463c6b5a-e577-4d1f-83ac-644274ad473b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78454
2464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.784542464
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3044705717
Short name T1698
Test name
Test status
Simulation time 194946964 ps
CPU time 0.86 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206188 kb
Host smart-196fc537-9e06-461d-86a4-ffb83d74faf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30447
05717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3044705717
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.902204990
Short name T908
Test name
Test status
Simulation time 4740789452 ps
CPU time 32.22 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:58 PM PDT 24
Peak memory 206384 kb
Host smart-ced66f71-bdab-4086-892c-16f43a22eb3f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=902204990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.902204990
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.818803377
Short name T2622
Test name
Test status
Simulation time 215312608 ps
CPU time 0.85 seconds
Started Jun 30 06:24:22 PM PDT 24
Finished Jun 30 06:24:23 PM PDT 24
Peak memory 206148 kb
Host smart-aa088ff5-2d98-4734-9028-69ea77a3917f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81880
3377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.818803377
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1698140416
Short name T615
Test name
Test status
Simulation time 23351501914 ps
CPU time 23.28 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 206316 kb
Host smart-0ad75b85-2a20-45eb-a36a-08d390366192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16981
40416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1698140416
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3655812509
Short name T2343
Test name
Test status
Simulation time 3299221079 ps
CPU time 3.63 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206236 kb
Host smart-b2f5d902-be81-481d-8f79-c47c3f500dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36558
12509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3655812509
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.701529203
Short name T760
Test name
Test status
Simulation time 12174438718 ps
CPU time 339.61 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:30:06 PM PDT 24
Peak memory 206408 kb
Host smart-77413d06-d10a-4366-911b-bb0ba6bfef56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70152
9203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.701529203
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2341013377
Short name T2310
Test name
Test status
Simulation time 5723539003 ps
CPU time 53.06 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:25:20 PM PDT 24
Peak memory 206460 kb
Host smart-f137c1f5-de1e-4a8e-902a-f7e0a9aa4b1b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2341013377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2341013377
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3344918156
Short name T2325
Test name
Test status
Simulation time 244179456 ps
CPU time 0.95 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:29 PM PDT 24
Peak memory 206112 kb
Host smart-db95c301-d231-40c8-96f5-5c8d0cfb7070
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3344918156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3344918156
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.608233197
Short name T2261
Test name
Test status
Simulation time 210555605 ps
CPU time 0.87 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206208 kb
Host smart-4aaf2f21-bcd9-44c1-a909-b1224d7df673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60823
3197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.608233197
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2354729947
Short name T2479
Test name
Test status
Simulation time 6354297769 ps
CPU time 61.31 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206400 kb
Host smart-20bcc522-f406-4686-8c55-0a7d294697c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23547
29947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2354729947
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.135555779
Short name T787
Test name
Test status
Simulation time 5401226863 ps
CPU time 38.4 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:25:09 PM PDT 24
Peak memory 206436 kb
Host smart-00da514c-444b-475b-aeed-e354f43ff19a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=135555779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.135555779
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.167063367
Short name T504
Test name
Test status
Simulation time 158106090 ps
CPU time 0.79 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206208 kb
Host smart-7548862e-94e9-485d-a5f5-65f206a80254
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=167063367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.167063367
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2776904701
Short name T486
Test name
Test status
Simulation time 198504288 ps
CPU time 0.84 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206200 kb
Host smart-67c86f61-5edf-448e-ae7f-757c7f7d0d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27769
04701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2776904701
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3806919823
Short name T132
Test name
Test status
Simulation time 210208016 ps
CPU time 0.92 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206192 kb
Host smart-6a2161bc-4f41-41d2-ae46-0ae3b316d2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38069
19823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3806919823
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.361329599
Short name T97
Test name
Test status
Simulation time 153737493 ps
CPU time 0.85 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206180 kb
Host smart-5e1addcf-3160-42a5-95c8-02fd8935bef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36132
9599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.361329599
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.521047078
Short name T1364
Test name
Test status
Simulation time 190002274 ps
CPU time 0.85 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:31 PM PDT 24
Peak memory 206180 kb
Host smart-4ac2ae4a-c492-4df8-be65-775cc59d8e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52104
7078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.521047078
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2474244251
Short name T1449
Test name
Test status
Simulation time 151061348 ps
CPU time 0.8 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206208 kb
Host smart-52b500cc-cdc3-4e54-b349-e25c113f1d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24742
44251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2474244251
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.4168932184
Short name T2162
Test name
Test status
Simulation time 160156781 ps
CPU time 0.84 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206156 kb
Host smart-b86d7fc1-e0d5-4902-a2e1-c1508ef518d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41689
32184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.4168932184
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1540307868
Short name T1247
Test name
Test status
Simulation time 202110216 ps
CPU time 0.88 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206212 kb
Host smart-2d0f3366-d3c5-448b-8688-f59582c51bd6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1540307868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1540307868
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.744132596
Short name T1760
Test name
Test status
Simulation time 204697242 ps
CPU time 0.77 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 206192 kb
Host smart-f1a242db-9e31-44d3-92ef-fb49f59d5538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74413
2596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.744132596
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3546590673
Short name T1085
Test name
Test status
Simulation time 44474658 ps
CPU time 0.68 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206204 kb
Host smart-73d2d24a-c368-4076-9e3a-5da023acd33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35465
90673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3546590673
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.372128232
Short name T1618
Test name
Test status
Simulation time 12423504007 ps
CPU time 27.79 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:25:02 PM PDT 24
Peak memory 206428 kb
Host smart-c25f204b-9be9-4fbb-af8c-420f391bfd09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37212
8232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.372128232
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2998557297
Short name T2364
Test name
Test status
Simulation time 192261022 ps
CPU time 0.86 seconds
Started Jun 30 06:24:30 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206188 kb
Host smart-5b004459-767c-4eaf-9829-51383268a07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29985
57297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2998557297
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1729704364
Short name T2174
Test name
Test status
Simulation time 223829409 ps
CPU time 0.91 seconds
Started Jun 30 06:24:30 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206204 kb
Host smart-af2fc279-73e8-4e02-bf7a-11a6b3b4e5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17297
04364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1729704364
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2782418199
Short name T974
Test name
Test status
Simulation time 186657154 ps
CPU time 0.88 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206208 kb
Host smart-9572ac29-967d-47f6-93a1-d0ab462066c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27824
18199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2782418199
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.548365580
Short name T673
Test name
Test status
Simulation time 173432540 ps
CPU time 0.85 seconds
Started Jun 30 06:24:25 PM PDT 24
Finished Jun 30 06:24:29 PM PDT 24
Peak memory 206140 kb
Host smart-0282e70f-7520-41ef-a8d9-c15dbaef0d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54836
5580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.548365580
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2555336550
Short name T1872
Test name
Test status
Simulation time 189895659 ps
CPU time 0.83 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206184 kb
Host smart-eb180942-53ae-457c-a202-433e6ba1bcbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25553
36550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2555336550
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.829049056
Short name T1301
Test name
Test status
Simulation time 144896826 ps
CPU time 0.76 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206172 kb
Host smart-b935c31c-cd36-46bd-8fdb-542db3f08eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82904
9056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.829049056
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1978846739
Short name T830
Test name
Test status
Simulation time 147926123 ps
CPU time 0.77 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206184 kb
Host smart-2e172536-a21d-4fe0-b67d-e96c6465f19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19788
46739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1978846739
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1171193577
Short name T1508
Test name
Test status
Simulation time 245785237 ps
CPU time 0.95 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206204 kb
Host smart-877fcf67-9440-4181-9e97-f2a2a4888068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11711
93577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1171193577
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.4107062880
Short name T1643
Test name
Test status
Simulation time 3881113935 ps
CPU time 36.99 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:25:09 PM PDT 24
Peak memory 206368 kb
Host smart-a46660cb-a72f-4eed-b3c5-06171d0c60c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4107062880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.4107062880
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2210910854
Short name T965
Test name
Test status
Simulation time 154228798 ps
CPU time 0.81 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206184 kb
Host smart-682b0d28-8a4d-401e-a2e0-0ba34e38490c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22109
10854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2210910854
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3367336002
Short name T1579
Test name
Test status
Simulation time 162638753 ps
CPU time 0.77 seconds
Started Jun 30 06:24:24 PM PDT 24
Finished Jun 30 06:24:27 PM PDT 24
Peak memory 206124 kb
Host smart-1459a52b-afed-4d09-a329-0f4792b02575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33673
36002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3367336002
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3965162461
Short name T1561
Test name
Test status
Simulation time 6537240738 ps
CPU time 179.32 seconds
Started Jun 30 06:24:23 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 206456 kb
Host smart-d267f285-0bbc-41b6-8729-17f1afa50014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39651
62461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3965162461
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.1305664963
Short name T208
Test name
Test status
Simulation time 44938854 ps
CPU time 0.66 seconds
Started Jun 30 06:20:44 PM PDT 24
Finished Jun 30 06:20:45 PM PDT 24
Peak memory 206204 kb
Host smart-a564da3e-a782-4117-a763-8a204815b5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1305664963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.1305664963
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1930283768
Short name T2102
Test name
Test status
Simulation time 4315146567 ps
CPU time 5.5 seconds
Started Jun 30 06:20:44 PM PDT 24
Finished Jun 30 06:20:50 PM PDT 24
Peak memory 206292 kb
Host smart-7fd9a7b0-7e02-447a-9d45-d878deac4c00
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1930283768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.1930283768
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.936406025
Short name T736
Test name
Test status
Simulation time 13417332678 ps
CPU time 14.57 seconds
Started Jun 30 06:20:35 PM PDT 24
Finished Jun 30 06:20:51 PM PDT 24
Peak memory 206348 kb
Host smart-1c47d116-0f22-4cbf-a56f-ba67f17cd509
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=936406025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.936406025
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.4018799058
Short name T1437
Test name
Test status
Simulation time 23536396485 ps
CPU time 23.03 seconds
Started Jun 30 06:20:35 PM PDT 24
Finished Jun 30 06:20:59 PM PDT 24
Peak memory 206440 kb
Host smart-ceecfe8d-c8c9-4869-a6de-c143d3155d35
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4018799058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.4018799058
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1422348789
Short name T2344
Test name
Test status
Simulation time 178897525 ps
CPU time 0.86 seconds
Started Jun 30 06:20:40 PM PDT 24
Finished Jun 30 06:20:42 PM PDT 24
Peak memory 206008 kb
Host smart-ab03dca1-71e6-466a-bd13-52f9933e3e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14223
48789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1422348789
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.4175341731
Short name T2021
Test name
Test status
Simulation time 194616095 ps
CPU time 0.84 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:36 PM PDT 24
Peak memory 206188 kb
Host smart-41e98c03-3e68-486c-8e05-b559eedc7f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41753
41731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.4175341731
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.611067738
Short name T85
Test name
Test status
Simulation time 138843227 ps
CPU time 0.81 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:36 PM PDT 24
Peak memory 206164 kb
Host smart-5c97c0de-a2d0-410b-a0b3-530f1f56ad7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61106
7738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.611067738
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2696030206
Short name T2269
Test name
Test status
Simulation time 150764875 ps
CPU time 0.75 seconds
Started Jun 30 06:20:40 PM PDT 24
Finished Jun 30 06:20:41 PM PDT 24
Peak memory 206188 kb
Host smart-9736f62f-a535-4485-811a-f81c0ab9fcfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26960
30206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2696030206
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3440375858
Short name T893
Test name
Test status
Simulation time 529762225 ps
CPU time 1.51 seconds
Started Jun 30 06:20:40 PM PDT 24
Finished Jun 30 06:20:43 PM PDT 24
Peak memory 206248 kb
Host smart-cce3f634-0290-44e6-9c74-c9f716fb1fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34403
75858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3440375858
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.724774493
Short name T1474
Test name
Test status
Simulation time 1479157809 ps
CPU time 3.43 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206232 kb
Host smart-063b4b2b-8b97-4e83-80aa-360b92d1d61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72477
4493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.724774493
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.375006849
Short name T2433
Test name
Test status
Simulation time 21490479268 ps
CPU time 38.46 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 206396 kb
Host smart-034c5ed9-af6b-4e1e-b12e-b2b3b8ee1872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37500
6849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.375006849
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.733257705
Short name T2327
Test name
Test status
Simulation time 407597818 ps
CPU time 1.25 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:36 PM PDT 24
Peak memory 206232 kb
Host smart-c17ac2f7-e5ae-42d5-b20b-cd21a744d864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73325
7705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.733257705
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.4188728962
Short name T1605
Test name
Test status
Simulation time 166809564 ps
CPU time 0.78 seconds
Started Jun 30 06:20:38 PM PDT 24
Finished Jun 30 06:20:39 PM PDT 24
Peak memory 206188 kb
Host smart-b852d548-2f91-44e4-9876-49b265d745ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41887
28962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.4188728962
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1951362350
Short name T1344
Test name
Test status
Simulation time 55958397 ps
CPU time 0.68 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206196 kb
Host smart-297988dc-5a66-47e2-adf6-684edf67cc6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19513
62350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1951362350
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3961831130
Short name T2122
Test name
Test status
Simulation time 911779784 ps
CPU time 2.2 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:20:39 PM PDT 24
Peak memory 206352 kb
Host smart-12216f8e-fc03-4ecf-9d7b-fb055ad92bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39618
31130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3961831130
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3840721933
Short name T2625
Test name
Test status
Simulation time 226130853 ps
CPU time 1.3 seconds
Started Jun 30 06:20:39 PM PDT 24
Finished Jun 30 06:20:41 PM PDT 24
Peak memory 206268 kb
Host smart-a65b4b02-5659-4468-918f-43236cba0a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38407
21933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3840721933
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1735114975
Short name T112
Test name
Test status
Simulation time 215018595 ps
CPU time 0.88 seconds
Started Jun 30 06:20:38 PM PDT 24
Finished Jun 30 06:20:39 PM PDT 24
Peak memory 206172 kb
Host smart-ba10a083-6510-498d-8473-197e2bacd7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17351
14975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1735114975
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1981560023
Short name T394
Test name
Test status
Simulation time 165668189 ps
CPU time 0.76 seconds
Started Jun 30 06:20:38 PM PDT 24
Finished Jun 30 06:20:40 PM PDT 24
Peak memory 206192 kb
Host smart-c2579c30-26ef-4e59-910f-9d38f7e9d4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815
60023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1981560023
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2093813239
Short name T2393
Test name
Test status
Simulation time 179861025 ps
CPU time 0.81 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:36 PM PDT 24
Peak memory 206196 kb
Host smart-adc1f7b0-75ba-412d-aa13-88584a5d29f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20938
13239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2093813239
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.3008178869
Short name T1910
Test name
Test status
Simulation time 8706780182 ps
CPU time 61.61 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:21:39 PM PDT 24
Peak memory 206408 kb
Host smart-37a6ad31-f884-4103-8ced-c683196564ea
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3008178869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3008178869
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1547261021
Short name T2444
Test name
Test status
Simulation time 155768578 ps
CPU time 0.81 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:36 PM PDT 24
Peak memory 206200 kb
Host smart-f07e198d-c9de-44dd-8f70-c77da6f11944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15472
61021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1547261021
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1659455217
Short name T713
Test name
Test status
Simulation time 23331817317 ps
CPU time 22.6 seconds
Started Jun 30 06:20:35 PM PDT 24
Finished Jun 30 06:20:59 PM PDT 24
Peak memory 206312 kb
Host smart-ca129226-fe6b-441e-9226-34fc2594831f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16594
55217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1659455217
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1834296547
Short name T1958
Test name
Test status
Simulation time 3356061222 ps
CPU time 4.62 seconds
Started Jun 30 06:20:38 PM PDT 24
Finished Jun 30 06:20:43 PM PDT 24
Peak memory 206236 kb
Host smart-3f819248-60ab-4879-ba51-a1cdad99c9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18342
96547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1834296547
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.4119067344
Short name T2218
Test name
Test status
Simulation time 7181084143 ps
CPU time 197.08 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:24:00 PM PDT 24
Peak memory 206476 kb
Host smart-60ba1324-de43-4f3d-a961-12e66d1212b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41190
67344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.4119067344
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1093790366
Short name T2242
Test name
Test status
Simulation time 4084998347 ps
CPU time 28.53 seconds
Started Jun 30 06:20:35 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206460 kb
Host smart-c42f315e-29a3-4328-beb0-abe37a31ec58
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1093790366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1093790366
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3146845307
Short name T2215
Test name
Test status
Simulation time 243458989 ps
CPU time 0.89 seconds
Started Jun 30 06:20:43 PM PDT 24
Finished Jun 30 06:20:45 PM PDT 24
Peak memory 206224 kb
Host smart-e3ed54a0-b9f5-4a87-a3d4-c4d6a45f9525
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3146845307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3146845307
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2337762464
Short name T1929
Test name
Test status
Simulation time 202225720 ps
CPU time 0.84 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206212 kb
Host smart-6a7af39e-3018-4278-997b-2844d65b1088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23377
62464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2337762464
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.327198041
Short name T2572
Test name
Test status
Simulation time 3763703522 ps
CPU time 28.16 seconds
Started Jun 30 06:20:35 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206408 kb
Host smart-3ec2b86a-5365-4693-b58d-4b5b12d81120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32719
8041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.327198041
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.628075234
Short name T2180
Test name
Test status
Simulation time 7603295412 ps
CPU time 66.79 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:21:44 PM PDT 24
Peak memory 206408 kb
Host smart-fbc50423-66ae-481b-8427-33c210c1ba21
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=628075234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.628075234
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3452514090
Short name T2422
Test name
Test status
Simulation time 152411008 ps
CPU time 0.79 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:36 PM PDT 24
Peak memory 206200 kb
Host smart-60e65df6-4e31-4b3d-9a53-36b8da2a9b87
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3452514090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3452514090
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2641424702
Short name T776
Test name
Test status
Simulation time 164480614 ps
CPU time 0.81 seconds
Started Jun 30 06:20:34 PM PDT 24
Finished Jun 30 06:20:36 PM PDT 24
Peak memory 206168 kb
Host smart-88b71928-afc8-418b-9129-2a0194fd11f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26414
24702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2641424702
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1702365241
Short name T140
Test name
Test status
Simulation time 193497953 ps
CPU time 0.89 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206168 kb
Host smart-b528f84c-e273-4bde-a528-85a405f974f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17023
65241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1702365241
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.74328441
Short name T1662
Test name
Test status
Simulation time 157374071 ps
CPU time 0.79 seconds
Started Jun 30 06:20:40 PM PDT 24
Finished Jun 30 06:20:42 PM PDT 24
Peak memory 206012 kb
Host smart-3cb9f8ba-c9d0-40e8-a597-107962d44e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74328
441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.74328441
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.169418830
Short name T601
Test name
Test status
Simulation time 185901206 ps
CPU time 0.81 seconds
Started Jun 30 06:20:41 PM PDT 24
Finished Jun 30 06:20:43 PM PDT 24
Peak memory 206204 kb
Host smart-c0587e80-af17-4e6c-b4e9-2c9f08b34a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16941
8830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.169418830
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2558110940
Short name T373
Test name
Test status
Simulation time 173768131 ps
CPU time 0.77 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:20:43 PM PDT 24
Peak memory 206200 kb
Host smart-f891a21e-f307-4f5f-b13e-b353128f1517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25581
10940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2558110940
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3980162049
Short name T197
Test name
Test status
Simulation time 153571730 ps
CPU time 0.78 seconds
Started Jun 30 06:20:41 PM PDT 24
Finished Jun 30 06:20:43 PM PDT 24
Peak memory 206204 kb
Host smart-5f90ac1b-b31e-4b6c-a1f3-250148c73898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39801
62049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3980162049
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2383440347
Short name T1693
Test name
Test status
Simulation time 189748921 ps
CPU time 0.89 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206200 kb
Host smart-af0cbba8-59b0-454b-897c-4358b1cd0f21
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2383440347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2383440347
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2240920936
Short name T1612
Test name
Test status
Simulation time 211290144 ps
CPU time 0.9 seconds
Started Jun 30 06:20:38 PM PDT 24
Finished Jun 30 06:20:40 PM PDT 24
Peak memory 206196 kb
Host smart-5186de45-ff34-40d8-818f-a6a6816b68a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22409
20936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2240920936
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.4121001006
Short name T1654
Test name
Test status
Simulation time 156685201 ps
CPU time 0.83 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206196 kb
Host smart-6093624b-d73c-4af8-9b50-02973bc2b627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41210
01006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.4121001006
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.392626441
Short name T815
Test name
Test status
Simulation time 34275167 ps
CPU time 0.67 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:20:43 PM PDT 24
Peak memory 206216 kb
Host smart-a119c051-f355-4cd9-8f9c-75d520ccb247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39262
6441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.392626441
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3103313725
Short name T669
Test name
Test status
Simulation time 12354166188 ps
CPU time 27.16 seconds
Started Jun 30 06:20:39 PM PDT 24
Finished Jun 30 06:21:07 PM PDT 24
Peak memory 206428 kb
Host smart-638343df-b53f-4352-a782-0ffd4dcd5a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31033
13725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3103313725
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3718007780
Short name T702
Test name
Test status
Simulation time 178399402 ps
CPU time 0.85 seconds
Started Jun 30 06:20:35 PM PDT 24
Finished Jun 30 06:20:37 PM PDT 24
Peak memory 206192 kb
Host smart-69b01357-a3b3-4bac-bc3a-0288417941b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37180
07780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3718007780
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1434484828
Short name T1772
Test name
Test status
Simulation time 176278940 ps
CPU time 0.82 seconds
Started Jun 30 06:20:35 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206212 kb
Host smart-f60058e2-1da7-4a47-ba20-5a5daf86dc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14344
84828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1434484828
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.584950464
Short name T202
Test name
Test status
Simulation time 14875894914 ps
CPU time 109.99 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:22:28 PM PDT 24
Peak memory 206496 kb
Host smart-036da0d4-a151-4492-bb63-210636b86d0a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=584950464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.584950464
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2654541022
Short name T1737
Test name
Test status
Simulation time 17854846377 ps
CPU time 412.85 seconds
Started Jun 30 06:20:38 PM PDT 24
Finished Jun 30 06:27:31 PM PDT 24
Peak memory 206500 kb
Host smart-8e39de42-c378-471c-8751-3c4a517e2ded
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2654541022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2654541022
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.515072653
Short name T1999
Test name
Test status
Simulation time 198925303 ps
CPU time 0.8 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:20:44 PM PDT 24
Peak memory 206216 kb
Host smart-91dd6df6-38dd-4413-b668-33f3dccd16f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51507
2653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.515072653
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1028392165
Short name T1146
Test name
Test status
Simulation time 188035425 ps
CPU time 0.9 seconds
Started Jun 30 06:20:45 PM PDT 24
Finished Jun 30 06:20:46 PM PDT 24
Peak memory 206148 kb
Host smart-9bf24780-cab2-4a21-a475-406e377bc31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10283
92165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1028392165
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.4244170849
Short name T903
Test name
Test status
Simulation time 150377146 ps
CPU time 0.78 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:20:44 PM PDT 24
Peak memory 206204 kb
Host smart-56f64a14-0ae3-4623-af14-9220e33d96e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42441
70849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.4244170849
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.563222312
Short name T72
Test name
Test status
Simulation time 179547639 ps
CPU time 0.83 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206068 kb
Host smart-33b526b6-dc4a-45ca-8043-fed36916651a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56322
2312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.563222312
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3451750415
Short name T216
Test name
Test status
Simulation time 258901066 ps
CPU time 1.11 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:20:44 PM PDT 24
Peak memory 223992 kb
Host smart-524c4e70-f69a-4709-a875-6243bbc474cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3451750415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3451750415
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.2805390286
Short name T2353
Test name
Test status
Simulation time 375371300 ps
CPU time 1.23 seconds
Started Jun 30 06:20:37 PM PDT 24
Finished Jun 30 06:20:39 PM PDT 24
Peak memory 206208 kb
Host smart-98e4b923-87fb-4b6b-8dd4-37052f5c7009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053
90286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.2805390286
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.1195870161
Short name T2314
Test name
Test status
Simulation time 205059869 ps
CPU time 0.93 seconds
Started Jun 30 06:20:37 PM PDT 24
Finished Jun 30 06:20:39 PM PDT 24
Peak memory 206168 kb
Host smart-434e09eb-5401-4ef4-9c8b-43e2db41ce63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11958
70161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.1195870161
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1158397512
Short name T1838
Test name
Test status
Simulation time 144815124 ps
CPU time 0.76 seconds
Started Jun 30 06:20:37 PM PDT 24
Finished Jun 30 06:20:39 PM PDT 24
Peak memory 206188 kb
Host smart-e11ab380-a634-4b80-8e2c-0f07823bd0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11583
97512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1158397512
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.546016019
Short name T436
Test name
Test status
Simulation time 175903603 ps
CPU time 0.89 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:20:38 PM PDT 24
Peak memory 206048 kb
Host smart-8e6dad9d-3955-4daa-b4f4-7e7c5efc3480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54601
6019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.546016019
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2330990690
Short name T1359
Test name
Test status
Simulation time 238335703 ps
CPU time 0.95 seconds
Started Jun 30 06:20:39 PM PDT 24
Finished Jun 30 06:20:40 PM PDT 24
Peak memory 206208 kb
Host smart-08d51465-7024-48d0-bec3-0299b71796fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23309
90690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2330990690
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.1831994840
Short name T2507
Test name
Test status
Simulation time 4079156709 ps
CPU time 118.74 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:22:36 PM PDT 24
Peak memory 206468 kb
Host smart-67cbb9b5-f19e-40f9-abcd-5c86a0a4de66
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1831994840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.1831994840
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1785495788
Short name T1117
Test name
Test status
Simulation time 189422409 ps
CPU time 0.93 seconds
Started Jun 30 06:20:37 PM PDT 24
Finished Jun 30 06:20:40 PM PDT 24
Peak memory 206208 kb
Host smart-2dcd9dc4-c088-4533-ac66-7f93030c0ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17854
95788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1785495788
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.106998071
Short name T1469
Test name
Test status
Simulation time 164162013 ps
CPU time 0.82 seconds
Started Jun 30 06:20:45 PM PDT 24
Finished Jun 30 06:20:46 PM PDT 24
Peak memory 206148 kb
Host smart-06441d29-9df8-4318-9a99-03485ae8e1d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10699
8071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.106998071
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.3916630462
Short name T653
Test name
Test status
Simulation time 3407544804 ps
CPU time 24.69 seconds
Started Jun 30 06:20:38 PM PDT 24
Finished Jun 30 06:21:03 PM PDT 24
Peak memory 206424 kb
Host smart-ffb3f9bb-a2d8-443f-b3b1-17d43a14e56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39166
30462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.3916630462
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.834883033
Short name T1520
Test name
Test status
Simulation time 14434364369 ps
CPU time 122.42 seconds
Started Jun 30 06:20:36 PM PDT 24
Finished Jun 30 06:22:40 PM PDT 24
Peak memory 206500 kb
Host smart-ebc13387-43a9-43a9-be13-b57807d40c9a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=834883033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.834883033
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2879276365
Short name T2590
Test name
Test status
Simulation time 40253758 ps
CPU time 0.66 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:40 PM PDT 24
Peak memory 206200 kb
Host smart-5289bb85-9777-4fe9-a491-eca8cf4e3b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2879276365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2879276365
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.752955623
Short name T1832
Test name
Test status
Simulation time 4205706456 ps
CPU time 4.59 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206360 kb
Host smart-7e5ddb99-9fcb-4fc6-85ac-14686b8afc19
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=752955623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.752955623
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2985599030
Short name T894
Test name
Test status
Simulation time 13453482268 ps
CPU time 13.75 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:47 PM PDT 24
Peak memory 206472 kb
Host smart-f2818194-4134-4999-8c78-f88b7295618a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2985599030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2985599030
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1465984657
Short name T635
Test name
Test status
Simulation time 23302193378 ps
CPU time 22.41 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:56 PM PDT 24
Peak memory 206308 kb
Host smart-2f929888-1f52-4b2a-9b49-6b397086606b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1465984657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1465984657
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.723013432
Short name T152
Test name
Test status
Simulation time 153909106 ps
CPU time 0.85 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206168 kb
Host smart-121a4321-f701-480f-98dd-164ba585ee0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72301
3432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.723013432
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1649398657
Short name T1855
Test name
Test status
Simulation time 183921365 ps
CPU time 0.77 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206180 kb
Host smart-d50a9a77-a678-494f-9a30-b779197c8c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16493
98657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1649398657
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1147170673
Short name T682
Test name
Test status
Simulation time 178933757 ps
CPU time 0.85 seconds
Started Jun 30 06:24:32 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206188 kb
Host smart-8eab5f8a-105a-4de5-b1de-81fdf8ebd631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11471
70673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1147170673
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_device_address.1877425627
Short name T1087
Test name
Test status
Simulation time 17692717498 ps
CPU time 33.87 seconds
Started Jun 30 06:24:36 PM PDT 24
Finished Jun 30 06:25:12 PM PDT 24
Peak memory 206396 kb
Host smart-ce069b5f-a0a7-4aa3-a96e-3805c7bd8e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18774
25627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.1877425627
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.961177514
Short name T1645
Test name
Test status
Simulation time 424402118 ps
CPU time 1.26 seconds
Started Jun 30 06:24:30 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206192 kb
Host smart-f863949a-a13f-404d-a2ca-f5a60482908f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96117
7514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.961177514
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3400754991
Short name T1361
Test name
Test status
Simulation time 153397991 ps
CPU time 0.79 seconds
Started Jun 30 06:24:34 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206168 kb
Host smart-aedcbb55-6285-4417-8210-b879f17f3332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34007
54991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3400754991
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.3181171607
Short name T257
Test name
Test status
Simulation time 75264135 ps
CPU time 0.69 seconds
Started Jun 30 06:24:35 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206148 kb
Host smart-a53ecd10-9917-4b3e-b1b2-7bd9d0eab4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31811
71607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3181171607
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3562194403
Short name T2176
Test name
Test status
Simulation time 895915259 ps
CPU time 2 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206304 kb
Host smart-a75bb407-1098-4485-849a-90cd17dcc986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35621
94403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3562194403
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3844088725
Short name T2238
Test name
Test status
Simulation time 365003052 ps
CPU time 2.32 seconds
Started Jun 30 06:24:34 PM PDT 24
Finished Jun 30 06:24:39 PM PDT 24
Peak memory 206264 kb
Host smart-54b5f3c6-d4b3-468c-a303-fc3fcdbb9d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38440
88725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3844088725
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.4031564628
Short name T1229
Test name
Test status
Simulation time 236643388 ps
CPU time 0.93 seconds
Started Jun 30 06:24:33 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206140 kb
Host smart-927d4f53-c08d-4a67-9db2-2f1bfe4f62a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40315
64628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.4031564628
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2802951896
Short name T1427
Test name
Test status
Simulation time 138759503 ps
CPU time 0.76 seconds
Started Jun 30 06:24:35 PM PDT 24
Finished Jun 30 06:24:49 PM PDT 24
Peak memory 206176 kb
Host smart-f99d1b9e-cc59-46e0-87d5-1bf62a37a53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28029
51896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2802951896
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1438231533
Short name T2086
Test name
Test status
Simulation time 163252871 ps
CPU time 0.87 seconds
Started Jun 30 06:24:26 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206216 kb
Host smart-d62dcb38-5af2-40a5-ae62-13326911ab03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14382
31533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1438231533
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1301942929
Short name T1908
Test name
Test status
Simulation time 174744042 ps
CPU time 0.81 seconds
Started Jun 30 06:24:39 PM PDT 24
Finished Jun 30 06:24:42 PM PDT 24
Peak memory 206164 kb
Host smart-cc578e7f-8dd6-4f92-8bd8-d2ffe918ace4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13019
42929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1301942929
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.4261321284
Short name T2110
Test name
Test status
Simulation time 23346020262 ps
CPU time 28.89 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:25:08 PM PDT 24
Peak memory 206112 kb
Host smart-fa9f704c-dcc8-4d2b-b1b6-5f1a643ee741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42613
21284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.4261321284
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2822172103
Short name T1770
Test name
Test status
Simulation time 3293467595 ps
CPU time 3.84 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:44 PM PDT 24
Peak memory 206108 kb
Host smart-671fca27-8072-4dcd-a105-a2ad7ac2b04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28221
72103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2822172103
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1869032962
Short name T1125
Test name
Test status
Simulation time 5594032169 ps
CPU time 58.17 seconds
Started Jun 30 06:24:30 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206420 kb
Host smart-c707960b-e70f-4e4e-acfc-9a9d0a91137f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18690
32962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1869032962
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3521735997
Short name T2190
Test name
Test status
Simulation time 4844214186 ps
CPU time 132.91 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:26:52 PM PDT 24
Peak memory 206444 kb
Host smart-4ddceacd-f09b-4a78-8bb7-1e0e5c80813f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3521735997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3521735997
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.740528247
Short name T2550
Test name
Test status
Simulation time 242233406 ps
CPU time 0.9 seconds
Started Jun 30 06:24:36 PM PDT 24
Finished Jun 30 06:24:40 PM PDT 24
Peak memory 206200 kb
Host smart-67b8d1ed-0301-4277-8c23-a15c04aac1b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=740528247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.740528247
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2165493992
Short name T1116
Test name
Test status
Simulation time 200794932 ps
CPU time 0.86 seconds
Started Jun 30 06:24:33 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206152 kb
Host smart-1092c3ab-7987-4334-b1e4-e8fa298b4e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21654
93992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2165493992
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.3081811222
Short name T1443
Test name
Test status
Simulation time 5700776172 ps
CPU time 39.28 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206428 kb
Host smart-50e7837a-a1f7-41eb-97c3-f63ef468bccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30818
11222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.3081811222
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1718464782
Short name T1829
Test name
Test status
Simulation time 6456287896 ps
CPU time 182.81 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:27:36 PM PDT 24
Peak memory 206428 kb
Host smart-0503cf19-3cae-437d-8215-4ea0d1ec7a2e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1718464782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1718464782
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.14507999
Short name T1709
Test name
Test status
Simulation time 167889790 ps
CPU time 0.78 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206192 kb
Host smart-7dd849f9-65c1-4613-95ec-a3aec34870f6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=14507999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.14507999
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.319699748
Short name T2158
Test name
Test status
Simulation time 148237851 ps
CPU time 0.78 seconds
Started Jun 30 06:24:34 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206176 kb
Host smart-e4163784-056f-4ac9-9ac9-3d5ab1dc2f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31969
9748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.319699748
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.427272927
Short name T1555
Test name
Test status
Simulation time 193897500 ps
CPU time 0.84 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206184 kb
Host smart-60b7f9ea-edc8-4436-8b54-46ea1d5d9039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42727
2927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.427272927
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.4240373309
Short name T971
Test name
Test status
Simulation time 167715523 ps
CPU time 0.81 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206228 kb
Host smart-e8c1acc1-94ea-4e79-921a-96346322f40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403
73309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.4240373309
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3431175526
Short name T1226
Test name
Test status
Simulation time 170163516 ps
CPU time 0.78 seconds
Started Jun 30 06:24:33 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206152 kb
Host smart-db4fcb76-3075-4a92-bed1-efb3884b0f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34311
75526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3431175526
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1084352373
Short name T2469
Test name
Test status
Simulation time 180200317 ps
CPU time 0.83 seconds
Started Jun 30 06:24:36 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 206200 kb
Host smart-0a2b132b-7c81-40fe-b74c-f9c153a12413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843
52373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1084352373
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3445410123
Short name T2367
Test name
Test status
Simulation time 153227336 ps
CPU time 0.79 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:43 PM PDT 24
Peak memory 206172 kb
Host smart-270455bd-a8c6-4f0a-8a64-fc3da7934937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34454
10123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3445410123
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1481545008
Short name T360
Test name
Test status
Simulation time 255743497 ps
CPU time 0.89 seconds
Started Jun 30 06:24:34 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206156 kb
Host smart-f56ded47-b93a-4f8e-bd9e-f1ed2d0bb286
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1481545008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1481545008
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3053740172
Short name T537
Test name
Test status
Simulation time 180599758 ps
CPU time 0.77 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:43 PM PDT 24
Peak memory 206172 kb
Host smart-548adbfc-aa92-4eb4-87e0-4c473aa28bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30537
40172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3053740172
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2121739879
Short name T1134
Test name
Test status
Simulation time 47617641 ps
CPU time 0.66 seconds
Started Jun 30 06:24:35 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206172 kb
Host smart-6207243c-d746-4299-8bb0-23286d0279a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21217
39879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2121739879
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3133896748
Short name T1978
Test name
Test status
Simulation time 14021511669 ps
CPU time 30.19 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:25:03 PM PDT 24
Peak memory 206480 kb
Host smart-be966c25-a47b-491b-a4db-c1e985869d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31338
96748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3133896748
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3324190189
Short name T560
Test name
Test status
Simulation time 206536452 ps
CPU time 0.86 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:43 PM PDT 24
Peak memory 206164 kb
Host smart-30a13019-85d7-4b28-a4c6-9126d14da79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33241
90189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3324190189
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2254043763
Short name T1356
Test name
Test status
Simulation time 230940489 ps
CPU time 1 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206196 kb
Host smart-432701c4-3ea1-4c0a-899f-cb40eab8c159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22540
43763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2254043763
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3764622605
Short name T341
Test name
Test status
Simulation time 169347631 ps
CPU time 0.78 seconds
Started Jun 30 06:24:35 PM PDT 24
Finished Jun 30 06:24:39 PM PDT 24
Peak memory 206188 kb
Host smart-0b55908a-3a55-4283-baf2-47f897fa5428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37646
22605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3764622605
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1121073517
Short name T376
Test name
Test status
Simulation time 172647987 ps
CPU time 0.81 seconds
Started Jun 30 06:24:36 PM PDT 24
Finished Jun 30 06:24:39 PM PDT 24
Peak memory 206188 kb
Host smart-a0b51302-5d51-4947-b379-fef5b18a8e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11210
73517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1121073517
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1500646006
Short name T1114
Test name
Test status
Simulation time 139428259 ps
CPU time 0.77 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206188 kb
Host smart-1cc93e4c-7a77-42bf-9957-0c4fec7ebf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15006
46006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1500646006
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1037614066
Short name T412
Test name
Test status
Simulation time 149605611 ps
CPU time 0.8 seconds
Started Jun 30 06:24:30 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206184 kb
Host smart-b042e314-f14b-4f4b-94f4-84b670fe6c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10376
14066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1037614066
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1626515323
Short name T1489
Test name
Test status
Simulation time 154657318 ps
CPU time 0.77 seconds
Started Jun 30 06:24:29 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 206176 kb
Host smart-51461966-577b-4e75-8f2d-c917edfef1d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16265
15323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1626515323
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3443801524
Short name T2043
Test name
Test status
Simulation time 192529506 ps
CPU time 0.9 seconds
Started Jun 30 06:24:30 PM PDT 24
Finished Jun 30 06:24:35 PM PDT 24
Peak memory 206208 kb
Host smart-46687c3c-47e8-4ad3-8a94-b1a64b4d6ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34438
01524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3443801524
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.873486415
Short name T1048
Test name
Test status
Simulation time 4860787807 ps
CPU time 32.2 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:25:12 PM PDT 24
Peak memory 206244 kb
Host smart-7f8d50dd-9eef-4384-8891-f326af08ebfb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=873486415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.873486415
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3563462922
Short name T2528
Test name
Test status
Simulation time 174603312 ps
CPU time 0.79 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 205980 kb
Host smart-4511fbbc-cda4-42b9-869e-cd87e4c55a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35634
62922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3563462922
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2504969
Short name T1649
Test name
Test status
Simulation time 174706670 ps
CPU time 0.77 seconds
Started Jun 30 06:24:34 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206156 kb
Host smart-c6923d84-8d8a-4dc4-8018-89d849d6d2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25049
69 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2504969
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.214939538
Short name T1572
Test name
Test status
Simulation time 3776411857 ps
CPU time 27.25 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:59 PM PDT 24
Peak memory 206352 kb
Host smart-1f452d39-cce4-4f59-b0aa-49d9e6be787c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21493
9538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.214939538
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.75341583
Short name T525
Test name
Test status
Simulation time 50027492 ps
CPU time 0.69 seconds
Started Jun 30 06:24:44 PM PDT 24
Finished Jun 30 06:24:48 PM PDT 24
Peak memory 206220 kb
Host smart-d04c444b-0f2f-4621-8c84-7bf955c8d364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=75341583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.75341583
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3883380481
Short name T2281
Test name
Test status
Simulation time 3820533199 ps
CPU time 4.56 seconds
Started Jun 30 06:24:35 PM PDT 24
Finished Jun 30 06:24:42 PM PDT 24
Peak memory 206260 kb
Host smart-7633209e-007b-4089-91dc-c4d08ea8b85a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3883380481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3883380481
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2788544245
Short name T1989
Test name
Test status
Simulation time 13396594723 ps
CPU time 12.6 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:52 PM PDT 24
Peak memory 206248 kb
Host smart-3384ff5e-be69-46b0-8975-ee272e8c45ad
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2788544245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2788544245
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2816761115
Short name T912
Test name
Test status
Simulation time 23311565833 ps
CPU time 26.46 seconds
Started Jun 30 06:24:28 PM PDT 24
Finished Jun 30 06:24:59 PM PDT 24
Peak memory 206280 kb
Host smart-1f3c9034-ae74-4be5-a40b-fb59a487b798
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2816761115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.2816761115
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2885324787
Short name T2101
Test name
Test status
Simulation time 193307874 ps
CPU time 0.86 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:32 PM PDT 24
Peak memory 206200 kb
Host smart-e04bcba2-6785-47f0-9052-1f0fe1453ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28853
24787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2885324787
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.221787817
Short name T1852
Test name
Test status
Simulation time 152661728 ps
CPU time 0.75 seconds
Started Jun 30 06:24:27 PM PDT 24
Finished Jun 30 06:24:33 PM PDT 24
Peak memory 206172 kb
Host smart-7336a748-3ab5-4ae1-aaa0-8d794a5a22ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22178
7817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.221787817
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3483639776
Short name T494
Test name
Test status
Simulation time 185857623 ps
CPU time 0.82 seconds
Started Jun 30 06:24:33 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206156 kb
Host smart-e83b5b7d-bc0b-4206-b991-12b0454b9fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
39776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3483639776
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.524838454
Short name T2609
Test name
Test status
Simulation time 709191614 ps
CPU time 1.83 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 206164 kb
Host smart-01ed6caa-3eb4-4e60-9f13-3817105e7b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52483
8454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.524838454
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.1204249997
Short name T934
Test name
Test status
Simulation time 11703455002 ps
CPU time 21.43 seconds
Started Jun 30 06:24:34 PM PDT 24
Finished Jun 30 06:24:58 PM PDT 24
Peak memory 206420 kb
Host smart-2ed68f86-d366-4604-a581-f30bc33bf3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12042
49997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1204249997
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3533182080
Short name T1390
Test name
Test status
Simulation time 470906779 ps
CPU time 1.45 seconds
Started Jun 30 06:24:46 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 206196 kb
Host smart-774ffa91-05d1-4218-a176-c5a573b06b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35331
82080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3533182080
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2767830144
Short name T2414
Test name
Test status
Simulation time 176743882 ps
CPU time 0.76 seconds
Started Jun 30 06:24:44 PM PDT 24
Finished Jun 30 06:24:47 PM PDT 24
Peak memory 206164 kb
Host smart-bb6298cb-30c3-4ee5-9c21-e0329c022f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27678
30144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2767830144
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3904248016
Short name T1043
Test name
Test status
Simulation time 85967858 ps
CPU time 0.69 seconds
Started Jun 30 06:24:33 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 206184 kb
Host smart-22e5a186-20e3-4d9a-b94e-1fb933090bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39042
48016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3904248016
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2960385613
Short name T877
Test name
Test status
Simulation time 821016662 ps
CPU time 1.86 seconds
Started Jun 30 06:24:35 PM PDT 24
Finished Jun 30 06:24:40 PM PDT 24
Peak memory 206240 kb
Host smart-c1662eb4-e74b-4c80-b06e-65cbc35aa422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29603
85613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2960385613
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2136132444
Short name T1823
Test name
Test status
Simulation time 169782713 ps
CPU time 1.81 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:42 PM PDT 24
Peak memory 206324 kb
Host smart-1a0910aa-3226-47bc-a11c-c3a56d81b2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21361
32444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2136132444
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.747683003
Short name T1329
Test name
Test status
Simulation time 232004142 ps
CPU time 0.91 seconds
Started Jun 30 06:24:36 PM PDT 24
Finished Jun 30 06:24:39 PM PDT 24
Peak memory 206152 kb
Host smart-44e4642a-fd23-47aa-999a-450e8113af7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74768
3003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.747683003
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3089003870
Short name T2285
Test name
Test status
Simulation time 162116319 ps
CPU time 0.79 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:24:42 PM PDT 24
Peak memory 206208 kb
Host smart-4e2eae39-effd-4f99-b539-166b257392fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30890
03870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3089003870
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2696241068
Short name T2496
Test name
Test status
Simulation time 162907368 ps
CPU time 0.79 seconds
Started Jun 30 06:24:41 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 206208 kb
Host smart-0035a4f8-4a38-404f-9fce-826a64e64654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26962
41068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2696241068
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.1020286702
Short name T102
Test name
Test status
Simulation time 6986704740 ps
CPU time 198.59 seconds
Started Jun 30 06:24:41 PM PDT 24
Finished Jun 30 06:28:02 PM PDT 24
Peak memory 206468 kb
Host smart-628ca752-c3da-4e9e-88fa-8432742962ee
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1020286702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.1020286702
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.532674963
Short name T1311
Test name
Test status
Simulation time 244980775 ps
CPU time 0.89 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:24:41 PM PDT 24
Peak memory 206196 kb
Host smart-b0b93711-d6b1-4c9c-8b9a-da34c48d4647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53267
4963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.532674963
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3546858953
Short name T28
Test name
Test status
Simulation time 23309414049 ps
CPU time 22.72 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:25:03 PM PDT 24
Peak memory 206288 kb
Host smart-a81b9ff6-12f0-403d-81ba-28fc7512e9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35468
58953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3546858953
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1532520124
Short name T1288
Test name
Test status
Simulation time 3312835166 ps
CPU time 3.81 seconds
Started Jun 30 06:24:39 PM PDT 24
Finished Jun 30 06:24:46 PM PDT 24
Peak memory 206472 kb
Host smart-f206402f-2278-49e1-875a-aba6681a1d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15325
20124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1532520124
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.3567154427
Short name T1397
Test name
Test status
Simulation time 7090703621 ps
CPU time 200.53 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:28:03 PM PDT 24
Peak memory 206476 kb
Host smart-fae9192e-e5de-4ff5-bc02-dfb774148519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35671
54427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.3567154427
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2122839425
Short name T2077
Test name
Test status
Simulation time 4472268426 ps
CPU time 122.54 seconds
Started Jun 30 06:24:34 PM PDT 24
Finished Jun 30 06:26:40 PM PDT 24
Peak memory 206452 kb
Host smart-d26ae4f4-94d1-4a90-bb6d-6c5df28abbfd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2122839425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2122839425
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2123336747
Short name T2601
Test name
Test status
Simulation time 248649804 ps
CPU time 1.02 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:24:41 PM PDT 24
Peak memory 206196 kb
Host smart-0a1a69a4-e78f-453e-95d6-9a6b9d0caec0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2123336747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2123336747
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.928954103
Short name T400
Test name
Test status
Simulation time 213878373 ps
CPU time 0.86 seconds
Started Jun 30 06:24:35 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206204 kb
Host smart-14eb901b-57f8-4a66-8736-6e8cc3581af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92895
4103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.928954103
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.2941487651
Short name T2567
Test name
Test status
Simulation time 3788252842 ps
CPU time 26.08 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:25:07 PM PDT 24
Peak memory 206496 kb
Host smart-64f81786-648e-4bae-a73d-24608b439c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29414
87651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.2941487651
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3182923191
Short name T2240
Test name
Test status
Simulation time 5596652835 ps
CPU time 50.53 seconds
Started Jun 30 06:24:43 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206488 kb
Host smart-2bda8003-0c64-4698-8c10-1da213473c7b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3182923191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3182923191
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.4244068827
Short name T2574
Test name
Test status
Simulation time 148860439 ps
CPU time 0.77 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:24:46 PM PDT 24
Peak memory 206212 kb
Host smart-dab3c888-0e03-43d5-9df5-6bfe1ca8eed4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4244068827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.4244068827
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.483021252
Short name T2594
Test name
Test status
Simulation time 144915381 ps
CPU time 0.75 seconds
Started Jun 30 06:24:42 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 206188 kb
Host smart-64dd2df0-9a24-401b-96b0-8d0c20cc738e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48302
1252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.483021252
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.843255454
Short name T136
Test name
Test status
Simulation time 200667018 ps
CPU time 0.9 seconds
Started Jun 30 06:24:41 PM PDT 24
Finished Jun 30 06:24:44 PM PDT 24
Peak memory 206192 kb
Host smart-7cda4ac2-6e80-49b4-825f-e5fc27784ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84325
5454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.843255454
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.399126020
Short name T471
Test name
Test status
Simulation time 249891605 ps
CPU time 0.9 seconds
Started Jun 30 06:24:46 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 206204 kb
Host smart-5fdaab8d-fcf5-4a6c-adc3-917c37dd7724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39912
6020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.399126020
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1282422638
Short name T2555
Test name
Test status
Simulation time 167487380 ps
CPU time 0.79 seconds
Started Jun 30 06:24:45 PM PDT 24
Finished Jun 30 06:24:49 PM PDT 24
Peak memory 206220 kb
Host smart-fc273f7d-edd2-49a8-a0b7-ee92c6ac5aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12824
22638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1282422638
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3948264777
Short name T1033
Test name
Test status
Simulation time 149314533 ps
CPU time 0.81 seconds
Started Jun 30 06:24:34 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206240 kb
Host smart-43b122fe-173f-4986-95c3-63f2352fb435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39482
64777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3948264777
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.118419482
Short name T185
Test name
Test status
Simulation time 201034437 ps
CPU time 0.83 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:43 PM PDT 24
Peak memory 206244 kb
Host smart-3e8f4fe0-c2b2-4650-a926-f65b5efd90a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11841
9482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.118419482
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.2895086145
Short name T985
Test name
Test status
Simulation time 245766259 ps
CPU time 1.05 seconds
Started Jun 30 06:24:41 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 206176 kb
Host smart-82e391e1-2ee0-4547-8fa1-1b27f75cab03
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2895086145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2895086145
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3491586632
Short name T2419
Test name
Test status
Simulation time 151056624 ps
CPU time 0.75 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:43 PM PDT 24
Peak memory 206188 kb
Host smart-5ce76b18-aeac-4bbe-8f8a-1ca426cbe5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34915
86632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3491586632
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3850503822
Short name T2384
Test name
Test status
Simulation time 42082332 ps
CPU time 0.65 seconds
Started Jun 30 06:24:45 PM PDT 24
Finished Jun 30 06:24:49 PM PDT 24
Peak memory 206196 kb
Host smart-2cd35891-4058-4f24-8b06-d9a48ab3d825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38505
03822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3850503822
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.261707637
Short name T1205
Test name
Test status
Simulation time 20734589251 ps
CPU time 44.53 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:25:25 PM PDT 24
Peak memory 206428 kb
Host smart-11ee72aa-5da7-4bb6-9a87-c01116f36469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26170
7637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.261707637
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2875551244
Short name T1186
Test name
Test status
Simulation time 183536701 ps
CPU time 0.85 seconds
Started Jun 30 06:24:41 PM PDT 24
Finished Jun 30 06:24:44 PM PDT 24
Peak memory 206356 kb
Host smart-48bbf344-3dc0-4122-839f-b032a683bb51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755
51244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2875551244
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.4070969039
Short name T1324
Test name
Test status
Simulation time 241744242 ps
CPU time 0.96 seconds
Started Jun 30 06:24:39 PM PDT 24
Finished Jun 30 06:24:42 PM PDT 24
Peak memory 206192 kb
Host smart-26055747-f28d-4dff-babf-8b9ccaec8391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40709
69039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.4070969039
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1321036867
Short name T2070
Test name
Test status
Simulation time 169571828 ps
CPU time 0.79 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:44 PM PDT 24
Peak memory 206224 kb
Host smart-c5abe87f-0d9f-42c8-8c78-8612f4db9131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13210
36867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1321036867
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.284487563
Short name T2377
Test name
Test status
Simulation time 174550213 ps
CPU time 0.85 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:24:41 PM PDT 24
Peak memory 206192 kb
Host smart-716a8eac-ebea-49ad-83d5-6fa088bcfc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28448
7563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.284487563
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3865494151
Short name T342
Test name
Test status
Simulation time 134952809 ps
CPU time 0.77 seconds
Started Jun 30 06:24:33 PM PDT 24
Finished Jun 30 06:24:42 PM PDT 24
Peak memory 206192 kb
Host smart-4bb62738-390a-4858-a42b-36fb3a3a2144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38654
94151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3865494151
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.535530394
Short name T451
Test name
Test status
Simulation time 152197792 ps
CPU time 0.77 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:43 PM PDT 24
Peak memory 206164 kb
Host smart-f7be5f67-5c32-4853-a0c5-19de4229c982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53553
0394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.535530394
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3880563198
Short name T1064
Test name
Test status
Simulation time 162928822 ps
CPU time 0.77 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:40 PM PDT 24
Peak memory 206032 kb
Host smart-d5b66953-881c-455e-ab8f-b95872e22f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38805
63198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3880563198
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1054175125
Short name T1710
Test name
Test status
Simulation time 202662920 ps
CPU time 0.86 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:41 PM PDT 24
Peak memory 206220 kb
Host smart-2b24b508-2e14-4ef3-9dac-688c275c5ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10541
75125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1054175125
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.2938660758
Short name T1464
Test name
Test status
Simulation time 3794985616 ps
CPU time 35.24 seconds
Started Jun 30 06:24:35 PM PDT 24
Finished Jun 30 06:25:13 PM PDT 24
Peak memory 206420 kb
Host smart-9936fa2e-2349-4b86-aa32-6b375543d852
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2938660758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.2938660758
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2132958172
Short name T1630
Test name
Test status
Simulation time 155065674 ps
CPU time 0.79 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:24:42 PM PDT 24
Peak memory 206228 kb
Host smart-594784a0-f00c-4137-ad77-475856617919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21329
58172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2132958172
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2603901083
Short name T2169
Test name
Test status
Simulation time 180492398 ps
CPU time 0.8 seconds
Started Jun 30 06:24:42 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 206168 kb
Host smart-12074aff-2ab6-4403-9082-62867b5098e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26039
01083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2603901083
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.428923928
Short name T1299
Test name
Test status
Simulation time 3872817366 ps
CPU time 27.04 seconds
Started Jun 30 06:24:42 PM PDT 24
Finished Jun 30 06:25:11 PM PDT 24
Peak memory 206400 kb
Host smart-762231fb-5a97-4830-9b66-b47688fe443c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42892
3928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.428923928
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.3724361084
Short name T521
Test name
Test status
Simulation time 51199904 ps
CPU time 0.66 seconds
Started Jun 30 06:24:45 PM PDT 24
Finished Jun 30 06:24:49 PM PDT 24
Peak memory 206200 kb
Host smart-639834f7-dc02-4889-b5aa-4136918413c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3724361084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3724361084
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2212531328
Short name T2068
Test name
Test status
Simulation time 4038976175 ps
CPU time 4.91 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:44 PM PDT 24
Peak memory 206384 kb
Host smart-99938364-03d8-4585-b39c-5d2f9a163cf3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2212531328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2212531328
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.4286469610
Short name T844
Test name
Test status
Simulation time 13318720434 ps
CPU time 13.97 seconds
Started Jun 30 06:24:36 PM PDT 24
Finished Jun 30 06:24:53 PM PDT 24
Peak memory 206216 kb
Host smart-384a80f5-1cf9-479d-86e0-f9a6cdf5c9df
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4286469610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.4286469610
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3334269281
Short name T2189
Test name
Test status
Simulation time 23408716396 ps
CPU time 22.76 seconds
Started Jun 30 06:24:36 PM PDT 24
Finished Jun 30 06:25:02 PM PDT 24
Peak memory 206424 kb
Host smart-86eb2bfd-787e-42a8-a78c-e1fea15033bb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3334269281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.3334269281
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3690562207
Short name T1715
Test name
Test status
Simulation time 146396911 ps
CPU time 0.77 seconds
Started Jun 30 06:24:34 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206180 kb
Host smart-349a578b-4d6c-4455-b1a2-f891de9db8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36905
62207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3690562207
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.4260930470
Short name T659
Test name
Test status
Simulation time 169323089 ps
CPU time 0.84 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:41 PM PDT 24
Peak memory 206172 kb
Host smart-fb65d3c8-ee4e-44df-ad9a-4090110d9da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42609
30470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.4260930470
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.2889983676
Short name T2126
Test name
Test status
Simulation time 188501745 ps
CPU time 0.84 seconds
Started Jun 30 06:24:35 PM PDT 24
Finished Jun 30 06:24:38 PM PDT 24
Peak memory 206188 kb
Host smart-9313ef31-d9ef-4489-8770-2fd29edaf542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28899
83676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.2889983676
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2606112162
Short name T1886
Test name
Test status
Simulation time 947838806 ps
CPU time 2.19 seconds
Started Jun 30 06:24:36 PM PDT 24
Finished Jun 30 06:24:41 PM PDT 24
Peak memory 206316 kb
Host smart-e78c53b7-3d79-46c5-b7e9-c762bf0c9611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26061
12162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2606112162
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.2562710340
Short name T1599
Test name
Test status
Simulation time 9220645467 ps
CPU time 18.4 seconds
Started Jun 30 06:24:46 PM PDT 24
Finished Jun 30 06:25:07 PM PDT 24
Peak memory 206384 kb
Host smart-62d5389d-63b7-465a-a20b-09228a64df1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25627
10340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.2562710340
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2923967126
Short name T1317
Test name
Test status
Simulation time 528334218 ps
CPU time 1.45 seconds
Started Jun 30 06:24:42 PM PDT 24
Finished Jun 30 06:24:46 PM PDT 24
Peak memory 206176 kb
Host smart-916e2f23-ed14-45e0-a1d1-77103c541d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29239
67126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2923967126
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1576550142
Short name T733
Test name
Test status
Simulation time 174801071 ps
CPU time 0.82 seconds
Started Jun 30 06:24:43 PM PDT 24
Finished Jun 30 06:24:47 PM PDT 24
Peak memory 206184 kb
Host smart-386fd4a6-9f72-44d5-b2a2-be69b0a23c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15765
50142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1576550142
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.590029106
Short name T2044
Test name
Test status
Simulation time 71602910 ps
CPU time 0.73 seconds
Started Jun 30 06:24:43 PM PDT 24
Finished Jun 30 06:24:46 PM PDT 24
Peak memory 206200 kb
Host smart-c026e7bd-aad1-49e2-baab-062dacb95529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59002
9106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.590029106
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1738995743
Short name T648
Test name
Test status
Simulation time 722440546 ps
CPU time 1.75 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:24:42 PM PDT 24
Peak memory 206332 kb
Host smart-c8057c4e-b1f0-4b02-929f-22905fd1d223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17389
95743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1738995743
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1209390631
Short name T621
Test name
Test status
Simulation time 188133490 ps
CPU time 2.18 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 206280 kb
Host smart-f9a6c316-9015-465f-b8d5-5f5981522a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12093
90631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1209390631
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3985681722
Short name T1724
Test name
Test status
Simulation time 240942874 ps
CPU time 0.93 seconds
Started Jun 30 06:24:42 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 206164 kb
Host smart-866c7be6-5942-411b-be63-77df6db73ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39856
81722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3985681722
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1542056117
Short name T617
Test name
Test status
Simulation time 167032327 ps
CPU time 0.75 seconds
Started Jun 30 06:24:37 PM PDT 24
Finished Jun 30 06:24:41 PM PDT 24
Peak memory 206196 kb
Host smart-7ea204c9-4b54-4fef-bbda-d2684dbf0269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15420
56117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1542056117
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.433222690
Short name T1758
Test name
Test status
Simulation time 168408486 ps
CPU time 0.78 seconds
Started Jun 30 06:24:43 PM PDT 24
Finished Jun 30 06:24:47 PM PDT 24
Peak memory 206132 kb
Host smart-d026c3a1-f56d-4b50-bd30-499f9e6cd5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43322
2690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.433222690
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.266222653
Short name T581
Test name
Test status
Simulation time 9401315391 ps
CPU time 83.76 seconds
Started Jun 30 06:24:45 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206380 kb
Host smart-64dc067e-37d7-4ff9-b9e4-9d92672bcc17
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=266222653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.266222653
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.3985290654
Short name T2208
Test name
Test status
Simulation time 238867305 ps
CPU time 0.87 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:24:41 PM PDT 24
Peak memory 206192 kb
Host smart-ccf80fec-5e81-47b0-8ca1-4245ec526488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39852
90654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.3985290654
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.569782468
Short name T2591
Test name
Test status
Simulation time 23264585847 ps
CPU time 22.41 seconds
Started Jun 30 06:24:36 PM PDT 24
Finished Jun 30 06:25:02 PM PDT 24
Peak memory 206312 kb
Host smart-cc66dc7f-6147-4777-a546-bfad4c2a2b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56978
2468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.569782468
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2328215685
Short name T1826
Test name
Test status
Simulation time 3306676677 ps
CPU time 3.62 seconds
Started Jun 30 06:24:46 PM PDT 24
Finished Jun 30 06:24:53 PM PDT 24
Peak memory 206248 kb
Host smart-309bad70-57e2-49eb-9fcb-4f977f306ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
15685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2328215685
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.3607839276
Short name T1452
Test name
Test status
Simulation time 14961721987 ps
CPU time 109.8 seconds
Started Jun 30 06:24:47 PM PDT 24
Finished Jun 30 06:26:39 PM PDT 24
Peak memory 206508 kb
Host smart-2024887f-86d3-424e-80d5-472e53e29d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36078
39276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.3607839276
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.619955369
Short name T2109
Test name
Test status
Simulation time 5636085267 ps
CPU time 39.77 seconds
Started Jun 30 06:24:41 PM PDT 24
Finished Jun 30 06:25:24 PM PDT 24
Peak memory 206448 kb
Host smart-75b04ee2-ff36-4b34-9a1d-647af8098648
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=619955369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.619955369
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.125371992
Short name T425
Test name
Test status
Simulation time 250968853 ps
CPU time 0.87 seconds
Started Jun 30 06:24:45 PM PDT 24
Finished Jun 30 06:24:49 PM PDT 24
Peak memory 206192 kb
Host smart-cacfde55-0f91-4bf0-aba2-6477323e3d25
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=125371992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.125371992
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2331245608
Short name T600
Test name
Test status
Simulation time 182105980 ps
CPU time 0.85 seconds
Started Jun 30 06:24:43 PM PDT 24
Finished Jun 30 06:24:46 PM PDT 24
Peak memory 206220 kb
Host smart-26eea9b8-4956-4c70-bb28-0618ca3a7aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23312
45608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2331245608
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.4224106795
Short name T2304
Test name
Test status
Simulation time 6033519514 ps
CPU time 43 seconds
Started Jun 30 06:24:47 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206404 kb
Host smart-b09ba4d0-cfff-40f7-b3da-58fb1efc155c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42241
06795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.4224106795
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.985625757
Short name T1959
Test name
Test status
Simulation time 5714410239 ps
CPU time 39.47 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206456 kb
Host smart-5f3be3e4-8fce-407b-8334-e511542a39d0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=985625757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.985625757
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.1608601060
Short name T997
Test name
Test status
Simulation time 197184236 ps
CPU time 0.82 seconds
Started Jun 30 06:24:43 PM PDT 24
Finished Jun 30 06:24:47 PM PDT 24
Peak memory 206180 kb
Host smart-894d6728-d5d2-4017-bda6-3969644741f3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1608601060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.1608601060
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3328698369
Short name T696
Test name
Test status
Simulation time 155826656 ps
CPU time 0.76 seconds
Started Jun 30 06:24:44 PM PDT 24
Finished Jun 30 06:24:47 PM PDT 24
Peak memory 206172 kb
Host smart-7a10f09a-148c-421a-b14e-e553e955f7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33286
98369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3328698369
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1482525259
Short name T1075
Test name
Test status
Simulation time 190497817 ps
CPU time 0.91 seconds
Started Jun 30 06:24:47 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 206200 kb
Host smart-710c54bf-2460-4b59-a6a6-2538fd449a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14825
25259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1482525259
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3318844376
Short name T1626
Test name
Test status
Simulation time 184739669 ps
CPU time 0.79 seconds
Started Jun 30 06:24:44 PM PDT 24
Finished Jun 30 06:24:47 PM PDT 24
Peak memory 206052 kb
Host smart-eda9859f-8d4f-4f2b-bd3f-6a584a11cf6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33188
44376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3318844376
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3051606932
Short name T2351
Test name
Test status
Simulation time 208645373 ps
CPU time 0.81 seconds
Started Jun 30 06:24:42 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 206204 kb
Host smart-144950f5-b283-4750-b19c-5c19a8c72ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30516
06932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3051606932
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1334227742
Short name T547
Test name
Test status
Simulation time 164750135 ps
CPU time 0.77 seconds
Started Jun 30 06:24:43 PM PDT 24
Finished Jun 30 06:24:47 PM PDT 24
Peak memory 206188 kb
Host smart-e0a420cc-5a81-49ad-9afd-8ab8fae9ca05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13342
27742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1334227742
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2594517306
Short name T421
Test name
Test status
Simulation time 243088207 ps
CPU time 1.05 seconds
Started Jun 30 06:24:49 PM PDT 24
Finished Jun 30 06:24:51 PM PDT 24
Peak memory 206216 kb
Host smart-7e1e81a9-0e5e-43e4-81ea-25615a80d881
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2594517306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2594517306
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1043855368
Short name T2200
Test name
Test status
Simulation time 159449973 ps
CPU time 0.77 seconds
Started Jun 30 06:24:44 PM PDT 24
Finished Jun 30 06:24:48 PM PDT 24
Peak memory 206172 kb
Host smart-edd8bf42-f5a0-4645-9f15-84c0998c5ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10438
55368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1043855368
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2967674398
Short name T2392
Test name
Test status
Simulation time 34733535 ps
CPU time 0.66 seconds
Started Jun 30 06:24:43 PM PDT 24
Finished Jun 30 06:24:46 PM PDT 24
Peak memory 206200 kb
Host smart-9211d3b1-787b-4763-8f79-0bd1d4351c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29676
74398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2967674398
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.522766172
Short name T1015
Test name
Test status
Simulation time 21864944687 ps
CPU time 52.84 seconds
Started Jun 30 06:24:43 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206388 kb
Host smart-963e08d4-02bb-49cf-8ad4-4051ef200f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52276
6172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.522766172
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1079029414
Short name T1733
Test name
Test status
Simulation time 168720372 ps
CPU time 0.84 seconds
Started Jun 30 06:24:47 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 206180 kb
Host smart-8afb8018-3313-41c7-88b4-60c8887da3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10790
29414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1079029414
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1623051438
Short name T385
Test name
Test status
Simulation time 206409900 ps
CPU time 0.85 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:43 PM PDT 24
Peak memory 206048 kb
Host smart-848e8eb9-baee-4fc7-a55f-1c2f9b1d70c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16230
51438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1623051438
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2757587344
Short name T2380
Test name
Test status
Simulation time 211693555 ps
CPU time 0.85 seconds
Started Jun 30 06:24:41 PM PDT 24
Finished Jun 30 06:24:45 PM PDT 24
Peak memory 206204 kb
Host smart-9c9440e5-c747-4013-b542-dc8398d765ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27575
87344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2757587344
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1756565
Short name T1544
Test name
Test status
Simulation time 235266061 ps
CPU time 0.88 seconds
Started Jun 30 06:24:45 PM PDT 24
Finished Jun 30 06:24:49 PM PDT 24
Peak memory 206120 kb
Host smart-67222e2b-2285-42f5-9ca6-8796f01c1aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17565
65 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1756565
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.97057956
Short name T2026
Test name
Test status
Simulation time 151221859 ps
CPU time 0.8 seconds
Started Jun 30 06:24:40 PM PDT 24
Finished Jun 30 06:24:44 PM PDT 24
Peak memory 206396 kb
Host smart-2cdc9e35-3287-4703-b854-adda382e4f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97057
956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.97057956
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3192613432
Short name T940
Test name
Test status
Simulation time 187479278 ps
CPU time 0.76 seconds
Started Jun 30 06:24:41 PM PDT 24
Finished Jun 30 06:24:44 PM PDT 24
Peak memory 206116 kb
Host smart-ee42fb38-dc17-4d6f-b0ab-92f9ecd97392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31926
13432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3192613432
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1818498284
Short name T1104
Test name
Test status
Simulation time 168689675 ps
CPU time 0.86 seconds
Started Jun 30 06:24:46 PM PDT 24
Finished Jun 30 06:24:49 PM PDT 24
Peak memory 206168 kb
Host smart-ed2cf9f0-90fe-474d-b7c6-7154de4e5261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18184
98284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1818498284
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3124898553
Short name T1699
Test name
Test status
Simulation time 236252682 ps
CPU time 0.96 seconds
Started Jun 30 06:24:38 PM PDT 24
Finished Jun 30 06:24:42 PM PDT 24
Peak memory 206196 kb
Host smart-b325f398-b65c-4003-be67-7592fd0ec9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31248
98553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3124898553
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.273453157
Short name T1549
Test name
Test status
Simulation time 4382320966 ps
CPU time 38.84 seconds
Started Jun 30 06:24:43 PM PDT 24
Finished Jun 30 06:25:24 PM PDT 24
Peak memory 206420 kb
Host smart-254af6c9-8f2c-40aa-9d68-06d6f608219f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=273453157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.273453157
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.196296292
Short name T2049
Test name
Test status
Simulation time 160025988 ps
CPU time 0.76 seconds
Started Jun 30 06:24:45 PM PDT 24
Finished Jun 30 06:24:48 PM PDT 24
Peak memory 206204 kb
Host smart-9b0ba2c2-1199-4a79-92ba-5dfa7843fe3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19629
6292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.196296292
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1966480078
Short name T988
Test name
Test status
Simulation time 153013889 ps
CPU time 0.87 seconds
Started Jun 30 06:24:45 PM PDT 24
Finished Jun 30 06:24:48 PM PDT 24
Peak memory 206188 kb
Host smart-87257e6c-e34c-495e-8888-d7a96bb9755e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19664
80078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1966480078
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.1793899772
Short name T585
Test name
Test status
Simulation time 5651168709 ps
CPU time 49.98 seconds
Started Jun 30 06:24:45 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206464 kb
Host smart-fc931093-5861-49e3-9575-c18db8467406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17938
99772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.1793899772
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.594760001
Short name T476
Test name
Test status
Simulation time 83906186 ps
CPU time 0.69 seconds
Started Jun 30 06:24:59 PM PDT 24
Finished Jun 30 06:25:00 PM PDT 24
Peak memory 206192 kb
Host smart-a6f8cee7-a13f-4626-9d27-b6d3b415ca20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=594760001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.594760001
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.4025801511
Short name T1806
Test name
Test status
Simulation time 3722198867 ps
CPU time 4.3 seconds
Started Jun 30 06:24:46 PM PDT 24
Finished Jun 30 06:24:53 PM PDT 24
Peak memory 206272 kb
Host smart-413d534e-bb5c-49c0-a8cb-bb6d5ba7c029
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4025801511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.4025801511
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.4221623090
Short name T1171
Test name
Test status
Simulation time 13343081315 ps
CPU time 13.18 seconds
Started Jun 30 06:25:00 PM PDT 24
Finished Jun 30 06:25:14 PM PDT 24
Peak memory 206384 kb
Host smart-914edb1d-1590-4a97-a472-5eac43997d57
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4221623090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.4221623090
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.3410570847
Short name T2014
Test name
Test status
Simulation time 23393372154 ps
CPU time 25.93 seconds
Started Jun 30 06:25:07 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206164 kb
Host smart-5a83e1c6-477a-48f1-9ef9-b16f436f75eb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3410570847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.3410570847
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2649442535
Short name T1796
Test name
Test status
Simulation time 164920528 ps
CPU time 0.84 seconds
Started Jun 30 06:25:03 PM PDT 24
Finished Jun 30 06:25:05 PM PDT 24
Peak memory 206196 kb
Host smart-ab667ad4-ebbb-4b70-9756-71f4080a18b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26494
42535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2649442535
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.4146025085
Short name T2286
Test name
Test status
Simulation time 224411000 ps
CPU time 0.88 seconds
Started Jun 30 06:24:49 PM PDT 24
Finished Jun 30 06:24:51 PM PDT 24
Peak memory 206192 kb
Host smart-df75dd93-a2d9-4f63-bc85-8d2d4a68b278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41460
25085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.4146025085
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.2382401474
Short name T1540
Test name
Test status
Simulation time 277036427 ps
CPU time 1.14 seconds
Started Jun 30 06:24:53 PM PDT 24
Finished Jun 30 06:24:54 PM PDT 24
Peak memory 206180 kb
Host smart-eab225f9-e2c7-4f35-b149-2d710bfae164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23824
01474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.2382401474
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3343002471
Short name T1383
Test name
Test status
Simulation time 1251263395 ps
CPU time 2.92 seconds
Started Jun 30 06:24:52 PM PDT 24
Finished Jun 30 06:24:55 PM PDT 24
Peak memory 206276 kb
Host smart-8cb757e6-f3ee-4ab8-9130-56368228cdd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33430
02471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3343002471
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2987964184
Short name T189
Test name
Test status
Simulation time 7965702451 ps
CPU time 15.49 seconds
Started Jun 30 06:24:55 PM PDT 24
Finished Jun 30 06:25:11 PM PDT 24
Peak memory 206408 kb
Host smart-e55e5c1b-d183-4870-89c5-1db9bbfa2268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29879
64184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2987964184
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3763850190
Short name T1697
Test name
Test status
Simulation time 324838986 ps
CPU time 1.11 seconds
Started Jun 30 06:24:49 PM PDT 24
Finished Jun 30 06:24:52 PM PDT 24
Peak memory 206204 kb
Host smart-c416f470-c7cf-4e86-ac03-438451f7f040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37638
50190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3763850190
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2649619680
Short name T1004
Test name
Test status
Simulation time 141982646 ps
CPU time 0.77 seconds
Started Jun 30 06:24:56 PM PDT 24
Finished Jun 30 06:24:57 PM PDT 24
Peak memory 206200 kb
Host smart-d3352d58-4471-4292-bbda-be9435f1c7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26496
19680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2649619680
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.594358196
Short name T2499
Test name
Test status
Simulation time 54594970 ps
CPU time 0.67 seconds
Started Jun 30 06:24:56 PM PDT 24
Finished Jun 30 06:24:57 PM PDT 24
Peak memory 206196 kb
Host smart-2fb52ee4-cdad-45a0-a07c-037a64141aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59435
8196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.594358196
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1869265703
Short name T1253
Test name
Test status
Simulation time 1041631243 ps
CPU time 2.4 seconds
Started Jun 30 06:24:55 PM PDT 24
Finished Jun 30 06:24:58 PM PDT 24
Peak memory 206388 kb
Host smart-492f6feb-9d4e-47a5-bf64-70142e095974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18692
65703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1869265703
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2295064978
Short name T1274
Test name
Test status
Simulation time 227626321 ps
CPU time 1.24 seconds
Started Jun 30 06:24:48 PM PDT 24
Finished Jun 30 06:24:51 PM PDT 24
Peak memory 206272 kb
Host smart-8a665067-eaf8-4936-aa93-cf54f4c0589e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22950
64978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2295064978
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.121214996
Short name T1740
Test name
Test status
Simulation time 197299979 ps
CPU time 0.89 seconds
Started Jun 30 06:25:00 PM PDT 24
Finished Jun 30 06:25:02 PM PDT 24
Peak memory 206060 kb
Host smart-d3f99006-d67c-4f98-a60e-66bcdc6d57da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12121
4996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.121214996
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2665955016
Short name T891
Test name
Test status
Simulation time 144359368 ps
CPU time 0.78 seconds
Started Jun 30 06:24:46 PM PDT 24
Finished Jun 30 06:24:49 PM PDT 24
Peak memory 206204 kb
Host smart-b8c53b82-436b-4f46-bfde-2a1fd723d95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
55016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2665955016
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2127090570
Short name T2460
Test name
Test status
Simulation time 184575475 ps
CPU time 0.84 seconds
Started Jun 30 06:24:47 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 206208 kb
Host smart-d3343d00-6289-4771-ab75-8e7dc5405a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21270
90570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2127090570
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2634887738
Short name T2541
Test name
Test status
Simulation time 192260189 ps
CPU time 0.85 seconds
Started Jun 30 06:24:48 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 206164 kb
Host smart-0a37886a-a222-44fc-9082-daa75ccd1fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26348
87738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2634887738
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.2290905561
Short name T725
Test name
Test status
Simulation time 23339052306 ps
CPU time 23.56 seconds
Started Jun 30 06:24:56 PM PDT 24
Finished Jun 30 06:25:20 PM PDT 24
Peak memory 206312 kb
Host smart-e687bef1-a23b-49c5-adc6-193a07c5f08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22909
05561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2290905561
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.2085428127
Short name T2062
Test name
Test status
Simulation time 3285078504 ps
CPU time 3.84 seconds
Started Jun 30 06:24:53 PM PDT 24
Finished Jun 30 06:24:58 PM PDT 24
Peak memory 206248 kb
Host smart-2aec4c99-2354-42bd-aaaf-7d2eaf163de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20854
28127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2085428127
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.3622209760
Short name T1651
Test name
Test status
Simulation time 9748641595 ps
CPU time 68.94 seconds
Started Jun 30 06:24:58 PM PDT 24
Finished Jun 30 06:26:08 PM PDT 24
Peak memory 206444 kb
Host smart-f235b709-837f-43ac-8969-4f6611168d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36222
09760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.3622209760
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1513111118
Short name T694
Test name
Test status
Simulation time 5780093329 ps
CPU time 161.88 seconds
Started Jun 30 06:25:00 PM PDT 24
Finished Jun 30 06:27:43 PM PDT 24
Peak memory 206444 kb
Host smart-e8dab6a0-1cd1-4e24-81b3-c019147d159f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1513111118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1513111118
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.3929426928
Short name T532
Test name
Test status
Simulation time 238194033 ps
CPU time 0.94 seconds
Started Jun 30 06:24:51 PM PDT 24
Finished Jun 30 06:24:52 PM PDT 24
Peak memory 206192 kb
Host smart-33a83298-a10a-4734-9fe2-bbf69e7ab88d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3929426928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.3929426928
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3570589102
Short name T26
Test name
Test status
Simulation time 198654003 ps
CPU time 0.85 seconds
Started Jun 30 06:24:53 PM PDT 24
Finished Jun 30 06:24:54 PM PDT 24
Peak memory 206164 kb
Host smart-582788af-d799-4b86-a641-7a6e0922bd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35705
89102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3570589102
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1172670899
Short name T2348
Test name
Test status
Simulation time 5959107201 ps
CPU time 42.88 seconds
Started Jun 30 06:24:55 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206480 kb
Host smart-cdf7a5af-d687-47c1-88e2-1d95edfb736f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11726
70899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1172670899
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.84505591
Short name T1685
Test name
Test status
Simulation time 3689953463 ps
CPU time 26.26 seconds
Started Jun 30 06:25:02 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206484 kb
Host smart-7e53a078-42de-4e52-8420-b3170ec2393b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=84505591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.84505591
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2748827616
Short name T1436
Test name
Test status
Simulation time 149328132 ps
CPU time 0.9 seconds
Started Jun 30 06:25:01 PM PDT 24
Finished Jun 30 06:25:03 PM PDT 24
Peak memory 206192 kb
Host smart-79c1fb1a-79e5-4d46-a66d-e6500701d68f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2748827616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2748827616
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3116537098
Short name T904
Test name
Test status
Simulation time 154650629 ps
CPU time 0.82 seconds
Started Jun 30 06:24:59 PM PDT 24
Finished Jun 30 06:25:00 PM PDT 24
Peak memory 206188 kb
Host smart-cc4f72c8-b233-4975-af34-1672deb1850e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
37098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3116537098
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2702123894
Short name T1381
Test name
Test status
Simulation time 167539797 ps
CPU time 0.87 seconds
Started Jun 30 06:25:09 PM PDT 24
Finished Jun 30 06:25:11 PM PDT 24
Peak memory 206284 kb
Host smart-75016735-95db-40f5-81a1-b076fef4aa0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27021
23894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2702123894
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.866331452
Short name T638
Test name
Test status
Simulation time 188971749 ps
CPU time 0.8 seconds
Started Jun 30 06:24:58 PM PDT 24
Finished Jun 30 06:25:00 PM PDT 24
Peak memory 206192 kb
Host smart-33439a79-7458-4d31-ad13-0532e3b53633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86633
1452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.866331452
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3423563870
Short name T330
Test name
Test status
Simulation time 148186115 ps
CPU time 0.82 seconds
Started Jun 30 06:24:53 PM PDT 24
Finished Jun 30 06:24:55 PM PDT 24
Peak memory 206216 kb
Host smart-9a1fc9f8-2523-41c1-9bc9-956193f2e87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34235
63870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3423563870
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.521445321
Short name T1825
Test name
Test status
Simulation time 174101651 ps
CPU time 0.83 seconds
Started Jun 30 06:24:55 PM PDT 24
Finished Jun 30 06:24:56 PM PDT 24
Peak memory 206208 kb
Host smart-e52bf577-8cee-4fbe-8f3e-8150cabb6817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52144
5321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.521445321
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.1621306511
Short name T2515
Test name
Test status
Simulation time 199981137 ps
CPU time 0.96 seconds
Started Jun 30 06:24:59 PM PDT 24
Finished Jun 30 06:25:01 PM PDT 24
Peak memory 206196 kb
Host smart-b2bac21c-6a53-45f2-a7be-870b202e1862
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1621306511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.1621306511
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.374239891
Short name T1640
Test name
Test status
Simulation time 147819195 ps
CPU time 0.82 seconds
Started Jun 30 06:24:52 PM PDT 24
Finished Jun 30 06:24:53 PM PDT 24
Peak memory 206184 kb
Host smart-4b241d1d-ef79-4344-aba1-b963e2a2e91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37423
9891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.374239891
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.4021681881
Short name T1815
Test name
Test status
Simulation time 74861393 ps
CPU time 0.7 seconds
Started Jun 30 06:24:56 PM PDT 24
Finished Jun 30 06:24:57 PM PDT 24
Peak memory 206208 kb
Host smart-9b2fed39-a12d-4eb4-8fc5-31c237128c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40216
81881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.4021681881
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2390249133
Short name T291
Test name
Test status
Simulation time 23825573968 ps
CPU time 52.45 seconds
Started Jun 30 06:25:04 PM PDT 24
Finished Jun 30 06:25:57 PM PDT 24
Peak memory 206572 kb
Host smart-66e84233-e25a-4fd3-81f5-eaa4fa17da4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23902
49133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2390249133
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2205023273
Short name T2234
Test name
Test status
Simulation time 190158125 ps
CPU time 0.84 seconds
Started Jun 30 06:24:55 PM PDT 24
Finished Jun 30 06:25:01 PM PDT 24
Peak memory 206168 kb
Host smart-e2668252-feb0-4646-9b30-dd3a701ab80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22050
23273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2205023273
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3289365119
Short name T2408
Test name
Test status
Simulation time 190954018 ps
CPU time 0.84 seconds
Started Jun 30 06:24:55 PM PDT 24
Finished Jun 30 06:24:56 PM PDT 24
Peak memory 206196 kb
Host smart-144912ad-93e6-4be4-a71c-6b983237882e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32893
65119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3289365119
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.3722637035
Short name T2506
Test name
Test status
Simulation time 198117103 ps
CPU time 0.82 seconds
Started Jun 30 06:24:55 PM PDT 24
Finished Jun 30 06:24:56 PM PDT 24
Peak memory 206204 kb
Host smart-ecba79c6-a73f-4d7e-8c47-b82e8f02f83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37226
37035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.3722637035
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.39426225
Short name T1924
Test name
Test status
Simulation time 174690442 ps
CPU time 0.79 seconds
Started Jun 30 06:25:05 PM PDT 24
Finished Jun 30 06:25:07 PM PDT 24
Peak memory 206188 kb
Host smart-b312c2e8-b140-482f-b81f-e754f938d6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39426
225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.39426225
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1808053381
Short name T1972
Test name
Test status
Simulation time 138499760 ps
CPU time 0.77 seconds
Started Jun 30 06:25:09 PM PDT 24
Finished Jun 30 06:25:10 PM PDT 24
Peak memory 206292 kb
Host smart-c802f480-02ba-4059-a20d-0dd0b2bc0800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18080
53381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1808053381
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1204895908
Short name T441
Test name
Test status
Simulation time 180432823 ps
CPU time 0.79 seconds
Started Jun 30 06:24:57 PM PDT 24
Finished Jun 30 06:24:58 PM PDT 24
Peak memory 206184 kb
Host smart-2407697c-7dbb-4b7c-ad96-1e63d61d1a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12048
95908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1204895908
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.773500224
Short name T1510
Test name
Test status
Simulation time 160259283 ps
CPU time 0.82 seconds
Started Jun 30 06:25:09 PM PDT 24
Finished Jun 30 06:25:10 PM PDT 24
Peak memory 206360 kb
Host smart-6fd37934-e28d-44fc-bb9c-8fd13ba1c6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77350
0224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.773500224
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.313098412
Short name T1666
Test name
Test status
Simulation time 262939170 ps
CPU time 0.96 seconds
Started Jun 30 06:25:00 PM PDT 24
Finished Jun 30 06:25:02 PM PDT 24
Peak memory 206208 kb
Host smart-7004295e-197b-469c-bc5f-fa818628db60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31309
8412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.313098412
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.2380261867
Short name T953
Test name
Test status
Simulation time 4157260550 ps
CPU time 28.98 seconds
Started Jun 30 06:25:04 PM PDT 24
Finished Jun 30 06:25:34 PM PDT 24
Peak memory 206392 kb
Host smart-862c7247-bed9-4fdc-80c8-101b53433772
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2380261867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.2380261867
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1843429663
Short name T1804
Test name
Test status
Simulation time 182197488 ps
CPU time 0.82 seconds
Started Jun 30 06:25:03 PM PDT 24
Finished Jun 30 06:25:04 PM PDT 24
Peak memory 206200 kb
Host smart-ff8b7706-c5b7-4c5c-b072-615b3c5c8492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18434
29663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1843429663
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1080840070
Short name T834
Test name
Test status
Simulation time 151720203 ps
CPU time 0.77 seconds
Started Jun 30 06:25:05 PM PDT 24
Finished Jun 30 06:25:06 PM PDT 24
Peak memory 206196 kb
Host smart-423cf979-150c-474b-8459-4cb53109372b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10808
40070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1080840070
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.936934275
Short name T2042
Test name
Test status
Simulation time 7059700154 ps
CPU time 195.64 seconds
Started Jun 30 06:25:07 PM PDT 24
Finished Jun 30 06:28:23 PM PDT 24
Peak memory 206436 kb
Host smart-b6ed6d36-ee1c-47b2-9388-021505d0f17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93693
4275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.936934275
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.556708036
Short name T791
Test name
Test status
Simulation time 40608203 ps
CPU time 0.66 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206208 kb
Host smart-df3f99c0-7ec1-493a-abd4-892f147dd085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=556708036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.556708036
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.570138757
Short name T15
Test name
Test status
Simulation time 3714899796 ps
CPU time 4.35 seconds
Started Jun 30 06:25:02 PM PDT 24
Finished Jun 30 06:25:07 PM PDT 24
Peak memory 206224 kb
Host smart-fc244448-592d-46d3-9e39-37f148a42ce9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=570138757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.570138757
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.2729989893
Short name T1347
Test name
Test status
Simulation time 13377376930 ps
CPU time 16.36 seconds
Started Jun 30 06:25:04 PM PDT 24
Finished Jun 30 06:25:20 PM PDT 24
Peak memory 206328 kb
Host smart-8fd9b804-5b52-413b-85f8-1184c35c83e1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2729989893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.2729989893
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.2469793455
Short name T1270
Test name
Test status
Simulation time 23466562758 ps
CPU time 23.73 seconds
Started Jun 30 06:24:58 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206384 kb
Host smart-c8de21c0-dd6b-4eb4-ba66-e30d45c37cbb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2469793455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.2469793455
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2205744094
Short name T661
Test name
Test status
Simulation time 146624726 ps
CPU time 0.82 seconds
Started Jun 30 06:24:58 PM PDT 24
Finished Jun 30 06:24:59 PM PDT 24
Peak memory 206196 kb
Host smart-265cd65e-ee95-4afb-b3ca-30625ea53450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22057
44094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2205744094
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.665857741
Short name T527
Test name
Test status
Simulation time 154253904 ps
CPU time 0.8 seconds
Started Jun 30 06:25:05 PM PDT 24
Finished Jun 30 06:25:06 PM PDT 24
Peak memory 206116 kb
Host smart-98af0550-8106-4031-88bf-17c87d72f20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66585
7741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.665857741
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.164959135
Short name T999
Test name
Test status
Simulation time 480363174 ps
CPU time 1.62 seconds
Started Jun 30 06:24:57 PM PDT 24
Finished Jun 30 06:24:59 PM PDT 24
Peak memory 206192 kb
Host smart-2f4bac61-ff46-4532-823d-4cb03412b293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16495
9135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.164959135
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2570500471
Short name T1732
Test name
Test status
Simulation time 711539031 ps
CPU time 1.67 seconds
Started Jun 30 06:25:07 PM PDT 24
Finished Jun 30 06:25:09 PM PDT 24
Peak memory 206308 kb
Host smart-c6965902-b011-4fe4-91dd-ff44028bcfa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25705
00471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2570500471
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2914714067
Short name T94
Test name
Test status
Simulation time 6880342545 ps
CPU time 13.07 seconds
Started Jun 30 06:25:09 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206232 kb
Host smart-7f2edfcf-d7bf-49a2-b68e-89edce955c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29147
14067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2914714067
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.3555498333
Short name T1244
Test name
Test status
Simulation time 377035090 ps
CPU time 1.21 seconds
Started Jun 30 06:25:05 PM PDT 24
Finished Jun 30 06:25:07 PM PDT 24
Peak memory 206204 kb
Host smart-0772b24e-02eb-42b5-ab81-9981c4f93ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35554
98333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.3555498333
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2310910007
Short name T1377
Test name
Test status
Simulation time 148962001 ps
CPU time 0.8 seconds
Started Jun 30 06:25:05 PM PDT 24
Finished Jun 30 06:25:06 PM PDT 24
Peak memory 206192 kb
Host smart-71e5c726-4cbc-4c4f-9d80-2c8fd0724f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23109
10007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2310910007
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3285879050
Short name T249
Test name
Test status
Simulation time 43578408 ps
CPU time 0.65 seconds
Started Jun 30 06:25:01 PM PDT 24
Finished Jun 30 06:25:02 PM PDT 24
Peak memory 206160 kb
Host smart-25496f81-a504-4bb0-80e8-b31e02420fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32858
79050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3285879050
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.494045984
Short name T2308
Test name
Test status
Simulation time 949915451 ps
CPU time 2.26 seconds
Started Jun 30 06:25:05 PM PDT 24
Finished Jun 30 06:25:08 PM PDT 24
Peak memory 206372 kb
Host smart-12d20317-ee9b-4b45-bc70-fe3e8961cc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49404
5984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.494045984
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2411200699
Short name T564
Test name
Test status
Simulation time 322151529 ps
CPU time 2.06 seconds
Started Jun 30 06:25:12 PM PDT 24
Finished Jun 30 06:25:15 PM PDT 24
Peak memory 206284 kb
Host smart-fd636a23-d0f7-4641-9cff-7450b32572a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24112
00699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2411200699
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1395041988
Short name T1879
Test name
Test status
Simulation time 164212527 ps
CPU time 0.76 seconds
Started Jun 30 06:25:15 PM PDT 24
Finished Jun 30 06:25:16 PM PDT 24
Peak memory 206188 kb
Host smart-b4d6ab7b-7248-4a2d-945f-3796628df960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13950
41988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1395041988
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3577473536
Short name T994
Test name
Test status
Simulation time 151778337 ps
CPU time 0.78 seconds
Started Jun 30 06:25:16 PM PDT 24
Finished Jun 30 06:25:18 PM PDT 24
Peak memory 206204 kb
Host smart-1e48d0d7-3c27-43a6-b440-1006555a79ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35774
73536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3577473536
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2565670816
Short name T884
Test name
Test status
Simulation time 173018200 ps
CPU time 0.86 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206228 kb
Host smart-51ad1a5f-15aa-4694-8603-7a14a52fdde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25656
70816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2565670816
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.145491609
Short name T2405
Test name
Test status
Simulation time 213526946 ps
CPU time 0.99 seconds
Started Jun 30 06:25:12 PM PDT 24
Finished Jun 30 06:25:13 PM PDT 24
Peak memory 206176 kb
Host smart-d248d945-2696-4f08-a5c1-d0fdc844a2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14549
1609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.145491609
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.2660493522
Short name T2255
Test name
Test status
Simulation time 23320629251 ps
CPU time 28.32 seconds
Started Jun 30 06:25:11 PM PDT 24
Finished Jun 30 06:25:40 PM PDT 24
Peak memory 206320 kb
Host smart-a30c2d07-a967-4800-9ad1-42fe262d33d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26604
93522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.2660493522
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1770065532
Short name T773
Test name
Test status
Simulation time 3312288825 ps
CPU time 4.03 seconds
Started Jun 30 06:25:03 PM PDT 24
Finished Jun 30 06:25:08 PM PDT 24
Peak memory 206472 kb
Host smart-d6b4f561-4f4f-43fb-8c98-d18be3999154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17700
65532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1770065532
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2789524053
Short name T709
Test name
Test status
Simulation time 9215076177 ps
CPU time 65.73 seconds
Started Jun 30 06:25:16 PM PDT 24
Finished Jun 30 06:26:23 PM PDT 24
Peak memory 206420 kb
Host smart-70ed0a7b-88c2-457f-84e5-4b72c4243ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27895
24053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2789524053
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2806625872
Short name T1723
Test name
Test status
Simulation time 6246269345 ps
CPU time 44.01 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:26:05 PM PDT 24
Peak memory 206456 kb
Host smart-adf74ed3-a37e-4cac-bcfd-3d1921408e33
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2806625872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2806625872
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1391915157
Short name T3
Test name
Test status
Simulation time 259895411 ps
CPU time 0.93 seconds
Started Jun 30 06:25:13 PM PDT 24
Finished Jun 30 06:25:15 PM PDT 24
Peak memory 206128 kb
Host smart-e4d35676-3536-4792-8e45-d11c55fa61b2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1391915157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1391915157
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.943011443
Short name T1068
Test name
Test status
Simulation time 196181084 ps
CPU time 0.92 seconds
Started Jun 30 06:25:18 PM PDT 24
Finished Jun 30 06:25:20 PM PDT 24
Peak memory 206212 kb
Host smart-060c2179-3f52-45d7-9492-7a6381168bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94301
1443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.943011443
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.3244218793
Short name T1935
Test name
Test status
Simulation time 4742885958 ps
CPU time 45.96 seconds
Started Jun 30 06:25:13 PM PDT 24
Finished Jun 30 06:25:59 PM PDT 24
Peak memory 206448 kb
Host smart-0e6bed24-b396-437e-b5e5-8e8463a895c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32442
18793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.3244218793
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2501126938
Short name T1900
Test name
Test status
Simulation time 3057816945 ps
CPU time 84.41 seconds
Started Jun 30 06:25:11 PM PDT 24
Finished Jun 30 06:26:35 PM PDT 24
Peak memory 206432 kb
Host smart-2bc3267c-dded-44c8-9f17-e5332000f0d0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2501126938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2501126938
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.3635804899
Short name T919
Test name
Test status
Simulation time 151983461 ps
CPU time 0.82 seconds
Started Jun 30 06:25:12 PM PDT 24
Finished Jun 30 06:25:14 PM PDT 24
Peak memory 206192 kb
Host smart-81aea7c0-6d30-4166-8da5-09f45d717727
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3635804899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.3635804899
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.607901219
Short name T329
Test name
Test status
Simulation time 147444818 ps
CPU time 0.77 seconds
Started Jun 30 06:25:05 PM PDT 24
Finished Jun 30 06:25:07 PM PDT 24
Peak memory 206212 kb
Host smart-c1664752-8a00-4289-a05e-3799057a714d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60790
1219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.607901219
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1690990040
Short name T133
Test name
Test status
Simulation time 189047706 ps
CPU time 0.83 seconds
Started Jun 30 06:25:09 PM PDT 24
Finished Jun 30 06:25:16 PM PDT 24
Peak memory 206188 kb
Host smart-605923e1-e517-48b8-aee0-aa0dd52fba99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16909
90040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1690990040
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1094063831
Short name T1521
Test name
Test status
Simulation time 154189477 ps
CPU time 0.79 seconds
Started Jun 30 06:25:17 PM PDT 24
Finished Jun 30 06:25:19 PM PDT 24
Peak memory 206220 kb
Host smart-4cf7913b-cd0e-4b94-af65-fa480aeb5658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10940
63831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1094063831
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2883695772
Short name T2612
Test name
Test status
Simulation time 148530051 ps
CPU time 0.82 seconds
Started Jun 30 06:25:13 PM PDT 24
Finished Jun 30 06:25:14 PM PDT 24
Peak memory 206192 kb
Host smart-7e7af9a8-9a19-4d5b-9487-acf7edd23ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28836
95772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2883695772
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2835099691
Short name T1981
Test name
Test status
Simulation time 176917801 ps
CPU time 0.77 seconds
Started Jun 30 06:25:08 PM PDT 24
Finished Jun 30 06:25:09 PM PDT 24
Peak memory 206212 kb
Host smart-21fe9fed-981f-4bd6-a7d9-49d63e82a7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28350
99691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2835099691
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1682957784
Short name T2362
Test name
Test status
Simulation time 158589703 ps
CPU time 0.8 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:25:34 PM PDT 24
Peak memory 206196 kb
Host smart-643c3426-b22b-422b-be87-5574be586837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16829
57784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1682957784
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.113555887
Short name T479
Test name
Test status
Simulation time 266906811 ps
CPU time 0.96 seconds
Started Jun 30 06:25:11 PM PDT 24
Finished Jun 30 06:25:12 PM PDT 24
Peak memory 206208 kb
Host smart-263a9c26-7da6-4c5c-94db-6508f448ef24
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=113555887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.113555887
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.688487176
Short name T2209
Test name
Test status
Simulation time 145399510 ps
CPU time 0.77 seconds
Started Jun 30 06:25:15 PM PDT 24
Finished Jun 30 06:25:16 PM PDT 24
Peak memory 206204 kb
Host smart-dd4bce98-c0bb-42ff-bbad-287bb7de7552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68848
7176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.688487176
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2389779947
Short name T935
Test name
Test status
Simulation time 46278731 ps
CPU time 0.65 seconds
Started Jun 30 06:25:11 PM PDT 24
Finished Jun 30 06:25:12 PM PDT 24
Peak memory 206172 kb
Host smart-452d8036-e254-491d-b9f7-d7024a0cb533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23897
79947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2389779947
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3111078310
Short name T1308
Test name
Test status
Simulation time 9540846435 ps
CPU time 22.67 seconds
Started Jun 30 06:25:12 PM PDT 24
Finished Jun 30 06:25:35 PM PDT 24
Peak memory 206396 kb
Host smart-14ce4fee-ef39-4275-8a47-c9e8f608a5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31110
78310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3111078310
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1946542671
Short name T2346
Test name
Test status
Simulation time 210263993 ps
CPU time 0.88 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:21 PM PDT 24
Peak memory 206192 kb
Host smart-9ce3e4bd-cefa-4c9b-bd7b-b2adbae0e929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19465
42671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1946542671
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3550750821
Short name T1477
Test name
Test status
Simulation time 177668418 ps
CPU time 0.84 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:31 PM PDT 24
Peak memory 206196 kb
Host smart-b60e0411-841a-4cd3-a597-8a6e17441cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35507
50821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3550750821
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3147048416
Short name T1350
Test name
Test status
Simulation time 180463661 ps
CPU time 0.86 seconds
Started Jun 30 06:25:11 PM PDT 24
Finished Jun 30 06:25:13 PM PDT 24
Peak memory 206208 kb
Host smart-ec819466-840b-4ec8-885a-edf4e15c07c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31470
48416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3147048416
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.3642620250
Short name T981
Test name
Test status
Simulation time 218856210 ps
CPU time 0.89 seconds
Started Jun 30 06:25:17 PM PDT 24
Finished Jun 30 06:25:19 PM PDT 24
Peak memory 206188 kb
Host smart-303f5b3b-9a22-4bb7-8bde-6d9421c6f27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36426
20250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.3642620250
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.904202836
Short name T1536
Test name
Test status
Simulation time 192416958 ps
CPU time 0.81 seconds
Started Jun 30 06:25:14 PM PDT 24
Finished Jun 30 06:25:15 PM PDT 24
Peak memory 206200 kb
Host smart-f05f721e-f141-45bf-8fee-d0c06ab47192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90420
2836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.904202836
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2136039478
Short name T1222
Test name
Test status
Simulation time 156879225 ps
CPU time 0.74 seconds
Started Jun 30 06:25:16 PM PDT 24
Finished Jun 30 06:25:17 PM PDT 24
Peak memory 206168 kb
Host smart-0a8f289a-a12b-476e-ad86-0b3a9b85a8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21360
39478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2136039478
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3229310761
Short name T2376
Test name
Test status
Simulation time 152410566 ps
CPU time 0.81 seconds
Started Jun 30 06:25:27 PM PDT 24
Finished Jun 30 06:25:31 PM PDT 24
Peak memory 206172 kb
Host smart-86bca201-3a54-42df-98b3-02f96b88dd5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32293
10761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3229310761
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3609632609
Short name T146
Test name
Test status
Simulation time 273164126 ps
CPU time 0.98 seconds
Started Jun 30 06:25:11 PM PDT 24
Finished Jun 30 06:25:13 PM PDT 24
Peak memory 206212 kb
Host smart-b47a9491-8545-41f8-9c41-c56a91581450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36096
32609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3609632609
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.19770668
Short name T2231
Test name
Test status
Simulation time 4778829363 ps
CPU time 43.34 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:26:06 PM PDT 24
Peak memory 206440 kb
Host smart-df8c3043-5a77-43b3-a4f9-7cd5a1896838
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=19770668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.19770668
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3769887403
Short name T1153
Test name
Test status
Simulation time 146363275 ps
CPU time 0.77 seconds
Started Jun 30 06:25:14 PM PDT 24
Finished Jun 30 06:25:15 PM PDT 24
Peak memory 206180 kb
Host smart-e8da1579-2531-48ed-bde5-a74897f820eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37698
87403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3769887403
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.761623851
Short name T1225
Test name
Test status
Simulation time 162286881 ps
CPU time 0.77 seconds
Started Jun 30 06:25:13 PM PDT 24
Finished Jun 30 06:25:15 PM PDT 24
Peak memory 206188 kb
Host smart-18eb1391-f8b6-42c4-8dd3-ae4eaa8cfefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76162
3851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.761623851
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1976610072
Short name T1065
Test name
Test status
Simulation time 6576083390 ps
CPU time 184.23 seconds
Started Jun 30 06:25:12 PM PDT 24
Finished Jun 30 06:28:17 PM PDT 24
Peak memory 206424 kb
Host smart-62a1ba5f-511e-4d80-a711-4bff7f5e943e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19766
10072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1976610072
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.1366088102
Short name T1940
Test name
Test status
Simulation time 40714739 ps
CPU time 0.71 seconds
Started Jun 30 06:25:17 PM PDT 24
Finished Jun 30 06:25:19 PM PDT 24
Peak memory 206196 kb
Host smart-a9757801-3384-447d-b028-f8aa564fa2f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1366088102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.1366088102
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3013458831
Short name T14
Test name
Test status
Simulation time 4266511023 ps
CPU time 5.49 seconds
Started Jun 30 06:25:08 PM PDT 24
Finished Jun 30 06:25:14 PM PDT 24
Peak memory 206364 kb
Host smart-a02d30b0-20e4-439a-90df-48b401527c44
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3013458831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.3013458831
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1689699256
Short name T1038
Test name
Test status
Simulation time 13327675580 ps
CPU time 14.27 seconds
Started Jun 30 06:25:16 PM PDT 24
Finished Jun 30 06:25:31 PM PDT 24
Peak memory 206316 kb
Host smart-716fc6de-5e94-4f5f-91f6-9cbbd158da22
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1689699256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1689699256
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.295476770
Short name T2091
Test name
Test status
Simulation time 23431544403 ps
CPU time 22.91 seconds
Started Jun 30 06:25:13 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206260 kb
Host smart-e6a58995-2c3a-46f5-ac77-d8edc11a85ea
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=295476770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.295476770
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1356357062
Short name T500
Test name
Test status
Simulation time 161052848 ps
CPU time 0.83 seconds
Started Jun 30 06:25:12 PM PDT 24
Finished Jun 30 06:25:14 PM PDT 24
Peak memory 206200 kb
Host smart-21030f89-a88f-4ad5-a744-be194cd32d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13563
57062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1356357062
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.981849133
Short name T523
Test name
Test status
Simulation time 141111246 ps
CPU time 0.77 seconds
Started Jun 30 06:25:12 PM PDT 24
Finished Jun 30 06:25:14 PM PDT 24
Peak memory 206172 kb
Host smart-41cec204-ba47-47b1-9b6e-0c422e4992b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98184
9133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.981849133
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.1890513802
Short name T892
Test name
Test status
Simulation time 234969243 ps
CPU time 0.93 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:26 PM PDT 24
Peak memory 206192 kb
Host smart-8186fd73-4e5c-4c89-9e68-176ea1ebb825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18905
13802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1890513802
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1295700156
Short name T2237
Test name
Test status
Simulation time 1016092680 ps
CPU time 2.33 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:23 PM PDT 24
Peak memory 206168 kb
Host smart-b8368ac0-8a1a-461a-aff9-5991ec961952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12957
00156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1295700156
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3475838007
Short name T172
Test name
Test status
Simulation time 11303838632 ps
CPU time 20.84 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:40 PM PDT 24
Peak memory 206488 kb
Host smart-b0afc9e2-84ae-4f97-95c6-47f6e7a3d463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34758
38007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3475838007
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.675471077
Short name T1582
Test name
Test status
Simulation time 391197271 ps
CPU time 1.16 seconds
Started Jun 30 06:25:22 PM PDT 24
Finished Jun 30 06:25:25 PM PDT 24
Peak memory 206008 kb
Host smart-45c06f4d-80d4-4ff0-af37-d68cd8c23e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67547
1077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.675471077
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.836362923
Short name T2466
Test name
Test status
Simulation time 135846345 ps
CPU time 0.8 seconds
Started Jun 30 06:25:16 PM PDT 24
Finished Jun 30 06:25:17 PM PDT 24
Peak memory 206184 kb
Host smart-43369f64-0a65-4ab1-9657-3a081201a4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83636
2923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.836362923
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3290484647
Short name T1461
Test name
Test status
Simulation time 74330486 ps
CPU time 0.68 seconds
Started Jun 30 06:25:21 PM PDT 24
Finished Jun 30 06:25:24 PM PDT 24
Peak memory 206028 kb
Host smart-a04b825b-ceea-431e-8bf0-969611a93198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32904
84647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3290484647
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2036665085
Short name T444
Test name
Test status
Simulation time 915191718 ps
CPU time 2.3 seconds
Started Jun 30 06:25:29 PM PDT 24
Finished Jun 30 06:25:34 PM PDT 24
Peak memory 206292 kb
Host smart-ec86fbe8-53ad-4d7f-b744-16892a7dd1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20366
65085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2036665085
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.12465064
Short name T1271
Test name
Test status
Simulation time 301425227 ps
CPU time 2.19 seconds
Started Jun 30 06:25:21 PM PDT 24
Finished Jun 30 06:25:25 PM PDT 24
Peak memory 206276 kb
Host smart-44842619-5f41-4215-9d4e-b12f44e42204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12465
064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.12465064
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2829928468
Short name T553
Test name
Test status
Simulation time 210151275 ps
CPU time 0.92 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:31 PM PDT 24
Peak memory 206168 kb
Host smart-2f75031c-84f6-410d-ba64-19b8eb652002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28299
28468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2829928468
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.4154254970
Short name T2417
Test name
Test status
Simulation time 142428574 ps
CPU time 0.79 seconds
Started Jun 30 06:25:22 PM PDT 24
Finished Jun 30 06:25:24 PM PDT 24
Peak memory 206048 kb
Host smart-f6a53aaf-bdea-4526-b244-823e95be3492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41542
54970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.4154254970
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1577862760
Short name T1545
Test name
Test status
Simulation time 204049377 ps
CPU time 0.93 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206188 kb
Host smart-99f15aa0-1e34-49a9-84b3-a6b52beac90f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15778
62760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1577862760
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1428388801
Short name T2144
Test name
Test status
Simulation time 176688088 ps
CPU time 0.8 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206144 kb
Host smart-643a551a-420f-43f7-b849-01a04173107e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14283
88801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1428388801
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.4205637087
Short name T1315
Test name
Test status
Simulation time 23362608140 ps
CPU time 21.38 seconds
Started Jun 30 06:25:27 PM PDT 24
Finished Jun 30 06:25:51 PM PDT 24
Peak memory 206308 kb
Host smart-695214a4-2550-4d1c-9933-ef573423e871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42056
37087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.4205637087
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.3249134304
Short name T1302
Test name
Test status
Simulation time 3335384179 ps
CPU time 3.89 seconds
Started Jun 30 06:25:21 PM PDT 24
Finished Jun 30 06:25:27 PM PDT 24
Peak memory 206212 kb
Host smart-c44f309a-753e-4fc6-89f5-5d7b37a22a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32491
34304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3249134304
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.3435594960
Short name T1652
Test name
Test status
Simulation time 8302497295 ps
CPU time 228.61 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:29:09 PM PDT 24
Peak memory 206460 kb
Host smart-5dfa925f-1be0-40b1-a9ee-a8d74c3c83da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34355
94960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.3435594960
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.4161450300
Short name T879
Test name
Test status
Simulation time 2990293101 ps
CPU time 27.69 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:26:02 PM PDT 24
Peak memory 206496 kb
Host smart-04a25c07-9232-4f5b-b111-262bf657b430
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4161450300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.4161450300
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2256876732
Short name T1512
Test name
Test status
Simulation time 251426635 ps
CPU time 0.97 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206192 kb
Host smart-4a474a05-c340-4a0c-bbd9-9b0273c372e3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2256876732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2256876732
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1870434597
Short name T1534
Test name
Test status
Simulation time 202444377 ps
CPU time 0.88 seconds
Started Jun 30 06:25:18 PM PDT 24
Finished Jun 30 06:25:20 PM PDT 24
Peak memory 206360 kb
Host smart-6ddeb7ca-c4e2-45e6-aec4-0287b9db69b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18704
34597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1870434597
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.3974086028
Short name T2355
Test name
Test status
Simulation time 4683591690 ps
CPU time 46.52 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:26:21 PM PDT 24
Peak memory 206424 kb
Host smart-386171bb-4a24-4162-8d34-3e2b406cf4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39740
86028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.3974086028
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.1043173976
Short name T1031
Test name
Test status
Simulation time 4239517261 ps
CPU time 30.85 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:52 PM PDT 24
Peak memory 206460 kb
Host smart-1dd84880-4917-4ee2-813e-4df43517d409
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1043173976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1043173976
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.291932232
Short name T1327
Test name
Test status
Simulation time 163612709 ps
CPU time 0.85 seconds
Started Jun 30 06:25:13 PM PDT 24
Finished Jun 30 06:25:15 PM PDT 24
Peak memory 206212 kb
Host smart-fca490d0-86f7-456e-b7a5-bbc7bbce0c6a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=291932232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.291932232
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1602728230
Short name T2456
Test name
Test status
Simulation time 179462072 ps
CPU time 0.79 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206128 kb
Host smart-ca8a3a1b-5a7f-4d4d-b693-d6cca49b00d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16027
28230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1602728230
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2406604141
Short name T126
Test name
Test status
Simulation time 203759236 ps
CPU time 0.82 seconds
Started Jun 30 06:25:22 PM PDT 24
Finished Jun 30 06:25:24 PM PDT 24
Peak memory 206196 kb
Host smart-d95129f0-e1d3-4c15-8451-e4e723520f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24066
04141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2406604141
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.2369847834
Short name T1277
Test name
Test status
Simulation time 150230755 ps
CPU time 0.79 seconds
Started Jun 30 06:25:17 PM PDT 24
Finished Jun 30 06:25:18 PM PDT 24
Peak memory 205724 kb
Host smart-bdca7772-785c-4343-895a-1c617d27a00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23698
47834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2369847834
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1959019601
Short name T2495
Test name
Test status
Simulation time 175417305 ps
CPU time 0.83 seconds
Started Jun 30 06:25:27 PM PDT 24
Finished Jun 30 06:25:31 PM PDT 24
Peak memory 206168 kb
Host smart-6a6155e7-afb6-445f-b36c-d1d2bd69ebcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19590
19601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1959019601
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1880593016
Short name T1149
Test name
Test status
Simulation time 221901923 ps
CPU time 0.86 seconds
Started Jun 30 06:25:30 PM PDT 24
Finished Jun 30 06:25:34 PM PDT 24
Peak memory 206200 kb
Host smart-302cea0b-76a2-4bcd-9be7-b5e98f183297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18805
93016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1880593016
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3808974613
Short name T799
Test name
Test status
Simulation time 158832858 ps
CPU time 0.82 seconds
Started Jun 30 06:25:17 PM PDT 24
Finished Jun 30 06:25:18 PM PDT 24
Peak memory 205836 kb
Host smart-53716c03-d2ba-456f-98b2-b3b50698fe83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38089
74613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3808974613
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.3661300849
Short name T449
Test name
Test status
Simulation time 232600635 ps
CPU time 0.97 seconds
Started Jun 30 06:25:16 PM PDT 24
Finished Jun 30 06:25:18 PM PDT 24
Peak memory 206208 kb
Host smart-2b0b3013-ffbc-4f52-a150-a91438489327
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3661300849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.3661300849
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2230985635
Short name T2262
Test name
Test status
Simulation time 147256214 ps
CPU time 0.76 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206176 kb
Host smart-33fd41b1-b12c-4c4e-9fbe-ce982171ab1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22309
85635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2230985635
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2997245843
Short name T2333
Test name
Test status
Simulation time 58499928 ps
CPU time 0.65 seconds
Started Jun 30 06:25:18 PM PDT 24
Finished Jun 30 06:25:20 PM PDT 24
Peak memory 206204 kb
Host smart-f9836951-6173-47e9-ab96-4a8ab2f40b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29972
45843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2997245843
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3359836030
Short name T266
Test name
Test status
Simulation time 15368765713 ps
CPU time 32.31 seconds
Started Jun 30 06:25:21 PM PDT 24
Finished Jun 30 06:25:55 PM PDT 24
Peak memory 206436 kb
Host smart-ec6d7cae-64cf-467f-bfcf-593a4f3d2901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33598
36030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3359836030
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.421298450
Short name T2217
Test name
Test status
Simulation time 219338238 ps
CPU time 0.86 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206204 kb
Host smart-5a309cde-ea0d-4fb4-86f7-7ad85d72b409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42129
8450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.421298450
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1901731818
Short name T1092
Test name
Test status
Simulation time 220112122 ps
CPU time 0.87 seconds
Started Jun 30 06:25:23 PM PDT 24
Finished Jun 30 06:25:26 PM PDT 24
Peak memory 206360 kb
Host smart-7d9a2d23-1075-4a09-a5a6-e8c9daa90dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19017
31818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1901731818
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3861114423
Short name T2586
Test name
Test status
Simulation time 157385870 ps
CPU time 0.8 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:23 PM PDT 24
Peak memory 206200 kb
Host smart-469c82ce-cbe2-4593-9fcf-645bd52baac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38611
14423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3861114423
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.308605990
Short name T69
Test name
Test status
Simulation time 138022123 ps
CPU time 0.74 seconds
Started Jun 30 06:25:21 PM PDT 24
Finished Jun 30 06:25:24 PM PDT 24
Peak memory 206124 kb
Host smart-c0363507-6c13-4466-b995-5669e70b82dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30860
5990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.308605990
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1297203015
Short name T961
Test name
Test status
Simulation time 156292481 ps
CPU time 0.82 seconds
Started Jun 30 06:25:22 PM PDT 24
Finished Jun 30 06:25:24 PM PDT 24
Peak memory 206168 kb
Host smart-c24160da-52c4-4d1b-8d81-407732bfca44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12972
03015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1297203015
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1254355414
Short name T1818
Test name
Test status
Simulation time 151324961 ps
CPU time 0.82 seconds
Started Jun 30 06:25:13 PM PDT 24
Finished Jun 30 06:25:15 PM PDT 24
Peak memory 206172 kb
Host smart-79b215ed-8eb9-44eb-80ae-090b109ce36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12543
55414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1254355414
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2482970593
Short name T1793
Test name
Test status
Simulation time 202357010 ps
CPU time 0.91 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:23 PM PDT 24
Peak memory 206204 kb
Host smart-559c84c1-efdf-4ded-8b7f-8a58cd67edcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24829
70593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2482970593
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1722179721
Short name T456
Test name
Test status
Simulation time 3758844238 ps
CPU time 107.71 seconds
Started Jun 30 06:25:18 PM PDT 24
Finished Jun 30 06:27:07 PM PDT 24
Peak memory 206484 kb
Host smart-30842e79-495f-4047-a40c-1205506aa535
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1722179721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1722179721
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3417220038
Short name T1367
Test name
Test status
Simulation time 192287130 ps
CPU time 0.81 seconds
Started Jun 30 06:25:18 PM PDT 24
Finished Jun 30 06:25:20 PM PDT 24
Peak memory 206052 kb
Host smart-be87a389-940e-4d35-a233-97835dca617a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34172
20038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3417220038
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3010599008
Short name T331
Test name
Test status
Simulation time 155742504 ps
CPU time 0.75 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206028 kb
Host smart-67b45556-5a07-4aa3-970d-bbf8763c2a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30105
99008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3010599008
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.4175314371
Short name T2228
Test name
Test status
Simulation time 4397972161 ps
CPU time 123.29 seconds
Started Jun 30 06:25:16 PM PDT 24
Finished Jun 30 06:27:20 PM PDT 24
Peak memory 206408 kb
Host smart-1730067c-1106-4916-af21-8a4c75669bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41753
14371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.4175314371
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.3448734609
Short name T1088
Test name
Test status
Simulation time 44810196 ps
CPU time 0.68 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206184 kb
Host smart-009b8132-1df8-4e70-ba61-455054bcdd61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3448734609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.3448734609
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3951384
Short name T663
Test name
Test status
Simulation time 4050423595 ps
CPU time 4.75 seconds
Started Jun 30 06:25:22 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206276 kb
Host smart-b2106fb2-137e-46b5-b5ca-b5da13b7dd3f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3951384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.3951384
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3923153174
Short name T2448
Test name
Test status
Simulation time 13334596321 ps
CPU time 11.58 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206376 kb
Host smart-37a01853-bae7-49f6-8382-c40275e9198d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3923153174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3923153174
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3426022946
Short name T1620
Test name
Test status
Simulation time 23386810832 ps
CPU time 22.9 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:51 PM PDT 24
Peak memory 206316 kb
Host smart-d68c8125-4f5c-457c-a65e-094915fad91f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3426022946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3426022946
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1381435260
Short name T546
Test name
Test status
Simulation time 208456857 ps
CPU time 0.84 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206192 kb
Host smart-d504a03f-23f1-43f0-bb51-a8dc488c525e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13814
35260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1381435260
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1354419086
Short name T915
Test name
Test status
Simulation time 147051827 ps
CPU time 0.85 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:21 PM PDT 24
Peak memory 206192 kb
Host smart-6415d6f8-efeb-44b3-b0b2-87ac4e98ef55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13544
19086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1354419086
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3017286104
Short name T2137
Test name
Test status
Simulation time 261542501 ps
CPU time 1.12 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206168 kb
Host smart-9abaae07-4da6-4646-a182-19290ec4de7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30172
86104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3017286104
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2674569885
Short name T166
Test name
Test status
Simulation time 1414215126 ps
CPU time 3.24 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:25 PM PDT 24
Peak memory 206328 kb
Host smart-ec1b5efe-b4ae-41d2-ac94-de68b7cac67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26745
69885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2674569885
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2307210781
Short name T2578
Test name
Test status
Simulation time 22415479595 ps
CPU time 41.28 seconds
Started Jun 30 06:25:22 PM PDT 24
Finished Jun 30 06:26:05 PM PDT 24
Peak memory 206396 kb
Host smart-04190dd9-4482-4bbe-979f-47c409e79f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23072
10781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2307210781
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2932616290
Short name T354
Test name
Test status
Simulation time 459231949 ps
CPU time 1.49 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:29 PM PDT 24
Peak memory 206136 kb
Host smart-eb50b74c-c2a6-4533-9570-9f3ff6e5210d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29326
16290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2932616290
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.774359170
Short name T2268
Test name
Test status
Simulation time 146158403 ps
CPU time 0.78 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206012 kb
Host smart-50f66ff0-3978-413f-9411-6fae82d717b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77435
9170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.774359170
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.4208622543
Short name T1196
Test name
Test status
Simulation time 26556153 ps
CPU time 0.67 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:21 PM PDT 24
Peak memory 206168 kb
Host smart-d478209d-a04a-4336-9231-6276d2558d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42086
22543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.4208622543
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3246708890
Short name T352
Test name
Test status
Simulation time 877468842 ps
CPU time 2.01 seconds
Started Jun 30 06:25:30 PM PDT 24
Finished Jun 30 06:25:35 PM PDT 24
Peak memory 206368 kb
Host smart-fce1f4bd-72fc-4a74-8107-669cfef5e0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32467
08890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3246708890
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3280018657
Short name T2071
Test name
Test status
Simulation time 217551104 ps
CPU time 1.32 seconds
Started Jun 30 06:25:13 PM PDT 24
Finished Jun 30 06:25:15 PM PDT 24
Peak memory 206324 kb
Host smart-49110a1f-d103-43fb-85c9-f7a62cd63ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32800
18657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3280018657
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.968136841
Short name T1713
Test name
Test status
Simulation time 266916569 ps
CPU time 0.88 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206048 kb
Host smart-e540fd2d-a0ca-459b-871d-eaf34c6e38a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96813
6841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.968136841
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2433060585
Short name T579
Test name
Test status
Simulation time 216531744 ps
CPU time 0.87 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:21 PM PDT 24
Peak memory 206196 kb
Host smart-76fb30fa-d29a-4072-a2c5-33859132b190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24330
60585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2433060585
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3238551775
Short name T1255
Test name
Test status
Simulation time 244795934 ps
CPU time 0.95 seconds
Started Jun 30 06:25:23 PM PDT 24
Finished Jun 30 06:25:26 PM PDT 24
Peak memory 206188 kb
Host smart-6c56706d-0598-4714-b5e4-ed9780350235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32385
51775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3238551775
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.857463928
Short name T1979
Test name
Test status
Simulation time 158659636 ps
CPU time 0.79 seconds
Started Jun 30 06:25:22 PM PDT 24
Finished Jun 30 06:25:25 PM PDT 24
Peak memory 206188 kb
Host smart-e24077a6-f588-46cb-a27b-d5c9e180863c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85746
3928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.857463928
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1786727275
Short name T594
Test name
Test status
Simulation time 23322841555 ps
CPU time 23.1 seconds
Started Jun 30 06:25:15 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206308 kb
Host smart-c990d1e8-1c35-46e3-87ee-cb3320452074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17867
27275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1786727275
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2291081963
Short name T1370
Test name
Test status
Simulation time 3262977187 ps
CPU time 4.13 seconds
Started Jun 30 06:25:18 PM PDT 24
Finished Jun 30 06:25:23 PM PDT 24
Peak memory 206232 kb
Host smart-fc9e166e-0610-4a38-bf0c-9df4934e1a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22910
81963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2291081963
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.3212871064
Short name T1221
Test name
Test status
Simulation time 9087259864 ps
CPU time 256.61 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:29:45 PM PDT 24
Peak memory 206476 kb
Host smart-6414085f-a003-4d9d-9816-0714ebbd03c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32128
71064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.3212871064
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.2056644093
Short name T248
Test name
Test status
Simulation time 4121071867 ps
CPU time 36.45 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:57 PM PDT 24
Peak memory 206400 kb
Host smart-54956e2e-d110-49c2-b24f-f945cbd4bb42
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2056644093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.2056644093
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2585867537
Short name T630
Test name
Test status
Simulation time 241766036 ps
CPU time 0.93 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:26 PM PDT 24
Peak memory 206216 kb
Host smart-3c7482ba-8375-47cf-a6b0-56ccabefe20d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2585867537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2585867537
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2598703989
Short name T1328
Test name
Test status
Simulation time 182312373 ps
CPU time 0.84 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206156 kb
Host smart-7891d308-b103-45fa-8d5e-a3dae74a8b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25987
03989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2598703989
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.211326536
Short name T1556
Test name
Test status
Simulation time 6332075750 ps
CPU time 48.07 seconds
Started Jun 30 06:25:17 PM PDT 24
Finished Jun 30 06:26:06 PM PDT 24
Peak memory 206456 kb
Host smart-0644ce8b-ff03-4f3b-8fbd-f5976a5dacb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21132
6536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.211326536
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1625762733
Short name T1318
Test name
Test status
Simulation time 3047350238 ps
CPU time 85.47 seconds
Started Jun 30 06:25:14 PM PDT 24
Finished Jun 30 06:26:40 PM PDT 24
Peak memory 206444 kb
Host smart-c64b5656-55c6-4b5a-af36-3a33c7928fa2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1625762733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1625762733
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1039730026
Short name T336
Test name
Test status
Simulation time 145740488 ps
CPU time 0.79 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206048 kb
Host smart-ca7aa6d3-d962-48d2-9874-79baa0319319
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1039730026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1039730026
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1942695250
Short name T2266
Test name
Test status
Simulation time 234335345 ps
CPU time 0.79 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:29 PM PDT 24
Peak memory 206200 kb
Host smart-1a7b93e0-0666-4167-b3af-7fc2f3fd9801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19426
95250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1942695250
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1728904166
Short name T2011
Test name
Test status
Simulation time 243102002 ps
CPU time 0.88 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:29 PM PDT 24
Peak memory 206200 kb
Host smart-85569681-d693-46b5-b759-0ebd15930329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17289
04166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1728904166
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3460047130
Short name T846
Test name
Test status
Simulation time 160373190 ps
CPU time 0.8 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:29 PM PDT 24
Peak memory 206164 kb
Host smart-caf339dd-3ff9-442c-9c5c-5c574fa84d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34600
47130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3460047130
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3470113166
Short name T1066
Test name
Test status
Simulation time 161281119 ps
CPU time 0.8 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206012 kb
Host smart-3b1aacde-334d-469e-92c9-14f8593dc368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34701
13166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3470113166
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2610195321
Short name T481
Test name
Test status
Simulation time 248977950 ps
CPU time 0.87 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206212 kb
Host smart-2e44e910-fa0d-4b44-82fb-acb88c597a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26101
95321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2610195321
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1263052150
Short name T2576
Test name
Test status
Simulation time 174021975 ps
CPU time 0.86 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206176 kb
Host smart-82c64d89-efa7-4709-b727-7b7eea6ad075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12630
52150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1263052150
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2733425040
Short name T1486
Test name
Test status
Simulation time 282425881 ps
CPU time 0.99 seconds
Started Jun 30 06:25:29 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206188 kb
Host smart-d6376f95-d1ac-4b59-94ee-64162d92c8c6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2733425040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2733425040
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.44505752
Short name T603
Test name
Test status
Simulation time 163418301 ps
CPU time 0.76 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206204 kb
Host smart-60b9aedf-654d-4f21-b604-737162f0f76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44505
752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.44505752
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2851213310
Short name T2
Test name
Test status
Simulation time 34300226 ps
CPU time 0.64 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:27 PM PDT 24
Peak memory 206200 kb
Host smart-c067f13f-1b8c-442b-b5e8-cc5110c65bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28512
13310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2851213310
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.4182709547
Short name T2022
Test name
Test status
Simulation time 20230305473 ps
CPU time 47.11 seconds
Started Jun 30 06:25:23 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206492 kb
Host smart-c1aeebe8-b789-4b2b-af22-8e3e59599b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41827
09547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.4182709547
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2116711288
Short name T1560
Test name
Test status
Simulation time 230568713 ps
CPU time 0.89 seconds
Started Jun 30 06:25:21 PM PDT 24
Finished Jun 30 06:25:24 PM PDT 24
Peak memory 206168 kb
Host smart-ec603c18-85a2-4dba-a204-11c1c3005f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21167
11288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2116711288
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1433503600
Short name T1532
Test name
Test status
Simulation time 181329413 ps
CPU time 0.8 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:23 PM PDT 24
Peak memory 206232 kb
Host smart-b1f38bef-8195-4add-ab47-35d17b0eb2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14335
03600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1433503600
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.548823106
Short name T693
Test name
Test status
Simulation time 174913476 ps
CPU time 0.8 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:31 PM PDT 24
Peak memory 206184 kb
Host smart-d016f3d6-8e9c-4969-9f99-025218e877da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54882
3106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.548823106
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.170567553
Short name T2593
Test name
Test status
Simulation time 158658870 ps
CPU time 0.83 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:29 PM PDT 24
Peak memory 206192 kb
Host smart-9e77e911-0273-4400-97ee-844e3d9a2457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17056
7553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.170567553
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2846506165
Short name T726
Test name
Test status
Simulation time 163257386 ps
CPU time 0.76 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206192 kb
Host smart-627e705b-22c3-4cf9-972e-1431239a7133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28465
06165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2846506165
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.127678760
Short name T1172
Test name
Test status
Simulation time 159700943 ps
CPU time 0.76 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:29 PM PDT 24
Peak memory 206192 kb
Host smart-9e36682d-c973-4d7c-a083-18458be87736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12767
8760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.127678760
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.4252326086
Short name T1668
Test name
Test status
Simulation time 153207954 ps
CPU time 0.76 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:25:34 PM PDT 24
Peak memory 206184 kb
Host smart-9b33f0de-85d6-454b-af21-386dedfe10d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42523
26086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.4252326086
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.217845969
Short name T1550
Test name
Test status
Simulation time 246486056 ps
CPU time 0.93 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206204 kb
Host smart-3f478378-4258-4d7e-b5a7-d1272d67d580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21784
5969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.217845969
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.4061580271
Short name T468
Test name
Test status
Simulation time 6747558045 ps
CPU time 46.43 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206432 kb
Host smart-31b83a43-bf20-4cfb-b5d1-86fd9f4e45d1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4061580271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.4061580271
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.602205855
Short name T2534
Test name
Test status
Simulation time 159403026 ps
CPU time 0.77 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:25:35 PM PDT 24
Peak memory 206204 kb
Host smart-ba43db31-0f56-454f-84c8-ae4125c760a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60220
5855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.602205855
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2010623786
Short name T920
Test name
Test status
Simulation time 190374156 ps
CPU time 0.81 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206196 kb
Host smart-fccb3ae2-6ff3-4e99-a746-73d401276b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20106
23786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2010623786
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.3945497404
Short name T906
Test name
Test status
Simulation time 4284128585 ps
CPU time 39.51 seconds
Started Jun 30 06:25:13 PM PDT 24
Finished Jun 30 06:25:53 PM PDT 24
Peak memory 206380 kb
Host smart-568512e5-9ecc-4bae-ba3c-beebae4b85de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39454
97404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3945497404
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2051164736
Short name T1601
Test name
Test status
Simulation time 41332806 ps
CPU time 0.66 seconds
Started Jun 30 06:25:27 PM PDT 24
Finished Jun 30 06:25:31 PM PDT 24
Peak memory 206216 kb
Host smart-cb59a3aa-0363-423c-86f2-ecd36e90eddf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2051164736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2051164736
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1068021555
Short name T210
Test name
Test status
Simulation time 3737773961 ps
CPU time 4.14 seconds
Started Jun 30 06:25:35 PM PDT 24
Finished Jun 30 06:25:42 PM PDT 24
Peak memory 206348 kb
Host smart-6f854177-b613-46df-a43a-bd7455cd5895
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1068021555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1068021555
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1664562927
Short name T2322
Test name
Test status
Simulation time 13487084790 ps
CPU time 14.05 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206416 kb
Host smart-fa61dd28-5176-42f6-ac7d-a39df8057081
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1664562927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1664562927
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.852222043
Short name T626
Test name
Test status
Simulation time 23384129888 ps
CPU time 24.52 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:52 PM PDT 24
Peak memory 206316 kb
Host smart-d873605a-52d1-467d-b5e7-8e092e521004
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=852222043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.852222043
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2049345762
Short name T2423
Test name
Test status
Simulation time 219548107 ps
CPU time 0.84 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206188 kb
Host smart-74525c2c-43fd-428c-b078-0324baa70470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20493
45762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2049345762
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1778636541
Short name T1169
Test name
Test status
Simulation time 150484894 ps
CPU time 0.74 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:35 PM PDT 24
Peak memory 206180 kb
Host smart-81506bc9-108b-451b-95be-9bc165b97ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17786
36541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1778636541
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.1074036990
Short name T2510
Test name
Test status
Simulation time 496216245 ps
CPU time 1.41 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206180 kb
Host smart-6113431e-1ad7-484b-8fa4-37ce2494fc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10740
36990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.1074036990
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2893829020
Short name T1867
Test name
Test status
Simulation time 271932399 ps
CPU time 0.96 seconds
Started Jun 30 06:25:18 PM PDT 24
Finished Jun 30 06:25:20 PM PDT 24
Peak memory 206164 kb
Host smart-e22b4ab9-051c-4023-ba7f-0bc29effa1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28938
29020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2893829020
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1429764311
Short name T2061
Test name
Test status
Simulation time 7780377381 ps
CPU time 14.08 seconds
Started Jun 30 06:25:21 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206484 kb
Host smart-0f72e3e2-2493-4a19-bcd0-d92ca2324d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14297
64311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1429764311
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2204065389
Short name T883
Test name
Test status
Simulation time 404083428 ps
CPU time 1.34 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206208 kb
Host smart-141393d5-9cee-4423-8a70-0ec5380c36b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22040
65389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2204065389
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1557755806
Short name T863
Test name
Test status
Simulation time 148498763 ps
CPU time 0.77 seconds
Started Jun 30 06:25:17 PM PDT 24
Finished Jun 30 06:25:19 PM PDT 24
Peak memory 206172 kb
Host smart-69cc5b5b-01a2-4833-82a1-71d82531cc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15577
55806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1557755806
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2133718758
Short name T606
Test name
Test status
Simulation time 37523931 ps
CPU time 0.71 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206180 kb
Host smart-8c310451-8634-484b-9287-7c24ff3d41b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21337
18758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2133718758
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3946284639
Short name T1954
Test name
Test status
Simulation time 726001983 ps
CPU time 1.77 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206284 kb
Host smart-e1658570-74d8-4aa5-8010-199305ca0eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39462
84639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3946284639
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.8233613
Short name T1044
Test name
Test status
Simulation time 256348855 ps
CPU time 1.61 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:28 PM PDT 24
Peak memory 206360 kb
Host smart-36b160a7-c5fc-4ab3-8471-7dda8604c9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82336
13 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.8233613
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3323084588
Short name T2251
Test name
Test status
Simulation time 175029232 ps
CPU time 0.8 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 205584 kb
Host smart-588f0ed3-67df-4c53-bf08-6d390b518556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33230
84588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3323084588
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2678566307
Short name T637
Test name
Test status
Simulation time 141825661 ps
CPU time 0.8 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206200 kb
Host smart-fb9404f3-08d3-4ef7-9182-06cfa4f5c1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26785
66307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2678566307
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2764089704
Short name T739
Test name
Test status
Simulation time 266928018 ps
CPU time 0.94 seconds
Started Jun 30 06:25:34 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206208 kb
Host smart-e0cfd314-1c9d-428f-9332-c6577692655c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27640
89704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2764089704
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.3226874837
Short name T574
Test name
Test status
Simulation time 6554153210 ps
CPU time 182.35 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:28:29 PM PDT 24
Peak memory 206476 kb
Host smart-9b57dd99-e13b-459c-b154-62652d12f5dd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3226874837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.3226874837
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3206523050
Short name T980
Test name
Test status
Simulation time 239762092 ps
CPU time 0.89 seconds
Started Jun 30 06:25:27 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206120 kb
Host smart-4222c696-b6ef-479e-b9cc-4f135966d84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32065
23050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3206523050
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.4207218997
Short name T1636
Test name
Test status
Simulation time 23317250634 ps
CPU time 22.81 seconds
Started Jun 30 06:25:35 PM PDT 24
Finished Jun 30 06:26:00 PM PDT 24
Peak memory 206312 kb
Host smart-cff5e6a0-e23b-4708-b55b-d63ad7db2644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072
18997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.4207218997
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.934204324
Short name T1854
Test name
Test status
Simulation time 3315619016 ps
CPU time 3.84 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206300 kb
Host smart-887128cf-4b02-4e8d-ad08-955963fe9493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93420
4324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.934204324
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.2782918819
Short name T2012
Test name
Test status
Simulation time 5673627762 ps
CPU time 48.48 seconds
Started Jun 30 06:25:21 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206476 kb
Host smart-426311c3-2fad-4b43-9b0b-a4d8596930ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27829
18819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.2782918819
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.407825756
Short name T1982
Test name
Test status
Simulation time 6950316999 ps
CPU time 61.33 seconds
Started Jun 30 06:25:34 PM PDT 24
Finished Jun 30 06:26:38 PM PDT 24
Peak memory 206488 kb
Host smart-7bb3f49d-6b71-49f9-b804-96b72c773671
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=407825756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.407825756
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1002587515
Short name T2442
Test name
Test status
Simulation time 256379358 ps
CPU time 0.94 seconds
Started Jun 30 06:25:23 PM PDT 24
Finished Jun 30 06:25:26 PM PDT 24
Peak memory 206224 kb
Host smart-29b657a3-3ed3-4a20-bc8d-3666be4307df
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1002587515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1002587515
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3458031781
Short name T804
Test name
Test status
Simulation time 212024527 ps
CPU time 0.87 seconds
Started Jun 30 06:25:30 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206060 kb
Host smart-16de001f-3081-4160-a668-ee76ead80b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34580
31781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3458031781
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3841969900
Short name T1889
Test name
Test status
Simulation time 3919714076 ps
CPU time 38.2 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:26:00 PM PDT 24
Peak memory 206380 kb
Host smart-2cd86b30-6caf-49cd-8dcd-27a57d11684d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38419
69900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3841969900
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.3325840136
Short name T644
Test name
Test status
Simulation time 3957099141 ps
CPU time 108.32 seconds
Started Jun 30 06:25:20 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 206424 kb
Host smart-3924afb7-fb0d-424c-9a46-317ae71ec0e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3325840136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.3325840136
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3188126838
Short name T1391
Test name
Test status
Simulation time 156713190 ps
CPU time 0.79 seconds
Started Jun 30 06:25:22 PM PDT 24
Finished Jun 30 06:25:24 PM PDT 24
Peak memory 205932 kb
Host smart-9d2f6e6e-0539-4bf4-a534-4a8fd6113196
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3188126838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3188126838
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3110958990
Short name T1362
Test name
Test status
Simulation time 159675159 ps
CPU time 0.77 seconds
Started Jun 30 06:25:35 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206204 kb
Host smart-e8616d88-8cd5-4e78-aa34-00150656f3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31109
58990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3110958990
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1400429155
Short name T2087
Test name
Test status
Simulation time 278597622 ps
CPU time 0.92 seconds
Started Jun 30 06:25:22 PM PDT 24
Finished Jun 30 06:25:25 PM PDT 24
Peak memory 206180 kb
Host smart-28208d2e-912b-47c0-9a52-d592303b94da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14004
29155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1400429155
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3949436672
Short name T236
Test name
Test status
Simulation time 185929977 ps
CPU time 0.8 seconds
Started Jun 30 06:25:19 PM PDT 24
Finished Jun 30 06:25:22 PM PDT 24
Peak memory 206160 kb
Host smart-3d2aba50-37a4-4556-80dd-17dcbcc09217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39494
36672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3949436672
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.704934573
Short name T2530
Test name
Test status
Simulation time 183383439 ps
CPU time 0.83 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206180 kb
Host smart-ebf6fa4c-4b67-4e3e-a088-8d496b6f96e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70493
4573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.704934573
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.4211921734
Short name T1491
Test name
Test status
Simulation time 213006237 ps
CPU time 0.8 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:35 PM PDT 24
Peak memory 206204 kb
Host smart-0a6528a7-78d0-4f61-8bb8-1e63b1773259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42119
21734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.4211921734
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3126423401
Short name T2051
Test name
Test status
Simulation time 149075546 ps
CPU time 0.75 seconds
Started Jun 30 06:25:29 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206204 kb
Host smart-57afc487-2200-4f4c-8e40-eb044be77f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31264
23401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3126423401
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1952421134
Short name T1748
Test name
Test status
Simulation time 206523867 ps
CPU time 0.86 seconds
Started Jun 30 06:25:23 PM PDT 24
Finished Jun 30 06:25:25 PM PDT 24
Peak memory 206208 kb
Host smart-64ae620e-8c02-4df5-9105-32a4b36fa4d8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1952421134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1952421134
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.631357442
Short name T2623
Test name
Test status
Simulation time 146025771 ps
CPU time 0.78 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 205516 kb
Host smart-a06328e6-2181-4f71-945c-4555fe953683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63135
7442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.631357442
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2352651653
Short name T2560
Test name
Test status
Simulation time 35336470 ps
CPU time 0.65 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:31 PM PDT 24
Peak memory 206208 kb
Host smart-c7e20422-2f66-41ac-bfb9-bcb706e5dcd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23526
51653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2352651653
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.4024526795
Short name T1777
Test name
Test status
Simulation time 7064279206 ps
CPU time 15.55 seconds
Started Jun 30 06:25:35 PM PDT 24
Finished Jun 30 06:25:53 PM PDT 24
Peak memory 206448 kb
Host smart-169df1ec-290c-4e16-885e-8ae86d9229c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40245
26795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.4024526795
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2487159911
Short name T1805
Test name
Test status
Simulation time 243445086 ps
CPU time 0.91 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206196 kb
Host smart-6749231a-99cb-44de-8e5d-5c7ce2e50f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24871
59911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2487159911
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2015709945
Short name T32
Test name
Test status
Simulation time 225484123 ps
CPU time 0.89 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206216 kb
Host smart-ad7980cf-f6a0-43d1-90b1-1c7cbf66568d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20157
09945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2015709945
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2108896069
Short name T1303
Test name
Test status
Simulation time 202433749 ps
CPU time 0.85 seconds
Started Jun 30 06:25:18 PM PDT 24
Finished Jun 30 06:25:19 PM PDT 24
Peak memory 206228 kb
Host smart-fe66cacf-31a6-464b-be46-92e15ce5b930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21088
96069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2108896069
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3601213417
Short name T1334
Test name
Test status
Simulation time 188496278 ps
CPU time 0.87 seconds
Started Jun 30 06:25:27 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206152 kb
Host smart-7ebbcc6d-1c98-40d5-b1b1-8a476d0a7949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36012
13417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3601213417
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2148273681
Short name T2195
Test name
Test status
Simulation time 153549657 ps
CPU time 0.76 seconds
Started Jun 30 06:25:18 PM PDT 24
Finished Jun 30 06:25:20 PM PDT 24
Peak memory 206192 kb
Host smart-5aade0e0-184a-4eea-a7e7-ce17d37c11ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21482
73681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2148273681
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.401075690
Short name T2063
Test name
Test status
Simulation time 162158789 ps
CPU time 0.79 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206188 kb
Host smart-017dcf22-9fa7-4c83-b8cb-aca29d9f5d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40107
5690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.401075690
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3554806957
Short name T2204
Test name
Test status
Simulation time 162281813 ps
CPU time 0.79 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206152 kb
Host smart-05b85513-404e-4d81-b3f6-de4c9f858fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35548
06957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3554806957
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2821977614
Short name T2490
Test name
Test status
Simulation time 234640783 ps
CPU time 0.88 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206216 kb
Host smart-da2ce90a-5030-4452-a8ec-c54f50fb21f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28219
77614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2821977614
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.3679750465
Short name T1326
Test name
Test status
Simulation time 4933863892 ps
CPU time 33.66 seconds
Started Jun 30 06:25:27 PM PDT 24
Finished Jun 30 06:26:04 PM PDT 24
Peak memory 206432 kb
Host smart-3a2d31cf-c81f-4c1e-8182-47a51377aa78
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3679750465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.3679750465
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1960770258
Short name T2441
Test name
Test status
Simulation time 174279613 ps
CPU time 0.9 seconds
Started Jun 30 06:25:37 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206216 kb
Host smart-309fc7b4-96b5-4212-b07e-eff4487fae91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19607
70258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1960770258
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3521094409
Short name T1024
Test name
Test status
Simulation time 179597990 ps
CPU time 0.9 seconds
Started Jun 30 06:25:30 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206196 kb
Host smart-30b7ba92-e8ec-4c0e-848f-2737a2ad9f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35210
94409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3521094409
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2947938063
Short name T2342
Test name
Test status
Simulation time 5328774075 ps
CPU time 49.83 seconds
Started Jun 30 06:25:37 PM PDT 24
Finished Jun 30 06:26:28 PM PDT 24
Peak memory 206472 kb
Host smart-dda72a44-9a4c-488a-996a-b108d49be6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29479
38063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2947938063
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.409101290
Short name T1747
Test name
Test status
Simulation time 31426750 ps
CPU time 0.65 seconds
Started Jun 30 06:25:34 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206136 kb
Host smart-708c26aa-23a9-4142-9c2e-8634f88b5080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=409101290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.409101290
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.4086918113
Short name T543
Test name
Test status
Simulation time 4218654008 ps
CPU time 4.64 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:34 PM PDT 24
Peak memory 206260 kb
Host smart-83cdefbf-e724-4dd2-8ec3-d9779126af75
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4086918113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.4086918113
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1453097879
Short name T2284
Test name
Test status
Simulation time 13406022642 ps
CPU time 12.21 seconds
Started Jun 30 06:25:30 PM PDT 24
Finished Jun 30 06:25:45 PM PDT 24
Peak memory 206500 kb
Host smart-6cede400-0c1a-4d4f-a303-500b18ad3d36
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1453097879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1453097879
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3316761375
Short name T771
Test name
Test status
Simulation time 23372036831 ps
CPU time 27.11 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:26:04 PM PDT 24
Peak memory 206304 kb
Host smart-a2870982-665c-4fb8-b0b1-5b46217f2994
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3316761375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.3316761375
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.151933148
Short name T1467
Test name
Test status
Simulation time 215062900 ps
CPU time 0.88 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206156 kb
Host smart-73317d15-287b-42bf-ad18-b7ba4750eef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15193
3148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.151933148
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1929072952
Short name T2428
Test name
Test status
Simulation time 162728491 ps
CPU time 0.79 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206184 kb
Host smart-b588e101-9e54-4ded-ad6b-2df3ec40222d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19290
72952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1929072952
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2689342948
Short name T1634
Test name
Test status
Simulation time 331515365 ps
CPU time 1.24 seconds
Started Jun 30 06:25:36 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206164 kb
Host smart-60f61fbe-8dd1-480a-848d-6f1f3c87e9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26893
42948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2689342948
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1067182998
Short name T101
Test name
Test status
Simulation time 536013925 ps
CPU time 1.54 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206192 kb
Host smart-73f3a098-3d43-4381-ba72-8d3a1ec90fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10671
82998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1067182998
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.4068542458
Short name T952
Test name
Test status
Simulation time 18528530657 ps
CPU time 35.37 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:26:05 PM PDT 24
Peak memory 206420 kb
Host smart-789c4e81-ec4e-4cb6-ac1b-dfdd0c35dce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40685
42458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.4068542458
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.741697542
Short name T1264
Test name
Test status
Simulation time 376680715 ps
CPU time 1.17 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:27 PM PDT 24
Peak memory 206216 kb
Host smart-715d7a04-cea6-4d87-9de6-562cbf6d1ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74169
7542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.741697542
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.960246808
Short name T2205
Test name
Test status
Simulation time 159266443 ps
CPU time 0.76 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:29 PM PDT 24
Peak memory 206184 kb
Host smart-3eee2f90-6cc6-47f3-8c7c-282289e7affb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96024
6808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.960246808
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.1316181148
Short name T1702
Test name
Test status
Simulation time 50509130 ps
CPU time 0.66 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:26 PM PDT 24
Peak memory 206176 kb
Host smart-558869d6-c1bb-465e-a8b2-d549b412eddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13161
81148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1316181148
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1657413158
Short name T2458
Test name
Test status
Simulation time 794493074 ps
CPU time 1.92 seconds
Started Jun 30 06:25:30 PM PDT 24
Finished Jun 30 06:25:34 PM PDT 24
Peak memory 206176 kb
Host smart-7adbf5ff-639d-4a87-b96c-30b817c2883d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16574
13158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1657413158
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1422664224
Short name T2573
Test name
Test status
Simulation time 176078582 ps
CPU time 1.53 seconds
Started Jun 30 06:25:30 PM PDT 24
Finished Jun 30 06:25:34 PM PDT 24
Peak memory 206156 kb
Host smart-621d1aaf-ccc3-4518-bedf-4c791503ad9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14226
64224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1422664224
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2669249368
Short name T563
Test name
Test status
Simulation time 212801857 ps
CPU time 0.88 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206176 kb
Host smart-938892b4-34e9-4c71-9c91-e7c91316f5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26692
49368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2669249368
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2806743126
Short name T1119
Test name
Test status
Simulation time 141736564 ps
CPU time 0.78 seconds
Started Jun 30 06:25:35 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206188 kb
Host smart-9137198d-710b-4085-80a9-580a38d7ce32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28067
43126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2806743126
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.71374837
Short name T2581
Test name
Test status
Simulation time 270035899 ps
CPU time 0.92 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206196 kb
Host smart-f1a7a294-2054-4aa1-ab8b-071e8146b528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71374
837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.71374837
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.993279720
Short name T792
Test name
Test status
Simulation time 187408260 ps
CPU time 0.86 seconds
Started Jun 30 06:25:38 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206168 kb
Host smart-b5506b4a-ed9c-4af6-a040-576a5647443a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99327
9720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.993279720
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1578565999
Short name T2619
Test name
Test status
Simulation time 23387935951 ps
CPU time 24.8 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:55 PM PDT 24
Peak memory 206292 kb
Host smart-a7a3e56b-79b3-4272-8d2e-9ae11ec1f729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15785
65999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1578565999
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3305393819
Short name T2453
Test name
Test status
Simulation time 3340542696 ps
CPU time 3.82 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206244 kb
Host smart-7e81997c-b932-4e5e-a566-9aea56a5875d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33053
93819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3305393819
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2333405879
Short name T1746
Test name
Test status
Simulation time 8403182946 ps
CPU time 79.8 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206416 kb
Host smart-9e17a0ee-ab9d-4967-8fa3-49f9f2dce215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23334
05879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2333405879
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3508123511
Short name T1907
Test name
Test status
Simulation time 4989245403 ps
CPU time 127.52 seconds
Started Jun 30 06:25:30 PM PDT 24
Finished Jun 30 06:27:40 PM PDT 24
Peak memory 206452 kb
Host smart-41ac0ab6-1501-4eeb-895d-76147accfb58
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3508123511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3508123511
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.4104834276
Short name T831
Test name
Test status
Simulation time 240672295 ps
CPU time 0.93 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206180 kb
Host smart-c05052a0-f315-4b8f-bdc9-daaf76590232
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4104834276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.4104834276
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3934256277
Short name T328
Test name
Test status
Simulation time 182507969 ps
CPU time 0.84 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:25:27 PM PDT 24
Peak memory 206360 kb
Host smart-b7fc44cb-6f38-4ea6-970e-33eb0af42bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39342
56277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3934256277
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1629003534
Short name T1583
Test name
Test status
Simulation time 5706160971 ps
CPU time 40.93 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:26:08 PM PDT 24
Peak memory 206372 kb
Host smart-5ba89ec7-ddd5-43df-b3d7-e13800f36c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290
03534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1629003534
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2049733170
Short name T84
Test name
Test status
Simulation time 4945689803 ps
CPU time 34.17 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:26:08 PM PDT 24
Peak memory 206308 kb
Host smart-a81d890d-8e93-4ebb-bcce-6dfeb4e4d563
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2049733170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2049733170
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.4196975752
Short name T2117
Test name
Test status
Simulation time 167196086 ps
CPU time 0.84 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206204 kb
Host smart-ab4c0099-0745-4aba-be9f-f573fbabd720
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4196975752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.4196975752
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.942616837
Short name T2434
Test name
Test status
Simulation time 152845421 ps
CPU time 0.77 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:25:35 PM PDT 24
Peak memory 206196 kb
Host smart-67963187-0bc0-48d4-a2cf-d59e1e2b3bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94261
6837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.942616837
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2419855342
Short name T2300
Test name
Test status
Simulation time 199489208 ps
CPU time 0.81 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206192 kb
Host smart-74365670-69d9-4b0d-be41-e998cd4fea80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24198
55342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2419855342
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.4129915220
Short name T19
Test name
Test status
Simulation time 203003471 ps
CPU time 0.82 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:31 PM PDT 24
Peak memory 206180 kb
Host smart-9929de87-cd32-421a-95b0-7d8dedf6df50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41299
15220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.4129915220
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2516395201
Short name T1677
Test name
Test status
Simulation time 174328982 ps
CPU time 0.83 seconds
Started Jun 30 06:25:35 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206192 kb
Host smart-c4258f86-28ac-40af-bba4-af4deaa3c7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25163
95201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2516395201
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2530076670
Short name T2595
Test name
Test status
Simulation time 178373324 ps
CPU time 0.82 seconds
Started Jun 30 06:25:23 PM PDT 24
Finished Jun 30 06:25:26 PM PDT 24
Peak memory 206220 kb
Host smart-9ec70a7b-174b-44f7-bd85-53aa64013a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25300
76670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2530076670
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1451166794
Short name T200
Test name
Test status
Simulation time 178998371 ps
CPU time 0.81 seconds
Started Jun 30 06:25:35 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206196 kb
Host smart-baedb833-1ac2-41bf-b349-89aec9481afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14511
66794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1451166794
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3603558489
Short name T1700
Test name
Test status
Simulation time 197585649 ps
CPU time 0.99 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:29 PM PDT 24
Peak memory 206196 kb
Host smart-90f05ff5-f9f8-4417-a9ae-2a083549891f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3603558489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3603558489
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2804215137
Short name T1261
Test name
Test status
Simulation time 155703611 ps
CPU time 0.77 seconds
Started Jun 30 06:25:39 PM PDT 24
Finished Jun 30 06:25:40 PM PDT 24
Peak memory 206188 kb
Host smart-fddeea1e-7db5-42b1-8a44-9b5e0891e491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28042
15137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2804215137
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2048833722
Short name T38
Test name
Test status
Simulation time 45547791 ps
CPU time 0.67 seconds
Started Jun 30 06:25:34 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206184 kb
Host smart-fb404ef7-416d-4017-9aaa-0c834a448275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20488
33722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2048833722
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.3531114432
Short name T293
Test name
Test status
Simulation time 7599557124 ps
CPU time 17.64 seconds
Started Jun 30 06:25:30 PM PDT 24
Finished Jun 30 06:25:50 PM PDT 24
Peak memory 206416 kb
Host smart-90d0a175-6c00-4c28-baf7-e6723bda7d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35311
14432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.3531114432
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.842554652
Short name T1077
Test name
Test status
Simulation time 221227569 ps
CPU time 0.83 seconds
Started Jun 30 06:25:23 PM PDT 24
Finished Jun 30 06:25:25 PM PDT 24
Peak memory 206148 kb
Host smart-07036c42-861e-4597-9333-65649d0dc189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84255
4652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.842554652
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1139074276
Short name T1314
Test name
Test status
Simulation time 264087858 ps
CPU time 0.93 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206196 kb
Host smart-90406006-99e2-49fd-a842-561223624b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11390
74276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1139074276
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.621472064
Short name T1273
Test name
Test status
Simulation time 191836719 ps
CPU time 0.9 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206180 kb
Host smart-7c357c95-ed70-4321-a016-8ea13a5cd5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62147
2064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.621472064
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1360197710
Short name T2411
Test name
Test status
Simulation time 161657993 ps
CPU time 0.8 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206180 kb
Host smart-e6421464-cf7b-4615-b6dc-3f04a08946e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13601
97710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1360197710
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.395508926
Short name T2349
Test name
Test status
Simulation time 163345931 ps
CPU time 0.77 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:25:30 PM PDT 24
Peak memory 206180 kb
Host smart-45089b91-39db-4507-8171-055d16d27a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
8926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.395508926
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2126598158
Short name T80
Test name
Test status
Simulation time 150199805 ps
CPU time 0.76 seconds
Started Jun 30 06:25:27 PM PDT 24
Finished Jun 30 06:25:31 PM PDT 24
Peak memory 206160 kb
Host smart-6bf0b265-59d3-461e-ad7d-db4eef10064e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21265
98158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2126598158
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3200685589
Short name T1814
Test name
Test status
Simulation time 175108740 ps
CPU time 0.82 seconds
Started Jun 30 06:25:34 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206148 kb
Host smart-b35662d7-e083-4ff5-b29c-cc21cf6815a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32006
85589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3200685589
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1601116105
Short name T849
Test name
Test status
Simulation time 209056817 ps
CPU time 0.93 seconds
Started Jun 30 06:25:35 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206208 kb
Host smart-fd9f7ed1-0ecb-4e20-ae50-c92bae913495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16011
16105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1601116105
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.3372055522
Short name T813
Test name
Test status
Simulation time 3526169700 ps
CPU time 98.41 seconds
Started Jun 30 06:25:24 PM PDT 24
Finished Jun 30 06:27:04 PM PDT 24
Peak memory 206472 kb
Host smart-b5241bd6-9f1a-433e-8967-779aaa921da4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3372055522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.3372055522
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3857961388
Short name T1795
Test name
Test status
Simulation time 196793912 ps
CPU time 0.8 seconds
Started Jun 30 06:25:34 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206180 kb
Host smart-de88b549-1b15-4f05-95e7-857a18c84342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38579
61388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3857961388
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2201517745
Short name T565
Test name
Test status
Simulation time 202638721 ps
CPU time 0.8 seconds
Started Jun 30 06:25:29 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206048 kb
Host smart-e914b1af-4dd3-4064-8fb4-5ee948d52e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22015
17745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2201517745
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2204348245
Short name T588
Test name
Test status
Simulation time 4318812948 ps
CPU time 113.01 seconds
Started Jun 30 06:25:26 PM PDT 24
Finished Jun 30 06:27:23 PM PDT 24
Peak memory 206468 kb
Host smart-b251cef9-10b5-4ec6-b251-908f7e0d6069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22043
48245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2204348245
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.3908360884
Short name T2522
Test name
Test status
Simulation time 58256391 ps
CPU time 0.72 seconds
Started Jun 30 06:25:50 PM PDT 24
Finished Jun 30 06:25:51 PM PDT 24
Peak memory 206208 kb
Host smart-0098c21e-2c4d-49f0-9221-81108cce7676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3908360884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3908360884
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.4130771031
Short name T1692
Test name
Test status
Simulation time 3959810166 ps
CPU time 4.97 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206416 kb
Host smart-31251cc3-8118-4dd6-b4d4-8ecbb506d2e5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4130771031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.4130771031
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2818477779
Short name T2329
Test name
Test status
Simulation time 13418250222 ps
CPU time 12.35 seconds
Started Jun 30 06:25:25 PM PDT 24
Finished Jun 30 06:25:40 PM PDT 24
Peak memory 206412 kb
Host smart-abe51c60-c6e0-4d71-a3a1-525ac09c4d57
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2818477779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2818477779
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3331848733
Short name T761
Test name
Test status
Simulation time 23413565223 ps
CPU time 24.02 seconds
Started Jun 30 06:25:38 PM PDT 24
Finished Jun 30 06:26:03 PM PDT 24
Peak memory 206320 kb
Host smart-7d06f9e9-5ae8-4649-ab86-4e2eece30727
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3331848733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.3331848733
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1551453669
Short name T2372
Test name
Test status
Simulation time 153459685 ps
CPU time 0.78 seconds
Started Jun 30 06:25:28 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 206180 kb
Host smart-ebd654af-2a7b-4e16-a8f4-74addeaed017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15514
53669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1551453669
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.334718959
Short name T950
Test name
Test status
Simulation time 146010365 ps
CPU time 0.71 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206156 kb
Host smart-2b365b59-a795-4606-a7fc-8a9b9c62246b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33471
8959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.334718959
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1085291667
Short name T175
Test name
Test status
Simulation time 244940155 ps
CPU time 0.96 seconds
Started Jun 30 06:25:29 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206192 kb
Host smart-5d14e483-151a-49a3-b6d7-bf5ef74e430c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10852
91667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1085291667
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2558935968
Short name T2267
Test name
Test status
Simulation time 343358058 ps
CPU time 1.12 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206180 kb
Host smart-9aea1bb6-e3ac-458d-81da-d287a94f1ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25589
35968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2558935968
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2822310431
Short name T168
Test name
Test status
Simulation time 6997747249 ps
CPU time 13.46 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:25:50 PM PDT 24
Peak memory 206384 kb
Host smart-26caf532-d5a9-4532-b4c4-f0d60b944aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28223
10431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2822310431
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2906565944
Short name T1298
Test name
Test status
Simulation time 450966647 ps
CPU time 1.34 seconds
Started Jun 30 06:25:35 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206192 kb
Host smart-6a224797-cb8f-42c7-a33d-8a632b92f2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29065
65944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2906565944
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3995366384
Short name T1140
Test name
Test status
Simulation time 160685213 ps
CPU time 0.79 seconds
Started Jun 30 06:25:37 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206192 kb
Host smart-eed81c75-17df-4a6a-83c3-ef36adc74c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39953
66384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3995366384
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3604629472
Short name T1606
Test name
Test status
Simulation time 36439398 ps
CPU time 0.66 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:35 PM PDT 24
Peak memory 206180 kb
Host smart-11d29f73-0f80-4950-ad33-7be6b639f99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36046
29472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3604629472
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.548528395
Short name T79
Test name
Test status
Simulation time 898937907 ps
CPU time 2.22 seconds
Started Jun 30 06:25:35 PM PDT 24
Finished Jun 30 06:25:40 PM PDT 24
Peak memory 206320 kb
Host smart-641daac7-4674-4168-8e43-478fb92d7740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54852
8395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.548528395
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3397789957
Short name T911
Test name
Test status
Simulation time 188379558 ps
CPU time 1.89 seconds
Started Jun 30 06:25:29 PM PDT 24
Finished Jun 30 06:25:34 PM PDT 24
Peak memory 206264 kb
Host smart-d7904131-25b0-4c2e-8285-5d188d50e469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977
89957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3397789957
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2838617130
Short name T2324
Test name
Test status
Simulation time 217030754 ps
CPU time 0.86 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:35 PM PDT 24
Peak memory 206176 kb
Host smart-e0a1c8b4-68b7-4a87-9279-c00cfe508c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28386
17130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2838617130
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3908350496
Short name T2548
Test name
Test status
Simulation time 147830886 ps
CPU time 0.81 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:25:35 PM PDT 24
Peak memory 206064 kb
Host smart-4c140c92-abec-4988-a8f7-75a90332059e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39083
50496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3908350496
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.312244952
Short name T1705
Test name
Test status
Simulation time 238917368 ps
CPU time 0.92 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:25:35 PM PDT 24
Peak memory 206208 kb
Host smart-05d6eb52-f5d8-4a2b-91c7-48b73d2908dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31224
4952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.312244952
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3267483480
Short name T2181
Test name
Test status
Simulation time 239436157 ps
CPU time 0.89 seconds
Started Jun 30 06:25:45 PM PDT 24
Finished Jun 30 06:25:46 PM PDT 24
Peak memory 206032 kb
Host smart-4ed81e14-734d-4f98-a270-5cbc081ab364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32674
83480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3267483480
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.2261131675
Short name T1162
Test name
Test status
Simulation time 23390264416 ps
CPU time 23.18 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:25:57 PM PDT 24
Peak memory 206308 kb
Host smart-450545f6-e87f-43fa-865e-85461e908908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22611
31675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.2261131675
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1642224645
Short name T942
Test name
Test status
Simulation time 3269465251 ps
CPU time 3.69 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:25:40 PM PDT 24
Peak memory 206180 kb
Host smart-b7188be8-9564-4166-87b8-ce0f5c78ecc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16422
24645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1642224645
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.952852472
Short name T995
Test name
Test status
Simulation time 6437471198 ps
CPU time 176.86 seconds
Started Jun 30 06:25:31 PM PDT 24
Finished Jun 30 06:28:30 PM PDT 24
Peak memory 206320 kb
Host smart-d68a2168-6073-4142-93f5-8dc72e5096b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95285
2472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.952852472
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.1248900953
Short name T1788
Test name
Test status
Simulation time 4227421298 ps
CPU time 29.05 seconds
Started Jun 30 06:25:36 PM PDT 24
Finished Jun 30 06:26:07 PM PDT 24
Peak memory 206476 kb
Host smart-205a94c7-d108-497f-9981-1dbb81f0ce07
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1248900953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.1248900953
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.549331368
Short name T1735
Test name
Test status
Simulation time 251388450 ps
CPU time 0.93 seconds
Started Jun 30 06:25:36 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 206168 kb
Host smart-fc7b2c8e-76dc-4c59-8631-5d8e55437e10
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=549331368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.549331368
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1785173653
Short name T1949
Test name
Test status
Simulation time 197073283 ps
CPU time 0.88 seconds
Started Jun 30 06:25:34 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206040 kb
Host smart-580b7dae-86dc-4568-a680-a5829a6daada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17851
73653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1785173653
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.2546202989
Short name T1727
Test name
Test status
Simulation time 6084559831 ps
CPU time 158.12 seconds
Started Jun 30 06:25:29 PM PDT 24
Finished Jun 30 06:28:10 PM PDT 24
Peak memory 206428 kb
Host smart-ff5efcf6-65b8-4c61-b505-8b4ab697d51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25462
02989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.2546202989
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1643105519
Short name T2136
Test name
Test status
Simulation time 3099376366 ps
CPU time 87.34 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:27:02 PM PDT 24
Peak memory 206444 kb
Host smart-82ce8220-13da-485c-89b3-af01d67c655f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1643105519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1643105519
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.726242072
Short name T1962
Test name
Test status
Simulation time 159980677 ps
CPU time 0.83 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206132 kb
Host smart-f6ca7da9-f030-4709-94eb-4a2bc383b118
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=726242072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.726242072
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1097147291
Short name T876
Test name
Test status
Simulation time 167746460 ps
CPU time 0.82 seconds
Started Jun 30 06:25:32 PM PDT 24
Finished Jun 30 06:25:36 PM PDT 24
Peak memory 206128 kb
Host smart-84d58b87-78f1-493d-9bbc-0936962bd923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10971
47291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1097147291
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3809765705
Short name T118
Test name
Test status
Simulation time 246951409 ps
CPU time 0.87 seconds
Started Jun 30 06:25:30 PM PDT 24
Finished Jun 30 06:25:33 PM PDT 24
Peak memory 206208 kb
Host smart-89add9ee-2812-45d9-8963-567f98d19002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38097
65705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3809765705
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.3777090495
Short name T234
Test name
Test status
Simulation time 167133419 ps
CPU time 0.8 seconds
Started Jun 30 06:25:34 PM PDT 24
Finished Jun 30 06:25:38 PM PDT 24
Peak memory 206200 kb
Host smart-44d96093-210f-41e8-9c73-48632c2492f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37770
90495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.3777090495
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2426102853
Short name T573
Test name
Test status
Simulation time 228965093 ps
CPU time 0.85 seconds
Started Jun 30 06:25:49 PM PDT 24
Finished Jun 30 06:25:50 PM PDT 24
Peak memory 206196 kb
Host smart-de4f9159-5aa1-488a-850f-9b3b87b21305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24261
02853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2426102853
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1320742864
Short name T27
Test name
Test status
Simulation time 206701422 ps
CPU time 0.89 seconds
Started Jun 30 06:25:46 PM PDT 24
Finished Jun 30 06:25:48 PM PDT 24
Peak memory 206192 kb
Host smart-c3acbac5-146b-4fd9-a5d4-a555173826f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13207
42864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1320742864
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1186385058
Short name T2246
Test name
Test status
Simulation time 156624267 ps
CPU time 0.84 seconds
Started Jun 30 06:25:52 PM PDT 24
Finished Jun 30 06:25:53 PM PDT 24
Peak memory 206192 kb
Host smart-9472b6bf-226c-4aa3-a927-2d6f79741c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11863
85058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1186385058
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.2655718528
Short name T1569
Test name
Test status
Simulation time 234282198 ps
CPU time 0.93 seconds
Started Jun 30 06:25:45 PM PDT 24
Finished Jun 30 06:25:47 PM PDT 24
Peak memory 206196 kb
Host smart-88cc493d-141a-43b6-8f06-f9b60eba0769
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2655718528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.2655718528
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1071487892
Short name T2019
Test name
Test status
Simulation time 149368707 ps
CPU time 0.74 seconds
Started Jun 30 06:25:57 PM PDT 24
Finished Jun 30 06:25:58 PM PDT 24
Peak memory 206196 kb
Host smart-993d8a1c-1ef9-4277-99ef-a7b47c3bbcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10714
87892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1071487892
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2089739053
Short name T1282
Test name
Test status
Simulation time 38605962 ps
CPU time 0.7 seconds
Started Jun 30 06:25:42 PM PDT 24
Finished Jun 30 06:25:43 PM PDT 24
Peak memory 206196 kb
Host smart-3bca2840-7fe5-4e40-bfa8-05975fd915f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20897
39053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2089739053
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.636382107
Short name T1822
Test name
Test status
Simulation time 20277150303 ps
CPU time 46.09 seconds
Started Jun 30 06:25:53 PM PDT 24
Finished Jun 30 06:26:40 PM PDT 24
Peak memory 206476 kb
Host smart-539a4757-0dc8-475a-871f-92063db88908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63638
2107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.636382107
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.428889442
Short name T676
Test name
Test status
Simulation time 168147131 ps
CPU time 0.89 seconds
Started Jun 30 06:25:53 PM PDT 24
Finished Jun 30 06:25:55 PM PDT 24
Peak memory 206188 kb
Host smart-7a0a3871-457c-4394-9c6e-319dd10eadbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42888
9442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.428889442
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1120817767
Short name T1023
Test name
Test status
Simulation time 177320517 ps
CPU time 0.86 seconds
Started Jun 30 06:25:53 PM PDT 24
Finished Jun 30 06:25:55 PM PDT 24
Peak memory 206204 kb
Host smart-ef8166bd-6927-4de4-930c-eca5270cc3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11208
17767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1120817767
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.2709841975
Short name T2527
Test name
Test status
Simulation time 177699217 ps
CPU time 0.81 seconds
Started Jun 30 06:25:43 PM PDT 24
Finished Jun 30 06:25:44 PM PDT 24
Peak memory 206192 kb
Host smart-aadd2b1c-b27d-4f74-82a4-bd3282ef1da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27098
41975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.2709841975
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.3560920855
Short name T881
Test name
Test status
Simulation time 189160039 ps
CPU time 0.86 seconds
Started Jun 30 06:25:43 PM PDT 24
Finished Jun 30 06:25:44 PM PDT 24
Peak memory 206200 kb
Host smart-414e5f51-54a5-4fd5-bf56-75ae95178e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35609
20855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3560920855
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2453640987
Short name T945
Test name
Test status
Simulation time 133187555 ps
CPU time 0.77 seconds
Started Jun 30 06:25:44 PM PDT 24
Finished Jun 30 06:25:45 PM PDT 24
Peak memory 206200 kb
Host smart-ad599bc0-975e-4b92-9950-a0f94547933d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24536
40987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2453640987
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1143327721
Short name T2041
Test name
Test status
Simulation time 146158992 ps
CPU time 0.83 seconds
Started Jun 30 06:25:52 PM PDT 24
Finished Jun 30 06:25:53 PM PDT 24
Peak memory 206184 kb
Host smart-1173ea32-75fd-47ca-b08d-0b7732c3f0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11433
27721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1143327721
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2145761005
Short name T1353
Test name
Test status
Simulation time 167642348 ps
CPU time 0.78 seconds
Started Jun 30 06:25:46 PM PDT 24
Finished Jun 30 06:25:47 PM PDT 24
Peak memory 206188 kb
Host smart-ceda81c1-3c95-4190-b3eb-d726e23cfb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21457
61005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2145761005
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2426947307
Short name T2250
Test name
Test status
Simulation time 220359066 ps
CPU time 0.92 seconds
Started Jun 30 06:25:41 PM PDT 24
Finished Jun 30 06:25:42 PM PDT 24
Peak memory 206200 kb
Host smart-fb345b85-fce5-40ca-b80c-20734127bbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269
47307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2426947307
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.84587283
Short name T2563
Test name
Test status
Simulation time 4642432951 ps
CPU time 31.64 seconds
Started Jun 30 06:25:45 PM PDT 24
Finished Jun 30 06:26:17 PM PDT 24
Peak memory 206440 kb
Host smart-60b0f62a-d90c-41de-a22e-c8b3e5e918d7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=84587283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.84587283
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.367055621
Short name T840
Test name
Test status
Simulation time 143253319 ps
CPU time 0.74 seconds
Started Jun 30 06:25:43 PM PDT 24
Finished Jun 30 06:25:44 PM PDT 24
Peak memory 206212 kb
Host smart-8d7a0f52-1755-4e0b-8d67-24bacb7cea8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36705
5621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.367055621
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2361596819
Short name T2536
Test name
Test status
Simulation time 189803034 ps
CPU time 0.81 seconds
Started Jun 30 06:25:47 PM PDT 24
Finished Jun 30 06:25:48 PM PDT 24
Peak memory 206184 kb
Host smart-fc2d531c-0949-4427-ae63-6da69dde7f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23615
96819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2361596819
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2377349261
Short name T1108
Test name
Test status
Simulation time 8068142019 ps
CPU time 73.34 seconds
Started Jun 30 06:25:46 PM PDT 24
Finished Jun 30 06:27:01 PM PDT 24
Peak memory 206376 kb
Host smart-3bae7b27-1c63-41e6-ae3e-c401122e00b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23773
49261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2377349261
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.2017252700
Short name T1293
Test name
Test status
Simulation time 63980982 ps
CPU time 0.73 seconds
Started Jun 30 06:20:55 PM PDT 24
Finished Jun 30 06:20:56 PM PDT 24
Peak memory 206152 kb
Host smart-57d19268-16e1-49f2-8e84-80ef6b48b9a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2017252700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.2017252700
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.297351462
Short name T769
Test name
Test status
Simulation time 3502253080 ps
CPU time 3.86 seconds
Started Jun 30 06:20:46 PM PDT 24
Finished Jun 30 06:20:51 PM PDT 24
Peak memory 206332 kb
Host smart-675f995e-6113-4fef-99ba-951a35ba34a6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=297351462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.297351462
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.4095599851
Short name T2519
Test name
Test status
Simulation time 13320908230 ps
CPU time 13.13 seconds
Started Jun 30 06:20:40 PM PDT 24
Finished Jun 30 06:20:54 PM PDT 24
Peak memory 206344 kb
Host smart-5006ad39-13e0-47b6-8249-95a732e8f189
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4095599851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.4095599851
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.285161137
Short name T1010
Test name
Test status
Simulation time 23389325552 ps
CPU time 24.07 seconds
Started Jun 30 06:20:39 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206408 kb
Host smart-c33aeb96-ad17-4250-abb0-9b1b8d09d3d4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=285161137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.285161137
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.122199533
Short name T2222
Test name
Test status
Simulation time 171628867 ps
CPU time 0.87 seconds
Started Jun 30 06:20:45 PM PDT 24
Finished Jun 30 06:20:46 PM PDT 24
Peak memory 206164 kb
Host smart-29cd9d93-5b23-45e7-b82f-58a8f3973ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12219
9533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.122199533
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.2016561845
Short name T53
Test name
Test status
Simulation time 159531147 ps
CPU time 0.77 seconds
Started Jun 30 06:20:40 PM PDT 24
Finished Jun 30 06:20:41 PM PDT 24
Peak memory 206208 kb
Host smart-fef74cd1-73cf-4f78-948e-7d3e75d83cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20165
61845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.2016561845
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2533188978
Short name T81
Test name
Test status
Simulation time 154339119 ps
CPU time 0.81 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:20:43 PM PDT 24
Peak memory 206156 kb
Host smart-d3a9e30f-32c2-4e1d-9f4d-5ce4fa650c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25331
88978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2533188978
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2738372545
Short name T1179
Test name
Test status
Simulation time 188150705 ps
CPU time 0.8 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:20:43 PM PDT 24
Peak memory 206120 kb
Host smart-1babdc9d-bf57-4445-90a0-da4a58aa928b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27383
72545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2738372545
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.4194093756
Short name T2634
Test name
Test status
Simulation time 184609949 ps
CPU time 0.83 seconds
Started Jun 30 06:20:43 PM PDT 24
Finished Jun 30 06:20:44 PM PDT 24
Peak memory 206164 kb
Host smart-e51f0902-68ed-4142-b924-a88e2b40901b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41940
93756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.4194093756
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1900912840
Short name T2291
Test name
Test status
Simulation time 467803197 ps
CPU time 1.39 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:20:44 PM PDT 24
Peak memory 206180 kb
Host smart-4d8844ec-1ccd-47a3-b5b6-e5e1330d25fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19009
12840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1900912840
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1354924363
Short name T2577
Test name
Test status
Simulation time 13489432037 ps
CPU time 27.57 seconds
Started Jun 30 06:20:40 PM PDT 24
Finished Jun 30 06:21:08 PM PDT 24
Peak memory 206364 kb
Host smart-81e3fa92-c2c2-473b-82f2-d2f96564a130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13549
24363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1354924363
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1585472624
Short name T708
Test name
Test status
Simulation time 421712914 ps
CPU time 1.26 seconds
Started Jun 30 06:20:45 PM PDT 24
Finished Jun 30 06:20:47 PM PDT 24
Peak memory 206192 kb
Host smart-05b5115f-0c84-4177-a54f-089dda193291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15854
72624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1585472624
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2043122450
Short name T434
Test name
Test status
Simulation time 147878504 ps
CPU time 0.79 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:20:44 PM PDT 24
Peak memory 206164 kb
Host smart-057caec3-1bec-4352-914d-f46dec4a01c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20431
22450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2043122450
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1230595361
Short name T1382
Test name
Test status
Simulation time 48841069 ps
CPU time 0.67 seconds
Started Jun 30 06:20:44 PM PDT 24
Finished Jun 30 06:20:46 PM PDT 24
Peak memory 206200 kb
Host smart-abc8551c-ec8c-424d-831f-11dcf23d3f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12305
95361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1230595361
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.705643589
Short name T1964
Test name
Test status
Simulation time 776392230 ps
CPU time 2.04 seconds
Started Jun 30 06:20:41 PM PDT 24
Finished Jun 30 06:20:44 PM PDT 24
Peak memory 206272 kb
Host smart-297ab0ef-f6be-4791-acbe-a3a9d596d54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70564
3589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.705643589
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2368050809
Short name T1887
Test name
Test status
Simulation time 206044158 ps
CPU time 1.28 seconds
Started Jun 30 06:20:46 PM PDT 24
Finished Jun 30 06:20:47 PM PDT 24
Peak memory 206296 kb
Host smart-f2a8fc5d-af30-4d88-8b33-abc88e9894b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23680
50809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2368050809
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1305702364
Short name T1628
Test name
Test status
Simulation time 184736083 ps
CPU time 0.83 seconds
Started Jun 30 06:20:42 PM PDT 24
Finished Jun 30 06:20:44 PM PDT 24
Peak memory 206192 kb
Host smart-49bc1065-4cb0-4ea4-908a-dbfc1265367f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13057
02364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1305702364
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.4124760187
Short name T470
Test name
Test status
Simulation time 141486376 ps
CPU time 0.75 seconds
Started Jun 30 06:20:41 PM PDT 24
Finished Jun 30 06:20:42 PM PDT 24
Peak memory 206204 kb
Host smart-0dfee19a-ba80-4a3d-878c-92f3ea6bee46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41247
60187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.4124760187
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.924959294
Short name T1800
Test name
Test status
Simulation time 153798312 ps
CPU time 0.79 seconds
Started Jun 30 06:20:44 PM PDT 24
Finished Jun 30 06:20:45 PM PDT 24
Peak memory 206168 kb
Host smart-2f257b65-4aeb-4941-a365-f688a4149463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92495
9294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.924959294
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1694855095
Short name T624
Test name
Test status
Simulation time 186633573 ps
CPU time 0.83 seconds
Started Jun 30 06:20:40 PM PDT 24
Finished Jun 30 06:20:41 PM PDT 24
Peak memory 206180 kb
Host smart-dddd3f41-277e-4432-b33e-74d3cab4aae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16948
55095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1694855095
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3613670328
Short name T2046
Test name
Test status
Simulation time 23299270008 ps
CPU time 21.74 seconds
Started Jun 30 06:20:39 PM PDT 24
Finished Jun 30 06:21:02 PM PDT 24
Peak memory 206300 kb
Host smart-2e7a6932-b629-4fae-9ad4-ab2da0da8a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36136
70328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3613670328
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1318207517
Short name T2182
Test name
Test status
Simulation time 3314508067 ps
CPU time 3.56 seconds
Started Jun 30 06:20:44 PM PDT 24
Finished Jun 30 06:20:48 PM PDT 24
Peak memory 206184 kb
Host smart-95ce3697-54ac-4788-9f53-13cf561db48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13182
07517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1318207517
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.3670771516
Short name T1246
Test name
Test status
Simulation time 6507638249 ps
CPU time 46.56 seconds
Started Jun 30 06:20:40 PM PDT 24
Finished Jun 30 06:21:28 PM PDT 24
Peak memory 206460 kb
Host smart-0138e689-b94e-4c53-80b8-1469831188b2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3670771516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.3670771516
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2008512161
Short name T743
Test name
Test status
Simulation time 251084281 ps
CPU time 0.99 seconds
Started Jun 30 06:20:40 PM PDT 24
Finished Jun 30 06:20:41 PM PDT 24
Peak memory 206220 kb
Host smart-7a2b6112-3a26-4a13-a10a-ddac44ceb4dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2008512161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2008512161
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.965977150
Short name T497
Test name
Test status
Simulation time 195593752 ps
CPU time 0.85 seconds
Started Jun 30 06:20:41 PM PDT 24
Finished Jun 30 06:20:42 PM PDT 24
Peak memory 206212 kb
Host smart-630ab50c-dbf8-4b69-aa4d-f2747b78446a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96597
7150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.965977150
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.177939614
Short name T2487
Test name
Test status
Simulation time 4440848393 ps
CPU time 127.76 seconds
Started Jun 30 06:20:44 PM PDT 24
Finished Jun 30 06:22:52 PM PDT 24
Peak memory 206456 kb
Host smart-766af840-2476-4242-831d-ac4bd7e7f793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17793
9614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.177939614
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3909987878
Short name T418
Test name
Test status
Simulation time 3890792043 ps
CPU time 105.85 seconds
Started Jun 30 06:20:43 PM PDT 24
Finished Jun 30 06:22:29 PM PDT 24
Peak memory 206384 kb
Host smart-a31a4c7e-87a9-4e48-b3b3-7960a38f445a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3909987878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3909987878
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.129417174
Short name T2617
Test name
Test status
Simulation time 173238000 ps
CPU time 0.86 seconds
Started Jun 30 06:20:47 PM PDT 24
Finished Jun 30 06:20:48 PM PDT 24
Peak memory 206188 kb
Host smart-432ec756-51b1-4370-a15b-81ce2c0daaef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=129417174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.129417174
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.876389501
Short name T1267
Test name
Test status
Simulation time 175743327 ps
CPU time 0.79 seconds
Started Jun 30 06:20:49 PM PDT 24
Finished Jun 30 06:20:50 PM PDT 24
Peak memory 206196 kb
Host smart-1d915e92-d2b9-45e4-b366-1e513c8cb3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87638
9501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.876389501
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.870049602
Short name T141
Test name
Test status
Simulation time 214509648 ps
CPU time 0.87 seconds
Started Jun 30 06:20:55 PM PDT 24
Finished Jun 30 06:20:57 PM PDT 24
Peak memory 206168 kb
Host smart-448be913-977c-449f-b26b-c5984a4edcb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87004
9602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.870049602
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1890107325
Short name T2108
Test name
Test status
Simulation time 176713782 ps
CPU time 0.97 seconds
Started Jun 30 06:20:47 PM PDT 24
Finished Jun 30 06:20:49 PM PDT 24
Peak memory 206176 kb
Host smart-b19b3cd7-67a0-4d1b-a13f-52d7e9a3c359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18901
07325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1890107325
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1347032969
Short name T1124
Test name
Test status
Simulation time 176586316 ps
CPU time 0.8 seconds
Started Jun 30 06:20:47 PM PDT 24
Finished Jun 30 06:20:48 PM PDT 24
Peak memory 206168 kb
Host smart-6b108e18-0b24-4384-93e4-d2d696b6b98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13470
32969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1347032969
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2254321682
Short name T816
Test name
Test status
Simulation time 189488252 ps
CPU time 0.83 seconds
Started Jun 30 06:20:48 PM PDT 24
Finished Jun 30 06:20:49 PM PDT 24
Peak memory 206144 kb
Host smart-0b8160aa-4141-49c4-a38b-e52ba853dfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22543
21682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2254321682
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3269290935
Short name T191
Test name
Test status
Simulation time 155987431 ps
CPU time 0.86 seconds
Started Jun 30 06:20:48 PM PDT 24
Finished Jun 30 06:20:50 PM PDT 24
Peak memory 206156 kb
Host smart-02ec2cb6-be5f-4a1f-90cb-8c2312eb32ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32692
90935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3269290935
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.565123457
Short name T1251
Test name
Test status
Simulation time 228130076 ps
CPU time 0.94 seconds
Started Jun 30 06:20:49 PM PDT 24
Finished Jun 30 06:20:50 PM PDT 24
Peak memory 206212 kb
Host smart-78569210-ec7d-4126-90ff-2b70f1d2de3f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=565123457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.565123457
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.1751275901
Short name T1227
Test name
Test status
Simulation time 212370984 ps
CPU time 1.02 seconds
Started Jun 30 06:20:48 PM PDT 24
Finished Jun 30 06:20:50 PM PDT 24
Peak memory 206200 kb
Host smart-6c73d12d-021f-4298-b719-bc370d20f000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17512
75901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.1751275901
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.556684483
Short name T1587
Test name
Test status
Simulation time 153936912 ps
CPU time 0.75 seconds
Started Jun 30 06:20:55 PM PDT 24
Finished Jun 30 06:20:56 PM PDT 24
Peak memory 206164 kb
Host smart-b71f5154-1b88-4df5-886b-f9d47dbacc2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55668
4483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.556684483
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2263622254
Short name T2128
Test name
Test status
Simulation time 38442497 ps
CPU time 0.66 seconds
Started Jun 30 06:20:47 PM PDT 24
Finished Jun 30 06:20:48 PM PDT 24
Peak memory 206192 kb
Host smart-ed62d2d6-ded4-44bd-8681-37af38f567b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22636
22254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2263622254
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1158821438
Short name T271
Test name
Test status
Simulation time 12445345226 ps
CPU time 28.79 seconds
Started Jun 30 06:20:50 PM PDT 24
Finished Jun 30 06:21:19 PM PDT 24
Peak memory 206456 kb
Host smart-f2f83544-df05-4ffe-aed1-ea0cfc76d5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11588
21438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1158821438
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1094446398
Short name T2024
Test name
Test status
Simulation time 176517333 ps
CPU time 0.92 seconds
Started Jun 30 06:20:49 PM PDT 24
Finished Jun 30 06:20:51 PM PDT 24
Peak memory 206192 kb
Host smart-a775d83c-e153-463b-adba-9ca954e2116b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10944
46398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1094446398
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3172785238
Short name T2252
Test name
Test status
Simulation time 178170992 ps
CPU time 0.87 seconds
Started Jun 30 06:20:47 PM PDT 24
Finished Jun 30 06:20:49 PM PDT 24
Peak memory 206196 kb
Host smart-0488ff55-eb4d-47a3-810d-c8f924781b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31727
85238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3172785238
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.3375368511
Short name T446
Test name
Test status
Simulation time 16823679802 ps
CPU time 394.48 seconds
Started Jun 30 06:20:46 PM PDT 24
Finished Jun 30 06:27:21 PM PDT 24
Peak memory 206496 kb
Host smart-655bc76a-8af3-4722-ab97-ca3531ad136f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3375368511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3375368511
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.21825947
Short name T1546
Test name
Test status
Simulation time 8109520982 ps
CPU time 47.86 seconds
Started Jun 30 06:20:45 PM PDT 24
Finished Jun 30 06:21:33 PM PDT 24
Peak memory 206500 kb
Host smart-afd9d02d-f2bc-498c-abef-845d3c0cce3c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=21825947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.21825947
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.112239407
Short name T636
Test name
Test status
Simulation time 16297787045 ps
CPU time 114.86 seconds
Started Jun 30 06:20:49 PM PDT 24
Finished Jun 30 06:22:45 PM PDT 24
Peak memory 206440 kb
Host smart-00d57554-9556-46eb-a0f1-98005a3cacd4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=112239407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.112239407
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1974236899
Short name T1591
Test name
Test status
Simulation time 247539367 ps
CPU time 0.89 seconds
Started Jun 30 06:20:47 PM PDT 24
Finished Jun 30 06:20:48 PM PDT 24
Peak memory 206216 kb
Host smart-1c949abc-a515-459c-a91e-e633ac2c1954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19742
36899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1974236899
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1823673291
Short name T2296
Test name
Test status
Simulation time 210482916 ps
CPU time 0.87 seconds
Started Jun 30 06:20:49 PM PDT 24
Finished Jun 30 06:20:50 PM PDT 24
Peak memory 206196 kb
Host smart-ccddd953-9faa-4d81-8c7f-7d2188d95bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18236
73291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1823673291
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3511767655
Short name T469
Test name
Test status
Simulation time 150977678 ps
CPU time 0.75 seconds
Started Jun 30 06:20:55 PM PDT 24
Finished Jun 30 06:20:56 PM PDT 24
Peak memory 206152 kb
Host smart-f0f1bd46-d469-4ab3-9b65-3f62aaf5827f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35117
67655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3511767655
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.4251822174
Short name T2312
Test name
Test status
Simulation time 191894296 ps
CPU time 0.86 seconds
Started Jun 30 06:20:50 PM PDT 24
Finished Jun 30 06:20:51 PM PDT 24
Peak memory 206196 kb
Host smart-ecf3bce6-29d7-4367-9f06-26cc59ae08b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42518
22174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.4251822174
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.1231430396
Short name T1845
Test name
Test status
Simulation time 429453733 ps
CPU time 1.41 seconds
Started Jun 30 06:20:55 PM PDT 24
Finished Jun 30 06:20:57 PM PDT 24
Peak memory 206212 kb
Host smart-44456419-7fca-4cc6-9052-e5278bf967f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12314
30396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.1231430396
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3190946474
Short name T1996
Test name
Test status
Simulation time 184973264 ps
CPU time 0.85 seconds
Started Jun 30 06:20:55 PM PDT 24
Finished Jun 30 06:20:56 PM PDT 24
Peak memory 206196 kb
Host smart-e71e22e0-8926-4133-aa13-c46ec97b4836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31909
46474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3190946474
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3292242772
Short name T2616
Test name
Test status
Simulation time 144881600 ps
CPU time 0.73 seconds
Started Jun 30 06:20:56 PM PDT 24
Finished Jun 30 06:20:58 PM PDT 24
Peak memory 206188 kb
Host smart-714c6f70-53e8-4551-b3ad-70b415ef57f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32922
42772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3292242772
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.4177350663
Short name T1242
Test name
Test status
Simulation time 164807878 ps
CPU time 0.8 seconds
Started Jun 30 06:20:56 PM PDT 24
Finished Jun 30 06:20:57 PM PDT 24
Peak memory 206172 kb
Host smart-d71ea00e-53b3-46ac-bc3d-56920bc7c539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41773
50663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.4177350663
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2843525544
Short name T522
Test name
Test status
Simulation time 251448615 ps
CPU time 1.01 seconds
Started Jun 30 06:20:57 PM PDT 24
Finished Jun 30 06:20:58 PM PDT 24
Peak memory 206200 kb
Host smart-ea2da94f-f4d4-4bfa-9384-d64f1deb3885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28435
25544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2843525544
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.2895404722
Short name T833
Test name
Test status
Simulation time 6381317210 ps
CPU time 62.24 seconds
Started Jun 30 06:20:54 PM PDT 24
Finished Jun 30 06:21:57 PM PDT 24
Peak memory 206424 kb
Host smart-8fa4640a-01d4-49e9-923e-ff39e5bca763
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2895404722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.2895404722
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3992619158
Short name T1039
Test name
Test status
Simulation time 193262705 ps
CPU time 0.9 seconds
Started Jun 30 06:20:56 PM PDT 24
Finished Jun 30 06:20:57 PM PDT 24
Peak memory 206220 kb
Host smart-bf68ec27-92d9-446d-81b6-acaa451685c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39926
19158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3992619158
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.39139955
Short name T641
Test name
Test status
Simulation time 230532011 ps
CPU time 0.93 seconds
Started Jun 30 06:20:58 PM PDT 24
Finished Jun 30 06:21:00 PM PDT 24
Peak memory 206156 kb
Host smart-4384a884-a0a2-4b44-87d6-266821d5186c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39139
955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.39139955
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3636991215
Short name T822
Test name
Test status
Simulation time 5453079454 ps
CPU time 40.77 seconds
Started Jun 30 06:20:55 PM PDT 24
Finished Jun 30 06:21:36 PM PDT 24
Peak memory 206464 kb
Host smart-b639addf-5736-441e-a909-40734f110bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36369
91215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3636991215
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.429278801
Short name T1492
Test name
Test status
Simulation time 9095532933 ps
CPU time 83.89 seconds
Started Jun 30 06:20:56 PM PDT 24
Finished Jun 30 06:22:21 PM PDT 24
Peak memory 206428 kb
Host smart-4e9b96af-3ce7-4a35-b3b5-d7e5d90c8b0a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=429278801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.429278801
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3456179563
Short name T2035
Test name
Test status
Simulation time 60310792 ps
CPU time 0.72 seconds
Started Jun 30 06:25:59 PM PDT 24
Finished Jun 30 06:26:00 PM PDT 24
Peak memory 206212 kb
Host smart-ddb64a6e-5b6c-4718-aed1-231b512cd70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3456179563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3456179563
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3641638105
Short name T1200
Test name
Test status
Simulation time 3490860965 ps
CPU time 4.02 seconds
Started Jun 30 06:25:45 PM PDT 24
Finished Jun 30 06:25:49 PM PDT 24
Peak memory 206248 kb
Host smart-4356efab-98aa-4d11-9bcd-250bb34e175e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3641638105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3641638105
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3932341156
Short name T1547
Test name
Test status
Simulation time 13363012366 ps
CPU time 14.94 seconds
Started Jun 30 06:25:52 PM PDT 24
Finished Jun 30 06:26:07 PM PDT 24
Peak memory 206300 kb
Host smart-7004600f-5594-4afd-8bee-cfdb78b2dcbc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3932341156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3932341156
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3681536122
Short name T954
Test name
Test status
Simulation time 23388712515 ps
CPU time 23.7 seconds
Started Jun 30 06:25:47 PM PDT 24
Finished Jun 30 06:26:11 PM PDT 24
Peak memory 206320 kb
Host smart-8bc26bfc-70c5-4de6-9f45-d3e13f7e707a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3681536122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3681536122
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1354013958
Short name T1824
Test name
Test status
Simulation time 162743243 ps
CPU time 0.73 seconds
Started Jun 30 06:25:33 PM PDT 24
Finished Jun 30 06:25:37 PM PDT 24
Peak memory 206156 kb
Host smart-5134a225-a43c-478e-8d15-fdcfe6869a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13540
13958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1354013958
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3921242743
Short name T1155
Test name
Test status
Simulation time 187561593 ps
CPU time 0.84 seconds
Started Jun 30 06:25:42 PM PDT 24
Finished Jun 30 06:25:43 PM PDT 24
Peak memory 206212 kb
Host smart-ecfcfbdf-dfef-42e0-be52-a9ae6a6212ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39212
42743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3921242743
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3209241363
Short name T1983
Test name
Test status
Simulation time 187970132 ps
CPU time 0.85 seconds
Started Jun 30 06:25:44 PM PDT 24
Finished Jun 30 06:25:45 PM PDT 24
Peak memory 206176 kb
Host smart-af415389-6793-4662-a0f8-ce45b1027117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32092
41363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3209241363
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2624563377
Short name T1761
Test name
Test status
Simulation time 450544472 ps
CPU time 1.31 seconds
Started Jun 30 06:25:49 PM PDT 24
Finished Jun 30 06:25:51 PM PDT 24
Peak memory 206188 kb
Host smart-282ce0f4-f96f-4203-a65d-96d8cca18805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26245
63377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2624563377
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1378806710
Short name T93
Test name
Test status
Simulation time 20752878583 ps
CPU time 40.54 seconds
Started Jun 30 06:25:52 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206408 kb
Host smart-1f19c2bb-0433-4c58-9fc9-7ba78f1be8df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13788
06710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1378806710
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2423626636
Short name T658
Test name
Test status
Simulation time 488009455 ps
CPU time 1.44 seconds
Started Jun 30 06:25:43 PM PDT 24
Finished Jun 30 06:25:45 PM PDT 24
Peak memory 206188 kb
Host smart-9cc0c8c6-eb43-450e-a17f-7188b191bd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24236
26636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2423626636
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1507675055
Short name T2140
Test name
Test status
Simulation time 139087330 ps
CPU time 0.76 seconds
Started Jun 30 06:25:43 PM PDT 24
Finished Jun 30 06:25:44 PM PDT 24
Peak memory 206188 kb
Host smart-15ec677a-63d8-43d7-ae4a-60cd07f211e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15076
75055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1507675055
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.778664140
Short name T501
Test name
Test status
Simulation time 35556663 ps
CPU time 0.71 seconds
Started Jun 30 06:25:40 PM PDT 24
Finished Jun 30 06:25:41 PM PDT 24
Peak memory 206192 kb
Host smart-29cd6a49-4a76-4bd4-851e-b6955f6dc876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77866
4140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.778664140
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.1290573622
Short name T850
Test name
Test status
Simulation time 789666049 ps
CPU time 1.89 seconds
Started Jun 30 06:25:44 PM PDT 24
Finished Jun 30 06:25:47 PM PDT 24
Peak memory 206288 kb
Host smart-010b7f5d-1499-4a06-8e7a-92737e218400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12905
73622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.1290573622
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1796104149
Short name T576
Test name
Test status
Simulation time 169688449 ps
CPU time 1.6 seconds
Started Jun 30 06:25:44 PM PDT 24
Finished Jun 30 06:25:46 PM PDT 24
Peak memory 206368 kb
Host smart-5361298b-9d14-491a-903c-0b387eaa7e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17961
04149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1796104149
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3659033084
Short name T530
Test name
Test status
Simulation time 192759350 ps
CPU time 0.94 seconds
Started Jun 30 06:26:02 PM PDT 24
Finished Jun 30 06:26:04 PM PDT 24
Peak memory 206044 kb
Host smart-607f0085-552b-4e80-bda7-db87b10427ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36590
33084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3659033084
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3043266061
Short name T1470
Test name
Test status
Simulation time 150946752 ps
CPU time 0.77 seconds
Started Jun 30 06:25:59 PM PDT 24
Finished Jun 30 06:26:00 PM PDT 24
Peak memory 206204 kb
Host smart-adb9c6ba-6413-4111-8527-25bf8899553a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30432
66061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3043266061
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.734028351
Short name T660
Test name
Test status
Simulation time 219100546 ps
CPU time 0.95 seconds
Started Jun 30 06:25:45 PM PDT 24
Finished Jun 30 06:25:47 PM PDT 24
Peak memory 206204 kb
Host smart-f0b6d791-5b6e-44dc-bc0e-fae23953b5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73402
8351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.734028351
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.517751604
Short name T1860
Test name
Test status
Simulation time 9785606282 ps
CPU time 66.38 seconds
Started Jun 30 06:25:48 PM PDT 24
Finished Jun 30 06:26:55 PM PDT 24
Peak memory 206444 kb
Host smart-1805b4aa-2ca5-43c1-a53e-ad2deb12e860
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=517751604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.517751604
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.576217676
Short name T359
Test name
Test status
Simulation time 177076268 ps
CPU time 0.83 seconds
Started Jun 30 06:26:02 PM PDT 24
Finished Jun 30 06:26:04 PM PDT 24
Peak memory 206048 kb
Host smart-ae9491a9-8894-46a9-9bc1-4594dc89b3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57621
7676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.576217676
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.147574455
Short name T2454
Test name
Test status
Simulation time 23275702147 ps
CPU time 23.69 seconds
Started Jun 30 06:25:45 PM PDT 24
Finished Jun 30 06:26:09 PM PDT 24
Peak memory 206312 kb
Host smart-f8d64473-16e3-4cda-ba77-669125228b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14757
4455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.147574455
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3713598443
Short name T745
Test name
Test status
Simulation time 3271743369 ps
CPU time 3.81 seconds
Started Jun 30 06:25:56 PM PDT 24
Finished Jun 30 06:26:00 PM PDT 24
Peak memory 206244 kb
Host smart-69792d2e-71c7-44ff-b088-0f869b0627d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37135
98443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3713598443
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.4100247952
Short name T1976
Test name
Test status
Simulation time 13094823451 ps
CPU time 362.31 seconds
Started Jun 30 06:25:45 PM PDT 24
Finished Jun 30 06:31:48 PM PDT 24
Peak memory 206440 kb
Host smart-6c732f82-35e6-4d68-8016-2450dac8d3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41002
47952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.4100247952
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.3275056854
Short name T1687
Test name
Test status
Simulation time 4728029746 ps
CPU time 43.43 seconds
Started Jun 30 06:25:48 PM PDT 24
Finished Jun 30 06:26:32 PM PDT 24
Peak memory 206456 kb
Host smart-e11917bf-468a-4aca-88b1-9e4883646c8e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3275056854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.3275056854
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2362808601
Short name T548
Test name
Test status
Simulation time 238825544 ps
CPU time 0.98 seconds
Started Jun 30 06:25:57 PM PDT 24
Finished Jun 30 06:25:59 PM PDT 24
Peak memory 206156 kb
Host smart-2fe12fc7-15dc-4521-8796-efc9914be0cc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2362808601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2362808601
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.79316926
Short name T1535
Test name
Test status
Simulation time 180749769 ps
CPU time 0.89 seconds
Started Jun 30 06:25:57 PM PDT 24
Finished Jun 30 06:25:59 PM PDT 24
Peak memory 206208 kb
Host smart-015c5f1d-f21b-4fd2-9ab6-6c341687cc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79316
926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.79316926
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1351440813
Short name T1407
Test name
Test status
Simulation time 4353045478 ps
CPU time 31.77 seconds
Started Jun 30 06:25:43 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206404 kb
Host smart-41e8caff-6f30-482b-beea-31e4c069db08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13514
40813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1351440813
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.2234246000
Short name T729
Test name
Test status
Simulation time 4282343296 ps
CPU time 34.4 seconds
Started Jun 30 06:25:46 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 206484 kb
Host smart-ec5b9272-02c7-4e71-be24-63b0c6a963dc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2234246000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.2234246000
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3429551207
Short name T1548
Test name
Test status
Simulation time 152510458 ps
CPU time 0.79 seconds
Started Jun 30 06:25:45 PM PDT 24
Finished Jun 30 06:25:47 PM PDT 24
Peak memory 206200 kb
Host smart-f3a209b9-d2e1-4175-b235-d2dbb637c294
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3429551207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3429551207
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1463016867
Short name T1103
Test name
Test status
Simulation time 155507116 ps
CPU time 0.77 seconds
Started Jun 30 06:25:43 PM PDT 24
Finished Jun 30 06:25:44 PM PDT 24
Peak memory 206200 kb
Host smart-5d1308bc-1ebd-41f9-ac36-8edd52162417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14630
16867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1463016867
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1405430921
Short name T498
Test name
Test status
Simulation time 231176446 ps
CPU time 0.88 seconds
Started Jun 30 06:25:50 PM PDT 24
Finished Jun 30 06:25:51 PM PDT 24
Peak memory 206204 kb
Host smart-cbe66b71-79ab-4d54-ba60-90367b54845a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14054
30921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1405430921
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3094238647
Short name T1673
Test name
Test status
Simulation time 158951418 ps
CPU time 0.84 seconds
Started Jun 30 06:25:46 PM PDT 24
Finished Jun 30 06:25:48 PM PDT 24
Peak memory 206192 kb
Host smart-a8b9e984-412f-4937-aa93-07024dd95866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30942
38647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3094238647
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3186485141
Short name T1519
Test name
Test status
Simulation time 156190656 ps
CPU time 0.77 seconds
Started Jun 30 06:25:55 PM PDT 24
Finished Jun 30 06:25:56 PM PDT 24
Peak memory 206200 kb
Host smart-a9c6d727-9fca-4bee-b942-dd395863559c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31864
85141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3186485141
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3573440390
Short name T1174
Test name
Test status
Simulation time 151570121 ps
CPU time 0.83 seconds
Started Jun 30 06:25:57 PM PDT 24
Finished Jun 30 06:25:58 PM PDT 24
Peak memory 206220 kb
Host smart-819aa97b-916a-4b3d-89f5-706400b6ed48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35734
40390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3573440390
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.769046843
Short name T177
Test name
Test status
Simulation time 153385319 ps
CPU time 0.84 seconds
Started Jun 30 06:25:46 PM PDT 24
Finished Jun 30 06:25:47 PM PDT 24
Peak memory 206204 kb
Host smart-ea23b6d0-a438-4e6a-b69a-f650c0876580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76904
6843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.769046843
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.3183758519
Short name T1139
Test name
Test status
Simulation time 234805817 ps
CPU time 0.92 seconds
Started Jun 30 06:25:43 PM PDT 24
Finished Jun 30 06:25:45 PM PDT 24
Peak memory 206196 kb
Host smart-e3c6552d-2bab-4b6b-82fd-9fb84fcba6f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3183758519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3183758519
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3458720873
Short name T1786
Test name
Test status
Simulation time 153875964 ps
CPU time 0.76 seconds
Started Jun 30 06:25:49 PM PDT 24
Finished Jun 30 06:25:50 PM PDT 24
Peak memory 206200 kb
Host smart-ed9407bb-3bd1-4828-bd36-ec3423c4f80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34587
20873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3458720873
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2138735525
Short name T2001
Test name
Test status
Simulation time 24589554418 ps
CPU time 54.74 seconds
Started Jun 30 06:25:48 PM PDT 24
Finished Jun 30 06:26:44 PM PDT 24
Peak memory 206452 kb
Host smart-2175e679-a3d9-4936-9f3f-863c7b75d36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21387
35525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2138735525
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2197040508
Short name T683
Test name
Test status
Simulation time 186204236 ps
CPU time 0.81 seconds
Started Jun 30 06:25:50 PM PDT 24
Finished Jun 30 06:25:51 PM PDT 24
Peak memory 206188 kb
Host smart-4093f25e-c908-4e57-96b6-2df990f06492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21970
40508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2197040508
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1171546104
Short name T1523
Test name
Test status
Simulation time 170276249 ps
CPU time 0.8 seconds
Started Jun 30 06:25:57 PM PDT 24
Finished Jun 30 06:25:58 PM PDT 24
Peak memory 206172 kb
Host smart-66de37f2-76df-4796-bb2e-cd497121dc8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11715
46104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1171546104
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.3188870377
Short name T1497
Test name
Test status
Simulation time 213252407 ps
CPU time 0.83 seconds
Started Jun 30 06:25:53 PM PDT 24
Finished Jun 30 06:25:54 PM PDT 24
Peak memory 206196 kb
Host smart-d5790c96-2ca2-4c7b-b5d5-8cb3a3274aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31888
70377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.3188870377
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1384902292
Short name T2381
Test name
Test status
Simulation time 172409456 ps
CPU time 0.83 seconds
Started Jun 30 06:26:04 PM PDT 24
Finished Jun 30 06:26:06 PM PDT 24
Peak memory 206192 kb
Host smart-9b4a87bd-b50f-427b-b4c1-8a23ab3326f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13849
02292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1384902292
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.22051875
Short name T1554
Test name
Test status
Simulation time 151586515 ps
CPU time 0.82 seconds
Started Jun 30 06:25:54 PM PDT 24
Finished Jun 30 06:25:56 PM PDT 24
Peak memory 206172 kb
Host smart-26bcfc01-d00f-4b53-bb10-c7fb99133a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22051
875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.22051875
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.401127180
Short name T597
Test name
Test status
Simulation time 180482123 ps
CPU time 0.88 seconds
Started Jun 30 06:25:59 PM PDT 24
Finished Jun 30 06:26:01 PM PDT 24
Peak memory 206172 kb
Host smart-c2af1ca2-67d3-419d-b4dc-ee5b157e795a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40112
7180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.401127180
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2630473201
Short name T1147
Test name
Test status
Simulation time 145548920 ps
CPU time 0.76 seconds
Started Jun 30 06:25:53 PM PDT 24
Finished Jun 30 06:25:54 PM PDT 24
Peak memory 206164 kb
Host smart-3ab87a2c-5905-42cf-a9b7-0bf95df52eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26304
73201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2630473201
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3880911642
Short name T757
Test name
Test status
Simulation time 214701511 ps
CPU time 0.96 seconds
Started Jun 30 06:26:24 PM PDT 24
Finished Jun 30 06:26:26 PM PDT 24
Peak memory 206176 kb
Host smart-985cac2d-2f91-4554-979f-7d31577f3c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
11642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3880911642
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2580647399
Short name T749
Test name
Test status
Simulation time 3964118717 ps
CPU time 108.54 seconds
Started Jun 30 06:26:05 PM PDT 24
Finished Jun 30 06:27:55 PM PDT 24
Peak memory 206412 kb
Host smart-c131a37b-c9d0-473c-86b5-cdbae7bf1cd5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2580647399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2580647399
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.970262823
Short name T1950
Test name
Test status
Simulation time 144299481 ps
CPU time 0.81 seconds
Started Jun 30 06:26:01 PM PDT 24
Finished Jun 30 06:26:02 PM PDT 24
Peak memory 206068 kb
Host smart-80c2e73c-9855-4c8b-b846-3921642292ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97026
2823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.970262823
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1512904953
Short name T561
Test name
Test status
Simulation time 182268848 ps
CPU time 0.84 seconds
Started Jun 30 06:26:00 PM PDT 24
Finished Jun 30 06:26:01 PM PDT 24
Peak memory 206184 kb
Host smart-28a22968-bcef-4507-bc54-57de619fd4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15129
04953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1512904953
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3998680964
Short name T677
Test name
Test status
Simulation time 4028397360 ps
CPU time 28.24 seconds
Started Jun 30 06:26:11 PM PDT 24
Finished Jun 30 06:26:40 PM PDT 24
Peak memory 206288 kb
Host smart-81e59101-d485-4663-a68c-c1ca8aad4268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39986
80964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3998680964
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1798133991
Short name T1945
Test name
Test status
Simulation time 48075772 ps
CPU time 0.66 seconds
Started Jun 30 06:26:06 PM PDT 24
Finished Jun 30 06:26:07 PM PDT 24
Peak memory 206208 kb
Host smart-013741ee-c3a4-4560-804f-d4b3e6567dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1798133991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1798133991
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.916800404
Short name T2056
Test name
Test status
Simulation time 4360665705 ps
CPU time 4.76 seconds
Started Jun 30 06:25:50 PM PDT 24
Finished Jun 30 06:25:55 PM PDT 24
Peak memory 206316 kb
Host smart-b857634a-fc2a-4b65-ae0f-25234e0516da
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=916800404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.916800404
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.2470014793
Short name T10
Test name
Test status
Simulation time 13489748827 ps
CPU time 16.78 seconds
Started Jun 30 06:25:48 PM PDT 24
Finished Jun 30 06:26:06 PM PDT 24
Peak memory 206380 kb
Host smart-0e07cb57-bce8-428c-8614-a0dc8fa68e75
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2470014793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.2470014793
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.496474400
Short name T2334
Test name
Test status
Simulation time 23338260580 ps
CPU time 29.23 seconds
Started Jun 30 06:25:52 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 206296 kb
Host smart-80cd23a1-69b0-4028-99a9-4dd59f255a98
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=496474400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.496474400
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.324367226
Short name T2220
Test name
Test status
Simulation time 169736685 ps
CPU time 0.86 seconds
Started Jun 30 06:26:01 PM PDT 24
Finished Jun 30 06:26:03 PM PDT 24
Peak memory 206176 kb
Host smart-7d419e5f-a10f-4430-8bac-fc3ac4cd5be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32436
7226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.324367226
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.871256342
Short name T2556
Test name
Test status
Simulation time 223183537 ps
CPU time 0.89 seconds
Started Jun 30 06:25:56 PM PDT 24
Finished Jun 30 06:25:57 PM PDT 24
Peak memory 206156 kb
Host smart-992c7df6-93aa-46c9-8713-78bd97ff2837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87125
6342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.871256342
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2477397018
Short name T182
Test name
Test status
Simulation time 450165130 ps
CPU time 1.32 seconds
Started Jun 30 06:25:48 PM PDT 24
Finished Jun 30 06:25:50 PM PDT 24
Peak memory 206184 kb
Host smart-282d3f46-9252-4d97-8d7e-6a7f5030dd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24773
97018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2477397018
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1178131737
Short name T1562
Test name
Test status
Simulation time 863922351 ps
CPU time 2.16 seconds
Started Jun 30 06:25:48 PM PDT 24
Finished Jun 30 06:25:50 PM PDT 24
Peak memory 206268 kb
Host smart-63897082-a1eb-4052-b250-01d15d4551cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11781
31737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1178131737
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2586934766
Short name T1158
Test name
Test status
Simulation time 21211412294 ps
CPU time 37.76 seconds
Started Jun 30 06:26:04 PM PDT 24
Finished Jun 30 06:26:42 PM PDT 24
Peak memory 206408 kb
Host smart-b9dc7deb-3c8a-4c5f-b8f8-2db2640c96d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25869
34766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2586934766
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.185260945
Short name T1711
Test name
Test status
Simulation time 367594656 ps
CPU time 1.24 seconds
Started Jun 30 06:26:04 PM PDT 24
Finished Jun 30 06:26:06 PM PDT 24
Peak memory 206216 kb
Host smart-1827e4cb-70e3-49ee-be89-bd7a75249626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18526
0945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.185260945
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.4123093156
Short name T1331
Test name
Test status
Simulation time 235931135 ps
CPU time 0.87 seconds
Started Jun 30 06:26:02 PM PDT 24
Finished Jun 30 06:26:04 PM PDT 24
Peak memory 206172 kb
Host smart-3dcd249a-5dde-49c1-91e2-5491ecfe1a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41230
93156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.4123093156
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.954921465
Short name T388
Test name
Test status
Simulation time 37269987 ps
CPU time 0.63 seconds
Started Jun 30 06:26:02 PM PDT 24
Finished Jun 30 06:26:04 PM PDT 24
Peak memory 206200 kb
Host smart-1d601db6-12ae-461a-987e-6f6666428b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95492
1465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.954921465
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3929641875
Short name T1725
Test name
Test status
Simulation time 770316205 ps
CPU time 2.04 seconds
Started Jun 30 06:25:59 PM PDT 24
Finished Jun 30 06:26:02 PM PDT 24
Peak memory 206268 kb
Host smart-76cdb76a-12c7-406d-bb7c-abb57443cb9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39296
41875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3929641875
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2596340363
Short name T1859
Test name
Test status
Simulation time 155337447 ps
CPU time 1.3 seconds
Started Jun 30 06:25:57 PM PDT 24
Finished Jun 30 06:25:59 PM PDT 24
Peak memory 206272 kb
Host smart-9f1d383e-a864-419b-b7c2-ab2ed22befa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25963
40363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2596340363
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1183887297
Short name T1863
Test name
Test status
Simulation time 227969094 ps
CPU time 0.95 seconds
Started Jun 30 06:26:00 PM PDT 24
Finished Jun 30 06:26:01 PM PDT 24
Peak memory 206188 kb
Host smart-ee2386ce-ae65-44d9-b9c9-15c36ce76aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11838
87297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1183887297
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1639154250
Short name T2505
Test name
Test status
Simulation time 146894892 ps
CPU time 0.76 seconds
Started Jun 30 06:25:53 PM PDT 24
Finished Jun 30 06:25:54 PM PDT 24
Peak memory 206188 kb
Host smart-a5a06fdf-f403-4bc8-a270-8f0edae5705a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16391
54250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1639154250
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1875053589
Short name T1956
Test name
Test status
Simulation time 188806432 ps
CPU time 0.82 seconds
Started Jun 30 06:26:00 PM PDT 24
Finished Jun 30 06:26:01 PM PDT 24
Peak memory 206212 kb
Host smart-b276b0f9-455f-4ef2-a45d-b3008fe372e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18750
53589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1875053589
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.705832883
Short name T2502
Test name
Test status
Simulation time 7641313320 ps
CPU time 53.2 seconds
Started Jun 30 06:25:48 PM PDT 24
Finished Jun 30 06:26:42 PM PDT 24
Peak memory 206380 kb
Host smart-64bc5007-0d5e-40c4-a7e1-7ba4ce050a95
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=705832883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.705832883
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2278580644
Short name T1084
Test name
Test status
Simulation time 209100207 ps
CPU time 0.86 seconds
Started Jun 30 06:25:51 PM PDT 24
Finished Jun 30 06:25:52 PM PDT 24
Peak memory 206196 kb
Host smart-6bc9ac50-870f-429a-b20c-b77314e67deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22785
80644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2278580644
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.1535747628
Short name T2148
Test name
Test status
Simulation time 23308463200 ps
CPU time 20.92 seconds
Started Jun 30 06:26:00 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 206308 kb
Host smart-ca32d892-09f1-46bb-9dcb-d5c8085dd2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15357
47628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1535747628
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.4090940291
Short name T670
Test name
Test status
Simulation time 3318571761 ps
CPU time 4.27 seconds
Started Jun 30 06:25:58 PM PDT 24
Finished Jun 30 06:26:03 PM PDT 24
Peak memory 206244 kb
Host smart-48ed9655-1d0a-4a03-9308-e5ad91246ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40909
40291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.4090940291
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2900287628
Short name T562
Test name
Test status
Simulation time 8612009187 ps
CPU time 236.46 seconds
Started Jun 30 06:25:59 PM PDT 24
Finished Jun 30 06:29:56 PM PDT 24
Peak memory 206460 kb
Host smart-742fbd31-d64c-497e-bafa-b1684b7569f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29002
87628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2900287628
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2536816471
Short name T1358
Test name
Test status
Simulation time 3651962248 ps
CPU time 33.57 seconds
Started Jun 30 06:26:07 PM PDT 24
Finished Jun 30 06:26:41 PM PDT 24
Peak memory 206376 kb
Host smart-c4223241-9206-47dc-9d9e-f733c1c0b77c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2536816471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2536816471
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.2614260507
Short name T1473
Test name
Test status
Simulation time 275855649 ps
CPU time 0.97 seconds
Started Jun 30 06:25:57 PM PDT 24
Finished Jun 30 06:25:58 PM PDT 24
Peak memory 206180 kb
Host smart-0e7ca059-e758-4b85-9981-9318fab1bb3a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2614260507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.2614260507
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.127358183
Short name T1720
Test name
Test status
Simulation time 195075103 ps
CPU time 0.92 seconds
Started Jun 30 06:26:03 PM PDT 24
Finished Jun 30 06:26:05 PM PDT 24
Peak memory 206208 kb
Host smart-35d56715-17c5-434c-a25e-fc0f58d15706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12735
8183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.127358183
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.1935113516
Short name T2271
Test name
Test status
Simulation time 5955225302 ps
CPU time 161.84 seconds
Started Jun 30 06:26:09 PM PDT 24
Finished Jun 30 06:28:52 PM PDT 24
Peak memory 206496 kb
Host smart-d93f2673-5e32-4e16-ae7e-3adeca258299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19351
13516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.1935113516
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2467026985
Short name T1696
Test name
Test status
Simulation time 6293525453 ps
CPU time 168.75 seconds
Started Jun 30 06:26:08 PM PDT 24
Finished Jun 30 06:28:58 PM PDT 24
Peak memory 206480 kb
Host smart-0fd670cf-447b-4b8c-a3df-f0a38c2959cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2467026985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2467026985
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.1322277683
Short name T2338
Test name
Test status
Simulation time 171679861 ps
CPU time 0.81 seconds
Started Jun 30 06:26:04 PM PDT 24
Finished Jun 30 06:26:06 PM PDT 24
Peak memory 206212 kb
Host smart-e2ff52e9-0839-4a89-abd0-f70f524810bf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1322277683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1322277683
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.993157901
Short name T338
Test name
Test status
Simulation time 156388767 ps
CPU time 0.82 seconds
Started Jun 30 06:25:57 PM PDT 24
Finished Jun 30 06:25:58 PM PDT 24
Peak memory 206220 kb
Host smart-2db3d4ed-ea39-472d-9f87-136cfdc09e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99315
7901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.993157901
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3833244678
Short name T129
Test name
Test status
Simulation time 248968853 ps
CPU time 0.91 seconds
Started Jun 30 06:26:03 PM PDT 24
Finished Jun 30 06:26:05 PM PDT 24
Peak memory 206196 kb
Host smart-32498887-8a82-4195-b081-fab2252d9b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38332
44678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3833244678
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1361471785
Short name T2028
Test name
Test status
Simulation time 188572864 ps
CPU time 0.96 seconds
Started Jun 30 06:26:03 PM PDT 24
Finished Jun 30 06:26:05 PM PDT 24
Peak memory 206200 kb
Host smart-eca81f08-b675-4163-9fd1-9a0337538bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13614
71785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1361471785
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.591525099
Short name T1485
Test name
Test status
Simulation time 162764329 ps
CPU time 0.81 seconds
Started Jun 30 06:26:23 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206188 kb
Host smart-24111891-5c14-4790-a8e0-1ae8b3a0d2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59152
5099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.591525099
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2139300638
Short name T2500
Test name
Test status
Simulation time 183038697 ps
CPU time 0.78 seconds
Started Jun 30 06:25:57 PM PDT 24
Finished Jun 30 06:25:59 PM PDT 24
Peak memory 206212 kb
Host smart-4f65cab4-1d81-439c-a5c1-345a8ca9437a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21393
00638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2139300638
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2311065542
Short name T1680
Test name
Test status
Simulation time 169250491 ps
CPU time 0.85 seconds
Started Jun 30 06:26:03 PM PDT 24
Finished Jun 30 06:26:05 PM PDT 24
Peak memory 206196 kb
Host smart-2b210506-ff94-4498-944b-65f467adc281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23110
65542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2311065542
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2534238811
Short name T1379
Test name
Test status
Simulation time 234300835 ps
CPU time 0.94 seconds
Started Jun 30 06:26:24 PM PDT 24
Finished Jun 30 06:26:26 PM PDT 24
Peak memory 206208 kb
Host smart-d805364b-1c1e-4cac-b5c1-6484cd9f6f3f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2534238811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2534238811
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3815484986
Short name T639
Test name
Test status
Simulation time 168850178 ps
CPU time 0.77 seconds
Started Jun 30 06:26:05 PM PDT 24
Finished Jun 30 06:26:07 PM PDT 24
Peak memory 206200 kb
Host smart-98b59873-b1a2-4aff-9be9-c491cde62e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38154
84986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3815484986
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3608841246
Short name T825
Test name
Test status
Simulation time 34567943 ps
CPU time 0.66 seconds
Started Jun 30 06:26:00 PM PDT 24
Finished Jun 30 06:26:01 PM PDT 24
Peak memory 206204 kb
Host smart-fc8b9d40-f384-4214-83e5-e315fc89dbf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36088
41246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3608841246
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3113851974
Short name T1757
Test name
Test status
Simulation time 16203255625 ps
CPU time 33.68 seconds
Started Jun 30 06:26:09 PM PDT 24
Finished Jun 30 06:26:43 PM PDT 24
Peak memory 206388 kb
Host smart-ab4b6714-0151-4066-8134-417d6f787de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
51974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3113851974
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.333855488
Short name T2544
Test name
Test status
Simulation time 190217403 ps
CPU time 0.82 seconds
Started Jun 30 06:26:02 PM PDT 24
Finished Jun 30 06:26:04 PM PDT 24
Peak memory 206192 kb
Host smart-d2c74396-1781-4646-8b4a-a8c7719fb34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33385
5488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.333855488
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3182566193
Short name T1393
Test name
Test status
Simulation time 225415293 ps
CPU time 1 seconds
Started Jun 30 06:26:07 PM PDT 24
Finished Jun 30 06:26:09 PM PDT 24
Peak memory 206200 kb
Host smart-248fda87-f3b2-4191-8675-23fa86656a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31825
66193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3182566193
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.589733385
Short name T1475
Test name
Test status
Simulation time 184732102 ps
CPU time 0.83 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206176 kb
Host smart-4ec1f6bd-ba44-4d9f-ae72-e2fd67443e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58973
3385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.589733385
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3011548454
Short name T2472
Test name
Test status
Simulation time 235963036 ps
CPU time 0.86 seconds
Started Jun 30 06:26:06 PM PDT 24
Finished Jun 30 06:26:08 PM PDT 24
Peak memory 206140 kb
Host smart-59d875f3-f33f-42fa-a1d9-1c2df2a145f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30115
48454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3011548454
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1166849880
Short name T1771
Test name
Test status
Simulation time 154659540 ps
CPU time 0.8 seconds
Started Jun 30 06:26:01 PM PDT 24
Finished Jun 30 06:26:02 PM PDT 24
Peak memory 206184 kb
Host smart-1c974018-c90f-4f3e-a810-1ee89a4d2477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11668
49880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1166849880
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3524476424
Short name T1137
Test name
Test status
Simulation time 196899706 ps
CPU time 0.8 seconds
Started Jun 30 06:25:54 PM PDT 24
Finished Jun 30 06:25:55 PM PDT 24
Peak memory 206192 kb
Host smart-6a4442d4-d76c-4071-b602-f7025d4adee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35244
76424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3524476424
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2945144081
Short name T358
Test name
Test status
Simulation time 161409490 ps
CPU time 0.84 seconds
Started Jun 30 06:26:04 PM PDT 24
Finished Jun 30 06:26:06 PM PDT 24
Peak memory 206172 kb
Host smart-61fdf816-754f-4104-b77f-6af7b992200f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29451
44081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2945144081
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1976954131
Short name T2017
Test name
Test status
Simulation time 184692421 ps
CPU time 0.82 seconds
Started Jun 30 06:26:01 PM PDT 24
Finished Jun 30 06:26:02 PM PDT 24
Peak memory 206196 kb
Host smart-d82beed3-f429-4149-92a5-183ff2d69fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19769
54131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1976954131
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.230984605
Short name T1650
Test name
Test status
Simulation time 5792804101 ps
CPU time 55.37 seconds
Started Jun 30 06:26:04 PM PDT 24
Finished Jun 30 06:27:00 PM PDT 24
Peak memory 206408 kb
Host smart-d7dd3ae5-db25-44c9-82d9-0d002283829f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=230984605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.230984605
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.343185514
Short name T735
Test name
Test status
Simulation time 178454214 ps
CPU time 0.82 seconds
Started Jun 30 06:26:24 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206176 kb
Host smart-4676a9c7-d454-4d5d-8cfd-c8e1316d3cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34318
5514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.343185514
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3865027056
Short name T1691
Test name
Test status
Simulation time 222448765 ps
CPU time 0.97 seconds
Started Jun 30 06:26:13 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206188 kb
Host smart-d95afaed-6b2f-4c9a-b61c-ad02fcca8655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38650
27056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3865027056
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.4083226556
Short name T586
Test name
Test status
Simulation time 7570698597 ps
CPU time 69.98 seconds
Started Jun 30 06:26:09 PM PDT 24
Finished Jun 30 06:27:20 PM PDT 24
Peak memory 206380 kb
Host smart-7d67f460-5c91-4f64-b9c5-ea5cc6c8c2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40832
26556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.4083226556
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.3580460318
Short name T1109
Test name
Test status
Simulation time 41467903 ps
CPU time 0.67 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:32 PM PDT 24
Peak memory 206044 kb
Host smart-34c71dc2-afb1-4a37-8c52-c7b3b0563a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3580460318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.3580460318
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.555268252
Short name T2518
Test name
Test status
Simulation time 4403651298 ps
CPU time 4.95 seconds
Started Jun 30 06:26:02 PM PDT 24
Finished Jun 30 06:26:08 PM PDT 24
Peak memory 206408 kb
Host smart-a836b9c4-874d-4348-9020-21e321ad12e2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=555268252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.555268252
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2335593913
Short name T1193
Test name
Test status
Simulation time 13316564780 ps
CPU time 12.16 seconds
Started Jun 30 06:26:09 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 206456 kb
Host smart-e61bba3d-e005-47ae-a1b5-da479fa31ca4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2335593913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2335593913
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.2575378780
Short name T8
Test name
Test status
Simulation time 23369072947 ps
CPU time 24.55 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:39 PM PDT 24
Peak memory 206316 kb
Host smart-4c372a57-dcfd-4a1c-8ac4-c4f51a5fc6cc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2575378780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.2575378780
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.4112629786
Short name T668
Test name
Test status
Simulation time 174454271 ps
CPU time 0.8 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:11 PM PDT 24
Peak memory 206196 kb
Host smart-4debf42a-a93f-4bc1-ba68-683a4093fb95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41126
29786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.4112629786
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2019208991
Short name T1413
Test name
Test status
Simulation time 153118805 ps
CPU time 0.78 seconds
Started Jun 30 06:26:11 PM PDT 24
Finished Jun 30 06:26:13 PM PDT 24
Peak memory 206164 kb
Host smart-1beb9130-0659-4d36-b74f-9af133e2b7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20192
08991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2019208991
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.276409357
Short name T1676
Test name
Test status
Simulation time 297468900 ps
CPU time 1.08 seconds
Started Jun 30 06:26:08 PM PDT 24
Finished Jun 30 06:26:10 PM PDT 24
Peak memory 206148 kb
Host smart-6c4cdb5b-d0db-4657-a637-4ca16a849dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27640
9357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.276409357
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1277897381
Short name T2025
Test name
Test status
Simulation time 1232984759 ps
CPU time 2.89 seconds
Started Jun 30 06:26:11 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206304 kb
Host smart-3b4c931b-262f-43e6-97ed-54d71f8fff26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12778
97381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1277897381
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.1992448769
Short name T1321
Test name
Test status
Simulation time 11932099180 ps
CPU time 20.72 seconds
Started Jun 30 06:26:11 PM PDT 24
Finished Jun 30 06:26:34 PM PDT 24
Peak memory 206396 kb
Host smart-45e33591-cf9a-4c62-8b1f-e851f6d6103a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19924
48769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1992448769
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.348390965
Short name T1657
Test name
Test status
Simulation time 479198503 ps
CPU time 1.34 seconds
Started Jun 30 06:26:11 PM PDT 24
Finished Jun 30 06:26:14 PM PDT 24
Peak memory 206220 kb
Host smart-965f5822-fd4d-426c-9311-1ca0ee994c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34839
0965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.348390965
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1662520990
Short name T1341
Test name
Test status
Simulation time 155076123 ps
CPU time 0.8 seconds
Started Jun 30 06:26:03 PM PDT 24
Finished Jun 30 06:26:04 PM PDT 24
Peak memory 206192 kb
Host smart-03c056f6-e76b-4242-9bc0-fcb17b700bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16625
20990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1662520990
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2922054652
Short name T502
Test name
Test status
Simulation time 37544349 ps
CPU time 0.64 seconds
Started Jun 30 06:26:04 PM PDT 24
Finished Jun 30 06:26:06 PM PDT 24
Peak memory 206156 kb
Host smart-aa9ac467-a563-4325-be54-f2080a4243e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29220
54652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2922054652
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.209975508
Short name T1020
Test name
Test status
Simulation time 1087199616 ps
CPU time 2.52 seconds
Started Jun 30 06:26:07 PM PDT 24
Finished Jun 30 06:26:10 PM PDT 24
Peak memory 206280 kb
Host smart-79c21834-5492-44a1-ab39-b4ea6443f38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20997
5508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.209975508
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.74987757
Short name T1622
Test name
Test status
Simulation time 240573143 ps
CPU time 1.66 seconds
Started Jun 30 06:26:11 PM PDT 24
Finished Jun 30 06:26:13 PM PDT 24
Peak memory 206288 kb
Host smart-de7fcbdd-eee4-4b8d-9b4b-b30b99990c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74987
757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.74987757
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2819006774
Short name T1032
Test name
Test status
Simulation time 200948372 ps
CPU time 0.87 seconds
Started Jun 30 06:26:04 PM PDT 24
Finished Jun 30 06:26:06 PM PDT 24
Peak memory 206160 kb
Host smart-4f7832e2-049c-4cb5-a422-b72e27f13116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28190
06774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2819006774
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3149985939
Short name T1505
Test name
Test status
Simulation time 146320010 ps
CPU time 0.75 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:14 PM PDT 24
Peak memory 206204 kb
Host smart-fae81f50-8cf2-4c5b-89d6-423f5eae4f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31499
85939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3149985939
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2688634984
Short name T2438
Test name
Test status
Simulation time 197965029 ps
CPU time 0.92 seconds
Started Jun 30 06:26:09 PM PDT 24
Finished Jun 30 06:26:11 PM PDT 24
Peak memory 206196 kb
Host smart-4616a6aa-7663-46aa-beab-de87e6cbe3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26886
34984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2688634984
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1155202439
Short name T239
Test name
Test status
Simulation time 10076390876 ps
CPU time 282.05 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:30:53 PM PDT 24
Peak memory 206496 kb
Host smart-0c37863a-64d7-494d-ae51-c475811f5b4c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1155202439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1155202439
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.756478536
Short name T2401
Test name
Test status
Simulation time 205543390 ps
CPU time 0.84 seconds
Started Jun 30 06:26:24 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206168 kb
Host smart-ac86b4cf-bdca-4a0d-8fce-ea088d3f8e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75647
8536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.756478536
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.654425133
Short name T2341
Test name
Test status
Simulation time 23354231595 ps
CPU time 23.21 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:37 PM PDT 24
Peak memory 206260 kb
Host smart-83efb5b5-3582-4d46-9d8f-b1a0b3b7e360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65442
5133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.654425133
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2080607460
Short name T1564
Test name
Test status
Simulation time 3294955151 ps
CPU time 3.67 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:15 PM PDT 24
Peak memory 206248 kb
Host smart-f92ceda8-c21e-49f3-aabd-79c5096375fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20806
07460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2080607460
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.3973431786
Short name T1938
Test name
Test status
Simulation time 9234154928 ps
CPU time 66.17 seconds
Started Jun 30 06:26:22 PM PDT 24
Finished Jun 30 06:27:30 PM PDT 24
Peak memory 206444 kb
Host smart-8fe70660-03c3-45ba-9b48-26ff9cbbaf09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39734
31786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3973431786
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3436143974
Short name T2202
Test name
Test status
Simulation time 3320644068 ps
CPU time 32.09 seconds
Started Jun 30 06:26:22 PM PDT 24
Finished Jun 30 06:26:56 PM PDT 24
Peak memory 206384 kb
Host smart-b0baadae-e609-4cb5-968b-48839cc17ae4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3436143974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3436143974
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2189361385
Short name T1144
Test name
Test status
Simulation time 271310499 ps
CPU time 0.96 seconds
Started Jun 30 06:26:16 PM PDT 24
Finished Jun 30 06:26:18 PM PDT 24
Peak memory 206192 kb
Host smart-fb1161fc-f34f-4ec3-8299-5a06a948db9d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2189361385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2189361385
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.4277116783
Short name T1975
Test name
Test status
Simulation time 227616556 ps
CPU time 0.9 seconds
Started Jun 30 06:26:23 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206176 kb
Host smart-17c17e03-23fa-4970-8e94-b4351cbe1b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42771
16783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.4277116783
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.3679272157
Short name T1127
Test name
Test status
Simulation time 4512958979 ps
CPU time 33.31 seconds
Started Jun 30 06:26:07 PM PDT 24
Finished Jun 30 06:26:41 PM PDT 24
Peak memory 206592 kb
Host smart-d3c2e74b-6e6f-41d1-ab59-193fc76f7f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36792
72157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.3679272157
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3341764413
Short name T545
Test name
Test status
Simulation time 6835588229 ps
CPU time 184.17 seconds
Started Jun 30 06:26:13 PM PDT 24
Finished Jun 30 06:29:19 PM PDT 24
Peak memory 206460 kb
Host smart-aa329408-e4fe-4880-82b9-6791baa0d0fb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3341764413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3341764413
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.2798124014
Short name T1862
Test name
Test status
Simulation time 153135154 ps
CPU time 0.81 seconds
Started Jun 30 06:26:06 PM PDT 24
Finished Jun 30 06:26:08 PM PDT 24
Peak memory 205996 kb
Host smart-fdb0bb7d-7be7-4f57-8f81-6918433bbcdb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2798124014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.2798124014
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.283282534
Short name T2072
Test name
Test status
Simulation time 170630844 ps
CPU time 0.77 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206176 kb
Host smart-e2c6a90e-0724-439b-80c7-55cf160b0e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28328
2534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.283282534
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.392043469
Short name T2489
Test name
Test status
Simulation time 208349426 ps
CPU time 0.85 seconds
Started Jun 30 06:26:22 PM PDT 24
Finished Jun 30 06:26:24 PM PDT 24
Peak memory 206168 kb
Host smart-7bb5b702-272c-4d85-8dd0-4be9d71610c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39204
3469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.392043469
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1039364787
Short name T1496
Test name
Test status
Simulation time 162025109 ps
CPU time 0.81 seconds
Started Jun 30 06:26:06 PM PDT 24
Finished Jun 30 06:26:08 PM PDT 24
Peak memory 206204 kb
Host smart-db3dff6e-0d20-4247-9b5a-bca779ae28c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10393
64787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1039364787
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1125440291
Short name T2378
Test name
Test status
Simulation time 278515793 ps
CPU time 0.96 seconds
Started Jun 30 06:26:06 PM PDT 24
Finished Jun 30 06:26:07 PM PDT 24
Peak memory 206056 kb
Host smart-77ef273f-fa17-46b9-9155-f2ce12a9fdc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11254
40291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1125440291
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2722432842
Short name T781
Test name
Test status
Simulation time 171467091 ps
CPU time 0.81 seconds
Started Jun 30 06:26:03 PM PDT 24
Finished Jun 30 06:26:04 PM PDT 24
Peak memory 206188 kb
Host smart-eedbde4f-222e-45d4-800f-266d7493446c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27224
32842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2722432842
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3159590029
Short name T1511
Test name
Test status
Simulation time 227213854 ps
CPU time 0.86 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206200 kb
Host smart-34785f07-efab-4b7e-9028-b90fa07bc1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31595
90029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3159590029
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.85493619
Short name T1843
Test name
Test status
Simulation time 222544063 ps
CPU time 1.01 seconds
Started Jun 30 06:26:05 PM PDT 24
Finished Jun 30 06:26:07 PM PDT 24
Peak memory 206224 kb
Host smart-e7305c21-1d8c-4c4c-970f-a507ddd93d62
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=85493619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.85493619
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1371396037
Short name T1614
Test name
Test status
Simulation time 145673305 ps
CPU time 0.77 seconds
Started Jun 30 06:26:17 PM PDT 24
Finished Jun 30 06:26:19 PM PDT 24
Peak memory 206172 kb
Host smart-860f60c4-811e-444b-9bdb-d476af800545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13713
96037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1371396037
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3384714791
Short name T2566
Test name
Test status
Simulation time 42998534 ps
CPU time 0.67 seconds
Started Jun 30 06:26:20 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 206392 kb
Host smart-b8d17107-33a0-4645-b17b-5128802fdbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33847
14791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3384714791
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.296623656
Short name T1690
Test name
Test status
Simulation time 7181367282 ps
CPU time 16.68 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206432 kb
Host smart-d5bd08a3-a3f0-4e09-b455-34f35861f330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29662
3656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.296623656
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3819491510
Short name T1447
Test name
Test status
Simulation time 163945899 ps
CPU time 0.78 seconds
Started Jun 30 06:26:11 PM PDT 24
Finished Jun 30 06:26:14 PM PDT 24
Peak memory 206164 kb
Host smart-d1c9e7c9-23b9-4a88-9a53-3e8c2ab28e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38194
91510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3819491510
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2324035372
Short name T398
Test name
Test status
Simulation time 239496012 ps
CPU time 0.89 seconds
Started Jun 30 06:26:24 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206204 kb
Host smart-ac181e76-332c-4509-ad85-a03be0f9df49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23240
35372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2324035372
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.3059424230
Short name T345
Test name
Test status
Simulation time 169800953 ps
CPU time 0.84 seconds
Started Jun 30 06:26:09 PM PDT 24
Finished Jun 30 06:26:10 PM PDT 24
Peak memory 206228 kb
Host smart-48555132-414e-4005-adea-a8ee4dc0d73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30594
24230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.3059424230
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3220204925
Short name T968
Test name
Test status
Simulation time 168728531 ps
CPU time 0.84 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:11 PM PDT 24
Peak memory 206196 kb
Host smart-11ab751a-9201-450c-b495-564c12d80ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32202
04925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3220204925
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2388219134
Short name T379
Test name
Test status
Simulation time 198105465 ps
CPU time 0.82 seconds
Started Jun 30 06:26:06 PM PDT 24
Finished Jun 30 06:26:08 PM PDT 24
Peak memory 206192 kb
Host smart-da4284e9-4f6e-41b7-a1cc-b55fc4d58ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23882
19134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2388219134
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3332225428
Short name T814
Test name
Test status
Simulation time 153093453 ps
CPU time 0.78 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206168 kb
Host smart-f5b64e59-468e-4ef9-8bc3-a0e0253f342f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33322
25428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3332225428
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2390047990
Short name T391
Test name
Test status
Simulation time 154062917 ps
CPU time 0.83 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:14 PM PDT 24
Peak memory 206148 kb
Host smart-80bc7185-d584-4ac1-b9e9-eb3609aad677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23900
47990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2390047990
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.4118025255
Short name T2157
Test name
Test status
Simulation time 222141170 ps
CPU time 0.96 seconds
Started Jun 30 06:26:13 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206396 kb
Host smart-df72ef85-0690-4cca-81d3-d79641857484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
25255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.4118025255
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.449930745
Short name T1410
Test name
Test status
Simulation time 4286765128 ps
CPU time 109.57 seconds
Started Jun 30 06:26:06 PM PDT 24
Finished Jun 30 06:27:57 PM PDT 24
Peak memory 206400 kb
Host smart-06eeb701-2309-4bda-ad43-ed65fe77e707
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=449930745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.449930745
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2882518371
Short name T612
Test name
Test status
Simulation time 176331946 ps
CPU time 0.8 seconds
Started Jun 30 06:26:05 PM PDT 24
Finished Jun 30 06:26:07 PM PDT 24
Peak memory 206416 kb
Host smart-6849a2c8-34e8-494b-a168-91d753d916a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28825
18371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2882518371
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2669358383
Short name T715
Test name
Test status
Simulation time 179478325 ps
CPU time 0.79 seconds
Started Jun 30 06:26:13 PM PDT 24
Finished Jun 30 06:26:15 PM PDT 24
Peak memory 206176 kb
Host smart-1608eb86-c382-4ab6-b514-60f32f81a948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26693
58383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2669358383
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.3918279281
Short name T334
Test name
Test status
Simulation time 5396310395 ps
CPU time 38.04 seconds
Started Jun 30 06:26:15 PM PDT 24
Finished Jun 30 06:26:54 PM PDT 24
Peak memory 206484 kb
Host smart-ce0876e3-49bf-46aa-bfe2-d2931640eae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39182
79281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.3918279281
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.3155876509
Short name T209
Test name
Test status
Simulation time 49017290 ps
CPU time 0.68 seconds
Started Jun 30 06:26:23 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206224 kb
Host smart-45696f0f-f219-4798-b43f-aef6c7e421ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3155876509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.3155876509
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1768519150
Short name T1624
Test name
Test status
Simulation time 3877464974 ps
CPU time 5.21 seconds
Started Jun 30 06:26:07 PM PDT 24
Finished Jun 30 06:26:13 PM PDT 24
Peak memory 206376 kb
Host smart-09242d1b-9750-44b3-9aae-1ce70d0e33b9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1768519150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.1768519150
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.365903569
Short name T2254
Test name
Test status
Simulation time 13379867562 ps
CPU time 15.48 seconds
Started Jun 30 06:26:09 PM PDT 24
Finished Jun 30 06:26:26 PM PDT 24
Peak memory 206460 kb
Host smart-faea8231-a642-4e87-bc26-99ca545edfd8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=365903569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.365903569
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.988301440
Short name T1101
Test name
Test status
Simulation time 23338004084 ps
CPU time 21.45 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:52 PM PDT 24
Peak memory 206456 kb
Host smart-34812f91-b41b-484f-8479-8f5e670dfbee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=988301440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.988301440
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1722249864
Short name T432
Test name
Test status
Simulation time 210854338 ps
CPU time 0.86 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206184 kb
Host smart-726f4e2d-6558-451c-a037-465d9db7d20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17222
49864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1722249864
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1017146659
Short name T1167
Test name
Test status
Simulation time 149334056 ps
CPU time 0.77 seconds
Started Jun 30 06:26:19 PM PDT 24
Finished Jun 30 06:26:21 PM PDT 24
Peak memory 206168 kb
Host smart-953e8a5b-a8f1-400d-aebd-dbc278d4e38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10171
46659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1017146659
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2776728508
Short name T951
Test name
Test status
Simulation time 433232042 ps
CPU time 1.32 seconds
Started Jun 30 06:26:15 PM PDT 24
Finished Jun 30 06:26:17 PM PDT 24
Peak memory 206180 kb
Host smart-f7579d43-72a4-4415-b30b-c1e367705bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27767
28508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2776728508
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2428576319
Short name T1224
Test name
Test status
Simulation time 1236019478 ps
CPU time 2.58 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206356 kb
Host smart-f42e8d56-70f9-421a-9425-c7c7ee3e7c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24285
76319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2428576319
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.2255225783
Short name T1403
Test name
Test status
Simulation time 14745346261 ps
CPU time 27.07 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:52 PM PDT 24
Peak memory 206428 kb
Host smart-f81c8fd9-7dce-4228-b3af-c12ef09f7cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22552
25783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2255225783
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3975066840
Short name T1781
Test name
Test status
Simulation time 481578402 ps
CPU time 1.29 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206120 kb
Host smart-2e64cd5a-aea8-4c71-b77a-c709ea667172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39750
66840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3975066840
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.2453360664
Short name T616
Test name
Test status
Simulation time 133544356 ps
CPU time 0.75 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206176 kb
Host smart-796de43c-0269-4ca2-93f4-adac09f3c31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24533
60664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2453360664
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3869954808
Short name T1766
Test name
Test status
Simulation time 32289739 ps
CPU time 0.65 seconds
Started Jun 30 06:26:11 PM PDT 24
Finished Jun 30 06:26:13 PM PDT 24
Peak memory 206176 kb
Host smart-59754f41-a52c-484e-9da2-de484c622bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38699
54808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3869954808
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3798381818
Short name T1923
Test name
Test status
Simulation time 806975965 ps
CPU time 2.11 seconds
Started Jun 30 06:26:09 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206496 kb
Host smart-54c22fbe-aca4-4723-9a54-363d578bf809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37983
81818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3798381818
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.144723641
Short name T459
Test name
Test status
Simulation time 212457424 ps
CPU time 1.44 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:27 PM PDT 24
Peak memory 206304 kb
Host smart-868ed1f9-7ac8-47b2-92ba-53c12b9e411e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14472
3641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.144723641
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2741499126
Short name T550
Test name
Test status
Simulation time 277405696 ps
CPU time 0.95 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:28 PM PDT 24
Peak memory 206116 kb
Host smart-f7d3d498-904e-4ff2-a835-ee99afbbb716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27414
99126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2741499126
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.443224111
Short name T1398
Test name
Test status
Simulation time 144402886 ps
CPU time 0.75 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 206148 kb
Host smart-887a84cb-12cb-448e-883f-17bed707d5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44322
4111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.443224111
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.2007666319
Short name T1501
Test name
Test status
Simulation time 201279390 ps
CPU time 0.87 seconds
Started Jun 30 06:26:09 PM PDT 24
Finished Jun 30 06:26:10 PM PDT 24
Peak memory 206344 kb
Host smart-8d8d9d58-7f08-4273-ab87-f7f35b5fed2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20076
66319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2007666319
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.4059131751
Short name T2163
Test name
Test status
Simulation time 226600951 ps
CPU time 0.89 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:32 PM PDT 24
Peak memory 206168 kb
Host smart-53a9e734-1c7d-42a8-8591-9c43a8fd9bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40591
31751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.4059131751
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2956891919
Short name T2112
Test name
Test status
Simulation time 23352127910 ps
CPU time 22.71 seconds
Started Jun 30 06:26:14 PM PDT 24
Finished Jun 30 06:26:38 PM PDT 24
Peak memory 206296 kb
Host smart-291465fd-bb93-4c50-a640-5baea24a7708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29568
91919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2956891919
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.4158979206
Short name T1340
Test name
Test status
Simulation time 3326959982 ps
CPU time 3.89 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206244 kb
Host smart-c5ab9b7c-8af8-4606-a543-894d82fa23b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41589
79206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.4158979206
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.1023510914
Short name T1369
Test name
Test status
Simulation time 7784718797 ps
CPU time 73.19 seconds
Started Jun 30 06:26:18 PM PDT 24
Finished Jun 30 06:27:33 PM PDT 24
Peak memory 206376 kb
Host smart-6db98ef6-dcb8-466a-811d-355d1cf789a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10235
10914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.1023510914
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1326040542
Short name T2604
Test name
Test status
Simulation time 7664330472 ps
CPU time 68.92 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:27:23 PM PDT 24
Peak memory 206496 kb
Host smart-e167d610-7f6c-473f-b78a-3e0fa8e1dc33
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1326040542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1326040542
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2971878706
Short name T1143
Test name
Test status
Simulation time 242985647 ps
CPU time 0.89 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206220 kb
Host smart-e931a9e3-a0a8-4e44-a5f2-d4fb56ed012e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2971878706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2971878706
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2255941878
Short name T701
Test name
Test status
Simulation time 209499329 ps
CPU time 0.85 seconds
Started Jun 30 06:26:31 PM PDT 24
Finished Jun 30 06:26:34 PM PDT 24
Peak memory 206176 kb
Host smart-018f2844-85ea-4d37-a8b3-40878049f8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22559
41878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2255941878
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.930311694
Short name T1941
Test name
Test status
Simulation time 5780673472 ps
CPU time 52.75 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 206400 kb
Host smart-215bb818-d9c4-4ab3-96ac-619e98cd03c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93031
1694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.930311694
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.2706903857
Short name T2105
Test name
Test status
Simulation time 5551363200 ps
CPU time 40.44 seconds
Started Jun 30 06:26:08 PM PDT 24
Finished Jun 30 06:26:49 PM PDT 24
Peak memory 206436 kb
Host smart-04fad86e-ece0-4904-94f2-54ee7c79ef33
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2706903857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.2706903857
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.3919508931
Short name T2198
Test name
Test status
Simulation time 153635531 ps
CPU time 0.88 seconds
Started Jun 30 06:26:07 PM PDT 24
Finished Jun 30 06:26:09 PM PDT 24
Peak memory 206208 kb
Host smart-81d8033a-4310-4539-81bc-240ac6fc855e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3919508931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.3919508931
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2277218874
Short name T513
Test name
Test status
Simulation time 150292398 ps
CPU time 0.82 seconds
Started Jun 30 06:26:18 PM PDT 24
Finished Jun 30 06:26:19 PM PDT 24
Peak memory 206188 kb
Host smart-8406cc64-2870-4935-a93f-8a8688b92072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22772
18874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2277218874
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1392160492
Short name T2294
Test name
Test status
Simulation time 205630293 ps
CPU time 0.81 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:28 PM PDT 24
Peak memory 206156 kb
Host smart-85bfdf91-129c-452c-b40a-da1ef5e07fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13921
60492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1392160492
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1779822931
Short name T1847
Test name
Test status
Simulation time 175810916 ps
CPU time 0.83 seconds
Started Jun 30 06:26:14 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206204 kb
Host smart-277e5978-bfc9-4feb-abf7-f67e4cb7298c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17798
22931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1779822931
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2590933656
Short name T753
Test name
Test status
Simulation time 196984531 ps
CPU time 0.8 seconds
Started Jun 30 06:26:06 PM PDT 24
Finished Jun 30 06:26:08 PM PDT 24
Peak memory 205996 kb
Host smart-0162e848-ca5b-45f0-904c-a2789badc35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25909
33656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2590933656
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2405748665
Short name T1342
Test name
Test status
Simulation time 208813601 ps
CPU time 0.85 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:15 PM PDT 24
Peak memory 206216 kb
Host smart-3ae958d8-2385-4058-bd8c-a38f972d0f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057
48665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2405748665
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2076560246
Short name T2239
Test name
Test status
Simulation time 179638595 ps
CPU time 0.86 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:32 PM PDT 24
Peak memory 206196 kb
Host smart-21562c9a-99f4-4fa2-a49c-89e74f5ab437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20765
60246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2076560246
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3264043433
Short name T395
Test name
Test status
Simulation time 220492035 ps
CPU time 0.95 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206176 kb
Host smart-0aec9224-dc1b-4537-a0ea-76a3e34499fa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3264043433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3264043433
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3457943756
Short name T2161
Test name
Test status
Simulation time 147124152 ps
CPU time 0.78 seconds
Started Jun 30 06:26:21 PM PDT 24
Finished Jun 30 06:26:23 PM PDT 24
Peak memory 206356 kb
Host smart-233c3f91-b7f4-4098-b911-5b2e47e66f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34579
43756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3457943756
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.19213625
Short name T526
Test name
Test status
Simulation time 55062539 ps
CPU time 0.71 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:15 PM PDT 24
Peak memory 206204 kb
Host smart-9ce7b663-556a-4fa9-a9a7-d3461da020fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19213
625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.19213625
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.643791597
Short name T1338
Test name
Test status
Simulation time 7131498802 ps
CPU time 14.92 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:28 PM PDT 24
Peak memory 206432 kb
Host smart-04598d7f-86ac-4cc5-b303-d41d6c249036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64379
1597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.643791597
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1010462062
Short name T2397
Test name
Test status
Simulation time 190241905 ps
CPU time 0.88 seconds
Started Jun 30 06:26:11 PM PDT 24
Finished Jun 30 06:26:13 PM PDT 24
Peak memory 206188 kb
Host smart-a55a5f83-5475-4184-b284-9edce4cc128d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10104
62062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1010462062
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3152880847
Short name T1565
Test name
Test status
Simulation time 163766592 ps
CPU time 0.76 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206212 kb
Host smart-9964c5e7-2811-48ac-814f-e2b27a6c5690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31528
80847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3152880847
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3800722950
Short name T1553
Test name
Test status
Simulation time 214542872 ps
CPU time 0.89 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206228 kb
Host smart-678aadd2-3963-4352-a39b-5ab326fa93c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38007
22950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3800722950
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.553262052
Short name T1498
Test name
Test status
Simulation time 151010247 ps
CPU time 0.84 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:26:12 PM PDT 24
Peak memory 206196 kb
Host smart-89a37aed-7b16-4a77-b42c-ce2758792c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55326
2052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.553262052
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3368710985
Short name T1487
Test name
Test status
Simulation time 177372129 ps
CPU time 0.81 seconds
Started Jun 30 06:26:14 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206192 kb
Host smart-60cd4228-3e04-4293-ba6e-1623540ff311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33687
10985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3368710985
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.784218726
Short name T1408
Test name
Test status
Simulation time 141647367 ps
CPU time 0.77 seconds
Started Jun 30 06:26:22 PM PDT 24
Finished Jun 30 06:26:24 PM PDT 24
Peak memory 206396 kb
Host smart-5e07de6e-81e8-4cb4-9b09-1bb7c9688312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78421
8726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.784218726
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2287676647
Short name T1320
Test name
Test status
Simulation time 149325006 ps
CPU time 0.78 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206204 kb
Host smart-963f3299-c95f-42c5-b6c7-2cc934ee90d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22876
76647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2287676647
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3077775103
Short name T1386
Test name
Test status
Simulation time 220028718 ps
CPU time 0.98 seconds
Started Jun 30 06:26:22 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206200 kb
Host smart-71848231-d2a9-4115-9fdd-aafa25da5403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30777
75103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3077775103
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2867944115
Short name T1175
Test name
Test status
Simulation time 5408995737 ps
CPU time 51.06 seconds
Started Jun 30 06:26:10 PM PDT 24
Finished Jun 30 06:27:02 PM PDT 24
Peak memory 206384 kb
Host smart-eb4c0ce1-005d-4edb-afeb-1fc3db831767
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2867944115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2867944115
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.824703094
Short name T837
Test name
Test status
Simulation time 163722979 ps
CPU time 0.79 seconds
Started Jun 30 06:26:24 PM PDT 24
Finished Jun 30 06:26:26 PM PDT 24
Peak memory 206396 kb
Host smart-99adf5f6-d6ad-490f-abb8-bae6a079374a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82470
3094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.824703094
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3426566521
Short name T2183
Test name
Test status
Simulation time 153031675 ps
CPU time 0.79 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206204 kb
Host smart-b43b3bef-9e01-456f-89e0-6c7c69f17ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34265
66521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3426566521
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3089255171
Short name T1768
Test name
Test status
Simulation time 3406538220 ps
CPU time 93.9 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:28:04 PM PDT 24
Peak memory 206456 kb
Host smart-6eb14aee-7872-4331-b461-75e176b0b32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30892
55171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3089255171
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.18772289
Short name T1026
Test name
Test status
Simulation time 39776440 ps
CPU time 0.66 seconds
Started Jun 30 06:26:16 PM PDT 24
Finished Jun 30 06:26:18 PM PDT 24
Peak memory 206196 kb
Host smart-a7281e2d-97ba-4900-9d48-57783816b5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=18772289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.18772289
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.546167131
Short name T1053
Test name
Test status
Simulation time 4353145577 ps
CPU time 5.4 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:34 PM PDT 24
Peak memory 206184 kb
Host smart-c8e3dc1b-9777-4827-9042-2f3b12fcd17e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=546167131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.546167131
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1652869577
Short name T1848
Test name
Test status
Simulation time 13343702809 ps
CPU time 12.03 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:39 PM PDT 24
Peak memory 206412 kb
Host smart-6e0e7478-0387-4b13-8557-c62d5ca4d787
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1652869577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1652869577
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3491746893
Short name T13
Test name
Test status
Simulation time 23371941422 ps
CPU time 23.45 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:55 PM PDT 24
Peak memory 206288 kb
Host smart-ba9d9d91-8be7-4e59-828e-5681dc8a4cd7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3491746893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.3491746893
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1849767519
Short name T795
Test name
Test status
Simulation time 175648324 ps
CPU time 0.82 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206196 kb
Host smart-35bb8518-bc60-435d-86a2-6f98fc6de346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18497
67519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1849767519
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3038493724
Short name T238
Test name
Test status
Simulation time 153133995 ps
CPU time 0.76 seconds
Started Jun 30 06:26:23 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206156 kb
Host smart-aa567ed4-a9c2-477f-ad93-b7d7f0016f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30384
93724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3038493724
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.161824227
Short name T2023
Test name
Test status
Simulation time 519189521 ps
CPU time 1.37 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206152 kb
Host smart-1630e982-e4fe-4b6d-aa9c-e86070457bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16182
4227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.161824227
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.321627348
Short name T975
Test name
Test status
Simulation time 1144377202 ps
CPU time 2.56 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206264 kb
Host smart-a3d93f49-34e6-49c2-b23a-f830495d0831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32162
7348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.321627348
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.957689005
Short name T1133
Test name
Test status
Simulation time 337310630 ps
CPU time 1.06 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 206172 kb
Host smart-7e361fb7-df11-43c6-a70b-4bb3682411ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95768
9005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.957689005
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.619772576
Short name T41
Test name
Test status
Simulation time 153857830 ps
CPU time 0.74 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 205888 kb
Host smart-ee36a306-3828-4afb-9307-f6c4c3d34436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61977
2576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.619772576
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2188195512
Short name T1881
Test name
Test status
Simulation time 53431405 ps
CPU time 0.66 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:32 PM PDT 24
Peak memory 206048 kb
Host smart-d49886a6-befc-4262-98dc-7b9b096928f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21881
95512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2188195512
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2853723210
Short name T405
Test name
Test status
Simulation time 856457162 ps
CPU time 1.94 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206276 kb
Host smart-88137b21-fa2e-491f-9850-a0b4aca5bd96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28537
23210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2853723210
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1345521635
Short name T2179
Test name
Test status
Simulation time 167332778 ps
CPU time 1.53 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 205848 kb
Host smart-99fdeb79-96cc-4638-907a-f1e87244bfae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13455
21635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1345521635
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2009116605
Short name T1792
Test name
Test status
Simulation time 178024066 ps
CPU time 0.87 seconds
Started Jun 30 06:26:09 PM PDT 24
Finished Jun 30 06:26:10 PM PDT 24
Peak memory 206188 kb
Host smart-4774944a-c8e1-422a-bdb4-786a32c5df3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20091
16605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2009116605
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.147264017
Short name T2125
Test name
Test status
Simulation time 165438265 ps
CPU time 0.77 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206132 kb
Host smart-37ede86d-3ba7-4c86-bc82-15b53fa2f57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14726
4017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.147264017
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2826677659
Short name T582
Test name
Test status
Simulation time 262258573 ps
CPU time 1.03 seconds
Started Jun 30 06:26:18 PM PDT 24
Finished Jun 30 06:26:21 PM PDT 24
Peak memory 206216 kb
Host smart-957ec4d2-d2d2-4f60-b337-aeb94c304b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28266
77659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2826677659
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.603701977
Short name T1884
Test name
Test status
Simulation time 171917030 ps
CPU time 0.78 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206196 kb
Host smart-325b59dd-60d1-4846-8d6a-65b20cf4a2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60370
1977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.603701977
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3053075641
Short name T1563
Test name
Test status
Simulation time 23408997424 ps
CPU time 21.17 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:49 PM PDT 24
Peak memory 206248 kb
Host smart-5da04c75-ba3d-41ff-bbe1-61afc1217c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530
75641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3053075641
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2465843463
Short name T1421
Test name
Test status
Simulation time 3366499369 ps
CPU time 3.52 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:34 PM PDT 24
Peak memory 206256 kb
Host smart-4ef77a7a-717d-4c2d-93a3-b38b38f57526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24658
43463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2465843463
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.1985492400
Short name T259
Test name
Test status
Simulation time 9779625534 ps
CPU time 270.32 seconds
Started Jun 30 06:26:15 PM PDT 24
Finished Jun 30 06:30:46 PM PDT 24
Peak memory 206460 kb
Host smart-d7cd6eb1-e836-4a96-957a-894a795b9364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19854
92400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.1985492400
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3309593066
Short name T535
Test name
Test status
Simulation time 4257781252 ps
CPU time 41.4 seconds
Started Jun 30 06:26:13 PM PDT 24
Finished Jun 30 06:26:56 PM PDT 24
Peak memory 206436 kb
Host smart-d75a9c56-5799-48ef-8f68-18683ca1a357
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3309593066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3309593066
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.20747829
Short name T2229
Test name
Test status
Simulation time 251609474 ps
CPU time 0.89 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206148 kb
Host smart-d352076d-c5b8-4b57-9536-2464e8beba86
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=20747829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.20747829
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.989792753
Short name T544
Test name
Test status
Simulation time 248383781 ps
CPU time 0.89 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:15 PM PDT 24
Peak memory 206208 kb
Host smart-0d050c6a-bdae-4be2-b873-d2187217a720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98979
2753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.989792753
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1676790611
Short name T826
Test name
Test status
Simulation time 3499522948 ps
CPU time 23.49 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:37 PM PDT 24
Peak memory 206380 kb
Host smart-a0c28d2b-daa3-4463-b5e6-712bd5bd5923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16767
90611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1676790611
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.539809602
Short name T1611
Test name
Test status
Simulation time 6752043966 ps
CPU time 191.33 seconds
Started Jun 30 06:26:16 PM PDT 24
Finished Jun 30 06:29:28 PM PDT 24
Peak memory 206444 kb
Host smart-886dff56-589a-40a1-96a1-ff0071946896
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=539809602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.539809602
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.284482947
Short name T1166
Test name
Test status
Simulation time 178378669 ps
CPU time 0.82 seconds
Started Jun 30 06:26:22 PM PDT 24
Finished Jun 30 06:26:24 PM PDT 24
Peak memory 206212 kb
Host smart-3d9dfe15-e470-4714-9dab-692b74955d52
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=284482947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.284482947
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.442553270
Short name T984
Test name
Test status
Simulation time 169392694 ps
CPU time 0.84 seconds
Started Jun 30 06:26:15 PM PDT 24
Finished Jun 30 06:26:17 PM PDT 24
Peak memory 206380 kb
Host smart-9751201b-06cf-4a59-82ec-f8773f9644a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44255
3270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.442553270
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3906690591
Short name T116
Test name
Test status
Simulation time 215957085 ps
CPU time 0.89 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 206196 kb
Host smart-bdf250f0-d400-4e92-8203-323984af517e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39066
90591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3906690591
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.669460858
Short name T1784
Test name
Test status
Simulation time 200544349 ps
CPU time 0.85 seconds
Started Jun 30 06:26:13 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206188 kb
Host smart-2f35f1d5-0331-4a3f-9558-79e82cbf75f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66946
0858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.669460858
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1508779725
Short name T382
Test name
Test status
Simulation time 144948619 ps
CPU time 0.75 seconds
Started Jun 30 06:26:16 PM PDT 24
Finished Jun 30 06:26:18 PM PDT 24
Peak memory 206184 kb
Host smart-9fbd909d-afba-4d67-afdb-3f3f0cc3c87f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15087
79725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1508779725
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.787763747
Short name T1240
Test name
Test status
Simulation time 215947465 ps
CPU time 0.86 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206176 kb
Host smart-0a7ef015-b6ee-430d-8e21-43a217136c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78776
3747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.787763747
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3709012110
Short name T1183
Test name
Test status
Simulation time 180189782 ps
CPU time 0.87 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206188 kb
Host smart-a0a1f82c-4096-4130-85e8-5dc22c55ff16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
12110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3709012110
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1431176832
Short name T656
Test name
Test status
Simulation time 293870570 ps
CPU time 1.06 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:26 PM PDT 24
Peak memory 206184 kb
Host smart-20cea107-d8c1-45c1-95fb-57807ef7e48c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1431176832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1431176832
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.4059708835
Short name T1445
Test name
Test status
Simulation time 183829348 ps
CPU time 0.75 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:15 PM PDT 24
Peak memory 206200 kb
Host smart-72ee3332-5070-4198-996a-7fc7d8b3f1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40597
08835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.4059708835
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.4035276281
Short name T2459
Test name
Test status
Simulation time 45286196 ps
CPU time 0.63 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:32 PM PDT 24
Peak memory 206204 kb
Host smart-94157376-fb19-49eb-836a-77d29d03deb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40352
76281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.4035276281
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.938857358
Short name T2152
Test name
Test status
Simulation time 7194645441 ps
CPU time 16.48 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:45 PM PDT 24
Peak memory 206404 kb
Host smart-771bf1d4-bd49-41b4-b3f7-ee7b43b865f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93885
7358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.938857358
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.4056892570
Short name T2248
Test name
Test status
Simulation time 161158825 ps
CPU time 0.82 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 206148 kb
Host smart-dd5c2792-a4e2-4262-aed8-e6689b97bc26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40568
92570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.4056892570
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2754672804
Short name T33
Test name
Test status
Simulation time 262427909 ps
CPU time 0.89 seconds
Started Jun 30 06:26:13 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206180 kb
Host smart-714aae98-de5c-4d9c-9f27-28bad7061218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27546
72804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2754672804
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1447615864
Short name T1707
Test name
Test status
Simulation time 235350386 ps
CPU time 0.93 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:15 PM PDT 24
Peak memory 206188 kb
Host smart-5851bfb2-abdf-4e57-9be1-6b6134f9f693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14476
15864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1447615864
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1968470406
Short name T807
Test name
Test status
Simulation time 142771211 ps
CPU time 0.79 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206188 kb
Host smart-a422c639-3834-428b-a1d4-88f0b5405636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19684
70406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1968470406
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.4282275674
Short name T1141
Test name
Test status
Simulation time 182232820 ps
CPU time 0.79 seconds
Started Jun 30 06:26:16 PM PDT 24
Finished Jun 30 06:26:23 PM PDT 24
Peak memory 206180 kb
Host smart-02d7d206-69c8-4a60-97ed-f97fe8e6b256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42822
75674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.4282275674
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3114152223
Short name T706
Test name
Test status
Simulation time 150561220 ps
CPU time 0.83 seconds
Started Jun 30 06:26:15 PM PDT 24
Finished Jun 30 06:26:17 PM PDT 24
Peak memory 206048 kb
Host smart-8520ad6e-abcd-418e-b272-f3ccd8167a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31141
52223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3114152223
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.871891792
Short name T2429
Test name
Test status
Simulation time 150368646 ps
CPU time 0.81 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206180 kb
Host smart-19c757f2-b3b1-4c49-bea7-cffacf4f7ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87189
1792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.871891792
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2776636532
Short name T2193
Test name
Test status
Simulation time 203052371 ps
CPU time 0.92 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:28 PM PDT 24
Peak memory 206120 kb
Host smart-645471fd-d0b9-4c91-84f0-a447c8902022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27766
36532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2776636532
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1066093383
Short name T1132
Test name
Test status
Simulation time 6026779649 ps
CPU time 165.49 seconds
Started Jun 30 06:26:15 PM PDT 24
Finished Jun 30 06:29:02 PM PDT 24
Peak memory 206472 kb
Host smart-de6d9f60-bd4e-47d1-8333-d5e7b25739e4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1066093383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1066093383
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1550572978
Short name T1304
Test name
Test status
Simulation time 159916400 ps
CPU time 0.8 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:28 PM PDT 24
Peak memory 206172 kb
Host smart-505352cb-0d9d-49ec-bfc1-a832210c0398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15505
72978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1550572978
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.4219573153
Short name T2545
Test name
Test status
Simulation time 201753170 ps
CPU time 0.82 seconds
Started Jun 30 06:26:15 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 206188 kb
Host smart-8c95d4e3-e2e7-4fe6-a888-ae0772fef39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42195
73153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.4219573153
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.143038749
Short name T2480
Test name
Test status
Simulation time 4103183916 ps
CPU time 110.89 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:28:04 PM PDT 24
Peak memory 206424 kb
Host smart-14ecf191-11d4-4290-a1a8-830a3aec97a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14303
8749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.143038749
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.2504949841
Short name T2197
Test name
Test status
Simulation time 40293660 ps
CPU time 0.68 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 206184 kb
Host smart-bf4b9dd1-63a0-402c-bd6d-29b1f598b0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2504949841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.2504949841
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.3698605329
Short name T1472
Test name
Test status
Simulation time 4239844777 ps
CPU time 4.77 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:34 PM PDT 24
Peak memory 206280 kb
Host smart-aa3e087c-d2c8-4b45-8c54-043c2a0533a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3698605329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.3698605329
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3450100003
Short name T16
Test name
Test status
Simulation time 13390088286 ps
CPU time 14.27 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:44 PM PDT 24
Peak memory 206316 kb
Host smart-ba8c129e-394b-4736-b320-06ac3d024654
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3450100003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3450100003
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3743920279
Short name T1736
Test name
Test status
Simulation time 23365670808 ps
CPU time 25.56 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206436 kb
Host smart-7562833c-fc5f-4476-b258-9a2d7acc7b24
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3743920279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.3743920279
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2994620586
Short name T2406
Test name
Test status
Simulation time 184583631 ps
CPU time 0.88 seconds
Started Jun 30 06:26:17 PM PDT 24
Finished Jun 30 06:26:19 PM PDT 24
Peak memory 206192 kb
Host smart-556f5dfe-1a08-410e-b160-d58a409cbd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29946
20586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2994620586
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3811015129
Short name T1596
Test name
Test status
Simulation time 152389757 ps
CPU time 0.75 seconds
Started Jun 30 06:26:14 PM PDT 24
Finished Jun 30 06:26:17 PM PDT 24
Peak memory 206048 kb
Host smart-ed9645bb-1346-41f8-9dae-2c1b95c83ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38110
15129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3811015129
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3692310719
Short name T1189
Test name
Test status
Simulation time 529893570 ps
CPU time 1.59 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206180 kb
Host smart-b9fa71e7-9cce-459d-87a0-58c246c65093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36923
10719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3692310719
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3319598034
Short name T1045
Test name
Test status
Simulation time 381772367 ps
CPU time 1.14 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206168 kb
Host smart-39f8dbff-a968-4423-a77a-f0d65d03fcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33195
98034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3319598034
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.1345520092
Short name T173
Test name
Test status
Simulation time 22472474493 ps
CPU time 46.11 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 206320 kb
Host smart-e8701466-9459-4a13-8cb0-cbc4a078306c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13455
20092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1345520092
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.1184710594
Short name T1453
Test name
Test status
Simulation time 483196623 ps
CPU time 1.43 seconds
Started Jun 30 06:26:14 PM PDT 24
Finished Jun 30 06:26:17 PM PDT 24
Peak memory 206184 kb
Host smart-d3b3d831-7a10-422d-a552-587fb25e2c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11847
10594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.1184710594
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.4103661906
Short name T2399
Test name
Test status
Simulation time 144042039 ps
CPU time 0.78 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:32 PM PDT 24
Peak memory 206176 kb
Host smart-a36e36af-6019-46fc-99dd-85f3a5df98b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41036
61906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.4103661906
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1996595840
Short name T917
Test name
Test status
Simulation time 71273097 ps
CPU time 0.68 seconds
Started Jun 30 06:26:29 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206156 kb
Host smart-626020ef-1240-49df-9fb9-e32799960cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19965
95840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1996595840
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.2197670959
Short name T1674
Test name
Test status
Simulation time 844373545 ps
CPU time 2.03 seconds
Started Jun 30 06:26:29 PM PDT 24
Finished Jun 30 06:26:34 PM PDT 24
Peak memory 206308 kb
Host smart-5b4aa462-92e9-4fcc-b263-fa9e73143ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21976
70959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2197670959
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1318918894
Short name T1008
Test name
Test status
Simulation time 324870584 ps
CPU time 2.13 seconds
Started Jun 30 06:26:14 PM PDT 24
Finished Jun 30 06:26:17 PM PDT 24
Peak memory 206352 kb
Host smart-cc1a7515-3e97-4730-95b7-3797fee55a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13189
18894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1318918894
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.467211857
Short name T2270
Test name
Test status
Simulation time 191341885 ps
CPU time 0.83 seconds
Started Jun 30 06:26:15 PM PDT 24
Finished Jun 30 06:26:17 PM PDT 24
Peak memory 206208 kb
Host smart-f3d08d7f-5bb2-4883-a3bb-0255cdc6cfae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46721
1857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.467211857
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3088494043
Short name T854
Test name
Test status
Simulation time 139345174 ps
CPU time 0.78 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206216 kb
Host smart-3ef7fc3f-878c-4c7c-b990-80d474810aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30884
94043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3088494043
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.4225862161
Short name T480
Test name
Test status
Simulation time 201069041 ps
CPU time 0.85 seconds
Started Jun 30 06:26:29 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206196 kb
Host smart-191d80c8-ad31-447f-ba58-54617a8ea303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42258
62161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.4225862161
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.608556722
Short name T2124
Test name
Test status
Simulation time 241785756 ps
CPU time 0.88 seconds
Started Jun 30 06:26:15 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 206352 kb
Host smart-3d3e79de-4318-42de-8eb4-1d0e44ba5ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60855
6722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.608556722
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.137621753
Short name T1135
Test name
Test status
Simulation time 23272811000 ps
CPU time 25.14 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:57 PM PDT 24
Peak memory 206300 kb
Host smart-6566bf61-4544-472c-9463-e41c9f7697e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13762
1753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.137621753
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2866323145
Short name T647
Test name
Test status
Simulation time 3329904896 ps
CPU time 3.74 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:35 PM PDT 24
Peak memory 206228 kb
Host smart-9bd43182-dfd8-4f76-9404-057d37f8f80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28663
23145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2866323145
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.171923986
Short name T1256
Test name
Test status
Simulation time 8308671393 ps
CPU time 230.35 seconds
Started Jun 30 06:26:18 PM PDT 24
Finished Jun 30 06:30:09 PM PDT 24
Peak memory 206424 kb
Host smart-d964a81d-6b01-45f2-974a-50eadd9d5236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17192
3986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.171923986
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3739712784
Short name T1434
Test name
Test status
Simulation time 4440011691 ps
CPU time 40.12 seconds
Started Jun 30 06:26:21 PM PDT 24
Finished Jun 30 06:27:02 PM PDT 24
Peak memory 206404 kb
Host smart-0473516d-f8d1-41d0-a57f-efe700cb5ed0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3739712784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3739712784
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.1790946796
Short name T410
Test name
Test status
Simulation time 230350623 ps
CPU time 0.9 seconds
Started Jun 30 06:26:22 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206212 kb
Host smart-fb3f1dad-e3e4-42b2-bcf5-2656cdcaeda6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1790946796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.1790946796
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2287746738
Short name T568
Test name
Test status
Simulation time 190745438 ps
CPU time 0.9 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 205924 kb
Host smart-eabb54b2-45a9-4117-bac5-74e8e66d7a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22877
46738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2287746738
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.2694180972
Short name T2365
Test name
Test status
Simulation time 6109466554 ps
CPU time 41.7 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 206360 kb
Host smart-31f5815f-4347-4407-b02c-d93eac1bec5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26941
80972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.2694180972
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.1183215711
Short name T1808
Test name
Test status
Simulation time 4094757697 ps
CPU time 36.23 seconds
Started Jun 30 06:26:16 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206264 kb
Host smart-198b4fd8-7b4e-46cb-bf0d-d152fc24b718
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1183215711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1183215711
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.4013192050
Short name T1531
Test name
Test status
Simulation time 153379345 ps
CPU time 0.79 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206208 kb
Host smart-5715e424-6d63-4350-a193-4d6056541c7f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4013192050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.4013192050
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.41429068
Short name T2508
Test name
Test status
Simulation time 150438693 ps
CPU time 0.8 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 206144 kb
Host smart-7ea700d3-0592-4b99-9efc-ddf02f5e6120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41429
068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.41429068
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.52739831
Short name T125
Test name
Test status
Simulation time 233035176 ps
CPU time 0.9 seconds
Started Jun 30 06:26:14 PM PDT 24
Finished Jun 30 06:26:16 PM PDT 24
Peak memory 206208 kb
Host smart-e3dd6a70-4408-4b86-a5b2-3efb0a95b624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52739
831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.52739831
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2075206973
Short name T864
Test name
Test status
Simulation time 158673469 ps
CPU time 0.77 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206196 kb
Host smart-839bd851-e95e-43f6-b74c-e0162e8b8c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20752
06973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2075206973
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2619529
Short name T1961
Test name
Test status
Simulation time 178360367 ps
CPU time 0.82 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206200 kb
Host smart-c5771886-53f5-4372-8c76-befd6d1e15e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26195
29 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2619529
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1672872774
Short name T2256
Test name
Test status
Simulation time 164033570 ps
CPU time 0.82 seconds
Started Jun 30 06:26:17 PM PDT 24
Finished Jun 30 06:26:18 PM PDT 24
Peak memory 206056 kb
Host smart-be2496e2-88b7-4284-9a79-8f811c67a9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16728
72774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1672872774
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.4064389584
Short name T789
Test name
Test status
Simulation time 180986637 ps
CPU time 0.78 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206188 kb
Host smart-4b76aa5d-0e18-4886-9024-6079a23301ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40643
89584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.4064389584
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3835000120
Short name T716
Test name
Test status
Simulation time 221511711 ps
CPU time 0.95 seconds
Started Jun 30 06:26:17 PM PDT 24
Finished Jun 30 06:26:19 PM PDT 24
Peak memory 206204 kb
Host smart-9039aeac-e031-43c0-9064-57461ea419c8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3835000120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3835000120
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3455010859
Short name T623
Test name
Test status
Simulation time 163858144 ps
CPU time 0.77 seconds
Started Jun 30 06:26:16 PM PDT 24
Finished Jun 30 06:26:18 PM PDT 24
Peak memory 206036 kb
Host smart-58b69cf7-c179-40de-a6bb-75e863199d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34550
10859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3455010859
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2639765270
Short name T1615
Test name
Test status
Simulation time 105343506 ps
CPU time 0.69 seconds
Started Jun 30 06:26:18 PM PDT 24
Finished Jun 30 06:26:19 PM PDT 24
Peak memory 206156 kb
Host smart-d0f34d98-d42c-4440-92a2-65ca034b5234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26397
65270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2639765270
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.413332757
Short name T1816
Test name
Test status
Simulation time 17979522449 ps
CPU time 37.94 seconds
Started Jun 30 06:26:12 PM PDT 24
Finished Jun 30 06:26:52 PM PDT 24
Peak memory 206424 kb
Host smart-37918478-dc35-46d7-bdc3-42e6a3a74da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41333
2757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.413332757
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.275039516
Short name T2095
Test name
Test status
Simulation time 183403066 ps
CPU time 0.92 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 205948 kb
Host smart-e20d7ccf-fd2e-4f61-9077-f183169cc4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27503
9516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.275039516
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.792550153
Short name T1154
Test name
Test status
Simulation time 183982355 ps
CPU time 0.88 seconds
Started Jun 30 06:26:17 PM PDT 24
Finished Jun 30 06:26:19 PM PDT 24
Peak memory 206156 kb
Host smart-0ea1b79b-c480-49d3-8739-65ed7976c280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79255
0153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.792550153
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.886797129
Short name T902
Test name
Test status
Simulation time 212307504 ps
CPU time 0.88 seconds
Started Jun 30 06:26:16 PM PDT 24
Finished Jun 30 06:26:18 PM PDT 24
Peak memory 206204 kb
Host smart-bc850889-71a5-462a-9b1f-32655bb8b309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88679
7129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.886797129
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.639884251
Short name T1802
Test name
Test status
Simulation time 157889595 ps
CPU time 0.74 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206160 kb
Host smart-54bb0f6e-0650-485d-bfaf-94341928b630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63988
4251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.639884251
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.542115960
Short name T1074
Test name
Test status
Simulation time 184136102 ps
CPU time 0.8 seconds
Started Jun 30 06:26:20 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 206056 kb
Host smart-c87509d1-71f3-4a62-a5f0-7d83f66e0884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54211
5960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.542115960
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1660728437
Short name T1701
Test name
Test status
Simulation time 162768608 ps
CPU time 0.75 seconds
Started Jun 30 06:26:20 PM PDT 24
Finished Jun 30 06:26:21 PM PDT 24
Peak memory 206184 kb
Host smart-7e730398-9a61-4f56-9672-de07d2cd485c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16607
28437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1660728437
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.4184925704
Short name T1216
Test name
Test status
Simulation time 173124892 ps
CPU time 0.8 seconds
Started Jun 30 06:26:19 PM PDT 24
Finished Jun 30 06:26:21 PM PDT 24
Peak memory 206192 kb
Host smart-a966cfa3-11b4-401c-bde6-96cda5642ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41849
25704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.4184925704
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.153084515
Short name T1765
Test name
Test status
Simulation time 248189983 ps
CPU time 1.01 seconds
Started Jun 30 06:26:20 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 206204 kb
Host smart-025501d7-50e3-40b6-acf0-1bc9da27e7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15308
4515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.153084515
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.4242159752
Short name T851
Test name
Test status
Simulation time 6469542029 ps
CPU time 46.17 seconds
Started Jun 30 06:26:38 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 206416 kb
Host smart-5e78aed5-0191-4ac3-be58-55c44e700460
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4242159752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.4242159752
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3559463807
Short name T973
Test name
Test status
Simulation time 149619111 ps
CPU time 0.79 seconds
Started Jun 30 06:26:29 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206180 kb
Host smart-adab8acc-c496-4750-aeb2-ac016861fea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35594
63807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3559463807
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1628354743
Short name T886
Test name
Test status
Simulation time 155359638 ps
CPU time 0.75 seconds
Started Jun 30 06:26:20 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 206172 kb
Host smart-2673c867-e2b3-49dd-9831-bf6741047baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16283
54743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1628354743
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3706216912
Short name T1525
Test name
Test status
Simulation time 5400406698 ps
CPU time 51.58 seconds
Started Jun 30 06:26:23 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 206396 kb
Host smart-fcaeb874-ad69-4341-8b91-3ff90b97331f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37062
16912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3706216912
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.2577064081
Short name T1769
Test name
Test status
Simulation time 43610186 ps
CPU time 0.69 seconds
Started Jun 30 06:26:46 PM PDT 24
Finished Jun 30 06:26:48 PM PDT 24
Peak memory 206052 kb
Host smart-8d553a93-4cae-4978-953e-c49764e71742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2577064081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.2577064081
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1700990959
Short name T1850
Test name
Test status
Simulation time 3937850954 ps
CPU time 5.42 seconds
Started Jun 30 06:26:22 PM PDT 24
Finished Jun 30 06:26:28 PM PDT 24
Peak memory 206340 kb
Host smart-2b87fc35-5378-4722-af6f-ad20fd9aa918
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1700990959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.1700990959
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3782746748
Short name T2232
Test name
Test status
Simulation time 13348642470 ps
CPU time 15.51 seconds
Started Jun 30 06:26:19 PM PDT 24
Finished Jun 30 06:26:35 PM PDT 24
Peak memory 206404 kb
Host smart-1913fbd7-dba7-482b-87f2-47aa7a52e1fe
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3782746748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3782746748
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.574679371
Short name T805
Test name
Test status
Simulation time 23370466384 ps
CPU time 24.45 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:54 PM PDT 24
Peak memory 206328 kb
Host smart-48b75082-7141-43d4-a739-9b32c1f62ff3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=574679371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.574679371
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2380192096
Short name T662
Test name
Test status
Simulation time 198488372 ps
CPU time 0.91 seconds
Started Jun 30 06:26:29 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206188 kb
Host smart-fda61d91-9013-4477-a9fb-77c8eb9604f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23801
92096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2380192096
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.774786064
Short name T1201
Test name
Test status
Simulation time 141298323 ps
CPU time 0.74 seconds
Started Jun 30 06:26:18 PM PDT 24
Finished Jun 30 06:26:20 PM PDT 24
Peak memory 206188 kb
Host smart-d6cc0eb7-4278-41c3-b5c5-490a0d435575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77478
6064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.774786064
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.4007902365
Short name T1471
Test name
Test status
Simulation time 597116549 ps
CPU time 1.65 seconds
Started Jun 30 06:26:34 PM PDT 24
Finished Jun 30 06:26:36 PM PDT 24
Peak memory 206348 kb
Host smart-0466a1cf-8a56-4cce-9b4c-beca96079931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40079
02365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.4007902365
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1283267600
Short name T655
Test name
Test status
Simulation time 618700405 ps
CPU time 1.62 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 206244 kb
Host smart-e382b6f2-a05d-411d-ae98-e34d84121ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12832
67600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1283267600
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.4144248706
Short name T932
Test name
Test status
Simulation time 9029352634 ps
CPU time 17.72 seconds
Started Jun 30 06:26:17 PM PDT 24
Finished Jun 30 06:26:36 PM PDT 24
Peak memory 206408 kb
Host smart-f81232d9-fd1d-40aa-89b4-927d4fef8ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41442
48706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.4144248706
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3720930243
Short name T1269
Test name
Test status
Simulation time 429035091 ps
CPU time 1.33 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206156 kb
Host smart-ed92456d-1073-408f-9dae-20c31ebfcbdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37209
30243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3720930243
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3613882671
Short name T552
Test name
Test status
Simulation time 170438494 ps
CPU time 0.78 seconds
Started Jun 30 06:26:21 PM PDT 24
Finished Jun 30 06:26:23 PM PDT 24
Peak memory 206156 kb
Host smart-2d619090-4107-49aa-90f5-f6fce68d787a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36138
82671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3613882671
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3447560665
Short name T910
Test name
Test status
Simulation time 37056715 ps
CPU time 0.64 seconds
Started Jun 30 06:26:20 PM PDT 24
Finished Jun 30 06:26:28 PM PDT 24
Peak memory 206164 kb
Host smart-e01fd334-f286-4399-88b9-407edeae2128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34475
60665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3447560665
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.4147980561
Short name T1194
Test name
Test status
Simulation time 1025036810 ps
CPU time 2.37 seconds
Started Jun 30 06:26:30 PM PDT 24
Finished Jun 30 06:26:35 PM PDT 24
Peak memory 206360 kb
Host smart-1a7d050c-27cf-4fd9-ae14-8fa5b4e3a304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41479
80561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.4147980561
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1675849734
Short name T1040
Test name
Test status
Simulation time 190426814 ps
CPU time 1.19 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206316 kb
Host smart-2f96eb04-d19d-4fd1-9b0d-a9e126ca765c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16758
49734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1675849734
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2944441500
Short name T2311
Test name
Test status
Simulation time 162711814 ps
CPU time 0.79 seconds
Started Jun 30 06:26:21 PM PDT 24
Finished Jun 30 06:26:23 PM PDT 24
Peak memory 206232 kb
Host smart-0fea1d46-4f01-4a4f-a66d-201d5f702670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29444
41500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2944441500
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2396343867
Short name T1813
Test name
Test status
Simulation time 177545774 ps
CPU time 0.74 seconds
Started Jun 30 06:26:19 PM PDT 24
Finished Jun 30 06:26:21 PM PDT 24
Peak memory 206176 kb
Host smart-76e80177-df61-49ef-8e6d-4984ab7a5247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23963
43867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2396343867
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2125758163
Short name T625
Test name
Test status
Simulation time 223027907 ps
CPU time 0.88 seconds
Started Jun 30 06:26:27 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206140 kb
Host smart-9a1197f2-29d7-488c-8360-f1db2f56db9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21257
58163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2125758163
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2975845262
Short name T1365
Test name
Test status
Simulation time 160437173 ps
CPU time 0.86 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:29 PM PDT 24
Peak memory 206176 kb
Host smart-26cbc86b-0447-40ff-88fe-1f57c6291994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29758
45262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2975845262
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.572289831
Short name T2040
Test name
Test status
Simulation time 23396091866 ps
CPU time 29.47 seconds
Started Jun 30 06:26:29 PM PDT 24
Finished Jun 30 06:27:02 PM PDT 24
Peak memory 206292 kb
Host smart-d1350b52-0298-44cc-bf6d-c4017e6064f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57228
9831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.572289831
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3798207439
Short name T1846
Test name
Test status
Simulation time 3255560904 ps
CPU time 4.58 seconds
Started Jun 30 06:26:19 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 206252 kb
Host smart-c16526b7-e5bb-4af3-ac28-2473bf41ffe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37982
07439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3798207439
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.3397703184
Short name T1234
Test name
Test status
Simulation time 13182755075 ps
CPU time 380.31 seconds
Started Jun 30 06:26:23 PM PDT 24
Finished Jun 30 06:32:51 PM PDT 24
Peak memory 206464 kb
Host smart-ff25be9b-7e97-4299-b1fd-71c78351df68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977
03184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.3397703184
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3093054300
Short name T383
Test name
Test status
Simulation time 4609884178 ps
CPU time 31.08 seconds
Started Jun 30 06:26:43 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 206444 kb
Host smart-c1826c46-d999-4c3f-b3cc-8a04a2c92a8d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3093054300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3093054300
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3301344158
Short name T2538
Test name
Test status
Simulation time 247834485 ps
CPU time 0.92 seconds
Started Jun 30 06:26:40 PM PDT 24
Finished Jun 30 06:26:41 PM PDT 24
Peak memory 206224 kb
Host smart-1720e2e9-14c8-415f-a882-05da97dcb6ff
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3301344158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3301344158
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1881098662
Short name T2564
Test name
Test status
Simulation time 204238429 ps
CPU time 0.88 seconds
Started Jun 30 06:26:35 PM PDT 24
Finished Jun 30 06:26:37 PM PDT 24
Peak memory 206200 kb
Host smart-b76af311-3a4b-4ffb-949e-472eea6cd0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18810
98662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1881098662
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.491934145
Short name T613
Test name
Test status
Simulation time 5683896129 ps
CPU time 52.32 seconds
Started Jun 30 06:26:23 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 206356 kb
Host smart-9eca9afc-d8a6-4702-976d-6159b3d765ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49193
4145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.491934145
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2041794018
Short name T889
Test name
Test status
Simulation time 4860843554 ps
CPU time 43.56 seconds
Started Jun 30 06:26:41 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 206416 kb
Host smart-4019124d-6607-4d94-ab70-c0f6aa4ee58a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2041794018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2041794018
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.4084396806
Short name T478
Test name
Test status
Simulation time 149668926 ps
CPU time 0.87 seconds
Started Jun 30 06:26:37 PM PDT 24
Finished Jun 30 06:26:38 PM PDT 24
Peak memory 206212 kb
Host smart-bf7695cb-df10-491f-b395-76d08c390378
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4084396806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.4084396806
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.497867848
Short name T1851
Test name
Test status
Simulation time 160188000 ps
CPU time 0.76 seconds
Started Jun 30 06:26:31 PM PDT 24
Finished Jun 30 06:26:34 PM PDT 24
Peak memory 206208 kb
Host smart-89af6145-27f3-4c24-8a03-24fa46feb30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49786
7848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.497867848
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1650973347
Short name T2192
Test name
Test status
Simulation time 223026730 ps
CPU time 0.88 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:30 PM PDT 24
Peak memory 206196 kb
Host smart-f1cfd90d-74a0-405b-80b9-4a776b714d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16509
73347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1650973347
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3995637710
Short name T2307
Test name
Test status
Simulation time 192613971 ps
CPU time 0.83 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:26:31 PM PDT 24
Peak memory 206192 kb
Host smart-51b6d378-2801-4139-82af-841de368b071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39956
37710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3995637710
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3144069065
Short name T1751
Test name
Test status
Simulation time 159774328 ps
CPU time 0.76 seconds
Started Jun 30 06:26:30 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206196 kb
Host smart-72f0cda3-b53f-4f48-ba76-77d653434da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440
69065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3144069065
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2413792930
Short name T442
Test name
Test status
Simulation time 180631186 ps
CPU time 0.77 seconds
Started Jun 30 06:26:45 PM PDT 24
Finished Jun 30 06:26:46 PM PDT 24
Peak memory 206224 kb
Host smart-07727d08-eaeb-40d6-a171-6d570fa2b1d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24137
92930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2413792930
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2104268345
Short name T2094
Test name
Test status
Simulation time 209864522 ps
CPU time 0.8 seconds
Started Jun 30 06:26:35 PM PDT 24
Finished Jun 30 06:26:36 PM PDT 24
Peak memory 206188 kb
Host smart-8489749e-dd8f-4bf2-b6ca-30c737f416ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21042
68345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2104268345
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.622763122
Short name T1425
Test name
Test status
Simulation time 249889832 ps
CPU time 0.99 seconds
Started Jun 30 06:26:31 PM PDT 24
Finished Jun 30 06:26:34 PM PDT 24
Peak memory 206212 kb
Host smart-a9c4e6d3-9473-4f66-b187-c1f41c7ebde4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=622763122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.622763122
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3268722713
Short name T777
Test name
Test status
Simulation time 152590847 ps
CPU time 0.78 seconds
Started Jun 30 06:26:25 PM PDT 24
Finished Jun 30 06:26:27 PM PDT 24
Peak memory 206236 kb
Host smart-6cf358a8-ffc5-49a6-80a7-fa7bd44c1885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32687
22713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3268722713
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2071810418
Short name T399
Test name
Test status
Simulation time 84907206 ps
CPU time 0.68 seconds
Started Jun 30 06:26:46 PM PDT 24
Finished Jun 30 06:26:48 PM PDT 24
Peak memory 206192 kb
Host smart-be5bd953-5ea3-4ee9-854d-1c9fe60efa40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20718
10418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2071810418
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.203131869
Short name T2504
Test name
Test status
Simulation time 12531772359 ps
CPU time 26.8 seconds
Started Jun 30 06:26:38 PM PDT 24
Finished Jun 30 06:27:05 PM PDT 24
Peak memory 206436 kb
Host smart-19aa83af-5e4d-4d3c-b4cb-e5c5d0330fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20313
1869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.203131869
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1904200352
Short name T1237
Test name
Test status
Simulation time 152148534 ps
CPU time 0.76 seconds
Started Jun 30 06:26:29 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206184 kb
Host smart-c605c0a0-4560-4e34-89e4-c36d07372177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19042
00352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1904200352
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3394379037
Short name T748
Test name
Test status
Simulation time 213267899 ps
CPU time 0.88 seconds
Started Jun 30 06:26:47 PM PDT 24
Finished Jun 30 06:26:49 PM PDT 24
Peak memory 206200 kb
Host smart-8368384e-e266-4488-958a-440706f68c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33943
79037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3394379037
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.287936192
Short name T1325
Test name
Test status
Simulation time 188611806 ps
CPU time 0.86 seconds
Started Jun 30 06:26:43 PM PDT 24
Finished Jun 30 06:26:44 PM PDT 24
Peak memory 206212 kb
Host smart-60dcdff9-9941-4854-b2bc-631c7967828a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28793
6192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.287936192
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1393346412
Short name T2387
Test name
Test status
Simulation time 180539492 ps
CPU time 0.83 seconds
Started Jun 30 06:26:34 PM PDT 24
Finished Jun 30 06:26:36 PM PDT 24
Peak memory 206244 kb
Host smart-b2229316-956c-4102-a8ad-0757eeff556f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13933
46412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1393346412
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3570330294
Short name T651
Test name
Test status
Simulation time 156812915 ps
CPU time 0.78 seconds
Started Jun 30 06:26:46 PM PDT 24
Finished Jun 30 06:26:48 PM PDT 24
Peak memory 206032 kb
Host smart-95800f3b-450d-471a-bb7f-2036945c2d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35703
30294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3570330294
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1516157608
Short name T646
Test name
Test status
Simulation time 153915923 ps
CPU time 0.83 seconds
Started Jun 30 06:26:49 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206032 kb
Host smart-42200fb2-a07a-49d0-a4f6-4a1ba367ba1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15161
57608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1516157608
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.253722525
Short name T1820
Test name
Test status
Simulation time 159131087 ps
CPU time 0.86 seconds
Started Jun 30 06:26:30 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206200 kb
Host smart-68c5b835-1555-46fc-89a2-8fa87e0a60e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
2525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.253722525
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.4022864918
Short name T724
Test name
Test status
Simulation time 284120998 ps
CPU time 1.07 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206208 kb
Host smart-d2e4ea2b-3561-40a4-a4f1-e19e2f5478c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40228
64918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.4022864918
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3791729536
Short name T2483
Test name
Test status
Simulation time 5808699205 ps
CPU time 41.34 seconds
Started Jun 30 06:26:45 PM PDT 24
Finished Jun 30 06:27:27 PM PDT 24
Peak memory 206420 kb
Host smart-a3d45925-9081-4c5b-bb01-2b83fab108a3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3791729536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3791729536
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1601182267
Short name T1581
Test name
Test status
Simulation time 169967714 ps
CPU time 0.84 seconds
Started Jun 30 06:26:30 PM PDT 24
Finished Jun 30 06:26:33 PM PDT 24
Peak memory 206192 kb
Host smart-08f28a12-0b29-4920-9718-8ae591926888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16011
82267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1601182267
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1236520493
Short name T1095
Test name
Test status
Simulation time 198519119 ps
CPU time 0.85 seconds
Started Jun 30 06:26:28 PM PDT 24
Finished Jun 30 06:26:32 PM PDT 24
Peak memory 206188 kb
Host smart-83036438-78dd-4905-b045-c46d52f14325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12365
20493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1236520493
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.41451649
Short name T2587
Test name
Test status
Simulation time 6725058378 ps
CPU time 191.37 seconds
Started Jun 30 06:26:26 PM PDT 24
Finished Jun 30 06:29:41 PM PDT 24
Peak memory 206292 kb
Host smart-3414ef40-404e-4c01-bdaa-82b70fe7a59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41451
649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.41451649
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3092213403
Short name T1206
Test name
Test status
Simulation time 38424097 ps
CPU time 0.66 seconds
Started Jun 30 06:26:46 PM PDT 24
Finished Jun 30 06:26:48 PM PDT 24
Peak memory 206188 kb
Host smart-8812464b-b76c-46d0-b659-52a908ef3fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3092213403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3092213403
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.1874924927
Short name T1670
Test name
Test status
Simulation time 3519849963 ps
CPU time 4.75 seconds
Started Jun 30 06:26:47 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206428 kb
Host smart-2fe9a727-9998-4026-8017-0352f2e74ec9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1874924927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.1874924927
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1668224719
Short name T675
Test name
Test status
Simulation time 13372819883 ps
CPU time 12.78 seconds
Started Jun 30 06:26:40 PM PDT 24
Finished Jun 30 06:26:54 PM PDT 24
Peak memory 206340 kb
Host smart-2e9e4cf9-4f80-455c-ad12-aeede2620a3c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1668224719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1668224719
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2066823312
Short name T923
Test name
Test status
Simulation time 23323911916 ps
CPU time 23.46 seconds
Started Jun 30 06:26:42 PM PDT 24
Finished Jun 30 06:27:06 PM PDT 24
Peak memory 206308 kb
Host smart-8de69c65-29fd-4bb6-a909-a61da203ed51
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2066823312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.2066823312
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1176155458
Short name T499
Test name
Test status
Simulation time 154923013 ps
CPU time 0.75 seconds
Started Jun 30 06:26:36 PM PDT 24
Finished Jun 30 06:26:38 PM PDT 24
Peak memory 206192 kb
Host smart-14573f59-5a6e-438b-9b83-1e5e9db91940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11761
55458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1176155458
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1507534110
Short name T871
Test name
Test status
Simulation time 154845859 ps
CPU time 0.81 seconds
Started Jun 30 06:26:48 PM PDT 24
Finished Jun 30 06:26:50 PM PDT 24
Peak memory 206184 kb
Host smart-de8e709c-46c8-4434-9e1d-be71fcb52f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15075
34110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1507534110
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.3180143191
Short name T2403
Test name
Test status
Simulation time 448419499 ps
CPU time 1.3 seconds
Started Jun 30 06:26:41 PM PDT 24
Finished Jun 30 06:26:43 PM PDT 24
Peak memory 206176 kb
Host smart-816032ea-80ca-43d4-93f2-65afa6f0dafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31801
43191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.3180143191
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3088050536
Short name T1129
Test name
Test status
Simulation time 938044831 ps
CPU time 2.49 seconds
Started Jun 30 06:26:48 PM PDT 24
Finished Jun 30 06:26:52 PM PDT 24
Peak memory 206328 kb
Host smart-8edb56b9-a4e2-41df-bf85-5515c0060a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30880
50536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3088050536
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3788351770
Short name T1465
Test name
Test status
Simulation time 13438909582 ps
CPU time 25.79 seconds
Started Jun 30 06:26:40 PM PDT 24
Finished Jun 30 06:27:07 PM PDT 24
Peak memory 206416 kb
Host smart-30fc2219-1e7a-410c-a4b7-5545aaa899f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37883
51770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3788351770
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1167374613
Short name T524
Test name
Test status
Simulation time 405981677 ps
CPU time 1.24 seconds
Started Jun 30 06:26:41 PM PDT 24
Finished Jun 30 06:26:44 PM PDT 24
Peak memory 206200 kb
Host smart-5dcf79d0-62f1-42b9-98f0-f4a257049629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11673
74613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1167374613
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1471263054
Short name T1593
Test name
Test status
Simulation time 150542514 ps
CPU time 0.77 seconds
Started Jun 30 06:26:46 PM PDT 24
Finished Jun 30 06:26:48 PM PDT 24
Peak memory 206184 kb
Host smart-fa3f900b-8237-4b18-9451-db79cec5f367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14712
63054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1471263054
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.4124456653
Short name T1678
Test name
Test status
Simulation time 55427927 ps
CPU time 0.68 seconds
Started Jun 30 06:26:49 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206172 kb
Host smart-a78851b3-ce43-4945-8dea-a4c8f36330c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41244
56653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.4124456653
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2665715812
Short name T2552
Test name
Test status
Simulation time 998710253 ps
CPU time 2.21 seconds
Started Jun 30 06:26:37 PM PDT 24
Finished Jun 30 06:26:40 PM PDT 24
Peak memory 206312 kb
Host smart-0eb6f7db-c9ba-471c-b5e2-2348e19b9750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26657
15812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2665715812
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.531122519
Short name T466
Test name
Test status
Simulation time 360690423 ps
CPU time 2.03 seconds
Started Jun 30 06:26:49 PM PDT 24
Finished Jun 30 06:26:52 PM PDT 24
Peak memory 206320 kb
Host smart-03038d07-4c2c-4f26-93ba-497a96268cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53112
2519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.531122519
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.944354675
Short name T1346
Test name
Test status
Simulation time 235639324 ps
CPU time 0.88 seconds
Started Jun 30 06:26:39 PM PDT 24
Finished Jun 30 06:26:41 PM PDT 24
Peak memory 206196 kb
Host smart-4b17cc13-ffef-464f-aaa0-681de795c2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94435
4675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.944354675
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1121615799
Short name T1097
Test name
Test status
Simulation time 136286007 ps
CPU time 0.79 seconds
Started Jun 30 06:26:37 PM PDT 24
Finished Jun 30 06:26:38 PM PDT 24
Peak memory 206212 kb
Host smart-a8872c53-5b0a-458e-bc10-0f6da7638c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11216
15799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1121615799
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3337029279
Short name T339
Test name
Test status
Simulation time 158115533 ps
CPU time 0.79 seconds
Started Jun 30 06:26:44 PM PDT 24
Finished Jun 30 06:26:45 PM PDT 24
Peak memory 206196 kb
Host smart-24c3cd90-5143-4696-9bb9-bef69f8add44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33370
29279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3337029279
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.3333584805
Short name T895
Test name
Test status
Simulation time 8061080812 ps
CPU time 55.89 seconds
Started Jun 30 06:26:48 PM PDT 24
Finished Jun 30 06:27:45 PM PDT 24
Peak memory 206420 kb
Host smart-60cf004a-97b7-45c7-a9ce-901d96146a18
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3333584805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.3333584805
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.344753765
Short name T664
Test name
Test status
Simulation time 250771901 ps
CPU time 0.94 seconds
Started Jun 30 06:26:34 PM PDT 24
Finished Jun 30 06:26:35 PM PDT 24
Peak memory 206188 kb
Host smart-3eb96c96-77a3-4aa1-a5c0-da07623c75de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34475
3765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.344753765
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.3752966691
Short name T584
Test name
Test status
Simulation time 23312277948 ps
CPU time 20.73 seconds
Started Jun 30 06:26:36 PM PDT 24
Finished Jun 30 06:26:58 PM PDT 24
Peak memory 206280 kb
Host smart-1a90dd58-eb8e-4764-b561-151a1f1d0069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37529
66691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.3752966691
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.630884415
Short name T416
Test name
Test status
Simulation time 3322506294 ps
CPU time 3.55 seconds
Started Jun 30 06:26:47 PM PDT 24
Finished Jun 30 06:26:52 PM PDT 24
Peak memory 206232 kb
Host smart-f92c8ee2-66cf-4b66-9200-755ec1b2beb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63088
4415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.630884415
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.87781815
Short name T614
Test name
Test status
Simulation time 13288646176 ps
CPU time 127.02 seconds
Started Jun 30 06:26:48 PM PDT 24
Finished Jun 30 06:28:56 PM PDT 24
Peak memory 206472 kb
Host smart-bcc6dffe-df64-4aa4-89ee-6c7bda2ed7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87781
815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.87781815
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.3697110297
Short name T628
Test name
Test status
Simulation time 5708334365 ps
CPU time 154.51 seconds
Started Jun 30 06:26:48 PM PDT 24
Finished Jun 30 06:29:24 PM PDT 24
Peak memory 206464 kb
Host smart-7400cdab-d0eb-4eeb-80c7-d2d11bbce07c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3697110297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3697110297
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3071822538
Short name T2010
Test name
Test status
Simulation time 249435056 ps
CPU time 0.92 seconds
Started Jun 30 06:26:36 PM PDT 24
Finished Jun 30 06:26:38 PM PDT 24
Peak memory 206204 kb
Host smart-4a490af3-44cb-4939-947c-997ccfd01776
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3071822538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3071822538
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3596736419
Short name T665
Test name
Test status
Simulation time 183068736 ps
CPU time 0.84 seconds
Started Jun 30 06:26:40 PM PDT 24
Finished Jun 30 06:26:42 PM PDT 24
Peak memory 206200 kb
Host smart-e78b9cf9-f4c4-4240-89ac-e2a4ae052600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35967
36419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3596736419
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.3985184429
Short name T1197
Test name
Test status
Simulation time 5526677286 ps
CPU time 149.7 seconds
Started Jun 30 06:26:53 PM PDT 24
Finished Jun 30 06:29:23 PM PDT 24
Peak memory 206444 kb
Host smart-3dcfada7-1f23-4774-be0e-6a4aa58cb65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39851
84429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.3985184429
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3317308830
Short name T888
Test name
Test status
Simulation time 5318674300 ps
CPU time 47.25 seconds
Started Jun 30 06:26:35 PM PDT 24
Finished Jun 30 06:27:23 PM PDT 24
Peak memory 206380 kb
Host smart-f4fe5e39-deb3-459c-bf3f-6723deb034b5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3317308830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3317308830
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2445338135
Short name T649
Test name
Test status
Simulation time 186815406 ps
CPU time 0.83 seconds
Started Jun 30 06:26:49 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206216 kb
Host smart-1bceca45-ff1d-46ca-b9c9-3c44a5ee9c2b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2445338135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2445338135
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.805429784
Short name T1459
Test name
Test status
Simulation time 209117245 ps
CPU time 0.84 seconds
Started Jun 30 06:26:49 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206200 kb
Host smart-2a017b21-e1fe-45ed-bd80-052a885e563f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80542
9784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.805429784
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.4138317498
Short name T1749
Test name
Test status
Simulation time 240038421 ps
CPU time 0.89 seconds
Started Jun 30 06:26:51 PM PDT 24
Finished Jun 30 06:26:52 PM PDT 24
Peak memory 206176 kb
Host smart-dd09b100-e98f-42b5-8e70-3d333a19cccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41383
17498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4138317498
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2097816443
Short name T905
Test name
Test status
Simulation time 166043910 ps
CPU time 0.82 seconds
Started Jun 30 06:26:47 PM PDT 24
Finished Jun 30 06:26:49 PM PDT 24
Peak memory 206180 kb
Host smart-5174f011-fb1c-4f61-ba7f-fba89d925fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20978
16443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2097816443
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2471315661
Short name T1439
Test name
Test status
Simulation time 208082497 ps
CPU time 0.92 seconds
Started Jun 30 06:26:51 PM PDT 24
Finished Jun 30 06:26:52 PM PDT 24
Peak memory 206348 kb
Host smart-7115fea2-dbcd-4393-bd3c-e2ad0a267024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24713
15661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2471315661
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1027996521
Short name T633
Test name
Test status
Simulation time 185940370 ps
CPU time 0.86 seconds
Started Jun 30 06:26:48 PM PDT 24
Finished Jun 30 06:26:50 PM PDT 24
Peak memory 206220 kb
Host smart-5fb3ab9e-cc80-44db-b9e0-91b4b41b305b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10279
96521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1027996521
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2213883460
Short name T1741
Test name
Test status
Simulation time 173637532 ps
CPU time 0.82 seconds
Started Jun 30 06:26:49 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206156 kb
Host smart-f48a0103-ded1-4707-aac0-6e5bb734ae4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22138
83460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2213883460
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2038256031
Short name T2111
Test name
Test status
Simulation time 276710364 ps
CPU time 0.98 seconds
Started Jun 30 06:26:46 PM PDT 24
Finished Jun 30 06:26:48 PM PDT 24
Peak memory 206188 kb
Host smart-e3bb01b0-5f08-4b76-b64e-3562c756a214
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2038256031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2038256031
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2977646978
Short name T42
Test name
Test status
Simulation time 151271255 ps
CPU time 0.78 seconds
Started Jun 30 06:26:50 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206204 kb
Host smart-66ade26e-8d5e-429b-8ca0-fb2e92dd2878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29776
46978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2977646978
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2511435814
Short name T1682
Test name
Test status
Simulation time 55223850 ps
CPU time 0.71 seconds
Started Jun 30 06:26:40 PM PDT 24
Finished Jun 30 06:26:42 PM PDT 24
Peak memory 206212 kb
Host smart-24dffa4d-ab33-40a6-8f8f-ca9e2534b445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25114
35814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2511435814
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1020706517
Short name T270
Test name
Test status
Simulation time 23394338789 ps
CPU time 56.76 seconds
Started Jun 30 06:26:50 PM PDT 24
Finished Jun 30 06:27:48 PM PDT 24
Peak memory 206496 kb
Host smart-92d938a0-2a0c-4bf9-a0f6-333d98f2cabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10207
06517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1020706517
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1090795490
Short name T2517
Test name
Test status
Simulation time 184908587 ps
CPU time 0.87 seconds
Started Jun 30 06:26:49 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206180 kb
Host smart-5fa91fef-054a-483e-9424-043bc6bd26d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10907
95490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1090795490
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1977342195
Short name T2074
Test name
Test status
Simulation time 185639895 ps
CPU time 0.84 seconds
Started Jun 30 06:26:39 PM PDT 24
Finished Jun 30 06:26:41 PM PDT 24
Peak memory 206180 kb
Host smart-9bd9bec5-50ee-4803-b1e7-11163aafbe71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19773
42195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1977342195
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.3845985115
Short name T827
Test name
Test status
Simulation time 177661106 ps
CPU time 0.78 seconds
Started Jun 30 06:26:41 PM PDT 24
Finished Jun 30 06:26:43 PM PDT 24
Peak memory 206220 kb
Host smart-181f061a-60da-4d48-a7f5-311ce353c84e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38459
85115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.3845985115
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.2879078486
Short name T2467
Test name
Test status
Simulation time 212509535 ps
CPU time 0.97 seconds
Started Jun 30 06:26:49 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206200 kb
Host smart-c85bc8a2-3d4c-42d1-93e6-1369e7a9cbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28790
78486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.2879078486
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.3405487384
Short name T538
Test name
Test status
Simulation time 150684199 ps
CPU time 0.74 seconds
Started Jun 30 06:26:40 PM PDT 24
Finished Jun 30 06:26:42 PM PDT 24
Peak memory 206172 kb
Host smart-53888652-1b48-4192-a809-b75176259bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34054
87384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.3405487384
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1164737258
Short name T485
Test name
Test status
Simulation time 164642433 ps
CPU time 0.8 seconds
Started Jun 30 06:26:45 PM PDT 24
Finished Jun 30 06:26:46 PM PDT 24
Peak memory 206188 kb
Host smart-2f02ea09-c6cf-47fa-8ee3-60c6019ae185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11647
37258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1164737258
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2771349457
Short name T2379
Test name
Test status
Simulation time 154442705 ps
CPU time 0.87 seconds
Started Jun 30 06:26:59 PM PDT 24
Finished Jun 30 06:27:01 PM PDT 24
Peak memory 206192 kb
Host smart-00932725-6f96-4955-80d1-931ac89445dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27713
49457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2771349457
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1405987218
Short name T1005
Test name
Test status
Simulation time 228794371 ps
CPU time 0.89 seconds
Started Jun 30 06:26:48 PM PDT 24
Finished Jun 30 06:26:50 PM PDT 24
Peak memory 206188 kb
Host smart-a44db547-5e10-4902-9932-70b7c6b6a540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14059
87218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1405987218
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3258105027
Short name T2385
Test name
Test status
Simulation time 3856080794 ps
CPU time 108.76 seconds
Started Jun 30 06:26:42 PM PDT 24
Finished Jun 30 06:28:31 PM PDT 24
Peak memory 206448 kb
Host smart-4056776c-fb0d-4f3f-aaab-3fcd423480b3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3258105027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3258105027
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.320077717
Short name T2493
Test name
Test status
Simulation time 147884624 ps
CPU time 0.83 seconds
Started Jun 30 06:26:55 PM PDT 24
Finished Jun 30 06:26:57 PM PDT 24
Peak memory 206212 kb
Host smart-aedbe634-5568-4b78-aa44-fff6346bc055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32007
7717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.320077717
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2068591811
Short name T1055
Test name
Test status
Simulation time 181668138 ps
CPU time 0.86 seconds
Started Jun 30 06:26:55 PM PDT 24
Finished Jun 30 06:26:56 PM PDT 24
Peak memory 206156 kb
Host smart-3cf71403-a72e-428b-98a7-1a6d96519784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20685
91811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2068591811
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1345380763
Short name T1348
Test name
Test status
Simulation time 6626704316 ps
CPU time 172.99 seconds
Started Jun 30 06:26:48 PM PDT 24
Finished Jun 30 06:29:42 PM PDT 24
Peak memory 206292 kb
Host smart-03ccf911-efc3-4bc1-991e-ad8b02f52ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13453
80763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1345380763
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.1491386452
Short name T618
Test name
Test status
Simulation time 49738819 ps
CPU time 0.69 seconds
Started Jun 30 06:26:57 PM PDT 24
Finished Jun 30 06:26:58 PM PDT 24
Peak memory 206204 kb
Host smart-9f18e4a6-ed84-484e-9a7c-b15dcd0252c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1491386452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.1491386452
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.493620336
Short name T1890
Test name
Test status
Simulation time 4330067202 ps
CPU time 4.91 seconds
Started Jun 30 06:26:39 PM PDT 24
Finished Jun 30 06:26:45 PM PDT 24
Peak memory 206472 kb
Host smart-8c72ec3e-87af-4491-88a9-4fe4878530df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=493620336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.493620336
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.4158717027
Short name T835
Test name
Test status
Simulation time 13373252413 ps
CPU time 13.26 seconds
Started Jun 30 06:26:47 PM PDT 24
Finished Jun 30 06:27:01 PM PDT 24
Peak memory 206368 kb
Host smart-e51e981e-4333-4e0b-a6ed-96c4293131da
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4158717027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.4158717027
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.876359396
Short name T591
Test name
Test status
Simulation time 23415475888 ps
CPU time 23.84 seconds
Started Jun 30 06:26:40 PM PDT 24
Finished Jun 30 06:27:05 PM PDT 24
Peak memory 206288 kb
Host smart-ce2a6266-81d9-4a67-adbe-3af8b87455f9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=876359396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.876359396
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.38791228
Short name T149
Test name
Test status
Simulation time 165635211 ps
CPU time 0.86 seconds
Started Jun 30 06:26:51 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206164 kb
Host smart-93ecf8db-aec4-4eb6-bcfb-4e839e3c92bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38791
228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.38791228
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.3481279752
Short name T529
Test name
Test status
Simulation time 154254053 ps
CPU time 0.81 seconds
Started Jun 30 06:26:39 PM PDT 24
Finished Jun 30 06:26:41 PM PDT 24
Peak memory 206200 kb
Host smart-72084588-5152-4f2a-9a6c-309742ef5ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34812
79752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.3481279752
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.3875352442
Short name T1600
Test name
Test status
Simulation time 337502399 ps
CPU time 1.13 seconds
Started Jun 30 06:26:40 PM PDT 24
Finished Jun 30 06:26:43 PM PDT 24
Peak memory 206196 kb
Host smart-c825c8e9-37c1-4ed3-af41-8f0d732daa25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38753
52442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.3875352442
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3737380648
Short name T1681
Test name
Test status
Simulation time 284841130 ps
CPU time 0.92 seconds
Started Jun 30 06:26:49 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206184 kb
Host smart-56c4043b-e980-4e45-a843-f10b60c1d9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37373
80648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3737380648
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.1136279346
Short name T2461
Test name
Test status
Simulation time 20607803719 ps
CPU time 39.55 seconds
Started Jun 30 06:26:40 PM PDT 24
Finished Jun 30 06:27:21 PM PDT 24
Peak memory 206376 kb
Host smart-997b6595-0314-4f0a-8767-56d89b885304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11362
79346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1136279346
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.242619685
Short name T1868
Test name
Test status
Simulation time 360219782 ps
CPU time 1.25 seconds
Started Jun 30 06:26:57 PM PDT 24
Finished Jun 30 06:26:59 PM PDT 24
Peak memory 206160 kb
Host smart-39d1f030-ca6a-4347-8274-3f2ffc5cc80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24261
9685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.242619685
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1588017368
Short name T1238
Test name
Test status
Simulation time 167615473 ps
CPU time 0.78 seconds
Started Jun 30 06:26:45 PM PDT 24
Finished Jun 30 06:26:46 PM PDT 24
Peak memory 206196 kb
Host smart-6ac41fff-9e08-45b0-8de2-e9468131b415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15880
17368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1588017368
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3018712767
Short name T1195
Test name
Test status
Simulation time 33642086 ps
CPU time 0.64 seconds
Started Jun 30 06:26:47 PM PDT 24
Finished Jun 30 06:26:49 PM PDT 24
Peak memory 206164 kb
Host smart-b0d51773-e486-42a1-afeb-102f83a9fb20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30187
12767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3018712767
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2422327347
Short name T823
Test name
Test status
Simulation time 1053033343 ps
CPU time 2.61 seconds
Started Jun 30 06:26:50 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206336 kb
Host smart-0bb05470-bb27-4390-8611-6384ceb47791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24223
27347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2422327347
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3604217930
Short name T454
Test name
Test status
Simulation time 218522788 ps
CPU time 1.23 seconds
Started Jun 30 06:26:47 PM PDT 24
Finished Jun 30 06:26:50 PM PDT 24
Peak memory 206264 kb
Host smart-4266ede9-7874-4e9f-8372-601dfe534182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36042
17930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3604217930
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2134980476
Short name T1791
Test name
Test status
Simulation time 191882288 ps
CPU time 0.87 seconds
Started Jun 30 06:26:51 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206180 kb
Host smart-1eb4f0ee-3734-445c-8f54-a5426cfdb626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21349
80476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2134980476
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1702793969
Short name T2145
Test name
Test status
Simulation time 135948509 ps
CPU time 0.75 seconds
Started Jun 30 06:26:48 PM PDT 24
Finished Jun 30 06:26:49 PM PDT 24
Peak memory 206208 kb
Host smart-082b85e6-39c1-4d7e-9a46-cb0f1bc1e501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17027
93969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1702793969
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1093577190
Short name T750
Test name
Test status
Simulation time 239712767 ps
CPU time 1.03 seconds
Started Jun 30 06:26:51 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206196 kb
Host smart-16cab176-d633-4564-80d6-67eb158cec57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10935
77190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1093577190
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.1467270549
Short name T74
Test name
Test status
Simulation time 6476446092 ps
CPU time 175.98 seconds
Started Jun 30 06:26:44 PM PDT 24
Finished Jun 30 06:29:41 PM PDT 24
Peak memory 206468 kb
Host smart-e5f74f03-53c8-427c-9eb6-720c03b3cc1e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1467270549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1467270549
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2521717309
Short name T1870
Test name
Test status
Simulation time 210356719 ps
CPU time 0.97 seconds
Started Jun 30 06:26:51 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206340 kb
Host smart-748a0761-c680-4606-9706-f3872ff03cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25217
17309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2521717309
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3091581931
Short name T2147
Test name
Test status
Simulation time 23278648885 ps
CPU time 26.64 seconds
Started Jun 30 06:27:09 PM PDT 24
Finished Jun 30 06:27:38 PM PDT 24
Peak memory 206312 kb
Host smart-7328d07b-b6d2-4984-8914-fec8b82ec4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30915
81931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3091581931
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3869719687
Short name T1337
Test name
Test status
Simulation time 3355436395 ps
CPU time 3.78 seconds
Started Jun 30 06:26:59 PM PDT 24
Finished Jun 30 06:27:04 PM PDT 24
Peak memory 206168 kb
Host smart-5530ad15-1884-41da-8f71-62d209b38eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38697
19687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3869719687
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.3117394342
Short name T1000
Test name
Test status
Simulation time 8068188487 ps
CPU time 222.17 seconds
Started Jun 30 06:26:55 PM PDT 24
Finished Jun 30 06:30:38 PM PDT 24
Peak memory 206460 kb
Host smart-564a4330-80b0-4eb4-805c-e15a7e268c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31173
94342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.3117394342
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2957002813
Short name T1731
Test name
Test status
Simulation time 5914638962 ps
CPU time 154.55 seconds
Started Jun 30 06:27:03 PM PDT 24
Finished Jun 30 06:29:39 PM PDT 24
Peak memory 206456 kb
Host smart-0df7dbe5-0bf1-4a7b-b9b0-d0b16897919f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2957002813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2957002813
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.240720775
Short name T350
Test name
Test status
Simulation time 242588939 ps
CPU time 0.94 seconds
Started Jun 30 06:26:56 PM PDT 24
Finished Jun 30 06:26:57 PM PDT 24
Peak memory 206216 kb
Host smart-850c3d7c-8a31-4880-8f49-a3be31a30a43
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=240720775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.240720775
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1367066636
Short name T1973
Test name
Test status
Simulation time 224012509 ps
CPU time 0.96 seconds
Started Jun 30 06:27:02 PM PDT 24
Finished Jun 30 06:27:04 PM PDT 24
Peak memory 206208 kb
Host smart-5f025d4d-e9b7-4c20-98c5-93e8fcc8a326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13670
66636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1367066636
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3447689120
Short name T763
Test name
Test status
Simulation time 3884288506 ps
CPU time 103.37 seconds
Started Jun 30 06:26:51 PM PDT 24
Finished Jun 30 06:28:35 PM PDT 24
Peak memory 206436 kb
Host smart-9dc754bf-db1a-4ace-94f6-a18f667c1d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34476
89120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3447689120
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.285419790
Short name T990
Test name
Test status
Simulation time 4011514943 ps
CPU time 37.32 seconds
Started Jun 30 06:27:02 PM PDT 24
Finished Jun 30 06:27:41 PM PDT 24
Peak memory 206408 kb
Host smart-9eff6b97-cd4d-4378-a3fc-889637dbd856
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=285419790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.285419790
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2599192815
Short name T1970
Test name
Test status
Simulation time 187343895 ps
CPU time 0.76 seconds
Started Jun 30 06:26:50 PM PDT 24
Finished Jun 30 06:26:52 PM PDT 24
Peak memory 206144 kb
Host smart-487d925d-526c-444c-ab19-f1637535b972
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2599192815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2599192815
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.274064044
Short name T237
Test name
Test status
Simulation time 158765941 ps
CPU time 0.8 seconds
Started Jun 30 06:26:50 PM PDT 24
Finished Jun 30 06:26:56 PM PDT 24
Peak memory 206208 kb
Host smart-155654c4-32bf-44bb-a8c7-eb4dc419ebb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27406
4044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.274064044
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.350771748
Short name T1625
Test name
Test status
Simulation time 227006252 ps
CPU time 0.9 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 206188 kb
Host smart-17812cc3-f6ad-4449-93d2-531f31c221ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077
1748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.350771748
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.1290109595
Short name T2474
Test name
Test status
Simulation time 201854479 ps
CPU time 0.87 seconds
Started Jun 30 06:27:00 PM PDT 24
Finished Jun 30 06:27:02 PM PDT 24
Peak memory 206208 kb
Host smart-d262e460-7009-4bc6-9d6f-06d24671f963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12901
09595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1290109595
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.480709576
Short name T741
Test name
Test status
Simulation time 206079612 ps
CPU time 0.89 seconds
Started Jun 30 06:27:04 PM PDT 24
Finished Jun 30 06:27:06 PM PDT 24
Peak memory 206192 kb
Host smart-14268e5e-3bb2-4256-9992-40bb0fff1297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48070
9576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.480709576
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.731466233
Short name T1176
Test name
Test status
Simulation time 183363488 ps
CPU time 0.83 seconds
Started Jun 30 06:26:58 PM PDT 24
Finished Jun 30 06:27:00 PM PDT 24
Peak memory 206156 kb
Host smart-6efdfb7b-f7e3-4b9b-96c9-377fcc10b0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73146
6233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.731466233
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2173153574
Short name T203
Test name
Test status
Simulation time 160957764 ps
CPU time 0.77 seconds
Started Jun 30 06:27:04 PM PDT 24
Finished Jun 30 06:27:07 PM PDT 24
Peak memory 206220 kb
Host smart-87dde258-3e14-4c8a-8fea-9a9d7bb01fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21731
53574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2173153574
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3247809023
Short name T492
Test name
Test status
Simulation time 247971976 ps
CPU time 0.93 seconds
Started Jun 30 06:26:51 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206208 kb
Host smart-e055440d-3809-4af7-9d12-067c576d3edb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3247809023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3247809023
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1934459972
Short name T1016
Test name
Test status
Simulation time 150217687 ps
CPU time 0.74 seconds
Started Jun 30 06:26:50 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206200 kb
Host smart-cc34a0b1-8aea-4840-ab65-d7a765c09e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19344
59972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1934459972
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.501317292
Short name T978
Test name
Test status
Simulation time 56426691 ps
CPU time 0.67 seconds
Started Jun 30 06:27:06 PM PDT 24
Finished Jun 30 06:27:09 PM PDT 24
Peak memory 206224 kb
Host smart-cf57d911-c07b-4123-bb66-ceec29723133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50131
7292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.501317292
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.618121748
Short name T294
Test name
Test status
Simulation time 7751622641 ps
CPU time 16.02 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:24 PM PDT 24
Peak memory 206252 kb
Host smart-d72b3423-dadd-4f46-8baa-d72fd16f548b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61812
1748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.618121748
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2531805498
Short name T948
Test name
Test status
Simulation time 208174972 ps
CPU time 0.89 seconds
Started Jun 30 06:26:55 PM PDT 24
Finished Jun 30 06:26:56 PM PDT 24
Peak memory 205968 kb
Host smart-3aeeff21-e852-4b60-a48d-0be4f908b4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25318
05498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2531805498
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1379952000
Short name T998
Test name
Test status
Simulation time 187275750 ps
CPU time 0.82 seconds
Started Jun 30 06:27:02 PM PDT 24
Finished Jun 30 06:27:04 PM PDT 24
Peak memory 206180 kb
Host smart-37645aae-cd4e-4218-a70e-cb94ec64b32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13799
52000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1379952000
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1526477831
Short name T1688
Test name
Test status
Simulation time 232769315 ps
CPU time 0.85 seconds
Started Jun 30 06:27:11 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 206204 kb
Host smart-49c5188b-87cd-4070-88dc-c4324c0efda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15264
77831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1526477831
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3130554195
Short name T343
Test name
Test status
Simulation time 153269138 ps
CPU time 0.78 seconds
Started Jun 30 06:26:51 PM PDT 24
Finished Jun 30 06:26:53 PM PDT 24
Peak memory 206180 kb
Host smart-d924aaa9-2dab-41ff-aff8-bf56b5739b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31305
54195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3130554195
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.215882604
Short name T774
Test name
Test status
Simulation time 159684966 ps
CPU time 0.79 seconds
Started Jun 30 06:26:55 PM PDT 24
Finished Jun 30 06:26:56 PM PDT 24
Peak memory 206004 kb
Host smart-4a25e52c-3e69-451a-89d6-c47d5a2bd6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21588
2604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.215882604
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2448526825
Short name T2203
Test name
Test status
Simulation time 155336675 ps
CPU time 0.77 seconds
Started Jun 30 06:26:54 PM PDT 24
Finished Jun 30 06:26:55 PM PDT 24
Peak memory 206188 kb
Host smart-db7e4d89-2f12-4263-a4d5-cb04d23dcd7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24485
26825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2448526825
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2316331083
Short name T1050
Test name
Test status
Simulation time 163252062 ps
CPU time 0.83 seconds
Started Jun 30 06:26:49 PM PDT 24
Finished Jun 30 06:26:51 PM PDT 24
Peak memory 206176 kb
Host smart-10ae7ab1-376e-4a08-8aee-8584b2bbaece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
31083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2316331083
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2684269889
Short name T2630
Test name
Test status
Simulation time 176122238 ps
CPU time 0.84 seconds
Started Jun 30 06:27:09 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 206232 kb
Host smart-10c3e031-8158-4044-9e29-1ee843128481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26842
69889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2684269889
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1758229450
Short name T1086
Test name
Test status
Simulation time 6204112490 ps
CPU time 59.51 seconds
Started Jun 30 06:27:04 PM PDT 24
Finished Jun 30 06:28:05 PM PDT 24
Peak memory 206356 kb
Host smart-d29932fa-ddd7-464f-bb17-2097beeb15ab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1758229450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1758229450
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1219816837
Short name T970
Test name
Test status
Simulation time 199052197 ps
CPU time 0.83 seconds
Started Jun 30 06:27:06 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 206192 kb
Host smart-0c027f83-a497-423e-94fa-48210d8e706b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12198
16837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1219816837
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2793093169
Short name T2244
Test name
Test status
Simulation time 172784752 ps
CPU time 0.9 seconds
Started Jun 30 06:26:53 PM PDT 24
Finished Jun 30 06:26:55 PM PDT 24
Peak memory 206184 kb
Host smart-4a09b0c5-f683-449d-b004-498eb1bba5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27930
93169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2793093169
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.18323
Short name T1637
Test name
Test status
Simulation time 4153038641 ps
CPU time 105.32 seconds
Started Jun 30 06:26:48 PM PDT 24
Finished Jun 30 06:28:35 PM PDT 24
Peak memory 206644 kb
Host smart-3c68846a-55ed-4bb1-b464-fd0114f7b4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18323
-assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.18323
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.4263073955
Short name T465
Test name
Test status
Simulation time 54417145 ps
CPU time 0.67 seconds
Started Jun 30 06:27:06 PM PDT 24
Finished Jun 30 06:27:09 PM PDT 24
Peak memory 206192 kb
Host smart-4cb22c85-c4ea-4039-aa51-bc6a2cc24c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4263073955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.4263073955
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1773364473
Short name T939
Test name
Test status
Simulation time 4384999813 ps
CPU time 4.73 seconds
Started Jun 30 06:26:59 PM PDT 24
Finished Jun 30 06:27:05 PM PDT 24
Peak memory 206252 kb
Host smart-4c5ce43a-3f9e-490c-a4ca-94a820388306
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1773364473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.1773364473
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2967762197
Short name T1991
Test name
Test status
Simulation time 13378191037 ps
CPU time 12.19 seconds
Started Jun 30 06:27:00 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 206316 kb
Host smart-1d677088-0846-4be9-b05e-049579fb570a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2967762197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2967762197
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.56632677
Short name T242
Test name
Test status
Simulation time 23390642890 ps
CPU time 25.85 seconds
Started Jun 30 06:26:47 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 206448 kb
Host smart-93e49e52-272c-47ec-8925-b9ec8e0c0b12
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=56632677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.56632677
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.4099309334
Short name T1939
Test name
Test status
Simulation time 196742722 ps
CPU time 0.89 seconds
Started Jun 30 06:26:53 PM PDT 24
Finished Jun 30 06:26:55 PM PDT 24
Peak memory 206176 kb
Host smart-618b4161-27d6-42d6-a527-a9d31dca40c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40993
09334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.4099309334
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.4060270081
Short name T1865
Test name
Test status
Simulation time 162232069 ps
CPU time 0.78 seconds
Started Jun 30 06:26:47 PM PDT 24
Finished Jun 30 06:26:49 PM PDT 24
Peak memory 206184 kb
Host smart-d2e5ff0a-04f1-4430-9c8d-712dadea066e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40602
70081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.4060270081
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.4185505317
Short name T1936
Test name
Test status
Simulation time 447327418 ps
CPU time 1.38 seconds
Started Jun 30 06:26:56 PM PDT 24
Finished Jun 30 06:26:58 PM PDT 24
Peak memory 206248 kb
Host smart-621221e6-0a06-49d3-91ad-5b2d07fa5ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41855
05317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.4185505317
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.4000169602
Short name T194
Test name
Test status
Simulation time 1251497166 ps
CPU time 2.98 seconds
Started Jun 30 06:26:58 PM PDT 24
Finished Jun 30 06:27:02 PM PDT 24
Peak memory 206264 kb
Host smart-220a98e1-c04e-40fa-a1f6-c97061ec875e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40001
69602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.4000169602
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2685303357
Short name T2114
Test name
Test status
Simulation time 17255634368 ps
CPU time 29.11 seconds
Started Jun 30 06:26:57 PM PDT 24
Finished Jun 30 06:27:26 PM PDT 24
Peak memory 206484 kb
Host smart-42a3f057-0a21-46c0-bde7-4d3dbb5c91f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26853
03357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2685303357
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.3027277004
Short name T645
Test name
Test status
Simulation time 434754417 ps
CPU time 1.31 seconds
Started Jun 30 06:27:10 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 206200 kb
Host smart-35090621-7850-41ad-ae5e-91b1b83e34a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30272
77004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.3027277004
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3567311057
Short name T959
Test name
Test status
Simulation time 158817730 ps
CPU time 0.79 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:09 PM PDT 24
Peak memory 206180 kb
Host smart-3f391bc9-3b56-49e1-86b8-5feedb0528eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35673
11057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3567311057
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.1724558539
Short name T1081
Test name
Test status
Simulation time 43708025 ps
CPU time 0.67 seconds
Started Jun 30 06:26:58 PM PDT 24
Finished Jun 30 06:27:00 PM PDT 24
Peak memory 206180 kb
Host smart-d7383379-7991-4187-a30d-3e358ae6e7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
58539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1724558539
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1013773381
Short name T885
Test name
Test status
Simulation time 801645484 ps
CPU time 1.87 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:11 PM PDT 24
Peak memory 206332 kb
Host smart-9deb0d55-8cc9-4650-b68a-0c36a2bf68f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10137
73381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1013773381
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.535810491
Short name T1658
Test name
Test status
Simulation time 282721891 ps
CPU time 2.18 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:18 PM PDT 24
Peak memory 206244 kb
Host smart-711dd100-bafa-496d-97ef-cb649f2278f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53581
0491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.535810491
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.412690853
Short name T1898
Test name
Test status
Simulation time 214411656 ps
CPU time 0.87 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:11 PM PDT 24
Peak memory 206068 kb
Host smart-5059de1f-6f02-48d2-9384-5b2b3b751f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41269
0853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.412690853
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3072218314
Short name T380
Test name
Test status
Simulation time 151029562 ps
CPU time 0.78 seconds
Started Jun 30 06:26:55 PM PDT 24
Finished Jun 30 06:26:56 PM PDT 24
Peak memory 206204 kb
Host smart-599a6fe4-d1fc-4a1a-82ed-f6febb312a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30722
18314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3072218314
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.4075006173
Short name T1414
Test name
Test status
Simulation time 247944589 ps
CPU time 0.87 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 206232 kb
Host smart-ec470123-026b-4b0a-ab36-aa87da0448cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40750
06173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.4075006173
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.2586412570
Short name T602
Test name
Test status
Simulation time 7081061793 ps
CPU time 194.28 seconds
Started Jun 30 06:26:58 PM PDT 24
Finished Jun 30 06:30:13 PM PDT 24
Peak memory 206448 kb
Host smart-e68fec57-5708-4d12-beb2-76b412365c75
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2586412570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.2586412570
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2615492166
Short name T58
Test name
Test status
Simulation time 222295017 ps
CPU time 0.89 seconds
Started Jun 30 06:27:04 PM PDT 24
Finished Jun 30 06:27:07 PM PDT 24
Peak memory 206120 kb
Host smart-95e81160-40e5-4476-b706-30d3b025554e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26154
92166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2615492166
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3061694039
Short name T2400
Test name
Test status
Simulation time 23339150047 ps
CPU time 26.17 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:34 PM PDT 24
Peak memory 206308 kb
Host smart-e4d3e924-0a2e-4278-bd47-23888d1edfee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30616
94039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3061694039
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3490721196
Short name T1098
Test name
Test status
Simulation time 3361846293 ps
CPU time 4.84 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 206248 kb
Host smart-c612d0f4-99cd-44c0-9d08-45dc89ec1e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34907
21196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3490721196
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1640722588
Short name T1207
Test name
Test status
Simulation time 10652694302 ps
CPU time 98.63 seconds
Started Jun 30 06:27:16 PM PDT 24
Finished Jun 30 06:28:58 PM PDT 24
Peak memory 206420 kb
Host smart-0b9b2197-9968-4657-8397-69603e27e3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16407
22588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1640722588
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.4268174267
Short name T1419
Test name
Test status
Simulation time 4917476161 ps
CPU time 42.95 seconds
Started Jun 30 06:27:01 PM PDT 24
Finished Jun 30 06:27:44 PM PDT 24
Peak memory 206452 kb
Host smart-09630216-aced-4cbf-b933-63b785cd6298
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4268174267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.4268174267
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2298477411
Short name T496
Test name
Test status
Simulation time 237831709 ps
CPU time 0.91 seconds
Started Jun 30 06:27:10 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 206200 kb
Host smart-bb54aad4-f545-48b9-80ae-837cfd550add
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2298477411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2298477411
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.4209275344
Short name T1025
Test name
Test status
Simulation time 191580707 ps
CPU time 0.86 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:16 PM PDT 24
Peak memory 206200 kb
Host smart-4ffdc514-5204-4a3e-9579-59f4c27c3a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42092
75344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.4209275344
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.3354754282
Short name T1113
Test name
Test status
Simulation time 6503579531 ps
CPU time 44.19 seconds
Started Jun 30 06:26:57 PM PDT 24
Finished Jun 30 06:27:41 PM PDT 24
Peak memory 206460 kb
Host smart-d7f8d963-5bb7-49a8-86e5-9fa02fa20b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33547
54282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.3354754282
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.4029432719
Short name T711
Test name
Test status
Simulation time 5986725538 ps
CPU time 59.58 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:28:07 PM PDT 24
Peak memory 206400 kb
Host smart-1e054b73-8b10-492e-9b30-a700f753d0ac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4029432719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.4029432719
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.299415201
Short name T1502
Test name
Test status
Simulation time 153486746 ps
CPU time 0.76 seconds
Started Jun 30 06:26:59 PM PDT 24
Finished Jun 30 06:27:00 PM PDT 24
Peak memory 206204 kb
Host smart-153c5bea-98c9-49e7-ab6a-4e2adae8abd9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=299415201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.299415201
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3378542502
Short name T1799
Test name
Test status
Simulation time 176143691 ps
CPU time 0.8 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:08 PM PDT 24
Peak memory 206196 kb
Host smart-6169cf7d-0fc7-47b5-9abc-69ac9b65cc25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33785
42502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3378542502
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3513187753
Short name T2106
Test name
Test status
Simulation time 206146434 ps
CPU time 0.92 seconds
Started Jun 30 06:27:04 PM PDT 24
Finished Jun 30 06:27:06 PM PDT 24
Peak memory 206172 kb
Host smart-87db9b00-6586-44b6-a9a6-30c548b6ccba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35131
87753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3513187753
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1302311904
Short name T414
Test name
Test status
Simulation time 199285207 ps
CPU time 0.84 seconds
Started Jun 30 06:27:00 PM PDT 24
Finished Jun 30 06:27:01 PM PDT 24
Peak memory 206204 kb
Host smart-93773e1d-3e68-4086-ab5d-f169f6982609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13023
11904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1302311904
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2587318953
Short name T650
Test name
Test status
Simulation time 166782952 ps
CPU time 0.78 seconds
Started Jun 30 06:26:58 PM PDT 24
Finished Jun 30 06:27:00 PM PDT 24
Peak memory 206172 kb
Host smart-24983ac7-67f6-4c94-8d56-9afd16193603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25873
18953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2587318953
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2010047275
Short name T1500
Test name
Test status
Simulation time 149677704 ps
CPU time 0.78 seconds
Started Jun 30 06:27:11 PM PDT 24
Finished Jun 30 06:27:14 PM PDT 24
Peak memory 206204 kb
Host smart-c35cfe16-3f90-48c6-9152-7ad5a274d9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20100
47275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2010047275
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1319765676
Short name T692
Test name
Test status
Simulation time 145908916 ps
CPU time 0.77 seconds
Started Jun 30 06:27:01 PM PDT 24
Finished Jun 30 06:27:03 PM PDT 24
Peak memory 206220 kb
Host smart-4f9a8e97-aca9-4cbf-baee-fca4aaa5a4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13197
65676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1319765676
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3926979261
Short name T48
Test name
Test status
Simulation time 255013478 ps
CPU time 0.99 seconds
Started Jun 30 06:27:13 PM PDT 24
Finished Jun 30 06:27:17 PM PDT 24
Peak memory 206212 kb
Host smart-e97d8865-67a0-43f9-98bf-fbb25f99b836
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3926979261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3926979261
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3759717806
Short name T861
Test name
Test status
Simulation time 158700062 ps
CPU time 0.75 seconds
Started Jun 30 06:27:10 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 206196 kb
Host smart-ca57ad61-c69d-4f06-af39-072d2ce772bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37597
17806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3759717806
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.248373239
Short name T1208
Test name
Test status
Simulation time 48877735 ps
CPU time 0.65 seconds
Started Jun 30 06:27:09 PM PDT 24
Finished Jun 30 06:27:12 PM PDT 24
Peak memory 206200 kb
Host smart-6d3c7661-c290-4c1f-92ed-3aa3662a17bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24837
3239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.248373239
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2177825579
Short name T2413
Test name
Test status
Simulation time 20200199424 ps
CPU time 49.38 seconds
Started Jun 30 06:27:01 PM PDT 24
Finished Jun 30 06:27:51 PM PDT 24
Peak memory 206376 kb
Host smart-0229dbc9-5207-4d6a-bc1b-c089a244ccda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21778
25579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2177825579
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3297011085
Short name T1947
Test name
Test status
Simulation time 187106260 ps
CPU time 0.8 seconds
Started Jun 30 06:27:15 PM PDT 24
Finished Jun 30 06:27:19 PM PDT 24
Peak memory 206140 kb
Host smart-d7e56128-9d46-4855-9da6-df5bb37172e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32970
11085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3297011085
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1884555041
Short name T2045
Test name
Test status
Simulation time 208281134 ps
CPU time 0.87 seconds
Started Jun 30 06:27:02 PM PDT 24
Finished Jun 30 06:27:04 PM PDT 24
Peak memory 206176 kb
Host smart-af0ecd21-877e-4040-a6c7-3d65c038215f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18845
55041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1884555041
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.2044166398
Short name T1417
Test name
Test status
Simulation time 211878989 ps
CPU time 0.9 seconds
Started Jun 30 06:27:09 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 206216 kb
Host smart-e239c9ae-3df0-4272-9392-b2ecb896dea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20441
66398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.2044166398
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.4130489359
Short name T2383
Test name
Test status
Simulation time 190468656 ps
CPU time 0.89 seconds
Started Jun 30 06:26:59 PM PDT 24
Finished Jun 30 06:27:01 PM PDT 24
Peak memory 206172 kb
Host smart-0ddb77ec-189d-4f6c-b578-94ea6d5274f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41304
89359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.4130489359
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2947461428
Short name T1706
Test name
Test status
Simulation time 143792635 ps
CPU time 0.79 seconds
Started Jun 30 06:26:56 PM PDT 24
Finished Jun 30 06:26:58 PM PDT 24
Peak memory 206164 kb
Host smart-f3323a4c-6fe7-42ff-bbfe-97b3e41e12b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29474
61428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2947461428
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.4081678043
Short name T402
Test name
Test status
Simulation time 177701332 ps
CPU time 0.8 seconds
Started Jun 30 06:27:12 PM PDT 24
Finished Jun 30 06:27:16 PM PDT 24
Peak memory 206188 kb
Host smart-c27bf701-7620-47d3-9778-45c436fa73cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40816
78043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.4081678043
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3602181986
Short name T2274
Test name
Test status
Simulation time 153724491 ps
CPU time 0.81 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 206352 kb
Host smart-cab40990-e10e-4855-8072-a1a72eb4657f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36021
81986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3602181986
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3267328341
Short name T1675
Test name
Test status
Simulation time 206813264 ps
CPU time 0.96 seconds
Started Jun 30 06:26:59 PM PDT 24
Finished Jun 30 06:27:00 PM PDT 24
Peak memory 206164 kb
Host smart-6113d542-b3fa-4ad9-bd57-91c1361df490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32673
28341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3267328341
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3523190964
Short name T1694
Test name
Test status
Simulation time 4173742542 ps
CPU time 113.95 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:29:03 PM PDT 24
Peak memory 206476 kb
Host smart-ba990cdc-550f-4c3f-9389-cbbe27ae19a6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3523190964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.3523190964
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1980278047
Short name T349
Test name
Test status
Simulation time 210035112 ps
CPU time 0.85 seconds
Started Jun 30 06:27:05 PM PDT 24
Finished Jun 30 06:27:08 PM PDT 24
Peak memory 206360 kb
Host smart-df68cf18-51d0-4946-9c74-6f0b842540d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19802
78047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1980278047
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1441853232
Short name T2287
Test name
Test status
Simulation time 227285917 ps
CPU time 0.85 seconds
Started Jun 30 06:27:07 PM PDT 24
Finished Jun 30 06:27:10 PM PDT 24
Peak memory 206052 kb
Host smart-aac88cc8-6c5d-4ff1-865c-572e89cef971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14418
53232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1441853232
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.3223473136
Short name T1835
Test name
Test status
Simulation time 6505182700 ps
CPU time 47.22 seconds
Started Jun 30 06:27:06 PM PDT 24
Finished Jun 30 06:27:56 PM PDT 24
Peak memory 206444 kb
Host smart-512cd37f-478c-4292-bf98-a3ff3c92d8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32234
73136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.3223473136
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.441090971
Short name T488
Test name
Test status
Simulation time 44427002 ps
CPU time 0.67 seconds
Started Jun 30 06:21:08 PM PDT 24
Finished Jun 30 06:21:09 PM PDT 24
Peak memory 206212 kb
Host smart-50a2bbc0-2bc1-47b8-9a66-f58eae903add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=441090971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.441090971
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2497634491
Short name T1787
Test name
Test status
Simulation time 3995778296 ps
CPU time 4.43 seconds
Started Jun 30 06:20:55 PM PDT 24
Finished Jun 30 06:21:00 PM PDT 24
Peak memory 206460 kb
Host smart-baf1a0ae-6bc1-4228-af15-7dcdba3f60d9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2497634491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.2497634491
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2011522273
Short name T413
Test name
Test status
Simulation time 13533916835 ps
CPU time 13.85 seconds
Started Jun 30 06:20:55 PM PDT 24
Finished Jun 30 06:21:09 PM PDT 24
Peak memory 206480 kb
Host smart-a61e3d60-5445-4def-9530-62d31652551f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2011522273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2011522273
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3673564809
Short name T506
Test name
Test status
Simulation time 23382431410 ps
CPU time 25.61 seconds
Started Jun 30 06:20:53 PM PDT 24
Finished Jun 30 06:21:19 PM PDT 24
Peak memory 206316 kb
Host smart-d984b25e-cdef-4a8b-917f-8c5137fe005f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3673564809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.3673564809
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.54862225
Short name T2331
Test name
Test status
Simulation time 163339906 ps
CPU time 0.81 seconds
Started Jun 30 06:20:54 PM PDT 24
Finished Jun 30 06:20:56 PM PDT 24
Peak memory 206208 kb
Host smart-8818b6c5-b30b-4988-a77a-727fe0e60661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54862
225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.54862225
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3766786666
Short name T1345
Test name
Test status
Simulation time 152970919 ps
CPU time 0.84 seconds
Started Jun 30 06:20:56 PM PDT 24
Finished Jun 30 06:20:57 PM PDT 24
Peak memory 206168 kb
Host smart-8e87f2a9-88a8-4d97-b9d9-06a7327db7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37667
86666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3766786666
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.1502440494
Short name T1874
Test name
Test status
Simulation time 374488875 ps
CPU time 1.14 seconds
Started Jun 30 06:20:55 PM PDT 24
Finished Jun 30 06:20:57 PM PDT 24
Peak memory 206396 kb
Host smart-78f222e6-0ede-4c08-be60-28b45d1f50ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15024
40494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.1502440494
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1354501463
Short name T154
Test name
Test status
Simulation time 729144672 ps
CPU time 1.98 seconds
Started Jun 30 06:20:57 PM PDT 24
Finished Jun 30 06:20:59 PM PDT 24
Peak memory 206260 kb
Host smart-8e5f7a70-1909-4920-bac7-e61b468991e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13545
01463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1354501463
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.496287156
Short name T1059
Test name
Test status
Simulation time 11022725782 ps
CPU time 19.98 seconds
Started Jun 30 06:20:54 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 206492 kb
Host smart-ba45795e-d350-416b-b0e3-49b2db1f1e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49628
7156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.496287156
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3323009218
Short name T443
Test name
Test status
Simulation time 388910442 ps
CPU time 1.24 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:06 PM PDT 24
Peak memory 206200 kb
Host smart-5e869552-c524-442d-bd36-73d235aaeeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33230
09218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3323009218
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.782962061
Short name T43
Test name
Test status
Simulation time 137093107 ps
CPU time 0.75 seconds
Started Jun 30 06:21:01 PM PDT 24
Finished Jun 30 06:21:02 PM PDT 24
Peak memory 206184 kb
Host smart-49571d4d-effe-46a7-9ba3-661636d917e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78296
2061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.782962061
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2587485758
Short name T2562
Test name
Test status
Simulation time 33270090 ps
CPU time 0.74 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206224 kb
Host smart-629571a4-be9e-45d9-b326-6d3b27d32872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25874
85758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2587485758
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.4091671430
Short name T1257
Test name
Test status
Simulation time 996031153 ps
CPU time 2.32 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:06 PM PDT 24
Peak memory 206372 kb
Host smart-17d2a3c1-490f-406a-95a0-2795744a00de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40916
71430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.4091671430
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3824261446
Short name T204
Test name
Test status
Simulation time 293674830 ps
CPU time 2.47 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:05 PM PDT 24
Peak memory 206336 kb
Host smart-7a174177-dca0-4890-82ff-61cd3cef8734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38242
61446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3824261446
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.233603458
Short name T528
Test name
Test status
Simulation time 260963450 ps
CPU time 0.98 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:05 PM PDT 24
Peak memory 206208 kb
Host smart-96b4b8e9-32f6-49e4-8749-ba53757d8c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23360
3458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.233603458
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1166036416
Short name T1920
Test name
Test status
Simulation time 146960758 ps
CPU time 0.8 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:05 PM PDT 24
Peak memory 206204 kb
Host smart-4acacc71-c84d-43ab-a215-5d1a9f45a917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11660
36416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1166036416
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2179794801
Short name T2430
Test name
Test status
Simulation time 163051164 ps
CPU time 0.82 seconds
Started Jun 30 06:21:00 PM PDT 24
Finished Jun 30 06:21:01 PM PDT 24
Peak memory 206228 kb
Host smart-b43c0495-8a76-428a-8939-9df2fd63d789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21797
94801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2179794801
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.183673925
Short name T1266
Test name
Test status
Simulation time 6627553463 ps
CPU time 62.9 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:22:06 PM PDT 24
Peak memory 206428 kb
Host smart-bb4d8da8-9534-49ad-bfad-bbaa9c3970a6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=183673925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.183673925
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.4060804620
Short name T1967
Test name
Test status
Simulation time 158852650 ps
CPU time 0.78 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:03 PM PDT 24
Peak memory 206184 kb
Host smart-32f0b5f5-7b47-4e18-bff3-a65fbf840894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40608
04620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.4060804620
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2468171806
Short name T1289
Test name
Test status
Simulation time 23288401440 ps
CPU time 24.8 seconds
Started Jun 30 06:21:01 PM PDT 24
Finished Jun 30 06:21:26 PM PDT 24
Peak memory 206312 kb
Host smart-1e98c47e-e178-4558-b5ca-d7dc66f89bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24681
71806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2468171806
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.665774197
Short name T233
Test name
Test status
Simulation time 3310083868 ps
CPU time 4 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 206228 kb
Host smart-4fa1e24f-b9c1-4f0f-8b81-99e135ec3237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66577
4197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.665774197
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1931317349
Short name T1971
Test name
Test status
Simulation time 10690426120 ps
CPU time 79.36 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:22:23 PM PDT 24
Peak memory 206480 kb
Host smart-323498f8-d7cd-4098-b7d7-3bd06f98d34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19313
17349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1931317349
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3072400235
Short name T1051
Test name
Test status
Simulation time 5556234001 ps
CPU time 38.99 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:43 PM PDT 24
Peak memory 206448 kb
Host smart-b9196841-b170-498c-88fd-ba0e88ca4059
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3072400235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3072400235
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1464497929
Short name T1481
Test name
Test status
Simulation time 295315888 ps
CPU time 1.03 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:05 PM PDT 24
Peak memory 206216 kb
Host smart-117bfc8a-c2ed-4c9c-91d7-9e2898cd19a5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1464497929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1464497929
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1941009058
Short name T2404
Test name
Test status
Simulation time 194458970 ps
CPU time 0.96 seconds
Started Jun 30 06:21:04 PM PDT 24
Finished Jun 30 06:21:06 PM PDT 24
Peak memory 206212 kb
Host smart-076ac837-e5a5-4427-8281-84e95612553c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19410
09058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1941009058
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.448800946
Short name T1399
Test name
Test status
Simulation time 5890075000 ps
CPU time 171.99 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:23:56 PM PDT 24
Peak memory 206456 kb
Host smart-874757df-7824-489f-8284-ac9b0103ef29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44880
0946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.448800946
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.3397399284
Short name T2013
Test name
Test status
Simulation time 4777860546 ps
CPU time 146.31 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:23:29 PM PDT 24
Peak memory 206432 kb
Host smart-9a483045-8eef-42b5-bab5-9b625128750f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3397399284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.3397399284
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.4240556349
Short name T674
Test name
Test status
Simulation time 157405716 ps
CPU time 0.83 seconds
Started Jun 30 06:21:05 PM PDT 24
Finished Jun 30 06:21:06 PM PDT 24
Peak memory 206356 kb
Host smart-a1d038a8-3f1f-462a-9b9a-c7dcd4e8dc05
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4240556349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.4240556349
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2421543532
Short name T587
Test name
Test status
Simulation time 144387378 ps
CPU time 0.84 seconds
Started Jun 30 06:21:04 PM PDT 24
Finished Jun 30 06:21:06 PM PDT 24
Peak memory 206212 kb
Host smart-391ea9d1-2bd8-42f4-bd64-165a1472820d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24215
43532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2421543532
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1214196854
Short name T137
Test name
Test status
Simulation time 186648659 ps
CPU time 0.91 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206196 kb
Host smart-31f032fe-f93c-4b08-a0ff-e5de4b90d24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12141
96854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1214196854
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.1919527749
Short name T96
Test name
Test status
Simulation time 182374173 ps
CPU time 0.89 seconds
Started Jun 30 06:21:01 PM PDT 24
Finished Jun 30 06:21:03 PM PDT 24
Peak memory 206180 kb
Host smart-16e00750-909b-4acf-a2ba-91205db452a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19195
27749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1919527749
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2375462707
Short name T2149
Test name
Test status
Simulation time 194512066 ps
CPU time 0.88 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:05 PM PDT 24
Peak memory 206196 kb
Host smart-4ae288b8-5dc7-40c1-95bb-1caa0603e881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23754
62707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2375462707
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1688703256
Short name T2185
Test name
Test status
Simulation time 167265704 ps
CPU time 0.8 seconds
Started Jun 30 06:21:04 PM PDT 24
Finished Jun 30 06:21:06 PM PDT 24
Peak memory 206192 kb
Host smart-e9087131-6123-4f4b-8b07-c317c4add5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16887
03256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1688703256
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2724720463
Short name T30
Test name
Test status
Simulation time 159570214 ps
CPU time 0.77 seconds
Started Jun 30 06:21:01 PM PDT 24
Finished Jun 30 06:21:02 PM PDT 24
Peak memory 206168 kb
Host smart-2e14e733-44f0-4979-aad9-d0c7565bba26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27247
20463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2724720463
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.667137867
Short name T2585
Test name
Test status
Simulation time 191474927 ps
CPU time 0.93 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206208 kb
Host smart-8d71b843-7177-4691-9ee1-090ffa50250a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=667137867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.667137867
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1413036564
Short name T1292
Test name
Test status
Simulation time 149484276 ps
CPU time 0.83 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:03 PM PDT 24
Peak memory 206220 kb
Host smart-3d6a1c03-2d9b-44e3-add3-d8ad70bc81b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14130
36564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1413036564
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2185276607
Short name T746
Test name
Test status
Simulation time 43267302 ps
CPU time 0.66 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:05 PM PDT 24
Peak memory 206208 kb
Host smart-7a0a1bc1-7678-4135-afec-510a01f13256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21852
76607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2185276607
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3078532081
Short name T2073
Test name
Test status
Simulation time 11575840726 ps
CPU time 27.2 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:31 PM PDT 24
Peak memory 206492 kb
Host smart-5ed4ea4b-b3ef-45d3-b421-21b22a7a6e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30785
32081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3078532081
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2383236409
Short name T2361
Test name
Test status
Simulation time 165734780 ps
CPU time 0.86 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:05 PM PDT 24
Peak memory 206160 kb
Host smart-edc56594-bc6b-401c-b079-b6d8fd700f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23832
36409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2383236409
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.403581848
Short name T393
Test name
Test status
Simulation time 283697314 ps
CPU time 0.93 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206192 kb
Host smart-ebea0cea-d8d0-4bc6-abcd-cf5a0d55680c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40358
1848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.403581848
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.3430353448
Short name T2569
Test name
Test status
Simulation time 9335640808 ps
CPU time 46.51 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:49 PM PDT 24
Peak memory 206432 kb
Host smart-f1520b0c-e639-42b7-a970-7728165ecd35
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3430353448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3430353448
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3320055530
Short name T211
Test name
Test status
Simulation time 9344028187 ps
CPU time 233.27 seconds
Started Jun 30 06:21:01 PM PDT 24
Finished Jun 30 06:24:55 PM PDT 24
Peak memory 206508 kb
Host smart-19db2ba1-4ac8-41c6-b780-c7bd60ed6d52
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3320055530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3320055530
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.717355822
Short name T1729
Test name
Test status
Simulation time 16878108861 ps
CPU time 360.75 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:27:11 PM PDT 24
Peak memory 206508 kb
Host smart-ac641485-d8d8-4bf2-b02f-1267d0691934
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=717355822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.717355822
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.60525595
Short name T1918
Test name
Test status
Simulation time 232015992 ps
CPU time 0.97 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206192 kb
Host smart-5ebc8b49-2f7b-4636-88f8-546dd03b6a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60525
595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.60525595
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.4091676316
Short name T1279
Test name
Test status
Simulation time 170740292 ps
CPU time 0.83 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:11 PM PDT 24
Peak memory 206160 kb
Host smart-6e32ceac-eae3-4b7b-8a39-cb3a9d0ccc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40916
76316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.4091676316
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2662414665
Short name T722
Test name
Test status
Simulation time 158634289 ps
CPU time 0.78 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:05 PM PDT 24
Peak memory 206192 kb
Host smart-698fedf9-a9dd-42b9-be99-fdcc23413821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
14665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2662414665
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.233855484
Short name T764
Test name
Test status
Simulation time 183967643 ps
CPU time 0.82 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:03 PM PDT 24
Peak memory 206192 kb
Host smart-b32c4a6c-9140-4244-9061-5e3acbd21a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23385
5484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.233855484
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3639640693
Short name T1198
Test name
Test status
Simulation time 176264686 ps
CPU time 0.82 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:05 PM PDT 24
Peak memory 206188 kb
Host smart-4ac7a091-ee2a-4a7e-841d-9e6ed6521244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36396
40693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3639640693
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2233591782
Short name T730
Test name
Test status
Simulation time 234278215 ps
CPU time 0.96 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:11 PM PDT 24
Peak memory 206188 kb
Host smart-90299bab-8262-4a94-9597-8cf87a5536da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22335
91782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2233591782
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.2934222806
Short name T144
Test name
Test status
Simulation time 4816458890 ps
CPU time 45.48 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:48 PM PDT 24
Peak memory 206412 kb
Host smart-8893fde6-3813-467c-a53e-68d7c147f7a1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2934222806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2934222806
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3461128059
Short name T2621
Test name
Test status
Simulation time 233462730 ps
CPU time 0.93 seconds
Started Jun 30 06:21:03 PM PDT 24
Finished Jun 30 06:21:05 PM PDT 24
Peak memory 206160 kb
Host smart-3d3ff52b-be20-4d17-9744-60d909cba979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34611
28059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3461128059
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.4195131821
Short name T1974
Test name
Test status
Simulation time 161460225 ps
CPU time 0.82 seconds
Started Jun 30 06:21:02 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 206180 kb
Host smart-f9ca6047-15bb-4b6f-8961-51bd99053c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41951
31821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.4195131821
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.4042550408
Short name T2057
Test name
Test status
Simulation time 6997802290 ps
CPU time 49.93 seconds
Started Jun 30 06:21:00 PM PDT 24
Finished Jun 30 06:21:50 PM PDT 24
Peak memory 206412 kb
Host smart-ac852400-fda8-46e8-ab2b-9adddc31c50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40425
50408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.4042550408
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.3265305447
Short name T720
Test name
Test status
Simulation time 69590775 ps
CPU time 0.74 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:19 PM PDT 24
Peak memory 206196 kb
Host smart-c17a2582-893c-40bc-b3fb-572c174d4668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3265305447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.3265305447
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1056423372
Short name T515
Test name
Test status
Simulation time 4408005559 ps
CPU time 5.23 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:21:18 PM PDT 24
Peak memory 206316 kb
Host smart-2cc76952-b190-489b-89db-1cf529d2f466
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1056423372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1056423372
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.1198627726
Short name T570
Test name
Test status
Simulation time 13415790175 ps
CPU time 12.35 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:21:24 PM PDT 24
Peak memory 206444 kb
Host smart-ea466dd8-e392-4b49-9289-331cd53b8f00
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1198627726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.1198627726
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3473462992
Short name T2337
Test name
Test status
Simulation time 23377863849 ps
CPU time 26.06 seconds
Started Jun 30 06:21:11 PM PDT 24
Finished Jun 30 06:21:39 PM PDT 24
Peak memory 206340 kb
Host smart-e57aab01-241c-4add-b75d-e84efe15be4f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3473462992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3473462992
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1860007736
Short name T1335
Test name
Test status
Simulation time 172483610 ps
CPU time 0.79 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:21:13 PM PDT 24
Peak memory 206164 kb
Host smart-866eb568-4e34-43a3-8b07-46fb2f07e6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18600
07736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1860007736
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3620556700
Short name T493
Test name
Test status
Simulation time 149572942 ps
CPU time 0.79 seconds
Started Jun 30 06:21:08 PM PDT 24
Finished Jun 30 06:21:09 PM PDT 24
Peak memory 206148 kb
Host smart-a24fd5b9-b798-47f6-a476-084dd1c38a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36205
56700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3620556700
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.405198128
Short name T882
Test name
Test status
Simulation time 382398618 ps
CPU time 1.35 seconds
Started Jun 30 06:21:11 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 206148 kb
Host smart-69ce6b05-38ce-4cf5-bc1a-3ea0d0b9388d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40519
8128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.405198128
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_device_address.889305200
Short name T92
Test name
Test status
Simulation time 6149933612 ps
CPU time 12.89 seconds
Started Jun 30 06:21:08 PM PDT 24
Finished Jun 30 06:21:22 PM PDT 24
Peak memory 206388 kb
Host smart-c89dc8a7-cddd-4571-9c30-0ed6e68695a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88930
5200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.889305200
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.2066415792
Short name T1296
Test name
Test status
Simulation time 398588184 ps
CPU time 1.31 seconds
Started Jun 30 06:21:07 PM PDT 24
Finished Jun 30 06:21:09 PM PDT 24
Peak memory 206188 kb
Host smart-7fd91b86-4400-41ab-84e0-ca0c0c8c6576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20664
15792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.2066415792
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2151036401
Short name T2153
Test name
Test status
Simulation time 143850352 ps
CPU time 0.79 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:11 PM PDT 24
Peak memory 206188 kb
Host smart-6368d3dc-cea0-4f51-aeda-3a31099649ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21510
36401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2151036401
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.856486168
Short name T347
Test name
Test status
Simulation time 42844933 ps
CPU time 0.64 seconds
Started Jun 30 06:21:11 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 206196 kb
Host smart-b23b86fb-79b3-483b-9273-39a63a1d8f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85648
6168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.856486168
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3480213443
Short name T1142
Test name
Test status
Simulation time 978339658 ps
CPU time 2.29 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:21 PM PDT 24
Peak memory 206328 kb
Host smart-32e52e55-135b-4fb8-93a8-806677e09162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34802
13443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3480213443
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2978242300
Short name T457
Test name
Test status
Simulation time 377870998 ps
CPU time 2.09 seconds
Started Jun 30 06:21:11 PM PDT 24
Finished Jun 30 06:21:15 PM PDT 24
Peak memory 206288 kb
Host smart-2c05a327-ce7f-4902-a352-209d3bfc54be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29782
42300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2978242300
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2345144643
Short name T1042
Test name
Test status
Simulation time 264174464 ps
CPU time 1.06 seconds
Started Jun 30 06:21:12 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 206192 kb
Host smart-0888ac87-da2d-4c8e-8368-5364c6c1715e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23451
44643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2345144643
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.942404204
Short name T921
Test name
Test status
Simulation time 143791479 ps
CPU time 0.76 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:21:12 PM PDT 24
Peak memory 206184 kb
Host smart-d3ef61ea-2add-4da3-978b-2b41069c7dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94240
4204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.942404204
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.190271530
Short name T1482
Test name
Test status
Simulation time 185717131 ps
CPU time 0.84 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:20 PM PDT 24
Peak memory 206208 kb
Host smart-ba21b311-02c0-4c5a-b562-56f03f9f1a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19027
1530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.190271530
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.3817928737
Short name T2264
Test name
Test status
Simulation time 8551996060 ps
CPU time 62.71 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:22:14 PM PDT 24
Peak memory 206396 kb
Host smart-091bf898-223a-495d-ab07-5b82e5dc2706
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3817928737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3817928737
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2682922081
Short name T685
Test name
Test status
Simulation time 258069142 ps
CPU time 0.91 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:11 PM PDT 24
Peak memory 206188 kb
Host smart-d8a46a70-4a0b-47a9-9656-6a87aa76168e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26829
22081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2682922081
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.3345979665
Short name T1368
Test name
Test status
Simulation time 23340411778 ps
CPU time 23.85 seconds
Started Jun 30 06:21:13 PM PDT 24
Finished Jun 30 06:21:38 PM PDT 24
Peak memory 206300 kb
Host smart-f38736bf-c40e-4ff1-bfdf-0d8cc98fec2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33459
79665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.3345979665
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1593696040
Short name T768
Test name
Test status
Simulation time 3320430354 ps
CPU time 3.77 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:22 PM PDT 24
Peak memory 206436 kb
Host smart-1fce31ff-b71c-4c1f-8e9d-71a0dd7a5a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936
96040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1593696040
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2099396012
Short name T808
Test name
Test status
Simulation time 5527353995 ps
CPU time 51.84 seconds
Started Jun 30 06:21:13 PM PDT 24
Finished Jun 30 06:22:06 PM PDT 24
Peak memory 206468 kb
Host smart-44769d18-8e19-447d-80a6-b3f04e4eeb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20993
96012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2099396012
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.4058789569
Short name T1745
Test name
Test status
Simulation time 8101388029 ps
CPU time 61.14 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:22:12 PM PDT 24
Peak memory 206456 kb
Host smart-70fc3f31-752c-480d-bc01-a6f77f1b5cb9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4058789569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.4058789569
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2151499015
Short name T2412
Test name
Test status
Simulation time 238665266 ps
CPU time 0.96 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:12 PM PDT 24
Peak memory 206212 kb
Host smart-6f659a28-5496-4a24-b17e-eac416bf4364
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2151499015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2151499015
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.407846033
Short name T1533
Test name
Test status
Simulation time 200744824 ps
CPU time 0.94 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:21:12 PM PDT 24
Peak memory 206208 kb
Host smart-1c5430cd-b702-4826-a337-adaa2bf6a0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40784
6033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.407846033
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3995043333
Short name T1466
Test name
Test status
Simulation time 4438134791 ps
CPU time 41.76 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:21:53 PM PDT 24
Peak memory 206500 kb
Host smart-3af5f157-c2d3-452a-8a39-9307e3897afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39950
43333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3995043333
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3242107844
Short name T150
Test name
Test status
Simulation time 3614365801 ps
CPU time 99.99 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 206380 kb
Host smart-f88bca78-ba53-4e61-b88d-feac125cfecf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3242107844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3242107844
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.1910540800
Short name T1742
Test name
Test status
Simulation time 177502292 ps
CPU time 0.82 seconds
Started Jun 30 06:21:12 PM PDT 24
Finished Jun 30 06:21:15 PM PDT 24
Peak memory 206204 kb
Host smart-ec431d52-31d6-4720-b5f7-831a0b17400c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1910540800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.1910540800
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1577567199
Short name T780
Test name
Test status
Simulation time 150318326 ps
CPU time 0.79 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:11 PM PDT 24
Peak memory 206168 kb
Host smart-033a5959-257e-4ab4-a1d6-b2497ef5cafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15775
67199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1577567199
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.440154500
Short name T114
Test name
Test status
Simulation time 206855775 ps
CPU time 0.9 seconds
Started Jun 30 06:21:08 PM PDT 24
Finished Jun 30 06:21:09 PM PDT 24
Peak memory 206204 kb
Host smart-5d9fe103-437a-495e-85a1-d7467a256200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44015
4500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.440154500
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.701045777
Short name T2003
Test name
Test status
Simulation time 153579700 ps
CPU time 0.79 seconds
Started Jun 30 06:21:08 PM PDT 24
Finished Jun 30 06:21:10 PM PDT 24
Peak memory 206204 kb
Host smart-7bb3f12b-9b86-4a1a-b3d7-0eddf68aced4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70104
5777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.701045777
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3944886845
Short name T979
Test name
Test status
Simulation time 160191714 ps
CPU time 0.79 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:21:12 PM PDT 24
Peak memory 206192 kb
Host smart-bd1d6f5c-6fa5-4e9f-9825-3a1b79378bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39448
86845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3944886845
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3833964759
Short name T327
Test name
Test status
Simulation time 214778438 ps
CPU time 0.83 seconds
Started Jun 30 06:21:11 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 206168 kb
Host smart-a9a22813-db79-4546-9de1-4877d8e36e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38339
64759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3833964759
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2004974012
Short name T567
Test name
Test status
Simulation time 159241647 ps
CPU time 0.84 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:21:13 PM PDT 24
Peak memory 206196 kb
Host smart-ba6ee73f-5714-41ee-ad0f-f0c8952fea18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20049
74012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2004974012
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.2344276478
Short name T1607
Test name
Test status
Simulation time 242833136 ps
CPU time 1.03 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:19 PM PDT 24
Peak memory 206212 kb
Host smart-5bb7d072-e197-4c83-82b1-a9a8968526c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2344276478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.2344276478
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.4291046306
Short name T924
Test name
Test status
Simulation time 146649846 ps
CPU time 0.8 seconds
Started Jun 30 06:21:08 PM PDT 24
Finished Jun 30 06:21:10 PM PDT 24
Peak memory 206208 kb
Host smart-99ebb447-be55-42c3-b6b0-36d579a08d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42910
46306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.4291046306
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.132822989
Short name T1934
Test name
Test status
Simulation time 46545471 ps
CPU time 0.72 seconds
Started Jun 30 06:21:12 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 206184 kb
Host smart-30a31594-5e33-48bb-853c-cf119f577494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13282
2989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.132822989
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1205749526
Short name T1522
Test name
Test status
Simulation time 15617127798 ps
CPU time 33.43 seconds
Started Jun 30 06:21:11 PM PDT 24
Finished Jun 30 06:21:46 PM PDT 24
Peak memory 206436 kb
Host smart-81e95d8c-201f-4731-9aa2-1f560a6cdd3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12057
49526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1205749526
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3011361349
Short name T2184
Test name
Test status
Simulation time 199583444 ps
CPU time 0.9 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:11 PM PDT 24
Peak memory 206188 kb
Host smart-fc50b7be-f008-4dc2-b24f-81adf8756291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30113
61349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3011361349
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2109563994
Short name T944
Test name
Test status
Simulation time 235367000 ps
CPU time 0.92 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:21:13 PM PDT 24
Peak memory 206156 kb
Host smart-b1337d52-5f90-4917-9517-cec986146d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21095
63994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2109563994
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3689808695
Short name T2223
Test name
Test status
Simulation time 7844110595 ps
CPU time 64.38 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:22:17 PM PDT 24
Peak memory 206432 kb
Host smart-5c5b179c-0385-4dc2-8d10-fdcc3bdcef81
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3689808695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3689808695
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3086505591
Short name T184
Test name
Test status
Simulation time 5609594524 ps
CPU time 131.16 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:23:23 PM PDT 24
Peak memory 206452 kb
Host smart-dba63575-ceea-4c9d-8d4b-20a352b533f5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3086505591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3086505591
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1538585649
Short name T558
Test name
Test status
Simulation time 17722253957 ps
CPU time 95.81 seconds
Started Jun 30 06:21:12 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 206424 kb
Host smart-850449ee-ee2b-4cde-b552-39a91bf77fda
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1538585649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1538585649
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.129288186
Short name T796
Test name
Test status
Simulation time 187288409 ps
CPU time 0.84 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:11 PM PDT 24
Peak memory 206160 kb
Host smart-73efb837-3043-4037-a9fb-b651a86e1722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12928
8186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.129288186
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.734830777
Short name T786
Test name
Test status
Simulation time 146726485 ps
CPU time 0.8 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:20 PM PDT 24
Peak memory 206156 kb
Host smart-c73ca390-4b5f-4cb7-b5cb-8aaee0530893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73483
0777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.734830777
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2767160122
Short name T2273
Test name
Test status
Simulation time 233259872 ps
CPU time 0.86 seconds
Started Jun 30 06:21:11 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 206180 kb
Host smart-7ed1a817-8e05-46a1-8fe9-00e75a29fb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27671
60122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2767160122
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.963030012
Short name T2289
Test name
Test status
Simulation time 148135965 ps
CPU time 0.8 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:10 PM PDT 24
Peak memory 206192 kb
Host smart-a2ac8606-5a23-45c4-837c-ded8c6448533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96303
0012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.963030012
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2451475577
Short name T1260
Test name
Test status
Simulation time 231182196 ps
CPU time 0.86 seconds
Started Jun 30 06:21:11 PM PDT 24
Finished Jun 30 06:21:14 PM PDT 24
Peak memory 206180 kb
Host smart-d391663b-5728-450f-a9f2-4795e27745ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24514
75577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2451475577
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2942448648
Short name T417
Test name
Test status
Simulation time 215401588 ps
CPU time 0.97 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:11 PM PDT 24
Peak memory 206188 kb
Host smart-fdef6f2f-0314-4fb0-b417-ffb6147cfe7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29424
48648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2942448648
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2119386676
Short name T1590
Test name
Test status
Simulation time 6076648733 ps
CPU time 56.51 seconds
Started Jun 30 06:21:11 PM PDT 24
Finished Jun 30 06:22:09 PM PDT 24
Peak memory 206344 kb
Host smart-e17368d7-e22c-43ff-b534-26c7c3d8df25
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2119386676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2119386676
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2336430738
Short name T1014
Test name
Test status
Simulation time 165535387 ps
CPU time 0.79 seconds
Started Jun 30 06:21:08 PM PDT 24
Finished Jun 30 06:21:10 PM PDT 24
Peak memory 206188 kb
Host smart-3d763bc2-8c87-4e41-aaa9-4c9966b8c2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23364
30738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2336430738
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3983607453
Short name T2602
Test name
Test status
Simulation time 166493574 ps
CPU time 0.79 seconds
Started Jun 30 06:21:09 PM PDT 24
Finished Jun 30 06:21:11 PM PDT 24
Peak memory 206188 kb
Host smart-a523d361-8f7f-4ff1-9598-11fbe2026168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39836
07453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3983607453
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.854746006
Short name T2016
Test name
Test status
Simulation time 5014345043 ps
CPU time 40.27 seconds
Started Jun 30 06:21:10 PM PDT 24
Finished Jun 30 06:21:53 PM PDT 24
Peak memory 206376 kb
Host smart-40ce3bdd-dbed-48ef-82ee-4c33c632e84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85474
6006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.854746006
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2138960578
Short name T1458
Test name
Test status
Simulation time 60358544 ps
CPU time 0.75 seconds
Started Jun 30 06:21:23 PM PDT 24
Finished Jun 30 06:21:25 PM PDT 24
Peak memory 206184 kb
Host smart-461e7c7f-df88-4a70-89ff-0d5b93300161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2138960578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2138960578
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2584189155
Short name T1683
Test name
Test status
Simulation time 3490319548 ps
CPU time 4.34 seconds
Started Jun 30 06:21:19 PM PDT 24
Finished Jun 30 06:21:24 PM PDT 24
Peak memory 206272 kb
Host smart-e937a5ab-6b8f-465d-ad55-34484a89cd22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2584189155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.2584189155
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2058610606
Short name T2432
Test name
Test status
Simulation time 13403214802 ps
CPU time 12.16 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:30 PM PDT 24
Peak memory 206448 kb
Host smart-90167ddc-c7c9-4731-96c5-dcbf94c4820f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2058610606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2058610606
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3045478896
Short name T680
Test name
Test status
Simulation time 23422954882 ps
CPU time 22.62 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:41 PM PDT 24
Peak memory 206440 kb
Host smart-c251fc5a-29d1-43ff-8fa9-b768a3bc3411
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3045478896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.3045478896
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2166805458
Short name T2047
Test name
Test status
Simulation time 158238314 ps
CPU time 0.8 seconds
Started Jun 30 06:21:21 PM PDT 24
Finished Jun 30 06:21:22 PM PDT 24
Peak memory 205788 kb
Host smart-dd59ee04-b3e5-4800-b533-337aa47284fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21668
05458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2166805458
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2921453573
Short name T35
Test name
Test status
Simulation time 168945906 ps
CPU time 0.84 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:21:18 PM PDT 24
Peak memory 206192 kb
Host smart-9424c894-ad8d-4e40-9afe-d1d265ed3845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29214
53573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2921453573
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3171618297
Short name T1738
Test name
Test status
Simulation time 326387337 ps
CPU time 1.12 seconds
Started Jun 30 06:21:14 PM PDT 24
Finished Jun 30 06:21:16 PM PDT 24
Peak memory 206164 kb
Host smart-f56d4ed5-d466-4b38-9597-0127723e0e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31716
18297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3171618297
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2100370704
Short name T1837
Test name
Test status
Simulation time 1029330000 ps
CPU time 2.53 seconds
Started Jun 30 06:21:14 PM PDT 24
Finished Jun 30 06:21:17 PM PDT 24
Peak memory 206336 kb
Host smart-1802b4ce-4833-486e-94f6-5876a0eacff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21003
70704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2100370704
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2867104010
Short name T1926
Test name
Test status
Simulation time 22942571314 ps
CPU time 50.17 seconds
Started Jun 30 06:21:14 PM PDT 24
Finished Jun 30 06:22:06 PM PDT 24
Peak memory 206400 kb
Host smart-ca99c84b-e19e-4b8a-9cf2-cac83a80241d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28671
04010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2867104010
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.2107012206
Short name T2272
Test name
Test status
Simulation time 311956103 ps
CPU time 1.29 seconds
Started Jun 30 06:21:15 PM PDT 24
Finished Jun 30 06:21:17 PM PDT 24
Peak memory 206220 kb
Host smart-6ff85b03-32a5-4c2e-ab1c-2d9e6071214f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21070
12206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.2107012206
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3988701047
Short name T1767
Test name
Test status
Simulation time 137699256 ps
CPU time 0.75 seconds
Started Jun 30 06:21:15 PM PDT 24
Finished Jun 30 06:21:17 PM PDT 24
Peak memory 206168 kb
Host smart-fae00459-d69a-4a4d-b460-b9cb7a232cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39887
01047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3988701047
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.1975101502
Short name T2525
Test name
Test status
Simulation time 44174766 ps
CPU time 0.67 seconds
Started Jun 30 06:21:15 PM PDT 24
Finished Jun 30 06:21:16 PM PDT 24
Peak memory 206184 kb
Host smart-4e46f952-febe-41b6-b967-925cc07dc530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19751
01502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1975101502
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.521192014
Short name T836
Test name
Test status
Simulation time 1019110231 ps
CPU time 2.19 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:21:19 PM PDT 24
Peak memory 206288 kb
Host smart-b0c6dc6d-774d-4207-8821-4406fbfd9f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52119
2014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.521192014
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2433699808
Short name T1217
Test name
Test status
Simulation time 226762437 ps
CPU time 1.56 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:21:19 PM PDT 24
Peak memory 206284 kb
Host smart-510c84a9-2a37-44bb-b0dd-19620fe07ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24336
99808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2433699808
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.451870983
Short name T1603
Test name
Test status
Simulation time 235946578 ps
CPU time 0.97 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:21:18 PM PDT 24
Peak memory 206160 kb
Host smart-5713729a-2785-4bca-b539-9e670924db02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45187
0983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.451870983
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.898278352
Short name T1012
Test name
Test status
Simulation time 144528544 ps
CPU time 0.8 seconds
Started Jun 30 06:21:20 PM PDT 24
Finished Jun 30 06:21:21 PM PDT 24
Peak memory 206200 kb
Host smart-40b99f4e-71ee-420a-b157-757b83691b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89827
8352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.898278352
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3760669224
Short name T1646
Test name
Test status
Simulation time 167491769 ps
CPU time 0.83 seconds
Started Jun 30 06:21:15 PM PDT 24
Finished Jun 30 06:21:17 PM PDT 24
Peak memory 206208 kb
Host smart-14c21b3c-a071-479d-9003-8168aff8a96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37606
69224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3760669224
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3446186407
Short name T860
Test name
Test status
Simulation time 229326971 ps
CPU time 1.01 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:19 PM PDT 24
Peak memory 206172 kb
Host smart-1b88324e-526b-4d3d-9aec-ffd00f588fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34461
86407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3446186407
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2914844486
Short name T2033
Test name
Test status
Simulation time 23370855633 ps
CPU time 29.46 seconds
Started Jun 30 06:21:14 PM PDT 24
Finished Jun 30 06:21:44 PM PDT 24
Peak memory 206284 kb
Host smart-ac3e4c8b-2170-4f61-bb65-cfef4f52b241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29148
44486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2914844486
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2516755968
Short name T654
Test name
Test status
Simulation time 3289632298 ps
CPU time 3.83 seconds
Started Jun 30 06:21:14 PM PDT 24
Finished Jun 30 06:21:19 PM PDT 24
Peak memory 206260 kb
Host smart-491b85cf-2dba-4983-af6e-e3f0c2134ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25167
55968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2516755968
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.221460290
Short name T966
Test name
Test status
Simulation time 9696249355 ps
CPU time 93.09 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:22:50 PM PDT 24
Peak memory 206472 kb
Host smart-a7fe7348-7206-4256-9ddb-d17e0ff592c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22146
0290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.221460290
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3090958374
Short name T2299
Test name
Test status
Simulation time 3415155476 ps
CPU time 29.82 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:49 PM PDT 24
Peak memory 206376 kb
Host smart-e335361b-9248-45ff-a4c4-875f7f469ecb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3090958374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3090958374
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2808155704
Short name T2332
Test name
Test status
Simulation time 266648708 ps
CPU time 0.85 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:20 PM PDT 24
Peak memory 206200 kb
Host smart-74556091-059d-4a66-99ca-c7af84a88794
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2808155704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2808155704
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1589677776
Short name T344
Test name
Test status
Simulation time 197287721 ps
CPU time 0.87 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:21:18 PM PDT 24
Peak memory 206208 kb
Host smart-bc0b3001-e090-4c41-b8c5-2198272a55e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15896
77776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1589677776
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1868198736
Short name T2036
Test name
Test status
Simulation time 3383406282 ps
CPU time 32.4 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:51 PM PDT 24
Peak memory 206440 kb
Host smart-a9f767fa-fec2-473d-baec-a36764b63a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18681
98736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1868198736
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1833645800
Short name T489
Test name
Test status
Simulation time 5526690149 ps
CPU time 151.46 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:23:49 PM PDT 24
Peak memory 206448 kb
Host smart-644b7d6c-0d21-4da4-9e1a-1856cc331c88
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1833645800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1833645800
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.4213816776
Short name T2375
Test name
Test status
Simulation time 163275399 ps
CPU time 0.81 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:21:18 PM PDT 24
Peak memory 206236 kb
Host smart-d53c85b9-5556-45a6-ba13-bf3d06742fe6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4213816776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.4213816776
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1014012424
Short name T913
Test name
Test status
Simulation time 183814721 ps
CPU time 0.81 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:21:18 PM PDT 24
Peak memory 206176 kb
Host smart-c00fa7ea-cef2-4d32-8cf5-4d9a784be0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10140
12424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1014012424
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.107907237
Short name T2064
Test name
Test status
Simulation time 185107613 ps
CPU time 0.9 seconds
Started Jun 30 06:21:14 PM PDT 24
Finished Jun 30 06:21:16 PM PDT 24
Peak memory 206200 kb
Host smart-b24ed116-1e3e-44c3-8d1e-30b4d5779c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10790
7237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.107907237
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2136456933
Short name T1932
Test name
Test status
Simulation time 150274065 ps
CPU time 0.81 seconds
Started Jun 30 06:21:19 PM PDT 24
Finished Jun 30 06:21:21 PM PDT 24
Peak memory 206188 kb
Host smart-5c0b4054-4af3-411d-98bc-5b8e39c427e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21364
56933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2136456933
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3548765397
Short name T1559
Test name
Test status
Simulation time 163358249 ps
CPU time 0.87 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:19 PM PDT 24
Peak memory 206192 kb
Host smart-a462de1e-538b-40f4-a117-86c8936d8469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35487
65397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3548765397
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2537209410
Short name T1378
Test name
Test status
Simulation time 174858199 ps
CPU time 0.83 seconds
Started Jun 30 06:21:15 PM PDT 24
Finished Jun 30 06:21:16 PM PDT 24
Peak memory 206164 kb
Host smart-c923e8a0-5dc9-4af9-a1f2-28c45e512dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
09410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2537209410
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.906029855
Short name T186
Test name
Test status
Simulation time 256118889 ps
CPU time 0.84 seconds
Started Jun 30 06:21:20 PM PDT 24
Finished Jun 30 06:21:22 PM PDT 24
Peak memory 206196 kb
Host smart-54276571-4d2a-4f24-a0f5-9dda77577400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90602
9855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.906029855
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.3194155192
Short name T2358
Test name
Test status
Simulation time 206536552 ps
CPU time 0.92 seconds
Started Jun 30 06:21:14 PM PDT 24
Finished Jun 30 06:21:15 PM PDT 24
Peak memory 206196 kb
Host smart-4633f6bc-279f-4a75-aa41-999a9edf171a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3194155192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.3194155192
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.4280630156
Short name T1235
Test name
Test status
Simulation time 157892796 ps
CPU time 0.77 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:19 PM PDT 24
Peak memory 206240 kb
Host smart-1dd68509-9931-4356-8ed9-3f3987bbd061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42806
30156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.4280630156
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1930845049
Short name T1588
Test name
Test status
Simulation time 50349088 ps
CPU time 0.66 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:21:18 PM PDT 24
Peak memory 206208 kb
Host smart-ba056481-d2c6-4845-86cf-6cb2649db993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19308
45049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1930845049
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1711809218
Short name T1744
Test name
Test status
Simulation time 152055989 ps
CPU time 0.84 seconds
Started Jun 30 06:21:21 PM PDT 24
Finished Jun 30 06:21:22 PM PDT 24
Peak memory 206168 kb
Host smart-b98793f4-76c7-4619-9df1-67859018f40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17118
09218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1711809218
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1613551359
Short name T433
Test name
Test status
Simulation time 225616837 ps
CPU time 0.82 seconds
Started Jun 30 06:21:19 PM PDT 24
Finished Jun 30 06:21:21 PM PDT 24
Peak memory 206176 kb
Host smart-d35e263c-f04d-42aa-8d6a-9a60402ba29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16135
51359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1613551359
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3603912994
Short name T155
Test name
Test status
Simulation time 7222265150 ps
CPU time 64.72 seconds
Started Jun 30 06:21:19 PM PDT 24
Finished Jun 30 06:22:25 PM PDT 24
Peak memory 206464 kb
Host smart-d604e4b7-b192-4844-ac95-6aeea69ad796
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3603912994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3603912994
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2595323348
Short name T1136
Test name
Test status
Simulation time 17031893958 ps
CPU time 119.96 seconds
Started Jun 30 06:21:18 PM PDT 24
Finished Jun 30 06:23:19 PM PDT 24
Peak memory 206500 kb
Host smart-e3d1b50f-13d7-4099-b9e0-7b3c29162747
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2595323348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2595323348
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.526058644
Short name T2359
Test name
Test status
Simulation time 16703602859 ps
CPU time 123.11 seconds
Started Jun 30 06:21:21 PM PDT 24
Finished Jun 30 06:23:25 PM PDT 24
Peak memory 206588 kb
Host smart-90328d0a-76cd-4fed-8f17-6eedf28e5467
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=526058644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.526058644
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.2169782475
Short name T1718
Test name
Test status
Simulation time 246418183 ps
CPU time 0.91 seconds
Started Jun 30 06:21:15 PM PDT 24
Finished Jun 30 06:21:16 PM PDT 24
Peak memory 206232 kb
Host smart-979a1c43-b092-4b9e-85f8-58518da45f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21697
82475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.2169782475
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.974853346
Short name T2104
Test name
Test status
Simulation time 178797955 ps
CPU time 0.9 seconds
Started Jun 30 06:21:21 PM PDT 24
Finished Jun 30 06:21:22 PM PDT 24
Peak memory 205656 kb
Host smart-55897515-2995-4ae2-bf66-14638747e5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97485
3346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.974853346
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3441815368
Short name T2007
Test name
Test status
Simulation time 141991880 ps
CPU time 0.77 seconds
Started Jun 30 06:21:17 PM PDT 24
Finished Jun 30 06:21:20 PM PDT 24
Peak memory 206184 kb
Host smart-2bd45d3d-70d5-4fdf-aba7-fafe05095efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34418
15368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3441815368
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1255359820
Short name T1655
Test name
Test status
Simulation time 180991826 ps
CPU time 0.84 seconds
Started Jun 30 06:21:23 PM PDT 24
Finished Jun 30 06:21:24 PM PDT 24
Peak memory 206180 kb
Host smart-e7d3d50a-4c89-4923-9057-087a7c4599e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553
59820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1255359820
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3159806073
Short name T1836
Test name
Test status
Simulation time 156243155 ps
CPU time 0.8 seconds
Started Jun 30 06:21:23 PM PDT 24
Finished Jun 30 06:21:24 PM PDT 24
Peak memory 206184 kb
Host smart-5a940152-a233-4530-bbd7-c0a498a1d949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31598
06073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3159806073
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1925292992
Short name T531
Test name
Test status
Simulation time 206878307 ps
CPU time 0.91 seconds
Started Jun 30 06:21:18 PM PDT 24
Finished Jun 30 06:21:21 PM PDT 24
Peak memory 206212 kb
Host smart-42e8f8e5-4302-4087-bebf-54a8b452e043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19252
92992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1925292992
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.1960078498
Short name T1608
Test name
Test status
Simulation time 4801470957 ps
CPU time 134.34 seconds
Started Jun 30 06:21:18 PM PDT 24
Finished Jun 30 06:23:34 PM PDT 24
Peak memory 206476 kb
Host smart-d5476fd4-418d-4b14-883f-3601c512aa35
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1960078498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.1960078498
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3622247493
Short name T790
Test name
Test status
Simulation time 201012591 ps
CPU time 0.83 seconds
Started Jun 30 06:21:16 PM PDT 24
Finished Jun 30 06:21:18 PM PDT 24
Peak memory 206184 kb
Host smart-310d1bd4-5798-4658-a185-7432e1ff180d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36222
47493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3622247493
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2275978018
Short name T1946
Test name
Test status
Simulation time 228169999 ps
CPU time 0.88 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:21:30 PM PDT 24
Peak memory 206144 kb
Host smart-7727459a-f4e0-4dda-9893-16ef721cd2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22759
78018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2275978018
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.477425373
Short name T869
Test name
Test status
Simulation time 7406488930 ps
CPU time 197.48 seconds
Started Jun 30 06:21:26 PM PDT 24
Finished Jun 30 06:24:44 PM PDT 24
Peak memory 206400 kb
Host smart-17765781-66e3-4467-a2ce-5821ec3e0892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47742
5373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.477425373
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1765772684
Short name T1997
Test name
Test status
Simulation time 64066598 ps
CPU time 0.72 seconds
Started Jun 30 06:21:30 PM PDT 24
Finished Jun 30 06:21:32 PM PDT 24
Peak memory 206192 kb
Host smart-39272e66-1986-4fa8-8298-a44934593af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1765772684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1765772684
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3674110169
Short name T1286
Test name
Test status
Simulation time 3834244069 ps
CPU time 4.55 seconds
Started Jun 30 06:21:25 PM PDT 24
Finished Jun 30 06:21:31 PM PDT 24
Peak memory 206420 kb
Host smart-d5fe4624-2a1b-4b86-bf4b-416e5e878446
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3674110169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3674110169
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1336249992
Short name T2450
Test name
Test status
Simulation time 13370878276 ps
CPU time 13.52 seconds
Started Jun 30 06:21:24 PM PDT 24
Finished Jun 30 06:21:39 PM PDT 24
Peak memory 206304 kb
Host smart-16620206-ab06-4652-afc9-e8cac654761a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1336249992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1336249992
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2547726435
Short name T2455
Test name
Test status
Simulation time 23403592296 ps
CPU time 23.42 seconds
Started Jun 30 06:21:25 PM PDT 24
Finished Jun 30 06:21:49 PM PDT 24
Peak memory 206288 kb
Host smart-1519294f-06bb-40ef-82d5-21a7ddbc4fa5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2547726435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2547726435
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.837834128
Short name T2259
Test name
Test status
Simulation time 144863825 ps
CPU time 0.79 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:21:29 PM PDT 24
Peak memory 206220 kb
Host smart-e96432ea-0c05-46d0-9dac-f4236774306a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83783
4128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.837834128
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3094244947
Short name T353
Test name
Test status
Simulation time 151413715 ps
CPU time 0.78 seconds
Started Jun 30 06:21:23 PM PDT 24
Finished Jun 30 06:21:24 PM PDT 24
Peak memory 206188 kb
Host smart-8c77f640-d14e-4d4a-b38b-589806ed329e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30942
44947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3094244947
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.936174129
Short name T672
Test name
Test status
Simulation time 387758557 ps
CPU time 1.26 seconds
Started Jun 30 06:21:25 PM PDT 24
Finished Jun 30 06:21:26 PM PDT 24
Peak memory 206176 kb
Host smart-7520b228-ec37-475a-a77e-08b511d0ba9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93617
4129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.936174129
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.712491884
Short name T198
Test name
Test status
Simulation time 1165485920 ps
CPU time 2.71 seconds
Started Jun 30 06:21:26 PM PDT 24
Finished Jun 30 06:21:30 PM PDT 24
Peak memory 206260 kb
Host smart-41d9a77d-aec1-46aa-a4fb-4aed0a494551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71249
1884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.712491884
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.3054684198
Short name T806
Test name
Test status
Simulation time 13337370404 ps
CPU time 24.44 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:21:53 PM PDT 24
Peak memory 206436 kb
Host smart-1159a5db-b65b-4f2f-b582-eed942ce7599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30546
84198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3054684198
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.33929560
Short name T375
Test name
Test status
Simulation time 408317570 ps
CPU time 1.29 seconds
Started Jun 30 06:21:21 PM PDT 24
Finished Jun 30 06:21:23 PM PDT 24
Peak memory 206184 kb
Host smart-256878a7-f739-4242-8552-fe36773656ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33929
560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.33929560
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.4221839671
Short name T1089
Test name
Test status
Simulation time 190181746 ps
CPU time 0.86 seconds
Started Jun 30 06:21:22 PM PDT 24
Finished Jun 30 06:21:23 PM PDT 24
Peak memory 206152 kb
Host smart-d01583f1-75a3-47b0-a6f0-90da21231667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42218
39671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.4221839671
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.61067054
Short name T2282
Test name
Test status
Simulation time 56850575 ps
CPU time 0.67 seconds
Started Jun 30 06:21:21 PM PDT 24
Finished Jun 30 06:21:22 PM PDT 24
Peak memory 206200 kb
Host smart-a2b041c8-17df-498d-8d08-014213e536cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61067
054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.61067054
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.29449317
Short name T1374
Test name
Test status
Simulation time 908117472 ps
CPU time 2.09 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:21:32 PM PDT 24
Peak memory 206244 kb
Host smart-b85abc43-8df8-4da7-bebb-7bcf5033e80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29449
317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.29449317
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.734559955
Short name T206
Test name
Test status
Simulation time 322810703 ps
CPU time 1.89 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:21:32 PM PDT 24
Peak memory 206276 kb
Host smart-bbd2d65d-cbc0-46a0-9b2d-c6c5fd1958d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73455
9955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.734559955
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2997157420
Short name T2103
Test name
Test status
Simulation time 198741314 ps
CPU time 0.84 seconds
Started Jun 30 06:21:24 PM PDT 24
Finished Jun 30 06:21:25 PM PDT 24
Peak memory 206196 kb
Host smart-ddd17fbe-f1e3-4e5f-919b-13753a2b2404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29971
57420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2997157420
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3316446777
Short name T1442
Test name
Test status
Simulation time 150896811 ps
CPU time 0.8 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:21:29 PM PDT 24
Peak memory 206196 kb
Host smart-6c4a7fc3-7ee2-469f-bd28-2f48348e431d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33164
46777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3316446777
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1767546717
Short name T1785
Test name
Test status
Simulation time 233365061 ps
CPU time 0.91 seconds
Started Jun 30 06:21:24 PM PDT 24
Finished Jun 30 06:21:26 PM PDT 24
Peak memory 206176 kb
Host smart-fe3e72d1-9389-4a41-be2e-e825c54de175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17675
46717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1767546717
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.4059753283
Short name T2431
Test name
Test status
Simulation time 248870555 ps
CPU time 0.85 seconds
Started Jun 30 06:21:20 PM PDT 24
Finished Jun 30 06:21:21 PM PDT 24
Peak memory 206188 kb
Host smart-927ca774-259f-46c1-a9cb-045ea02695c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40597
53283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.4059753283
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.465372426
Short name T534
Test name
Test status
Simulation time 23297148406 ps
CPU time 22.71 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:21:53 PM PDT 24
Peak memory 205956 kb
Host smart-8bf6c379-5b0a-4276-936b-cdd7ffbe30df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46537
2426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.465372426
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2409004572
Short name T1305
Test name
Test status
Simulation time 3274223368 ps
CPU time 4.58 seconds
Started Jun 30 06:21:30 PM PDT 24
Finished Jun 30 06:21:36 PM PDT 24
Peak memory 206244 kb
Host smart-44ee74ef-ac37-4d0b-9b5a-1bd61eb59dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24090
04572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2409004572
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3389315495
Short name T2427
Test name
Test status
Simulation time 11008300581 ps
CPU time 312.96 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:26:41 PM PDT 24
Peak memory 206508 kb
Host smart-d46cdeb3-54ce-407c-b7d6-1092a5360f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33893
15495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3389315495
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.905726283
Short name T1395
Test name
Test status
Simulation time 5036346830 ps
CPU time 48.7 seconds
Started Jun 30 06:21:26 PM PDT 24
Finished Jun 30 06:22:15 PM PDT 24
Peak memory 206440 kb
Host smart-19f3ae08-874b-4eac-8396-4c26ae125c05
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=905726283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.905726283
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3501535894
Short name T938
Test name
Test status
Simulation time 243227697 ps
CPU time 0.94 seconds
Started Jun 30 06:21:21 PM PDT 24
Finished Jun 30 06:21:23 PM PDT 24
Peak memory 206188 kb
Host smart-67a0716a-2159-4c12-abb9-1ada79efca84
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3501535894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3501535894
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.4242469794
Short name T2116
Test name
Test status
Simulation time 181669460 ps
CPU time 0.83 seconds
Started Jun 30 06:21:26 PM PDT 24
Finished Jun 30 06:21:28 PM PDT 24
Peak memory 206204 kb
Host smart-3b3e824a-5ba6-4469-a0b6-8d568415db04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42424
69794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.4242469794
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.949611704
Short name T841
Test name
Test status
Simulation time 4447040391 ps
CPU time 122.16 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:23:32 PM PDT 24
Peak memory 206108 kb
Host smart-60d1f316-2d38-4ffb-be30-8d68f601a8c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94961
1704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.949611704
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.4115271422
Short name T82
Test name
Test status
Simulation time 6685252067 ps
CPU time 66.49 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:22:36 PM PDT 24
Peak memory 206484 kb
Host smart-14d76e6b-7038-44e3-adb7-4862afa1d5b1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4115271422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.4115271422
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.77940308
Short name T688
Test name
Test status
Simulation time 156934880 ps
CPU time 0.83 seconds
Started Jun 30 06:21:24 PM PDT 24
Finished Jun 30 06:21:26 PM PDT 24
Peak memory 206164 kb
Host smart-9d4e176a-31aa-44f4-9595-973806d37c99
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=77940308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.77940308
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1618903375
Short name T1577
Test name
Test status
Simulation time 151330552 ps
CPU time 0.75 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:21:31 PM PDT 24
Peak memory 206164 kb
Host smart-660edae5-f352-474c-9af5-a1cff0bf5ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16189
03375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1618903375
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3505889442
Short name T131
Test name
Test status
Simulation time 185580016 ps
CPU time 0.82 seconds
Started Jun 30 06:21:23 PM PDT 24
Finished Jun 30 06:21:24 PM PDT 24
Peak memory 206120 kb
Host smart-3b96a2fc-fa10-4f90-bf72-4a41301f601d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35058
89442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3505889442
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2251751097
Short name T2305
Test name
Test status
Simulation time 191007243 ps
CPU time 0.81 seconds
Started Jun 30 06:21:29 PM PDT 24
Finished Jun 30 06:21:31 PM PDT 24
Peak memory 206144 kb
Host smart-73e8f543-bda4-4b4e-b8f1-1a973e109031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22517
51097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2251751097
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1671835760
Short name T2154
Test name
Test status
Simulation time 156111393 ps
CPU time 0.76 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:21:30 PM PDT 24
Peak memory 206176 kb
Host smart-884cd969-766f-45c7-9375-99682478370a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16718
35760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1671835760
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1753386014
Short name T1027
Test name
Test status
Simulation time 173127081 ps
CPU time 0.76 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:21:30 PM PDT 24
Peak memory 206176 kb
Host smart-692ffb96-f4e1-465a-ba7a-327f02f5de4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17533
86014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1753386014
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2543958537
Short name T853
Test name
Test status
Simulation time 175709042 ps
CPU time 0.81 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:21:31 PM PDT 24
Peak memory 206196 kb
Host smart-ca97dc50-6174-44b2-8bc6-cc386fd7c668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25439
58537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2543958537
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.1037647218
Short name T1644
Test name
Test status
Simulation time 239189909 ps
CPU time 0.96 seconds
Started Jun 30 06:21:26 PM PDT 24
Finished Jun 30 06:21:29 PM PDT 24
Peak memory 206204 kb
Host smart-44d78b10-ca8d-4270-a525-87d811d0809a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1037647218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.1037647218
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.953002297
Short name T1503
Test name
Test status
Simulation time 168565920 ps
CPU time 0.75 seconds
Started Jun 30 06:21:32 PM PDT 24
Finished Jun 30 06:21:33 PM PDT 24
Peak memory 206212 kb
Host smart-492126b4-1d5f-4ff3-8b2d-7ddd3fd6d6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95300
2297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.953002297
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2733990
Short name T620
Test name
Test status
Simulation time 46932108 ps
CPU time 0.68 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:21:29 PM PDT 24
Peak memory 206184 kb
Host smart-c6999d94-80bb-497c-ac9c-bb770bc63584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27339
90 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2733990
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2222174627
Short name T1888
Test name
Test status
Simulation time 9937811697 ps
CPU time 21.57 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:21:49 PM PDT 24
Peak memory 206436 kb
Host smart-f725ca73-628e-460c-9804-736dc255bd4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22221
74627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2222174627
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1383679769
Short name T49
Test name
Test status
Simulation time 199215845 ps
CPU time 0.86 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:21:30 PM PDT 24
Peak memory 206196 kb
Host smart-04cf7b35-77da-4569-8e9a-b8ada6bf0323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13836
79769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1383679769
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2830072318
Short name T1529
Test name
Test status
Simulation time 167753582 ps
CPU time 0.86 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:21:29 PM PDT 24
Peak memory 206156 kb
Host smart-13b48cc5-29a0-4e50-a13a-b05ac9c07ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28300
72318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2830072318
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1267060463
Short name T171
Test name
Test status
Simulation time 11544824296 ps
CPU time 60.07 seconds
Started Jun 30 06:21:26 PM PDT 24
Finished Jun 30 06:22:27 PM PDT 24
Peak memory 206464 kb
Host smart-31e3b2d7-07dd-4356-b5ef-b03931a7bc89
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1267060463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1267060463
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3922061663
Short name T161
Test name
Test status
Simulation time 14426662616 ps
CPU time 97.48 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:23:07 PM PDT 24
Peak memory 206476 kb
Host smart-b7a4cd0b-c2c6-403e-82ad-977b20c30b4a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3922061663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3922061663
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1365319394
Short name T2565
Test name
Test status
Simulation time 8740498358 ps
CPU time 48.7 seconds
Started Jun 30 06:21:29 PM PDT 24
Finished Jun 30 06:22:19 PM PDT 24
Peak memory 206488 kb
Host smart-2ccb2afb-dc79-4f7e-9356-1e20c51b17f3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1365319394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1365319394
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1682386629
Short name T1609
Test name
Test status
Simulation time 228586021 ps
CPU time 0.86 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:21:30 PM PDT 24
Peak memory 206196 kb
Host smart-628d4bfe-f515-4c1c-82ce-07bcf25fee42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16823
86629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1682386629
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.96956949
Short name T1840
Test name
Test status
Simulation time 179163793 ps
CPU time 0.84 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:21:30 PM PDT 24
Peak memory 206176 kb
Host smart-a3cbd34d-402a-4cfb-b493-f71515dfdef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96956
949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.96956949
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2422967231
Short name T1987
Test name
Test status
Simulation time 183611370 ps
CPU time 0.77 seconds
Started Jun 30 06:21:32 PM PDT 24
Finished Jun 30 06:21:34 PM PDT 24
Peak memory 206200 kb
Host smart-553e8a3b-1c76-468c-8362-0c1dfaa4d5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24229
67231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2422967231
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2018487031
Short name T2424
Test name
Test status
Simulation time 145737169 ps
CPU time 0.8 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:21:30 PM PDT 24
Peak memory 206160 kb
Host smart-74e5883a-f2dc-4216-908e-ab1d3af17fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20184
87031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2018487031
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1412686462
Short name T1921
Test name
Test status
Simulation time 169430267 ps
CPU time 0.89 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:21:29 PM PDT 24
Peak memory 206164 kb
Host smart-46c4d04a-08da-46b0-bc70-89eff6ba0f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14126
86462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1412686462
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1015026397
Short name T1743
Test name
Test status
Simulation time 209673225 ps
CPU time 0.9 seconds
Started Jun 30 06:21:27 PM PDT 24
Finished Jun 30 06:21:29 PM PDT 24
Peak memory 206200 kb
Host smart-c8866104-0284-43f4-bdee-4bdd02b1a227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10150
26397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1015026397
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1910768896
Short name T2426
Test name
Test status
Simulation time 4037389428 ps
CPU time 29.51 seconds
Started Jun 30 06:21:28 PM PDT 24
Finished Jun 30 06:22:00 PM PDT 24
Peak memory 206360 kb
Host smart-f48a2d6c-984d-4476-9e63-6987cddeaa94
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1910768896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1910768896
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.488690563
Short name T1928
Test name
Test status
Simulation time 177251194 ps
CPU time 0.84 seconds
Started Jun 30 06:21:26 PM PDT 24
Finished Jun 30 06:21:28 PM PDT 24
Peak memory 206224 kb
Host smart-e70bc72b-2423-4c3d-a59a-46f1bba97871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48869
0563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.488690563
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3830524825
Short name T598
Test name
Test status
Simulation time 216437632 ps
CPU time 0.86 seconds
Started Jun 30 06:21:29 PM PDT 24
Finished Jun 30 06:21:31 PM PDT 24
Peak memory 206180 kb
Host smart-f77fc8ba-74dc-43dd-b4c6-95fb2c53acfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38305
24825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3830524825
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3363512125
Short name T2143
Test name
Test status
Simulation time 6202898116 ps
CPU time 166.44 seconds
Started Jun 30 06:21:30 PM PDT 24
Finished Jun 30 06:24:17 PM PDT 24
Peak memory 206444 kb
Host smart-97389311-f746-487d-ae76-884ce864c559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33635
12125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3363512125
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.4050040293
Short name T2323
Test name
Test status
Simulation time 37151330 ps
CPU time 0.67 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206044 kb
Host smart-4eb35655-807a-4246-90c4-8fbaa6087b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4050040293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.4050040293
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.469886024
Short name T2514
Test name
Test status
Simulation time 3968599920 ps
CPU time 4.78 seconds
Started Jun 30 06:21:36 PM PDT 24
Finished Jun 30 06:21:41 PM PDT 24
Peak memory 206396 kb
Host smart-05a06984-a111-4495-8cf4-fe72dae8a7ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=469886024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.469886024
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3443125532
Short name T2031
Test name
Test status
Simulation time 13438883592 ps
CPU time 12.98 seconds
Started Jun 30 06:21:38 PM PDT 24
Finished Jun 30 06:21:52 PM PDT 24
Peak memory 206404 kb
Host smart-569ac7a0-e87e-4d43-b5ec-997d76289ae6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3443125532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3443125532
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1536224417
Short name T1457
Test name
Test status
Simulation time 23332088883 ps
CPU time 24.4 seconds
Started Jun 30 06:21:37 PM PDT 24
Finished Jun 30 06:22:02 PM PDT 24
Peak memory 206276 kb
Host smart-cb206184-22bd-4c2f-a41d-a181a38f1786
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1536224417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.1536224417
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.4029345483
Short name T1944
Test name
Test status
Simulation time 160740133 ps
CPU time 0.79 seconds
Started Jun 30 06:21:36 PM PDT 24
Finished Jun 30 06:21:37 PM PDT 24
Peak memory 206192 kb
Host smart-4d36ad6b-1fa4-4ac9-b005-10dc136cdcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40293
45483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.4029345483
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.3903810171
Short name T176
Test name
Test status
Simulation time 395333632 ps
CPU time 1.35 seconds
Started Jun 30 06:21:36 PM PDT 24
Finished Jun 30 06:21:38 PM PDT 24
Peak memory 206192 kb
Host smart-2badc050-76f0-4588-89d8-dddde82a7c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39038
10171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.3903810171
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3166996490
Short name T993
Test name
Test status
Simulation time 672497678 ps
CPU time 1.71 seconds
Started Jun 30 06:21:33 PM PDT 24
Finished Jun 30 06:21:35 PM PDT 24
Peak memory 206184 kb
Host smart-8c949dcf-1c1f-42da-b0cb-8917c8167e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31669
96490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3166996490
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1188078378
Short name T1164
Test name
Test status
Simulation time 9408755919 ps
CPU time 18.15 seconds
Started Jun 30 06:21:33 PM PDT 24
Finished Jun 30 06:21:52 PM PDT 24
Peak memory 206432 kb
Host smart-2cde17c1-6d52-48d3-b271-8dc9bc4b7af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11880
78378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1188078378
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3002384097
Short name T356
Test name
Test status
Simulation time 471042378 ps
CPU time 1.41 seconds
Started Jun 30 06:21:37 PM PDT 24
Finished Jun 30 06:21:38 PM PDT 24
Peak memory 206216 kb
Host smart-d425fbe1-20ef-4397-9631-960084436b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30023
84097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3002384097
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.2466175079
Short name T1704
Test name
Test status
Simulation time 166157901 ps
CPU time 0.79 seconds
Started Jun 30 06:21:42 PM PDT 24
Finished Jun 30 06:21:43 PM PDT 24
Peak memory 206144 kb
Host smart-2fbbc41e-499b-424e-ab24-6355e503b181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24661
75079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.2466175079
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3679425151
Short name T1157
Test name
Test status
Simulation time 50096400 ps
CPU time 0.67 seconds
Started Jun 30 06:21:34 PM PDT 24
Finished Jun 30 06:21:35 PM PDT 24
Peak memory 206384 kb
Host smart-6dec430e-728d-47cc-a258-761adfd0fa7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36794
25151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3679425151
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.1507144990
Short name T2484
Test name
Test status
Simulation time 944549373 ps
CPU time 2.13 seconds
Started Jun 30 06:21:35 PM PDT 24
Finished Jun 30 06:21:38 PM PDT 24
Peak memory 206308 kb
Host smart-1b5ed1e8-1274-47ab-96dc-e1f0bd148734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15071
44990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1507144990
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1158816734
Short name T759
Test name
Test status
Simulation time 191341558 ps
CPU time 1.3 seconds
Started Jun 30 06:21:38 PM PDT 24
Finished Jun 30 06:21:40 PM PDT 24
Peak memory 206288 kb
Host smart-740ea161-6692-4171-809d-a3c524132d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11588
16734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1158816734
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1251855159
Short name T2088
Test name
Test status
Simulation time 219319157 ps
CPU time 0.94 seconds
Started Jun 30 06:21:35 PM PDT 24
Finished Jun 30 06:21:36 PM PDT 24
Peak memory 206168 kb
Host smart-06c89277-b403-46db-9a04-e0861a89372e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12518
55159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1251855159
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2986072267
Short name T1017
Test name
Test status
Simulation time 141240638 ps
CPU time 0.81 seconds
Started Jun 30 06:21:36 PM PDT 24
Finished Jun 30 06:21:37 PM PDT 24
Peak memory 206188 kb
Host smart-23603f25-e8ed-4e89-b818-6d895cacb8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29860
72267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2986072267
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2686102821
Short name T368
Test name
Test status
Simulation time 250512902 ps
CPU time 1.02 seconds
Started Jun 30 06:21:36 PM PDT 24
Finished Jun 30 06:21:37 PM PDT 24
Peak memory 206212 kb
Host smart-647e53bc-633e-4018-956c-d64e75a67e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26861
02821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2686102821
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.298251076
Short name T407
Test name
Test status
Simulation time 198551072 ps
CPU time 0.85 seconds
Started Jun 30 06:21:34 PM PDT 24
Finished Jun 30 06:21:35 PM PDT 24
Peak memory 206396 kb
Host smart-258134e7-9165-4d3e-8c05-08fde8d7cf5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29825
1076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.298251076
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.4178014346
Short name T571
Test name
Test status
Simulation time 23408130622 ps
CPU time 23.95 seconds
Started Jun 30 06:21:35 PM PDT 24
Finished Jun 30 06:21:59 PM PDT 24
Peak memory 206300 kb
Host smart-47461d29-4a8e-4ed3-82c0-cd4b49c2d778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41780
14346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.4178014346
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1827395884
Short name T703
Test name
Test status
Simulation time 3356395194 ps
CPU time 4.13 seconds
Started Jun 30 06:21:34 PM PDT 24
Finished Jun 30 06:21:38 PM PDT 24
Peak memory 206252 kb
Host smart-feaabb38-0d3c-4714-ac4d-a432f9bc0de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18273
95884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1827395884
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1497690267
Short name T2315
Test name
Test status
Simulation time 7390087212 ps
CPU time 71.71 seconds
Started Jun 30 06:21:34 PM PDT 24
Finished Jun 30 06:22:46 PM PDT 24
Peak memory 206464 kb
Host smart-d082b31f-e226-48cb-9a24-864f4be5cbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14976
90267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1497690267
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.727012464
Short name T2196
Test name
Test status
Simulation time 3933546227 ps
CPU time 37.01 seconds
Started Jun 30 06:21:36 PM PDT 24
Finished Jun 30 06:22:13 PM PDT 24
Peak memory 206460 kb
Host smart-d14993f8-dc4f-4f30-883a-5fc19859f273
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=727012464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.727012464
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3886937046
Short name T705
Test name
Test status
Simulation time 243251071 ps
CPU time 0.96 seconds
Started Jun 30 06:21:34 PM PDT 24
Finished Jun 30 06:21:36 PM PDT 24
Peak memory 206216 kb
Host smart-4b49c8ec-aaf6-4322-8176-9c2ff2df37cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3886937046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3886937046
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1907620658
Short name T1076
Test name
Test status
Simulation time 186330510 ps
CPU time 0.91 seconds
Started Jun 30 06:21:36 PM PDT 24
Finished Jun 30 06:21:38 PM PDT 24
Peak memory 206212 kb
Host smart-fe0c78bb-b97d-4f36-bfcc-f8a9677efadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19076
20658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1907620658
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.1736703242
Short name T2034
Test name
Test status
Simulation time 5085519042 ps
CPU time 36.08 seconds
Started Jun 30 06:21:33 PM PDT 24
Finished Jun 30 06:22:10 PM PDT 24
Peak memory 206460 kb
Host smart-dcddf4ee-2040-47dd-bf48-96a7807f0c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17367
03242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.1736703242
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.621030847
Short name T2275
Test name
Test status
Simulation time 4550232706 ps
CPU time 41.76 seconds
Started Jun 30 06:21:34 PM PDT 24
Finished Jun 30 06:22:17 PM PDT 24
Peak memory 206412 kb
Host smart-273d014f-c0a5-4ba9-ac09-d11049bab3bd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=621030847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.621030847
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.1989672240
Short name T2166
Test name
Test status
Simulation time 148723249 ps
CPU time 0.79 seconds
Started Jun 30 06:21:34 PM PDT 24
Finished Jun 30 06:21:35 PM PDT 24
Peak memory 206236 kb
Host smart-f7931dcc-b856-486f-ae11-e4e9eb5f715e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1989672240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.1989672240
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.4203074942
Short name T1306
Test name
Test status
Simulation time 155902653 ps
CPU time 0.8 seconds
Started Jun 30 06:21:36 PM PDT 24
Finished Jun 30 06:21:37 PM PDT 24
Peak memory 206212 kb
Host smart-116c6028-c6ad-4d8f-aa30-2a44e5948976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42030
74942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.4203074942
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1381004911
Short name T122
Test name
Test status
Simulation time 213932418 ps
CPU time 0.89 seconds
Started Jun 30 06:21:40 PM PDT 24
Finished Jun 30 06:21:42 PM PDT 24
Peak memory 206180 kb
Host smart-d0213cdc-734a-488e-a6e2-63a89ef169be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13810
04911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1381004911
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2596735823
Short name T1380
Test name
Test status
Simulation time 183291118 ps
CPU time 0.88 seconds
Started Jun 30 06:21:42 PM PDT 24
Finished Jun 30 06:21:44 PM PDT 24
Peak memory 206156 kb
Host smart-a0550278-a2fc-4705-906a-8cbc0feaab98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25967
35823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2596735823
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.4102042343
Short name T351
Test name
Test status
Simulation time 162073158 ps
CPU time 0.81 seconds
Started Jun 30 06:21:40 PM PDT 24
Finished Jun 30 06:21:42 PM PDT 24
Peak memory 206200 kb
Host smart-193be73f-a350-40c0-9235-fdfb33a73094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41020
42343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.4102042343
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.415553930
Short name T2561
Test name
Test status
Simulation time 170388107 ps
CPU time 0.83 seconds
Started Jun 30 06:21:40 PM PDT 24
Finished Jun 30 06:21:41 PM PDT 24
Peak memory 206192 kb
Host smart-c624716b-e6c7-44a7-99bf-cf457b235539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41555
3930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.415553930
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1480798517
Short name T1145
Test name
Test status
Simulation time 150109208 ps
CPU time 0.82 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206152 kb
Host smart-9893fe23-dd0b-46dd-81dc-020bd0e0fa89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14807
98517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1480798517
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3751727730
Short name T890
Test name
Test status
Simulation time 269427105 ps
CPU time 1.04 seconds
Started Jun 30 06:21:39 PM PDT 24
Finished Jun 30 06:21:40 PM PDT 24
Peak memory 206208 kb
Host smart-ccc68ae2-4d1b-41e8-ad7f-310698b7eb42
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3751727730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3751727730
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3648518022
Short name T1078
Test name
Test status
Simulation time 143518927 ps
CPU time 0.76 seconds
Started Jun 30 06:21:41 PM PDT 24
Finished Jun 30 06:21:42 PM PDT 24
Peak memory 206164 kb
Host smart-786b467a-9376-4ce0-a3df-98697b12523d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36485
18022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3648518022
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.995843582
Short name T36
Test name
Test status
Simulation time 44930392 ps
CPU time 0.68 seconds
Started Jun 30 06:21:40 PM PDT 24
Finished Jun 30 06:21:42 PM PDT 24
Peak memory 206200 kb
Host smart-491883c2-1c4c-4782-a239-f3358c6e0e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99584
3582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.995843582
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3595016727
Short name T22
Test name
Test status
Simulation time 21988132705 ps
CPU time 48.93 seconds
Started Jun 30 06:21:39 PM PDT 24
Finished Jun 30 06:22:28 PM PDT 24
Peak memory 206436 kb
Host smart-5f341ee9-1acc-469b-9232-3b6a79d9b32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950
16727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3595016727
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3354069022
Short name T678
Test name
Test status
Simulation time 153950261 ps
CPU time 0.78 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206148 kb
Host smart-76086b87-2c7a-4c98-b987-3038b6e020f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33540
69022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3354069022
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3533260681
Short name T1071
Test name
Test status
Simulation time 265133259 ps
CPU time 0.99 seconds
Started Jun 30 06:21:42 PM PDT 24
Finished Jun 30 06:21:44 PM PDT 24
Peak memory 206128 kb
Host smart-87f305b9-b58d-4e82-b5b3-780ec6d828f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35332
60681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3533260681
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1927882673
Short name T1902
Test name
Test status
Simulation time 13868505263 ps
CPU time 265.03 seconds
Started Jun 30 06:21:40 PM PDT 24
Finished Jun 30 06:26:05 PM PDT 24
Peak memory 206532 kb
Host smart-d9129b24-3943-4289-966f-62d57e1ba59a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1927882673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1927882673
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.2910838024
Short name T1821
Test name
Test status
Simulation time 14913291220 ps
CPU time 311.22 seconds
Started Jun 30 06:21:38 PM PDT 24
Finished Jun 30 06:26:50 PM PDT 24
Peak memory 206484 kb
Host smart-d927c4d5-2a38-44b9-a54c-221ba8d4ff6a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2910838024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2910838024
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2455597498
Short name T503
Test name
Test status
Simulation time 222215367 ps
CPU time 0.91 seconds
Started Jun 30 06:21:39 PM PDT 24
Finished Jun 30 06:21:40 PM PDT 24
Peak memory 206228 kb
Host smart-a2bafca0-2bb2-48ed-b51c-7b60c967b1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24555
97498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2455597498
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.3249877974
Short name T679
Test name
Test status
Simulation time 181275002 ps
CPU time 0.82 seconds
Started Jun 30 06:21:46 PM PDT 24
Finished Jun 30 06:21:48 PM PDT 24
Peak memory 206192 kb
Host smart-bec1bd6e-848a-4ec9-b036-97006fa0ab80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32498
77974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3249877974
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3031991128
Short name T1717
Test name
Test status
Simulation time 195342673 ps
CPU time 0.86 seconds
Started Jun 30 06:21:40 PM PDT 24
Finished Jun 30 06:21:42 PM PDT 24
Peak memory 206196 kb
Host smart-b9a77b7a-b61b-47a5-a94f-7f5b828b1ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30319
91128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3031991128
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1959879465
Short name T2121
Test name
Test status
Simulation time 149139996 ps
CPU time 0.83 seconds
Started Jun 30 06:21:38 PM PDT 24
Finished Jun 30 06:21:40 PM PDT 24
Peak memory 206180 kb
Host smart-de0508da-b8b7-4b60-9d09-81139504656a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19598
79465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1959879465
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3014871480
Short name T1631
Test name
Test status
Simulation time 167682446 ps
CPU time 0.78 seconds
Started Jun 30 06:21:46 PM PDT 24
Finished Jun 30 06:21:48 PM PDT 24
Peak memory 206188 kb
Host smart-29f49bba-9341-4651-b745-3bec80021f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30148
71480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3014871480
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2218008045
Short name T2030
Test name
Test status
Simulation time 209481082 ps
CPU time 0.89 seconds
Started Jun 30 06:21:39 PM PDT 24
Finished Jun 30 06:21:41 PM PDT 24
Peak memory 206200 kb
Host smart-7e835043-2e32-48ed-9f7e-2ddc12ec8b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22180
08045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2218008045
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2363454699
Short name T901
Test name
Test status
Simulation time 4375852221 ps
CPU time 31.63 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:22:29 PM PDT 24
Peak memory 206212 kb
Host smart-6c977600-5747-4610-aae4-17ca44944b14
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2363454699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2363454699
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3056881510
Short name T2368
Test name
Test status
Simulation time 167433425 ps
CPU time 0.83 seconds
Started Jun 30 06:21:46 PM PDT 24
Finished Jun 30 06:21:48 PM PDT 24
Peak memory 206216 kb
Host smart-76748acb-240b-4f15-bdea-ecd76b4989d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30568
81510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3056881510
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.433371995
Short name T767
Test name
Test status
Simulation time 224705423 ps
CPU time 0.87 seconds
Started Jun 30 06:21:55 PM PDT 24
Finished Jun 30 06:21:58 PM PDT 24
Peak memory 206148 kb
Host smart-35237963-323b-4b63-a0b2-0b9512a0ad3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43337
1995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.433371995
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.996471354
Short name T2029
Test name
Test status
Simulation time 3124288825 ps
CPU time 29.78 seconds
Started Jun 30 06:21:41 PM PDT 24
Finished Jun 30 06:22:11 PM PDT 24
Peak memory 206460 kb
Host smart-de889a80-23bf-4031-9ea7-13f18db26cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99647
1354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.996471354
Directory /workspace/9.usbdev_streaming_out/latest
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