Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	168191	1		T1	2		T2	2		T3	2
all_values[1]	168191	1		T1	2		T2	2		T3	2
all_values[2]	168191	1		T1	2		T2	2		T3	2
all_values[3]	168191	1		T1	2		T2	2		T3	2
all_values[4]	168191	1		T1	2		T2	2		T3	2
all_values[5]	168191	1		T1	2		T2	2		T3	2
all_values[6]	168191	1		T1	2		T2	2		T3	2
all_values[7]	168191	1		T1	2		T2	2		T3	2
all_values[8]	168191	1		T1	2		T2	2		T3	2
all_values[9]	168191	1		T1	2		T2	2		T3	2
all_values[10]	168191	1		T1	2		T2	2		T3	2
all_values[11]	168191	1		T1	2		T2	2		T3	2
all_values[12]	168191	1		T1	2		T2	2		T3	2
all_values[13]	168191	1		T1	2		T2	2		T3	2
all_values[14]	168191	1		T1	2		T2	2		T3	2
all_values[15]	168191	1		T1	2		T2	2		T3	2
all_values[16]	168191	1		T1	2		T2	2		T3	2
all_values[17]	168191	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3020571	1		T1	34		T2	36		T3	36
auto[1]	6867	1		T1	2		T30	14		T36	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3022528	1		T1	36		T2	36		T3	36
auto[1]	4910	1		T223	77		T224	54		T227	65

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	167221	1		T1	2		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	132	1		T224	1		T227	1		T311	1
all_values[0]	auto[1]	auto[0]	694	1		T18	4		T51	3		T52	4
all_values[0]	auto[1]	auto[1]	144	1		T223	5		T224	4		T227	4
all_values[1]	auto[0]	auto[0]	166409	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	133	1		T224	1		T227	3		T311	4
all_values[1]	auto[1]	auto[0]	1530	1		T30	14		T7	2		T32	2
all_values[1]	auto[1]	auto[1]	119	1		T223	4		T224	3		T227	2
all_values[2]	auto[0]	auto[0]	167782	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	145	1		T223	3		T224	3		T227	1
all_values[2]	auto[1]	auto[0]	118	1		T43	2		T46	2		T47	2
all_values[2]	auto[1]	auto[1]	146	1		T223	2		T224	2		T227	3
all_values[3]	auto[0]	auto[0]	166404	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	158	1		T223	1		T224	3		T226	4
all_values[3]	auto[1]	auto[0]	1509	1		T68	1485		T224	1		T227	1
all_values[3]	auto[1]	auto[1]	120	1		T223	4		T229	2		T228	1
all_values[4]	auto[0]	auto[0]	167883	1		T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	142	1		T227	1		T225	5		T226	3
all_values[4]	auto[1]	auto[0]	42	1		T69	2		T223	1		T224	4
all_values[4]	auto[1]	auto[1]	124	1		T223	4		T227	4		T225	2
all_values[5]	auto[0]	auto[0]	167893	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	143	1		T223	3		T227	3		T311	4
all_values[5]	auto[1]	auto[0]	21	1		T223	1		T224	2		T227	1
all_values[5]	auto[1]	auto[1]	134	1		T223	1		T227	1		T225	3
all_values[6]	auto[0]	auto[0]	167887	1		T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	132	1		T223	4		T224	2		T227	1
all_values[6]	auto[1]	auto[0]	19	1		T312	1		T310	1		T313	1
all_values[6]	auto[1]	auto[1]	153	1		T223	1		T224	3		T227	4
all_values[7]	auto[0]	auto[0]	167882	1		T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	125	1		T227	3		T226	1		T228	3
all_values[7]	auto[1]	auto[0]	24	1		T54	2		T55	2		T56	2
all_values[7]	auto[1]	auto[1]	160	1		T223	3		T224	5		T227	2
all_values[8]	auto[0]	auto[0]	167877	1		T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	114	1		T223	1		T224	3		T227	1
all_values[8]	auto[1]	auto[0]	40	1		T57	11		T224	1		T226	1
all_values[8]	auto[1]	auto[1]	160	1		T223	4		T227	4		T311	4
all_values[9]	auto[0]	auto[0]	167871	1		T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	148	1		T223	1		T224	1		T227	1
all_values[9]	auto[1]	auto[0]	52	1		T50	5		T66	5		T67	5
all_values[9]	auto[1]	auto[1]	120	1		T223	3		T224	4		T227	3
all_values[10]	auto[0]	auto[0]	167898	1		T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	134	1		T223	1		T227	4		T225	5
all_values[10]	auto[1]	auto[0]	26	1		T314	1		T312	2		T310	1
all_values[10]	auto[1]	auto[1]	133	1		T223	4		T224	4		T227	1
all_values[11]	auto[0]	auto[0]	167792	1		T2	2		T3	2		T28	3
all_values[11]	auto[0]	auto[1]	137	1		T223	2		T227	5		T311	4
all_values[11]	auto[1]	auto[0]	135	1		T1	2		T36	2		T73	2
all_values[11]	auto[1]	auto[1]	127	1		T223	3		T311	1		T225	5
all_values[12]	auto[0]	auto[0]	167873	1		T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	144	1		T224	3		T225	5		T226	4
all_values[12]	auto[1]	auto[0]	52	1		T74	3		T76	3		T77	3
all_values[12]	auto[1]	auto[1]	122	1		T311	4		T225	3		T229	1
all_values[13]	auto[0]	auto[0]	167889	1		T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	135	1		T223	4		T311	4		T225	5
all_values[13]	auto[1]	auto[0]	24	1		T224	4		T227	2		T226	1
all_values[13]	auto[1]	auto[1]	143	1		T311	1		T225	3		T226	4
all_values[14]	auto[0]	auto[0]	167902	1		T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	119	1		T311	4		T225	1		T226	1
all_values[14]	auto[1]	auto[0]	23	1		T227	2		T314	1		T313	1
all_values[14]	auto[1]	auto[1]	147	1		T223	5		T311	1		T225	7
all_values[15]	auto[0]	auto[0]	167894	1		T1	2		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	141	1		T224	3		T227	4		T311	4
all_values[15]	auto[1]	auto[0]	25	1		T224	1		T226	1		T229	5
all_values[15]	auto[1]	auto[1]	131	1		T223	5		T224	1		T225	6
all_values[16]	auto[0]	auto[0]	167868	1		T1	2		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	147	1		T223	4		T224	4		T227	1
all_values[16]	auto[1]	auto[0]	52	1		T70	8		T71	8		T72	8
all_values[16]	auto[1]	auto[1]	124	1		T223	1		T227	4		T225	3
all_values[17]	auto[0]	auto[0]	167890	1		T1	2		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	127	1		T224	1		T227	4		T311	4
all_values[17]	auto[1]	auto[0]	27	1		T61	2		T223	1		T224	1
all_values[17]	auto[1]	auto[1]	147	1		T223	4		T224	3		T311	1