Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	168191	1		T1	2		T2	2		T3	2
all_pins[1]	168191	1		T1	2		T2	2		T3	2
all_pins[2]	168191	1		T1	2		T2	2		T3	2
all_pins[3]	168191	1		T1	2		T2	2		T3	2
all_pins[4]	168191	1		T1	2		T2	2		T3	2
all_pins[5]	168191	1		T1	2		T2	2		T3	2
all_pins[6]	168191	1		T1	2		T2	2		T3	2
all_pins[7]	168191	1		T1	2		T2	2		T3	2
all_pins[8]	168191	1		T1	2		T2	2		T3	2
all_pins[9]	168191	1		T1	2		T2	2		T3	2
all_pins[10]	168191	1		T1	2		T2	2		T3	2
all_pins[11]	168191	1		T1	2		T2	2		T3	2
all_pins[12]	168191	1		T1	2		T2	2		T3	2
all_pins[13]	168191	1		T1	2		T2	2		T3	2
all_pins[14]	168191	1		T1	2		T2	2		T3	2
all_pins[15]	168191	1		T1	2		T2	2		T3	2
all_pins[16]	168191	1		T1	2		T2	2		T3	2
all_pins[17]	168191	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3025107	1		T1	35		T2	36		T3	36
values[0x1]	2331	1		T1	1		T30	12		T36	1
transitions[0x0=>0x1]	1989	1		T1	1		T30	12		T36	1
transitions[0x1=>0x0]	2004	1		T1	1		T30	12		T36	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	168077	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	114	1		T18	1		T52	1		T315	1
all_pins[0]	transitions[0x0=>0x1]	100	1		T18	1		T52	1		T315	1
all_pins[0]	transitions[0x1=>0x0]	984	1		T30	12		T7	1		T32	1
all_pins[1]	values[0x0]	167193	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	998	1		T30	12		T7	1		T32	1
all_pins[1]	transitions[0x0=>0x1]	985	1		T30	12		T7	1		T32	1
all_pins[1]	transitions[0x1=>0x0]	124	1		T43	1		T46	1		T47	1
all_pins[2]	values[0x0]	168054	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	137	1		T43	1		T46	1		T47	1
all_pins[2]	transitions[0x0=>0x1]	111	1		T43	1		T46	1		T47	1
all_pins[2]	transitions[0x1=>0x0]	36	1		T68	1		T223	3		T229	1
all_pins[3]	values[0x0]	168129	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	62	1		T68	1		T223	3		T229	1
all_pins[3]	transitions[0x0=>0x1]	42	1		T68	1		T229	1		T228	1
all_pins[3]	transitions[0x1=>0x0]	56	1		T69	1		T227	1		T225	1
all_pins[4]	values[0x0]	168115	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	76	1		T69	1		T223	3		T227	1
all_pins[4]	transitions[0x0=>0x1]	63	1		T69	1		T223	2		T227	1
all_pins[4]	transitions[0x1=>0x0]	59	1		T226	2		T229	1		T228	2
all_pins[5]	values[0x0]	168119	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	72	1		T223	1		T226	3		T229	1
all_pins[5]	transitions[0x0=>0x1]	51	1		T226	1		T309	2		T312	1
all_pins[5]	transitions[0x1=>0x0]	49	1		T224	2		T227	1		T311	2
all_pins[6]	values[0x0]	168121	1		T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	70	1		T223	1		T224	2		T227	1
all_pins[6]	transitions[0x0=>0x1]	53	1		T223	1		T224	1		T311	1
all_pins[6]	transitions[0x1=>0x0]	54	1		T54	1		T55	1		T56	1
all_pins[7]	values[0x0]	168120	1		T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	71	1		T54	1		T55	1		T56	1
all_pins[7]	transitions[0x0=>0x1]	52	1		T54	1		T55	1		T56	1
all_pins[7]	transitions[0x1=>0x0]	44	1		T57	1		T223	1		T227	1
all_pins[8]	values[0x0]	168128	1		T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	63	1		T57	1		T223	2		T227	1
all_pins[8]	transitions[0x0=>0x1]	43	1		T57	1		T223	1		T227	1
all_pins[8]	transitions[0x1=>0x0]	58	1		T50	2		T66	2		T67	2
all_pins[9]	values[0x0]	168113	1		T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	78	1		T50	2		T66	2		T67	2
all_pins[9]	transitions[0x0=>0x1]	64	1		T50	2		T66	2		T67	2
all_pins[9]	transitions[0x1=>0x0]	44	1		T223	1		T227	1		T311	2
all_pins[10]	values[0x0]	168133	1		T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	58	1		T223	3		T224	2		T227	1
all_pins[10]	transitions[0x0=>0x1]	40	1		T223	1		T224	2		T227	1
all_pins[10]	transitions[0x1=>0x0]	100	1		T1	1		T36	1		T73	1
all_pins[11]	values[0x0]	168073	1		T1	1		T2	2		T3	2
all_pins[11]	values[0x1]	118	1		T1	1		T36	1		T73	1
all_pins[11]	transitions[0x0=>0x1]	97	1		T1	1		T36	1		T73	1
all_pins[11]	transitions[0x1=>0x0]	57	1		T74	1		T76	1		T77	1
all_pins[12]	values[0x0]	168113	1		T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	78	1		T74	1		T76	1		T77	1
all_pins[12]	transitions[0x0=>0x1]	58	1		T74	1		T76	1		T77	1
all_pins[12]	transitions[0x1=>0x0]	45	1		T226	1		T312	2		T310	1
all_pins[13]	values[0x0]	168126	1		T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	65	1		T225	1		T226	1		T228	2
all_pins[13]	transitions[0x0=>0x1]	47	1		T225	1		T226	1		T312	5
all_pins[13]	transitions[0x1=>0x0]	51	1		T223	4		T225	2		T229	2
all_pins[14]	values[0x0]	168122	1		T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	69	1		T223	4		T225	2		T229	2
all_pins[14]	transitions[0x0=>0x1]	54	1		T225	1		T229	2		T228	1
all_pins[14]	transitions[0x1=>0x0]	47	1		T224	1		T225	1		T226	2
all_pins[15]	values[0x0]	168129	1		T1	2		T2	2		T3	2
all_pins[15]	values[0x1]	62	1		T223	4		T224	1		T225	2
all_pins[15]	transitions[0x0=>0x1]	39	1		T223	3		T224	1		T225	1
all_pins[15]	transitions[0x1=>0x0]	52	1		T70	4		T71	4		T72	4
all_pins[16]	values[0x0]	168116	1		T1	2		T2	2		T3	2
all_pins[16]	values[0x1]	75	1		T70	4		T71	4		T72	4
all_pins[16]	transitions[0x0=>0x1]	57	1		T70	4		T71	4		T72	4
all_pins[16]	transitions[0x1=>0x0]	47	1		T61	1		T224	1		T311	1
all_pins[17]	values[0x0]	168126	1		T1	2		T2	2		T3	2
all_pins[17]	values[0x1]	65	1		T61	1		T223	1		T224	1
all_pins[17]	transitions[0x0=>0x1]	33	1		T61	1		T226	2		T308	1
all_pins[17]	transitions[0x1=>0x0]	97	1		T18	1		T52	1		T315	1