Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00
Crosses 108 0 108 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 18 0 18 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 108 0 108 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 18 0 18 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 275 1 T223 4 T224 4 T227 4
all_values[1] 275 1 T223 4 T224 4 T227 4
all_values[2] 275 1 T223 4 T224 4 T227 4
all_values[3] 275 1 T223 4 T224 4 T227 4
all_values[4] 275 1 T223 4 T224 4 T227 4
all_values[5] 275 1 T223 4 T224 4 T227 4
all_values[6] 275 1 T223 4 T224 4 T227 4
all_values[7] 275 1 T223 4 T224 4 T227 4
all_values[8] 275 1 T223 4 T224 4 T227 4
all_values[9] 275 1 T223 4 T224 4 T227 4
all_values[10] 275 1 T223 4 T224 4 T227 4
all_values[11] 275 1 T223 4 T224 4 T227 4
all_values[12] 275 1 T223 4 T224 4 T227 4
all_values[13] 275 1 T223 4 T224 4 T227 4
all_values[14] 275 1 T223 4 T224 4 T227 4
all_values[15] 275 1 T223 4 T224 4 T227 4
all_values[16] 275 1 T223 4 T224 4 T227 4
all_values[17] 275 1 T223 4 T224 4 T227 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2711 1 T223 36 T224 32 T227 35
auto[1] 2239 1 T223 36 T224 40 T227 37



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 881 1 T223 12 T224 31 T227 21
auto[1] 4069 1 T223 60 T224 41 T227 51



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2873 1 T223 38 T224 51 T227 46
auto[1] 2077 1 T223 34 T224 21 T227 26



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 108 0 108 100.00
Automatically Generated Cross Bins 108 0 108 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 29 1 T308 2 T309 2 T316 3
all_values[0] auto[0] auto[0] auto[1] 61 1 T227 1 T225 2 T226 1
all_values[0] auto[0] auto[1] auto[0] 16 1 T308 2 T317 2 T318 1
all_values[0] auto[0] auto[1] auto[1] 56 1 T223 1 T224 2 T227 1
all_values[0] auto[1] auto[0] auto[1] 61 1 T223 1 T224 1 T227 1
all_values[0] auto[1] auto[1] auto[1] 52 1 T223 2 T224 1 T227 1
all_values[1] auto[0] auto[0] auto[0] 45 1 T223 1 T224 1 T225 2
all_values[1] auto[0] auto[0] auto[1] 46 1 T227 1 T311 2 T229 2
all_values[1] auto[0] auto[1] auto[0] 24 1 T225 1 T226 2 T308 1
all_values[1] auto[0] auto[1] auto[1] 56 1 T223 1 T224 1 T227 1
all_values[1] auto[1] auto[0] auto[1] 62 1 T223 1 T224 1 T229 1
all_values[1] auto[1] auto[1] auto[1] 42 1 T223 1 T224 1 T227 2
all_values[2] auto[0] auto[0] auto[0] 25 1 T225 2 T308 1 T314 1
all_values[2] auto[0] auto[0] auto[1] 56 1 T223 1 T224 1 T311 1
all_values[2] auto[0] auto[1] auto[0] 9 1 T227 1 T225 1 T314 1
all_values[2] auto[0] auto[1] auto[1] 55 1 T223 1 T224 1 T227 1
all_values[2] auto[1] auto[0] auto[1] 81 1 T223 1 T224 1 T227 2
all_values[2] auto[1] auto[1] auto[1] 49 1 T223 1 T224 1 T229 1
all_values[3] auto[0] auto[0] auto[0] 28 1 T224 1 T227 2 T311 2
all_values[3] auto[0] auto[0] auto[1] 79 1 T224 1 T226 2 T229 1
all_values[3] auto[0] auto[1] auto[0] 15 1 T224 1 T227 2 T311 2
all_values[3] auto[0] auto[1] auto[1] 48 1 T223 2 T308 1 T309 1
all_values[3] auto[1] auto[0] auto[1] 55 1 T223 2 T224 1 T229 2
all_values[3] auto[1] auto[1] auto[1] 50 1 T226 1 T229 1 T228 1
all_values[4] auto[0] auto[0] auto[0] 27 1 T223 1 T224 1 T311 2
all_values[4] auto[0] auto[0] auto[1] 52 1 T225 2 T226 2 T229 1
all_values[4] auto[0] auto[1] auto[0] 28 1 T224 3 T311 2 T314 3
all_values[4] auto[0] auto[1] auto[1] 45 1 T223 1 T227 2 T226 1
all_values[4] auto[1] auto[0] auto[1] 61 1 T227 1 T225 2 T229 2
all_values[4] auto[1] auto[1] auto[1] 62 1 T223 2 T227 1 T225 2
all_values[5] auto[0] auto[0] auto[0] 29 1 T223 1 T224 2 T311 1
all_values[5] auto[0] auto[0] auto[1] 46 1 T223 1 T227 1 T311 2
all_values[5] auto[0] auto[1] auto[0] 17 1 T224 2 T227 1 T226 1
all_values[5] auto[0] auto[1] auto[1] 59 1 T227 1 T225 2 T226 1
all_values[5] auto[1] auto[0] auto[1] 73 1 T311 1 T225 3 T229 1
all_values[5] auto[1] auto[1] auto[1] 51 1 T223 2 T227 1 T226 2
all_values[6] auto[0] auto[0] auto[0] 29 1 T229 1 T309 1 T312 1
all_values[6] auto[0] auto[0] auto[1] 51 1 T223 1 T224 1 T227 2
all_values[6] auto[0] auto[1] auto[0] 11 1 T313 1 T319 1 T320 2
all_values[6] auto[0] auto[1] auto[1] 62 1 T224 1 T227 1 T225 1
all_values[6] auto[1] auto[0] auto[1] 68 1 T223 2 T224 1 T311 1
all_values[6] auto[1] auto[1] auto[1] 54 1 T223 1 T224 1 T227 1
all_values[7] auto[0] auto[0] auto[0] 26 1 T223 1 T311 1 T225 2
all_values[7] auto[0] auto[0] auto[1] 55 1 T227 1 T228 2 T308 1
all_values[7] auto[0] auto[1] auto[0] 11 1 T223 1 T229 1 T321 1
all_values[7] auto[0] auto[1] auto[1] 62 1 T223 1 T224 1 T227 2
all_values[7] auto[1] auto[0] auto[1] 60 1 T311 1 T226 1 T228 1
all_values[7] auto[1] auto[1] auto[1] 61 1 T223 1 T224 3 T227 1
all_values[8] auto[0] auto[0] auto[0] 29 1 T224 1 T226 2 T228 1
all_values[8] auto[0] auto[0] auto[1] 41 1 T224 1 T225 1 T226 1
all_values[8] auto[0] auto[1] auto[0] 18 1 T224 1 T308 2 T314 3
all_values[8] auto[0] auto[1] auto[1] 69 1 T223 1 T227 2 T311 2
all_values[8] auto[1] auto[0] auto[1] 62 1 T223 2 T224 1 T227 1
all_values[8] auto[1] auto[1] auto[1] 56 1 T223 1 T227 1 T311 2
all_values[9] auto[0] auto[0] auto[0] 40 1 T223 1 T229 1 T314 4
all_values[9] auto[0] auto[0] auto[1] 63 1 T223 1 T311 2 T225 3
all_values[9] auto[0] auto[1] auto[0] 15 1 T227 1 T229 1 T321 1
all_values[9] auto[0] auto[1] auto[1] 43 1 T223 1 T224 3 T227 1
all_values[9] auto[1] auto[0] auto[1] 60 1 T223 1 T224 1 T227 2
all_values[9] auto[1] auto[1] auto[1] 54 1 T311 2 T226 2 T312 1
all_values[10] auto[0] auto[0] auto[0] 35 1 T224 1 T311 2 T228 2
all_values[10] auto[0] auto[0] auto[1] 56 1 T227 3 T225 2 T226 2
all_values[10] auto[0] auto[1] auto[0] 20 1 T314 1 T312 1 T321 2
all_values[10] auto[0] auto[1] auto[1] 55 1 T223 1 T224 1 T311 1
all_values[10] auto[1] auto[0] auto[1] 59 1 T223 2 T225 3 T226 2
all_values[10] auto[1] auto[1] auto[1] 50 1 T223 1 T224 2 T227 1
all_values[11] auto[0] auto[0] auto[0] 35 1 T224 1 T225 2 T226 2
all_values[11] auto[0] auto[0] auto[1] 60 1 T223 1 T227 1 T311 1
all_values[11] auto[0] auto[1] auto[0] 21 1 T224 3 T225 1 T314 1
all_values[11] auto[0] auto[1] auto[1] 58 1 T223 1 T311 1 T225 3
all_values[11] auto[1] auto[0] auto[1] 47 1 T223 2 T227 3 T311 1
all_values[11] auto[1] auto[1] auto[1] 54 1 T311 1 T225 1 T226 1
all_values[12] auto[0] auto[0] auto[0] 24 1 T223 2 T227 1 T316 1
all_values[12] auto[0] auto[0] auto[1] 58 1 T224 1 T225 2 T226 2
all_values[12] auto[0] auto[1] auto[0] 31 1 T223 2 T224 2 T227 3
all_values[12] auto[0] auto[1] auto[1] 46 1 T311 2 T225 1 T229 1
all_values[12] auto[1] auto[0] auto[1] 70 1 T224 1 T225 2 T229 2
all_values[12] auto[1] auto[1] auto[1] 46 1 T311 1 T225 2 T226 1
all_values[13] auto[0] auto[0] auto[0] 24 1 T223 1 T224 1 T227 1
all_values[13] auto[0] auto[0] auto[1] 56 1 T223 2 T311 3 T225 2
all_values[13] auto[0] auto[1] auto[0] 19 1 T224 3 T227 3 T226 1
all_values[13] auto[0] auto[1] auto[1] 57 1 T225 2 T226 2 T308 1
all_values[13] auto[1] auto[0] auto[1] 73 1 T223 1 T311 1 T225 2
all_values[13] auto[1] auto[1] auto[1] 46 1 T225 1 T226 1 T228 1
all_values[14] auto[0] auto[0] auto[0] 34 1 T224 4 T227 1 T226 1
all_values[14] auto[0] auto[0] auto[1] 53 1 T311 1 T225 1 T228 1
all_values[14] auto[0] auto[1] auto[0] 20 1 T227 3 T317 2 T322 3
all_values[14] auto[0] auto[1] auto[1] 64 1 T223 2 T225 4 T226 2
all_values[14] auto[1] auto[0] auto[1] 54 1 T223 1 T311 3 T225 1
all_values[14] auto[1] auto[1] auto[1] 50 1 T223 1 T225 1 T229 1
all_values[15] auto[0] auto[0] auto[0] 33 1 T227 1 T311 1 T229 1
all_values[15] auto[0] auto[0] auto[1] 54 1 T224 2 T227 1 T311 1
all_values[15] auto[0] auto[1] auto[0] 15 1 T224 1 T226 1 T229 3
all_values[15] auto[0] auto[1] auto[1] 54 1 T223 2 T225 2 T226 1
all_values[15] auto[1] auto[0] auto[1] 78 1 T223 1 T227 2 T311 2
all_values[15] auto[1] auto[1] auto[1] 41 1 T223 1 T224 1 T225 2
all_values[16] auto[0] auto[0] auto[0] 33 1 T226 1 T229 2 T314 2
all_values[16] auto[0] auto[0] auto[1] 59 1 T223 2 T224 2 T311 1
all_values[16] auto[0] auto[1] auto[0] 18 1 T224 1 T311 1 T308 2
all_values[16] auto[0] auto[1] auto[1] 49 1 T227 1 T225 1 T226 2
all_values[16] auto[1] auto[0] auto[1] 73 1 T223 1 T224 1 T227 2
all_values[16] auto[1] auto[1] auto[1] 43 1 T223 1 T227 1 T311 1
all_values[17] auto[0] auto[0] auto[0] 32 1 T223 1 T227 1 T225 1
all_values[17] auto[0] auto[0] auto[1] 48 1 T227 1 T311 1 T225 3
all_values[17] auto[0] auto[1] auto[0] 16 1 T224 1 T229 2 T310 2
all_values[17] auto[0] auto[1] auto[1] 60 1 T223 2 T224 1 T225 2
all_values[17] auto[1] auto[0] auto[1] 63 1 T224 1 T227 2 T311 3
all_values[17] auto[1] auto[1] auto[1] 56 1 T223 1 T224 1 T225 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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