Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.59 97.84 93.81 97.44 75.00 96.26 98.17 96.58


Total test records in report: 2810
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T2755 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1723105682 Jul 02 08:07:15 AM PDT 24 Jul 02 08:07:22 AM PDT 24 34475763 ps
T2756 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.848493786 Jul 02 08:06:52 AM PDT 24 Jul 02 08:06:57 AM PDT 24 140665350 ps
T2757 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2730369531 Jul 02 08:06:39 AM PDT 24 Jul 02 08:06:50 AM PDT 24 1521170157 ps
T2758 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1290713084 Jul 02 08:07:01 AM PDT 24 Jul 02 08:07:10 AM PDT 24 515283215 ps
T2759 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2998297141 Jul 02 08:06:59 AM PDT 24 Jul 02 08:07:06 AM PDT 24 119737685 ps
T2760 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1395949268 Jul 02 08:07:10 AM PDT 24 Jul 02 08:07:18 AM PDT 24 39343180 ps
T2761 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1962475574 Jul 02 08:06:59 AM PDT 24 Jul 02 08:07:06 AM PDT 24 287468811 ps
T327 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.217311026 Jul 02 08:06:40 AM PDT 24 Jul 02 08:06:48 AM PDT 24 745866970 ps
T2762 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4271545300 Jul 02 08:07:06 AM PDT 24 Jul 02 08:07:14 AM PDT 24 81916698 ps
T2763 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3181493103 Jul 02 08:06:39 AM PDT 24 Jul 02 08:06:43 AM PDT 24 48107084 ps
T2764 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3197225976 Jul 02 08:06:43 AM PDT 24 Jul 02 08:06:50 AM PDT 24 299620923 ps
T2765 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3097895919 Jul 02 08:07:07 AM PDT 24 Jul 02 08:07:14 AM PDT 24 178499156 ps
T2766 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1585978211 Jul 02 08:06:51 AM PDT 24 Jul 02 08:06:58 AM PDT 24 413933481 ps
T320 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2074280454 Jul 02 08:07:13 AM PDT 24 Jul 02 08:07:21 AM PDT 24 52859250 ps
T2767 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2172774232 Jul 02 08:06:50 AM PDT 24 Jul 02 08:06:55 AM PDT 24 42673508 ps
T2768 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1541026235 Jul 02 08:07:01 AM PDT 24 Jul 02 08:07:08 AM PDT 24 55478678 ps
T2769 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1810477009 Jul 02 08:07:12 AM PDT 24 Jul 02 08:07:19 AM PDT 24 36841850 ps
T2770 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1291233005 Jul 02 08:06:53 AM PDT 24 Jul 02 08:06:58 AM PDT 24 78744405 ps
T324 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1663274569 Jul 02 08:07:01 AM PDT 24 Jul 02 08:07:10 AM PDT 24 967870368 ps
T2771 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3732924501 Jul 02 08:06:58 AM PDT 24 Jul 02 08:07:03 AM PDT 24 46924827 ps
T2772 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2515637886 Jul 02 08:07:16 AM PDT 24 Jul 02 08:07:23 AM PDT 24 55588501 ps
T2773 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1104387427 Jul 02 08:06:46 AM PDT 24 Jul 02 08:06:50 AM PDT 24 125388810 ps
T2774 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3085569303 Jul 02 08:07:06 AM PDT 24 Jul 02 08:07:13 AM PDT 24 52464331 ps
T2775 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.344418900 Jul 02 08:07:06 AM PDT 24 Jul 02 08:07:13 AM PDT 24 36914214 ps
T2776 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2074183389 Jul 02 08:07:01 AM PDT 24 Jul 02 08:07:08 AM PDT 24 92468497 ps
T2777 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4184676871 Jul 02 08:06:41 AM PDT 24 Jul 02 08:06:48 AM PDT 24 377114241 ps
T2778 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1105245435 Jul 02 08:06:39 AM PDT 24 Jul 02 08:06:47 AM PDT 24 484010837 ps
T2779 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.464966567 Jul 02 08:07:02 AM PDT 24 Jul 02 08:07:08 AM PDT 24 39539903 ps
T2780 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3326893892 Jul 02 08:06:51 AM PDT 24 Jul 02 08:06:57 AM PDT 24 210716442 ps
T2781 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2326575693 Jul 02 08:06:45 AM PDT 24 Jul 02 08:06:49 AM PDT 24 63658179 ps
T2782 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.402573881 Jul 02 08:07:11 AM PDT 24 Jul 02 08:07:19 AM PDT 24 85714567 ps
T2783 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.855746939 Jul 02 08:06:58 AM PDT 24 Jul 02 08:07:03 AM PDT 24 80545883 ps
T262 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2133641789 Jul 02 08:06:46 AM PDT 24 Jul 02 08:06:52 AM PDT 24 606482371 ps
T2784 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1902615923 Jul 02 08:06:58 AM PDT 24 Jul 02 08:07:02 AM PDT 24 126960387 ps
T2785 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3733906467 Jul 02 08:07:11 AM PDT 24 Jul 02 08:07:18 AM PDT 24 57970407 ps
T2786 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4288753779 Jul 02 08:07:01 AM PDT 24 Jul 02 08:07:06 AM PDT 24 59403385 ps
T2787 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2230533548 Jul 02 08:07:01 AM PDT 24 Jul 02 08:07:08 AM PDT 24 87834064 ps
T2788 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1744029071 Jul 02 08:07:16 AM PDT 24 Jul 02 08:07:23 AM PDT 24 121297630 ps
T2789 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4081038355 Jul 02 08:06:50 AM PDT 24 Jul 02 08:06:56 AM PDT 24 227192100 ps
T2790 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3643034521 Jul 02 08:06:45 AM PDT 24 Jul 02 08:06:48 AM PDT 24 52516478 ps
T2791 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2046483122 Jul 02 08:06:52 AM PDT 24 Jul 02 08:06:57 AM PDT 24 85512970 ps
T2792 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1860824186 Jul 02 08:07:08 AM PDT 24 Jul 02 08:07:18 AM PDT 24 786271975 ps
T2793 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.435141246 Jul 02 08:07:08 AM PDT 24 Jul 02 08:07:14 AM PDT 24 80816012 ps
T2794 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.444549939 Jul 02 08:07:00 AM PDT 24 Jul 02 08:07:06 AM PDT 24 129140308 ps
T2795 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1040358235 Jul 02 08:07:02 AM PDT 24 Jul 02 08:07:11 AM PDT 24 335728372 ps
T2796 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.631492088 Jul 02 08:07:09 AM PDT 24 Jul 02 08:07:16 AM PDT 24 52428300 ps
T2797 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2652513229 Jul 02 08:06:44 AM PDT 24 Jul 02 08:06:47 AM PDT 24 110835853 ps
T2798 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1599795418 Jul 02 08:07:14 AM PDT 24 Jul 02 08:07:22 AM PDT 24 39315739 ps
T2799 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1262853003 Jul 02 08:06:46 AM PDT 24 Jul 02 08:06:52 AM PDT 24 987765518 ps
T2800 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3992249711 Jul 02 08:06:50 AM PDT 24 Jul 02 08:06:56 AM PDT 24 226100610 ps
T2801 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3149964159 Jul 02 08:06:51 AM PDT 24 Jul 02 08:06:55 AM PDT 24 69640365 ps
T2802 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4224212504 Jul 02 08:07:10 AM PDT 24 Jul 02 08:07:18 AM PDT 24 123878753 ps
T2803 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3659726827 Jul 02 08:06:40 AM PDT 24 Jul 02 08:06:46 AM PDT 24 139609381 ps
T2804 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1498687992 Jul 02 08:07:13 AM PDT 24 Jul 02 08:07:21 AM PDT 24 57366381 ps
T2805 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3499845293 Jul 02 08:06:52 AM PDT 24 Jul 02 08:07:02 AM PDT 24 1103950711 ps
T2806 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2782031313 Jul 02 08:07:04 AM PDT 24 Jul 02 08:07:10 AM PDT 24 111013784 ps
T2807 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1390648614 Jul 02 08:06:42 AM PDT 24 Jul 02 08:06:48 AM PDT 24 274185204 ps
T2808 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1380369949 Jul 02 08:06:40 AM PDT 24 Jul 02 08:06:45 AM PDT 24 115942505 ps
T2809 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3403311299 Jul 02 08:07:01 AM PDT 24 Jul 02 08:07:09 AM PDT 24 130252690 ps
T2810 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3620111364 Jul 02 08:07:00 AM PDT 24 Jul 02 08:07:06 AM PDT 24 43663702 ps

Test location /workspace/coverage/default/36.usbdev_endpoint_access.1985376519
Short name T30
Test name
Test status
Simulation time 1008627626 ps
CPU time 2.3 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:11:21 AM PDT 24
Peak memory 206320 kb
Host smart-22758fd4-4889-4fe5-bb08-2fd937b23f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19853
76519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.1985376519
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2740749258
Short name T5
Test name
Test status
Simulation time 7546275697 ps
CPU time 34.8 seconds
Started Jul 02 09:06:36 AM PDT 24
Finished Jul 02 09:07:13 AM PDT 24
Peak memory 206492 kb
Host smart-92965513-6245-4816-b9a6-78164ca9be87
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2740749258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2740749258
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2128789322
Short name T225
Test name
Test status
Simulation time 58484453 ps
CPU time 0.7 seconds
Started Jul 02 08:07:08 AM PDT 24
Finished Jul 02 08:07:14 AM PDT 24
Peak memory 205784 kb
Host smart-4eae6e16-cce4-4ccc-be38-168845a5eb7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2128789322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2128789322
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3204808828
Short name T213
Test name
Test status
Simulation time 106908078 ps
CPU time 1.26 seconds
Started Jul 02 08:07:00 AM PDT 24
Finished Jul 02 08:07:05 AM PDT 24
Peak memory 214184 kb
Host smart-3ccfeada-69dd-41b0-b5ab-ed8c35acc42f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204808828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3204808828
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2421300362
Short name T12
Test name
Test status
Simulation time 4025038456 ps
CPU time 5.28 seconds
Started Jul 02 09:11:27 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206436 kb
Host smart-e1f4b348-2379-4acc-818f-0d0ae17e7047
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2421300362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2421300362
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2279639394
Short name T312
Test name
Test status
Simulation time 63158198 ps
CPU time 0.71 seconds
Started Jul 02 08:07:10 AM PDT 24
Finished Jul 02 08:07:17 AM PDT 24
Peak memory 205792 kb
Host smart-72de728a-ba4b-4fa7-926a-c593eb86f4d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2279639394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2279639394
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/default/15.usbdev_device_address.2221094313
Short name T95
Test name
Test status
Simulation time 20392242865 ps
CPU time 39.87 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:09:06 AM PDT 24
Peak memory 206480 kb
Host smart-3b805045-cfbd-48a7-8807-f8cbf554ca03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22210
94313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2221094313
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2130786864
Short name T35
Test name
Test status
Simulation time 181518580 ps
CPU time 0.8 seconds
Started Jul 02 09:07:12 AM PDT 24
Finished Jul 02 09:07:14 AM PDT 24
Peak memory 206200 kb
Host smart-93c022b3-9b44-4177-9353-0da1eb239e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21307
86864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2130786864
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2786215770
Short name T48
Test name
Test status
Simulation time 12090165220 ps
CPU time 65.94 seconds
Started Jul 02 09:06:34 AM PDT 24
Finished Jul 02 09:07:42 AM PDT 24
Peak memory 206424 kb
Host smart-3c188ddd-a324-41c5-ad89-cfbc0377352d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2786215770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2786215770
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2871370102
Short name T210
Test name
Test status
Simulation time 581441782 ps
CPU time 1.33 seconds
Started Jul 02 09:06:50 AM PDT 24
Finished Jul 02 09:06:53 AM PDT 24
Peak memory 224048 kb
Host smart-afadaae1-980b-4acb-ab86-e74e96f4706e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2871370102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2871370102
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.99238217
Short name T515
Test name
Test status
Simulation time 153492975 ps
CPU time 0.77 seconds
Started Jul 02 09:06:16 AM PDT 24
Finished Jul 02 09:06:18 AM PDT 24
Peak memory 206200 kb
Host smart-851895b9-b2b8-4474-acf4-91d33c339088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99238
217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.99238217
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.2219338407
Short name T47
Test name
Test status
Simulation time 140765146 ps
CPU time 0.8 seconds
Started Jul 02 09:09:48 AM PDT 24
Finished Jul 02 09:09:52 AM PDT 24
Peak memory 206140 kb
Host smart-8202eeb5-324d-4cf3-ac8f-47cf574e98dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22193
38407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.2219338407
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.846076766
Short name T268
Test name
Test status
Simulation time 719438277 ps
CPU time 4.26 seconds
Started Jul 02 08:06:38 AM PDT 24
Finished Jul 02 08:06:46 AM PDT 24
Peak memory 205964 kb
Host smart-d5656e8d-8c63-4da6-9bc1-bf3161d7ab5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=846076766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.846076766
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1239919890
Short name T115
Test name
Test status
Simulation time 234491256 ps
CPU time 0.96 seconds
Started Jul 02 09:13:07 AM PDT 24
Finished Jul 02 09:13:11 AM PDT 24
Peak memory 206212 kb
Host smart-87daa541-d8e9-4b8a-89cf-0d9883effd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12399
19890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1239919890
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.541136987
Short name T186
Test name
Test status
Simulation time 386581467 ps
CPU time 1.25 seconds
Started Jul 02 09:10:43 AM PDT 24
Finished Jul 02 09:10:45 AM PDT 24
Peak memory 206212 kb
Host smart-52278e51-7b51-4c3f-aaf3-9b2cb9388d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54113
6987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.541136987
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1914766388
Short name T25
Test name
Test status
Simulation time 35926871 ps
CPU time 0.68 seconds
Started Jul 02 09:08:28 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206176 kb
Host smart-3a3ae516-bc79-44de-b480-d413ca1e923c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19147
66388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1914766388
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3299571296
Short name T224
Test name
Test status
Simulation time 33368299 ps
CPU time 0.71 seconds
Started Jul 02 08:07:12 AM PDT 24
Finished Jul 02 08:07:20 AM PDT 24
Peak memory 205744 kb
Host smart-3abf6fd8-933b-4c31-bfd4-f737acd224fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3299571296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3299571296
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3339962193
Short name T79
Test name
Test status
Simulation time 296662762 ps
CPU time 0.96 seconds
Started Jul 02 09:05:59 AM PDT 24
Finished Jul 02 09:06:02 AM PDT 24
Peak memory 206176 kb
Host smart-94c9d957-53b5-4b52-970d-71a03f3efc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33399
62193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3339962193
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2706690528
Short name T49
Test name
Test status
Simulation time 20198261981 ps
CPU time 21.99 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:27 AM PDT 24
Peak memory 206172 kb
Host smart-e96e1fb1-545c-491c-a4fa-bd091c4f449c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27066
90528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2706690528
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2588912767
Short name T45
Test name
Test status
Simulation time 13654892940 ps
CPU time 353.75 seconds
Started Jul 02 09:06:46 AM PDT 24
Finished Jul 02 09:12:42 AM PDT 24
Peak memory 206544 kb
Host smart-7f611aef-1d3f-4ff3-8bbf-d779e4926bb1
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2588912767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2588912767
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.368647314
Short name T259
Test name
Test status
Simulation time 269523331 ps
CPU time 2.88 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 222472 kb
Host smart-3464f533-a71c-4711-b7ba-a874012780ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=368647314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.368647314
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4220250516
Short name T282
Test name
Test status
Simulation time 60293057 ps
CPU time 0.96 seconds
Started Jul 02 08:07:09 AM PDT 24
Finished Jul 02 08:07:16 AM PDT 24
Peak memory 205952 kb
Host smart-a4ede6c9-c0c4-48a6-a7bd-78a763e39f56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4220250516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4220250516
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3180072840
Short name T317
Test name
Test status
Simulation time 64984317 ps
CPU time 0.76 seconds
Started Jul 02 08:07:08 AM PDT 24
Finished Jul 02 08:07:15 AM PDT 24
Peak memory 205772 kb
Host smart-23c1851c-9d3e-41c3-9a70-30f8950a8a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3180072840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3180072840
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.339159821
Short name T62
Test name
Test status
Simulation time 1496516988 ps
CPU time 3.02 seconds
Started Jul 02 09:10:48 AM PDT 24
Finished Jul 02 09:10:53 AM PDT 24
Peak memory 206412 kb
Host smart-1614858d-11e9-4900-abc8-b269cb639af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33915
9821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.339159821
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3656576710
Short name T36
Test name
Test status
Simulation time 184980157 ps
CPU time 0.81 seconds
Started Jul 02 09:09:26 AM PDT 24
Finished Jul 02 09:09:28 AM PDT 24
Peak memory 206200 kb
Host smart-95d82f1a-941f-4324-ad1d-081a733be555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36565
76710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3656576710
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.36020446
Short name T315
Test name
Test status
Simulation time 199963473 ps
CPU time 0.83 seconds
Started Jul 02 09:06:12 AM PDT 24
Finished Jul 02 09:06:15 AM PDT 24
Peak memory 206208 kb
Host smart-fce9d049-a93e-4828-9a49-68d62b03550d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36020
446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.36020446
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3881049371
Short name T216
Test name
Test status
Simulation time 23384702988 ps
CPU time 23.09 seconds
Started Jul 02 09:08:25 AM PDT 24
Finished Jul 02 09:08:52 AM PDT 24
Peak memory 206204 kb
Host smart-f9fb278d-b664-4c23-8a1a-41bbd9327bd8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3881049371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3881049371
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1604123162
Short name T321
Test name
Test status
Simulation time 37941237 ps
CPU time 0.7 seconds
Started Jul 02 08:07:07 AM PDT 24
Finished Jul 02 08:07:13 AM PDT 24
Peak memory 205776 kb
Host smart-40a32e20-d818-4f4a-95fc-539b26e57af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1604123162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1604123162
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1290713084
Short name T2758
Test name
Test status
Simulation time 515283215 ps
CPU time 4.21 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:10 AM PDT 24
Peak memory 205940 kb
Host smart-e0e030f4-a698-4b33-95f2-d4bc82ee90eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1290713084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1290713084
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2661482691
Short name T72
Test name
Test status
Simulation time 480278634 ps
CPU time 1.38 seconds
Started Jul 02 09:05:58 AM PDT 24
Finished Jul 02 09:06:02 AM PDT 24
Peak memory 206160 kb
Host smart-aedc2bd5-c5a0-4c49-8306-cea456050b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26614
82691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2661482691
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.804384679
Short name T319
Test name
Test status
Simulation time 55931144 ps
CPU time 0.67 seconds
Started Jul 02 08:07:13 AM PDT 24
Finished Jul 02 08:07:21 AM PDT 24
Peak memory 205784 kb
Host smart-86b32c0b-a85c-40f4-b7f0-f28b20394d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=804384679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.804384679
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.4218167838
Short name T476
Test name
Test status
Simulation time 69840444 ps
CPU time 0.73 seconds
Started Jul 02 09:06:08 AM PDT 24
Finished Jul 02 09:06:12 AM PDT 24
Peak memory 206200 kb
Host smart-b9f9ad6f-0764-480b-9ef3-6797035927cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4218167838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.4218167838
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.935515431
Short name T217
Test name
Test status
Simulation time 13348906684 ps
CPU time 12.06 seconds
Started Jul 02 09:06:49 AM PDT 24
Finished Jul 02 09:07:03 AM PDT 24
Peak memory 206500 kb
Host smart-18100b35-6394-438a-af6f-60a05d40216a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=935515431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.935515431
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.2994827651
Short name T57
Test name
Test status
Simulation time 332340632 ps
CPU time 1.18 seconds
Started Jul 02 09:06:12 AM PDT 24
Finished Jul 02 09:06:15 AM PDT 24
Peak memory 206212 kb
Host smart-13e5f295-b073-448e-8a76-4b9a5ce58478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29948
27651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2994827651
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2217022028
Short name T214
Test name
Test status
Simulation time 552415570 ps
CPU time 2.7 seconds
Started Jul 02 08:07:11 AM PDT 24
Finished Jul 02 08:07:20 AM PDT 24
Peak memory 205880 kb
Host smart-41b5f273-5e5d-4d83-b131-87f26dea01df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2217022028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2217022028
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.2667064177
Short name T90
Test name
Test status
Simulation time 191542439 ps
CPU time 0.82 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 206120 kb
Host smart-bbe3f068-e668-4829-8419-fe3a5e4d6e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26670
64177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.2667064177
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.4220608168
Short name T188
Test name
Test status
Simulation time 5532605988 ps
CPU time 41.92 seconds
Started Jul 02 09:06:11 AM PDT 24
Finished Jul 02 09:06:55 AM PDT 24
Peak memory 206384 kb
Host smart-66eb6930-456f-42af-bf50-89856def5bee
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4220608168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.4220608168
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2909596893
Short name T325
Test name
Test status
Simulation time 1001306953 ps
CPU time 5.15 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:07:00 AM PDT 24
Peak memory 206012 kb
Host smart-136cbdb8-8d18-43a2-86fb-99ff409bffa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2909596893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2909596893
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3198019271
Short name T323
Test name
Test status
Simulation time 579425342 ps
CPU time 4.6 seconds
Started Jul 02 08:06:58 AM PDT 24
Finished Jul 02 08:07:06 AM PDT 24
Peak memory 205988 kb
Host smart-19d9e32f-c701-42dd-8ea6-56dd6856cf42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3198019271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3198019271
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2950825447
Short name T98
Test name
Test status
Simulation time 20585797264 ps
CPU time 39.36 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:52 AM PDT 24
Peak memory 206444 kb
Host smart-111e3919-843e-4152-ab1d-83fc53dff010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29508
25447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2950825447
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.76585500
Short name T261
Test name
Test status
Simulation time 74349775 ps
CPU time 1.91 seconds
Started Jul 02 08:06:49 AM PDT 24
Finished Jul 02 08:06:53 AM PDT 24
Peak memory 222268 kb
Host smart-039ca705-64c3-45a4-ae14-00d5246520a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=76585500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.76585500
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1706608495
Short name T160
Test name
Test status
Simulation time 3496881263 ps
CPU time 95.15 seconds
Started Jul 02 09:13:14 AM PDT 24
Finished Jul 02 09:14:54 AM PDT 24
Peak memory 206472 kb
Host smart-d2747bcc-3b54-4a70-88c3-b6884f992825
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1706608495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1706608495
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.3559949558
Short name T175
Test name
Test status
Simulation time 13042411758 ps
CPU time 89.01 seconds
Started Jul 02 09:07:37 AM PDT 24
Finished Jul 02 09:09:08 AM PDT 24
Peak memory 206508 kb
Host smart-4e82c2d8-9fe0-48f4-a8fa-600c72edbc9f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3559949558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.3559949558
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.362940128
Short name T417
Test name
Test status
Simulation time 145453566 ps
CPU time 0.77 seconds
Started Jul 02 09:07:41 AM PDT 24
Finished Jul 02 09:07:44 AM PDT 24
Peak memory 206196 kb
Host smart-452bf934-f9b6-4b17-8826-cdf3ac2b2981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36294
0128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.362940128
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3642332487
Short name T106
Test name
Test status
Simulation time 1288457090 ps
CPU time 2.76 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 206376 kb
Host smart-790c7410-a822-403c-bd7e-739239111e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36423
32487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3642332487
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3101584543
Short name T545
Test name
Test status
Simulation time 183585071 ps
CPU time 1.67 seconds
Started Jul 02 09:07:57 AM PDT 24
Finished Jul 02 09:08:00 AM PDT 24
Peak memory 206408 kb
Host smart-92f3901d-52e5-44b9-bd76-03d1c42ee76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31015
84543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3101584543
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2291219112
Short name T66
Test name
Test status
Simulation time 150075096 ps
CPU time 0.87 seconds
Started Jul 02 09:06:16 AM PDT 24
Finished Jul 02 09:06:18 AM PDT 24
Peak memory 206156 kb
Host smart-0c09b99b-8b49-465c-b75e-accb031bc14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22912
19112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2291219112
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.256421154
Short name T54
Test name
Test status
Simulation time 200355952 ps
CPU time 0.83 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:58 AM PDT 24
Peak memory 206212 kb
Host smart-ee4c673d-eb70-420e-a80e-601d18a62a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25642
1154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.256421154
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.2060583612
Short name T68
Test name
Test status
Simulation time 4165482414 ps
CPU time 8.38 seconds
Started Jul 02 09:06:03 AM PDT 24
Finished Jul 02 09:06:14 AM PDT 24
Peak memory 206480 kb
Host smart-ab52e0bf-3e77-4955-a21d-efe9ce3e68df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20605
83612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.2060583612
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1238974032
Short name T69
Test name
Test status
Simulation time 166802276 ps
CPU time 0.78 seconds
Started Jul 02 09:05:54 AM PDT 24
Finished Jul 02 09:06:00 AM PDT 24
Peak memory 206168 kb
Host smart-ae06df45-65af-4e70-ab4b-33e0f1848c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12389
74032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1238974032
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2034674118
Short name T1561
Test name
Test status
Simulation time 182151346 ps
CPU time 0.9 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:05 AM PDT 24
Peak memory 206120 kb
Host smart-390529fa-e1d8-431c-b521-a99cfd9c2540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20346
74118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2034674118
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2867594870
Short name T664
Test name
Test status
Simulation time 6337449667 ps
CPU time 179.38 seconds
Started Jul 02 09:06:13 AM PDT 24
Finished Jul 02 09:09:14 AM PDT 24
Peak memory 206448 kb
Host smart-8da5f036-f11c-46c4-a69c-2b0575ab61d0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2867594870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2867594870
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1900844398
Short name T982
Test name
Test status
Simulation time 66032839 ps
CPU time 0.71 seconds
Started Jul 02 09:07:42 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206208 kb
Host smart-d8426a50-5d27-436f-87dc-5454619b7f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19008
44398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1900844398
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3237080348
Short name T167
Test name
Test status
Simulation time 1530117407 ps
CPU time 3.49 seconds
Started Jul 02 09:08:55 AM PDT 24
Finished Jul 02 09:08:59 AM PDT 24
Peak memory 206432 kb
Host smart-9abf039d-5840-4c55-a55d-39f5176a4d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32370
80348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3237080348
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2469138573
Short name T61
Test name
Test status
Simulation time 155608510 ps
CPU time 0.79 seconds
Started Jul 02 09:06:19 AM PDT 24
Finished Jul 02 09:06:20 AM PDT 24
Peak memory 206188 kb
Host smart-5d5a42c2-b8d2-4477-a147-feb28c04b458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24691
38573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2469138573
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2133641789
Short name T262
Test name
Test status
Simulation time 606482371 ps
CPU time 3.04 seconds
Started Jul 02 08:06:46 AM PDT 24
Finished Jul 02 08:06:52 AM PDT 24
Peak memory 205912 kb
Host smart-03febe94-a4e7-44e9-8dab-5706b6e7f3c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2133641789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2133641789
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.348281402
Short name T104
Test name
Test status
Simulation time 6693947974 ps
CPU time 183.14 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:08:54 AM PDT 24
Peak memory 206464 kb
Host smart-0530360f-bcfe-40d3-8942-e6864a76c0d1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=348281402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.348281402
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.712144467
Short name T2053
Test name
Test status
Simulation time 178712558 ps
CPU time 0.83 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 206204 kb
Host smart-1767ec8c-0add-49b7-b2a3-ea152a4bb4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71214
4467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.712144467
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1169676165
Short name T58
Test name
Test status
Simulation time 456698481 ps
CPU time 1.4 seconds
Started Jul 02 09:05:56 AM PDT 24
Finished Jul 02 09:06:02 AM PDT 24
Peak memory 206172 kb
Host smart-6f3c4893-4567-4f4c-8025-83eb38ea1936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11696
76165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1169676165
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.4275849319
Short name T137
Test name
Test status
Simulation time 204181841 ps
CPU time 0.81 seconds
Started Jul 02 09:06:14 AM PDT 24
Finished Jul 02 09:06:17 AM PDT 24
Peak memory 206160 kb
Host smart-ffa0c164-92e4-4731-a6fc-dbafdf1ad0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42758
49319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.4275849319
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1780544965
Short name T121
Test name
Test status
Simulation time 198934032 ps
CPU time 0.83 seconds
Started Jul 02 09:07:46 AM PDT 24
Finished Jul 02 09:07:49 AM PDT 24
Peak memory 206208 kb
Host smart-299b5302-e272-4cbb-a878-2cfdb063fb5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17805
44965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1780544965
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3088977396
Short name T191
Test name
Test status
Simulation time 1032942593 ps
CPU time 2.33 seconds
Started Jul 02 09:07:46 AM PDT 24
Finished Jul 02 09:07:49 AM PDT 24
Peak memory 206452 kb
Host smart-daa1b502-f77b-49c7-a1a0-b55b2d96e099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30889
77396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3088977396
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2138387260
Short name T123
Test name
Test status
Simulation time 197682083 ps
CPU time 0.9 seconds
Started Jul 02 09:08:03 AM PDT 24
Finished Jul 02 09:08:05 AM PDT 24
Peak memory 206120 kb
Host smart-fc93fe6d-2af2-449d-af33-b0c4da8b600d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21383
87260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2138387260
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2880933300
Short name T1682
Test name
Test status
Simulation time 8006049277 ps
CPU time 18.84 seconds
Started Jul 02 09:08:03 AM PDT 24
Finished Jul 02 09:08:23 AM PDT 24
Peak memory 206560 kb
Host smart-18b24bf2-72fb-4f3e-b8f7-7f92973fe04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28809
33300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2880933300
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2264895963
Short name T127
Test name
Test status
Simulation time 186951486 ps
CPU time 0.85 seconds
Started Jul 02 09:08:12 AM PDT 24
Finished Jul 02 09:08:13 AM PDT 24
Peak memory 206124 kb
Host smart-b520bed5-97b2-4465-a737-deb35873a7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22648
95963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2264895963
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2943435699
Short name T134
Test name
Test status
Simulation time 198235688 ps
CPU time 0.84 seconds
Started Jul 02 09:08:36 AM PDT 24
Finished Jul 02 09:08:37 AM PDT 24
Peak memory 206212 kb
Host smart-ff0ba59a-2ce3-43d7-94a4-b7e0b115353f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29434
35699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2943435699
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2067989538
Short name T2010
Test name
Test status
Simulation time 272765954 ps
CPU time 0.92 seconds
Started Jul 02 09:08:55 AM PDT 24
Finished Jul 02 09:08:58 AM PDT 24
Peak memory 206204 kb
Host smart-aac04edb-83a4-4b8e-b40a-f37679ea8790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20679
89538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2067989538
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3128437861
Short name T2151
Test name
Test status
Simulation time 241489912 ps
CPU time 0.91 seconds
Started Jul 02 09:09:06 AM PDT 24
Finished Jul 02 09:09:10 AM PDT 24
Peak memory 206208 kb
Host smart-5a43c766-d10b-4573-878d-ca99a26dc9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
37861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3128437861
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3170749800
Short name T2706
Test name
Test status
Simulation time 240603959 ps
CPU time 0.89 seconds
Started Jul 02 09:09:17 AM PDT 24
Finished Jul 02 09:09:19 AM PDT 24
Peak memory 206196 kb
Host smart-556496ed-a08c-4228-aef0-1c7601741a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31707
49800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3170749800
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.107540481
Short name T130
Test name
Test status
Simulation time 211991287 ps
CPU time 0.87 seconds
Started Jul 02 09:09:38 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206184 kb
Host smart-421b6dd5-58ab-44ef-a086-bde76f6bb8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10754
0481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.107540481
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.544794888
Short name T117
Test name
Test status
Simulation time 248617543 ps
CPU time 0.9 seconds
Started Jul 02 09:12:08 AM PDT 24
Finished Jul 02 09:12:11 AM PDT 24
Peak memory 206224 kb
Host smart-fa3c2223-86a3-4add-bc8e-8ec4b1acb9ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54479
4888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.544794888
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4184676871
Short name T2777
Test name
Test status
Simulation time 377114241 ps
CPU time 3.54 seconds
Started Jul 02 08:06:41 AM PDT 24
Finished Jul 02 08:06:48 AM PDT 24
Peak memory 205804 kb
Host smart-bd71e155-5552-44de-954f-0dfb5376ed5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4184676871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.4184676871
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2730369531
Short name T2757
Test name
Test status
Simulation time 1521170157 ps
CPU time 7.92 seconds
Started Jul 02 08:06:39 AM PDT 24
Finished Jul 02 08:06:50 AM PDT 24
Peak memory 205992 kb
Host smart-524a62ef-37c6-4126-a4f5-1d1456bb3c19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2730369531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2730369531
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1306046332
Short name T304
Test name
Test status
Simulation time 76562454 ps
CPU time 0.85 seconds
Started Jul 02 08:06:40 AM PDT 24
Finished Jul 02 08:06:44 AM PDT 24
Peak memory 205772 kb
Host smart-1c097eff-ad77-4139-9c1b-36543e5d0caf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1306046332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1306046332
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1456100445
Short name T2711
Test name
Test status
Simulation time 110418653 ps
CPU time 2.4 seconds
Started Jul 02 08:06:40 AM PDT 24
Finished Jul 02 08:06:47 AM PDT 24
Peak memory 213904 kb
Host smart-9d91b84d-a41e-4b2d-9bd9-51e98cae5c91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456100445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1456100445
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3181493103
Short name T2763
Test name
Test status
Simulation time 48107084 ps
CPU time 0.78 seconds
Started Jul 02 08:06:39 AM PDT 24
Finished Jul 02 08:06:43 AM PDT 24
Peak memory 205820 kb
Host smart-a88bde8f-1897-4f36-b5ee-2c2617bc0c27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3181493103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3181493103
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2506464068
Short name T2720
Test name
Test status
Simulation time 46581450 ps
CPU time 0.69 seconds
Started Jul 02 08:06:39 AM PDT 24
Finished Jul 02 08:06:43 AM PDT 24
Peak memory 205776 kb
Host smart-d9dffea6-7865-4003-b18c-a6ddbbd56062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2506464068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2506464068
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.846787568
Short name T288
Test name
Test status
Simulation time 93811864 ps
CPU time 2.22 seconds
Started Jul 02 08:06:40 AM PDT 24
Finished Jul 02 08:06:46 AM PDT 24
Peak memory 222352 kb
Host smart-3aeffe66-b687-4c68-9cd9-8d198196451a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=846787568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.846787568
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3995866785
Short name T2724
Test name
Test status
Simulation time 100441013 ps
CPU time 2.37 seconds
Started Jul 02 08:06:37 AM PDT 24
Finished Jul 02 08:06:42 AM PDT 24
Peak memory 205928 kb
Host smart-66b64463-16bf-4e6f-b803-b6526a58e333
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3995866785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3995866785
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.629293882
Short name T2727
Test name
Test status
Simulation time 284959714 ps
CPU time 1.76 seconds
Started Jul 02 08:06:41 AM PDT 24
Finished Jul 02 08:06:46 AM PDT 24
Peak memory 205928 kb
Host smart-ed701239-76d2-4a7a-9e77-ac2b33ac78e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=629293882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.629293882
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1390648614
Short name T2807
Test name
Test status
Simulation time 274185204 ps
CPU time 2.9 seconds
Started Jul 02 08:06:42 AM PDT 24
Finished Jul 02 08:06:48 AM PDT 24
Peak memory 221608 kb
Host smart-9bf33247-fd7f-491d-8eb1-1a61a97d15ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1390648614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1390648614
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3880572260
Short name T251
Test name
Test status
Simulation time 384053108 ps
CPU time 2.61 seconds
Started Jul 02 08:06:38 AM PDT 24
Finished Jul 02 08:06:44 AM PDT 24
Peak memory 206032 kb
Host smart-91188425-0770-4e49-9a98-0801036cfc93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3880572260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3880572260
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.632783182
Short name T284
Test name
Test status
Simulation time 80902213 ps
CPU time 2.02 seconds
Started Jul 02 08:06:39 AM PDT 24
Finished Jul 02 08:06:45 AM PDT 24
Peak memory 205924 kb
Host smart-29b998d6-88a3-4f68-aacd-337fbd127d47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=632783182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.632783182
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2081537417
Short name T302
Test name
Test status
Simulation time 841841264 ps
CPU time 5.11 seconds
Started Jul 02 08:06:38 AM PDT 24
Finished Jul 02 08:06:47 AM PDT 24
Peak memory 206040 kb
Host smart-49bf1b60-664a-41cc-b5fb-0f901e1a0f3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2081537417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2081537417
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4269410395
Short name T291
Test name
Test status
Simulation time 105020856 ps
CPU time 0.93 seconds
Started Jul 02 08:06:38 AM PDT 24
Finished Jul 02 08:06:42 AM PDT 24
Peak memory 205980 kb
Host smart-f5c0df7c-424d-4d3f-809d-35b09c75f9b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4269410395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.4269410395
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1498276157
Short name T2716
Test name
Test status
Simulation time 101350505 ps
CPU time 2.29 seconds
Started Jul 02 08:06:39 AM PDT 24
Finished Jul 02 08:06:45 AM PDT 24
Peak memory 214256 kb
Host smart-67c9f0bd-e71d-47cf-b861-27bc16754214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498276157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1498276157
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.365046047
Short name T290
Test name
Test status
Simulation time 51824948 ps
CPU time 0.87 seconds
Started Jul 02 08:06:39 AM PDT 24
Finished Jul 02 08:06:43 AM PDT 24
Peak memory 205804 kb
Host smart-8f728346-98b1-4ed2-889d-c59de3cd9f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=365046047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.365046047
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.4175132303
Short name T2747
Test name
Test status
Simulation time 47634556 ps
CPU time 0.74 seconds
Started Jul 02 08:06:42 AM PDT 24
Finished Jul 02 08:06:46 AM PDT 24
Peak memory 205768 kb
Host smart-ee552e38-953d-4bcf-8555-8c8573b9ac92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4175132303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.4175132303
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1464060898
Short name T283
Test name
Test status
Simulation time 85727987 ps
CPU time 2.1 seconds
Started Jul 02 08:06:39 AM PDT 24
Finished Jul 02 08:06:45 AM PDT 24
Peak memory 214236 kb
Host smart-ac7d3e06-12fe-4c0e-b4d4-e183d4d9e7cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1464060898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1464060898
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2205349096
Short name T2715
Test name
Test status
Simulation time 162643992 ps
CPU time 4 seconds
Started Jul 02 08:06:40 AM PDT 24
Finished Jul 02 08:06:47 AM PDT 24
Peak memory 205904 kb
Host smart-f13f9ecc-d5a6-4f6c-9bd5-46c435442e4f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2205349096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2205349096
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3124586711
Short name T245
Test name
Test status
Simulation time 86500249 ps
CPU time 1.03 seconds
Started Jul 02 08:06:39 AM PDT 24
Finished Jul 02 08:06:44 AM PDT 24
Peak memory 205940 kb
Host smart-60ea9fbb-1415-44d2-9038-336020854cea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3124586711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3124586711
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3659726827
Short name T2803
Test name
Test status
Simulation time 139609381 ps
CPU time 2.24 seconds
Started Jul 02 08:06:40 AM PDT 24
Finished Jul 02 08:06:46 AM PDT 24
Peak memory 221876 kb
Host smart-020c3e03-1cc5-4c0b-a7d0-b0b9d23579bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3659726827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3659726827
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3652756827
Short name T265
Test name
Test status
Simulation time 219557774 ps
CPU time 2.02 seconds
Started Jul 02 08:06:58 AM PDT 24
Finished Jul 02 08:07:04 AM PDT 24
Peak memory 214248 kb
Host smart-695fe436-6c59-425a-bf69-13a9873916d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652756827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3652756827
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3732924501
Short name T2771
Test name
Test status
Simulation time 46924827 ps
CPU time 0.8 seconds
Started Jul 02 08:06:58 AM PDT 24
Finished Jul 02 08:07:03 AM PDT 24
Peak memory 205832 kb
Host smart-2fdd7e73-8391-461a-94e8-745fcbb6232e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3732924501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3732924501
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2114841427
Short name T314
Test name
Test status
Simulation time 46112789 ps
CPU time 0.66 seconds
Started Jul 02 08:06:59 AM PDT 24
Finished Jul 02 08:07:04 AM PDT 24
Peak memory 205788 kb
Host smart-9012fb2a-5021-48d6-804e-c40560808668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2114841427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2114841427
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.855746939
Short name T2783
Test name
Test status
Simulation time 80545883 ps
CPU time 1.1 seconds
Started Jul 02 08:06:58 AM PDT 24
Finished Jul 02 08:07:03 AM PDT 24
Peak memory 206020 kb
Host smart-82afa4ce-8c8a-45ed-86dd-7d79cb4439d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=855746939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.855746939
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3403311299
Short name T2809
Test name
Test status
Simulation time 130252690 ps
CPU time 3.26 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:09 AM PDT 24
Peak memory 222352 kb
Host smart-b5f948e9-9b0f-4a04-811c-b08302758de3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3403311299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3403311299
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2336582506
Short name T328
Test name
Test status
Simulation time 1511938535 ps
CPU time 4.74 seconds
Started Jul 02 08:07:00 AM PDT 24
Finished Jul 02 08:07:10 AM PDT 24
Peak memory 206016 kb
Host smart-fea36e88-b31d-4e58-bcfb-89ac23ea1952
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2336582506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2336582506
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3620251556
Short name T263
Test name
Test status
Simulation time 135228377 ps
CPU time 2.19 seconds
Started Jul 02 08:06:58 AM PDT 24
Finished Jul 02 08:07:04 AM PDT 24
Peak memory 214204 kb
Host smart-e29ca2bd-04f4-4bf6-a728-9ea02d0fcede
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620251556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3620251556
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1162335462
Short name T286
Test name
Test status
Simulation time 104820307 ps
CPU time 1.01 seconds
Started Jul 02 08:06:58 AM PDT 24
Finished Jul 02 08:07:02 AM PDT 24
Peak memory 206008 kb
Host smart-5f3d6024-3610-4b17-9f6e-4c196924cfac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1162335462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1162335462
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2064723349
Short name T2754
Test name
Test status
Simulation time 101403934 ps
CPU time 0.76 seconds
Started Jul 02 08:06:59 AM PDT 24
Finished Jul 02 08:07:04 AM PDT 24
Peak memory 205728 kb
Host smart-8c191bdb-5f84-4277-8722-9a23d6bd612e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2064723349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2064723349
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.606739034
Short name T305
Test name
Test status
Simulation time 118242761 ps
CPU time 1.22 seconds
Started Jul 02 08:06:59 AM PDT 24
Finished Jul 02 08:07:05 AM PDT 24
Peak memory 206004 kb
Host smart-7afb3925-6a3c-49c8-bf9e-8859ad51db96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=606739034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.606739034
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1962475574
Short name T2761
Test name
Test status
Simulation time 287468811 ps
CPU time 3.19 seconds
Started Jul 02 08:06:59 AM PDT 24
Finished Jul 02 08:07:06 AM PDT 24
Peak memory 214212 kb
Host smart-0cc81b08-f2a5-432a-8d9c-6c6b0b768495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1962475574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1962475574
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1663274569
Short name T324
Test name
Test status
Simulation time 967870368 ps
CPU time 4.35 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:10 AM PDT 24
Peak memory 205980 kb
Host smart-153affdc-2c70-4388-ac65-f0d9f1730f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1663274569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1663274569
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1902615923
Short name T2784
Test name
Test status
Simulation time 126960387 ps
CPU time 1.35 seconds
Started Jul 02 08:06:58 AM PDT 24
Finished Jul 02 08:07:02 AM PDT 24
Peak memory 214180 kb
Host smart-63584ea7-70cb-4cf1-afd9-e1a715f9662f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902615923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1902615923
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.444549939
Short name T2794
Test name
Test status
Simulation time 129140308 ps
CPU time 0.89 seconds
Started Jul 02 08:07:00 AM PDT 24
Finished Jul 02 08:07:06 AM PDT 24
Peak memory 205784 kb
Host smart-f4935640-5159-4014-8990-a11188db4d20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=444549939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.444549939
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.111149765
Short name T2741
Test name
Test status
Simulation time 68480003 ps
CPU time 0.73 seconds
Started Jul 02 08:07:02 AM PDT 24
Finished Jul 02 08:07:08 AM PDT 24
Peak memory 205752 kb
Host smart-6ee61e20-979a-43bd-b75f-5a946f9ed95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=111149765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.111149765
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2090621628
Short name T296
Test name
Test status
Simulation time 215210348 ps
CPU time 1.64 seconds
Started Jul 02 08:07:00 AM PDT 24
Finished Jul 02 08:07:06 AM PDT 24
Peak memory 206020 kb
Host smart-90ab9835-c54a-4988-bc0e-c7b32f8fbc17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2090621628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2090621628
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2998297141
Short name T2759
Test name
Test status
Simulation time 119737685 ps
CPU time 2.68 seconds
Started Jul 02 08:06:59 AM PDT 24
Finished Jul 02 08:07:06 AM PDT 24
Peak memory 214184 kb
Host smart-c012ffc3-d916-489c-8cf6-34e7ebefe32c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2998297141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2998297141
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2140689736
Short name T329
Test name
Test status
Simulation time 729974928 ps
CPU time 2.95 seconds
Started Jul 02 08:07:00 AM PDT 24
Finished Jul 02 08:07:08 AM PDT 24
Peak memory 205944 kb
Host smart-00f3a029-4cd8-41c3-8f2a-fc4a90341636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2140689736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2140689736
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2210381763
Short name T2725
Test name
Test status
Simulation time 65512913 ps
CPU time 1.56 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:07 AM PDT 24
Peak memory 214212 kb
Host smart-c6d99769-fa90-4e9a-b15e-5ba1ae60359f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210381763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2210381763
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1541026235
Short name T2768
Test name
Test status
Simulation time 55478678 ps
CPU time 0.82 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:08 AM PDT 24
Peak memory 205732 kb
Host smart-21eaed8c-d627-462c-adb2-c35a60c021fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1541026235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1541026235
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3620111364
Short name T2810
Test name
Test status
Simulation time 43663702 ps
CPU time 0.67 seconds
Started Jul 02 08:07:00 AM PDT 24
Finished Jul 02 08:07:06 AM PDT 24
Peak memory 205780 kb
Host smart-79e7e70f-f371-45c3-9222-b8c462ad6c82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3620111364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3620111364
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1452006437
Short name T303
Test name
Test status
Simulation time 230644820 ps
CPU time 1.6 seconds
Started Jul 02 08:07:05 AM PDT 24
Finished Jul 02 08:07:12 AM PDT 24
Peak memory 205940 kb
Host smart-763099fd-65f8-4dcb-9cc9-1fe61bdc93fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1452006437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1452006437
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.310485969
Short name T2730
Test name
Test status
Simulation time 74644763 ps
CPU time 1.92 seconds
Started Jul 02 08:07:00 AM PDT 24
Finished Jul 02 08:07:07 AM PDT 24
Peak memory 214108 kb
Host smart-110e1b7e-42e2-4566-b9af-99cea238b95b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=310485969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.310485969
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2690100672
Short name T2729
Test name
Test status
Simulation time 130202398 ps
CPU time 1.33 seconds
Started Jul 02 08:07:05 AM PDT 24
Finished Jul 02 08:07:12 AM PDT 24
Peak memory 214232 kb
Host smart-1dd1fecf-a0fc-41f3-97cd-8bb74b730c99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690100672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2690100672
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4288753779
Short name T2786
Test name
Test status
Simulation time 59403385 ps
CPU time 0.8 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:06 AM PDT 24
Peak memory 205784 kb
Host smart-bab743d7-db09-48a6-9712-c1ffe5941373
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4288753779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4288753779
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1382438837
Short name T228
Test name
Test status
Simulation time 36318544 ps
CPU time 0.65 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:07 AM PDT 24
Peak memory 205724 kb
Host smart-3d7ad32f-7925-48df-9d14-04a52b38afe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1382438837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1382438837
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1561938773
Short name T2744
Test name
Test status
Simulation time 131701405 ps
CPU time 1.24 seconds
Started Jul 02 08:07:02 AM PDT 24
Finished Jul 02 08:07:09 AM PDT 24
Peak memory 206008 kb
Host smart-1caab17e-3f5c-4d27-a8df-64652c6fab41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1561938773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1561938773
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2230533548
Short name T2787
Test name
Test status
Simulation time 87834064 ps
CPU time 2.38 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:08 AM PDT 24
Peak memory 221680 kb
Host smart-8947c57c-4596-4d07-a0bf-119ad74f0e14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2230533548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2230533548
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3486524519
Short name T2736
Test name
Test status
Simulation time 636862155 ps
CPU time 3.02 seconds
Started Jul 02 08:07:06 AM PDT 24
Finished Jul 02 08:07:15 AM PDT 24
Peak memory 205948 kb
Host smart-70a42950-7143-4ebe-9949-03820d81052d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3486524519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3486524519
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2363385183
Short name T266
Test name
Test status
Simulation time 98468911 ps
CPU time 2.58 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:09 AM PDT 24
Peak memory 214188 kb
Host smart-5691ce87-056e-440c-b395-5347585d17c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363385183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2363385183
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4020909787
Short name T2749
Test name
Test status
Simulation time 61444020 ps
CPU time 0.99 seconds
Started Jul 02 08:07:04 AM PDT 24
Finished Jul 02 08:07:09 AM PDT 24
Peak memory 205944 kb
Host smart-a64c978e-306e-47c2-8d68-e744fd78f60f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4020909787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4020909787
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1115676325
Short name T2728
Test name
Test status
Simulation time 59728801 ps
CPU time 0.68 seconds
Started Jul 02 08:07:11 AM PDT 24
Finished Jul 02 08:07:18 AM PDT 24
Peak memory 205660 kb
Host smart-f6960ed3-335a-406e-a851-dd07dcb7de15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1115676325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1115676325
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4207183448
Short name T306
Test name
Test status
Simulation time 112793715 ps
CPU time 1.06 seconds
Started Jul 02 08:07:10 AM PDT 24
Finished Jul 02 08:07:18 AM PDT 24
Peak memory 205816 kb
Host smart-e6184190-6737-471f-9393-b9cfe6645542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4207183448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.4207183448
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.402573881
Short name T2782
Test name
Test status
Simulation time 85714567 ps
CPU time 1.49 seconds
Started Jul 02 08:07:11 AM PDT 24
Finished Jul 02 08:07:19 AM PDT 24
Peak memory 214116 kb
Host smart-ba695757-5c56-4863-91f8-bd6f3ba68007
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=402573881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.402573881
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2074183389
Short name T2776
Test name
Test status
Simulation time 92468497 ps
CPU time 1.28 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:08 AM PDT 24
Peak memory 214136 kb
Host smart-12ec93a3-8fee-4ff2-b5ef-c2a8e0a64885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074183389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2074183389
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1395949268
Short name T2760
Test name
Test status
Simulation time 39343180 ps
CPU time 0.76 seconds
Started Jul 02 08:07:10 AM PDT 24
Finished Jul 02 08:07:18 AM PDT 24
Peak memory 205664 kb
Host smart-ec19b5b5-3fee-4e3d-bb84-239317c88597
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1395949268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1395949268
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.464966567
Short name T2779
Test name
Test status
Simulation time 39539903 ps
CPU time 0.69 seconds
Started Jul 02 08:07:02 AM PDT 24
Finished Jul 02 08:07:08 AM PDT 24
Peak memory 205752 kb
Host smart-b220781e-a8ba-4ff9-8fa9-b3c2a84bc39d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=464966567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.464966567
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2782031313
Short name T2806
Test name
Test status
Simulation time 111013784 ps
CPU time 1.2 seconds
Started Jul 02 08:07:04 AM PDT 24
Finished Jul 02 08:07:10 AM PDT 24
Peak memory 205972 kb
Host smart-a3b5e7c0-2962-4be4-8f25-54c6e7b66e81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2782031313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2782031313
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2710696920
Short name T244
Test name
Test status
Simulation time 205526498 ps
CPU time 1.84 seconds
Started Jul 02 08:07:02 AM PDT 24
Finished Jul 02 08:07:09 AM PDT 24
Peak memory 205988 kb
Host smart-114ee785-f59b-429d-95cc-2b38dcb04032
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2710696920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2710696920
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.259017619
Short name T267
Test name
Test status
Simulation time 1305308449 ps
CPU time 5.21 seconds
Started Jul 02 08:07:00 AM PDT 24
Finished Jul 02 08:07:11 AM PDT 24
Peak memory 205900 kb
Host smart-f981057e-eabc-4bce-bb81-ec21c0ed3b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=259017619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.259017619
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3097895919
Short name T2765
Test name
Test status
Simulation time 178499156 ps
CPU time 1.31 seconds
Started Jul 02 08:07:07 AM PDT 24
Finished Jul 02 08:07:14 AM PDT 24
Peak memory 214172 kb
Host smart-2f1fb006-0dbd-4f0b-99a5-5410a910fcd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097895919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3097895919
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1396965388
Short name T2738
Test name
Test status
Simulation time 68470182 ps
CPU time 0.8 seconds
Started Jul 02 08:07:10 AM PDT 24
Finished Jul 02 08:07:17 AM PDT 24
Peak memory 205816 kb
Host smart-b604af04-ceab-4fef-884d-e49cb808f51f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1396965388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1396965388
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4224212504
Short name T2802
Test name
Test status
Simulation time 123878753 ps
CPU time 1.21 seconds
Started Jul 02 08:07:10 AM PDT 24
Finished Jul 02 08:07:18 AM PDT 24
Peak memory 206020 kb
Host smart-9796c39c-5487-45ee-9bdb-98fb988ffce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4224212504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.4224212504
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1040358235
Short name T2795
Test name
Test status
Simulation time 335728372 ps
CPU time 3.42 seconds
Started Jul 02 08:07:02 AM PDT 24
Finished Jul 02 08:07:11 AM PDT 24
Peak memory 222280 kb
Host smart-c7bb9949-37bc-489c-84e4-f53b82de58eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1040358235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1040358235
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1416215217
Short name T301
Test name
Test status
Simulation time 461454515 ps
CPU time 2.82 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:10 AM PDT 24
Peak memory 205952 kb
Host smart-67e0aa18-4b66-4595-af4b-6d145e24a494
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1416215217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1416215217
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4025403830
Short name T2745
Test name
Test status
Simulation time 92788844 ps
CPU time 1.97 seconds
Started Jul 02 08:07:14 AM PDT 24
Finished Jul 02 08:07:23 AM PDT 24
Peak memory 214156 kb
Host smart-06160af5-9081-4792-b4f1-b6ea483bcbd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025403830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.4025403830
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2542529546
Short name T2751
Test name
Test status
Simulation time 207820918 ps
CPU time 1.73 seconds
Started Jul 02 08:07:05 AM PDT 24
Finished Jul 02 08:07:13 AM PDT 24
Peak memory 205996 kb
Host smart-9e3654d6-2574-4130-aa79-233ad71f3959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2542529546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2542529546
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4271545300
Short name T2762
Test name
Test status
Simulation time 81916698 ps
CPU time 1.79 seconds
Started Jul 02 08:07:06 AM PDT 24
Finished Jul 02 08:07:14 AM PDT 24
Peak memory 214200 kb
Host smart-84fe8090-5051-4956-be73-88dc0f7db9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4271545300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.4271545300
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2138319256
Short name T218
Test name
Test status
Simulation time 643905595 ps
CPU time 2.92 seconds
Started Jul 02 08:07:06 AM PDT 24
Finished Jul 02 08:07:15 AM PDT 24
Peak memory 206028 kb
Host smart-0c42c475-efcf-4db9-a7f3-f5a83732af70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2138319256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2138319256
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2572794786
Short name T2753
Test name
Test status
Simulation time 76627043 ps
CPU time 1.84 seconds
Started Jul 02 08:07:10 AM PDT 24
Finished Jul 02 08:07:18 AM PDT 24
Peak memory 214264 kb
Host smart-a4919ee6-2b45-40e5-ad93-fedd08b63753
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572794786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2572794786
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.435141246
Short name T2793
Test name
Test status
Simulation time 80816012 ps
CPU time 1.04 seconds
Started Jul 02 08:07:08 AM PDT 24
Finished Jul 02 08:07:14 AM PDT 24
Peak memory 205928 kb
Host smart-3b0b7b20-192c-496b-896f-d63f21d818ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=435141246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.435141246
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3692674830
Short name T2718
Test name
Test status
Simulation time 33949460 ps
CPU time 0.68 seconds
Started Jul 02 08:07:10 AM PDT 24
Finished Jul 02 08:07:17 AM PDT 24
Peak memory 205792 kb
Host smart-3ee8dbad-ad5e-412e-ae88-10e1b52a0b33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3692674830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3692674830
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1818664425
Short name T2714
Test name
Test status
Simulation time 249143507 ps
CPU time 1.58 seconds
Started Jul 02 08:07:06 AM PDT 24
Finished Jul 02 08:07:13 AM PDT 24
Peak memory 206012 kb
Host smart-c3846283-6931-4d0d-a5a4-5ea0dd321f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1818664425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1818664425
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3167092934
Short name T2734
Test name
Test status
Simulation time 270604062 ps
CPU time 3.08 seconds
Started Jul 02 08:07:08 AM PDT 24
Finished Jul 02 08:07:16 AM PDT 24
Peak memory 214216 kb
Host smart-539818d5-f329-4ad6-95cc-64351c2ed18a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3167092934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3167092934
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1860824186
Short name T2792
Test name
Test status
Simulation time 786271975 ps
CPU time 4.23 seconds
Started Jul 02 08:07:08 AM PDT 24
Finished Jul 02 08:07:18 AM PDT 24
Peak memory 205892 kb
Host smart-adeb6840-2af4-4b73-af6d-3b3f8e89091d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1860824186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1860824186
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3197225976
Short name T2764
Test name
Test status
Simulation time 299620923 ps
CPU time 3.6 seconds
Started Jul 02 08:06:43 AM PDT 24
Finished Jul 02 08:06:50 AM PDT 24
Peak memory 205992 kb
Host smart-a6a7ebfe-db66-47c8-8a65-0816d8d1f5ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3197225976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3197225976
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.757459875
Short name T292
Test name
Test status
Simulation time 1222404889 ps
CPU time 8.65 seconds
Started Jul 02 08:06:44 AM PDT 24
Finished Jul 02 08:06:56 AM PDT 24
Peak memory 206160 kb
Host smart-a23a8b0f-c304-4094-8d3c-48ec06bee4aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=757459875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.757459875
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3149964159
Short name T2801
Test name
Test status
Simulation time 69640365 ps
CPU time 0.83 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:55 AM PDT 24
Peak memory 205780 kb
Host smart-377738fa-6638-4413-86b4-e342324ef1d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3149964159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3149964159
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3748871951
Short name T2752
Test name
Test status
Simulation time 96533828 ps
CPU time 1.11 seconds
Started Jul 02 08:06:46 AM PDT 24
Finished Jul 02 08:06:50 AM PDT 24
Peak memory 214192 kb
Host smart-110dc3fa-d5d1-481f-82a2-98a120db62c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748871951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3748871951
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2588730056
Short name T297
Test name
Test status
Simulation time 86234361 ps
CPU time 0.9 seconds
Started Jul 02 08:06:47 AM PDT 24
Finished Jul 02 08:06:50 AM PDT 24
Peak memory 205844 kb
Host smart-098f823f-9cbd-461f-847b-012c262d8f29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2588730056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2588730056
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.4172630957
Short name T313
Test name
Test status
Simulation time 45903021 ps
CPU time 0.68 seconds
Started Jul 02 08:06:41 AM PDT 24
Finished Jul 02 08:06:45 AM PDT 24
Peak memory 205716 kb
Host smart-981766c5-df6b-4656-aeb5-4838c1670b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4172630957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.4172630957
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3992249711
Short name T2800
Test name
Test status
Simulation time 226100610 ps
CPU time 2.47 seconds
Started Jul 02 08:06:50 AM PDT 24
Finished Jul 02 08:06:56 AM PDT 24
Peak memory 214196 kb
Host smart-ba186b38-65d5-4886-8395-99ec943b9b8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3992249711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3992249711
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1105245435
Short name T2778
Test name
Test status
Simulation time 484010837 ps
CPU time 4.49 seconds
Started Jul 02 08:06:39 AM PDT 24
Finished Jul 02 08:06:47 AM PDT 24
Peak memory 205960 kb
Host smart-b3fb32bd-10ee-4c4a-9a40-b938d5005d10
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1105245435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1105245435
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2652513229
Short name T2797
Test name
Test status
Simulation time 110835853 ps
CPU time 1.21 seconds
Started Jul 02 08:06:44 AM PDT 24
Finished Jul 02 08:06:47 AM PDT 24
Peak memory 206020 kb
Host smart-e8c5e696-97d1-4bca-80a4-fabc5efd8dff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2652513229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2652513229
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1380369949
Short name T2808
Test name
Test status
Simulation time 115942505 ps
CPU time 1.62 seconds
Started Jul 02 08:06:40 AM PDT 24
Finished Jul 02 08:06:45 AM PDT 24
Peak memory 206028 kb
Host smart-fece74fb-d0d8-486b-86a1-e44c375c628c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1380369949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1380369949
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.217311026
Short name T327
Test name
Test status
Simulation time 745866970 ps
CPU time 4.13 seconds
Started Jul 02 08:06:40 AM PDT 24
Finished Jul 02 08:06:48 AM PDT 24
Peak memory 205988 kb
Host smart-94ad8714-b8e0-491b-b14e-617980858635
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=217311026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.217311026
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2491908001
Short name T311
Test name
Test status
Simulation time 44545001 ps
CPU time 0.68 seconds
Started Jul 02 08:07:07 AM PDT 24
Finished Jul 02 08:07:13 AM PDT 24
Peak memory 205788 kb
Host smart-ff0af25b-c0e5-4bb1-97db-f459ffb3382d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2491908001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2491908001
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3597275856
Short name T226
Test name
Test status
Simulation time 37908118 ps
CPU time 0.65 seconds
Started Jul 02 08:07:09 AM PDT 24
Finished Jul 02 08:07:16 AM PDT 24
Peak memory 205760 kb
Host smart-258aaae0-2733-4fbd-886e-84ad109f1e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3597275856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3597275856
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.344418900
Short name T2775
Test name
Test status
Simulation time 36914214 ps
CPU time 0.67 seconds
Started Jul 02 08:07:06 AM PDT 24
Finished Jul 02 08:07:13 AM PDT 24
Peak memory 205764 kb
Host smart-402da18a-0464-4b8e-b20b-4c721e745b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=344418900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.344418900
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2593324582
Short name T2743
Test name
Test status
Simulation time 78586613 ps
CPU time 0.69 seconds
Started Jul 02 08:07:06 AM PDT 24
Finished Jul 02 08:07:13 AM PDT 24
Peak memory 205756 kb
Host smart-5722a9ee-49c6-467e-98c9-f6292b05e000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2593324582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2593324582
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1420212887
Short name T308
Test name
Test status
Simulation time 45598627 ps
CPU time 0.67 seconds
Started Jul 02 08:07:07 AM PDT 24
Finished Jul 02 08:07:13 AM PDT 24
Peak memory 205972 kb
Host smart-1e7fb065-99ec-4f16-b9f5-fc27c7b5741c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1420212887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1420212887
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.16650380
Short name T2746
Test name
Test status
Simulation time 37965122 ps
CPU time 0.65 seconds
Started Jul 02 08:07:10 AM PDT 24
Finished Jul 02 08:07:17 AM PDT 24
Peak memory 205788 kb
Host smart-06cea66f-fc53-4315-ac58-1245c3acd353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=16650380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.16650380
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.998384986
Short name T2717
Test name
Test status
Simulation time 101823110 ps
CPU time 0.75 seconds
Started Jul 02 08:07:05 AM PDT 24
Finished Jul 02 08:07:11 AM PDT 24
Peak memory 205716 kb
Host smart-76c54387-f2d5-458b-887f-3785e8561cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=998384986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.998384986
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1808524366
Short name T227
Test name
Test status
Simulation time 37832119 ps
CPU time 0.67 seconds
Started Jul 02 08:07:09 AM PDT 24
Finished Jul 02 08:07:15 AM PDT 24
Peak memory 205788 kb
Host smart-d86d2cb2-7181-4fb8-a1be-ffa27f520864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1808524366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1808524366
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3326893892
Short name T2780
Test name
Test status
Simulation time 210716442 ps
CPU time 2.21 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 206008 kb
Host smart-41d95b25-ac94-495b-bc7c-85489273cb98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3326893892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3326893892
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2578310619
Short name T2733
Test name
Test status
Simulation time 2092312613 ps
CPU time 8.42 seconds
Started Jul 02 08:06:44 AM PDT 24
Finished Jul 02 08:06:55 AM PDT 24
Peak memory 206000 kb
Host smart-fd96bc3b-768d-44ee-97dd-4c95e1fae612
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2578310619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2578310619
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1104387427
Short name T2773
Test name
Test status
Simulation time 125388810 ps
CPU time 1 seconds
Started Jul 02 08:06:46 AM PDT 24
Finished Jul 02 08:06:50 AM PDT 24
Peak memory 205796 kb
Host smart-01513e32-73ea-4be7-8a67-e00d680ebd7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1104387427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1104387427
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2326575693
Short name T2781
Test name
Test status
Simulation time 63658179 ps
CPU time 1.55 seconds
Started Jul 02 08:06:45 AM PDT 24
Finished Jul 02 08:06:49 AM PDT 24
Peak memory 214220 kb
Host smart-52195d8d-54c5-4d40-884a-a956d6262d32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326575693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2326575693
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3969979424
Short name T285
Test name
Test status
Simulation time 89978195 ps
CPU time 1.01 seconds
Started Jul 02 08:06:44 AM PDT 24
Finished Jul 02 08:06:48 AM PDT 24
Peak memory 205984 kb
Host smart-8f23a499-0c70-408c-aa1b-0f2ccce0e6b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3969979424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3969979424
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3643034521
Short name T2790
Test name
Test status
Simulation time 52516478 ps
CPU time 0.71 seconds
Started Jul 02 08:06:45 AM PDT 24
Finished Jul 02 08:06:48 AM PDT 24
Peak memory 205796 kb
Host smart-89c76bed-c508-4fad-913e-d21cc5111ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3643034521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3643034521
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3803270237
Short name T293
Test name
Test status
Simulation time 185150488 ps
CPU time 2.32 seconds
Started Jul 02 08:06:46 AM PDT 24
Finished Jul 02 08:06:51 AM PDT 24
Peak memory 214144 kb
Host smart-bf15ccba-893f-4a21-a06c-1742a97771df
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3803270237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3803270237
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.89745477
Short name T2723
Test name
Test status
Simulation time 371423659 ps
CPU time 2.65 seconds
Started Jul 02 08:06:45 AM PDT 24
Finished Jul 02 08:06:50 AM PDT 24
Peak memory 205972 kb
Host smart-e8adbbea-e680-40a5-b80b-71e6b57e97cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=89745477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.89745477
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2012403792
Short name T2721
Test name
Test status
Simulation time 257144909 ps
CPU time 1.86 seconds
Started Jul 02 08:06:45 AM PDT 24
Finished Jul 02 08:06:50 AM PDT 24
Peak memory 205944 kb
Host smart-b9e230d3-69bf-450c-a06a-ae4dbabdc047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2012403792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2012403792
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.745973324
Short name T252
Test name
Test status
Simulation time 78738953 ps
CPU time 1.82 seconds
Started Jul 02 08:06:47 AM PDT 24
Finished Jul 02 08:06:51 AM PDT 24
Peak memory 221688 kb
Host smart-faba5f2d-348e-449e-898a-d881c1fd3a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=745973324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.745973324
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1262853003
Short name T2799
Test name
Test status
Simulation time 987765518 ps
CPU time 3.18 seconds
Started Jul 02 08:06:46 AM PDT 24
Finished Jul 02 08:06:52 AM PDT 24
Peak memory 205944 kb
Host smart-1882266f-cba5-46b8-b6b4-daf6555bb4f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1262853003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1262853003
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.631492088
Short name T2796
Test name
Test status
Simulation time 52428300 ps
CPU time 0.73 seconds
Started Jul 02 08:07:09 AM PDT 24
Finished Jul 02 08:07:16 AM PDT 24
Peak memory 205764 kb
Host smart-285ffba5-1525-46fd-b157-880b51e679f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=631492088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.631492088
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3085569303
Short name T2774
Test name
Test status
Simulation time 52464331 ps
CPU time 0.67 seconds
Started Jul 02 08:07:06 AM PDT 24
Finished Jul 02 08:07:13 AM PDT 24
Peak memory 205760 kb
Host smart-ac394dac-7140-4666-b619-0e146c7a5324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3085569303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3085569303
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1972536492
Short name T223
Test name
Test status
Simulation time 81547034 ps
CPU time 0.78 seconds
Started Jul 02 08:07:06 AM PDT 24
Finished Jul 02 08:07:12 AM PDT 24
Peak memory 205756 kb
Host smart-78b8b88c-f5cd-4a6e-a771-cdcdef1bd7c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1972536492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1972536492
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1810477009
Short name T2769
Test name
Test status
Simulation time 36841850 ps
CPU time 0.7 seconds
Started Jul 02 08:07:12 AM PDT 24
Finished Jul 02 08:07:19 AM PDT 24
Peak memory 205772 kb
Host smart-f5793c53-4f8a-4377-9d22-e325dddf4ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1810477009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1810477009
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.657615404
Short name T2739
Test name
Test status
Simulation time 31301116 ps
CPU time 0.66 seconds
Started Jul 02 08:07:13 AM PDT 24
Finished Jul 02 08:07:21 AM PDT 24
Peak memory 205764 kb
Host smart-ad783449-b5b0-4010-bd73-f05644820001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=657615404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.657615404
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3733906467
Short name T2785
Test name
Test status
Simulation time 57970407 ps
CPU time 0.69 seconds
Started Jul 02 08:07:11 AM PDT 24
Finished Jul 02 08:07:18 AM PDT 24
Peak memory 205772 kb
Host smart-9dfeff3c-aa56-4ccb-b3f7-624f41c6d21b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3733906467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3733906467
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1498687992
Short name T2804
Test name
Test status
Simulation time 57366381 ps
CPU time 0.69 seconds
Started Jul 02 08:07:13 AM PDT 24
Finished Jul 02 08:07:21 AM PDT 24
Peak memory 205784 kb
Host smart-b6711282-b4a3-44a5-bd40-c175572703bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1498687992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1498687992
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2515637886
Short name T2772
Test name
Test status
Simulation time 55588501 ps
CPU time 0.7 seconds
Started Jul 02 08:07:16 AM PDT 24
Finished Jul 02 08:07:23 AM PDT 24
Peak memory 205764 kb
Host smart-22064143-0c3a-4343-8cae-4e79bb6e78f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2515637886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2515637886
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.325650585
Short name T229
Test name
Test status
Simulation time 75849696 ps
CPU time 0.74 seconds
Started Jul 02 08:07:13 AM PDT 24
Finished Jul 02 08:07:21 AM PDT 24
Peak memory 205760 kb
Host smart-0ea6256d-1800-45f4-8f04-e0cc5a4c5ed4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=325650585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.325650585
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1350044909
Short name T2710
Test name
Test status
Simulation time 91899699 ps
CPU time 2.01 seconds
Started Jul 02 08:06:53 AM PDT 24
Finished Jul 02 08:06:59 AM PDT 24
Peak memory 205904 kb
Host smart-f007f93b-243d-4ff4-9df7-1224b702b2be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1350044909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1350044909
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4117830341
Short name T2708
Test name
Test status
Simulation time 344696589 ps
CPU time 4.5 seconds
Started Jul 02 08:06:52 AM PDT 24
Finished Jul 02 08:07:00 AM PDT 24
Peak memory 205840 kb
Host smart-d8ac987b-cb52-418d-9c00-1dae97026c05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4117830341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.4117830341
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1411815727
Short name T2719
Test name
Test status
Simulation time 133819017 ps
CPU time 0.97 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:55 AM PDT 24
Peak memory 205812 kb
Host smart-243bb488-216a-4e26-850e-10993caf1ee0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1411815727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1411815727
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4084182961
Short name T2737
Test name
Test status
Simulation time 95349370 ps
CPU time 2.4 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 214152 kb
Host smart-402a375d-0f1d-4b96-9630-2be0dde2a8ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084182961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.4084182961
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2279596308
Short name T264
Test name
Test status
Simulation time 60795804 ps
CPU time 0.85 seconds
Started Jul 02 08:06:48 AM PDT 24
Finished Jul 02 08:06:51 AM PDT 24
Peak memory 205768 kb
Host smart-cee12f8e-c770-4109-a60d-3089c18cd558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2279596308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2279596308
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1056228439
Short name T318
Test name
Test status
Simulation time 112852573 ps
CPU time 0.75 seconds
Started Jul 02 08:06:45 AM PDT 24
Finished Jul 02 08:06:48 AM PDT 24
Peak memory 205784 kb
Host smart-3b30ff10-a4db-4aaa-b1e5-197e242e6ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1056228439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1056228439
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2446185760
Short name T287
Test name
Test status
Simulation time 84500887 ps
CPU time 1.42 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 214204 kb
Host smart-6f7595b9-4ef0-4032-b584-039924554d68
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2446185760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2446185760
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.205422662
Short name T2750
Test name
Test status
Simulation time 711051175 ps
CPU time 4.51 seconds
Started Jul 02 08:06:50 AM PDT 24
Finished Jul 02 08:06:58 AM PDT 24
Peak memory 205972 kb
Host smart-f0ed6351-8281-46b7-a0ae-d32b73e2f630
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=205422662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.205422662
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2726746465
Short name T2722
Test name
Test status
Simulation time 173782203 ps
CPU time 1.76 seconds
Started Jul 02 08:06:53 AM PDT 24
Finished Jul 02 08:06:58 AM PDT 24
Peak memory 205956 kb
Host smart-4d3d2301-1412-4829-80e7-adbbc2bb8f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2726746465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2726746465
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2396773005
Short name T258
Test name
Test status
Simulation time 248942823 ps
CPU time 2.74 seconds
Started Jul 02 08:06:46 AM PDT 24
Finished Jul 02 08:06:51 AM PDT 24
Peak memory 222276 kb
Host smart-4cf27bca-94ba-4ace-8b86-f78c652421bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2396773005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2396773005
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1723105682
Short name T2755
Test name
Test status
Simulation time 34475763 ps
CPU time 0.68 seconds
Started Jul 02 08:07:15 AM PDT 24
Finished Jul 02 08:07:22 AM PDT 24
Peak memory 205780 kb
Host smart-94b64415-ce2a-4d98-8259-58d393d3f7cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1723105682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1723105682
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1599795418
Short name T2798
Test name
Test status
Simulation time 39315739 ps
CPU time 0.65 seconds
Started Jul 02 08:07:14 AM PDT 24
Finished Jul 02 08:07:22 AM PDT 24
Peak memory 205792 kb
Host smart-07b74b15-f5f7-4262-8e06-ddf7463ca3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1599795418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1599795418
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3869939505
Short name T2735
Test name
Test status
Simulation time 55182687 ps
CPU time 0.68 seconds
Started Jul 02 08:07:13 AM PDT 24
Finished Jul 02 08:07:21 AM PDT 24
Peak memory 205756 kb
Host smart-f3b2857e-ae15-4044-9d79-f91511f24857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3869939505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3869939505
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1744029071
Short name T2788
Test name
Test status
Simulation time 121297630 ps
CPU time 0.72 seconds
Started Jul 02 08:07:16 AM PDT 24
Finished Jul 02 08:07:23 AM PDT 24
Peak memory 205748 kb
Host smart-c4eeab6f-8023-4039-b787-c579af4d5ab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1744029071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1744029071
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1217311913
Short name T316
Test name
Test status
Simulation time 39476810 ps
CPU time 0.7 seconds
Started Jul 02 08:07:13 AM PDT 24
Finished Jul 02 08:07:21 AM PDT 24
Peak memory 205940 kb
Host smart-bf2dab7b-b04f-44da-beae-62b8cff3d500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1217311913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1217311913
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.601570459
Short name T322
Test name
Test status
Simulation time 45955972 ps
CPU time 0.69 seconds
Started Jul 02 08:07:14 AM PDT 24
Finished Jul 02 08:07:21 AM PDT 24
Peak memory 205744 kb
Host smart-1daa17a3-cdb5-4383-96a9-b5785cee159e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=601570459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.601570459
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2074280454
Short name T320
Test name
Test status
Simulation time 52859250 ps
CPU time 0.73 seconds
Started Jul 02 08:07:13 AM PDT 24
Finished Jul 02 08:07:21 AM PDT 24
Peak memory 205764 kb
Host smart-c4119de8-026d-4b47-8525-d77fe64d52b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2074280454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2074280454
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1694960954
Short name T2740
Test name
Test status
Simulation time 36439964 ps
CPU time 0.64 seconds
Started Jul 02 08:07:13 AM PDT 24
Finished Jul 02 08:07:21 AM PDT 24
Peak memory 205780 kb
Host smart-7651bbeb-d712-4a2b-a92a-074628800b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1694960954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1694960954
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4045242616
Short name T2742
Test name
Test status
Simulation time 39437102 ps
CPU time 0.68 seconds
Started Jul 02 08:07:13 AM PDT 24
Finished Jul 02 08:07:20 AM PDT 24
Peak memory 205796 kb
Host smart-4d7be51d-1078-4e6e-b918-eca288047c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4045242616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.4045242616
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1405174019
Short name T2712
Test name
Test status
Simulation time 95030648 ps
CPU time 1.2 seconds
Started Jul 02 08:06:52 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 222368 kb
Host smart-f8ccb783-904d-419d-929a-a46db56e16b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405174019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1405174019
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3751716505
Short name T289
Test name
Test status
Simulation time 53986093 ps
CPU time 0.86 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:56 AM PDT 24
Peak memory 205764 kb
Host smart-6ee9b485-fa81-449d-902a-84e20797a007
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3751716505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3751716505
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1578955686
Short name T2726
Test name
Test status
Simulation time 44301763 ps
CPU time 0.7 seconds
Started Jul 02 08:06:52 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 205792 kb
Host smart-ae009a32-fc6b-4cff-bbaf-e4e71572156a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1578955686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1578955686
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2517641160
Short name T2731
Test name
Test status
Simulation time 86609389 ps
CPU time 1.23 seconds
Started Jul 02 08:06:54 AM PDT 24
Finished Jul 02 08:06:58 AM PDT 24
Peak memory 205956 kb
Host smart-23f5b351-b7d5-40ec-9cbd-a1252c19ab0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2517641160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2517641160
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1680602588
Short name T2748
Test name
Test status
Simulation time 155483830 ps
CPU time 2.01 seconds
Started Jul 02 08:06:53 AM PDT 24
Finished Jul 02 08:06:58 AM PDT 24
Peak memory 215216 kb
Host smart-20a4a846-7c86-41fd-9a74-bc3fbdc19ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1680602588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1680602588
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2321733778
Short name T326
Test name
Test status
Simulation time 566010765 ps
CPU time 2.65 seconds
Started Jul 02 08:06:50 AM PDT 24
Finished Jul 02 08:06:56 AM PDT 24
Peak memory 205980 kb
Host smart-e951f8ef-717c-479a-8932-c14d1e609808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2321733778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2321733778
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4081038355
Short name T2789
Test name
Test status
Simulation time 227192100 ps
CPU time 2.26 seconds
Started Jul 02 08:06:50 AM PDT 24
Finished Jul 02 08:06:56 AM PDT 24
Peak memory 214216 kb
Host smart-ab78bda0-14bc-41bf-9907-e840a848d9b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081038355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.4081038355
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1109886924
Short name T294
Test name
Test status
Simulation time 97477074 ps
CPU time 0.9 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:56 AM PDT 24
Peak memory 205812 kb
Host smart-96f8a979-3819-4ef4-b4e7-126ad2165194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1109886924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1109886924
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2172774232
Short name T2767
Test name
Test status
Simulation time 42673508 ps
CPU time 0.73 seconds
Started Jul 02 08:06:50 AM PDT 24
Finished Jul 02 08:06:55 AM PDT 24
Peak memory 205948 kb
Host smart-844caa1d-0faf-4ddf-9494-1135658b88ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2172774232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2172774232
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2730851198
Short name T307
Test name
Test status
Simulation time 176485987 ps
CPU time 1.65 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 205860 kb
Host smart-61143f9b-d68d-4d7d-8c5b-eecab355add7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2730851198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2730851198
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.747192221
Short name T215
Test name
Test status
Simulation time 314174894 ps
CPU time 2.72 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:58 AM PDT 24
Peak memory 222104 kb
Host smart-eef33489-8350-4d1d-b92f-47ea6cc65e48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=747192221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.747192221
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3193623099
Short name T2709
Test name
Test status
Simulation time 76507065 ps
CPU time 1.27 seconds
Started Jul 02 08:06:50 AM PDT 24
Finished Jul 02 08:06:55 AM PDT 24
Peak memory 214268 kb
Host smart-8d96aaca-863e-478e-b798-75edfa9826fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193623099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3193623099
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1291233005
Short name T2770
Test name
Test status
Simulation time 78744405 ps
CPU time 1.05 seconds
Started Jul 02 08:06:53 AM PDT 24
Finished Jul 02 08:06:58 AM PDT 24
Peak memory 205984 kb
Host smart-77f5975a-8dd0-4d57-a9ab-a90ed916341f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1291233005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1291233005
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2891239805
Short name T2732
Test name
Test status
Simulation time 38909224 ps
CPU time 0.67 seconds
Started Jul 02 08:06:52 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 205752 kb
Host smart-718cc79b-39bf-4187-86fc-72216d7e0a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2891239805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2891239805
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.848493786
Short name T2756
Test name
Test status
Simulation time 140665350 ps
CPU time 1.49 seconds
Started Jul 02 08:06:52 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 205984 kb
Host smart-15de1003-0034-4587-b7a7-66f72f9b7299
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=848493786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.848493786
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1585978211
Short name T2766
Test name
Test status
Simulation time 413933481 ps
CPU time 2.91 seconds
Started Jul 02 08:06:51 AM PDT 24
Finished Jul 02 08:06:58 AM PDT 24
Peak memory 205980 kb
Host smart-fcc2db60-952f-455c-8856-62525c79172d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1585978211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1585978211
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2688818868
Short name T2713
Test name
Test status
Simulation time 69792996 ps
CPU time 1.27 seconds
Started Jul 02 08:06:58 AM PDT 24
Finished Jul 02 08:07:03 AM PDT 24
Peak memory 214212 kb
Host smart-f439f82d-5d21-497d-b371-474c79667abb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688818868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2688818868
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2234175935
Short name T281
Test name
Test status
Simulation time 51278777 ps
CPU time 1 seconds
Started Jul 02 08:06:53 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 205972 kb
Host smart-4f5c510d-5125-4a48-9379-866fae73ad29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2234175935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2234175935
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.600045042
Short name T309
Test name
Test status
Simulation time 66844834 ps
CPU time 0.69 seconds
Started Jul 02 08:06:50 AM PDT 24
Finished Jul 02 08:06:54 AM PDT 24
Peak memory 205784 kb
Host smart-94660631-6b09-4441-8ae5-62cbbfa28375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=600045042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.600045042
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2046483122
Short name T2791
Test name
Test status
Simulation time 85512970 ps
CPU time 1.08 seconds
Started Jul 02 08:06:52 AM PDT 24
Finished Jul 02 08:06:57 AM PDT 24
Peak memory 205856 kb
Host smart-649e1023-e869-443a-a445-fecf86b58ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2046483122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2046483122
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3499845293
Short name T2805
Test name
Test status
Simulation time 1103950711 ps
CPU time 5.56 seconds
Started Jul 02 08:06:52 AM PDT 24
Finished Jul 02 08:07:02 AM PDT 24
Peak memory 206004 kb
Host smart-663d128a-5154-4194-a9a3-65a70d7082a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3499845293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3499845293
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1455436738
Short name T246
Test name
Test status
Simulation time 45847236 ps
CPU time 0.85 seconds
Started Jul 02 08:06:59 AM PDT 24
Finished Jul 02 08:07:03 AM PDT 24
Peak memory 205848 kb
Host smart-2312bcc5-a9e0-44c3-8d38-601e05cf71aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1455436738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1455436738
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.849529335
Short name T310
Test name
Test status
Simulation time 113301118 ps
CPU time 0.77 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:07 AM PDT 24
Peak memory 205764 kb
Host smart-e6b9d6b2-afea-4c87-a558-e015a08003dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=849529335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.849529335
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.57967840
Short name T295
Test name
Test status
Simulation time 125772495 ps
CPU time 1.27 seconds
Started Jul 02 08:06:59 AM PDT 24
Finished Jul 02 08:07:04 AM PDT 24
Peak memory 205952 kb
Host smart-9a23d068-1aef-4442-bce2-49d6279eb84c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=57967840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.57967840
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1522025267
Short name T260
Test name
Test status
Simulation time 98950311 ps
CPU time 2.7 seconds
Started Jul 02 08:07:01 AM PDT 24
Finished Jul 02 08:07:08 AM PDT 24
Peak memory 222308 kb
Host smart-2709979b-8aae-41e0-bc23-fbd25b2ab781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1522025267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1522025267
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2913295758
Short name T11
Test name
Test status
Simulation time 4187914424 ps
CPU time 5.24 seconds
Started Jul 02 09:05:55 AM PDT 24
Finished Jul 02 09:06:05 AM PDT 24
Peak memory 206504 kb
Host smart-42118d72-aa1e-48f1-bbe5-9a8fe5543a33
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2913295758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.2913295758
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3684796021
Short name T2552
Test name
Test status
Simulation time 13416092064 ps
CPU time 12.08 seconds
Started Jul 02 09:05:56 AM PDT 24
Finished Jul 02 09:06:12 AM PDT 24
Peak memory 206420 kb
Host smart-d2aea852-4f32-48ea-a2c7-abca8e7e5265
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3684796021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3684796021
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3317343537
Short name T706
Test name
Test status
Simulation time 23361846723 ps
CPU time 24.47 seconds
Started Jul 02 09:06:03 AM PDT 24
Finished Jul 02 09:06:30 AM PDT 24
Peak memory 206252 kb
Host smart-afde75b0-929f-40dd-8fc3-16163a8aa43e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3317343537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3317343537
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3624329257
Short name T1158
Test name
Test status
Simulation time 215319349 ps
CPU time 0.9 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:55 AM PDT 24
Peak memory 206180 kb
Host smart-a2700b54-2a12-4a4d-8c35-ecafe42934f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36243
29257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3624329257
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.218923032
Short name T910
Test name
Test status
Simulation time 145417907 ps
CPU time 0.79 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 206140 kb
Host smart-9588dfb4-b16e-4f3f-8dac-1b731474bc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21892
3032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.218923032
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3989210056
Short name T1946
Test name
Test status
Simulation time 257595533 ps
CPU time 1.05 seconds
Started Jul 02 09:05:55 AM PDT 24
Finished Jul 02 09:06:01 AM PDT 24
Peak memory 206176 kb
Host smart-7e674d37-abdd-4f9a-9cd5-32e99541fa8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39892
10056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3989210056
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3821390295
Short name T1740
Test name
Test status
Simulation time 11900293467 ps
CPU time 26.15 seconds
Started Jul 02 09:05:55 AM PDT 24
Finished Jul 02 09:06:26 AM PDT 24
Peak memory 206440 kb
Host smart-bff05fec-1c77-4dc1-b3b8-5e06fa85d965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38213
90295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3821390295
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3744463081
Short name T952
Test name
Test status
Simulation time 489544032 ps
CPU time 1.41 seconds
Started Jul 02 09:05:50 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 206216 kb
Host smart-2421d434-da59-4dbd-b1c7-edf15ce9d912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37444
63081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3744463081
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.484626280
Short name T1084
Test name
Test status
Simulation time 149396181 ps
CPU time 0.76 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:58 AM PDT 24
Peak memory 206220 kb
Host smart-d61053b2-2291-4e61-9817-24ed755cf870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48462
6280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.484626280
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3427982671
Short name T830
Test name
Test status
Simulation time 5112194245 ps
CPU time 137.14 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:08:13 AM PDT 24
Peak memory 206528 kb
Host smart-4ea73d61-467b-4434-81d4-d04ddd6f698e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34279
82671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3427982671
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.2602814136
Short name T630
Test name
Test status
Simulation time 71212242 ps
CPU time 0.75 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:56 AM PDT 24
Peak memory 206212 kb
Host smart-6d8dd979-2b7d-4f22-a9f9-5893c8c96d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26028
14136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2602814136
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2655546789
Short name T2472
Test name
Test status
Simulation time 778834823 ps
CPU time 1.88 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 206404 kb
Host smart-2eac84a8-4aae-44d5-aa0e-da6f3ae2f115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26555
46789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2655546789
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1217741373
Short name T2546
Test name
Test status
Simulation time 223136560 ps
CPU time 1.61 seconds
Started Jul 02 09:05:50 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 206452 kb
Host smart-9deb8464-dbf4-4732-ac96-d884a9db1a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12177
41373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1217741373
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.3416249049
Short name T469
Test name
Test status
Simulation time 121211776937 ps
CPU time 184.77 seconds
Started Jul 02 09:05:54 AM PDT 24
Finished Jul 02 09:09:03 AM PDT 24
Peak memory 206448 kb
Host smart-38b7f4a1-b040-4e92-b0e5-fbe8bfa97a10
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3416249049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.3416249049
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.3200604175
Short name T2079
Test name
Test status
Simulation time 98331700634 ps
CPU time 131.79 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:08:06 AM PDT 24
Peak memory 206468 kb
Host smart-df604b46-bdd2-43d6-b3c2-70d522d0c5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200604175 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.3200604175
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.2586973013
Short name T428
Test name
Test status
Simulation time 88119740123 ps
CPU time 122.89 seconds
Started Jul 02 09:06:00 AM PDT 24
Finished Jul 02 09:08:05 AM PDT 24
Peak memory 206396 kb
Host smart-8e6888ec-df0a-4b5d-8d04-c831c5f3b920
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2586973013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.2586973013
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.76815258
Short name T707
Test name
Test status
Simulation time 119040729585 ps
CPU time 157.02 seconds
Started Jul 02 09:05:56 AM PDT 24
Finished Jul 02 09:08:37 AM PDT 24
Peak memory 206472 kb
Host smart-50cc4c78-7b53-4033-9b9a-afeb5c063178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76815258 -assert nop
ostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.76815258
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3957654698
Short name T580
Test name
Test status
Simulation time 100162188766 ps
CPU time 128 seconds
Started Jul 02 09:05:54 AM PDT 24
Finished Jul 02 09:08:07 AM PDT 24
Peak memory 206440 kb
Host smart-6f19ca8e-3c07-40fe-a42b-bfbf6fda2cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39576
54698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3957654698
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2184404590
Short name T1160
Test name
Test status
Simulation time 166571315 ps
CPU time 0.85 seconds
Started Jul 02 09:05:54 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 206176 kb
Host smart-d14a53b0-5448-4686-981b-9c9a072ed8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21844
04590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2184404590
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2342995529
Short name T924
Test name
Test status
Simulation time 139647095 ps
CPU time 0.78 seconds
Started Jul 02 09:05:54 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 206156 kb
Host smart-55703656-778a-4752-a9de-021e61754a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23429
95529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2342995529
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.550103242
Short name T1570
Test name
Test status
Simulation time 213048147 ps
CPU time 0.92 seconds
Started Jul 02 09:05:48 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 206392 kb
Host smart-879c600a-7e61-4dfa-86d5-b1bf9becb47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55010
3242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.550103242
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3188494999
Short name T1643
Test name
Test status
Simulation time 231622289 ps
CPU time 0.93 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:06 AM PDT 24
Peak memory 206176 kb
Host smart-3adf98e5-b9d5-4d45-91c8-21ed33fe8f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31884
94999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3188494999
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.892964657
Short name T70
Test name
Test status
Simulation time 539731059 ps
CPU time 1.32 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 206212 kb
Host smart-a1ca75c5-2567-4a3a-bbd2-88ec3fdb6a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89296
4657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.892964657
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.680289673
Short name T1866
Test name
Test status
Simulation time 23335948509 ps
CPU time 21.6 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:06:18 AM PDT 24
Peak memory 206232 kb
Host smart-f2b4ea71-009f-4f19-9783-6f6b0956ea51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68028
9673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.680289673
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2001770794
Short name T1736
Test name
Test status
Simulation time 3315049893 ps
CPU time 4.02 seconds
Started Jul 02 09:06:00 AM PDT 24
Finished Jul 02 09:06:07 AM PDT 24
Peak memory 206208 kb
Host smart-d7e8922c-eadc-477b-a245-35600e246ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20017
70794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2001770794
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.2820842562
Short name T154
Test name
Test status
Simulation time 10684945018 ps
CPU time 283.88 seconds
Started Jul 02 09:05:50 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206472 kb
Host smart-3c5e8978-0ec3-45b0-a172-fa629f90b887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28208
42562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.2820842562
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3691644008
Short name T1041
Test name
Test status
Simulation time 3097059627 ps
CPU time 21.27 seconds
Started Jul 02 09:05:58 AM PDT 24
Finished Jul 02 09:06:23 AM PDT 24
Peak memory 206364 kb
Host smart-1ca253cd-5944-44c5-af79-42ecdedfaa30
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3691644008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3691644008
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2787998213
Short name T2144
Test name
Test status
Simulation time 239325263 ps
CPU time 0.93 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:06 AM PDT 24
Peak memory 206188 kb
Host smart-bbdd345d-5b5e-477b-8dd8-b315e1db0f7a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2787998213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2787998213
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2913468698
Short name T2676
Test name
Test status
Simulation time 186388004 ps
CPU time 0.85 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:58 AM PDT 24
Peak memory 206180 kb
Host smart-784ac52b-1acf-47af-b0d7-cdbfbddae2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29134
68698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2913468698
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.3691248308
Short name T2506
Test name
Test status
Simulation time 4443280418 ps
CPU time 126.87 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:08:11 AM PDT 24
Peak memory 206400 kb
Host smart-27e91427-9f91-4402-a19e-d7047a99f54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36912
48308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3691248308
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.35145681
Short name T1242
Test name
Test status
Simulation time 5897058141 ps
CPU time 40.9 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:06:39 AM PDT 24
Peak memory 206440 kb
Host smart-22367344-4abd-4bb1-aa1c-6463bf21c206
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=35145681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.35145681
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1023914536
Short name T593
Test name
Test status
Simulation time 148514867 ps
CPU time 0.85 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 206164 kb
Host smart-ba5b1b64-7c6e-4526-8aee-8405a29db9a1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1023914536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1023914536
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2171988527
Short name T722
Test name
Test status
Simulation time 158850321 ps
CPU time 0.8 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:58 AM PDT 24
Peak memory 206208 kb
Host smart-74e0abd9-b583-4a0c-ae85-21539bb7777b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21719
88527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2171988527
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.4035367120
Short name T71
Test name
Test status
Simulation time 488871719 ps
CPU time 1.32 seconds
Started Jul 02 09:05:58 AM PDT 24
Finished Jul 02 09:06:02 AM PDT 24
Peak memory 206164 kb
Host smart-7d64e91a-5bdd-4c25-b58f-84b27a8550e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40353
67120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.4035367120
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1415047926
Short name T2480
Test name
Test status
Simulation time 166960738 ps
CPU time 0.82 seconds
Started Jul 02 09:06:12 AM PDT 24
Finished Jul 02 09:06:15 AM PDT 24
Peak memory 206212 kb
Host smart-c44cf608-5c65-4449-9f4a-fa40f2bd5780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14150
47926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1415047926
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3486724591
Short name T2600
Test name
Test status
Simulation time 149641918 ps
CPU time 0.75 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:58 AM PDT 24
Peak memory 206180 kb
Host smart-ed8b8699-79ec-4bb4-a305-b567ceb18d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34867
24591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3486724591
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2082369793
Short name T2363
Test name
Test status
Simulation time 181711885 ps
CPU time 0.81 seconds
Started Jul 02 09:05:55 AM PDT 24
Finished Jul 02 09:06:01 AM PDT 24
Peak memory 206128 kb
Host smart-927b1e79-3297-4b9c-b1e3-931d5b4faf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20823
69793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2082369793
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3230855499
Short name T909
Test name
Test status
Simulation time 144919957 ps
CPU time 0.84 seconds
Started Jul 02 09:06:01 AM PDT 24
Finished Jul 02 09:06:04 AM PDT 24
Peak memory 206212 kb
Host smart-258f111c-2a64-4d50-b5b4-06ad7d62f980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32308
55499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3230855499
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.450686936
Short name T2063
Test name
Test status
Simulation time 231109492 ps
CPU time 0.93 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:05 AM PDT 24
Peak memory 206204 kb
Host smart-222cb2a0-abf0-4df8-9f58-62d92fdd0d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45068
6936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.450686936
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.178671685
Short name T2071
Test name
Test status
Simulation time 238352487 ps
CPU time 0.9 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 206168 kb
Host smart-42094b01-530a-4052-9897-55a8e5ebe5aa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=178671685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.178671685
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.756829293
Short name T2592
Test name
Test status
Simulation time 206628921 ps
CPU time 0.96 seconds
Started Jul 02 09:06:12 AM PDT 24
Finished Jul 02 09:06:15 AM PDT 24
Peak memory 206212 kb
Host smart-498fd235-bb93-46ec-99d7-0c9aea46de9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75682
9293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.756829293
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.753103392
Short name T814
Test name
Test status
Simulation time 237504571 ps
CPU time 1.01 seconds
Started Jul 02 09:05:57 AM PDT 24
Finished Jul 02 09:06:02 AM PDT 24
Peak memory 206188 kb
Host smart-2af3a8ea-71d6-49d2-bbc0-9b735a0ecede
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=753103392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.753103392
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.3125337451
Short name T219
Test name
Test status
Simulation time 229375145 ps
CPU time 0.93 seconds
Started Jul 02 09:05:55 AM PDT 24
Finished Jul 02 09:06:01 AM PDT 24
Peak memory 206100 kb
Host smart-defb1631-ffb3-4fa1-8c8c-ab68f51ea7bd
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3125337451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.3125337451
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1751090831
Short name T1028
Test name
Test status
Simulation time 148549900 ps
CPU time 0.75 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:58 AM PDT 24
Peak memory 206160 kb
Host smart-5a2c6874-15d2-4035-aab3-1471e72e1c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17510
90831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1751090831
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3742346725
Short name T1534
Test name
Test status
Simulation time 108497034 ps
CPU time 0.77 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:05 AM PDT 24
Peak memory 206116 kb
Host smart-62d8277f-e8c4-422a-91bb-03e7ae8582a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37423
46725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3742346725
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.819149444
Short name T300
Test name
Test status
Simulation time 11193655649 ps
CPU time 24.61 seconds
Started Jul 02 09:05:56 AM PDT 24
Finished Jul 02 09:06:25 AM PDT 24
Peak memory 206528 kb
Host smart-ad38887e-962d-4eb0-9556-500427321016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81914
9444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.819149444
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1920178358
Short name T1351
Test name
Test status
Simulation time 182199006 ps
CPU time 0.88 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:05 AM PDT 24
Peak memory 206116 kb
Host smart-a25024fa-efc4-4522-a9b5-f5c9bd3b0071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19201
78358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1920178358
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1849863219
Short name T2001
Test name
Test status
Simulation time 15919967723 ps
CPU time 85.88 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:07:30 AM PDT 24
Peak memory 206348 kb
Host smart-9873e662-6c7e-4d62-a45b-8543a569e620
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1849863219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1849863219
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.523117366
Short name T170
Test name
Test status
Simulation time 17558704463 ps
CPU time 103.25 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:07:40 AM PDT 24
Peak memory 206656 kb
Host smart-a5016d8d-4514-44d1-a907-1724bfd377e4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=523117366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.523117366
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.647799558
Short name T2670
Test name
Test status
Simulation time 6712540876 ps
CPU time 33.77 seconds
Started Jul 02 09:06:12 AM PDT 24
Finished Jul 02 09:06:48 AM PDT 24
Peak memory 206444 kb
Host smart-f3ddf751-dd56-4aa4-a03b-ebce6f72c3c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=647799558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.647799558
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3439989661
Short name T639
Test name
Test status
Simulation time 165878837 ps
CPU time 0.82 seconds
Started Jul 02 09:06:00 AM PDT 24
Finished Jul 02 09:06:03 AM PDT 24
Peak memory 206152 kb
Host smart-beb6e9c7-1aa2-44a5-b0cc-a961317468e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399
89661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3439989661
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1385841029
Short name T2624
Test name
Test status
Simulation time 186255449 ps
CPU time 0.83 seconds
Started Jul 02 09:06:04 AM PDT 24
Finished Jul 02 09:06:08 AM PDT 24
Peak memory 206180 kb
Host smart-77174ff1-f251-419a-ae50-43c015f034bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13858
41029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1385841029
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1964010922
Short name T2489
Test name
Test status
Simulation time 171417585 ps
CPU time 0.78 seconds
Started Jul 02 09:06:00 AM PDT 24
Finished Jul 02 09:06:03 AM PDT 24
Peak memory 206336 kb
Host smart-5f21fc47-0428-49ea-8b09-7dd9e340c77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19640
10922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1964010922
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.4238004469
Short name T230
Test name
Test status
Simulation time 302648809 ps
CPU time 1.13 seconds
Started Jul 02 09:05:56 AM PDT 24
Finished Jul 02 09:06:01 AM PDT 24
Peak memory 224068 kb
Host smart-3484620a-eb52-4758-8297-8b356611be3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4238004469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.4238004469
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.2269403380
Short name T2690
Test name
Test status
Simulation time 227551901 ps
CPU time 0.89 seconds
Started Jul 02 09:05:55 AM PDT 24
Finished Jul 02 09:06:01 AM PDT 24
Peak memory 206224 kb
Host smart-d12a8639-e8f3-4de6-a60f-b4b92ab2af91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22694
03380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2269403380
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3404950209
Short name T1301
Test name
Test status
Simulation time 149417807 ps
CPU time 0.8 seconds
Started Jul 02 09:06:18 AM PDT 24
Finished Jul 02 09:06:19 AM PDT 24
Peak memory 206204 kb
Host smart-53701c9e-9dd7-493d-8ec7-76cabf0cada5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34049
50209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3404950209
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1817067668
Short name T572
Test name
Test status
Simulation time 227447506 ps
CPU time 0.91 seconds
Started Jul 02 09:06:08 AM PDT 24
Finished Jul 02 09:06:12 AM PDT 24
Peak memory 206160 kb
Host smart-7a6f6865-f418-48aa-ab65-fcba1cd3b5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18170
67668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1817067668
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1344455856
Short name T2196
Test name
Test status
Simulation time 284665409 ps
CPU time 1.02 seconds
Started Jul 02 09:06:05 AM PDT 24
Finished Jul 02 09:06:09 AM PDT 24
Peak memory 206212 kb
Host smart-4736d74f-2d18-4824-ae3b-986d92eb5645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13444
55856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1344455856
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2276131600
Short name T2101
Test name
Test status
Simulation time 4877980973 ps
CPU time 131.63 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:08:17 AM PDT 24
Peak memory 206472 kb
Host smart-88880c9d-f515-405e-b13e-0c5966c43658
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2276131600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2276131600
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2650694938
Short name T2341
Test name
Test status
Simulation time 223800128 ps
CPU time 0.84 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:06 AM PDT 24
Peak memory 206096 kb
Host smart-c1b18ebe-8cdc-42b2-8c92-26f0597886e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26506
94938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2650694938
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3697149844
Short name T1764
Test name
Test status
Simulation time 177937107 ps
CPU time 0.82 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:06 AM PDT 24
Peak memory 206136 kb
Host smart-b48be7e6-95d8-4b9a-a52d-6a2399fe5727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36971
49844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3697149844
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.4171310712
Short name T1004
Test name
Test status
Simulation time 664579956 ps
CPU time 1.62 seconds
Started Jul 02 09:06:00 AM PDT 24
Finished Jul 02 09:06:04 AM PDT 24
Peak memory 206216 kb
Host smart-95674f92-9535-4cc0-939f-4fac32ad2f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41713
10712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.4171310712
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3805957208
Short name T594
Test name
Test status
Simulation time 5109123142 ps
CPU time 45.21 seconds
Started Jul 02 09:06:03 AM PDT 24
Finished Jul 02 09:06:51 AM PDT 24
Peak memory 206476 kb
Host smart-b057fd87-aed2-4d44-a15b-70e75d8dabb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38059
57208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3805957208
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2782634080
Short name T176
Test name
Test status
Simulation time 12271044272 ps
CPU time 337.6 seconds
Started Jul 02 09:06:03 AM PDT 24
Finished Jul 02 09:11:43 AM PDT 24
Peak memory 206552 kb
Host smart-7b643cff-6984-4daa-9c24-cef20b80ad03
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2782634080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2782634080
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.3513258833
Short name T2349
Test name
Test status
Simulation time 66423416 ps
CPU time 0.73 seconds
Started Jul 02 09:06:14 AM PDT 24
Finished Jul 02 09:06:16 AM PDT 24
Peak memory 206248 kb
Host smart-a69172bc-c9ce-438b-97fd-7a063dad41ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3513258833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.3513258833
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3026054274
Short name T1754
Test name
Test status
Simulation time 3907671995 ps
CPU time 4.78 seconds
Started Jul 02 09:05:57 AM PDT 24
Finished Jul 02 09:06:05 AM PDT 24
Peak memory 206236 kb
Host smart-0ed21ff4-c585-48cf-a5b8-3e4232ff5586
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3026054274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.3026054274
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1418618201
Short name T1353
Test name
Test status
Simulation time 13306126081 ps
CPU time 14.31 seconds
Started Jul 02 09:06:04 AM PDT 24
Finished Jul 02 09:06:22 AM PDT 24
Peak memory 206424 kb
Host smart-89539662-39d3-4518-a97d-887de4ce3b17
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1418618201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1418618201
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.663133850
Short name T2083
Test name
Test status
Simulation time 23380637294 ps
CPU time 21.33 seconds
Started Jul 02 09:06:14 AM PDT 24
Finished Jul 02 09:06:37 AM PDT 24
Peak memory 206400 kb
Host smart-9db1f09f-4735-450f-a6e7-36bbd274209f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=663133850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.663133850
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1472470095
Short name T1737
Test name
Test status
Simulation time 146638891 ps
CPU time 0.8 seconds
Started Jul 02 09:06:03 AM PDT 24
Finished Jul 02 09:06:07 AM PDT 24
Peak memory 206216 kb
Host smart-c5f13ecd-7238-4c3a-942f-432f6f07d7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14724
70095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1472470095
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1278868331
Short name T2426
Test name
Test status
Simulation time 181655822 ps
CPU time 0.85 seconds
Started Jul 02 09:05:58 AM PDT 24
Finished Jul 02 09:06:02 AM PDT 24
Peak memory 206124 kb
Host smart-83554a0e-d0ca-4725-8e68-abf71377bfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12788
68331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1278868331
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.720320840
Short name T67
Test name
Test status
Simulation time 161425616 ps
CPU time 0.82 seconds
Started Jul 02 09:06:06 AM PDT 24
Finished Jul 02 09:06:10 AM PDT 24
Peak memory 206200 kb
Host smart-31a64c0e-d11f-424a-9f97-89f8b4931dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72032
0840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.720320840
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.662625266
Short name T883
Test name
Test status
Simulation time 149368000 ps
CPU time 0.79 seconds
Started Jul 02 09:06:01 AM PDT 24
Finished Jul 02 09:06:04 AM PDT 24
Peak memory 206160 kb
Host smart-e2082224-eaca-433f-9486-6e763f34cd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66262
5266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.662625266
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2232343637
Short name T584
Test name
Test status
Simulation time 194165277 ps
CPU time 0.84 seconds
Started Jul 02 09:05:58 AM PDT 24
Finished Jul 02 09:06:02 AM PDT 24
Peak memory 206164 kb
Host smart-b5f12cbb-2b85-4317-9646-d588379577ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22323
43637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2232343637
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.3160377794
Short name T196
Test name
Test status
Simulation time 841636830 ps
CPU time 2.06 seconds
Started Jul 02 09:06:06 AM PDT 24
Finished Jul 02 09:06:11 AM PDT 24
Peak memory 206408 kb
Host smart-de672ddb-27ce-4092-a8e3-aa3fb49a8894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31603
77794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3160377794
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.1313241589
Short name T182
Test name
Test status
Simulation time 16048651760 ps
CPU time 29.52 seconds
Started Jul 02 09:05:57 AM PDT 24
Finished Jul 02 09:06:30 AM PDT 24
Peak memory 206520 kb
Host smart-8556366f-a99e-41f4-b025-ff58d006a9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13132
41589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.1313241589
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.986659146
Short name T363
Test name
Test status
Simulation time 416916184 ps
CPU time 1.28 seconds
Started Jul 02 09:06:07 AM PDT 24
Finished Jul 02 09:06:11 AM PDT 24
Peak memory 206224 kb
Host smart-8be5747f-2ecd-48ca-992a-5732631e455f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98665
9146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.986659146
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2811531075
Short name T494
Test name
Test status
Simulation time 143434663 ps
CPU time 0.78 seconds
Started Jul 02 09:06:06 AM PDT 24
Finished Jul 02 09:06:09 AM PDT 24
Peak memory 206212 kb
Host smart-fd394d48-eff0-41a0-9c81-07baec660c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28115
31075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2811531075
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1913065003
Short name T2108
Test name
Test status
Simulation time 39926178 ps
CPU time 0.66 seconds
Started Jul 02 09:05:58 AM PDT 24
Finished Jul 02 09:06:02 AM PDT 24
Peak memory 206176 kb
Host smart-8a9245ca-8c65-4204-b2c9-0af9c1149f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19130
65003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1913065003
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.180414950
Short name T1563
Test name
Test status
Simulation time 985999496 ps
CPU time 2.5 seconds
Started Jul 02 09:06:06 AM PDT 24
Finished Jul 02 09:06:11 AM PDT 24
Peak memory 206456 kb
Host smart-4fb436da-6d28-434f-9381-1f11e7b93466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18041
4950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.180414950
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.777179243
Short name T1430
Test name
Test status
Simulation time 145935777 ps
CPU time 1.18 seconds
Started Jul 02 09:06:04 AM PDT 24
Finished Jul 02 09:06:08 AM PDT 24
Peak memory 206408 kb
Host smart-332f4dbb-af20-49e4-b616-923218357667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77717
9243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.777179243
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.2056415994
Short name T2288
Test name
Test status
Simulation time 113189621609 ps
CPU time 153.19 seconds
Started Jul 02 09:06:05 AM PDT 24
Finished Jul 02 09:08:41 AM PDT 24
Peak memory 206404 kb
Host smart-161c1262-478c-4404-a3cd-72a29364d516
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2056415994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.2056415994
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.3599995884
Short name T715
Test name
Test status
Simulation time 111397524828 ps
CPU time 141.47 seconds
Started Jul 02 09:06:14 AM PDT 24
Finished Jul 02 09:08:37 AM PDT 24
Peak memory 206424 kb
Host smart-8f7a8bd8-0b0c-42c9-8f84-05fb301844dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599995884 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.3599995884
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.3145692592
Short name T1356
Test name
Test status
Simulation time 103105619678 ps
CPU time 134.36 seconds
Started Jul 02 09:06:14 AM PDT 24
Finished Jul 02 09:08:30 AM PDT 24
Peak memory 206412 kb
Host smart-74094c08-19b4-4d8a-9491-977e8571aa3e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3145692592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.3145692592
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.4259855874
Short name T973
Test name
Test status
Simulation time 100170365718 ps
CPU time 154.75 seconds
Started Jul 02 09:06:08 AM PDT 24
Finished Jul 02 09:08:45 AM PDT 24
Peak memory 206440 kb
Host smart-063a000a-d9a2-46f1-89ee-af1f267f5d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259855874 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.4259855874
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.1120447561
Short name T918
Test name
Test status
Simulation time 107154378389 ps
CPU time 149.5 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:08:35 AM PDT 24
Peak memory 206652 kb
Host smart-f096b79f-bdd5-4af8-b425-da0b1c3798b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11204
47561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.1120447561
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1217484576
Short name T1842
Test name
Test status
Simulation time 229964080 ps
CPU time 0.86 seconds
Started Jul 02 09:06:07 AM PDT 24
Finished Jul 02 09:06:11 AM PDT 24
Peak memory 206164 kb
Host smart-993f8d2e-e4e0-4d7d-a23d-56751fda53a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12174
84576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1217484576
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.726761421
Short name T1146
Test name
Test status
Simulation time 176643159 ps
CPU time 0.83 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:06 AM PDT 24
Peak memory 206160 kb
Host smart-d31bcb11-7882-40a7-a06d-a1a5bbec2b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72676
1421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.726761421
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1362958655
Short name T1314
Test name
Test status
Simulation time 280195621 ps
CPU time 0.98 seconds
Started Jul 02 09:06:16 AM PDT 24
Finished Jul 02 09:06:18 AM PDT 24
Peak memory 206200 kb
Host smart-9b3248f9-3a5f-429d-8f4b-c8336c854555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13629
58655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1362958655
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.574542102
Short name T78
Test name
Test status
Simulation time 5792366578 ps
CPU time 56.74 seconds
Started Jul 02 09:06:16 AM PDT 24
Finished Jul 02 09:07:14 AM PDT 24
Peak memory 206456 kb
Host smart-168a66ea-399f-4d2f-b2d9-6fbb62f9671b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=574542102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.574542102
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3988583063
Short name T2004
Test name
Test status
Simulation time 225214303 ps
CPU time 0.93 seconds
Started Jul 02 09:06:01 AM PDT 24
Finished Jul 02 09:06:04 AM PDT 24
Peak memory 206184 kb
Host smart-08d1f98a-c860-4078-99f7-c56d422e98c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39885
83063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3988583063
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.3234418415
Short name T1696
Test name
Test status
Simulation time 23284986310 ps
CPU time 22.54 seconds
Started Jul 02 09:06:01 AM PDT 24
Finished Jul 02 09:06:26 AM PDT 24
Peak memory 206220 kb
Host smart-c0caeba1-82d6-49a9-8e50-17f1c2dcac6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32344
18415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.3234418415
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3209528266
Short name T1657
Test name
Test status
Simulation time 3298114558 ps
CPU time 4.16 seconds
Started Jul 02 09:06:03 AM PDT 24
Finished Jul 02 09:06:10 AM PDT 24
Peak memory 206208 kb
Host smart-24f0d8a9-0eeb-4001-954e-b59ca71650a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32095
28266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3209528266
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.3955348188
Short name T2479
Test name
Test status
Simulation time 7761327493 ps
CPU time 57.36 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:07:02 AM PDT 24
Peak memory 206524 kb
Host smart-9fd6eab9-0edf-494d-bfaf-529b32e8d3c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
48188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.3955348188
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1110666511
Short name T1229
Test name
Test status
Simulation time 5401786524 ps
CPU time 49 seconds
Started Jul 02 09:06:03 AM PDT 24
Finished Jul 02 09:06:55 AM PDT 24
Peak memory 206460 kb
Host smart-3a8f2138-b31d-4b46-9603-2feb6eb62d78
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1110666511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1110666511
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.2365245357
Short name T1083
Test name
Test status
Simulation time 238664791 ps
CPU time 0.86 seconds
Started Jul 02 09:06:08 AM PDT 24
Finished Jul 02 09:06:12 AM PDT 24
Peak memory 206144 kb
Host smart-8e5010be-2be9-4584-b771-3084696a4fed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2365245357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.2365245357
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2706709017
Short name T1716
Test name
Test status
Simulation time 214300524 ps
CPU time 0.96 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:05 AM PDT 24
Peak memory 206216 kb
Host smart-f0592937-bb8a-4412-990f-f161f07ded5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27067
09017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2706709017
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3431299827
Short name T747
Test name
Test status
Simulation time 4913427833 ps
CPU time 134.31 seconds
Started Jul 02 09:06:06 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206468 kb
Host smart-400c7345-852e-423b-bd92-975cad38d7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34312
99827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3431299827
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.1084107698
Short name T1695
Test name
Test status
Simulation time 5238750266 ps
CPU time 45.29 seconds
Started Jul 02 09:06:00 AM PDT 24
Finished Jul 02 09:06:47 AM PDT 24
Peak memory 206360 kb
Host smart-febf9214-0065-42aa-b138-0349f675dff4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1084107698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.1084107698
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.4087927116
Short name T1246
Test name
Test status
Simulation time 151159325 ps
CPU time 0.82 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:06 AM PDT 24
Peak memory 206144 kb
Host smart-ac4e5de6-793f-4a89-b2c4-ca137db342fe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4087927116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.4087927116
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1020433840
Short name T711
Test name
Test status
Simulation time 162173275 ps
CPU time 0.8 seconds
Started Jul 02 09:06:11 AM PDT 24
Finished Jul 02 09:06:13 AM PDT 24
Peak memory 206132 kb
Host smart-d0577755-c00b-44ec-8c60-eb6c48ceb957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204
33840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1020433840
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.239565736
Short name T102
Test name
Test status
Simulation time 155327503 ps
CPU time 0.76 seconds
Started Jul 02 09:06:05 AM PDT 24
Finished Jul 02 09:06:09 AM PDT 24
Peak memory 206196 kb
Host smart-876209e0-c73b-40bd-a2fb-8d588efaa09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23956
5736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.239565736
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.585201880
Short name T860
Test name
Test status
Simulation time 209471189 ps
CPU time 0.82 seconds
Started Jul 02 09:06:04 AM PDT 24
Finished Jul 02 09:06:08 AM PDT 24
Peak memory 206212 kb
Host smart-1e70a9a7-0222-4914-ad92-43fc2d46847c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58520
1880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.585201880
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.4081602316
Short name T1681
Test name
Test status
Simulation time 159606736 ps
CPU time 0.77 seconds
Started Jul 02 09:06:06 AM PDT 24
Finished Jul 02 09:06:09 AM PDT 24
Peak memory 206188 kb
Host smart-a3c50120-f950-4241-adc1-26d10d1bdfad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40816
02316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.4081602316
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2671095836
Short name T638
Test name
Test status
Simulation time 151983695 ps
CPU time 0.82 seconds
Started Jul 02 09:06:11 AM PDT 24
Finished Jul 02 09:06:14 AM PDT 24
Peak memory 206208 kb
Host smart-1ff814a3-529e-4cda-a767-a252d007f152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26710
95836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2671095836
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.1868097424
Short name T1427
Test name
Test status
Simulation time 236750977 ps
CPU time 0.96 seconds
Started Jul 02 09:06:06 AM PDT 24
Finished Jul 02 09:06:10 AM PDT 24
Peak memory 206192 kb
Host smart-872b9790-7663-46d7-a32e-688355616509
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1868097424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1868097424
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1893379050
Short name T153
Test name
Test status
Simulation time 226741723 ps
CPU time 0.99 seconds
Started Jul 02 09:06:05 AM PDT 24
Finished Jul 02 09:06:09 AM PDT 24
Peak memory 206204 kb
Host smart-8bd371f4-f3ca-4877-a610-c620f0969b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18933
79050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1893379050
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.737947737
Short name T986
Test name
Test status
Simulation time 152173636 ps
CPU time 0.79 seconds
Started Jul 02 09:06:09 AM PDT 24
Finished Jul 02 09:06:12 AM PDT 24
Peak memory 206192 kb
Host smart-72835438-aca1-45bb-93b6-76171ad3f4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73794
7737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.737947737
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1023273470
Short name T1729
Test name
Test status
Simulation time 96646582 ps
CPU time 0.76 seconds
Started Jul 02 09:06:06 AM PDT 24
Finished Jul 02 09:06:09 AM PDT 24
Peak memory 206168 kb
Host smart-3744d2f0-3952-443d-a66e-033f58161eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10232
73470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1023273470
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.348153192
Short name T277
Test name
Test status
Simulation time 18017307592 ps
CPU time 40.23 seconds
Started Jul 02 09:06:13 AM PDT 24
Finished Jul 02 09:06:54 AM PDT 24
Peak memory 206508 kb
Host smart-ff363693-3c11-4ac0-b2ef-b1cd5917c067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34815
3192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.348153192
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1812172559
Short name T1094
Test name
Test status
Simulation time 229771632 ps
CPU time 0.88 seconds
Started Jul 02 09:06:09 AM PDT 24
Finished Jul 02 09:06:13 AM PDT 24
Peak memory 206224 kb
Host smart-9004d425-097f-42b3-9a76-606f5d7da0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18121
72559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1812172559
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.766507019
Short name T1554
Test name
Test status
Simulation time 187460141 ps
CPU time 0.84 seconds
Started Jul 02 09:06:07 AM PDT 24
Finished Jul 02 09:06:10 AM PDT 24
Peak memory 206204 kb
Host smart-3436b307-2ac0-4cf7-a9f5-6e95d4265e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76650
7019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.766507019
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2097902316
Short name T1340
Test name
Test status
Simulation time 7802520614 ps
CPU time 116.19 seconds
Started Jul 02 09:06:13 AM PDT 24
Finished Jul 02 09:08:11 AM PDT 24
Peak memory 206460 kb
Host smart-bf058d13-abf3-4d83-845f-5bd345cf50fa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2097902316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2097902316
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.4070571355
Short name T1533
Test name
Test status
Simulation time 12607895902 ps
CPU time 242.43 seconds
Started Jul 02 09:06:15 AM PDT 24
Finished Jul 02 09:10:19 AM PDT 24
Peak memory 206456 kb
Host smart-d1ce3a00-d50b-47a7-9904-174b0e90c07b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4070571355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.4070571355
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.1419107075
Short name T2501
Test name
Test status
Simulation time 227292383 ps
CPU time 1.02 seconds
Started Jul 02 09:06:07 AM PDT 24
Finished Jul 02 09:06:10 AM PDT 24
Peak memory 206212 kb
Host smart-1371369a-7205-4a9f-9e2d-7f9dc0a52a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14191
07075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.1419107075
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2256903581
Short name T807
Test name
Test status
Simulation time 152315010 ps
CPU time 0.77 seconds
Started Jul 02 09:06:14 AM PDT 24
Finished Jul 02 09:06:17 AM PDT 24
Peak memory 206220 kb
Host smart-5f020c83-a29b-4770-a861-22d1c81bb145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22569
03581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2256903581
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.882370540
Short name T1088
Test name
Test status
Simulation time 144377556 ps
CPU time 0.79 seconds
Started Jul 02 09:06:09 AM PDT 24
Finished Jul 02 09:06:12 AM PDT 24
Peak memory 206200 kb
Host smart-f1908f9a-739e-4cb0-804a-c634649cdbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88237
0540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.882370540
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3653697669
Short name T74
Test name
Test status
Simulation time 248066970 ps
CPU time 0.91 seconds
Started Jul 02 09:06:11 AM PDT 24
Finished Jul 02 09:06:14 AM PDT 24
Peak memory 206196 kb
Host smart-631e7f96-7697-423e-9e37-0da883ce2f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36536
97669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3653697669
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1593454185
Short name T231
Test name
Test status
Simulation time 207842391 ps
CPU time 1.06 seconds
Started Jul 02 09:06:10 AM PDT 24
Finished Jul 02 09:06:14 AM PDT 24
Peak memory 224060 kb
Host smart-089f0092-5142-4ad1-b209-c38554bed849
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1593454185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1593454185
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1941847207
Short name T60
Test name
Test status
Simulation time 468487168 ps
CPU time 1.36 seconds
Started Jul 02 09:06:07 AM PDT 24
Finished Jul 02 09:06:11 AM PDT 24
Peak memory 206128 kb
Host smart-7b5f6bb0-afb2-4694-a76a-4a707793ca43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19418
47207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1941847207
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.1367741482
Short name T1338
Test name
Test status
Simulation time 200770871 ps
CPU time 0.89 seconds
Started Jul 02 09:06:10 AM PDT 24
Finished Jul 02 09:06:13 AM PDT 24
Peak memory 206192 kb
Host smart-6c297e50-3445-4df8-8b63-1582ce18fcb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13677
41482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.1367741482
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.598063719
Short name T413
Test name
Test status
Simulation time 178768720 ps
CPU time 0.8 seconds
Started Jul 02 09:06:11 AM PDT 24
Finished Jul 02 09:06:14 AM PDT 24
Peak memory 206180 kb
Host smart-76a5071b-bbdd-48b6-abad-e5fd62d7f832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59806
3719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.598063719
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2091257339
Short name T1115
Test name
Test status
Simulation time 171602271 ps
CPU time 0.81 seconds
Started Jul 02 09:06:11 AM PDT 24
Finished Jul 02 09:06:14 AM PDT 24
Peak memory 206172 kb
Host smart-f61a1bb7-8d07-417b-8f6d-5d9c552c3d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20912
57339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2091257339
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.169344249
Short name T1923
Test name
Test status
Simulation time 218759263 ps
CPU time 0.98 seconds
Started Jul 02 09:06:09 AM PDT 24
Finished Jul 02 09:06:12 AM PDT 24
Peak memory 206168 kb
Host smart-d14a50ed-ca34-479f-ab55-f2dbbae87f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16934
4249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.169344249
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1656228994
Short name T148
Test name
Test status
Simulation time 174214149 ps
CPU time 0.8 seconds
Started Jul 02 09:06:13 AM PDT 24
Finished Jul 02 09:06:15 AM PDT 24
Peak memory 206216 kb
Host smart-a93f4bb8-f1d3-4634-a4ae-7e6cca37592f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16562
28994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1656228994
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1556440066
Short name T2510
Test name
Test status
Simulation time 172772409 ps
CPU time 0.79 seconds
Started Jul 02 09:06:09 AM PDT 24
Finished Jul 02 09:06:13 AM PDT 24
Peak memory 206196 kb
Host smart-b9467277-88c9-463e-92ca-02461397e257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15564
40066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1556440066
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.743670055
Short name T349
Test name
Test status
Simulation time 1356653441 ps
CPU time 2.82 seconds
Started Jul 02 09:06:07 AM PDT 24
Finished Jul 02 09:06:13 AM PDT 24
Peak memory 206460 kb
Host smart-db606f77-4b84-424e-8ed0-aae6b80fe4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74367
0055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.743670055
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.4032475300
Short name T1378
Test name
Test status
Simulation time 3380258553 ps
CPU time 32.79 seconds
Started Jul 02 09:06:15 AM PDT 24
Finished Jul 02 09:06:49 AM PDT 24
Peak memory 206516 kb
Host smart-0d02ff0f-6ec5-4214-9fc9-fa26d317dbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40324
75300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.4032475300
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1812723521
Short name T189
Test name
Test status
Simulation time 11731543164 ps
CPU time 76.86 seconds
Started Jul 02 09:06:10 AM PDT 24
Finished Jul 02 09:07:29 AM PDT 24
Peak memory 206492 kb
Host smart-deca1d24-2a4a-4d13-b0f1-6088d3cf4493
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1812723521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1812723521
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.4203049493
Short name T2669
Test name
Test status
Simulation time 102522022 ps
CPU time 0.74 seconds
Started Jul 02 09:07:47 AM PDT 24
Finished Jul 02 09:07:49 AM PDT 24
Peak memory 206164 kb
Host smart-36a66665-fdad-4d92-bd6c-0b551873802c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4203049493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.4203049493
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3316672972
Short name T785
Test name
Test status
Simulation time 3750463754 ps
CPU time 5.44 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206252 kb
Host smart-86e90634-f727-4c49-a898-48039e390e7b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3316672972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.3316672972
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.243376615
Short name T2459
Test name
Test status
Simulation time 13334955381 ps
CPU time 11.92 seconds
Started Jul 02 09:07:42 AM PDT 24
Finished Jul 02 09:07:56 AM PDT 24
Peak memory 206484 kb
Host smart-82a08279-89af-44da-9a37-72407342e6b5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=243376615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.243376615
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.2763058301
Short name T1569
Test name
Test status
Simulation time 23340287385 ps
CPU time 26.14 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:08:08 AM PDT 24
Peak memory 206240 kb
Host smart-ed6f6c63-dede-4edc-8898-f8d0018d293e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2763058301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.2763058301
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1449578504
Short name T414
Test name
Test status
Simulation time 151648485 ps
CPU time 0.83 seconds
Started Jul 02 09:07:42 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206204 kb
Host smart-35c6b0de-60b2-45f6-b892-349505e34a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14495
78504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1449578504
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3000747344
Short name T2693
Test name
Test status
Simulation time 144590495 ps
CPU time 0.73 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206176 kb
Host smart-2c2570a0-0f36-4d87-92ac-0883f436c951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30007
47344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3000747344
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3373166817
Short name T2687
Test name
Test status
Simulation time 229672521 ps
CPU time 0.9 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:42 AM PDT 24
Peak memory 206176 kb
Host smart-b666e2c4-f410-4f23-8f89-ec8d327b23ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33731
66817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3373166817
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.967290617
Short name T2372
Test name
Test status
Simulation time 647834419 ps
CPU time 1.56 seconds
Started Jul 02 09:07:41 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206204 kb
Host smart-350f61ee-34f2-4b26-befd-ffa99c4cbbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96729
0617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.967290617
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.97648031
Short name T2254
Test name
Test status
Simulation time 21604728042 ps
CPU time 41.4 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:08:21 AM PDT 24
Peak memory 206532 kb
Host smart-02a76970-4b9c-4773-8140-cf1c954f1b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97648
031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.97648031
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.1729545618
Short name T853
Test name
Test status
Simulation time 426487797 ps
CPU time 1.39 seconds
Started Jul 02 09:07:36 AM PDT 24
Finished Jul 02 09:07:39 AM PDT 24
Peak memory 206124 kb
Host smart-b14551dc-7112-4595-b031-d367c17f09d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17295
45618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.1729545618
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2385145131
Short name T432
Test name
Test status
Simulation time 138372293 ps
CPU time 0.75 seconds
Started Jul 02 09:07:40 AM PDT 24
Finished Jul 02 09:07:43 AM PDT 24
Peak memory 206204 kb
Host smart-d5adf392-1e2e-4f8f-a777-ffe6754d572e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23851
45131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2385145131
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3373158928
Short name T2659
Test name
Test status
Simulation time 60352303 ps
CPU time 0.66 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206216 kb
Host smart-645d9e6c-7f1d-4bfb-a82a-e0332148691e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33731
58928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3373158928
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2416378898
Short name T628
Test name
Test status
Simulation time 786315045 ps
CPU time 1.95 seconds
Started Jul 02 09:07:40 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206408 kb
Host smart-49c9999e-620f-4628-acbf-4d344dcdc465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24163
78898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2416378898
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.233313175
Short name T1131
Test name
Test status
Simulation time 188279995 ps
CPU time 1.76 seconds
Started Jul 02 09:07:37 AM PDT 24
Finished Jul 02 09:07:40 AM PDT 24
Peak memory 206408 kb
Host smart-71c6cefb-4a59-4733-ab25-1609e9dbeb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23331
3175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.233313175
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.4048119974
Short name T1515
Test name
Test status
Simulation time 194604579 ps
CPU time 0.88 seconds
Started Jul 02 09:07:37 AM PDT 24
Finished Jul 02 09:07:40 AM PDT 24
Peak memory 206168 kb
Host smart-9a406d27-0c38-4a18-9490-0e007bef42b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40481
19974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.4048119974
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.21467473
Short name T2502
Test name
Test status
Simulation time 142914071 ps
CPU time 0.74 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206116 kb
Host smart-17fbced1-b6d2-4ec7-986e-1e028fa28e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21467
473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.21467473
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2640751896
Short name T1891
Test name
Test status
Simulation time 194617566 ps
CPU time 0.89 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:07:42 AM PDT 24
Peak memory 206120 kb
Host smart-0a0f88dc-2c76-4072-839f-8ff05b9ea552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26407
51896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2640751896
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.3086392109
Short name T1868
Test name
Test status
Simulation time 6248449593 ps
CPU time 169.01 seconds
Started Jul 02 09:07:40 AM PDT 24
Finished Jul 02 09:10:31 AM PDT 24
Peak memory 206500 kb
Host smart-a681835c-cc90-4c25-8fd1-23c6ccec690c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3086392109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.3086392109
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.959445359
Short name T1853
Test name
Test status
Simulation time 260635940 ps
CPU time 0.89 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:07:42 AM PDT 24
Peak memory 206196 kb
Host smart-3c1b3642-e21c-47fa-bd62-25bdef576ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95944
5359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.959445359
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.4107355985
Short name T484
Test name
Test status
Simulation time 23330046985 ps
CPU time 24.41 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:08:05 AM PDT 24
Peak memory 206176 kb
Host smart-a1cfbccf-129e-4ef2-a7b0-caa8155223fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41073
55985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.4107355985
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.892732284
Short name T916
Test name
Test status
Simulation time 3282104020 ps
CPU time 3.8 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:44 AM PDT 24
Peak memory 206228 kb
Host smart-88d2480f-cd35-4c6d-b360-88af791afc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89273
2284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.892732284
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2673573576
Short name T2208
Test name
Test status
Simulation time 7141462847 ps
CPU time 52.5 seconds
Started Jul 02 09:07:43 AM PDT 24
Finished Jul 02 09:08:37 AM PDT 24
Peak memory 206520 kb
Host smart-4f24666c-c2e4-446b-8893-239ca397ee14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26735
73576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2673573576
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3520575426
Short name T891
Test name
Test status
Simulation time 6197789234 ps
CPU time 166.76 seconds
Started Jul 02 09:07:40 AM PDT 24
Finished Jul 02 09:10:30 AM PDT 24
Peak memory 206452 kb
Host smart-484e0d8c-b536-4756-8dfd-fb58c9108f44
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3520575426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3520575426
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1568696474
Short name T1838
Test name
Test status
Simulation time 277097153 ps
CPU time 0.93 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:07:43 AM PDT 24
Peak memory 206184 kb
Host smart-bd9a1ebe-458e-4549-ae9a-c02e770e6cd8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1568696474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1568696474
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.778936482
Short name T1922
Test name
Test status
Simulation time 224572244 ps
CPU time 0.93 seconds
Started Jul 02 09:07:40 AM PDT 24
Finished Jul 02 09:07:44 AM PDT 24
Peak memory 206208 kb
Host smart-07ebfc0b-fbf5-4013-92fc-06ebf6316ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77893
6482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.778936482
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1930008918
Short name T981
Test name
Test status
Simulation time 4907073391 ps
CPU time 46.12 seconds
Started Jul 02 09:07:43 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206372 kb
Host smart-71feb8de-190d-4f77-8775-12dbce52ccbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19300
08918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1930008918
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.3900573402
Short name T2454
Test name
Test status
Simulation time 6626528964 ps
CPU time 189.11 seconds
Started Jul 02 09:07:42 AM PDT 24
Finished Jul 02 09:10:53 AM PDT 24
Peak memory 206404 kb
Host smart-46629492-7e65-4da4-b76e-d328f8d0ccfd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3900573402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3900573402
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1594450099
Short name T2311
Test name
Test status
Simulation time 169973339 ps
CPU time 0.82 seconds
Started Jul 02 09:07:42 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206188 kb
Host smart-29404712-fe17-453d-8f5f-8bf24f5ab60f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1594450099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1594450099
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.4257713823
Short name T1588
Test name
Test status
Simulation time 151067818 ps
CPU time 0.79 seconds
Started Jul 02 09:07:40 AM PDT 24
Finished Jul 02 09:07:44 AM PDT 24
Peak memory 206176 kb
Host smart-03f8dbc6-0355-438c-8b3b-787cf9b85a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42577
13823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.4257713823
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2310942467
Short name T568
Test name
Test status
Simulation time 167653732 ps
CPU time 0.86 seconds
Started Jul 02 09:07:45 AM PDT 24
Finished Jul 02 09:07:48 AM PDT 24
Peak memory 206132 kb
Host smart-f059d293-1acf-4f2b-af3f-fcc01dd5fc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23109
42467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2310942467
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3223305371
Short name T1337
Test name
Test status
Simulation time 179160374 ps
CPU time 0.89 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:07:43 AM PDT 24
Peak memory 206168 kb
Host smart-b37a1caf-d1cb-4bed-a3aa-5c3579d77712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32233
05371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3223305371
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1178487164
Short name T2415
Test name
Test status
Simulation time 200881257 ps
CPU time 0.82 seconds
Started Jul 02 09:07:47 AM PDT 24
Finished Jul 02 09:07:49 AM PDT 24
Peak memory 206208 kb
Host smart-d2dcf18a-d2ac-4c37-ab5d-945ade005c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11784
87164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1178487164
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1528589441
Short name T172
Test name
Test status
Simulation time 141580851 ps
CPU time 0.8 seconds
Started Jul 02 09:07:41 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206208 kb
Host smart-7cf3a2b0-0b74-4b7b-b458-209bbd3f9978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15285
89441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1528589441
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.76096898
Short name T2299
Test name
Test status
Simulation time 250283796 ps
CPU time 0.93 seconds
Started Jul 02 09:07:40 AM PDT 24
Finished Jul 02 09:07:44 AM PDT 24
Peak memory 206188 kb
Host smart-c34d2564-29b7-4454-8736-21d611bbd618
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=76096898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.76096898
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1480781168
Short name T24
Test name
Test status
Simulation time 17609442850 ps
CPU time 41.8 seconds
Started Jul 02 09:07:41 AM PDT 24
Finished Jul 02 09:08:26 AM PDT 24
Peak memory 206524 kb
Host smart-56fce3f8-6586-4dc3-b1ee-a61f04663aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14807
81168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1480781168
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2666437294
Short name T377
Test name
Test status
Simulation time 190424589 ps
CPU time 0.81 seconds
Started Jul 02 09:07:41 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206160 kb
Host smart-ddef74fd-9350-4350-9562-636acbf2aff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26664
37294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2666437294
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.213993461
Short name T2539
Test name
Test status
Simulation time 239546425 ps
CPU time 0.85 seconds
Started Jul 02 09:07:42 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206184 kb
Host smart-7903edaf-b9b8-40f9-9589-c720d4583c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21399
3461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.213993461
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2376128470
Short name T2409
Test name
Test status
Simulation time 183690861 ps
CPU time 0.82 seconds
Started Jul 02 09:07:43 AM PDT 24
Finished Jul 02 09:07:46 AM PDT 24
Peak memory 206084 kb
Host smart-d47f2136-0bd8-426e-8a88-bc5097848c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23761
28470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2376128470
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.1171719305
Short name T1689
Test name
Test status
Simulation time 171364994 ps
CPU time 0.79 seconds
Started Jul 02 09:07:42 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206192 kb
Host smart-da90e7f4-836c-44d2-a7d6-536d6ed01233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11717
19305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.1171719305
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2769070405
Short name T2335
Test name
Test status
Simulation time 133672166 ps
CPU time 0.78 seconds
Started Jul 02 09:07:46 AM PDT 24
Finished Jul 02 09:07:49 AM PDT 24
Peak memory 206192 kb
Host smart-fa698bd5-1666-474a-8ea1-efedcc96d0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27690
70405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2769070405
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3872002825
Short name T465
Test name
Test status
Simulation time 180873256 ps
CPU time 0.78 seconds
Started Jul 02 09:07:47 AM PDT 24
Finished Jul 02 09:07:50 AM PDT 24
Peak memory 206204 kb
Host smart-c59e2df2-3b18-4cd7-89ec-a52dae6d6274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38720
02825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3872002825
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1088068337
Short name T1552
Test name
Test status
Simulation time 182053327 ps
CPU time 0.84 seconds
Started Jul 02 09:07:43 AM PDT 24
Finished Jul 02 09:07:46 AM PDT 24
Peak memory 206208 kb
Host smart-0d7b374e-3362-4f3a-b0c6-fd3440c399b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10880
68337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1088068337
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.901081810
Short name T763
Test name
Test status
Simulation time 209689819 ps
CPU time 0.91 seconds
Started Jul 02 09:07:47 AM PDT 24
Finished Jul 02 09:07:50 AM PDT 24
Peak memory 206224 kb
Host smart-e8d0bdc2-6fea-4c78-92ab-35704601b04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90108
1810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.901081810
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2715432263
Short name T1501
Test name
Test status
Simulation time 5154936579 ps
CPU time 45.5 seconds
Started Jul 02 09:07:42 AM PDT 24
Finished Jul 02 09:08:30 AM PDT 24
Peak memory 206472 kb
Host smart-211b0daa-c97c-4776-9700-b6f5f48d6c8e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2715432263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2715432263
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2051602249
Short name T1058
Test name
Test status
Simulation time 200526414 ps
CPU time 0.89 seconds
Started Jul 02 09:07:45 AM PDT 24
Finished Jul 02 09:07:48 AM PDT 24
Peak memory 206192 kb
Host smart-dfbd878b-2905-415e-92f3-6f967402303d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20516
02249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2051602249
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.872881717
Short name T2
Test name
Test status
Simulation time 187635532 ps
CPU time 0.9 seconds
Started Jul 02 09:07:46 AM PDT 24
Finished Jul 02 09:07:48 AM PDT 24
Peak memory 206192 kb
Host smart-d8d00723-6f4b-46ff-86a4-cd931096d2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87288
1717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.872881717
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.3553346533
Short name T426
Test name
Test status
Simulation time 956333385 ps
CPU time 2.12 seconds
Started Jul 02 09:07:41 AM PDT 24
Finished Jul 02 09:07:46 AM PDT 24
Peak memory 206448 kb
Host smart-32f976e2-4664-48c1-a56a-87678acb1a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35533
46533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3553346533
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.2074847490
Short name T1979
Test name
Test status
Simulation time 7806846299 ps
CPU time 55.74 seconds
Started Jul 02 09:07:41 AM PDT 24
Finished Jul 02 09:08:40 AM PDT 24
Peak memory 206532 kb
Host smart-dc2dabe1-4d6f-4fce-a568-2686d4d3010e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20748
47490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2074847490
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1443074113
Short name T1392
Test name
Test status
Simulation time 39590557 ps
CPU time 0.7 seconds
Started Jul 02 09:07:57 AM PDT 24
Finished Jul 02 09:07:59 AM PDT 24
Peak memory 206204 kb
Host smart-2f7f9ae4-c2f0-4b68-bfb2-3157e534a1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1443074113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1443074113
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3164413193
Short name T636
Test name
Test status
Simulation time 4234516646 ps
CPU time 5.19 seconds
Started Jul 02 09:07:46 AM PDT 24
Finished Jul 02 09:07:52 AM PDT 24
Peak memory 206248 kb
Host smart-9b8b9b3f-892b-4dbb-b6a4-e5269d419750
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3164413193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.3164413193
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.845143308
Short name T751
Test name
Test status
Simulation time 13387232706 ps
CPU time 14.22 seconds
Started Jul 02 09:07:46 AM PDT 24
Finished Jul 02 09:08:03 AM PDT 24
Peak memory 206216 kb
Host smart-f69f3361-b375-473f-a11d-dd8a4615edc7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=845143308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.845143308
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3353374466
Short name T1583
Test name
Test status
Simulation time 23340000499 ps
CPU time 23.94 seconds
Started Jul 02 09:07:48 AM PDT 24
Finished Jul 02 09:08:14 AM PDT 24
Peak memory 206260 kb
Host smart-5c11a5fc-cbd5-42b0-ad44-635bf5671864
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3353374466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.3353374466
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.531751417
Short name T1212
Test name
Test status
Simulation time 177276425 ps
CPU time 0.82 seconds
Started Jul 02 09:07:47 AM PDT 24
Finished Jul 02 09:07:50 AM PDT 24
Peak memory 206180 kb
Host smart-7c5bbcd8-a708-4196-bb6b-91750f55fa4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53175
1417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.531751417
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.746223248
Short name T1120
Test name
Test status
Simulation time 150665472 ps
CPU time 0.8 seconds
Started Jul 02 09:07:46 AM PDT 24
Finished Jul 02 09:07:49 AM PDT 24
Peak memory 206392 kb
Host smart-5f2f8c44-270b-47f6-99af-0564ff424c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74622
3248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.746223248
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.2259638418
Short name T2413
Test name
Test status
Simulation time 155465771 ps
CPU time 0.76 seconds
Started Jul 02 09:07:50 AM PDT 24
Finished Jul 02 09:07:52 AM PDT 24
Peak memory 206188 kb
Host smart-f6ec7fb5-2a66-47da-b421-9eb8e1ec0f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22596
38418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2259638418
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_device_address.3906012047
Short name T2678
Test name
Test status
Simulation time 20432245305 ps
CPU time 40.71 seconds
Started Jul 02 09:07:50 AM PDT 24
Finished Jul 02 09:08:32 AM PDT 24
Peak memory 206452 kb
Host smart-5f272ef3-7aff-47a3-b835-e16728ed88d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39060
12047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.3906012047
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.914847546
Short name T1404
Test name
Test status
Simulation time 423316220 ps
CPU time 1.46 seconds
Started Jul 02 09:07:47 AM PDT 24
Finished Jul 02 09:07:50 AM PDT 24
Peak memory 206124 kb
Host smart-3d3291ac-5a3e-4e43-929c-38c42efce9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91484
7546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.914847546
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1015130522
Short name T781
Test name
Test status
Simulation time 207622735 ps
CPU time 0.79 seconds
Started Jul 02 09:07:45 AM PDT 24
Finished Jul 02 09:07:47 AM PDT 24
Peak memory 206204 kb
Host smart-d9fe5c93-aaed-4b6e-b0f5-225a0c217e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10151
30522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1015130522
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2689953399
Short name T1226
Test name
Test status
Simulation time 39327683 ps
CPU time 0.69 seconds
Started Jul 02 09:07:49 AM PDT 24
Finished Jul 02 09:07:51 AM PDT 24
Peak memory 206180 kb
Host smart-8fe15204-7ba1-4d0e-98f2-bada082001e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26899
53399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2689953399
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.870615593
Short name T771
Test name
Test status
Simulation time 913609836 ps
CPU time 2.15 seconds
Started Jul 02 09:07:48 AM PDT 24
Finished Jul 02 09:07:51 AM PDT 24
Peak memory 206364 kb
Host smart-e00628c3-a799-484d-8645-f9a6f33adfab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87061
5593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.870615593
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3552056975
Short name T2165
Test name
Test status
Simulation time 181101325 ps
CPU time 2.05 seconds
Started Jul 02 09:07:48 AM PDT 24
Finished Jul 02 09:07:52 AM PDT 24
Peak memory 206424 kb
Host smart-573dd0cf-9222-4edd-9e3f-0ccd2bad6939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35520
56975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3552056975
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1651428139
Short name T1178
Test name
Test status
Simulation time 208406108 ps
CPU time 0.9 seconds
Started Jul 02 09:07:46 AM PDT 24
Finished Jul 02 09:07:49 AM PDT 24
Peak memory 206180 kb
Host smart-0ccea5a3-bcc3-498b-b330-6116e3dcd95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16514
28139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1651428139
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1283996422
Short name T1711
Test name
Test status
Simulation time 143620673 ps
CPU time 0.8 seconds
Started Jul 02 09:07:49 AM PDT 24
Finished Jul 02 09:07:51 AM PDT 24
Peak memory 206180 kb
Host smart-1d5b1bcd-53bd-4700-85b2-f230b6d08669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12839
96422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1283996422
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2031811301
Short name T560
Test name
Test status
Simulation time 275861621 ps
CPU time 0.96 seconds
Started Jul 02 09:07:45 AM PDT 24
Finished Jul 02 09:07:48 AM PDT 24
Peak memory 206184 kb
Host smart-b01642f3-486d-427e-8473-a58b88a7ce69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20318
11301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2031811301
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1535096971
Short name T236
Test name
Test status
Simulation time 236235282 ps
CPU time 0.95 seconds
Started Jul 02 09:07:50 AM PDT 24
Finished Jul 02 09:07:52 AM PDT 24
Peak memory 206208 kb
Host smart-eed66e56-c913-46a1-816f-7eee89ae0b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15350
96971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1535096971
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1654964756
Short name T2629
Test name
Test status
Simulation time 23307181465 ps
CPU time 24.18 seconds
Started Jul 02 09:07:48 AM PDT 24
Finished Jul 02 09:08:14 AM PDT 24
Peak memory 206248 kb
Host smart-5c57f099-3b98-45f8-83b3-23a529aa2e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16549
64756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1654964756
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2914747639
Short name T2022
Test name
Test status
Simulation time 3263229955 ps
CPU time 3.9 seconds
Started Jul 02 09:07:47 AM PDT 24
Finished Jul 02 09:07:53 AM PDT 24
Peak memory 206272 kb
Host smart-09d2188e-dff4-48c4-9c1c-46e031a1e6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29147
47639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2914747639
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.948615578
Short name T4
Test name
Test status
Simulation time 6798472715 ps
CPU time 48.12 seconds
Started Jul 02 09:07:49 AM PDT 24
Finished Jul 02 09:08:40 AM PDT 24
Peak memory 206580 kb
Host smart-f72a75fb-9ca1-4fb5-9071-91547fe84b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94861
5578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.948615578
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3256192703
Short name T1426
Test name
Test status
Simulation time 5024367528 ps
CPU time 142.39 seconds
Started Jul 02 09:07:47 AM PDT 24
Finished Jul 02 09:10:12 AM PDT 24
Peak memory 206448 kb
Host smart-f9431ed5-06db-40c3-bef2-b7ea8650db61
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3256192703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3256192703
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1225078207
Short name T240
Test name
Test status
Simulation time 236885960 ps
CPU time 0.93 seconds
Started Jul 02 09:07:48 AM PDT 24
Finished Jul 02 09:07:51 AM PDT 24
Peak memory 206160 kb
Host smart-76179825-df75-475c-8965-d5b7066c979e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1225078207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1225078207
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2077975545
Short name T1600
Test name
Test status
Simulation time 191984705 ps
CPU time 0.86 seconds
Started Jul 02 09:07:49 AM PDT 24
Finished Jul 02 09:07:52 AM PDT 24
Peak memory 206168 kb
Host smart-aca5c257-673f-4454-9526-205b2f21d8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20779
75545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2077975545
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.4278953568
Short name T2637
Test name
Test status
Simulation time 3751162172 ps
CPU time 33.28 seconds
Started Jul 02 09:07:49 AM PDT 24
Finished Jul 02 09:08:24 AM PDT 24
Peak memory 206536 kb
Host smart-a958ba97-db41-4a42-9644-036c5aead258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42789
53568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.4278953568
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.290401655
Short name T600
Test name
Test status
Simulation time 5139110516 ps
CPU time 140.03 seconds
Started Jul 02 09:07:52 AM PDT 24
Finished Jul 02 09:10:13 AM PDT 24
Peak memory 206428 kb
Host smart-3da27699-c0c4-4748-a5c3-ccc9c7c5b556
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=290401655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.290401655
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.1601717262
Short name T1410
Test name
Test status
Simulation time 154620147 ps
CPU time 0.76 seconds
Started Jul 02 09:07:52 AM PDT 24
Finished Jul 02 09:07:54 AM PDT 24
Peak memory 206200 kb
Host smart-69b56003-fc0b-4f54-ac5a-52be58735e72
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1601717262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.1601717262
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3198127089
Short name T1869
Test name
Test status
Simulation time 175433985 ps
CPU time 0.77 seconds
Started Jul 02 09:07:51 AM PDT 24
Finished Jul 02 09:07:53 AM PDT 24
Peak memory 206212 kb
Host smart-b1b7e3fd-18ef-49d6-b9fb-65faae9a880e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31981
27089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3198127089
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.435543342
Short name T144
Test name
Test status
Simulation time 231356078 ps
CPU time 0.87 seconds
Started Jul 02 09:07:49 AM PDT 24
Finished Jul 02 09:07:52 AM PDT 24
Peak memory 206176 kb
Host smart-6b00bcb6-343b-4f5a-994d-8169fa83d0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43554
3342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.435543342
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3301775101
Short name T1503
Test name
Test status
Simulation time 186361773 ps
CPU time 0.83 seconds
Started Jul 02 09:07:50 AM PDT 24
Finished Jul 02 09:07:53 AM PDT 24
Peak memory 206164 kb
Host smart-e30bcf0c-a286-4014-ba4c-1546ad9113b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33017
75101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3301775101
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1208920753
Short name T2153
Test name
Test status
Simulation time 192331340 ps
CPU time 0.82 seconds
Started Jul 02 09:07:49 AM PDT 24
Finished Jul 02 09:07:52 AM PDT 24
Peak memory 206224 kb
Host smart-b2a20af3-f464-4f12-9db9-341a07830b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12089
20753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1208920753
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3164514216
Short name T2283
Test name
Test status
Simulation time 152872884 ps
CPU time 0.82 seconds
Started Jul 02 09:07:50 AM PDT 24
Finished Jul 02 09:07:52 AM PDT 24
Peak memory 206208 kb
Host smart-802a4c5d-4883-47bc-88d8-71eff8c37624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645
14216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3164514216
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1633660606
Short name T1510
Test name
Test status
Simulation time 149224813 ps
CPU time 0.81 seconds
Started Jul 02 09:07:52 AM PDT 24
Finished Jul 02 09:07:54 AM PDT 24
Peak memory 206180 kb
Host smart-3fbfe5d5-d856-45c1-86ac-f795b447593e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16336
60606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1633660606
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.3564880024
Short name T1811
Test name
Test status
Simulation time 218576259 ps
CPU time 0.91 seconds
Started Jul 02 09:07:52 AM PDT 24
Finished Jul 02 09:07:54 AM PDT 24
Peak memory 206160 kb
Host smart-1fa53bc2-bc57-4848-bd76-5bd35dcb10fa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3564880024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.3564880024
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3696664799
Short name T1911
Test name
Test status
Simulation time 145114413 ps
CPU time 0.8 seconds
Started Jul 02 09:07:53 AM PDT 24
Finished Jul 02 09:07:54 AM PDT 24
Peak memory 206160 kb
Host smart-b5ecc063-3d23-4b2b-8caa-d9f53ffa396b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36966
64799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3696664799
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2445119702
Short name T1741
Test name
Test status
Simulation time 41594364 ps
CPU time 0.67 seconds
Started Jul 02 09:07:49 AM PDT 24
Finished Jul 02 09:07:51 AM PDT 24
Peak memory 206200 kb
Host smart-4f6c11d1-705e-435f-93bc-4182e570a7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24451
19702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2445119702
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1488505494
Short name T1715
Test name
Test status
Simulation time 20611619267 ps
CPU time 45.51 seconds
Started Jul 02 09:07:52 AM PDT 24
Finished Jul 02 09:08:39 AM PDT 24
Peak memory 206524 kb
Host smart-40b39ce0-bc4d-47bb-af62-f0639e742477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14885
05494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1488505494
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1572679614
Short name T543
Test name
Test status
Simulation time 159909890 ps
CPU time 0.84 seconds
Started Jul 02 09:07:50 AM PDT 24
Finished Jul 02 09:07:52 AM PDT 24
Peak memory 206212 kb
Host smart-be03fc54-2e51-49d0-889f-98d64cf321b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15726
79614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1572679614
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.25511439
Short name T676
Test name
Test status
Simulation time 260632928 ps
CPU time 0.93 seconds
Started Jul 02 09:07:55 AM PDT 24
Finished Jul 02 09:07:56 AM PDT 24
Peak memory 206116 kb
Host smart-1f5deef0-93eb-4813-9748-dbd1a0ecfea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25511
439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.25511439
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2306353024
Short name T1846
Test name
Test status
Simulation time 248591133 ps
CPU time 1 seconds
Started Jul 02 09:07:56 AM PDT 24
Finished Jul 02 09:07:58 AM PDT 24
Peak memory 206216 kb
Host smart-a6412499-8da1-4c9b-9513-527e6aafef6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23063
53024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2306353024
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.3153441626
Short name T2044
Test name
Test status
Simulation time 261858133 ps
CPU time 0.9 seconds
Started Jul 02 09:07:53 AM PDT 24
Finished Jul 02 09:07:54 AM PDT 24
Peak memory 206160 kb
Host smart-78b95751-7715-438a-9709-88aa1bce15be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31534
41626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.3153441626
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1370278633
Short name T429
Test name
Test status
Simulation time 144345064 ps
CPU time 0.73 seconds
Started Jul 02 09:07:54 AM PDT 24
Finished Jul 02 09:07:55 AM PDT 24
Peak memory 206192 kb
Host smart-9260beb3-8f7d-42ef-ac0e-462d3718ccb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13702
78633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1370278633
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3892798366
Short name T2605
Test name
Test status
Simulation time 154201722 ps
CPU time 0.77 seconds
Started Jul 02 09:07:53 AM PDT 24
Finished Jul 02 09:07:54 AM PDT 24
Peak memory 206152 kb
Host smart-29aa0f9f-a3ea-4691-9c3f-961e6bfbb5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38927
98366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3892798366
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.815293060
Short name T556
Test name
Test status
Simulation time 186265394 ps
CPU time 0.8 seconds
Started Jul 02 09:07:56 AM PDT 24
Finished Jul 02 09:07:59 AM PDT 24
Peak memory 206200 kb
Host smart-e98a9813-c308-4da3-923e-1170f6104360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81529
3060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.815293060
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2517236087
Short name T651
Test name
Test status
Simulation time 249261716 ps
CPU time 1 seconds
Started Jul 02 09:07:54 AM PDT 24
Finished Jul 02 09:07:56 AM PDT 24
Peak memory 206156 kb
Host smart-05fa0f62-f04c-4e59-8814-9174b5f3d64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25172
36087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2517236087
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3301537867
Short name T514
Test name
Test status
Simulation time 4383092067 ps
CPU time 39.83 seconds
Started Jul 02 09:07:50 AM PDT 24
Finished Jul 02 09:08:32 AM PDT 24
Peak memory 206512 kb
Host smart-ca2c31db-103a-49de-9e3b-06e6acc2f205
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3301537867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3301537867
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3752631032
Short name T472
Test name
Test status
Simulation time 162759058 ps
CPU time 0.8 seconds
Started Jul 02 09:07:50 AM PDT 24
Finished Jul 02 09:07:53 AM PDT 24
Peak memory 206184 kb
Host smart-9ac85ea5-abf5-4b20-8156-bb2a0fb8095d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37526
31032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3752631032
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.4233479478
Short name T551
Test name
Test status
Simulation time 199733916 ps
CPU time 0.86 seconds
Started Jul 02 09:07:50 AM PDT 24
Finished Jul 02 09:07:53 AM PDT 24
Peak memory 206212 kb
Host smart-62224095-a1ff-473b-b46b-5589625daeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42334
79478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.4233479478
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.3537350443
Short name T479
Test name
Test status
Simulation time 1269533954 ps
CPU time 2.64 seconds
Started Jul 02 09:07:56 AM PDT 24
Finished Jul 02 09:08:00 AM PDT 24
Peak memory 206452 kb
Host smart-cc2ba410-1425-4788-bf63-5dd08ee411ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35373
50443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.3537350443
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.667616008
Short name T2455
Test name
Test status
Simulation time 5402107518 ps
CPU time 39.14 seconds
Started Jul 02 09:07:52 AM PDT 24
Finished Jul 02 09:08:32 AM PDT 24
Peak memory 206472 kb
Host smart-1df50994-9b38-42ba-b6a9-ab35d9d57cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66761
6008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.667616008
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.571102354
Short name T1256
Test name
Test status
Simulation time 31030195 ps
CPU time 0.7 seconds
Started Jul 02 09:08:02 AM PDT 24
Finished Jul 02 09:08:04 AM PDT 24
Peak memory 206236 kb
Host smart-0a179197-bbc9-4eda-ba6b-e71d94e53767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=571102354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.571102354
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1592309463
Short name T2297
Test name
Test status
Simulation time 3926986894 ps
CPU time 5.4 seconds
Started Jul 02 09:07:58 AM PDT 24
Finished Jul 02 09:08:04 AM PDT 24
Peak memory 206216 kb
Host smart-e0f9995a-cc47-469c-8446-f63b37c665dc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1592309463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.1592309463
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3379207280
Short name T222
Test name
Test status
Simulation time 13372622706 ps
CPU time 12.78 seconds
Started Jul 02 09:07:57 AM PDT 24
Finished Jul 02 09:08:11 AM PDT 24
Peak memory 206436 kb
Host smart-ebe098c5-4af0-4ee9-ad91-0d9abd4af746
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3379207280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3379207280
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1988092285
Short name T1240
Test name
Test status
Simulation time 23408131897 ps
CPU time 27.46 seconds
Started Jul 02 09:07:59 AM PDT 24
Finished Jul 02 09:08:27 AM PDT 24
Peak memory 206480 kb
Host smart-d0d0e003-7bf9-424c-89b7-98a8918dad7a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1988092285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.1988092285
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.837567498
Short name T1870
Test name
Test status
Simulation time 163142901 ps
CPU time 0.83 seconds
Started Jul 02 09:07:57 AM PDT 24
Finished Jul 02 09:07:59 AM PDT 24
Peak memory 206212 kb
Host smart-f6c33ac0-06dd-4e7a-b82d-f116cad9f796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83756
7498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.837567498
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3063275996
Short name T694
Test name
Test status
Simulation time 171111431 ps
CPU time 0.84 seconds
Started Jul 02 09:07:56 AM PDT 24
Finished Jul 02 09:07:59 AM PDT 24
Peak memory 206208 kb
Host smart-013e3982-9fd2-41ba-8a63-ee58aed5e288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30632
75996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3063275996
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.188734756
Short name T1375
Test name
Test status
Simulation time 382515048 ps
CPU time 1.21 seconds
Started Jul 02 09:07:56 AM PDT 24
Finished Jul 02 09:07:57 AM PDT 24
Peak memory 206208 kb
Host smart-26e705ea-aac6-4c4d-b220-5e276250fb0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18873
4756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.188734756
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3837912222
Short name T173
Test name
Test status
Simulation time 622519400 ps
CPU time 1.84 seconds
Started Jul 02 09:07:59 AM PDT 24
Finished Jul 02 09:08:02 AM PDT 24
Peak memory 206184 kb
Host smart-42120335-37bf-4455-92ed-b53557640455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38379
12222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3837912222
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1905628939
Short name T2438
Test name
Test status
Simulation time 7495109187 ps
CPU time 15.22 seconds
Started Jul 02 09:07:56 AM PDT 24
Finished Jul 02 09:08:12 AM PDT 24
Peak memory 206496 kb
Host smart-a38682c0-bcf1-43a5-b4cc-684bc49172f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19056
28939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1905628939
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.2315381049
Short name T2285
Test name
Test status
Simulation time 388338238 ps
CPU time 1.22 seconds
Started Jul 02 09:07:58 AM PDT 24
Finished Jul 02 09:08:00 AM PDT 24
Peak memory 206384 kb
Host smart-b92eef9a-4cf8-4c69-a1e1-5a421d465dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23153
81049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.2315381049
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2809901344
Short name T1205
Test name
Test status
Simulation time 145851119 ps
CPU time 0.8 seconds
Started Jul 02 09:07:59 AM PDT 24
Finished Jul 02 09:08:01 AM PDT 24
Peak memory 206200 kb
Host smart-eb955137-54b5-400b-9999-bc20c5c924b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28099
01344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2809901344
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.4687186
Short name T369
Test name
Test status
Simulation time 42417805 ps
CPU time 0.68 seconds
Started Jul 02 09:07:59 AM PDT 24
Finished Jul 02 09:08:00 AM PDT 24
Peak memory 206184 kb
Host smart-01fddb97-5712-44f9-82b0-775272486aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46871
86 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.4687186
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1896245127
Short name T1984
Test name
Test status
Simulation time 724041253 ps
CPU time 1.82 seconds
Started Jul 02 09:07:55 AM PDT 24
Finished Jul 02 09:07:57 AM PDT 24
Peak memory 206376 kb
Host smart-06880b71-4c02-4726-b4e1-a80b4714271a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18962
45127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1896245127
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1939052611
Short name T1278
Test name
Test status
Simulation time 199121465 ps
CPU time 0.86 seconds
Started Jul 02 09:07:56 AM PDT 24
Finished Jul 02 09:07:58 AM PDT 24
Peak memory 206168 kb
Host smart-f1f406da-a81c-4d8d-b0ae-4f224a50a56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19390
52611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1939052611
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2479747716
Short name T1363
Test name
Test status
Simulation time 147879463 ps
CPU time 0.76 seconds
Started Jul 02 09:08:02 AM PDT 24
Finished Jul 02 09:08:04 AM PDT 24
Peak memory 206180 kb
Host smart-383ae5b0-b588-4c63-854e-43dbd1ddc496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24797
47716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2479747716
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.454179044
Short name T2117
Test name
Test status
Simulation time 227003563 ps
CPU time 0.89 seconds
Started Jul 02 09:07:58 AM PDT 24
Finished Jul 02 09:08:00 AM PDT 24
Peak memory 206212 kb
Host smart-8f3401f8-792d-4681-b596-4fcb5d958b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45417
9044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.454179044
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2147873751
Short name T1902
Test name
Test status
Simulation time 195433297 ps
CPU time 0.85 seconds
Started Jul 02 09:08:03 AM PDT 24
Finished Jul 02 09:08:05 AM PDT 24
Peak memory 206128 kb
Host smart-d3e5f948-22ed-4d8f-8ba0-c2b7feddea18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21478
73751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2147873751
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.4207689991
Short name T1543
Test name
Test status
Simulation time 23349402129 ps
CPU time 23.99 seconds
Started Jul 02 09:07:58 AM PDT 24
Finished Jul 02 09:08:24 AM PDT 24
Peak memory 206272 kb
Host smart-f5168b46-c441-4a73-8049-a9d708e44822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42076
89991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.4207689991
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.1003633503
Short name T32
Test name
Test status
Simulation time 3288522066 ps
CPU time 4.12 seconds
Started Jul 02 09:08:00 AM PDT 24
Finished Jul 02 09:08:05 AM PDT 24
Peak memory 206268 kb
Host smart-5b7b4868-c839-4526-a2f4-ff71bd7c5ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10036
33503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.1003633503
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.793937812
Short name T1447
Test name
Test status
Simulation time 13412849840 ps
CPU time 368.25 seconds
Started Jul 02 09:08:00 AM PDT 24
Finished Jul 02 09:14:09 AM PDT 24
Peak memory 206556 kb
Host smart-a7dc0c9c-46c4-4455-8dda-0d1d1225093f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79393
7812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.793937812
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2668890654
Short name T1527
Test name
Test status
Simulation time 6972995722 ps
CPU time 51.76 seconds
Started Jul 02 09:07:59 AM PDT 24
Finished Jul 02 09:08:52 AM PDT 24
Peak memory 206432 kb
Host smart-771b1dd7-cd34-4247-9d4a-f28478611295
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2668890654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2668890654
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.758062661
Short name T1905
Test name
Test status
Simulation time 244978718 ps
CPU time 0.89 seconds
Started Jul 02 09:07:56 AM PDT 24
Finished Jul 02 09:07:58 AM PDT 24
Peak memory 206184 kb
Host smart-d2aa8388-dac6-42ea-8a1e-c8962f678ddf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=758062661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.758062661
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2938270715
Short name T1596
Test name
Test status
Simulation time 191593246 ps
CPU time 0.83 seconds
Started Jul 02 09:07:57 AM PDT 24
Finished Jul 02 09:07:59 AM PDT 24
Peak memory 206212 kb
Host smart-6d7b8055-7908-4499-81d7-d391559fbc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29382
70715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2938270715
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1857632339
Short name T2056
Test name
Test status
Simulation time 6282700655 ps
CPU time 43.02 seconds
Started Jul 02 09:08:03 AM PDT 24
Finished Jul 02 09:08:47 AM PDT 24
Peak memory 206380 kb
Host smart-184f7be1-280f-4925-8f9b-7b0cae7e8dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18576
32339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1857632339
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.3557680374
Short name T1964
Test name
Test status
Simulation time 5394165839 ps
CPU time 155.74 seconds
Started Jul 02 09:07:58 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206460 kb
Host smart-4ec1b7c4-70fa-4096-85f8-79fc570ccc39
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3557680374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.3557680374
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.2029281680
Short name T1143
Test name
Test status
Simulation time 163379476 ps
CPU time 0.86 seconds
Started Jul 02 09:08:00 AM PDT 24
Finished Jul 02 09:08:02 AM PDT 24
Peak memory 206148 kb
Host smart-5b7a2e26-b791-4c71-845c-26b656bda4bf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2029281680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2029281680
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.159158994
Short name T1765
Test name
Test status
Simulation time 154313493 ps
CPU time 0.77 seconds
Started Jul 02 09:07:56 AM PDT 24
Finished Jul 02 09:07:57 AM PDT 24
Peak memory 206192 kb
Host smart-dccf565e-20a2-425a-8205-ccb78794599e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15915
8994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.159158994
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2855594969
Short name T1377
Test name
Test status
Simulation time 191385747 ps
CPU time 0.87 seconds
Started Jul 02 09:07:57 AM PDT 24
Finished Jul 02 09:08:00 AM PDT 24
Peak memory 206144 kb
Host smart-1c05d5e5-bd26-42a4-ac68-b3f443e527fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28555
94969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2855594969
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1636467433
Short name T880
Test name
Test status
Simulation time 146922865 ps
CPU time 0.8 seconds
Started Jul 02 09:07:57 AM PDT 24
Finished Jul 02 09:08:00 AM PDT 24
Peak memory 206204 kb
Host smart-b7570dac-bf3e-47b9-a7b5-d9214aeacc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16364
67433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1636467433
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3598749439
Short name T1348
Test name
Test status
Simulation time 175014583 ps
CPU time 0.82 seconds
Started Jul 02 09:07:59 AM PDT 24
Finished Jul 02 09:08:01 AM PDT 24
Peak memory 206192 kb
Host smart-1c27129d-9e9c-4f2d-a51e-9748f33052ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35987
49439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3598749439
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2057124434
Short name T1597
Test name
Test status
Simulation time 164393835 ps
CPU time 0.81 seconds
Started Jul 02 09:08:00 AM PDT 24
Finished Jul 02 09:08:02 AM PDT 24
Peak memory 206168 kb
Host smart-2b56ddb3-0dfe-4ea9-a960-380768b34b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20571
24434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2057124434
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.2988656460
Short name T2495
Test name
Test status
Simulation time 242660501 ps
CPU time 0.96 seconds
Started Jul 02 09:08:02 AM PDT 24
Finished Jul 02 09:08:04 AM PDT 24
Peak memory 206108 kb
Host smart-196bf379-cc73-4761-a560-a4fdd351d954
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2988656460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2988656460
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.4256694592
Short name T1784
Test name
Test status
Simulation time 167316381 ps
CPU time 0.85 seconds
Started Jul 02 09:08:02 AM PDT 24
Finished Jul 02 09:08:03 AM PDT 24
Peak memory 206204 kb
Host smart-3ffa0b26-5799-4215-987c-a3b6b1369188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42566
94592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.4256694592
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1295362818
Short name T39
Test name
Test status
Simulation time 41176366 ps
CPU time 0.66 seconds
Started Jul 02 09:08:08 AM PDT 24
Finished Jul 02 09:08:09 AM PDT 24
Peak memory 206180 kb
Host smart-4a89d97d-30b1-452e-a79f-1fd1f6247abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12953
62818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1295362818
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2555967079
Short name T1968
Test name
Test status
Simulation time 149077148 ps
CPU time 0.79 seconds
Started Jul 02 09:08:06 AM PDT 24
Finished Jul 02 09:08:08 AM PDT 24
Peak memory 206204 kb
Host smart-4f7c6d23-9067-4e16-b8bf-1ceef60e7e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25559
67079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2555967079
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1176299223
Short name T1714
Test name
Test status
Simulation time 227677361 ps
CPU time 0.92 seconds
Started Jul 02 09:08:05 AM PDT 24
Finished Jul 02 09:08:07 AM PDT 24
Peak memory 206128 kb
Host smart-3f2a80aa-cd3a-4888-9524-3bad8de8af6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11762
99223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1176299223
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.521096217
Short name T1550
Test name
Test status
Simulation time 261999090 ps
CPU time 1 seconds
Started Jul 02 09:08:09 AM PDT 24
Finished Jul 02 09:08:11 AM PDT 24
Peak memory 206140 kb
Host smart-e78dec96-0268-4e50-8ac1-4cacf321c608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52109
6217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.521096217
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.1385655274
Short name T339
Test name
Test status
Simulation time 194216355 ps
CPU time 0.89 seconds
Started Jul 02 09:08:03 AM PDT 24
Finished Jul 02 09:08:05 AM PDT 24
Peak memory 206228 kb
Host smart-0d27c5b3-0025-421f-8cba-00843c5015c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
55274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.1385655274
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1457704300
Short name T383
Test name
Test status
Simulation time 157108980 ps
CPU time 0.89 seconds
Started Jul 02 09:08:02 AM PDT 24
Finished Jul 02 09:08:03 AM PDT 24
Peak memory 206124 kb
Host smart-de8b661d-b96e-4194-a651-ab35542f7c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14577
04300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1457704300
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2015163792
Short name T1387
Test name
Test status
Simulation time 150276933 ps
CPU time 0.83 seconds
Started Jul 02 09:08:06 AM PDT 24
Finished Jul 02 09:08:08 AM PDT 24
Peak memory 206200 kb
Host smart-6ddc541b-9dd0-424b-b057-e05a5bca36f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20151
63792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2015163792
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2115527708
Short name T2508
Test name
Test status
Simulation time 148268996 ps
CPU time 0.85 seconds
Started Jul 02 09:08:01 AM PDT 24
Finished Jul 02 09:08:03 AM PDT 24
Peak memory 206168 kb
Host smart-3e79145d-1d16-4e1b-9a03-c4e00e3e6767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21155
27708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2115527708
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1921865346
Short name T2541
Test name
Test status
Simulation time 255885007 ps
CPU time 1.06 seconds
Started Jul 02 09:08:01 AM PDT 24
Finished Jul 02 09:08:02 AM PDT 24
Peak memory 206168 kb
Host smart-497d5c72-02b5-45da-a884-38e95e2a3211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19218
65346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1921865346
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3982016366
Short name T859
Test name
Test status
Simulation time 5403313474 ps
CPU time 40.13 seconds
Started Jul 02 09:08:02 AM PDT 24
Finished Jul 02 09:08:42 AM PDT 24
Peak memory 206492 kb
Host smart-c74df644-ffe5-4e92-9bee-9971ad0d4cc3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3982016366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3982016366
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3280212245
Short name T2388
Test name
Test status
Simulation time 162988820 ps
CPU time 0.85 seconds
Started Jul 02 09:08:03 AM PDT 24
Finished Jul 02 09:08:05 AM PDT 24
Peak memory 206168 kb
Host smart-71c49794-9a0e-41fb-86cd-0f9b2fe2faaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32802
12245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3280212245
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.4029847655
Short name T2675
Test name
Test status
Simulation time 170153820 ps
CPU time 0.83 seconds
Started Jul 02 09:08:01 AM PDT 24
Finished Jul 02 09:08:03 AM PDT 24
Peak memory 206156 kb
Host smart-054e9c6e-e34c-4402-8fca-c9e6d75942f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40298
47655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.4029847655
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.4140145286
Short name T1861
Test name
Test status
Simulation time 1280059412 ps
CPU time 2.68 seconds
Started Jul 02 09:08:03 AM PDT 24
Finished Jul 02 09:08:06 AM PDT 24
Peak memory 206448 kb
Host smart-5bcd294e-3f57-42af-bf81-81d89023760d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41401
45286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.4140145286
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3095145447
Short name T2477
Test name
Test status
Simulation time 6903816460 ps
CPU time 72.09 seconds
Started Jul 02 09:08:04 AM PDT 24
Finished Jul 02 09:09:16 AM PDT 24
Peak memory 206488 kb
Host smart-405b4d6b-fdee-4ecd-a050-ae4f92292e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30951
45447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3095145447
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.839993184
Short name T2408
Test name
Test status
Simulation time 53538674 ps
CPU time 0.68 seconds
Started Jul 02 09:08:15 AM PDT 24
Finished Jul 02 09:08:17 AM PDT 24
Peak memory 206220 kb
Host smart-2f2b1c41-c40b-48a6-9d1f-7d3b072d2b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=839993184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.839993184
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.540662357
Short name T2309
Test name
Test status
Simulation time 4386702795 ps
CPU time 5.8 seconds
Started Jul 02 09:08:09 AM PDT 24
Finished Jul 02 09:08:15 AM PDT 24
Peak memory 206380 kb
Host smart-e9843f57-3cfb-444f-adcc-39781009dc78
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=540662357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.540662357
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.368081194
Short name T2043
Test name
Test status
Simulation time 13416959575 ps
CPU time 13.19 seconds
Started Jul 02 09:08:08 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206252 kb
Host smart-15882481-8127-43cf-b7c9-e9bba5debc8a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=368081194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.368081194
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2111000751
Short name T1139
Test name
Test status
Simulation time 23419446209 ps
CPU time 24.58 seconds
Started Jul 02 09:08:07 AM PDT 24
Finished Jul 02 09:08:33 AM PDT 24
Peak memory 206444 kb
Host smart-3d41079f-997a-480e-a88e-bc2ea52bfe24
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2111000751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.2111000751
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1103007839
Short name T2317
Test name
Test status
Simulation time 154552754 ps
CPU time 0.79 seconds
Started Jul 02 09:08:03 AM PDT 24
Finished Jul 02 09:08:05 AM PDT 24
Peak memory 206176 kb
Host smart-fbc57a01-9525-4886-9a94-639b8e2ade1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11030
07839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1103007839
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.1693000208
Short name T1551
Test name
Test status
Simulation time 159782191 ps
CPU time 0.86 seconds
Started Jul 02 09:08:08 AM PDT 24
Finished Jul 02 09:08:09 AM PDT 24
Peak memory 206196 kb
Host smart-71eb78ae-8429-48b4-bfd5-4a7897a23cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16930
00208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1693000208
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.431910240
Short name T1419
Test name
Test status
Simulation time 294988420 ps
CPU time 1.21 seconds
Started Jul 02 09:08:05 AM PDT 24
Finished Jul 02 09:08:07 AM PDT 24
Peak memory 206120 kb
Host smart-02f09344-4f57-4467-8b68-db7598ac01a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43191
0240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.431910240
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.990209633
Short name T2051
Test name
Test status
Simulation time 1213024387 ps
CPU time 2.7 seconds
Started Jul 02 09:08:10 AM PDT 24
Finished Jul 02 09:08:13 AM PDT 24
Peak memory 206300 kb
Host smart-0002bece-4f73-4caa-9d62-eb924dd778f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99020
9633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.990209633
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.4183482275
Short name T949
Test name
Test status
Simulation time 21196578756 ps
CPU time 38.83 seconds
Started Jul 02 09:08:05 AM PDT 24
Finished Jul 02 09:08:45 AM PDT 24
Peak memory 206516 kb
Host smart-4a3c0671-879c-496a-9b47-0f2dec849260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41834
82275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.4183482275
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2391527590
Short name T799
Test name
Test status
Simulation time 389211040 ps
CPU time 1.2 seconds
Started Jul 02 09:08:06 AM PDT 24
Finished Jul 02 09:08:08 AM PDT 24
Peak memory 206212 kb
Host smart-2e522d07-3885-46e9-bd1a-7c1defbb66b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23915
27590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2391527590
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.95424225
Short name T536
Test name
Test status
Simulation time 146554893 ps
CPU time 0.78 seconds
Started Jul 02 09:08:10 AM PDT 24
Finished Jul 02 09:08:11 AM PDT 24
Peak memory 206144 kb
Host smart-fce57584-8258-4710-b029-693890672db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95424
225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.95424225
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.4086086942
Short name T2243
Test name
Test status
Simulation time 51799547 ps
CPU time 0.68 seconds
Started Jul 02 09:08:06 AM PDT 24
Finished Jul 02 09:08:07 AM PDT 24
Peak memory 206212 kb
Host smart-f78885b7-f6f2-4646-9af7-06cee9d91133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40860
86942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.4086086942
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2078392975
Short name T1211
Test name
Test status
Simulation time 926244506 ps
CPU time 2.15 seconds
Started Jul 02 09:08:11 AM PDT 24
Finished Jul 02 09:08:14 AM PDT 24
Peak memory 206276 kb
Host smart-5227fd67-05f2-43a2-abfb-257cf56c9727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20783
92975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2078392975
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2421167616
Short name T1986
Test name
Test status
Simulation time 356051812 ps
CPU time 1.98 seconds
Started Jul 02 09:08:09 AM PDT 24
Finished Jul 02 09:08:12 AM PDT 24
Peak memory 206400 kb
Host smart-0375d36b-2dbb-47c9-afd7-7de23f0ca831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24211
67616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2421167616
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.4206019667
Short name T1679
Test name
Test status
Simulation time 191422696 ps
CPU time 0.9 seconds
Started Jul 02 09:08:07 AM PDT 24
Finished Jul 02 09:08:09 AM PDT 24
Peak memory 206340 kb
Host smart-d6071867-65e4-42e8-9ca0-59bb54ba42bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42060
19667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.4206019667
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.121865659
Short name T948
Test name
Test status
Simulation time 161049967 ps
CPU time 0.78 seconds
Started Jul 02 09:08:11 AM PDT 24
Finished Jul 02 09:08:12 AM PDT 24
Peak memory 206088 kb
Host smart-0c376bbb-6211-4c7e-96d5-b272ae4bc83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12186
5659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.121865659
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1160745198
Short name T2390
Test name
Test status
Simulation time 261848001 ps
CPU time 0.96 seconds
Started Jul 02 09:08:08 AM PDT 24
Finished Jul 02 09:08:09 AM PDT 24
Peak memory 206196 kb
Host smart-63f3820b-5219-4e7c-b9cf-0b3dfb953861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11607
45198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1160745198
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1804605278
Short name T1930
Test name
Test status
Simulation time 186633557 ps
CPU time 0.92 seconds
Started Jul 02 09:08:10 AM PDT 24
Finished Jul 02 09:08:11 AM PDT 24
Peak memory 206140 kb
Host smart-00b54c03-34dd-4f79-9e8e-570ad2061aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18046
05278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1804605278
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.785315243
Short name T759
Test name
Test status
Simulation time 23376592588 ps
CPU time 30.41 seconds
Started Jul 02 09:08:08 AM PDT 24
Finished Jul 02 09:08:39 AM PDT 24
Peak memory 206272 kb
Host smart-a0abef48-5523-4361-a9fa-b49a535b37e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78531
5243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.785315243
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2941101280
Short name T530
Test name
Test status
Simulation time 3275717180 ps
CPU time 4 seconds
Started Jul 02 09:08:06 AM PDT 24
Finished Jul 02 09:08:10 AM PDT 24
Peak memory 206260 kb
Host smart-efe146e0-e813-4053-87d4-413db86aa6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29411
01280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2941101280
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2346283939
Short name T457
Test name
Test status
Simulation time 10524838112 ps
CPU time 74.27 seconds
Started Jul 02 09:08:07 AM PDT 24
Finished Jul 02 09:09:22 AM PDT 24
Peak memory 206540 kb
Host smart-c9860d7d-a72f-4ea5-925a-62fe287992e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23462
83939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2346283939
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.3360242181
Short name T649
Test name
Test status
Simulation time 4505336519 ps
CPU time 128.5 seconds
Started Jul 02 09:08:07 AM PDT 24
Finished Jul 02 09:10:16 AM PDT 24
Peak memory 206444 kb
Host smart-ce43586b-1ff4-4872-befa-fa57382ce15b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3360242181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3360242181
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1627387882
Short name T1168
Test name
Test status
Simulation time 274688380 ps
CPU time 1.02 seconds
Started Jul 02 09:08:11 AM PDT 24
Finished Jul 02 09:08:12 AM PDT 24
Peak memory 205992 kb
Host smart-c2976ab3-d9c6-48a6-b591-90f7e446e8de
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1627387882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1627387882
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2533149490
Short name T590
Test name
Test status
Simulation time 187184022 ps
CPU time 0.91 seconds
Started Jul 02 09:08:08 AM PDT 24
Finished Jul 02 09:08:10 AM PDT 24
Peak memory 206180 kb
Host smart-e4de4eee-0f4e-433c-96c5-c0d421cd67c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25331
49490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2533149490
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2909572661
Short name T1770
Test name
Test status
Simulation time 4583472572 ps
CPU time 125.47 seconds
Started Jul 02 09:08:06 AM PDT 24
Finished Jul 02 09:10:12 AM PDT 24
Peak memory 206456 kb
Host smart-93b48519-a598-4669-bcd1-7cc55dcdf80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29095
72661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2909572661
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3625148195
Short name T998
Test name
Test status
Simulation time 7218824146 ps
CPU time 197.4 seconds
Started Jul 02 09:08:22 AM PDT 24
Finished Jul 02 09:11:41 AM PDT 24
Peak memory 206436 kb
Host smart-7f967a55-2292-48a4-9bfb-babde961a3c2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3625148195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3625148195
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2364988649
Short name T470
Test name
Test status
Simulation time 154548932 ps
CPU time 0.77 seconds
Started Jul 02 09:08:10 AM PDT 24
Finished Jul 02 09:08:11 AM PDT 24
Peak memory 206340 kb
Host smart-bcda64de-0428-450f-b2f6-1dce4bb5186f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2364988649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2364988649
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.105703893
Short name T2586
Test name
Test status
Simulation time 140626866 ps
CPU time 0.76 seconds
Started Jul 02 09:08:22 AM PDT 24
Finished Jul 02 09:08:24 AM PDT 24
Peak memory 206196 kb
Host smart-f3a5bfd7-cad0-4ce8-a596-55e34005f3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10570
3893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.105703893
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.94633773
Short name T2593
Test name
Test status
Simulation time 159378078 ps
CPU time 0.84 seconds
Started Jul 02 09:08:13 AM PDT 24
Finished Jul 02 09:08:15 AM PDT 24
Peak memory 206076 kb
Host smart-c3f7969a-27f9-4e53-ac80-18a9e55ae398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94633
773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.94633773
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1058551059
Short name T2700
Test name
Test status
Simulation time 178776914 ps
CPU time 0.82 seconds
Started Jul 02 09:08:12 AM PDT 24
Finished Jul 02 09:08:13 AM PDT 24
Peak memory 206188 kb
Host smart-edc9aef5-f5b3-4f9e-b1aa-5119ecb47ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10585
51059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1058551059
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1122062891
Short name T635
Test name
Test status
Simulation time 174872429 ps
CPU time 0.76 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:26 AM PDT 24
Peak memory 206196 kb
Host smart-eba32c08-1d85-4bc6-a24b-c8d398738359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11220
62891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1122062891
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2288142124
Short name T1172
Test name
Test status
Simulation time 163722196 ps
CPU time 0.82 seconds
Started Jul 02 09:08:10 AM PDT 24
Finished Jul 02 09:08:11 AM PDT 24
Peak memory 206208 kb
Host smart-1799aa1a-d9ae-46e2-8f77-fd6e9ec03d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22881
42124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2288142124
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.882228087
Short name T532
Test name
Test status
Simulation time 254330029 ps
CPU time 0.92 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:28 AM PDT 24
Peak memory 206176 kb
Host smart-a1e987b1-366f-46e1-a960-6f35a1b0a16d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=882228087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.882228087
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1203210915
Short name T1611
Test name
Test status
Simulation time 138876632 ps
CPU time 0.77 seconds
Started Jul 02 09:08:15 AM PDT 24
Finished Jul 02 09:08:16 AM PDT 24
Peak memory 206128 kb
Host smart-00601b3f-c49f-46e8-a764-94bc35e2b104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032
10915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1203210915
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2454425138
Short name T1216
Test name
Test status
Simulation time 79644725 ps
CPU time 0.67 seconds
Started Jul 02 09:08:12 AM PDT 24
Finished Jul 02 09:08:13 AM PDT 24
Peak memory 206076 kb
Host smart-c77c4bf8-1d0b-4612-a2d7-c8cc7d0f98bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24544
25138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2454425138
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3425178032
Short name T1343
Test name
Test status
Simulation time 8038165320 ps
CPU time 18.56 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:45 AM PDT 24
Peak memory 206544 kb
Host smart-1cc5835d-826e-44f0-8ad9-070317d922dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34251
78032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3425178032
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2471006081
Short name T503
Test name
Test status
Simulation time 201116031 ps
CPU time 0.86 seconds
Started Jul 02 09:08:12 AM PDT 24
Finished Jul 02 09:08:13 AM PDT 24
Peak memory 206072 kb
Host smart-daa9a587-588b-4f11-a48a-5c3c5196dbb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24710
06081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2471006081
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3787207118
Short name T1502
Test name
Test status
Simulation time 195039180 ps
CPU time 0.85 seconds
Started Jul 02 09:08:12 AM PDT 24
Finished Jul 02 09:08:13 AM PDT 24
Peak memory 206204 kb
Host smart-54b0c4d3-8d4b-4886-9028-75aaf7dd174a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37872
07118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3787207118
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.4216781263
Short name T1171
Test name
Test status
Simulation time 234301483 ps
CPU time 0.88 seconds
Started Jul 02 09:08:12 AM PDT 24
Finished Jul 02 09:08:15 AM PDT 24
Peak memory 206080 kb
Host smart-d1f8be14-f2aa-4876-989c-b71743194e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42167
81263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.4216781263
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2933076092
Short name T2421
Test name
Test status
Simulation time 174772799 ps
CPU time 0.8 seconds
Started Jul 02 09:08:24 AM PDT 24
Finished Jul 02 09:08:28 AM PDT 24
Peak memory 206200 kb
Host smart-4c36cf66-d1d5-44cd-b461-2d8bf21c97e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29330
76092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2933076092
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3587135757
Short name T2289
Test name
Test status
Simulation time 226603975 ps
CPU time 0.88 seconds
Started Jul 02 09:08:11 AM PDT 24
Finished Jul 02 09:08:13 AM PDT 24
Peak memory 206164 kb
Host smart-893bc1da-201b-460d-ad59-7d5d7ef7c760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35871
35757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3587135757
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.423302519
Short name T1162
Test name
Test status
Simulation time 174983937 ps
CPU time 0.77 seconds
Started Jul 02 09:08:12 AM PDT 24
Finished Jul 02 09:08:13 AM PDT 24
Peak memory 206188 kb
Host smart-cd7fe931-62ba-4d31-b71a-2ad326222a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42330
2519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.423302519
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1555007471
Short name T2566
Test name
Test status
Simulation time 213925478 ps
CPU time 0.91 seconds
Started Jul 02 09:08:15 AM PDT 24
Finished Jul 02 09:08:17 AM PDT 24
Peak memory 206204 kb
Host smart-9cc3d786-2d7e-4ca4-bc74-65269e497e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15550
07471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1555007471
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3458606975
Short name T1620
Test name
Test status
Simulation time 251829093 ps
CPU time 0.96 seconds
Started Jul 02 09:08:14 AM PDT 24
Finished Jul 02 09:08:15 AM PDT 24
Peak memory 206220 kb
Host smart-5f931bde-c7fa-4ca7-955e-40cee0c916e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
06975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3458606975
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.1881851253
Short name T892
Test name
Test status
Simulation time 3597538676 ps
CPU time 34.23 seconds
Started Jul 02 09:08:15 AM PDT 24
Finished Jul 02 09:08:50 AM PDT 24
Peak memory 206512 kb
Host smart-f672724f-945a-4c79-bcaa-544295373575
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1881851253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.1881851253
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1381811300
Short name T920
Test name
Test status
Simulation time 182996447 ps
CPU time 0.86 seconds
Started Jul 02 09:08:14 AM PDT 24
Finished Jul 02 09:08:15 AM PDT 24
Peak memory 206184 kb
Host smart-772b9390-e0c5-48b6-999f-3240ebcdbf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13818
11300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1381811300
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1533085234
Short name T401
Test name
Test status
Simulation time 186156033 ps
CPU time 0.79 seconds
Started Jul 02 09:08:24 AM PDT 24
Finished Jul 02 09:08:28 AM PDT 24
Peak memory 206196 kb
Host smart-13acf142-32e3-434b-bf91-56d9d2a6d044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15330
85234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1533085234
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.2884265435
Short name T2211
Test name
Test status
Simulation time 1043700283 ps
CPU time 2.17 seconds
Started Jul 02 09:08:15 AM PDT 24
Finished Jul 02 09:08:18 AM PDT 24
Peak memory 206364 kb
Host smart-7cd28038-3262-45ba-a66d-406c6533a09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28842
65435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.2884265435
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.467478412
Short name T1491
Test name
Test status
Simulation time 4396587809 ps
CPU time 121.43 seconds
Started Jul 02 09:08:16 AM PDT 24
Finished Jul 02 09:10:18 AM PDT 24
Peak memory 206544 kb
Host smart-a59b9115-5a40-4f8b-91da-ec001f62bdf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46747
8412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.467478412
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2036738439
Short name T2061
Test name
Test status
Simulation time 67521552 ps
CPU time 0.69 seconds
Started Jul 02 09:08:26 AM PDT 24
Finished Jul 02 09:08:30 AM PDT 24
Peak memory 206252 kb
Host smart-0c2cc799-fd95-41b6-b713-9290279436e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2036738439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2036738439
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.953852183
Short name T1317
Test name
Test status
Simulation time 3905017748 ps
CPU time 5.29 seconds
Started Jul 02 09:08:42 AM PDT 24
Finished Jul 02 09:08:48 AM PDT 24
Peak memory 206472 kb
Host smart-96a14c1f-cc1c-4dce-9daf-7baaff107106
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=953852183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.953852183
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1679562820
Short name T1141
Test name
Test status
Simulation time 13372980077 ps
CPU time 13.57 seconds
Started Jul 02 09:08:16 AM PDT 24
Finished Jul 02 09:08:30 AM PDT 24
Peak memory 206224 kb
Host smart-b8795fed-556a-4343-87f5-44e6f95884d1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1679562820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1679562820
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2321816370
Short name T1023
Test name
Test status
Simulation time 23421613227 ps
CPU time 28.38 seconds
Started Jul 02 09:08:13 AM PDT 24
Finished Jul 02 09:08:42 AM PDT 24
Peak memory 206204 kb
Host smart-4c35f54e-5c12-4302-8185-2cf923c50b51
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2321816370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.2321816370
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2427207916
Short name T1159
Test name
Test status
Simulation time 172126391 ps
CPU time 0.84 seconds
Started Jul 02 09:08:14 AM PDT 24
Finished Jul 02 09:08:15 AM PDT 24
Peak memory 206224 kb
Host smart-d65608c3-ca6e-4718-9d81-8498387bef88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24272
07916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2427207916
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3765570355
Short name T2402
Test name
Test status
Simulation time 148071265 ps
CPU time 0.8 seconds
Started Jul 02 09:08:42 AM PDT 24
Finished Jul 02 09:08:44 AM PDT 24
Peak memory 206196 kb
Host smart-461a4547-a191-4be1-99de-9fd177093c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37655
70355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3765570355
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1279738204
Short name T937
Test name
Test status
Simulation time 395376765 ps
CPU time 1.26 seconds
Started Jul 02 09:08:42 AM PDT 24
Finished Jul 02 09:08:45 AM PDT 24
Peak memory 206208 kb
Host smart-afce8148-032f-4678-93b2-8c2c4bba2f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12797
38204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1279738204
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1714759512
Short name T1195
Test name
Test status
Simulation time 563915239 ps
CPU time 1.43 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:28 AM PDT 24
Peak memory 206200 kb
Host smart-10238782-2162-41e7-ba3c-b1f37ec3d369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17147
59512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1714759512
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.2594789354
Short name T2134
Test name
Test status
Simulation time 10570897707 ps
CPU time 19.59 seconds
Started Jul 02 09:08:14 AM PDT 24
Finished Jul 02 09:08:34 AM PDT 24
Peak memory 206480 kb
Host smart-a39f2161-ad3f-489d-92dc-c1726565135d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25947
89354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.2594789354
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1034093551
Short name T1876
Test name
Test status
Simulation time 354722385 ps
CPU time 1.29 seconds
Started Jul 02 09:08:16 AM PDT 24
Finished Jul 02 09:08:18 AM PDT 24
Peak memory 206124 kb
Host smart-c6b90071-3e6a-4164-bdfc-5d0f018fafdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10340
93551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1034093551
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.432881043
Short name T1374
Test name
Test status
Simulation time 157784462 ps
CPU time 0.76 seconds
Started Jul 02 09:08:43 AM PDT 24
Finished Jul 02 09:08:45 AM PDT 24
Peak memory 206200 kb
Host smart-c3072674-613c-48d0-beb1-73fe0092f2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43288
1043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.432881043
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1406456568
Short name T1994
Test name
Test status
Simulation time 37151289 ps
CPU time 0.64 seconds
Started Jul 02 09:08:50 AM PDT 24
Finished Jul 02 09:08:51 AM PDT 24
Peak memory 206196 kb
Host smart-4f965636-2bb9-4b4b-8657-145dc70a3283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14064
56568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1406456568
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.662863572
Short name T2494
Test name
Test status
Simulation time 844525439 ps
CPU time 2.05 seconds
Started Jul 02 09:08:14 AM PDT 24
Finished Jul 02 09:08:17 AM PDT 24
Peak memory 206404 kb
Host smart-efe084ad-1fe7-4589-9c82-8f2dfcc9f00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66286
3572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.662863572
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1854463122
Short name T1395
Test name
Test status
Simulation time 242700617 ps
CPU time 1.38 seconds
Started Jul 02 09:08:43 AM PDT 24
Finished Jul 02 09:08:46 AM PDT 24
Peak memory 206460 kb
Host smart-a0e2bfe5-1f20-4a9a-86fa-fa3d091570a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18544
63122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1854463122
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3430152156
Short name T2195
Test name
Test status
Simulation time 177434514 ps
CPU time 0.82 seconds
Started Jul 02 09:08:49 AM PDT 24
Finished Jul 02 09:08:51 AM PDT 24
Peak memory 206204 kb
Host smart-3af16e1c-64dd-4d9f-b384-f9587164a545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34301
52156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3430152156
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1876861319
Short name T440
Test name
Test status
Simulation time 149106866 ps
CPU time 0.72 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:26 AM PDT 24
Peak memory 206192 kb
Host smart-451dae93-c140-4dc0-ab39-c9d06674f54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18768
61319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1876861319
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.21626793
Short name T1136
Test name
Test status
Simulation time 259274704 ps
CPU time 0.97 seconds
Started Jul 02 09:08:14 AM PDT 24
Finished Jul 02 09:08:16 AM PDT 24
Peak memory 206188 kb
Host smart-fe33ea10-b36d-4c1c-96a9-9931934671ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21626
793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.21626793
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3826998674
Short name T595
Test name
Test status
Simulation time 206787987 ps
CPU time 0.88 seconds
Started Jul 02 09:08:24 AM PDT 24
Finished Jul 02 09:08:28 AM PDT 24
Peak memory 206196 kb
Host smart-aaf9770a-a325-42f9-9f2c-344692a072ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38269
98674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3826998674
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.2019901088
Short name T238
Test name
Test status
Simulation time 23282460316 ps
CPU time 23.27 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:45 AM PDT 24
Peak memory 206284 kb
Host smart-dd220e0e-a77a-44cb-8cb2-2a7e255f4d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20199
01088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2019901088
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3828616775
Short name T1379
Test name
Test status
Simulation time 3268910674 ps
CPU time 3.7 seconds
Started Jul 02 09:08:19 AM PDT 24
Finished Jul 02 09:08:24 AM PDT 24
Peak memory 206188 kb
Host smart-15155a4d-288e-4d75-a570-05bf5d827ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38286
16775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3828616775
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.988403279
Short name T1362
Test name
Test status
Simulation time 12679771519 ps
CPU time 90.35 seconds
Started Jul 02 09:08:18 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206532 kb
Host smart-d7816ad3-868e-460e-b054-2ccce0e7657e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98840
3279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.988403279
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.882736456
Short name T1896
Test name
Test status
Simulation time 4913226425 ps
CPU time 144.85 seconds
Started Jul 02 09:08:19 AM PDT 24
Finished Jul 02 09:10:45 AM PDT 24
Peak memory 206688 kb
Host smart-7086f200-9dc7-46cd-934e-030cf41a0bca
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=882736456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.882736456
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1916170332
Short name T2555
Test name
Test status
Simulation time 248239014 ps
CPU time 0.94 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:28 AM PDT 24
Peak memory 206188 kb
Host smart-b6ae301b-1c91-4abb-ac6f-2fb525289872
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1916170332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1916170332
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.327966281
Short name T2364
Test name
Test status
Simulation time 188435180 ps
CPU time 0.85 seconds
Started Jul 02 09:08:18 AM PDT 24
Finished Jul 02 09:08:19 AM PDT 24
Peak memory 206188 kb
Host smart-b09c5997-9035-49d9-a269-9d445e44bf40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32796
6281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.327966281
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.2137693551
Short name T1717
Test name
Test status
Simulation time 4076525074 ps
CPU time 38.7 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:09:05 AM PDT 24
Peak memory 206472 kb
Host smart-96bcce58-00ef-44cd-8af8-04d7c164d18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21376
93551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2137693551
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3452368768
Short name T2654
Test name
Test status
Simulation time 4476052966 ps
CPU time 32.84 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:54 AM PDT 24
Peak memory 205596 kb
Host smart-b2f04ced-1151-4120-8dd0-9287b1ae5373
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3452368768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3452368768
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2190766906
Short name T1789
Test name
Test status
Simulation time 231700157 ps
CPU time 0.86 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206180 kb
Host smart-66f22055-7e96-4d1b-80b0-b86d90138b2f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2190766906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2190766906
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3423760155
Short name T650
Test name
Test status
Simulation time 153873814 ps
CPU time 0.84 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206224 kb
Host smart-21b9ef9e-a5e2-430d-acfa-8a7561815225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34237
60155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3423760155
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2470073314
Short name T120
Test name
Test status
Simulation time 215771294 ps
CPU time 0.88 seconds
Started Jul 02 09:08:19 AM PDT 24
Finished Jul 02 09:08:21 AM PDT 24
Peak memory 206212 kb
Host smart-3462ad2b-7b50-4926-abaf-57644a061202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24700
73314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2470073314
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1513049594
Short name T2032
Test name
Test status
Simulation time 220675090 ps
CPU time 0.88 seconds
Started Jul 02 09:08:21 AM PDT 24
Finished Jul 02 09:08:23 AM PDT 24
Peak memory 206200 kb
Host smart-f7f70a1d-663b-43da-a751-9935eda06ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15130
49594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1513049594
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1452956194
Short name T454
Test name
Test status
Simulation time 172001609 ps
CPU time 0.85 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:27 AM PDT 24
Peak memory 206136 kb
Host smart-5ab13777-d4aa-4b77-932c-dabcd90ea048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14529
56194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1452956194
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2683423275
Short name T1142
Test name
Test status
Simulation time 226615390 ps
CPU time 0.84 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206208 kb
Host smart-918a37d1-cf88-49fd-84cf-ddee13b39daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26834
23275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2683423275
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.23105309
Short name T509
Test name
Test status
Simulation time 159200119 ps
CPU time 0.8 seconds
Started Jul 02 09:08:19 AM PDT 24
Finished Jul 02 09:08:21 AM PDT 24
Peak memory 206184 kb
Host smart-d090205a-988a-4acc-a543-c4b0f85fd260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23105
309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.23105309
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2853134764
Short name T1310
Test name
Test status
Simulation time 254224738 ps
CPU time 0.97 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206144 kb
Host smart-cdb10eb9-da6e-479a-941f-13bb6edc8f56
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2853134764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2853134764
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2291273298
Short name T507
Test name
Test status
Simulation time 153133235 ps
CPU time 0.77 seconds
Started Jul 02 09:08:18 AM PDT 24
Finished Jul 02 09:08:19 AM PDT 24
Peak memory 206212 kb
Host smart-a98b23f0-23b8-4b81-8a0c-3989108444d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22912
73298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2291273298
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3520003719
Short name T2052
Test name
Test status
Simulation time 44607547 ps
CPU time 0.7 seconds
Started Jul 02 09:08:21 AM PDT 24
Finished Jul 02 09:08:23 AM PDT 24
Peak memory 206196 kb
Host smart-843b1d6e-13bd-4270-9ac8-093b5eb7bee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35200
03719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3520003719
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1207436191
Short name T1085
Test name
Test status
Simulation time 16001768487 ps
CPU time 36.32 seconds
Started Jul 02 09:08:19 AM PDT 24
Finished Jul 02 09:08:56 AM PDT 24
Peak memory 206512 kb
Host smart-1e40db19-5df0-431e-927c-19300c92b1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12074
36191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1207436191
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4232985630
Short name T692
Test name
Test status
Simulation time 248778475 ps
CPU time 0.86 seconds
Started Jul 02 09:08:19 AM PDT 24
Finished Jul 02 09:08:20 AM PDT 24
Peak memory 206220 kb
Host smart-097d0796-18b5-496e-9043-9f0568b203f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42329
85630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4232985630
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3750023375
Short name T1654
Test name
Test status
Simulation time 254608801 ps
CPU time 0.98 seconds
Started Jul 02 09:08:19 AM PDT 24
Finished Jul 02 09:08:20 AM PDT 24
Peak memory 206116 kb
Host smart-0566c6b7-f7d3-4de3-8857-96b5f8b09ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37500
23375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3750023375
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3516224687
Short name T442
Test name
Test status
Simulation time 248432240 ps
CPU time 0.87 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206164 kb
Host smart-a6d3fb44-f450-435d-8b27-3141a2e47154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35162
24687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3516224687
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2277512904
Short name T2246
Test name
Test status
Simulation time 171304083 ps
CPU time 0.8 seconds
Started Jul 02 09:08:19 AM PDT 24
Finished Jul 02 09:08:21 AM PDT 24
Peak memory 206180 kb
Host smart-89377e27-0238-43ae-9428-f7587ec9a74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22775
12904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2277512904
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2723146312
Short name T626
Test name
Test status
Simulation time 199753827 ps
CPU time 0.91 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206340 kb
Host smart-0e0de73e-d33a-4b34-9394-9ba038cb20fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27231
46312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2723146312
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1673888321
Short name T732
Test name
Test status
Simulation time 176645287 ps
CPU time 0.83 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206200 kb
Host smart-a625e015-6ec9-42d0-b29f-c106e461bfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16738
88321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1673888321
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1306954009
Short name T2249
Test name
Test status
Simulation time 164575936 ps
CPU time 0.79 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206132 kb
Host smart-92907f71-5f5b-483b-9bd7-6223f389bc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13069
54009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1306954009
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.285639494
Short name T1839
Test name
Test status
Simulation time 197218152 ps
CPU time 0.89 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:27 AM PDT 24
Peak memory 206140 kb
Host smart-c24be843-1067-4590-93c4-2ad594f6dd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28563
9494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.285639494
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2839502917
Short name T1098
Test name
Test status
Simulation time 3227273072 ps
CPU time 29.16 seconds
Started Jul 02 09:08:21 AM PDT 24
Finished Jul 02 09:08:52 AM PDT 24
Peak memory 206448 kb
Host smart-7367d3b2-d847-4423-8385-baa4453d7575
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2839502917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2839502917
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2889119002
Short name T1024
Test name
Test status
Simulation time 169002258 ps
CPU time 0.81 seconds
Started Jul 02 09:08:19 AM PDT 24
Finished Jul 02 09:08:20 AM PDT 24
Peak memory 206180 kb
Host smart-7b3e720d-e790-4c90-b4a2-1a56faf2a408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28891
19002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2889119002
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1980220341
Short name T1969
Test name
Test status
Simulation time 148554317 ps
CPU time 0.78 seconds
Started Jul 02 09:08:20 AM PDT 24
Finished Jul 02 09:08:21 AM PDT 24
Peak memory 205524 kb
Host smart-85453e4d-140d-4070-a3fa-22846ecde874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19802
20341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1980220341
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.495590977
Short name T1748
Test name
Test status
Simulation time 883821643 ps
CPU time 1.99 seconds
Started Jul 02 09:08:22 AM PDT 24
Finished Jul 02 09:08:25 AM PDT 24
Peak memory 206460 kb
Host smart-02a877e0-7686-4cfb-9415-1c11aab9ddfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49559
0977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.495590977
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2548104456
Short name T809
Test name
Test status
Simulation time 7180825963 ps
CPU time 51.04 seconds
Started Jul 02 09:08:21 AM PDT 24
Finished Jul 02 09:09:13 AM PDT 24
Peak memory 206464 kb
Host smart-c358c816-5b7e-4768-9fc8-1cd9b0bf0cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25481
04456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2548104456
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.1374316243
Short name T1823
Test name
Test status
Simulation time 42390969 ps
CPU time 0.68 seconds
Started Jul 02 09:08:31 AM PDT 24
Finished Jul 02 09:08:33 AM PDT 24
Peak memory 206252 kb
Host smart-59a98933-4c69-4103-b39f-a02fd828adc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1374316243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.1374316243
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2789314575
Short name T1064
Test name
Test status
Simulation time 4049702696 ps
CPU time 5.02 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:32 AM PDT 24
Peak memory 206448 kb
Host smart-d9f7b02a-15ba-49f1-a26b-78a513ed0401
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2789314575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2789314575
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2023780965
Short name T2478
Test name
Test status
Simulation time 13431439229 ps
CPU time 13.88 seconds
Started Jul 02 09:08:24 AM PDT 24
Finished Jul 02 09:08:41 AM PDT 24
Peak memory 206460 kb
Host smart-34c102e9-8cd4-4d3d-8fad-9539dc2487f9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2023780965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2023780965
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.4074122873
Short name T564
Test name
Test status
Simulation time 168559334 ps
CPU time 0.78 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:26 AM PDT 24
Peak memory 206164 kb
Host smart-a59a5b8b-84fc-473e-8dcf-7c3da7006919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40741
22873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.4074122873
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3455516441
Short name T1153
Test name
Test status
Simulation time 164073972 ps
CPU time 0.82 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:27 AM PDT 24
Peak memory 206176 kb
Host smart-d6e7fe6f-39dd-4e4e-8419-c80e9d3f0d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34555
16441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3455516441
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.743129617
Short name T1104
Test name
Test status
Simulation time 376167554 ps
CPU time 1.31 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:27 AM PDT 24
Peak memory 206204 kb
Host smart-69871788-4edd-4036-be2e-cf4480db864a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74312
9617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.743129617
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.5443245
Short name T2453
Test name
Test status
Simulation time 971798134 ps
CPU time 2.33 seconds
Started Jul 02 09:08:24 AM PDT 24
Finished Jul 02 09:08:29 AM PDT 24
Peak memory 206444 kb
Host smart-f770f8db-ead4-4141-9342-0d576e3ffe13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54432
45 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.5443245
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.1435328208
Short name T1309
Test name
Test status
Simulation time 452783998 ps
CPU time 1.31 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:26 AM PDT 24
Peak memory 206208 kb
Host smart-d3f455fb-eea3-480f-9037-ae98d62fd567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
28208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.1435328208
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.427813028
Short name T1056
Test name
Test status
Simulation time 172260035 ps
CPU time 0.77 seconds
Started Jul 02 09:08:25 AM PDT 24
Finished Jul 02 09:08:29 AM PDT 24
Peak memory 206172 kb
Host smart-1fa293b6-16e9-419f-b20c-916bf049710a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42781
3028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.427813028
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.2229399052
Short name T977
Test name
Test status
Simulation time 66191760 ps
CPU time 0.7 seconds
Started Jul 02 09:08:22 AM PDT 24
Finished Jul 02 09:08:24 AM PDT 24
Peak memory 206164 kb
Host smart-b2d23821-8eea-4225-90ed-437336bc6750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22293
99052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2229399052
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1880887629
Short name T1718
Test name
Test status
Simulation time 1031483401 ps
CPU time 2.11 seconds
Started Jul 02 09:08:26 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206368 kb
Host smart-aac3649a-3384-4ecf-87af-91637994314f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18808
87629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1880887629
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2263764502
Short name T1385
Test name
Test status
Simulation time 260975542 ps
CPU time 1.89 seconds
Started Jul 02 09:08:26 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206376 kb
Host smart-3315828b-d413-4b6d-9d6c-df99ec72ab1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22637
64502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2263764502
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2108535378
Short name T1829
Test name
Test status
Simulation time 201828416 ps
CPU time 0.8 seconds
Started Jul 02 09:08:24 AM PDT 24
Finished Jul 02 09:08:28 AM PDT 24
Peak memory 206180 kb
Host smart-e5763149-8c53-4d1e-8a12-251483589ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21085
35378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2108535378
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3528056228
Short name T1992
Test name
Test status
Simulation time 147648727 ps
CPU time 0.84 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:27 AM PDT 24
Peak memory 206192 kb
Host smart-d5fd4de0-b36b-466d-b918-6f5f3bfa339d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35280
56228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3528056228
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2851022555
Short name T1752
Test name
Test status
Simulation time 202121043 ps
CPU time 0.86 seconds
Started Jul 02 09:08:24 AM PDT 24
Finished Jul 02 09:08:28 AM PDT 24
Peak memory 206164 kb
Host smart-9bc4ca47-5bbe-414e-bc9b-639caf39e5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28510
22555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2851022555
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.1742652315
Short name T2176
Test name
Test status
Simulation time 9877873090 ps
CPU time 271.62 seconds
Started Jul 02 09:08:22 AM PDT 24
Finished Jul 02 09:12:55 AM PDT 24
Peak memory 206488 kb
Host smart-044e2a6e-2a96-4ac6-b679-510214d24af2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1742652315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1742652315
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3684844297
Short name T1686
Test name
Test status
Simulation time 169392002 ps
CPU time 0.85 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:27 AM PDT 24
Peak memory 206164 kb
Host smart-aa711ca9-0c6b-4c1e-853a-fae1044f5fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36848
44297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3684844297
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3205066608
Short name T2612
Test name
Test status
Simulation time 23300070588 ps
CPU time 20.79 seconds
Started Jul 02 09:08:24 AM PDT 24
Finished Jul 02 09:08:48 AM PDT 24
Peak memory 206240 kb
Host smart-4f59ce8a-8c01-4acf-9223-f048b8b5a725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32050
66608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3205066608
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.4218889218
Short name T833
Test name
Test status
Simulation time 3310632116 ps
CPU time 3.78 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:08:30 AM PDT 24
Peak memory 206240 kb
Host smart-6cf08a1e-9c5d-4f2d-ada2-96f68536cf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42188
89218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.4218889218
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2358979685
Short name T1785
Test name
Test status
Simulation time 5993148994 ps
CPU time 168.68 seconds
Started Jul 02 09:08:23 AM PDT 24
Finished Jul 02 09:11:15 AM PDT 24
Peak memory 206512 kb
Host smart-56609a3d-cbb2-4b87-a3c6-dc74dd04ceeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23589
79685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2358979685
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.1505719077
Short name T1837
Test name
Test status
Simulation time 5174823277 ps
CPU time 140.72 seconds
Started Jul 02 09:08:26 AM PDT 24
Finished Jul 02 09:10:50 AM PDT 24
Peak memory 206364 kb
Host smart-ae7d069f-b849-4900-aa92-3db011a707cd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1505719077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.1505719077
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1360473703
Short name T1280
Test name
Test status
Simulation time 233839517 ps
CPU time 0.97 seconds
Started Jul 02 09:08:29 AM PDT 24
Finished Jul 02 09:08:32 AM PDT 24
Peak memory 206160 kb
Host smart-4238b19e-0046-44e1-9d88-8f3d93db10ce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1360473703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1360473703
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2073092351
Short name T85
Test name
Test status
Simulation time 195810278 ps
CPU time 0.89 seconds
Started Jul 02 09:08:31 AM PDT 24
Finished Jul 02 09:08:34 AM PDT 24
Peak memory 206228 kb
Host smart-41a2237f-3682-49a6-8dd3-3972f1a98e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20730
92351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2073092351
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.4138856914
Short name T1388
Test name
Test status
Simulation time 3639035170 ps
CPU time 34.42 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:09:07 AM PDT 24
Peak memory 206508 kb
Host smart-d94f6b77-783a-4d7b-845d-89579afbffef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41388
56914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.4138856914
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2733857272
Short name T2557
Test name
Test status
Simulation time 7753033949 ps
CPU time 203.25 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:11:55 AM PDT 24
Peak memory 206448 kb
Host smart-b8e0f30b-862b-44aa-92c2-f6c1dc70a7c5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2733857272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2733857272
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1353949986
Short name T2242
Test name
Test status
Simulation time 150218162 ps
CPU time 0.83 seconds
Started Jul 02 09:08:28 AM PDT 24
Finished Jul 02 09:08:32 AM PDT 24
Peak memory 206188 kb
Host smart-d77cd32f-6309-46f3-a791-adb3ff78c6ff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1353949986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1353949986
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2252723506
Short name T750
Test name
Test status
Simulation time 229987691 ps
CPU time 0.82 seconds
Started Jul 02 09:08:52 AM PDT 24
Finished Jul 02 09:08:53 AM PDT 24
Peak memory 206204 kb
Host smart-e6a13afc-9f38-4e67-a7ac-79acc989b012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
23506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2252723506
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1247741423
Short name T2704
Test name
Test status
Simulation time 193569786 ps
CPU time 0.83 seconds
Started Jul 02 09:08:27 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206212 kb
Host smart-070edb24-0cc6-40fc-8111-0fce9d74de3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12477
41423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1247741423
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2552318224
Short name T1254
Test name
Test status
Simulation time 150909760 ps
CPU time 0.87 seconds
Started Jul 02 09:08:29 AM PDT 24
Finished Jul 02 09:08:33 AM PDT 24
Peak memory 206192 kb
Host smart-a9bee779-f942-4d8f-b67e-a069aecdc903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25523
18224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2552318224
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3822289199
Short name T523
Test name
Test status
Simulation time 165322898 ps
CPU time 0.8 seconds
Started Jul 02 09:08:27 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206180 kb
Host smart-c54f8e30-f92e-4bae-8ae0-2378fba53273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38222
89199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3822289199
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1823610490
Short name T2595
Test name
Test status
Simulation time 180518714 ps
CPU time 0.88 seconds
Started Jul 02 09:08:25 AM PDT 24
Finished Jul 02 09:08:29 AM PDT 24
Peak memory 206128 kb
Host smart-b368f4e6-508a-4fda-a5c0-59710b8a6361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18236
10490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1823610490
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2200070049
Short name T740
Test name
Test status
Simulation time 154990817 ps
CPU time 0.78 seconds
Started Jul 02 09:08:27 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206204 kb
Host smart-72e6d4da-c74f-4e01-8b1b-f4f9e72a68c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22000
70049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2200070049
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.3200519619
Short name T2068
Test name
Test status
Simulation time 244526516 ps
CPU time 0.96 seconds
Started Jul 02 09:08:24 AM PDT 24
Finished Jul 02 09:08:29 AM PDT 24
Peak memory 206168 kb
Host smart-23ce2029-9a0d-44fb-8bdb-243c061e72fe
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3200519619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.3200519619
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1353732278
Short name T1672
Test name
Test status
Simulation time 161487683 ps
CPU time 0.79 seconds
Started Jul 02 09:08:26 AM PDT 24
Finished Jul 02 09:08:30 AM PDT 24
Peak memory 206388 kb
Host smart-989cbea7-ed5a-4a58-b7c0-ab6f196f0763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13537
32278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1353732278
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2732679981
Short name T276
Test name
Test status
Simulation time 13162989366 ps
CPU time 29.89 seconds
Started Jul 02 09:08:27 AM PDT 24
Finished Jul 02 09:09:00 AM PDT 24
Peak memory 206528 kb
Host smart-6ed9aef8-2c30-4a08-8975-054b2273d224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27326
79981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2732679981
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1564018585
Short name T449
Test name
Test status
Simulation time 180587377 ps
CPU time 0.82 seconds
Started Jul 02 09:08:28 AM PDT 24
Finished Jul 02 09:08:32 AM PDT 24
Peak memory 206208 kb
Host smart-0738f619-67b1-40b0-a1bc-275738863d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640
18585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1564018585
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3020808077
Short name T149
Test name
Test status
Simulation time 171647387 ps
CPU time 0.87 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:08:33 AM PDT 24
Peak memory 206184 kb
Host smart-ff9fccfd-7f24-4394-8222-94e2449a99be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30208
08077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3020808077
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2966449950
Short name T1140
Test name
Test status
Simulation time 208084325 ps
CPU time 0.93 seconds
Started Jul 02 09:08:28 AM PDT 24
Finished Jul 02 09:08:32 AM PDT 24
Peak memory 206180 kb
Host smart-43097f0f-3494-4d44-861f-f4dd3c226a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29664
49950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2966449950
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2684676850
Short name T1831
Test name
Test status
Simulation time 152818140 ps
CPU time 0.77 seconds
Started Jul 02 09:08:27 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206196 kb
Host smart-36a94bff-461f-449b-a601-ef316cae8eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26846
76850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2684676850
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.64372514
Short name T2180
Test name
Test status
Simulation time 149344818 ps
CPU time 0.76 seconds
Started Jul 02 09:08:27 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206192 kb
Host smart-9a895210-c4ef-4fdc-8c4a-112e244bf5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64372
514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.64372514
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.1806932075
Short name T1661
Test name
Test status
Simulation time 165022555 ps
CPU time 0.91 seconds
Started Jul 02 09:08:31 AM PDT 24
Finished Jul 02 09:08:34 AM PDT 24
Peak memory 206220 kb
Host smart-e8f093f0-77b8-4652-a47c-82da07e2d4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18069
32075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1806932075
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.4144261986
Short name T2457
Test name
Test status
Simulation time 157136375 ps
CPU time 0.77 seconds
Started Jul 02 09:08:27 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206196 kb
Host smart-bb15898b-9006-4e67-85b1-d1a973843bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41442
61986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.4144261986
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3374662345
Short name T434
Test name
Test status
Simulation time 261376906 ps
CPU time 0.96 seconds
Started Jul 02 09:08:29 AM PDT 24
Finished Jul 02 09:08:32 AM PDT 24
Peak memory 206124 kb
Host smart-bba5dbfb-5751-48ea-964f-d3f30e2d94f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33746
62345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3374662345
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.3623242789
Short name T2026
Test name
Test status
Simulation time 6970167167 ps
CPU time 67.26 seconds
Started Jul 02 09:08:27 AM PDT 24
Finished Jul 02 09:09:37 AM PDT 24
Peak memory 206488 kb
Host smart-e880ed30-814a-4e9a-b348-5d57c02aff15
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3623242789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.3623242789
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1269185648
Short name T835
Test name
Test status
Simulation time 167192427 ps
CPU time 0.88 seconds
Started Jul 02 09:08:29 AM PDT 24
Finished Jul 02 09:08:33 AM PDT 24
Peak memory 206216 kb
Host smart-65f08e15-5ace-4151-9d42-ebbc1cb9af43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12691
85648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1269185648
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1184626814
Short name T2463
Test name
Test status
Simulation time 227638164 ps
CPU time 0.88 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:08:33 AM PDT 24
Peak memory 206200 kb
Host smart-dae008eb-0258-4dcc-af52-61848cebfdb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11846
26814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1184626814
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.3002087993
Short name T2371
Test name
Test status
Simulation time 600142003 ps
CPU time 1.44 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:08:33 AM PDT 24
Peak memory 206164 kb
Host smart-dd6324fa-639c-4f5e-8193-256080a78602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30020
87993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3002087993
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2718410511
Short name T1612
Test name
Test status
Simulation time 6993275403 ps
CPU time 50.63 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:09:23 AM PDT 24
Peak memory 206492 kb
Host smart-a9a98ade-fe14-40e8-83a0-f2429f69b451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27184
10511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2718410511
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2327918300
Short name T2025
Test name
Test status
Simulation time 40185438 ps
CPU time 0.66 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:08:59 AM PDT 24
Peak memory 206256 kb
Host smart-c992b6a2-53bd-4ee1-a028-257bf7da77ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2327918300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2327918300
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1215165347
Short name T2301
Test name
Test status
Simulation time 3501532356 ps
CPU time 3.96 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:08:36 AM PDT 24
Peak memory 206496 kb
Host smart-19359854-a40c-49cb-b033-8ef6ca45660d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1215165347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1215165347
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3358190392
Short name T930
Test name
Test status
Simulation time 13387631875 ps
CPU time 13.19 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:08:45 AM PDT 24
Peak memory 206520 kb
Host smart-c11747b3-a491-4358-97c4-efb0908fe696
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3358190392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3358190392
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2641026859
Short name T10
Test name
Test status
Simulation time 23376098096 ps
CPU time 29.4 seconds
Started Jul 02 09:08:33 AM PDT 24
Finished Jul 02 09:09:03 AM PDT 24
Peak memory 206244 kb
Host smart-04bf929d-bfcf-4062-812a-986db2a11e19
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2641026859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2641026859
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2141058491
Short name T1009
Test name
Test status
Simulation time 164586809 ps
CPU time 0.79 seconds
Started Jul 02 09:08:29 AM PDT 24
Finished Jul 02 09:08:33 AM PDT 24
Peak memory 206212 kb
Host smart-926aa833-1a80-4bb6-9c22-5a0cecc0bbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21410
58491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2141058491
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1582545370
Short name T2019
Test name
Test status
Simulation time 155658562 ps
CPU time 0.78 seconds
Started Jul 02 09:08:31 AM PDT 24
Finished Jul 02 09:08:34 AM PDT 24
Peak memory 206164 kb
Host smart-d509ceb4-579b-4e95-b65b-adc3dd9aec79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15825
45370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1582545370
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.3807700053
Short name T1608
Test name
Test status
Simulation time 184983041 ps
CPU time 0.85 seconds
Started Jul 02 09:08:29 AM PDT 24
Finished Jul 02 09:08:33 AM PDT 24
Peak memory 206184 kb
Host smart-7c473168-5e2e-44e1-8e2e-e57bafac2974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38077
00053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.3807700053
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.57256805
Short name T181
Test name
Test status
Simulation time 996972591 ps
CPU time 2.13 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:08:34 AM PDT 24
Peak memory 206360 kb
Host smart-706bec45-7414-48fb-93aa-6016dbb8fb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57256
805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.57256805
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.2305011936
Short name T1445
Test name
Test status
Simulation time 8394276234 ps
CPU time 14.9 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:08:47 AM PDT 24
Peak memory 206552 kb
Host smart-efea73cf-67b2-42b8-9a8f-e99788938a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23050
11936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.2305011936
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.132429072
Short name T1605
Test name
Test status
Simulation time 512127962 ps
CPU time 1.69 seconds
Started Jul 02 09:08:30 AM PDT 24
Finished Jul 02 09:08:34 AM PDT 24
Peak memory 206212 kb
Host smart-3155a45c-9fba-44a7-ba71-a3c7bfaf6541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13242
9072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.132429072
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.11698854
Short name T1928
Test name
Test status
Simulation time 157205759 ps
CPU time 0.82 seconds
Started Jul 02 09:08:35 AM PDT 24
Finished Jul 02 09:08:36 AM PDT 24
Peak memory 206124 kb
Host smart-5bc84def-4f0f-4055-99bb-542d79338f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11698
854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.11698854
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1235770343
Short name T2130
Test name
Test status
Simulation time 66794655 ps
CPU time 0.7 seconds
Started Jul 02 09:08:40 AM PDT 24
Finished Jul 02 09:08:42 AM PDT 24
Peak memory 206204 kb
Host smart-a13f6445-9b73-4af2-a82a-7831a75b1592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12357
70343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1235770343
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1935140152
Short name T1345
Test name
Test status
Simulation time 844269285 ps
CPU time 2.29 seconds
Started Jul 02 09:08:39 AM PDT 24
Finished Jul 02 09:08:42 AM PDT 24
Peak memory 206408 kb
Host smart-b6b59695-6637-4243-ae86-53bde0a87a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19351
40152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1935140152
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1032693801
Short name T993
Test name
Test status
Simulation time 307416054 ps
CPU time 2.23 seconds
Started Jul 02 09:08:34 AM PDT 24
Finished Jul 02 09:08:36 AM PDT 24
Peak memory 206404 kb
Host smart-e5f86432-3a4e-405b-b9c3-b915a25817cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10326
93801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1032693801
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1769283154
Short name T526
Test name
Test status
Simulation time 228063990 ps
CPU time 0.87 seconds
Started Jul 02 09:08:34 AM PDT 24
Finished Jul 02 09:08:36 AM PDT 24
Peak memory 206216 kb
Host smart-676cbcd5-2b6e-46b9-b5a5-62aae65c2a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17692
83154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1769283154
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3963045810
Short name T1951
Test name
Test status
Simulation time 193852079 ps
CPU time 0.82 seconds
Started Jul 02 09:08:39 AM PDT 24
Finished Jul 02 09:08:41 AM PDT 24
Peak memory 206208 kb
Host smart-a97473e9-3359-4b12-9a91-6605c5d96f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39630
45810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3963045810
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4116935821
Short name T768
Test name
Test status
Simulation time 250220962 ps
CPU time 0.94 seconds
Started Jul 02 09:08:36 AM PDT 24
Finished Jul 02 09:08:38 AM PDT 24
Peak memory 206164 kb
Host smart-c197b968-fae1-4f7d-913b-a6ba1785ab9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41169
35821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4116935821
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1980041449
Short name T107
Test name
Test status
Simulation time 219007246 ps
CPU time 0.97 seconds
Started Jul 02 09:08:37 AM PDT 24
Finished Jul 02 09:08:38 AM PDT 24
Peak memory 206180 kb
Host smart-fb8862c3-889a-4fbc-bd4e-0e72a178c9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19800
41449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1980041449
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.4085609995
Short name T823
Test name
Test status
Simulation time 23316758126 ps
CPU time 27.05 seconds
Started Jul 02 09:08:36 AM PDT 24
Finished Jul 02 09:09:04 AM PDT 24
Peak memory 206204 kb
Host smart-be5fca65-c712-401a-a277-017413ce6729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40856
09995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.4085609995
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2180658399
Short name T2524
Test name
Test status
Simulation time 3290100513 ps
CPU time 3.59 seconds
Started Jul 02 09:08:40 AM PDT 24
Finished Jul 02 09:08:45 AM PDT 24
Peak memory 206108 kb
Host smart-4beafdc1-7402-44f4-9406-18eb9ca720ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21806
58399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2180658399
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.3443252583
Short name T462
Test name
Test status
Simulation time 7559272598 ps
CPU time 73.36 seconds
Started Jul 02 09:08:42 AM PDT 24
Finished Jul 02 09:09:56 AM PDT 24
Peak memory 206524 kb
Host smart-285c84b3-a347-4ec1-af2d-34dd9c89873b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34432
52583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.3443252583
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.3028215879
Short name T2680
Test name
Test status
Simulation time 5314578269 ps
CPU time 53.18 seconds
Started Jul 02 09:08:36 AM PDT 24
Finished Jul 02 09:09:30 AM PDT 24
Peak memory 206476 kb
Host smart-2509e991-249c-49b8-bc6f-1a2a69883685
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3028215879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.3028215879
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.2945102150
Short name T435
Test name
Test status
Simulation time 235763836 ps
CPU time 0.88 seconds
Started Jul 02 09:08:35 AM PDT 24
Finished Jul 02 09:08:36 AM PDT 24
Peak memory 206188 kb
Host smart-3f374947-045d-40b7-81f6-67e614d77027
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2945102150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.2945102150
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2319957868
Short name T2338
Test name
Test status
Simulation time 191822215 ps
CPU time 0.87 seconds
Started Jul 02 09:08:36 AM PDT 24
Finished Jul 02 09:08:38 AM PDT 24
Peak memory 206168 kb
Host smart-572627cb-650b-4314-840e-7fdbd38f4616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23199
57868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2319957868
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.3201505433
Short name T1804
Test name
Test status
Simulation time 4665260692 ps
CPU time 45.4 seconds
Started Jul 02 09:08:35 AM PDT 24
Finished Jul 02 09:09:21 AM PDT 24
Peak memory 206500 kb
Host smart-b5a74bcf-d232-4ad8-bfc4-99c6c673e11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32015
05433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.3201505433
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1668993071
Short name T2355
Test name
Test status
Simulation time 5287139097 ps
CPU time 36.98 seconds
Started Jul 02 09:08:41 AM PDT 24
Finished Jul 02 09:09:18 AM PDT 24
Peak memory 206292 kb
Host smart-bb63d4c6-42b3-49ac-b82c-a59a2eb98a61
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1668993071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1668993071
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3903293521
Short name T2182
Test name
Test status
Simulation time 154220248 ps
CPU time 0.79 seconds
Started Jul 02 09:08:40 AM PDT 24
Finished Jul 02 09:08:42 AM PDT 24
Peak memory 206188 kb
Host smart-c806333b-1316-453b-a35e-8999a71c2e11
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3903293521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3903293521
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1684010333
Short name T1680
Test name
Test status
Simulation time 191188324 ps
CPU time 0.83 seconds
Started Jul 02 09:08:35 AM PDT 24
Finished Jul 02 09:08:36 AM PDT 24
Peak memory 206192 kb
Host smart-fdf8be08-f53d-4cb1-963c-8ba1c62baf68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16840
10333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1684010333
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.833673073
Short name T1339
Test name
Test status
Simulation time 242655278 ps
CPU time 0.89 seconds
Started Jul 02 09:08:42 AM PDT 24
Finished Jul 02 09:08:44 AM PDT 24
Peak memory 206208 kb
Host smart-e3738c92-09c7-45b8-8ba2-669e88461edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83367
3073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.833673073
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1002170164
Short name T2470
Test name
Test status
Simulation time 177733194 ps
CPU time 0.8 seconds
Started Jul 02 09:08:35 AM PDT 24
Finished Jul 02 09:08:37 AM PDT 24
Peak memory 206204 kb
Host smart-73af28cb-2992-4720-97ef-59feb6ab507f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10021
70164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1002170164
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3873902215
Short name T1655
Test name
Test status
Simulation time 213632201 ps
CPU time 0.82 seconds
Started Jul 02 09:08:42 AM PDT 24
Finished Jul 02 09:08:44 AM PDT 24
Peak memory 206204 kb
Host smart-c19888d0-2d46-4287-ad72-3e1256519da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38739
02215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3873902215
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.70575113
Short name T1328
Test name
Test status
Simulation time 158566598 ps
CPU time 0.8 seconds
Started Jul 02 09:08:38 AM PDT 24
Finished Jul 02 09:08:39 AM PDT 24
Peak memory 206180 kb
Host smart-fb1f73bd-f7e6-4500-9e88-553482bb6fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70575
113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.70575113
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.1298488651
Short name T1194
Test name
Test status
Simulation time 204482064 ps
CPU time 0.9 seconds
Started Jul 02 09:08:35 AM PDT 24
Finished Jul 02 09:08:36 AM PDT 24
Peak memory 206192 kb
Host smart-158a7a47-be5c-4a43-9b19-3414ec51973f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1298488651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.1298488651
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.521946400
Short name T356
Test name
Test status
Simulation time 173300261 ps
CPU time 0.8 seconds
Started Jul 02 09:08:37 AM PDT 24
Finished Jul 02 09:08:38 AM PDT 24
Peak memory 206184 kb
Host smart-9abb26f2-fa25-4e23-8fd9-b16cb1cfe539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52194
6400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.521946400
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1387189025
Short name T1590
Test name
Test status
Simulation time 52976067 ps
CPU time 0.66 seconds
Started Jul 02 09:08:40 AM PDT 24
Finished Jul 02 09:08:42 AM PDT 24
Peak memory 206204 kb
Host smart-9412554b-c68e-4682-a266-9920a3b2ee34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13871
89025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1387189025
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3963662052
Short name T278
Test name
Test status
Simulation time 18586410780 ps
CPU time 40.33 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:09:27 AM PDT 24
Peak memory 206496 kb
Host smart-ff7d9914-df00-4e7b-9563-e12c076cc49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39636
62052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3963662052
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.273941615
Short name T1390
Test name
Test status
Simulation time 186049055 ps
CPU time 0.86 seconds
Started Jul 02 09:08:40 AM PDT 24
Finished Jul 02 09:08:42 AM PDT 24
Peak memory 206200 kb
Host smart-e2d900aa-b4e5-4b15-9c8e-41ea6b0e526c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27394
1615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.273941615
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2143101000
Short name T2560
Test name
Test status
Simulation time 160524980 ps
CPU time 0.81 seconds
Started Jul 02 09:08:38 AM PDT 24
Finished Jul 02 09:08:40 AM PDT 24
Peak memory 206184 kb
Host smart-b95f9730-96d1-4fe3-9927-521f252d5dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21431
01000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2143101000
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.3808395222
Short name T1843
Test name
Test status
Simulation time 195444248 ps
CPU time 0.84 seconds
Started Jul 02 09:08:45 AM PDT 24
Finished Jul 02 09:08:48 AM PDT 24
Peak memory 206228 kb
Host smart-d1c7209f-c454-461b-9ac7-17f3a35e947c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38083
95222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.3808395222
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.876756774
Short name T1806
Test name
Test status
Simulation time 170841702 ps
CPU time 0.78 seconds
Started Jul 02 09:08:43 AM PDT 24
Finished Jul 02 09:08:46 AM PDT 24
Peak memory 206220 kb
Host smart-13b82db6-1255-43b6-ae3c-26a111c52192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87675
6774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.876756774
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2437683171
Short name T1167
Test name
Test status
Simulation time 173706753 ps
CPU time 0.83 seconds
Started Jul 02 09:08:45 AM PDT 24
Finished Jul 02 09:08:48 AM PDT 24
Peak memory 206200 kb
Host smart-990408cf-1f01-4d04-87c9-4b00f6030c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24376
83171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2437683171
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3306258089
Short name T1440
Test name
Test status
Simulation time 145655843 ps
CPU time 0.8 seconds
Started Jul 02 09:08:38 AM PDT 24
Finished Jul 02 09:08:40 AM PDT 24
Peak memory 206192 kb
Host smart-630d4d4b-4019-4a39-9878-557d8af987f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33062
58089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3306258089
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3579307713
Short name T51
Test name
Test status
Simulation time 152314588 ps
CPU time 0.77 seconds
Started Jul 02 09:08:38 AM PDT 24
Finished Jul 02 09:08:40 AM PDT 24
Peak memory 206124 kb
Host smart-2e78d9df-fb4a-439f-8c63-e7c06f3c5098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35793
07713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3579307713
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1285914369
Short name T1704
Test name
Test status
Simulation time 210117791 ps
CPU time 1 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:08:47 AM PDT 24
Peak memory 206188 kb
Host smart-50126c8a-dee5-47f0-8006-efe9083a6a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12859
14369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1285914369
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2882345346
Short name T601
Test name
Test status
Simulation time 5209207305 ps
CPU time 37.71 seconds
Started Jul 02 09:08:38 AM PDT 24
Finished Jul 02 09:09:16 AM PDT 24
Peak memory 206412 kb
Host smart-2b75c0a5-efee-4744-93cb-723a7cf8272f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2882345346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2882345346
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1551036366
Short name T746
Test name
Test status
Simulation time 157713787 ps
CPU time 0.81 seconds
Started Jul 02 09:08:41 AM PDT 24
Finished Jul 02 09:08:42 AM PDT 24
Peak memory 206204 kb
Host smart-94df5ae2-c199-4a32-a52a-9bcad2721ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15510
36366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1551036366
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3249963309
Short name T1658
Test name
Test status
Simulation time 180507475 ps
CPU time 0.81 seconds
Started Jul 02 09:08:39 AM PDT 24
Finished Jul 02 09:08:41 AM PDT 24
Peak memory 206164 kb
Host smart-83a8729b-ab01-4a4b-ac50-296a7d169715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32499
63309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3249963309
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.2325686694
Short name T2686
Test name
Test status
Simulation time 826627427 ps
CPU time 1.91 seconds
Started Jul 02 09:08:45 AM PDT 24
Finished Jul 02 09:08:49 AM PDT 24
Peak memory 206476 kb
Host smart-ed9a0c73-d461-44d5-bde9-ece98dc48fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23256
86694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.2325686694
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3796114583
Short name T1939
Test name
Test status
Simulation time 7912655280 ps
CPU time 60.47 seconds
Started Jul 02 09:08:38 AM PDT 24
Finished Jul 02 09:09:39 AM PDT 24
Peak memory 206476 kb
Host smart-1d498627-e12c-4978-ae65-76390d031262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37961
14583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3796114583
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.800830278
Short name T876
Test name
Test status
Simulation time 61254077 ps
CPU time 0.68 seconds
Started Jul 02 09:08:52 AM PDT 24
Finished Jul 02 09:08:54 AM PDT 24
Peak memory 206252 kb
Host smart-2040b6df-09cc-4fdb-b9fa-c7d3903f59c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=800830278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.800830278
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1703295604
Short name T1645
Test name
Test status
Simulation time 4545207898 ps
CPU time 5.62 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:09:04 AM PDT 24
Peak memory 206440 kb
Host smart-42f45f52-99f8-48fb-a935-726b9bc09dbb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1703295604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1703295604
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.4275626597
Short name T1461
Test name
Test status
Simulation time 13379377799 ps
CPU time 13.97 seconds
Started Jul 02 09:08:40 AM PDT 24
Finished Jul 02 09:08:54 AM PDT 24
Peak memory 206392 kb
Host smart-5586e2a0-c48f-4382-bc0f-cb5fa5865e45
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4275626597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.4275626597
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2368527155
Short name T1201
Test name
Test status
Simulation time 23347598270 ps
CPU time 23.42 seconds
Started Jul 02 09:08:39 AM PDT 24
Finished Jul 02 09:09:03 AM PDT 24
Peak memory 206432 kb
Host smart-2cee2316-a61f-4c74-a1ab-6e4509628069
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2368527155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2368527155
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2942796024
Short name T367
Test name
Test status
Simulation time 159918784 ps
CPU time 0.81 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:08:47 AM PDT 24
Peak memory 206188 kb
Host smart-ddba6a1b-e581-4b87-a5d3-48498d29955a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29427
96024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2942796024
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1835514026
Short name T1702
Test name
Test status
Simulation time 193897894 ps
CPU time 0.88 seconds
Started Jul 02 09:08:39 AM PDT 24
Finished Jul 02 09:08:40 AM PDT 24
Peak memory 206156 kb
Host smart-d0d6acb6-f5c5-470a-b617-20d7df295299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18355
14026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1835514026
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2826385005
Short name T561
Test name
Test status
Simulation time 302708392 ps
CPU time 1.03 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:08:48 AM PDT 24
Peak memory 206200 kb
Host smart-b92d968f-fdbb-4990-a8d6-f65fbec84a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28263
85005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2826385005
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.188760347
Short name T2369
Test name
Test status
Simulation time 1151822261 ps
CPU time 2.75 seconds
Started Jul 02 09:08:38 AM PDT 24
Finished Jul 02 09:08:42 AM PDT 24
Peak memory 206472 kb
Host smart-5ca2e350-e844-4132-986c-8dee624cc180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18876
0347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.188760347
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.974572117
Short name T789
Test name
Test status
Simulation time 11461454822 ps
CPU time 21.14 seconds
Started Jul 02 09:08:45 AM PDT 24
Finished Jul 02 09:09:09 AM PDT 24
Peak memory 206560 kb
Host smart-c66291eb-565c-45dc-9f35-b2d3059fe4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97457
2117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.974572117
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2847336994
Short name T1333
Test name
Test status
Simulation time 433611821 ps
CPU time 1.4 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:09:00 AM PDT 24
Peak memory 206148 kb
Host smart-b3ea13e4-ea15-4490-b83c-51a276f319b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28473
36994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2847336994
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3327193368
Short name T803
Test name
Test status
Simulation time 139127156 ps
CPU time 0.79 seconds
Started Jul 02 09:08:46 AM PDT 24
Finished Jul 02 09:08:48 AM PDT 24
Peak memory 206180 kb
Host smart-4f253655-b36e-4ebd-b02c-95d855198200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33271
93368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3327193368
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1367809543
Short name T1188
Test name
Test status
Simulation time 62307089 ps
CPU time 0.69 seconds
Started Jul 02 09:08:45 AM PDT 24
Finished Jul 02 09:08:48 AM PDT 24
Peak memory 206204 kb
Host smart-96aea4a1-db62-49bf-a0cf-7a68ecb5c34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13678
09543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1367809543
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.3787901560
Short name T1862
Test name
Test status
Simulation time 1052838297 ps
CPU time 2.48 seconds
Started Jul 02 09:08:46 AM PDT 24
Finished Jul 02 09:08:50 AM PDT 24
Peak memory 206384 kb
Host smart-b3e1673f-e085-4a26-a848-73b432c185e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37879
01560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3787901560
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.722549030
Short name T2610
Test name
Test status
Simulation time 239717186 ps
CPU time 1.63 seconds
Started Jul 02 09:08:45 AM PDT 24
Finished Jul 02 09:08:49 AM PDT 24
Peak memory 206400 kb
Host smart-246c2791-278c-449a-84b0-d334b27fae89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72254
9030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.722549030
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1512347517
Short name T2193
Test name
Test status
Simulation time 190890802 ps
CPU time 0.86 seconds
Started Jul 02 09:08:43 AM PDT 24
Finished Jul 02 09:08:45 AM PDT 24
Peak memory 206184 kb
Host smart-93e2f611-ab63-40dc-9ef5-16a419aa816d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15123
47517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1512347517
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.4170802777
Short name T1224
Test name
Test status
Simulation time 166533884 ps
CPU time 0.79 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:08:47 AM PDT 24
Peak memory 206208 kb
Host smart-5117e5b6-ae37-4c5e-bd3d-c6c573eb2740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41708
02777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.4170802777
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3735844300
Short name T1200
Test name
Test status
Simulation time 201027086 ps
CPU time 0.91 seconds
Started Jul 02 09:08:47 AM PDT 24
Finished Jul 02 09:08:50 AM PDT 24
Peak memory 206220 kb
Host smart-220cd0a5-53db-4482-b846-713f75970238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37358
44300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3735844300
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3275001441
Short name T1924
Test name
Test status
Simulation time 222569465 ps
CPU time 0.86 seconds
Started Jul 02 09:08:45 AM PDT 24
Finished Jul 02 09:08:48 AM PDT 24
Peak memory 206176 kb
Host smart-0749b907-7408-4ae0-8a9f-5aab46b32aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32750
01441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3275001441
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.3723785030
Short name T2599
Test name
Test status
Simulation time 23299985609 ps
CPU time 23.77 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:09:10 AM PDT 24
Peak memory 206264 kb
Host smart-48373988-9de8-4a18-9ccf-b60fd4d39582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37237
85030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.3723785030
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2315940536
Short name T806
Test name
Test status
Simulation time 3288903335 ps
CPU time 4.17 seconds
Started Jul 02 09:08:48 AM PDT 24
Finished Jul 02 09:08:53 AM PDT 24
Peak memory 206400 kb
Host smart-9670b06d-1306-4833-ac8c-47aa6dabeb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23159
40536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2315940536
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.2731591364
Short name T610
Test name
Test status
Simulation time 7413949777 ps
CPU time 57.02 seconds
Started Jul 02 09:08:43 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206516 kb
Host smart-7040ac77-ede7-403f-bb03-600041442f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
91364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.2731591364
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2518474430
Short name T1483
Test name
Test status
Simulation time 3277668432 ps
CPU time 29.8 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:09:15 AM PDT 24
Peak memory 206444 kb
Host smart-34578a5e-5a17-4740-81b2-0158416540ff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2518474430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2518474430
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1813997697
Short name T1604
Test name
Test status
Simulation time 252348238 ps
CPU time 0.96 seconds
Started Jul 02 09:08:46 AM PDT 24
Finished Jul 02 09:08:49 AM PDT 24
Peak memory 206100 kb
Host smart-6c736bc8-0dac-41ee-9456-0848ed77fc45
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1813997697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1813997697
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1365581397
Short name T2617
Test name
Test status
Simulation time 191202013 ps
CPU time 0.87 seconds
Started Jul 02 09:08:48 AM PDT 24
Finished Jul 02 09:08:50 AM PDT 24
Peak memory 206200 kb
Host smart-85f37347-e0e0-4746-b660-797b916c8a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13655
81397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1365581397
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.4045783647
Short name T2570
Test name
Test status
Simulation time 5024362532 ps
CPU time 139.81 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:11:05 AM PDT 24
Peak memory 206484 kb
Host smart-e5d23ab6-a6fd-4b88-ae9d-c3175ec8cc85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40457
83647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.4045783647
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.4294404302
Short name T1983
Test name
Test status
Simulation time 5851224091 ps
CPU time 168.37 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:11:34 AM PDT 24
Peak memory 206420 kb
Host smart-b1ca24d4-56ee-4e60-bac2-2a896e89f1a1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4294404302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.4294404302
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.591164197
Short name T331
Test name
Test status
Simulation time 157472540 ps
CPU time 0.88 seconds
Started Jul 02 09:08:43 AM PDT 24
Finished Jul 02 09:08:46 AM PDT 24
Peak memory 206100 kb
Host smart-0cf3b391-ce0c-4ea0-8413-7d47827d799e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=591164197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.591164197
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2260484261
Short name T565
Test name
Test status
Simulation time 242899650 ps
CPU time 0.8 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:08:47 AM PDT 24
Peak memory 206188 kb
Host smart-e14cd652-bea8-49bd-bdd4-f581a1e09b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22604
84261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2260484261
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2651156019
Short name T2378
Test name
Test status
Simulation time 262310446 ps
CPU time 0.92 seconds
Started Jul 02 09:08:47 AM PDT 24
Finished Jul 02 09:08:50 AM PDT 24
Peak memory 206220 kb
Host smart-f72b941f-5d0c-4479-829b-7ae371914776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26511
56019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2651156019
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2054474022
Short name T2214
Test name
Test status
Simulation time 168224418 ps
CPU time 0.81 seconds
Started Jul 02 09:08:44 AM PDT 24
Finished Jul 02 09:08:47 AM PDT 24
Peak memory 206208 kb
Host smart-665f9aea-5735-43e1-8c59-f33ae312c7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20544
74022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2054474022
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1028987181
Short name T574
Test name
Test status
Simulation time 168824358 ps
CPU time 0.83 seconds
Started Jul 02 09:08:42 AM PDT 24
Finished Jul 02 09:08:44 AM PDT 24
Peak memory 206220 kb
Host smart-485818a3-f24e-40af-a15e-c1e1476584f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10289
87181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1028987181
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1336744317
Short name T2497
Test name
Test status
Simulation time 180073401 ps
CPU time 0.91 seconds
Started Jul 02 09:08:43 AM PDT 24
Finished Jul 02 09:08:46 AM PDT 24
Peak memory 206204 kb
Host smart-4f03960a-1187-49b7-93c6-cdd3c2d6dd39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13367
44317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1336744317
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2145410398
Short name T1917
Test name
Test status
Simulation time 151979585 ps
CPU time 0.9 seconds
Started Jul 02 09:08:50 AM PDT 24
Finished Jul 02 09:08:52 AM PDT 24
Peak memory 206128 kb
Host smart-06028a17-b430-4bfe-aff9-a436c7ce23a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21454
10398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2145410398
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.563385847
Short name T2540
Test name
Test status
Simulation time 210656572 ps
CPU time 1.15 seconds
Started Jul 02 09:08:51 AM PDT 24
Finished Jul 02 09:08:53 AM PDT 24
Peak memory 206108 kb
Host smart-9081373f-f4a5-4ea0-9903-34e3fbae0353
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=563385847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.563385847
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.4127325700
Short name T2635
Test name
Test status
Simulation time 142261798 ps
CPU time 0.81 seconds
Started Jul 02 09:08:54 AM PDT 24
Finished Jul 02 09:08:56 AM PDT 24
Peak memory 206144 kb
Host smart-56817aa7-1960-45f4-9733-9b684d9bcaaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41273
25700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.4127325700
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.561166036
Short name T2009
Test name
Test status
Simulation time 36089381 ps
CPU time 0.67 seconds
Started Jul 02 09:08:54 AM PDT 24
Finished Jul 02 09:08:55 AM PDT 24
Peak memory 206156 kb
Host smart-747b1bdf-740a-4a05-a577-4cc526dd1634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56116
6036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.561166036
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3458463050
Short name T1116
Test name
Test status
Simulation time 9696511561 ps
CPU time 20.23 seconds
Started Jul 02 09:08:50 AM PDT 24
Finished Jul 02 09:09:11 AM PDT 24
Peak memory 206456 kb
Host smart-0c776ee3-6580-41d0-bdd2-f13eef70e6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34584
63050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3458463050
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1202977053
Short name T822
Test name
Test status
Simulation time 209165307 ps
CPU time 0.84 seconds
Started Jul 02 09:08:48 AM PDT 24
Finished Jul 02 09:08:50 AM PDT 24
Peak memory 206196 kb
Host smart-05a7cda6-e513-4bbe-8d9d-e19c1f6b12ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12029
77053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1202977053
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3785269350
Short name T808
Test name
Test status
Simulation time 237627260 ps
CPU time 0.91 seconds
Started Jul 02 09:08:50 AM PDT 24
Finished Jul 02 09:08:52 AM PDT 24
Peak memory 206196 kb
Host smart-8f98a652-4886-4b21-937f-42a6fec41a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37852
69350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3785269350
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2159388791
Short name T1790
Test name
Test status
Simulation time 182856973 ps
CPU time 0.91 seconds
Started Jul 02 09:08:49 AM PDT 24
Finished Jul 02 09:08:51 AM PDT 24
Peak memory 206216 kb
Host smart-e48a04b5-6240-4fcb-b5b5-ccad7ef81676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21593
88791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2159388791
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1161454185
Short name T1840
Test name
Test status
Simulation time 155236867 ps
CPU time 0.85 seconds
Started Jul 02 09:08:49 AM PDT 24
Finished Jul 02 09:08:51 AM PDT 24
Peak memory 206356 kb
Host smart-e48f38ee-9705-457a-baab-36ea4c0c1e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11614
54185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1161454185
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2609950123
Short name T2112
Test name
Test status
Simulation time 204407139 ps
CPU time 0.86 seconds
Started Jul 02 09:08:48 AM PDT 24
Finished Jul 02 09:08:50 AM PDT 24
Peak memory 206176 kb
Host smart-8a953032-0b37-47f5-836c-4717d2e020a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26099
50123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2609950123
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2567111101
Short name T2197
Test name
Test status
Simulation time 221774286 ps
CPU time 1.03 seconds
Started Jul 02 09:08:49 AM PDT 24
Finished Jul 02 09:08:51 AM PDT 24
Peak memory 206120 kb
Host smart-345fc184-ae1e-4045-9731-3238029b895f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25671
11101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2567111101
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.4176441997
Short name T1294
Test name
Test status
Simulation time 156429469 ps
CPU time 0.81 seconds
Started Jul 02 09:08:48 AM PDT 24
Finished Jul 02 09:08:50 AM PDT 24
Peak memory 206180 kb
Host smart-6c6aece4-1a46-407f-8f7e-251e5b07a8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41764
41997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.4176441997
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1524324630
Short name T53
Test name
Test status
Simulation time 181814344 ps
CPU time 0.86 seconds
Started Jul 02 09:08:47 AM PDT 24
Finished Jul 02 09:08:49 AM PDT 24
Peak memory 206208 kb
Host smart-c35491f7-7f5c-4fa2-b36d-cc2ccf62c0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15243
24630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1524324630
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.938475850
Short name T2577
Test name
Test status
Simulation time 5214386348 ps
CPU time 39.44 seconds
Started Jul 02 09:08:49 AM PDT 24
Finished Jul 02 09:09:30 AM PDT 24
Peak memory 206656 kb
Host smart-44763be9-87c8-4c64-9484-b7d5beed97a9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=938475850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.938475850
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3085509079
Short name T2665
Test name
Test status
Simulation time 195936382 ps
CPU time 0.87 seconds
Started Jul 02 09:08:51 AM PDT 24
Finished Jul 02 09:08:53 AM PDT 24
Peak memory 206212 kb
Host smart-2f5b61bf-085b-499f-9238-a61c6842ff7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30855
09079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3085509079
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.454327965
Short name T2147
Test name
Test status
Simulation time 175056440 ps
CPU time 0.85 seconds
Started Jul 02 09:08:52 AM PDT 24
Finished Jul 02 09:08:54 AM PDT 24
Peak memory 206204 kb
Host smart-b41dfe52-af76-43b2-85c6-c331955571a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45432
7965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.454327965
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.1574494235
Short name T2607
Test name
Test status
Simulation time 1148608436 ps
CPU time 2.64 seconds
Started Jul 02 09:08:54 AM PDT 24
Finished Jul 02 09:08:58 AM PDT 24
Peak memory 206392 kb
Host smart-15b3547c-04bb-422f-9a6e-66df6768bcfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15744
94235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.1574494235
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1811325123
Short name T1619
Test name
Test status
Simulation time 3330839771 ps
CPU time 89.71 seconds
Started Jul 02 09:08:48 AM PDT 24
Finished Jul 02 09:10:19 AM PDT 24
Peak memory 206508 kb
Host smart-d31bf4d5-092e-439c-b7f7-ccf663077a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18113
25123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1811325123
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.3970863319
Short name T1753
Test name
Test status
Simulation time 58229703 ps
CPU time 0.71 seconds
Started Jul 02 09:09:04 AM PDT 24
Finished Jul 02 09:09:09 AM PDT 24
Peak memory 206116 kb
Host smart-a2b01cfb-5761-4929-9a36-46204bfa347e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3970863319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.3970863319
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2255326785
Short name T1326
Test name
Test status
Simulation time 3413368411 ps
CPU time 4.42 seconds
Started Jul 02 09:08:48 AM PDT 24
Finished Jul 02 09:08:54 AM PDT 24
Peak memory 206496 kb
Host smart-96f1cbc0-d6ef-40b5-ad2d-d4e52a46fce4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2255326785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.2255326785
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.3898991301
Short name T2020
Test name
Test status
Simulation time 13393584073 ps
CPU time 13.96 seconds
Started Jul 02 09:08:54 AM PDT 24
Finished Jul 02 09:09:09 AM PDT 24
Peak memory 206368 kb
Host smart-db6579fd-e19d-4315-8bb8-16dc17050571
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3898991301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.3898991301
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3079009759
Short name T585
Test name
Test status
Simulation time 23499302578 ps
CPU time 26.87 seconds
Started Jul 02 09:08:49 AM PDT 24
Finished Jul 02 09:09:17 AM PDT 24
Peak memory 206348 kb
Host smart-ab2d8027-bb8c-43bb-a8e2-091e0a531e12
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3079009759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3079009759
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.905323572
Short name T1509
Test name
Test status
Simulation time 174496005 ps
CPU time 0.8 seconds
Started Jul 02 09:08:55 AM PDT 24
Finished Jul 02 09:08:57 AM PDT 24
Peak memory 206224 kb
Host smart-295af2c5-be9f-4335-86c4-e6cd91e1d124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90532
3572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.905323572
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.4090294640
Short name T1763
Test name
Test status
Simulation time 159517370 ps
CPU time 0.78 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:08:59 AM PDT 24
Peak memory 206184 kb
Host smart-48d7aa6e-c8bf-4ee9-8d29-9c5e78262f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40902
94640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.4090294640
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.1373496730
Short name T688
Test name
Test status
Simulation time 553999938 ps
CPU time 1.58 seconds
Started Jul 02 09:08:55 AM PDT 24
Finished Jul 02 09:08:58 AM PDT 24
Peak memory 206348 kb
Host smart-7854dde3-84c6-44a0-9e05-bb2801c841b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13734
96730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.1373496730
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_device_address.327617987
Short name T1603
Test name
Test status
Simulation time 22749256355 ps
CPU time 40.15 seconds
Started Jul 02 09:08:56 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206516 kb
Host smart-9057b022-ae0f-4a8a-ab86-6ffffe2f08b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32761
7987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.327617987
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.2040898229
Short name T1215
Test name
Test status
Simulation time 477920778 ps
CPU time 1.33 seconds
Started Jul 02 09:08:55 AM PDT 24
Finished Jul 02 09:08:58 AM PDT 24
Peak memory 206156 kb
Host smart-92f14f13-a1c5-4a05-8925-5c283dcd05b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20408
98229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.2040898229
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.193474417
Short name T1253
Test name
Test status
Simulation time 133110718 ps
CPU time 0.76 seconds
Started Jul 02 09:08:59 AM PDT 24
Finished Jul 02 09:09:02 AM PDT 24
Peak memory 206204 kb
Host smart-10444af8-6aec-4629-bb37-a9711fa5ec08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19347
4417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.193474417
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2127507858
Short name T2554
Test name
Test status
Simulation time 108031826 ps
CPU time 0.77 seconds
Started Jul 02 09:08:55 AM PDT 24
Finished Jul 02 09:08:57 AM PDT 24
Peak memory 206212 kb
Host smart-f1c70b82-9732-4605-85e1-7d7bb5a42674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21275
07858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2127507858
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1779525694
Short name T2639
Test name
Test status
Simulation time 943223025 ps
CPU time 2.13 seconds
Started Jul 02 09:08:55 AM PDT 24
Finished Jul 02 09:08:59 AM PDT 24
Peak memory 206396 kb
Host smart-750a1461-0eb5-426d-af9a-595aa4c11d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17795
25694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1779525694
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1638962714
Short name T1508
Test name
Test status
Simulation time 252828757 ps
CPU time 1.42 seconds
Started Jul 02 09:08:56 AM PDT 24
Finished Jul 02 09:08:59 AM PDT 24
Peak memory 206388 kb
Host smart-e11a94c8-8fa6-4bd5-90f1-9c733f319055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16389
62714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1638962714
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2095972114
Short name T1341
Test name
Test status
Simulation time 166806666 ps
CPU time 0.83 seconds
Started Jul 02 09:08:51 AM PDT 24
Finished Jul 02 09:08:53 AM PDT 24
Peak memory 206184 kb
Host smart-dd4ff3c9-bfd4-405d-adaa-d47c52125a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
72114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2095972114
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3658464272
Short name T555
Test name
Test status
Simulation time 145801527 ps
CPU time 0.8 seconds
Started Jul 02 09:08:51 AM PDT 24
Finished Jul 02 09:08:53 AM PDT 24
Peak memory 206164 kb
Host smart-f0396abb-963d-4836-8375-b2d297a0d6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36584
64272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3658464272
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1224686141
Short name T1346
Test name
Test status
Simulation time 226264212 ps
CPU time 0.87 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:09:00 AM PDT 24
Peak memory 206176 kb
Host smart-c14e877a-ac5c-43e8-ae07-c5c21017fc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12246
86141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1224686141
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.3243362381
Short name T2265
Test name
Test status
Simulation time 8664755283 ps
CPU time 86.44 seconds
Started Jul 02 09:08:52 AM PDT 24
Finished Jul 02 09:10:19 AM PDT 24
Peak memory 206436 kb
Host smart-3be120a5-2c67-4bc2-a705-623975bdbd99
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3243362381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.3243362381
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3199128625
Short name T1982
Test name
Test status
Simulation time 180793177 ps
CPU time 0.81 seconds
Started Jul 02 09:08:52 AM PDT 24
Finished Jul 02 09:08:54 AM PDT 24
Peak memory 206124 kb
Host smart-608f10c3-120f-4c0a-9755-fc67d913eee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31991
28625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3199128625
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.319740365
Short name T1517
Test name
Test status
Simulation time 23315365368 ps
CPU time 21.27 seconds
Started Jul 02 09:08:58 AM PDT 24
Finished Jul 02 09:09:22 AM PDT 24
Peak memory 206220 kb
Host smart-a098cbfc-76e5-4110-892a-1a456f80fa30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31974
0365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.319740365
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.751975834
Short name T2626
Test name
Test status
Simulation time 3280311505 ps
CPU time 4.12 seconds
Started Jul 02 09:08:55 AM PDT 24
Finished Jul 02 09:09:01 AM PDT 24
Peak memory 206252 kb
Host smart-a7fd672f-b21e-4634-9c85-4c85c62369f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75197
5834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.751975834
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.291678442
Short name T152
Test name
Test status
Simulation time 12172099493 ps
CPU time 94.21 seconds
Started Jul 02 09:08:53 AM PDT 24
Finished Jul 02 09:10:28 AM PDT 24
Peak memory 206540 kb
Host smart-f81fe475-388a-4638-bee2-99373a03662d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29167
8442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.291678442
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1808608988
Short name T943
Test name
Test status
Simulation time 3475218174 ps
CPU time 33.17 seconds
Started Jul 02 09:08:52 AM PDT 24
Finished Jul 02 09:09:27 AM PDT 24
Peak memory 206500 kb
Host smart-cd66a027-3852-44cc-a0bf-da3cd53acad5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1808608988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1808608988
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3980319376
Short name T2352
Test name
Test status
Simulation time 236083615 ps
CPU time 0.99 seconds
Started Jul 02 09:08:58 AM PDT 24
Finished Jul 02 09:09:01 AM PDT 24
Peak memory 206192 kb
Host smart-de4eaf7a-b540-40e4-9d38-4bdedeb97bb7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3980319376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3980319376
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1105425202
Short name T1644
Test name
Test status
Simulation time 202718488 ps
CPU time 0.92 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:09:00 AM PDT 24
Peak memory 206200 kb
Host smart-16759584-8eb2-4bcc-911e-c30ee4b03f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11054
25202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1105425202
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.184974342
Short name T1580
Test name
Test status
Simulation time 5372879944 ps
CPU time 159.61 seconds
Started Jul 02 09:08:56 AM PDT 24
Finished Jul 02 09:11:38 AM PDT 24
Peak memory 206476 kb
Host smart-35b64de9-b908-4445-a731-85724278c62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18497
4342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.184974342
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.2115653429
Short name T2325
Test name
Test status
Simulation time 6871850898 ps
CPU time 195.34 seconds
Started Jul 02 09:08:58 AM PDT 24
Finished Jul 02 09:12:16 AM PDT 24
Peak memory 206460 kb
Host smart-1318a897-c97f-494c-93a0-be5110b6c9cf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2115653429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.2115653429
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.1985035597
Short name T1090
Test name
Test status
Simulation time 152863559 ps
CPU time 0.82 seconds
Started Jul 02 09:08:56 AM PDT 24
Finished Jul 02 09:08:59 AM PDT 24
Peak memory 206192 kb
Host smart-763e27b3-f5f6-45b6-bea2-6deba97f29df
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1985035597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.1985035597
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.796727435
Short name T2181
Test name
Test status
Simulation time 165747819 ps
CPU time 0.82 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:09:00 AM PDT 24
Peak memory 206188 kb
Host smart-620bed7f-56bf-44b5-9ab7-c978bd78cf53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79672
7435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.796727435
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2512924536
Short name T765
Test name
Test status
Simulation time 222442266 ps
CPU time 0.85 seconds
Started Jul 02 09:09:05 AM PDT 24
Finished Jul 02 09:09:09 AM PDT 24
Peak memory 206076 kb
Host smart-d2f29817-2541-4274-812b-f7f3bfd131c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25129
24536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2512924536
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1621848680
Short name T396
Test name
Test status
Simulation time 157545871 ps
CPU time 0.75 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:09:00 AM PDT 24
Peak memory 206176 kb
Host smart-df269915-4955-4ffa-9344-4b7a15ad6379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16218
48680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1621848680
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.681138315
Short name T527
Test name
Test status
Simulation time 174597732 ps
CPU time 0.83 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:09:00 AM PDT 24
Peak memory 206212 kb
Host smart-5de43f82-d7b4-4433-836f-8f1f3f2993b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68113
8315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.681138315
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1407315725
Short name T2234
Test name
Test status
Simulation time 163214036 ps
CPU time 0.79 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:06 AM PDT 24
Peak memory 206168 kb
Host smart-492a03cb-bf8f-41dc-b2d1-d24371336e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073
15725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1407315725
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.3056817023
Short name T858
Test name
Test status
Simulation time 255034211 ps
CPU time 1 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:08:59 AM PDT 24
Peak memory 206136 kb
Host smart-27496c0c-b08a-42f9-9730-f59a88172392
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3056817023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.3056817023
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3791456838
Short name T1875
Test name
Test status
Simulation time 223646229 ps
CPU time 0.84 seconds
Started Jul 02 09:09:02 AM PDT 24
Finished Jul 02 09:09:05 AM PDT 24
Peak memory 206172 kb
Host smart-c0df0b5b-6c0c-4c01-90fe-020bc77c52e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37914
56838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3791456838
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.4148971296
Short name T1235
Test name
Test status
Simulation time 30458343 ps
CPU time 0.63 seconds
Started Jul 02 09:09:02 AM PDT 24
Finished Jul 02 09:09:05 AM PDT 24
Peak memory 206164 kb
Host smart-a7db3caf-d29f-4092-8b1e-c608b878a0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41489
71296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.4148971296
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.628618220
Short name T2148
Test name
Test status
Simulation time 11229523285 ps
CPU time 27.75 seconds
Started Jul 02 09:08:57 AM PDT 24
Finished Jul 02 09:09:27 AM PDT 24
Peak memory 206560 kb
Host smart-3243d830-0932-4dd4-9696-c51ee45eef84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62861
8220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.628618220
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.691678135
Short name T1458
Test name
Test status
Simulation time 220488593 ps
CPU time 1 seconds
Started Jul 02 09:08:56 AM PDT 24
Finished Jul 02 09:08:59 AM PDT 24
Peak memory 206184 kb
Host smart-52b32b30-46c0-4aad-a3ca-28b73abce3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69167
8135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.691678135
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1222464670
Short name T2209
Test name
Test status
Simulation time 260949308 ps
CPU time 0.89 seconds
Started Jul 02 09:09:02 AM PDT 24
Finished Jul 02 09:09:05 AM PDT 24
Peak memory 206168 kb
Host smart-efeac498-4f69-4e5e-93b2-ca64ac4759e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12224
64670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1222464670
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.1881228125
Short name T682
Test name
Test status
Simulation time 271935438 ps
CPU time 1 seconds
Started Jul 02 09:08:59 AM PDT 24
Finished Jul 02 09:09:02 AM PDT 24
Peak memory 206128 kb
Host smart-1714183c-b06c-430b-afb2-baae7efe371e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18812
28125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.1881228125
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.324340570
Short name T376
Test name
Test status
Simulation time 216033799 ps
CPU time 0.89 seconds
Started Jul 02 09:08:58 AM PDT 24
Finished Jul 02 09:09:01 AM PDT 24
Peak memory 206144 kb
Host smart-47b9e8f8-21b7-4cff-86c6-10794127def4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32434
0570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.324340570
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3381972015
Short name T2129
Test name
Test status
Simulation time 149231333 ps
CPU time 0.8 seconds
Started Jul 02 09:09:00 AM PDT 24
Finished Jul 02 09:09:02 AM PDT 24
Peak memory 206220 kb
Host smart-a555793d-edda-4fcf-be4d-6dc55596951e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33819
72015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3381972015
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1661441390
Short name T614
Test name
Test status
Simulation time 160082514 ps
CPU time 0.86 seconds
Started Jul 02 09:08:56 AM PDT 24
Finished Jul 02 09:08:59 AM PDT 24
Peak memory 206388 kb
Host smart-2a78c68b-45c4-469e-810f-1b8f8b0da0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16614
41390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1661441390
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2498714407
Short name T1231
Test name
Test status
Simulation time 172800192 ps
CPU time 0.77 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:06 AM PDT 24
Peak memory 206172 kb
Host smart-0b60d65f-e2c0-4f34-a282-10762a7247ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24987
14407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2498714407
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1993848199
Short name T672
Test name
Test status
Simulation time 237015058 ps
CPU time 0.92 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:07 AM PDT 24
Peak memory 206076 kb
Host smart-239b733c-0d74-4d7e-a90b-b4c54c6de7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19938
48199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1993848199
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.858134799
Short name T1072
Test name
Test status
Simulation time 3532049968 ps
CPU time 26.84 seconds
Started Jul 02 09:08:58 AM PDT 24
Finished Jul 02 09:09:27 AM PDT 24
Peak memory 206460 kb
Host smart-40748155-52ed-441d-bc20-b91cf83c1398
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=858134799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.858134799
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.839088421
Short name T1637
Test name
Test status
Simulation time 181257445 ps
CPU time 0.87 seconds
Started Jul 02 09:08:58 AM PDT 24
Finished Jul 02 09:09:01 AM PDT 24
Peak memory 206128 kb
Host smart-6ddaa853-5ec5-41b0-a69a-63c795e7d5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83908
8421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.839088421
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2439675701
Short name T843
Test name
Test status
Simulation time 175073969 ps
CPU time 0.84 seconds
Started Jul 02 09:08:59 AM PDT 24
Finished Jul 02 09:09:02 AM PDT 24
Peak memory 206188 kb
Host smart-e8fc13b3-7256-4764-9f3e-1ec0694049a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24396
75701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2439675701
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.1532695383
Short name T547
Test name
Test status
Simulation time 826925276 ps
CPU time 1.79 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:08 AM PDT 24
Peak memory 206324 kb
Host smart-ba837668-db7b-449a-94ba-b9d5485b6b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15326
95383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.1532695383
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.401222706
Short name T2466
Test name
Test status
Simulation time 6480474504 ps
CPU time 189.72 seconds
Started Jul 02 09:08:56 AM PDT 24
Finished Jul 02 09:12:07 AM PDT 24
Peak memory 206480 kb
Host smart-01dc816d-fc58-4d3d-b91c-9c1ae6de2ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40122
2706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.401222706
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.3533950720
Short name T204
Test name
Test status
Simulation time 43470320 ps
CPU time 0.69 seconds
Started Jul 02 09:09:04 AM PDT 24
Finished Jul 02 09:09:07 AM PDT 24
Peak memory 206252 kb
Host smart-6ef393f5-2ffe-4dbd-a238-be50d15ed43e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3533950720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.3533950720
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1092906539
Short name T207
Test name
Test status
Simulation time 3668986675 ps
CPU time 4.78 seconds
Started Jul 02 09:08:59 AM PDT 24
Finished Jul 02 09:09:06 AM PDT 24
Peak memory 206224 kb
Host smart-abcb5167-53db-4c9a-87a6-131688f07ef9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1092906539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1092906539
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3590396232
Short name T1835
Test name
Test status
Simulation time 13364970564 ps
CPU time 12.37 seconds
Started Jul 02 09:08:58 AM PDT 24
Finished Jul 02 09:09:13 AM PDT 24
Peak memory 206236 kb
Host smart-8ee942c7-fa52-47c5-804e-73bdc95c1b7c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3590396232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3590396232
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2794533293
Short name T1699
Test name
Test status
Simulation time 23451412976 ps
CPU time 25.52 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:32 AM PDT 24
Peak memory 206500 kb
Host smart-544c7227-fd34-49de-aaf2-ab611c81101f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2794533293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.2794533293
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3811653777
Short name T1808
Test name
Test status
Simulation time 169152507 ps
CPU time 0.81 seconds
Started Jul 02 09:09:00 AM PDT 24
Finished Jul 02 09:09:02 AM PDT 24
Peak memory 206208 kb
Host smart-870a3415-b2ca-47a8-9205-10bc3da372db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38116
53777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3811653777
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.4251900655
Short name T2385
Test name
Test status
Simulation time 158675798 ps
CPU time 0.79 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:06 AM PDT 24
Peak memory 206196 kb
Host smart-875c0090-2f7a-4b56-8b62-19c3071b1202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42519
00655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.4251900655
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.3679154446
Short name T194
Test name
Test status
Simulation time 348117646 ps
CPU time 1.2 seconds
Started Jul 02 09:09:01 AM PDT 24
Finished Jul 02 09:09:04 AM PDT 24
Peak memory 206124 kb
Host smart-07bad4b4-5c6c-47c0-a467-d5b42a650d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36791
54446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3679154446
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3605036230
Short name T1767
Test name
Test status
Simulation time 435643238 ps
CPU time 1.34 seconds
Started Jul 02 09:08:59 AM PDT 24
Finished Jul 02 09:09:02 AM PDT 24
Peak memory 206204 kb
Host smart-fd92f16e-80b5-48a1-91e2-c17896f5113c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36050
36230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3605036230
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.865919912
Short name T2609
Test name
Test status
Simulation time 17799277546 ps
CPU time 32.97 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:38 AM PDT 24
Peak memory 206424 kb
Host smart-0e309d84-9259-4a4b-9b97-b5cadf8e7a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86591
9912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.865919912
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.4144973834
Short name T2467
Test name
Test status
Simulation time 382268829 ps
CPU time 1.23 seconds
Started Jul 02 09:09:07 AM PDT 24
Finished Jul 02 09:09:11 AM PDT 24
Peak memory 206120 kb
Host smart-3f204c6e-4705-4c82-8a86-bd6fd93b16a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41449
73834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.4144973834
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1005809916
Short name T748
Test name
Test status
Simulation time 165412331 ps
CPU time 0.75 seconds
Started Jul 02 09:09:01 AM PDT 24
Finished Jul 02 09:09:04 AM PDT 24
Peak memory 206140 kb
Host smart-864ec5a7-2611-4535-a654-a5813404aea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10058
09916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1005809916
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3184456959
Short name T344
Test name
Test status
Simulation time 58514312 ps
CPU time 0.67 seconds
Started Jul 02 09:09:02 AM PDT 24
Finished Jul 02 09:09:04 AM PDT 24
Peak memory 206336 kb
Host smart-c9d3665a-5e9b-4a49-bbd7-9573ca7ee606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31844
56959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3184456959
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.4233233281
Short name T1054
Test name
Test status
Simulation time 926741523 ps
CPU time 2.38 seconds
Started Jul 02 09:09:01 AM PDT 24
Finished Jul 02 09:09:06 AM PDT 24
Peak memory 206376 kb
Host smart-35592eb0-bda0-41c5-9015-05b3be1c68b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42332
33281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.4233233281
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1276186673
Short name T540
Test name
Test status
Simulation time 319999176 ps
CPU time 1.65 seconds
Started Jul 02 09:09:02 AM PDT 24
Finished Jul 02 09:09:07 AM PDT 24
Peak memory 206408 kb
Host smart-204fc43d-a28d-4f66-b206-dc7c55538593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12761
86673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1276186673
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3645216587
Short name T1985
Test name
Test status
Simulation time 170589494 ps
CPU time 0.93 seconds
Started Jul 02 09:09:01 AM PDT 24
Finished Jul 02 09:09:04 AM PDT 24
Peak memory 206184 kb
Host smart-50804d85-da43-4b61-9616-80fce9d76fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36452
16587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3645216587
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.3312663969
Short name T779
Test name
Test status
Simulation time 144693099 ps
CPU time 0.76 seconds
Started Jul 02 09:09:00 AM PDT 24
Finished Jul 02 09:09:02 AM PDT 24
Peak memory 206116 kb
Host smart-5e4910a8-53b3-4cdf-ab2c-acba6c04b3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33126
63969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3312663969
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.842168702
Short name T338
Test name
Test status
Simulation time 199085635 ps
CPU time 0.86 seconds
Started Jul 02 09:09:10 AM PDT 24
Finished Jul 02 09:09:13 AM PDT 24
Peak memory 206192 kb
Host smart-9fe928a3-e1e1-4794-86f9-02214d862945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84216
8702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.842168702
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2356635311
Short name T1873
Test name
Test status
Simulation time 163206534 ps
CPU time 0.86 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:06 AM PDT 24
Peak memory 206164 kb
Host smart-ddd6a240-085f-45ce-aab7-0c8408bf58b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23566
35311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2356635311
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3930798968
Short name T2057
Test name
Test status
Simulation time 23295193141 ps
CPU time 22.17 seconds
Started Jul 02 09:09:00 AM PDT 24
Finished Jul 02 09:09:24 AM PDT 24
Peak memory 206244 kb
Host smart-79deab0d-a961-4b27-9c60-47379fb186aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39307
98968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3930798968
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.538395398
Short name T2691
Test name
Test status
Simulation time 3269105904 ps
CPU time 4.64 seconds
Started Jul 02 09:09:01 AM PDT 24
Finished Jul 02 09:09:08 AM PDT 24
Peak memory 206268 kb
Host smart-9fa2414f-b4b2-44ce-8395-cecf1f185e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53839
5398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.538395398
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.808368346
Short name T1066
Test name
Test status
Simulation time 8442712706 ps
CPU time 60.33 seconds
Started Jul 02 09:09:01 AM PDT 24
Finished Jul 02 09:10:03 AM PDT 24
Peak memory 206540 kb
Host smart-222c0a8c-9cf2-4119-af72-0a9b86a054e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80836
8346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.808368346
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.3286474566
Short name T1500
Test name
Test status
Simulation time 3896577493 ps
CPU time 105.97 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:10:51 AM PDT 24
Peak memory 206484 kb
Host smart-71f7d50d-7726-4abb-97c7-656f431d4366
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3286474566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.3286474566
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3086442109
Short name T2257
Test name
Test status
Simulation time 243816249 ps
CPU time 0.93 seconds
Started Jul 02 09:09:09 AM PDT 24
Finished Jul 02 09:09:12 AM PDT 24
Peak memory 206108 kb
Host smart-042ef71b-d7b8-4275-adfc-3343d38f0448
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3086442109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3086442109
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3925176198
Short name T1855
Test name
Test status
Simulation time 209906088 ps
CPU time 0.87 seconds
Started Jul 02 09:08:59 AM PDT 24
Finished Jul 02 09:09:02 AM PDT 24
Peak memory 206224 kb
Host smart-be0d974d-81e5-46c1-a3a8-22e549f49f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39251
76198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3925176198
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.740681073
Short name T1011
Test name
Test status
Simulation time 4550847924 ps
CPU time 35.41 seconds
Started Jul 02 09:09:02 AM PDT 24
Finished Jul 02 09:09:39 AM PDT 24
Peak memory 206532 kb
Host smart-683a8712-c26c-439f-aa9a-01902cf67283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74068
1073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.740681073
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2518883173
Short name T1549
Test name
Test status
Simulation time 3536047674 ps
CPU time 104.18 seconds
Started Jul 02 09:09:00 AM PDT 24
Finished Jul 02 09:10:47 AM PDT 24
Peak memory 206436 kb
Host smart-e704a14d-43bf-4976-aaed-42865bca0035
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2518883173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2518883173
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1630176691
Short name T2270
Test name
Test status
Simulation time 190760380 ps
CPU time 0.83 seconds
Started Jul 02 09:09:07 AM PDT 24
Finished Jul 02 09:09:11 AM PDT 24
Peak memory 206056 kb
Host smart-bdee8c7f-4e0b-40b2-bfd0-ee111414d7c8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1630176691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1630176691
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2694716369
Short name T375
Test name
Test status
Simulation time 194599120 ps
CPU time 0.86 seconds
Started Jul 02 09:09:04 AM PDT 24
Finished Jul 02 09:09:09 AM PDT 24
Peak memory 206144 kb
Host smart-56918601-0ed1-48d3-b5b1-96c60fc3d173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26947
16369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2694716369
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3387611607
Short name T2411
Test name
Test status
Simulation time 183670111 ps
CPU time 0.88 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:07 AM PDT 24
Peak memory 206200 kb
Host smart-09daaa62-e709-41d2-aff6-6cd81e40a715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33876
11607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3387611607
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.886375445
Short name T641
Test name
Test status
Simulation time 153511059 ps
CPU time 0.84 seconds
Started Jul 02 09:09:10 AM PDT 24
Finished Jul 02 09:09:13 AM PDT 24
Peak memory 206196 kb
Host smart-586b3a28-6829-409b-9714-fc46ca8665fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88637
5445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.886375445
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.3526590840
Short name T735
Test name
Test status
Simulation time 190589375 ps
CPU time 0.84 seconds
Started Jul 02 09:09:04 AM PDT 24
Finished Jul 02 09:09:09 AM PDT 24
Peak memory 206172 kb
Host smart-63eba71e-192a-4d89-9b35-2681c3433afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35265
90840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3526590840
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3999243867
Short name T1318
Test name
Test status
Simulation time 170424818 ps
CPU time 0.85 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:07 AM PDT 24
Peak memory 206220 kb
Host smart-dc15a81c-61ea-402a-b931-a3f977bb996d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39992
43867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3999243867
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3227961524
Short name T80
Test name
Test status
Simulation time 280262213 ps
CPU time 1.09 seconds
Started Jul 02 09:09:20 AM PDT 24
Finished Jul 02 09:09:22 AM PDT 24
Peak memory 206120 kb
Host smart-e39ad82c-04fd-4f7c-8ae8-9f001c266fee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3227961524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3227961524
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.4140742777
Short name T2178
Test name
Test status
Simulation time 145653992 ps
CPU time 0.78 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:06 AM PDT 24
Peak memory 206176 kb
Host smart-0078a240-22ce-4e0f-8fdd-d90dfcd6d880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41407
42777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.4140742777
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3302790600
Short name T1177
Test name
Test status
Simulation time 35354838 ps
CPU time 0.65 seconds
Started Jul 02 09:09:06 AM PDT 24
Finished Jul 02 09:09:10 AM PDT 24
Peak memory 206204 kb
Host smart-47a3cc16-e000-4898-9469-e89b14bbc6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33027
90600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3302790600
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3435144240
Short name T2028
Test name
Test status
Simulation time 17777752894 ps
CPU time 38.46 seconds
Started Jul 02 09:09:06 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206556 kb
Host smart-8b11d683-29d8-4e48-b78d-5eb05dcba9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34351
44240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3435144240
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2797154118
Short name T480
Test name
Test status
Simulation time 182612806 ps
CPU time 0.84 seconds
Started Jul 02 09:09:06 AM PDT 24
Finished Jul 02 09:09:11 AM PDT 24
Peak memory 206164 kb
Host smart-f1db5c38-644b-4e0d-a5b0-3c31eab6c8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27971
54118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2797154118
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1030635817
Short name T1525
Test name
Test status
Simulation time 242457639 ps
CPU time 0.94 seconds
Started Jul 02 09:09:08 AM PDT 24
Finished Jul 02 09:09:12 AM PDT 24
Peak memory 206204 kb
Host smart-c72722e0-bdca-436a-ada1-2cb3650f3873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10306
35817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1030635817
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.4223283461
Short name T498
Test name
Test status
Simulation time 219580763 ps
CPU time 0.84 seconds
Started Jul 02 09:09:14 AM PDT 24
Finished Jul 02 09:09:17 AM PDT 24
Peak memory 206200 kb
Host smart-2c7f109f-c31c-4448-90a5-76bfc2022c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42232
83461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.4223283461
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2079107415
Short name T399
Test name
Test status
Simulation time 218020689 ps
CPU time 0.92 seconds
Started Jul 02 09:09:05 AM PDT 24
Finished Jul 02 09:09:09 AM PDT 24
Peak memory 206212 kb
Host smart-ddd119f5-e9e9-4458-a573-6da5adaf2df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20791
07415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2079107415
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.551910049
Short name T678
Test name
Test status
Simulation time 182187448 ps
CPU time 0.82 seconds
Started Jul 02 09:09:04 AM PDT 24
Finished Jul 02 09:09:09 AM PDT 24
Peak memory 206188 kb
Host smart-83faf900-0e7f-4951-8ffa-80ff9264c08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55191
0049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.551910049
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1107530608
Short name T2418
Test name
Test status
Simulation time 190520760 ps
CPU time 0.83 seconds
Started Jul 02 09:09:11 AM PDT 24
Finished Jul 02 09:09:14 AM PDT 24
Peak memory 206192 kb
Host smart-6c89055a-d4e6-45fd-844c-62349d236c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11075
30608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1107530608
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1329814703
Short name T1180
Test name
Test status
Simulation time 190759828 ps
CPU time 0.81 seconds
Started Jul 02 09:09:06 AM PDT 24
Finished Jul 02 09:09:10 AM PDT 24
Peak memory 206080 kb
Host smart-abaf1cfd-0045-411d-88e0-fd481a8ac14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13298
14703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1329814703
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3791447625
Short name T2529
Test name
Test status
Simulation time 236640427 ps
CPU time 1.06 seconds
Started Jul 02 09:09:11 AM PDT 24
Finished Jul 02 09:09:14 AM PDT 24
Peak memory 206196 kb
Host smart-34031224-6dac-4b88-a06f-6a9f6fc710e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37914
47625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3791447625
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3393449042
Short name T371
Test name
Test status
Simulation time 6876815832 ps
CPU time 49.74 seconds
Started Jul 02 09:09:07 AM PDT 24
Finished Jul 02 09:10:00 AM PDT 24
Peak memory 206408 kb
Host smart-5322fc14-0ea6-4618-9919-18bd4c09cea3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3393449042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3393449042
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3957407398
Short name T513
Test name
Test status
Simulation time 174427097 ps
CPU time 0.84 seconds
Started Jul 02 09:09:12 AM PDT 24
Finished Jul 02 09:09:15 AM PDT 24
Peak memory 206160 kb
Host smart-3f61c06f-1ff9-4b02-b3ec-a78e4a2a2fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39574
07398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3957407398
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2959421414
Short name T2127
Test name
Test status
Simulation time 226493716 ps
CPU time 0.86 seconds
Started Jul 02 09:09:04 AM PDT 24
Finished Jul 02 09:09:09 AM PDT 24
Peak memory 206224 kb
Host smart-37a9858d-4155-4f78-945f-723b0f29c79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29594
21414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2959421414
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.1205296386
Short name T2110
Test name
Test status
Simulation time 201447745 ps
CPU time 0.98 seconds
Started Jul 02 09:09:09 AM PDT 24
Finished Jul 02 09:09:12 AM PDT 24
Peak memory 206132 kb
Host smart-b9ef7eba-65a5-4b53-839d-5a8036c20929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12052
96386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.1205296386
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.931277136
Short name T1859
Test name
Test status
Simulation time 2833470788 ps
CPU time 19.01 seconds
Started Jul 02 09:09:06 AM PDT 24
Finished Jul 02 09:09:29 AM PDT 24
Peak memory 206388 kb
Host smart-ad21f530-06bf-458d-a92f-287abb0cb925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93127
7136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.931277136
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3203537250
Short name T1850
Test name
Test status
Simulation time 84676082 ps
CPU time 0.75 seconds
Started Jul 02 09:06:31 AM PDT 24
Finished Jul 02 09:06:34 AM PDT 24
Peak memory 206224 kb
Host smart-cc29a393-320f-470c-83d7-1eee1f63c550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3203537250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3203537250
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.4218332260
Short name T1877
Test name
Test status
Simulation time 3526314127 ps
CPU time 4.06 seconds
Started Jul 02 09:06:18 AM PDT 24
Finished Jul 02 09:06:22 AM PDT 24
Peak memory 206408 kb
Host smart-c1a7e910-3797-41e2-ba7d-b0d7db38996b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4218332260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.4218332260
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2412567143
Short name T1886
Test name
Test status
Simulation time 13338149225 ps
CPU time 12.56 seconds
Started Jul 02 09:06:19 AM PDT 24
Finished Jul 02 09:06:32 AM PDT 24
Peak memory 206240 kb
Host smart-ef8f9f53-9fe0-4f11-bc7b-8dd3b34e1936
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2412567143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2412567143
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2922695901
Short name T14
Test name
Test status
Simulation time 23441290368 ps
CPU time 22.98 seconds
Started Jul 02 09:06:10 AM PDT 24
Finished Jul 02 09:06:35 AM PDT 24
Peak memory 206244 kb
Host smart-2b9c6e63-f212-45d5-8d14-63ee4a172ad0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2922695901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.2922695901
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2340753526
Short name T897
Test name
Test status
Simulation time 151534814 ps
CPU time 0.75 seconds
Started Jul 02 09:06:14 AM PDT 24
Finished Jul 02 09:06:17 AM PDT 24
Peak memory 206216 kb
Host smart-b83f888b-941c-4bbd-b2fd-f88be208a82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23407
53526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2340753526
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2948400996
Short name T1454
Test name
Test status
Simulation time 221958039 ps
CPU time 0.91 seconds
Started Jul 02 09:06:25 AM PDT 24
Finished Jul 02 09:06:26 AM PDT 24
Peak memory 206188 kb
Host smart-f90adec7-bad0-4ded-ae41-2db5e45f356b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29484
00996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2948400996
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3677605195
Short name T2000
Test name
Test status
Simulation time 186217770 ps
CPU time 0.84 seconds
Started Jul 02 09:06:18 AM PDT 24
Finished Jul 02 09:06:20 AM PDT 24
Peak memory 206224 kb
Host smart-f9649538-7997-4836-9cbe-de70bca95c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36776
05195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3677605195
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.4195698625
Short name T2578
Test name
Test status
Simulation time 745344957 ps
CPU time 2.05 seconds
Started Jul 02 09:06:16 AM PDT 24
Finished Jul 02 09:06:19 AM PDT 24
Peak memory 206412 kb
Host smart-bc2acfd9-803e-4559-ae8e-f2ab0ab53a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41956
98625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.4195698625
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.854085107
Short name T101
Test name
Test status
Simulation time 7175301583 ps
CPU time 16.07 seconds
Started Jul 02 09:06:17 AM PDT 24
Finished Jul 02 09:06:34 AM PDT 24
Peak memory 206684 kb
Host smart-e8875bb9-3689-4e12-8569-48c40798f254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85408
5107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.854085107
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.377102942
Short name T452
Test name
Test status
Simulation time 425084866 ps
CPU time 1.27 seconds
Started Jul 02 09:06:20 AM PDT 24
Finished Jul 02 09:06:22 AM PDT 24
Peak memory 206128 kb
Host smart-a30945db-d576-4f5b-bd1a-00ac83150067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37710
2942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.377102942
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3864441184
Short name T1889
Test name
Test status
Simulation time 136811557 ps
CPU time 0.73 seconds
Started Jul 02 09:06:14 AM PDT 24
Finished Jul 02 09:06:16 AM PDT 24
Peak memory 206180 kb
Host smart-f7b708f6-8a35-4d07-9a24-5ec23979ca93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38644
41184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3864441184
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.60958791
Short name T1950
Test name
Test status
Simulation time 38262313 ps
CPU time 0.65 seconds
Started Jul 02 09:06:14 AM PDT 24
Finished Jul 02 09:06:16 AM PDT 24
Peak memory 206152 kb
Host smart-99454001-ddef-4649-b429-b3a2960917b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60958
791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.60958791
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3818235251
Short name T1369
Test name
Test status
Simulation time 823596187 ps
CPU time 2.07 seconds
Started Jul 02 09:06:12 AM PDT 24
Finished Jul 02 09:06:16 AM PDT 24
Peak memory 206360 kb
Host smart-ace53c2b-d8bf-41c2-a887-c547198a85fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38182
35251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3818235251
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.880450906
Short name T1908
Test name
Test status
Simulation time 165292848 ps
CPU time 1.71 seconds
Started Jul 02 09:06:23 AM PDT 24
Finished Jul 02 09:06:25 AM PDT 24
Peak memory 206416 kb
Host smart-2fc6defb-836f-4556-8421-a90770af49f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88045
0906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.880450906
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.755165940
Short name T1697
Test name
Test status
Simulation time 95182621231 ps
CPU time 140.96 seconds
Started Jul 02 09:06:15 AM PDT 24
Finished Jul 02 09:08:37 AM PDT 24
Peak memory 206492 kb
Host smart-75c80bf2-440c-48e7-9cd5-ce5994685e54
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=755165940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.755165940
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.4033754153
Short name T1755
Test name
Test status
Simulation time 84061330463 ps
CPU time 122.02 seconds
Started Jul 02 09:06:19 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206440 kb
Host smart-d8741b9f-27fe-4dbd-b407-4890ad07cdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033754153 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.4033754153
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.1066533243
Short name T1163
Test name
Test status
Simulation time 111113396717 ps
CPU time 166.44 seconds
Started Jul 02 09:06:20 AM PDT 24
Finished Jul 02 09:09:07 AM PDT 24
Peak memory 206416 kb
Host smart-699ddc14-b66c-44a0-a04a-a16fcf770551
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1066533243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1066533243
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1463440770
Short name T1538
Test name
Test status
Simulation time 121175470876 ps
CPU time 162.2 seconds
Started Jul 02 09:06:17 AM PDT 24
Finished Jul 02 09:09:00 AM PDT 24
Peak memory 206376 kb
Host smart-55c956f6-ee2d-4a64-b4a2-776b1c5ba732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463440770 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1463440770
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.3831398544
Short name T2103
Test name
Test status
Simulation time 100169955068 ps
CPU time 126.37 seconds
Started Jul 02 09:06:12 AM PDT 24
Finished Jul 02 09:08:20 AM PDT 24
Peak memory 206460 kb
Host smart-3b9df645-abcf-4ba6-93c0-8c4038a316dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38313
98544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3831398544
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.4145942417
Short name T2189
Test name
Test status
Simulation time 143627586 ps
CPU time 0.8 seconds
Started Jul 02 09:06:18 AM PDT 24
Finished Jul 02 09:06:19 AM PDT 24
Peak memory 206204 kb
Host smart-f62ef0b7-f446-4bdb-87e8-5d63433a6c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41459
42417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.4145942417
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1117676511
Short name T2300
Test name
Test status
Simulation time 258130233 ps
CPU time 1 seconds
Started Jul 02 09:06:13 AM PDT 24
Finished Jul 02 09:06:16 AM PDT 24
Peak memory 206200 kb
Host smart-9fffaf5c-8335-4602-a766-50f31fc35ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
76511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1117676511
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.122246814
Short name T242
Test name
Test status
Simulation time 7199748021 ps
CPU time 203.58 seconds
Started Jul 02 09:06:20 AM PDT 24
Finished Jul 02 09:09:44 AM PDT 24
Peak memory 206508 kb
Host smart-b2a395b4-7008-4354-a386-9ed61fe22c22
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=122246814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.122246814
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.975083057
Short name T2253
Test name
Test status
Simulation time 301516448 ps
CPU time 1 seconds
Started Jul 02 09:06:18 AM PDT 24
Finished Jul 02 09:06:19 AM PDT 24
Peak memory 206180 kb
Host smart-9d91c296-ceb7-4746-81bd-64cfed039411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97508
3057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.975083057
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.386448612
Short name T1651
Test name
Test status
Simulation time 23294231191 ps
CPU time 23.77 seconds
Started Jul 02 09:06:13 AM PDT 24
Finished Jul 02 09:06:39 AM PDT 24
Peak memory 206268 kb
Host smart-d24dc0cf-cd91-4ba2-a8e8-f7c6efba10c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38644
8612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.386448612
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3797092752
Short name T570
Test name
Test status
Simulation time 3380647060 ps
CPU time 4.52 seconds
Started Jul 02 09:06:15 AM PDT 24
Finished Jul 02 09:06:21 AM PDT 24
Peak memory 206240 kb
Host smart-f1722c59-b9ee-44e1-8ba1-c666cb33f73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37970
92752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3797092752
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2778326977
Short name T1631
Test name
Test status
Simulation time 8409730606 ps
CPU time 59.99 seconds
Started Jul 02 09:06:18 AM PDT 24
Finished Jul 02 09:07:19 AM PDT 24
Peak memory 206496 kb
Host smart-199359af-5ce7-4cd3-a949-2f071936d8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783
26977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2778326977
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.2800385405
Short name T424
Test name
Test status
Simulation time 7118458968 ps
CPU time 185.05 seconds
Started Jul 02 09:06:26 AM PDT 24
Finished Jul 02 09:09:32 AM PDT 24
Peak memory 206424 kb
Host smart-da87d948-d5b1-4862-9cbd-d96d8eca4ceb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2800385405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.2800385405
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.3517895768
Short name T2357
Test name
Test status
Simulation time 275265646 ps
CPU time 0.94 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:06:29 AM PDT 24
Peak memory 206164 kb
Host smart-7de4ffc1-6749-4dea-b074-ce9dd6e35559
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3517895768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.3517895768
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2517478495
Short name T553
Test name
Test status
Simulation time 187786013 ps
CPU time 0.9 seconds
Started Jul 02 09:06:22 AM PDT 24
Finished Jul 02 09:06:24 AM PDT 24
Peak memory 206220 kb
Host smart-0f1c4b39-f740-4848-bae1-8f391c93db7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25174
78495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2517478495
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.3166467421
Short name T1071
Test name
Test status
Simulation time 6277474898 ps
CPU time 176.02 seconds
Started Jul 02 09:06:20 AM PDT 24
Finished Jul 02 09:09:17 AM PDT 24
Peak memory 206504 kb
Host smart-6c3f3da4-ec39-4090-bddf-1c939bbc0837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31664
67421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.3166467421
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1143242232
Short name T1993
Test name
Test status
Simulation time 4776273832 ps
CPU time 35.99 seconds
Started Jul 02 09:06:19 AM PDT 24
Finished Jul 02 09:06:56 AM PDT 24
Peak memory 206428 kb
Host smart-46ca08ed-293e-4fef-bed5-13f569bc1da1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1143242232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1143242232
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1213808240
Short name T761
Test name
Test status
Simulation time 154804550 ps
CPU time 0.8 seconds
Started Jul 02 09:06:21 AM PDT 24
Finished Jul 02 09:06:22 AM PDT 24
Peak memory 206160 kb
Host smart-a9b038f5-bd03-460f-b579-631077af19e6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1213808240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1213808240
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.281884363
Short name T1038
Test name
Test status
Simulation time 153670105 ps
CPU time 0.76 seconds
Started Jul 02 09:06:19 AM PDT 24
Finished Jul 02 09:06:21 AM PDT 24
Peak memory 206136 kb
Host smart-1ba668d9-6003-4c8f-9897-0b4ba186cbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28188
4363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.281884363
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2751560273
Short name T2486
Test name
Test status
Simulation time 236781035 ps
CPU time 0.87 seconds
Started Jul 02 09:06:21 AM PDT 24
Finished Jul 02 09:06:23 AM PDT 24
Peak memory 206184 kb
Host smart-26bbc7a8-300a-4474-b5f4-6425072aa7e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27515
60273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2751560273
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2209246357
Short name T811
Test name
Test status
Simulation time 166269314 ps
CPU time 0.79 seconds
Started Jul 02 09:06:20 AM PDT 24
Finished Jul 02 09:06:21 AM PDT 24
Peak memory 206216 kb
Host smart-0865ef58-01df-43bb-b936-d319788ec5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22092
46357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2209246357
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3467657095
Short name T330
Test name
Test status
Simulation time 192238455 ps
CPU time 0.83 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:06:31 AM PDT 24
Peak memory 206220 kb
Host smart-62bf3073-2c6f-4a31-959c-740e7f292940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34676
57095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3467657095
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1911105782
Short name T274
Test name
Test status
Simulation time 188056041 ps
CPU time 0.81 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:06:30 AM PDT 24
Peak memory 206204 kb
Host smart-560e5c82-02fd-49f9-ac63-751120d11f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19111
05782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1911105782
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.893741289
Short name T1322
Test name
Test status
Simulation time 176761643 ps
CPU time 0.82 seconds
Started Jul 02 09:06:23 AM PDT 24
Finished Jul 02 09:06:24 AM PDT 24
Peak memory 206392 kb
Host smart-a7154ca6-d60a-4cb4-830c-91b5e1e5badc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89374
1289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.893741289
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2745292460
Short name T2614
Test name
Test status
Simulation time 206494788 ps
CPU time 0.92 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:06:36 AM PDT 24
Peak memory 206184 kb
Host smart-007f207c-c354-4273-b40c-6616f6c9c88e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2745292460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2745292460
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.3461854355
Short name T2650
Test name
Test status
Simulation time 214613417 ps
CPU time 0.98 seconds
Started Jul 02 09:06:22 AM PDT 24
Finished Jul 02 09:06:23 AM PDT 24
Peak memory 206216 kb
Host smart-4461d2a8-b214-4c0e-96ee-47f581925bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34618
54355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.3461854355
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1667466554
Short name T919
Test name
Test status
Simulation time 139332037 ps
CPU time 0.74 seconds
Started Jul 02 09:06:23 AM PDT 24
Finished Jul 02 09:06:25 AM PDT 24
Peak memory 206132 kb
Host smart-588d40ff-c067-440f-9001-dc7ba9b2be67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16674
66554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1667466554
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.4092719285
Short name T2206
Test name
Test status
Simulation time 51368815 ps
CPU time 0.65 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:06:31 AM PDT 24
Peak memory 206184 kb
Host smart-4d44389d-1f1c-495f-bcca-3ebdd512ab2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40927
19285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.4092719285
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.4090137638
Short name T2069
Test name
Test status
Simulation time 20604780843 ps
CPU time 48.37 seconds
Started Jul 02 09:06:30 AM PDT 24
Finished Jul 02 09:07:20 AM PDT 24
Peak memory 214740 kb
Host smart-0176dd46-f905-4628-a9a7-dbd1f19982e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40901
37638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.4090137638
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1595583114
Short name T1956
Test name
Test status
Simulation time 187951570 ps
CPU time 0.87 seconds
Started Jul 02 09:06:24 AM PDT 24
Finished Jul 02 09:06:26 AM PDT 24
Peak memory 206184 kb
Host smart-6d16b44a-937d-443a-9b20-ef8461c7b920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15955
83114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1595583114
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2110511888
Short name T618
Test name
Test status
Simulation time 263411202 ps
CPU time 0.94 seconds
Started Jul 02 09:06:27 AM PDT 24
Finished Jul 02 09:06:29 AM PDT 24
Peak memory 206156 kb
Host smart-8869401a-ef03-4d2d-aaca-8eb6b5a980d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21105
11888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2110511888
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3541406979
Short name T2075
Test name
Test status
Simulation time 10062924807 ps
CPU time 49.68 seconds
Started Jul 02 09:06:22 AM PDT 24
Finished Jul 02 09:07:13 AM PDT 24
Peak memory 206524 kb
Host smart-7ff2b5d5-0d42-4f4d-8a2b-5d3298f94af0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3541406979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3541406979
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.784120275
Short name T2343
Test name
Test status
Simulation time 4409240822 ps
CPU time 40.31 seconds
Started Jul 02 09:06:27 AM PDT 24
Finished Jul 02 09:07:08 AM PDT 24
Peak memory 206440 kb
Host smart-e48c0e95-6858-4f80-9f91-59618079c2fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=784120275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.784120275
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2438213370
Short name T2534
Test name
Test status
Simulation time 11238620241 ps
CPU time 209.79 seconds
Started Jul 02 09:06:22 AM PDT 24
Finished Jul 02 09:09:53 AM PDT 24
Peak memory 206532 kb
Host smart-76e65705-c1f8-438c-aa1c-cf75c54d298b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2438213370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2438213370
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.2493149296
Short name T2291
Test name
Test status
Simulation time 219688180 ps
CPU time 0.9 seconds
Started Jul 02 09:06:24 AM PDT 24
Finished Jul 02 09:06:26 AM PDT 24
Peak memory 206176 kb
Host smart-79603634-5230-4791-8fc6-cbf5682d5269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24931
49296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.2493149296
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2404644063
Short name T622
Test name
Test status
Simulation time 163582288 ps
CPU time 0.79 seconds
Started Jul 02 09:06:25 AM PDT 24
Finished Jul 02 09:06:27 AM PDT 24
Peak memory 206224 kb
Host smart-2a1a73f6-3bfc-410a-b801-da45185f5e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24046
44063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2404644063
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3494680489
Short name T387
Test name
Test status
Simulation time 131663796 ps
CPU time 0.75 seconds
Started Jul 02 09:06:23 AM PDT 24
Finished Jul 02 09:06:24 AM PDT 24
Peak memory 206120 kb
Host smart-f3c0ead1-1e70-4e82-80c9-cb689cb7f565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34946
80489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3494680489
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.52991875
Short name T77
Test name
Test status
Simulation time 184743867 ps
CPU time 0.82 seconds
Started Jul 02 09:06:23 AM PDT 24
Finished Jul 02 09:06:24 AM PDT 24
Peak memory 206128 kb
Host smart-38c194b4-ab00-4f11-b4da-fca0d58b54ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52991
875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.52991875
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.812124942
Short name T212
Test name
Test status
Simulation time 343873863 ps
CPU time 1.22 seconds
Started Jul 02 09:06:31 AM PDT 24
Finished Jul 02 09:06:34 AM PDT 24
Peak memory 223952 kb
Host smart-6b9485ce-ed09-49ee-bd5c-0b12b0c86a87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=812124942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.812124942
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1699780063
Short name T2424
Test name
Test status
Simulation time 350939376 ps
CPU time 1.12 seconds
Started Jul 02 09:06:26 AM PDT 24
Finished Jul 02 09:06:28 AM PDT 24
Peak memory 206192 kb
Host smart-f0c2b401-15ea-4f5c-b26f-5c7f50b01c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16997
80063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1699780063
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.702850311
Short name T2533
Test name
Test status
Simulation time 199870843 ps
CPU time 0.89 seconds
Started Jul 02 09:06:26 AM PDT 24
Finished Jul 02 09:06:27 AM PDT 24
Peak memory 206212 kb
Host smart-af136174-4772-450c-9099-04609454c26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70285
0311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.702850311
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.590798140
Short name T439
Test name
Test status
Simulation time 148271979 ps
CPU time 0.8 seconds
Started Jul 02 09:06:27 AM PDT 24
Finished Jul 02 09:06:29 AM PDT 24
Peak memory 206180 kb
Host smart-5b277e8d-c0a4-4dbb-b781-7dc15ead7ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59079
8140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.590798140
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3600182937
Short name T1506
Test name
Test status
Simulation time 153657443 ps
CPU time 0.76 seconds
Started Jul 02 09:06:25 AM PDT 24
Finished Jul 02 09:06:26 AM PDT 24
Peak memory 206216 kb
Host smart-f00ff4bd-e310-485f-b168-ae2b0a0aabe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36001
82937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3600182937
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.4274892951
Short name T627
Test name
Test status
Simulation time 199149390 ps
CPU time 0.89 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:06:36 AM PDT 24
Peak memory 206156 kb
Host smart-dde3300d-42d2-4618-8423-0f253a687a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42748
92951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4274892951
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3486273103
Short name T161
Test name
Test status
Simulation time 3787055718 ps
CPU time 26.36 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:06:56 AM PDT 24
Peak memory 206436 kb
Host smart-b88cb33b-4d51-46ea-b57b-b053528a7044
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3486273103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3486273103
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2503370220
Short name T1929
Test name
Test status
Simulation time 163505892 ps
CPU time 0.81 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:06:31 AM PDT 24
Peak memory 206216 kb
Host smart-3428d23d-27a5-440e-8878-e7b47ce7bd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25033
70220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2503370220
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3614456972
Short name T1437
Test name
Test status
Simulation time 170987571 ps
CPU time 0.85 seconds
Started Jul 02 09:06:31 AM PDT 24
Finished Jul 02 09:06:33 AM PDT 24
Peak memory 206160 kb
Host smart-b2ed6715-0562-494c-af69-ced1d2fb7f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144
56972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3614456972
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.124218279
Short name T2628
Test name
Test status
Simulation time 898933685 ps
CPU time 2.04 seconds
Started Jul 02 09:06:29 AM PDT 24
Finished Jul 02 09:06:33 AM PDT 24
Peak memory 206436 kb
Host smart-d08c3580-80d8-4ba5-a590-0307c5fbb713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12421
8279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.124218279
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.65487359
Short name T158
Test name
Test status
Simulation time 4755633094 ps
CPU time 133.87 seconds
Started Jul 02 09:06:26 AM PDT 24
Finished Jul 02 09:08:41 AM PDT 24
Peak memory 206440 kb
Host smart-fdcb012c-3a94-4930-ad14-50655d9d4d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65487
359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.65487359
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.1890892399
Short name T17
Test name
Test status
Simulation time 32290311 ps
CPU time 0.74 seconds
Started Jul 02 09:09:29 AM PDT 24
Finished Jul 02 09:09:32 AM PDT 24
Peak memory 206252 kb
Host smart-4a000ceb-04e8-405d-b97e-c6e7ffa14fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1890892399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.1890892399
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.3767998570
Short name T2037
Test name
Test status
Simulation time 4225354787 ps
CPU time 5.36 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:11 AM PDT 24
Peak memory 206496 kb
Host smart-2068a721-0b8f-4064-aa76-7d59b427d290
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3767998570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.3767998570
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.813495720
Short name T1879
Test name
Test status
Simulation time 13372302504 ps
CPU time 13.14 seconds
Started Jul 02 09:09:11 AM PDT 24
Finished Jul 02 09:09:26 AM PDT 24
Peak memory 206244 kb
Host smart-877964d7-16d9-4124-b6b7-001c5312b809
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=813495720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.813495720
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.2533096741
Short name T959
Test name
Test status
Simulation time 23420362296 ps
CPU time 24.37 seconds
Started Jul 02 09:09:11 AM PDT 24
Finished Jul 02 09:09:37 AM PDT 24
Peak memory 206232 kb
Host smart-5284c127-22a9-43d3-9345-e19d8062cfdd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2533096741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.2533096741
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.949957301
Short name T2173
Test name
Test status
Simulation time 178822367 ps
CPU time 0.84 seconds
Started Jul 02 09:09:06 AM PDT 24
Finished Jul 02 09:09:10 AM PDT 24
Peak memory 206176 kb
Host smart-71a7ad73-e6f5-4f8d-bf0b-b9bb0d6fd39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94995
7301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.949957301
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3509299079
Short name T1281
Test name
Test status
Simulation time 228893406 ps
CPU time 0.89 seconds
Started Jul 02 09:09:06 AM PDT 24
Finished Jul 02 09:09:11 AM PDT 24
Peak memory 206184 kb
Host smart-0f347c03-d3c7-42df-964b-b678cbc5d922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35092
99079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3509299079
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.22760143
Short name T2303
Test name
Test status
Simulation time 532406488 ps
CPU time 1.59 seconds
Started Jul 02 09:09:13 AM PDT 24
Finished Jul 02 09:09:17 AM PDT 24
Peak memory 206452 kb
Host smart-8a3b5172-51bd-4357-be8e-41eaedf74fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22760
143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.22760143
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1975521990
Short name T199
Test name
Test status
Simulation time 994066217 ps
CPU time 2.24 seconds
Started Jul 02 09:09:04 AM PDT 24
Finished Jul 02 09:09:10 AM PDT 24
Peak memory 206444 kb
Host smart-70221095-c4d9-458f-87b8-5a4e13b84804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19755
21990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1975521990
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.1909935528
Short name T178
Test name
Test status
Simulation time 16635685667 ps
CPU time 33.38 seconds
Started Jul 02 09:09:03 AM PDT 24
Finished Jul 02 09:09:39 AM PDT 24
Peak memory 206480 kb
Host smart-5ef89048-d8eb-4baa-9043-308874a9b7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19099
35528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.1909935528
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.723871513
Short name T1401
Test name
Test status
Simulation time 362178417 ps
CPU time 1.14 seconds
Started Jul 02 09:09:12 AM PDT 24
Finished Jul 02 09:09:15 AM PDT 24
Peak memory 206200 kb
Host smart-a2bdb76f-995d-48bb-9298-12b2b546d3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72387
1513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.723871513
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3944686170
Short name T418
Test name
Test status
Simulation time 212424827 ps
CPU time 0.77 seconds
Started Jul 02 09:09:11 AM PDT 24
Finished Jul 02 09:09:14 AM PDT 24
Peak memory 206196 kb
Host smart-a9990148-455c-48ba-8eb4-04a5a4789a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
86170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3944686170
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1630565822
Short name T474
Test name
Test status
Simulation time 46819174 ps
CPU time 0.71 seconds
Started Jul 02 09:09:20 AM PDT 24
Finished Jul 02 09:09:22 AM PDT 24
Peak memory 206140 kb
Host smart-04f90f49-7737-4e76-b31f-cc34c3b31a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16305
65822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1630565822
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2698046767
Short name T852
Test name
Test status
Simulation time 1164141865 ps
CPU time 2.61 seconds
Started Jul 02 09:09:09 AM PDT 24
Finished Jul 02 09:09:14 AM PDT 24
Peak memory 206364 kb
Host smart-71fca969-a920-4671-88f6-76cb264c2e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26980
46767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2698046767
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3330208981
Short name T2082
Test name
Test status
Simulation time 207131796 ps
CPU time 1.25 seconds
Started Jul 02 09:09:10 AM PDT 24
Finished Jul 02 09:09:14 AM PDT 24
Peak memory 206368 kb
Host smart-44ab9f0d-6592-4424-973a-e44375473d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33302
08981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3330208981
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3815462820
Short name T113
Test name
Test status
Simulation time 167331659 ps
CPU time 0.85 seconds
Started Jul 02 09:09:10 AM PDT 24
Finished Jul 02 09:09:13 AM PDT 24
Peak memory 206184 kb
Host smart-d5058d21-b510-49f6-b7dc-0627f6d8ac93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38154
62820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3815462820
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3758430046
Short name T1288
Test name
Test status
Simulation time 176364645 ps
CPU time 0.8 seconds
Started Jul 02 09:09:08 AM PDT 24
Finished Jul 02 09:09:12 AM PDT 24
Peak memory 206180 kb
Host smart-9f6d38c4-18dc-4d4c-b8b1-01b33b043c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37584
30046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3758430046
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.891694352
Short name T2531
Test name
Test status
Simulation time 209664997 ps
CPU time 0.87 seconds
Started Jul 02 09:09:17 AM PDT 24
Finished Jul 02 09:09:18 AM PDT 24
Peak memory 206208 kb
Host smart-793c9d69-918c-4a1f-9d7b-863befe98f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89169
4352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.891694352
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.2022643803
Short name T1757
Test name
Test status
Simulation time 6076862810 ps
CPU time 174.48 seconds
Started Jul 02 09:09:11 AM PDT 24
Finished Jul 02 09:12:08 AM PDT 24
Peak memory 206540 kb
Host smart-913d2dbd-6dbc-43bd-a7f9-9ef9199d44a5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2022643803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2022643803
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2063832660
Short name T354
Test name
Test status
Simulation time 189246716 ps
CPU time 0.85 seconds
Started Jul 02 09:09:17 AM PDT 24
Finished Jul 02 09:09:19 AM PDT 24
Peak memory 206208 kb
Host smart-2fa43a42-05cf-469e-ae2c-6859fb4d8a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20638
32660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2063832660
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.34228568
Short name T1014
Test name
Test status
Simulation time 23342254620 ps
CPU time 27.69 seconds
Started Jul 02 09:09:15 AM PDT 24
Finished Jul 02 09:09:49 AM PDT 24
Peak memory 206240 kb
Host smart-f49d53c2-9125-4851-8ab1-790fb5dc945d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34228
568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.34228568
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3719135093
Short name T1222
Test name
Test status
Simulation time 3340279853 ps
CPU time 4.8 seconds
Started Jul 02 09:09:08 AM PDT 24
Finished Jul 02 09:09:16 AM PDT 24
Peak memory 206240 kb
Host smart-b944ace7-bb15-420f-9b9f-1b81c40de57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37191
35093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3719135093
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.3976251063
Short name T1966
Test name
Test status
Simulation time 5947278834 ps
CPU time 164 seconds
Started Jul 02 09:09:14 AM PDT 24
Finished Jul 02 09:12:00 AM PDT 24
Peak memory 206528 kb
Host smart-752e99e2-08ee-4d52-92aa-313d05fb2074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39762
51063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.3976251063
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.1560943043
Short name T254
Test name
Test status
Simulation time 5459441038 ps
CPU time 48.26 seconds
Started Jul 02 09:09:15 AM PDT 24
Finished Jul 02 09:10:05 AM PDT 24
Peak memory 206440 kb
Host smart-32bcb147-25f1-4891-9720-1cf90edab318
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1560943043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.1560943043
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2397299186
Short name T2519
Test name
Test status
Simulation time 245936664 ps
CPU time 0.92 seconds
Started Jul 02 09:09:11 AM PDT 24
Finished Jul 02 09:09:14 AM PDT 24
Peak memory 206188 kb
Host smart-cf4c36fc-9163-4b47-ad81-25b61f21a4be
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2397299186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2397299186
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1907899410
Short name T478
Test name
Test status
Simulation time 215159927 ps
CPU time 0.9 seconds
Started Jul 02 09:09:20 AM PDT 24
Finished Jul 02 09:09:23 AM PDT 24
Peak memory 206172 kb
Host smart-5bf5ae36-e278-4db1-a06a-fd690e7d473f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19078
99410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1907899410
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.297617491
Short name T2505
Test name
Test status
Simulation time 6003251262 ps
CPU time 54.94 seconds
Started Jul 02 09:09:16 AM PDT 24
Finished Jul 02 09:10:12 AM PDT 24
Peak memory 206468 kb
Host smart-6014b094-36d4-4751-91ea-a432d2860537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761
7491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.297617491
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.147668015
Short name T557
Test name
Test status
Simulation time 6763605353 ps
CPU time 198.24 seconds
Started Jul 02 09:09:10 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206472 kb
Host smart-5c223a34-08ba-4411-8c54-75f505ae0072
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=147668015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.147668015
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1202793547
Short name T1319
Test name
Test status
Simulation time 182946360 ps
CPU time 0.84 seconds
Started Jul 02 09:09:23 AM PDT 24
Finished Jul 02 09:09:25 AM PDT 24
Peak memory 206204 kb
Host smart-4d2b73e0-1c20-41a7-8275-d0841e55e180
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1202793547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1202793547
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3263670499
Short name T1700
Test name
Test status
Simulation time 146316352 ps
CPU time 0.78 seconds
Started Jul 02 09:09:09 AM PDT 24
Finished Jul 02 09:09:12 AM PDT 24
Peak memory 206184 kb
Host smart-67c27ba1-4b86-4b50-98c7-e5c50eb57ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32636
70499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3263670499
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1578050087
Short name T135
Test name
Test status
Simulation time 231975118 ps
CPU time 0.95 seconds
Started Jul 02 09:09:19 AM PDT 24
Finished Jul 02 09:09:21 AM PDT 24
Peak memory 206224 kb
Host smart-968d57c0-275a-4ff8-9d7c-493b176d8f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15780
50087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1578050087
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.1451186350
Short name T734
Test name
Test status
Simulation time 233281551 ps
CPU time 0.91 seconds
Started Jul 02 09:09:11 AM PDT 24
Finished Jul 02 09:09:14 AM PDT 24
Peak memory 206216 kb
Host smart-176b1339-03bb-4d0a-97a9-8bc9b48bc23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14511
86350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.1451186350
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1874883552
Short name T1526
Test name
Test status
Simulation time 166994530 ps
CPU time 0.81 seconds
Started Jul 02 09:09:10 AM PDT 24
Finished Jul 02 09:09:13 AM PDT 24
Peak memory 206176 kb
Host smart-293a2bda-cbe4-41b7-b083-d4f34a3235bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18748
83552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1874883552
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3050186325
Short name T381
Test name
Test status
Simulation time 175945933 ps
CPU time 0.83 seconds
Started Jul 02 09:09:10 AM PDT 24
Finished Jul 02 09:09:13 AM PDT 24
Peak memory 206388 kb
Host smart-03923c02-c8a7-47e9-a44c-c7482a18b58a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30501
86325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3050186325
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2434379647
Short name T31
Test name
Test status
Simulation time 148915163 ps
CPU time 0.78 seconds
Started Jul 02 09:09:13 AM PDT 24
Finished Jul 02 09:09:16 AM PDT 24
Peak memory 206160 kb
Host smart-734ec44f-cb06-4c61-87e9-fb3d813d7a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24343
79647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2434379647
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2840689370
Short name T813
Test name
Test status
Simulation time 213503548 ps
CPU time 0.94 seconds
Started Jul 02 09:09:11 AM PDT 24
Finished Jul 02 09:09:14 AM PDT 24
Peak memory 206192 kb
Host smart-aed4fb8d-1904-48f7-8377-f4bf3e7b6607
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2840689370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2840689370
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1022673021
Short name T2005
Test name
Test status
Simulation time 180280437 ps
CPU time 0.76 seconds
Started Jul 02 09:09:07 AM PDT 24
Finished Jul 02 09:09:11 AM PDT 24
Peak memory 206212 kb
Host smart-f2c225e4-3614-409b-b205-40b875a0bc89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10226
73021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1022673021
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.141553513
Short name T1112
Test name
Test status
Simulation time 81170531 ps
CPU time 0.72 seconds
Started Jul 02 09:09:10 AM PDT 24
Finished Jul 02 09:09:13 AM PDT 24
Peak memory 206176 kb
Host smart-a5069604-fa8c-4ef0-8cf7-34e7e11b88eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14155
3513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.141553513
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3935770171
Short name T1937
Test name
Test status
Simulation time 7988159677 ps
CPU time 17.72 seconds
Started Jul 02 09:09:09 AM PDT 24
Finished Jul 02 09:09:30 AM PDT 24
Peak memory 214712 kb
Host smart-c1864f86-833b-4330-acd3-0c20fd2a045a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39357
70171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3935770171
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3845164664
Short name T1805
Test name
Test status
Simulation time 178383424 ps
CPU time 0.87 seconds
Started Jul 02 09:09:12 AM PDT 24
Finished Jul 02 09:09:15 AM PDT 24
Peak memory 206392 kb
Host smart-69901fc1-82ec-4871-bb22-f2f9191c4553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38451
64664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3845164664
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3661698010
Short name T1942
Test name
Test status
Simulation time 208136544 ps
CPU time 0.92 seconds
Started Jul 02 09:09:23 AM PDT 24
Finished Jul 02 09:09:25 AM PDT 24
Peak memory 206204 kb
Host smart-8a31c6b3-f91c-46ca-a1a9-875f6dcb5675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36616
98010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3661698010
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.2834719962
Short name T1585
Test name
Test status
Simulation time 205433079 ps
CPU time 0.91 seconds
Started Jul 02 09:09:14 AM PDT 24
Finished Jul 02 09:09:17 AM PDT 24
Peak memory 206216 kb
Host smart-db900cc5-9e1f-40e0-a22d-30b3995a0f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28347
19962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.2834719962
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3758468311
Short name T1350
Test name
Test status
Simulation time 203133701 ps
CPU time 0.88 seconds
Started Jul 02 09:09:17 AM PDT 24
Finished Jul 02 09:09:20 AM PDT 24
Peak memory 206184 kb
Host smart-c7f55e80-6f01-431c-9e64-d15a2c924b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37584
68311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3758468311
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3464740926
Short name T950
Test name
Test status
Simulation time 141290798 ps
CPU time 0.75 seconds
Started Jul 02 09:09:21 AM PDT 24
Finished Jul 02 09:09:23 AM PDT 24
Peak memory 206204 kb
Host smart-03e2137a-27d8-4c83-94cf-2b5d99c7bee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34647
40926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3464740926
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3933497353
Short name T165
Test name
Test status
Simulation time 151215477 ps
CPU time 0.79 seconds
Started Jul 02 09:09:22 AM PDT 24
Finished Jul 02 09:09:24 AM PDT 24
Peak memory 206204 kb
Host smart-1e78d9c9-d208-4af7-a7e5-3121d48d9440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39334
97353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3933497353
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2723326688
Short name T1394
Test name
Test status
Simulation time 195534220 ps
CPU time 0.82 seconds
Started Jul 02 09:09:25 AM PDT 24
Finished Jul 02 09:09:27 AM PDT 24
Peak memory 206184 kb
Host smart-50c7b39a-f959-45ea-a0e7-3344106a9cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233
26688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2723326688
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3265021092
Short name T1801
Test name
Test status
Simulation time 230035278 ps
CPU time 0.98 seconds
Started Jul 02 09:09:13 AM PDT 24
Finished Jul 02 09:09:16 AM PDT 24
Peak memory 206120 kb
Host smart-9dbabde8-8db0-4ba0-a9aa-a33e4c0dfa90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32650
21092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3265021092
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2820410786
Short name T578
Test name
Test status
Simulation time 3914254345 ps
CPU time 112.67 seconds
Started Jul 02 09:09:18 AM PDT 24
Finished Jul 02 09:11:12 AM PDT 24
Peak memory 206508 kb
Host smart-384f7ead-113f-43bb-8856-7ab29db97b0f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2820410786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2820410786
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.701289703
Short name T1630
Test name
Test status
Simulation time 175190234 ps
CPU time 0.87 seconds
Started Jul 02 09:09:15 AM PDT 24
Finished Jul 02 09:09:18 AM PDT 24
Peak memory 206216 kb
Host smart-3b7a710e-c106-4c45-8c36-0c0282532faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70128
9703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.701289703
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1548022143
Short name T889
Test name
Test status
Simulation time 154397229 ps
CPU time 0.79 seconds
Started Jul 02 09:09:18 AM PDT 24
Finished Jul 02 09:09:20 AM PDT 24
Peak memory 206212 kb
Host smart-b840bed2-6523-4426-a92d-5418a411f882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15480
22143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1548022143
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2623854771
Short name T491
Test name
Test status
Simulation time 881052698 ps
CPU time 1.89 seconds
Started Jul 02 09:09:19 AM PDT 24
Finished Jul 02 09:09:22 AM PDT 24
Peak memory 206396 kb
Host smart-dd13e6c4-eda1-4127-8439-0575924deb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26238
54771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2623854771
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.1852778307
Short name T2375
Test name
Test status
Simulation time 5634071011 ps
CPU time 40.7 seconds
Started Jul 02 09:09:19 AM PDT 24
Finished Jul 02 09:10:01 AM PDT 24
Peak memory 206436 kb
Host smart-7341a85a-8cfc-4fb7-8f36-6941ad1890b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18527
78307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.1852778307
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.3810551913
Short name T1817
Test name
Test status
Simulation time 38781888 ps
CPU time 0.67 seconds
Started Jul 02 09:09:27 AM PDT 24
Finished Jul 02 09:09:29 AM PDT 24
Peak memory 206236 kb
Host smart-d0c8943b-4ca2-46d1-a4e4-a50602f35128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3810551913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.3810551913
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.514773965
Short name T611
Test name
Test status
Simulation time 4161342717 ps
CPU time 5.09 seconds
Started Jul 02 09:09:21 AM PDT 24
Finished Jul 02 09:09:27 AM PDT 24
Peak memory 206500 kb
Host smart-53c4133e-ec24-47da-be2d-cd0bbf154528
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=514773965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.514773965
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.14661214
Short name T762
Test name
Test status
Simulation time 13441538095 ps
CPU time 13.38 seconds
Started Jul 02 09:09:22 AM PDT 24
Finished Jul 02 09:09:37 AM PDT 24
Peak memory 206248 kb
Host smart-a1b5654b-272b-46c6-bd2f-4980e663748d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=14661214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.14661214
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2086805377
Short name T2097
Test name
Test status
Simulation time 23380058173 ps
CPU time 24.05 seconds
Started Jul 02 09:09:15 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206200 kb
Host smart-db0c4803-93a8-4787-adfd-7d1ec6994d2d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2086805377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2086805377
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2695580462
Short name T839
Test name
Test status
Simulation time 182414688 ps
CPU time 0.85 seconds
Started Jul 02 09:09:22 AM PDT 24
Finished Jul 02 09:09:24 AM PDT 24
Peak memory 206168 kb
Host smart-10c6aa92-8b33-4217-8568-6809c41f1b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26955
80462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2695580462
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3869783997
Short name T2280
Test name
Test status
Simulation time 176962971 ps
CPU time 0.76 seconds
Started Jul 02 09:09:13 AM PDT 24
Finished Jul 02 09:09:16 AM PDT 24
Peak memory 206188 kb
Host smart-1271b96c-b1d3-4bb0-892a-3ffe2d7ab8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38697
83997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3869783997
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2792670066
Short name T111
Test name
Test status
Simulation time 248332317 ps
CPU time 0.98 seconds
Started Jul 02 09:09:21 AM PDT 24
Finished Jul 02 09:09:23 AM PDT 24
Peak memory 206208 kb
Host smart-86cc9fc2-44b5-4514-b143-45181257a0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27926
70066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2792670066
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.184541481
Short name T1976
Test name
Test status
Simulation time 1253677092 ps
CPU time 2.83 seconds
Started Jul 02 09:09:19 AM PDT 24
Finished Jul 02 09:09:23 AM PDT 24
Peak memory 206396 kb
Host smart-e0af17bd-fb14-452e-946b-e3e0d12943ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18454
1481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.184541481
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3874482162
Short name T100
Test name
Test status
Simulation time 8329000639 ps
CPU time 16.33 seconds
Started Jul 02 09:09:20 AM PDT 24
Finished Jul 02 09:09:38 AM PDT 24
Peak memory 206452 kb
Host smart-75eb811c-23a0-4f0f-891d-f3534a3b2693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38744
82162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3874482162
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3313199862
Short name T2038
Test name
Test status
Simulation time 374492318 ps
CPU time 1.2 seconds
Started Jul 02 09:09:24 AM PDT 24
Finished Jul 02 09:09:26 AM PDT 24
Peak memory 206168 kb
Host smart-3757fa98-06e4-4e3c-8fe2-f9b77dbb058d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33131
99862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3313199862
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1080757863
Short name T466
Test name
Test status
Simulation time 149673847 ps
CPU time 0.77 seconds
Started Jul 02 09:09:27 AM PDT 24
Finished Jul 02 09:09:30 AM PDT 24
Peak memory 206172 kb
Host smart-196d3892-f7c7-4397-8c9a-79923312e6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10807
57863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1080757863
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1363540961
Short name T1199
Test name
Test status
Simulation time 49805355 ps
CPU time 0.72 seconds
Started Jul 02 09:09:13 AM PDT 24
Finished Jul 02 09:09:16 AM PDT 24
Peak memory 206156 kb
Host smart-a7197816-d1ea-40dd-8610-54de9816ad34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13635
40961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1363540961
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.2066683927
Short name T741
Test name
Test status
Simulation time 1037473288 ps
CPU time 2.52 seconds
Started Jul 02 09:09:20 AM PDT 24
Finished Jul 02 09:09:24 AM PDT 24
Peak memory 206340 kb
Host smart-7e609021-54dd-47eb-93d3-bd07475ee40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20666
83927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2066683927
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1077869163
Short name T824
Test name
Test status
Simulation time 335231467 ps
CPU time 2.24 seconds
Started Jul 02 09:09:26 AM PDT 24
Finished Jul 02 09:09:29 AM PDT 24
Peak memory 206452 kb
Host smart-78075d86-9444-4fa4-9f31-2c38ff47b94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10778
69163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1077869163
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.307743753
Short name T1147
Test name
Test status
Simulation time 262078677 ps
CPU time 1.01 seconds
Started Jul 02 09:09:19 AM PDT 24
Finished Jul 02 09:09:21 AM PDT 24
Peak memory 206168 kb
Host smart-bfa0df60-2bf8-4380-84e6-7522d4ef79a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30774
3753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.307743753
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3951765278
Short name T2002
Test name
Test status
Simulation time 142497944 ps
CPU time 0.78 seconds
Started Jul 02 09:09:17 AM PDT 24
Finished Jul 02 09:09:20 AM PDT 24
Peak memory 206152 kb
Host smart-3bc14f21-6a1f-4a7e-bdd7-d0b720c67b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39517
65278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3951765278
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1062520286
Short name T2275
Test name
Test status
Simulation time 197482081 ps
CPU time 0.9 seconds
Started Jul 02 09:09:18 AM PDT 24
Finished Jul 02 09:09:20 AM PDT 24
Peak memory 206208 kb
Host smart-9f42c59c-acf5-4071-ab23-0a0b5596321b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10625
20286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1062520286
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.798069844
Short name T1751
Test name
Test status
Simulation time 173545498 ps
CPU time 0.89 seconds
Started Jul 02 09:09:22 AM PDT 24
Finished Jul 02 09:09:24 AM PDT 24
Peak memory 206208 kb
Host smart-5f6eb096-e728-4666-b8da-adc9dc1c82ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79806
9844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.798069844
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.1022229069
Short name T2465
Test name
Test status
Simulation time 23273607909 ps
CPU time 21.5 seconds
Started Jul 02 09:09:19 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206268 kb
Host smart-148ead2f-99d6-4e0a-a733-234b20bbd79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10222
29069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1022229069
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1182208398
Short name T1628
Test name
Test status
Simulation time 3328578832 ps
CPU time 4.25 seconds
Started Jul 02 09:09:22 AM PDT 24
Finished Jul 02 09:09:28 AM PDT 24
Peak memory 206272 kb
Host smart-afe849df-99b4-47bd-a132-d6923b295938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11822
08398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1182208398
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1813355174
Short name T1849
Test name
Test status
Simulation time 6739324876 ps
CPU time 191.13 seconds
Started Jul 02 09:09:20 AM PDT 24
Finished Jul 02 09:12:33 AM PDT 24
Peak memory 206532 kb
Host smart-c3b7996e-2d8b-4273-b8c3-1cd1939e72a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18133
55174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1813355174
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1002837353
Short name T1008
Test name
Test status
Simulation time 5191196929 ps
CPU time 38.19 seconds
Started Jul 02 09:09:19 AM PDT 24
Finished Jul 02 09:09:59 AM PDT 24
Peak memory 206504 kb
Host smart-28185e9a-40b6-402f-a5a8-45aa40aca0cf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1002837353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1002837353
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2571554750
Short name T109
Test name
Test status
Simulation time 271804762 ps
CPU time 1.02 seconds
Started Jul 02 09:09:30 AM PDT 24
Finished Jul 02 09:09:34 AM PDT 24
Peak memory 206176 kb
Host smart-3bbd16bb-536e-48f3-9745-ddd26a41b134
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2571554750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2571554750
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.4248654877
Short name T893
Test name
Test status
Simulation time 190226547 ps
CPU time 0.82 seconds
Started Jul 02 09:09:31 AM PDT 24
Finished Jul 02 09:09:34 AM PDT 24
Peak memory 206200 kb
Host smart-4152b79d-d020-4bdc-a3a2-c35dd2e8e3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42486
54877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.4248654877
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.3078150316
Short name T1516
Test name
Test status
Simulation time 6810482055 ps
CPU time 51.32 seconds
Started Jul 02 09:09:21 AM PDT 24
Finished Jul 02 09:10:14 AM PDT 24
Peak memory 206452 kb
Host smart-2c495c5e-a6ff-4243-b4e5-3d8516aa001c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30781
50316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.3078150316
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2309731230
Short name T1586
Test name
Test status
Simulation time 3526375298 ps
CPU time 23.9 seconds
Started Jul 02 09:09:24 AM PDT 24
Finished Jul 02 09:09:49 AM PDT 24
Peak memory 206408 kb
Host smart-d8d43b77-39df-42c0-a493-6c9535245c20
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2309731230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2309731230
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3096052339
Short name T2702
Test name
Test status
Simulation time 158904611 ps
CPU time 0.91 seconds
Started Jul 02 09:09:21 AM PDT 24
Finished Jul 02 09:09:23 AM PDT 24
Peak memory 206176 kb
Host smart-a7c0fdc2-069a-4cb4-8ff4-23c46c8c4027
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3096052339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3096052339
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2533460452
Short name T1267
Test name
Test status
Simulation time 150185731 ps
CPU time 0.77 seconds
Started Jul 02 09:09:17 AM PDT 24
Finished Jul 02 09:09:19 AM PDT 24
Peak memory 206128 kb
Host smart-1aded41b-4c8a-45a0-9953-e4e8464e1e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25334
60452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2533460452
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.1975458145
Short name T1274
Test name
Test status
Simulation time 214874619 ps
CPU time 0.86 seconds
Started Jul 02 09:09:17 AM PDT 24
Finished Jul 02 09:09:19 AM PDT 24
Peak memory 206192 kb
Host smart-2b5c820e-cbf0-4434-9167-d6847eb78e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
58145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1975458145
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2248448177
Short name T1578
Test name
Test status
Simulation time 191766154 ps
CPU time 0.85 seconds
Started Jul 02 09:09:20 AM PDT 24
Finished Jul 02 09:09:22 AM PDT 24
Peak memory 206176 kb
Host smart-fcd6e701-b9bc-49cf-9a9d-f16eb8d80675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22484
48177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2248448177
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3752827074
Short name T506
Test name
Test status
Simulation time 173641887 ps
CPU time 0.79 seconds
Started Jul 02 09:09:18 AM PDT 24
Finished Jul 02 09:09:20 AM PDT 24
Peak memory 206216 kb
Host smart-0fcc25c8-4d62-4d8d-91c8-97d544d7f2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37528
27074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3752827074
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1680777870
Short name T2487
Test name
Test status
Simulation time 171135336 ps
CPU time 0.86 seconds
Started Jul 02 09:09:22 AM PDT 24
Finished Jul 02 09:09:24 AM PDT 24
Peak memory 206212 kb
Host smart-3f47a582-d291-473a-9a66-18b1d5f74366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16807
77870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1680777870
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3450778359
Short name T579
Test name
Test status
Simulation time 203043681 ps
CPU time 0.9 seconds
Started Jul 02 09:09:21 AM PDT 24
Finished Jul 02 09:09:23 AM PDT 24
Peak memory 206108 kb
Host smart-3d027200-c0dc-4ca2-b4f5-a4561455dc25
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3450778359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3450778359
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.915158447
Short name T1882
Test name
Test status
Simulation time 141453048 ps
CPU time 0.79 seconds
Started Jul 02 09:09:27 AM PDT 24
Finished Jul 02 09:09:29 AM PDT 24
Peak memory 206192 kb
Host smart-0bb887d4-d714-430d-828d-25de3e9029d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91515
8447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.915158447
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.4036984637
Short name T2220
Test name
Test status
Simulation time 46508104 ps
CPU time 0.67 seconds
Started Jul 02 09:09:29 AM PDT 24
Finished Jul 02 09:09:33 AM PDT 24
Peak memory 206200 kb
Host smart-c0389a2e-1277-48d8-ad39-73bdaaaf70f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40369
84637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.4036984637
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.792721509
Short name T93
Test name
Test status
Simulation time 20988002358 ps
CPU time 48.64 seconds
Started Jul 02 09:09:33 AM PDT 24
Finished Jul 02 09:10:24 AM PDT 24
Peak memory 206472 kb
Host smart-37ce730f-9b99-433b-a861-0579d8a403a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79272
1509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.792721509
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.418142945
Short name T2102
Test name
Test status
Simulation time 208107114 ps
CPU time 0.85 seconds
Started Jul 02 09:09:32 AM PDT 24
Finished Jul 02 09:09:36 AM PDT 24
Peak memory 206200 kb
Host smart-2fd72726-87d2-4e54-9c1e-5c20c198f0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41814
2945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.418142945
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1901281125
Short name T2615
Test name
Test status
Simulation time 227651823 ps
CPU time 0.93 seconds
Started Jul 02 09:09:25 AM PDT 24
Finished Jul 02 09:09:28 AM PDT 24
Peak memory 206208 kb
Host smart-da1762dc-51cf-4ac8-96f8-5f8577fc9174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19012
81125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1901281125
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.2584951828
Short name T1649
Test name
Test status
Simulation time 261846527 ps
CPU time 0.95 seconds
Started Jul 02 09:09:22 AM PDT 24
Finished Jul 02 09:09:24 AM PDT 24
Peak memory 206208 kb
Host smart-fb0c213f-f211-41c3-b3ba-aee475b4a4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25849
51828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.2584951828
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.599248989
Short name T1692
Test name
Test status
Simulation time 165159654 ps
CPU time 0.84 seconds
Started Jul 02 09:09:26 AM PDT 24
Finished Jul 02 09:09:29 AM PDT 24
Peak memory 206196 kb
Host smart-54888bc9-486f-4bd4-aedb-d0c5a5fa779d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59924
8989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.599248989
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.4134869154
Short name T1272
Test name
Test status
Simulation time 147903726 ps
CPU time 0.77 seconds
Started Jul 02 09:09:37 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206196 kb
Host smart-2e70c4ec-f3cb-4b44-a6b3-3498f9e3c30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41348
69154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.4134869154
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1842687126
Short name T1927
Test name
Test status
Simulation time 164710949 ps
CPU time 0.84 seconds
Started Jul 02 09:09:27 AM PDT 24
Finished Jul 02 09:09:30 AM PDT 24
Peak memory 206212 kb
Host smart-11f78d81-90ac-4c42-b042-d5d0d544adc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18426
87126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1842687126
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1907346212
Short name T1492
Test name
Test status
Simulation time 270367863 ps
CPU time 1.04 seconds
Started Jul 02 09:09:38 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206196 kb
Host smart-919771ac-214d-404a-9ef8-94601404f731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19073
46212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1907346212
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.405641605
Short name T1260
Test name
Test status
Simulation time 5095008445 ps
CPU time 136.5 seconds
Started Jul 02 09:09:35 AM PDT 24
Finished Jul 02 09:11:55 AM PDT 24
Peak memory 206492 kb
Host smart-2ea3525e-b0d9-4f20-8525-a1e4173e9b83
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=405641605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.405641605
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1441036421
Short name T563
Test name
Test status
Simulation time 191210064 ps
CPU time 0.83 seconds
Started Jul 02 09:09:29 AM PDT 24
Finished Jul 02 09:09:33 AM PDT 24
Peak memory 206220 kb
Host smart-38c54fbd-e853-4c46-8cc0-e05730d2306a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14410
36421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1441036421
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3964593844
Short name T1047
Test name
Test status
Simulation time 151147971 ps
CPU time 0.79 seconds
Started Jul 02 09:09:38 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206196 kb
Host smart-647cf15e-8ace-4b92-b58d-c4bd61de5729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39645
93844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3964593844
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.4289943219
Short name T2417
Test name
Test status
Simulation time 951478732 ps
CPU time 2.21 seconds
Started Jul 02 09:09:24 AM PDT 24
Finished Jul 02 09:09:27 AM PDT 24
Peak memory 206428 kb
Host smart-bf73147e-153f-4de3-ab1d-6f476db0a0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42899
43219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.4289943219
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.1276500918
Short name T1815
Test name
Test status
Simulation time 6455406017 ps
CPU time 177.65 seconds
Started Jul 02 09:09:21 AM PDT 24
Finished Jul 02 09:12:20 AM PDT 24
Peak memory 206568 kb
Host smart-ff132244-8be4-417b-93d4-90c9c2851b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12765
00918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1276500918
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.1694528101
Short name T1418
Test name
Test status
Simulation time 42501186 ps
CPU time 0.67 seconds
Started Jul 02 09:09:29 AM PDT 24
Finished Jul 02 09:09:33 AM PDT 24
Peak memory 206240 kb
Host smart-6bef5fa5-ca99-4251-8191-fd6cfaf607bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1694528101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1694528101
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.553294128
Short name T1833
Test name
Test status
Simulation time 4400697851 ps
CPU time 4.89 seconds
Started Jul 02 09:09:23 AM PDT 24
Finished Jul 02 09:09:29 AM PDT 24
Peak memory 206208 kb
Host smart-d2a14306-725e-48f5-b811-b252c78b5486
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=553294128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.553294128
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1738228194
Short name T1296
Test name
Test status
Simulation time 13340045308 ps
CPU time 12.39 seconds
Started Jul 02 09:09:32 AM PDT 24
Finished Jul 02 09:09:47 AM PDT 24
Peak memory 206228 kb
Host smart-379c353e-bf53-4217-a7b6-e3cde1de9ccf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1738228194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1738228194
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1840561275
Short name T1252
Test name
Test status
Simulation time 23367324410 ps
CPU time 23.22 seconds
Started Jul 02 09:09:22 AM PDT 24
Finished Jul 02 09:09:46 AM PDT 24
Peak memory 206200 kb
Host smart-da4ebd91-972d-4700-8c3f-10faf59bd895
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1840561275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1840561275
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3660078019
Short name T575
Test name
Test status
Simulation time 153618909 ps
CPU time 0.8 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206184 kb
Host smart-a711aab8-68b0-40ed-8d98-4df62d7534d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36600
78019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3660078019
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.865267156
Short name T744
Test name
Test status
Simulation time 156159488 ps
CPU time 0.83 seconds
Started Jul 02 09:09:31 AM PDT 24
Finished Jul 02 09:09:34 AM PDT 24
Peak memory 206184 kb
Host smart-d1c3538d-1f59-4529-8ab5-f7464b01e613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86526
7156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.865267156
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3506897312
Short name T1856
Test name
Test status
Simulation time 476262792 ps
CPU time 1.61 seconds
Started Jul 02 09:09:35 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206196 kb
Host smart-6889702d-13bb-4ba6-86fe-d0a940445b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35068
97312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3506897312
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.4284521735
Short name T1133
Test name
Test status
Simulation time 347217330 ps
CPU time 0.99 seconds
Started Jul 02 09:09:29 AM PDT 24
Finished Jul 02 09:09:33 AM PDT 24
Peak memory 206188 kb
Host smart-765dc0e9-231a-4872-ba1d-0334ef95a7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42845
21735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.4284521735
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2772989215
Short name T1438
Test name
Test status
Simulation time 11583335339 ps
CPU time 22.86 seconds
Started Jul 02 09:09:30 AM PDT 24
Finished Jul 02 09:09:56 AM PDT 24
Peak memory 206524 kb
Host smart-074b8e30-8c8d-42c2-a337-0e19025d22de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27729
89215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2772989215
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.770091867
Short name T1271
Test name
Test status
Simulation time 447632377 ps
CPU time 1.35 seconds
Started Jul 02 09:09:29 AM PDT 24
Finished Jul 02 09:09:33 AM PDT 24
Peak memory 206192 kb
Host smart-c7118c2c-c1af-4b65-b91c-d497d79e7dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77009
1867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.770091867
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3639593965
Short name T940
Test name
Test status
Simulation time 138541553 ps
CPU time 0.8 seconds
Started Jul 02 09:09:33 AM PDT 24
Finished Jul 02 09:09:37 AM PDT 24
Peak memory 206216 kb
Host smart-23173c8a-4a60-4e38-b480-e0ca7636b683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36395
93965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3639593965
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2568366822
Short name T1039
Test name
Test status
Simulation time 65277939 ps
CPU time 0.68 seconds
Started Jul 02 09:09:26 AM PDT 24
Finished Jul 02 09:09:27 AM PDT 24
Peak memory 206204 kb
Host smart-ecc86d62-1278-4593-81c5-743a2b8f083c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25683
66822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2568366822
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3030213878
Short name T2080
Test name
Test status
Simulation time 883977857 ps
CPU time 2.11 seconds
Started Jul 02 09:09:32 AM PDT 24
Finished Jul 02 09:09:36 AM PDT 24
Peak memory 206472 kb
Host smart-999efca3-b2d6-4532-a2b3-3b7d91a8c4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
13878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3030213878
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2445596558
Short name T2215
Test name
Test status
Simulation time 363503817 ps
CPU time 2.43 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206464 kb
Host smart-83be7ab9-dad4-4dd2-a177-b5c6a215aa65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24455
96558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2445596558
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3985979423
Short name T28
Test name
Test status
Simulation time 161896006 ps
CPU time 0.79 seconds
Started Jul 02 09:09:35 AM PDT 24
Finished Jul 02 09:09:40 AM PDT 24
Peak memory 206228 kb
Host smart-e7d8eb40-6821-4e8b-8058-fa48e7750f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39859
79423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3985979423
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2640705627
Short name T2398
Test name
Test status
Simulation time 153304371 ps
CPU time 0.76 seconds
Started Jul 02 09:09:32 AM PDT 24
Finished Jul 02 09:09:36 AM PDT 24
Peak memory 206200 kb
Host smart-859386ba-4558-4fe6-95cc-2418ab552562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26407
05627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2640705627
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3238760213
Short name T2258
Test name
Test status
Simulation time 168817753 ps
CPU time 0.8 seconds
Started Jul 02 09:09:35 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206200 kb
Host smart-9ed84aba-606c-4343-b1ca-010e9a0454a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32387
60213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3238760213
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.3461538568
Short name T1798
Test name
Test status
Simulation time 6413396577 ps
CPU time 48.55 seconds
Started Jul 02 09:09:26 AM PDT 24
Finished Jul 02 09:10:15 AM PDT 24
Peak memory 206480 kb
Host smart-1729017e-f5d9-4776-ae74-748f096e79f7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3461538568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.3461538568
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2190478547
Short name T1852
Test name
Test status
Simulation time 197099202 ps
CPU time 0.81 seconds
Started Jul 02 09:09:41 AM PDT 24
Finished Jul 02 09:09:45 AM PDT 24
Peak memory 206160 kb
Host smart-59a683f4-11de-47d4-8b19-29095015844b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21904
78547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2190478547
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3532888580
Short name T1723
Test name
Test status
Simulation time 23286039797 ps
CPU time 22.05 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:10:02 AM PDT 24
Peak memory 206396 kb
Host smart-fd3f9113-f9d5-4209-b721-f5481caf1e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35328
88580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3532888580
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.266378632
Short name T1558
Test name
Test status
Simulation time 3267206812 ps
CPU time 3.81 seconds
Started Jul 02 09:09:28 AM PDT 24
Finished Jul 02 09:09:34 AM PDT 24
Peak memory 206196 kb
Host smart-57d6fcf6-dac1-4dfb-a0fc-605a3c5f3ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26637
8632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.266378632
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.4071614674
Short name T1507
Test name
Test status
Simulation time 8910039671 ps
CPU time 256.35 seconds
Started Jul 02 09:09:28 AM PDT 24
Finished Jul 02 09:13:47 AM PDT 24
Peak memory 206560 kb
Host smart-c0508f3e-d2b1-40f8-96c8-05396298fd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40716
14674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.4071614674
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.4031790263
Short name T1857
Test name
Test status
Simulation time 4102203630 ps
CPU time 36.4 seconds
Started Jul 02 09:09:31 AM PDT 24
Finished Jul 02 09:10:10 AM PDT 24
Peak memory 206508 kb
Host smart-4f735492-dba4-4b78-a309-81cfae9975a8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4031790263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.4031790263
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3435485479
Short name T1475
Test name
Test status
Simulation time 240445750 ps
CPU time 0.91 seconds
Started Jul 02 09:09:41 AM PDT 24
Finished Jul 02 09:09:45 AM PDT 24
Peak memory 206200 kb
Host smart-cc7e0453-e0f7-48b2-a91a-c3105d1c3b05
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3435485479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3435485479
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.618242328
Short name T1915
Test name
Test status
Simulation time 208843011 ps
CPU time 0.87 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206200 kb
Host smart-979f2064-ef15-4fc3-bbea-6c41c8335f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61824
2328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.618242328
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.33804808
Short name T1393
Test name
Test status
Simulation time 4135673077 ps
CPU time 40.28 seconds
Started Jul 02 09:09:30 AM PDT 24
Finished Jul 02 09:10:13 AM PDT 24
Peak memory 206424 kb
Host smart-15a8b6f4-c30d-4806-94ea-7978bb9cbfcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33804
808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.33804808
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1093430869
Short name T1397
Test name
Test status
Simulation time 4009644526 ps
CPU time 106.21 seconds
Started Jul 02 09:09:40 AM PDT 24
Finished Jul 02 09:11:30 AM PDT 24
Peak memory 206448 kb
Host smart-4f60b46a-a20f-403e-961b-e4caff115950
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1093430869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1093430869
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2716848559
Short name T1641
Test name
Test status
Simulation time 196869080 ps
CPU time 0.83 seconds
Started Jul 02 09:09:26 AM PDT 24
Finished Jul 02 09:09:28 AM PDT 24
Peak memory 206156 kb
Host smart-1c543f08-2ca1-4796-846b-624204a28329
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2716848559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2716848559
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3951608161
Short name T395
Test name
Test status
Simulation time 146613424 ps
CPU time 0.78 seconds
Started Jul 02 09:09:37 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206204 kb
Host smart-186152bf-34c3-45ff-b68b-d6759fa6dac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39516
08161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3951608161
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3036249083
Short name T2581
Test name
Test status
Simulation time 216805547 ps
CPU time 0.85 seconds
Started Jul 02 09:09:27 AM PDT 24
Finished Jul 02 09:09:29 AM PDT 24
Peak memory 206204 kb
Host smart-49d362e5-39a3-4dbb-9bcd-6797e1168ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30362
49083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3036249083
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.686853597
Short name T410
Test name
Test status
Simulation time 188495120 ps
CPU time 0.86 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206208 kb
Host smart-0dbcd23b-5cc6-43b9-846b-15fb7447bb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68685
3597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.686853597
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.90803691
Short name T1264
Test name
Test status
Simulation time 221248789 ps
CPU time 0.86 seconds
Started Jul 02 09:09:26 AM PDT 24
Finished Jul 02 09:09:29 AM PDT 24
Peak memory 206188 kb
Host smart-56cb9350-e3a2-4555-b3db-c8bc17ab475f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90803
691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.90803691
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.479505470
Short name T1262
Test name
Test status
Simulation time 174202189 ps
CPU time 0.79 seconds
Started Jul 02 09:09:35 AM PDT 24
Finished Jul 02 09:09:40 AM PDT 24
Peak memory 206204 kb
Host smart-01e5a3bc-fc94-42e1-8fc3-8d25a59abf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47950
5470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.479505470
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1131438257
Short name T1185
Test name
Test status
Simulation time 151781068 ps
CPU time 0.84 seconds
Started Jul 02 09:09:25 AM PDT 24
Finished Jul 02 09:09:28 AM PDT 24
Peak memory 206176 kb
Host smart-5ec65982-c893-4956-b902-6541342d9736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11314
38257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1131438257
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1636574870
Short name T1592
Test name
Test status
Simulation time 196627457 ps
CPU time 0.89 seconds
Started Jul 02 09:09:32 AM PDT 24
Finished Jul 02 09:09:35 AM PDT 24
Peak memory 206160 kb
Host smart-c981dda1-9916-4efe-a258-30866e4be73e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1636574870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1636574870
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2887122200
Short name T2651
Test name
Test status
Simulation time 185832878 ps
CPU time 0.8 seconds
Started Jul 02 09:09:35 AM PDT 24
Finished Jul 02 09:09:40 AM PDT 24
Peak memory 206204 kb
Host smart-66d66816-bf65-407f-86d7-85d3664fda1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28871
22200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2887122200
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3817043111
Short name T1541
Test name
Test status
Simulation time 32234678 ps
CPU time 0.64 seconds
Started Jul 02 09:09:25 AM PDT 24
Finished Jul 02 09:09:27 AM PDT 24
Peak memory 206192 kb
Host smart-a4bd07d5-df66-4443-9b6b-9d71ec4b6a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38170
43111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3817043111
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1090271839
Short name T877
Test name
Test status
Simulation time 11398775461 ps
CPU time 24.74 seconds
Started Jul 02 09:09:28 AM PDT 24
Finished Jul 02 09:09:55 AM PDT 24
Peak memory 206468 kb
Host smart-0e74fbbc-2bcf-4322-940f-cf996ce61a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10902
71839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1090271839
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3763053357
Short name T1174
Test name
Test status
Simulation time 234041685 ps
CPU time 0.96 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206180 kb
Host smart-0881222d-4aad-4934-946f-bd9e7dcebea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37630
53357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3763053357
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2875595977
Short name T1175
Test name
Test status
Simulation time 284488271 ps
CPU time 0.91 seconds
Started Jul 02 09:09:33 AM PDT 24
Finished Jul 02 09:09:36 AM PDT 24
Peak memory 206180 kb
Host smart-74eeaa33-86f7-45ae-b716-58aa4326ef41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755
95977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2875595977
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1694181881
Short name T443
Test name
Test status
Simulation time 172423168 ps
CPU time 0.78 seconds
Started Jul 02 09:09:30 AM PDT 24
Finished Jul 02 09:09:34 AM PDT 24
Peak memory 206212 kb
Host smart-f5a639f2-4e76-4ac4-8b5e-51c4163de2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16941
81881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1694181881
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1135080499
Short name T2410
Test name
Test status
Simulation time 262644044 ps
CPU time 0.93 seconds
Started Jul 02 09:09:31 AM PDT 24
Finished Jul 02 09:09:35 AM PDT 24
Peak memory 206212 kb
Host smart-ea50f47d-45ed-45bf-839f-5a4b9ed09d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11350
80499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1135080499
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1107598994
Short name T1878
Test name
Test status
Simulation time 174210995 ps
CPU time 0.78 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206204 kb
Host smart-15e54b42-8d2e-4975-b921-8e66fee99ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11075
98994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1107598994
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1440558835
Short name T1446
Test name
Test status
Simulation time 164002119 ps
CPU time 0.8 seconds
Started Jul 02 09:09:32 AM PDT 24
Finished Jul 02 09:09:35 AM PDT 24
Peak memory 206164 kb
Host smart-c3dd1c26-b477-43d0-9c2c-c56af73062eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14405
58835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1440558835
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2647647988
Short name T1650
Test name
Test status
Simulation time 177505699 ps
CPU time 0.79 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206356 kb
Host smart-35f96c40-d032-42fb-ba35-7d5a11cbebf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26476
47988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2647647988
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.67829214
Short name T1990
Test name
Test status
Simulation time 210956989 ps
CPU time 0.87 seconds
Started Jul 02 09:09:31 AM PDT 24
Finished Jul 02 09:09:35 AM PDT 24
Peak memory 206208 kb
Host smart-5f769b9a-5f09-4f97-9511-a7bc0a665b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67829
214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.67829214
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.2395096431
Short name T1523
Test name
Test status
Simulation time 3315100502 ps
CPU time 22.76 seconds
Started Jul 02 09:09:37 AM PDT 24
Finished Jul 02 09:10:04 AM PDT 24
Peak memory 206440 kb
Host smart-be83fc69-2601-4fe0-9ebd-b63466ed8d84
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2395096431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.2395096431
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1651068457
Short name T772
Test name
Test status
Simulation time 184546491 ps
CPU time 0.84 seconds
Started Jul 02 09:09:29 AM PDT 24
Finished Jul 02 09:09:33 AM PDT 24
Peak memory 206128 kb
Host smart-e04a3b83-11d7-4b1d-9d89-55d9e82dd951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16510
68457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1651068457
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1764172172
Short name T1671
Test name
Test status
Simulation time 188132450 ps
CPU time 0.87 seconds
Started Jul 02 09:09:30 AM PDT 24
Finished Jul 02 09:09:34 AM PDT 24
Peak memory 206168 kb
Host smart-b42eb114-1b00-4396-a0b9-84ab2cd763c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17641
72172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1764172172
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.4058749857
Short name T1245
Test name
Test status
Simulation time 820623024 ps
CPU time 2.09 seconds
Started Jul 02 09:09:33 AM PDT 24
Finished Jul 02 09:09:38 AM PDT 24
Peak memory 206420 kb
Host smart-85947244-ee91-49f5-bc6c-9c07bc6e9105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40587
49857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.4058749857
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.56572297
Short name T455
Test name
Test status
Simulation time 4401313161 ps
CPU time 118.17 seconds
Started Jul 02 09:09:37 AM PDT 24
Finished Jul 02 09:11:39 AM PDT 24
Peak memory 206516 kb
Host smart-28cbcae4-e552-4486-b958-decb88aeb167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56572
297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.56572297
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.585406759
Short name T2428
Test name
Test status
Simulation time 55634593 ps
CPU time 0.71 seconds
Started Jul 02 09:09:40 AM PDT 24
Finished Jul 02 09:09:44 AM PDT 24
Peak memory 206168 kb
Host smart-6a7e960d-2dcb-4fe9-80b4-8d2b7b06c28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=585406759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.585406759
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2863419292
Short name T16
Test name
Test status
Simulation time 4327738005 ps
CPU time 4.91 seconds
Started Jul 02 09:09:33 AM PDT 24
Finished Jul 02 09:09:40 AM PDT 24
Peak memory 206256 kb
Host smart-9cd7a7a1-314e-4a7f-bad4-6dcd3d8c4a9b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2863419292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.2863419292
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.826933262
Short name T1934
Test name
Test status
Simulation time 13359210195 ps
CPU time 11.89 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:09:59 AM PDT 24
Peak memory 206428 kb
Host smart-ea492205-124e-4b57-854f-8861eea4d6b3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=826933262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.826933262
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.4245804976
Short name T2236
Test name
Test status
Simulation time 23368487887 ps
CPU time 24.48 seconds
Started Jul 02 09:09:34 AM PDT 24
Finished Jul 02 09:10:02 AM PDT 24
Peak memory 206244 kb
Host smart-96d32518-bc08-450a-bca5-5754cbc55374
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4245804976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.4245804976
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2099829127
Short name T801
Test name
Test status
Simulation time 174558783 ps
CPU time 0.85 seconds
Started Jul 02 09:09:39 AM PDT 24
Finished Jul 02 09:09:44 AM PDT 24
Peak memory 206212 kb
Host smart-24de0e4c-0d5f-4e8f-aba4-9a881609e756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20998
29127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2099829127
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.4241923452
Short name T677
Test name
Test status
Simulation time 151041462 ps
CPU time 0.79 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206224 kb
Host smart-c5d5c7e6-302d-43d6-88dd-618e0b321d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42419
23452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.4241923452
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.3303560301
Short name T1635
Test name
Test status
Simulation time 318838711 ps
CPU time 1.15 seconds
Started Jul 02 09:09:34 AM PDT 24
Finished Jul 02 09:09:37 AM PDT 24
Peak memory 206204 kb
Host smart-7b8a7d29-1be4-4529-a3b9-28530c104d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33035
60301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.3303560301
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1414111974
Short name T1565
Test name
Test status
Simulation time 1373945543 ps
CPU time 2.88 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206412 kb
Host smart-cadee389-dae1-4e1e-a8e2-e010be90f3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14141
11974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1414111974
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.1748962636
Short name T1117
Test name
Test status
Simulation time 16711522082 ps
CPU time 33.24 seconds
Started Jul 02 09:09:34 AM PDT 24
Finished Jul 02 09:10:12 AM PDT 24
Peak memory 206440 kb
Host smart-f6c49cc1-9146-4750-bb76-805ada805dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17489
62636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1748962636
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.1620175258
Short name T963
Test name
Test status
Simulation time 487279601 ps
CPU time 1.41 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206204 kb
Host smart-bf1b7574-2e7a-47dc-a837-3386f2a0c0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16201
75258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.1620175258
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.3228938134
Short name T683
Test name
Test status
Simulation time 156315175 ps
CPU time 0.78 seconds
Started Jul 02 09:09:38 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206156 kb
Host smart-037bde75-21d3-466b-b643-e83f76d1f4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32289
38134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3228938134
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2282882017
Short name T966
Test name
Test status
Simulation time 50296485 ps
CPU time 0.7 seconds
Started Jul 02 09:09:38 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206180 kb
Host smart-6ef20ad9-cd10-4156-8a8a-3fd3ab755985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22828
82017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2282882017
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.3057962872
Short name T83
Test name
Test status
Simulation time 815056473 ps
CPU time 2.02 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:49 AM PDT 24
Peak memory 206360 kb
Host smart-3bfa5365-85bf-482b-b1b4-5100e49b7f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
62872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.3057962872
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3196633931
Short name T1571
Test name
Test status
Simulation time 326946950 ps
CPU time 1.53 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206380 kb
Host smart-fa692d1b-e865-41e2-b8f1-01f8b57f5f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31966
33931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3196633931
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2122914710
Short name T2440
Test name
Test status
Simulation time 216103197 ps
CPU time 0.84 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:09:47 AM PDT 24
Peak memory 206204 kb
Host smart-9135f05d-f554-4a53-bdc5-bc6bb48ed85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21229
14710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2122914710
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.34409654
Short name T903
Test name
Test status
Simulation time 137216337 ps
CPU time 0.78 seconds
Started Jul 02 09:09:33 AM PDT 24
Finished Jul 02 09:09:36 AM PDT 24
Peak memory 206156 kb
Host smart-3f038517-e416-49a2-b817-b603343e4c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34409
654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.34409654
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2273624619
Short name T927
Test name
Test status
Simulation time 226160976 ps
CPU time 0.93 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206140 kb
Host smart-dbe3daf6-231f-4c70-a0ad-d97c073b796c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22736
24619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2273624619
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.2116484423
Short name T1327
Test name
Test status
Simulation time 7289289956 ps
CPU time 75.68 seconds
Started Jul 02 09:09:35 AM PDT 24
Finished Jul 02 09:10:55 AM PDT 24
Peak memory 206416 kb
Host smart-5c86b167-698a-4ca8-a2e8-ff2c47b401fb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2116484423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.2116484423
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.134197566
Short name T1636
Test name
Test status
Simulation time 249680039 ps
CPU time 0.92 seconds
Started Jul 02 09:09:35 AM PDT 24
Finished Jul 02 09:09:39 AM PDT 24
Peak memory 206176 kb
Host smart-a254726f-7307-4b9c-8d3d-416e7e2d6f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13419
7566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.134197566
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2341550277
Short name T1827
Test name
Test status
Simulation time 23291140912 ps
CPU time 21.23 seconds
Started Jul 02 09:09:34 AM PDT 24
Finished Jul 02 09:10:00 AM PDT 24
Peak memory 206192 kb
Host smart-6e6a072f-3b23-42ee-b574-7ae428a136dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23415
50277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2341550277
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1213925788
Short name T912
Test name
Test status
Simulation time 3312137906 ps
CPU time 4.19 seconds
Started Jul 02 09:09:42 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 206264 kb
Host smart-03cdccbc-32e2-4c6c-8a3d-b31c005c5bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12139
25788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1213925788
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.2323470265
Short name T1468
Test name
Test status
Simulation time 10646560141 ps
CPU time 99.63 seconds
Started Jul 02 09:09:42 AM PDT 24
Finished Jul 02 09:11:25 AM PDT 24
Peak memory 206532 kb
Host smart-7f450b54-244e-44d7-ad1b-5e78e2012d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23234
70265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.2323470265
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1823234568
Short name T2212
Test name
Test status
Simulation time 3100319070 ps
CPU time 28.52 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:10:15 AM PDT 24
Peak memory 206480 kb
Host smart-6d3d9b17-e517-49d0-9776-2c728cb49000
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1823234568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1823234568
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3620267302
Short name T1918
Test name
Test status
Simulation time 290772924 ps
CPU time 0.93 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:41 AM PDT 24
Peak memory 206184 kb
Host smart-c3d90b38-d556-46d7-9ef4-df7bd952a5f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3620267302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3620267302
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3505067614
Short name T989
Test name
Test status
Simulation time 190918767 ps
CPU time 0.93 seconds
Started Jul 02 09:09:38 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206160 kb
Host smart-766f14ca-26f7-43db-b612-3a4ff3850fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35050
67614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3505067614
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.3443566620
Short name T1095
Test name
Test status
Simulation time 6800296322 ps
CPU time 66.65 seconds
Started Jul 02 09:09:38 AM PDT 24
Finished Jul 02 09:10:49 AM PDT 24
Peak memory 206496 kb
Host smart-c04dbff6-32bd-4404-a11e-f6baddf6fb9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34435
66620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.3443566620
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2975438122
Short name T1484
Test name
Test status
Simulation time 4471987944 ps
CPU time 126.56 seconds
Started Jul 02 09:09:39 AM PDT 24
Finished Jul 02 09:11:49 AM PDT 24
Peak memory 206484 kb
Host smart-753f9a65-5682-4569-a82c-3b73b8bd8a3a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2975438122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2975438122
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.3049575760
Short name T1032
Test name
Test status
Simulation time 219061160 ps
CPU time 0.87 seconds
Started Jul 02 09:09:39 AM PDT 24
Finished Jul 02 09:09:44 AM PDT 24
Peak memory 206192 kb
Host smart-07e3ef3e-a458-40c6-83a8-860d2323e305
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3049575760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.3049575760
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.228507878
Short name T911
Test name
Test status
Simulation time 196482721 ps
CPU time 0.82 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:09:47 AM PDT 24
Peak memory 206132 kb
Host smart-07dec66c-6dd7-4700-b95b-5c7a2949b50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22850
7878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.228507878
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.172414073
Short name T103
Test name
Test status
Simulation time 184584560 ps
CPU time 0.83 seconds
Started Jul 02 09:09:33 AM PDT 24
Finished Jul 02 09:09:36 AM PDT 24
Peak memory 206216 kb
Host smart-39236544-c55a-40a3-b3a4-438e5479535f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17241
4073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.172414073
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2307202937
Short name T1826
Test name
Test status
Simulation time 226411114 ps
CPU time 0.95 seconds
Started Jul 02 09:09:36 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206196 kb
Host smart-b4a27705-a012-47c8-a7c6-fcb383006ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23072
02937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2307202937
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1458830766
Short name T1030
Test name
Test status
Simulation time 143804137 ps
CPU time 0.76 seconds
Started Jul 02 09:09:35 AM PDT 24
Finished Jul 02 09:09:40 AM PDT 24
Peak memory 206120 kb
Host smart-ed21d8a7-8888-49ae-a4f6-bdc5c41d0a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14588
30766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1458830766
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1526693961
Short name T180
Test name
Test status
Simulation time 173626244 ps
CPU time 0.81 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206212 kb
Host smart-a5b4d99d-6305-4008-a48b-7898d37eb318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15266
93961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1526693961
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1988027843
Short name T2673
Test name
Test status
Simulation time 234409522 ps
CPU time 0.95 seconds
Started Jul 02 09:09:40 AM PDT 24
Finished Jul 02 09:09:44 AM PDT 24
Peak memory 206368 kb
Host smart-3d73ef7b-188c-4b94-a5a2-0b52dd8d96d3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1988027843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1988027843
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3700252131
Short name T1313
Test name
Test status
Simulation time 181351019 ps
CPU time 0.83 seconds
Started Jul 02 09:09:40 AM PDT 24
Finished Jul 02 09:09:45 AM PDT 24
Peak memory 206160 kb
Host smart-b553be06-1d9d-4e9e-b0f3-75b311f2c454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37002
52131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3700252131
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.78187978
Short name T26
Test name
Test status
Simulation time 38796642 ps
CPU time 0.65 seconds
Started Jul 02 09:09:47 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 206136 kb
Host smart-f9f3e0a2-3e35-4527-9b5c-de99029069be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78187
978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.78187978
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.4123784710
Short name T1747
Test name
Test status
Simulation time 22355243300 ps
CPU time 50.24 seconds
Started Jul 02 09:09:38 AM PDT 24
Finished Jul 02 09:10:32 AM PDT 24
Peak memory 206528 kb
Host smart-695554d5-5588-45f7-8cb6-80b00077fd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41237
84710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.4123784710
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.843719809
Short name T2231
Test name
Test status
Simulation time 158579910 ps
CPU time 0.78 seconds
Started Jul 02 09:09:37 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206216 kb
Host smart-8d915a1a-b89a-4777-b175-bb3ebd444dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84371
9809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.843719809
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.977783958
Short name T1623
Test name
Test status
Simulation time 259595959 ps
CPU time 0.92 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 205724 kb
Host smart-8ee1f33d-9391-4086-970a-8167e791d79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97778
3958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.977783958
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.23557417
Short name T1544
Test name
Test status
Simulation time 224615349 ps
CPU time 0.85 seconds
Started Jul 02 09:09:45 AM PDT 24
Finished Jul 02 09:09:49 AM PDT 24
Peak memory 206192 kb
Host smart-0562d802-b051-4ec9-b9a2-4927cb14b4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23557
417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.23557417
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.407978256
Short name T471
Test name
Test status
Simulation time 170325281 ps
CPU time 0.88 seconds
Started Jul 02 09:09:39 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206180 kb
Host smart-93ad807b-9350-4787-9c74-eda192d45a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40797
8256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.407978256
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2817181637
Short name T96
Test name
Test status
Simulation time 143970632 ps
CPU time 0.75 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 205812 kb
Host smart-94f56588-33b7-47cc-beaf-4fa1199fa062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171
81637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2817181637
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1621993173
Short name T2278
Test name
Test status
Simulation time 158637339 ps
CPU time 0.82 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:47 AM PDT 24
Peak memory 206184 kb
Host smart-3405ca0a-8f2f-4deb-b188-2e96a9303c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16219
93173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1621993173
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.4211080327
Short name T361
Test name
Test status
Simulation time 253347760 ps
CPU time 0.89 seconds
Started Jul 02 09:09:39 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206184 kb
Host smart-808c6d9a-727c-4ca0-826b-32aceb1645e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42110
80327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.4211080327
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3659205808
Short name T1431
Test name
Test status
Simulation time 231746911 ps
CPU time 1.03 seconds
Started Jul 02 09:09:38 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206176 kb
Host smart-f0291e51-9d87-4b13-8963-1130db16e9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36592
05808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3659205808
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.988408232
Short name T773
Test name
Test status
Simulation time 7298620166 ps
CPU time 51.52 seconds
Started Jul 02 09:09:40 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206452 kb
Host smart-e718fdd0-935a-4b84-bacd-c73f79b2e1e7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=988408232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.988408232
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.4027437604
Short name T421
Test name
Test status
Simulation time 176183655 ps
CPU time 0.82 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206140 kb
Host smart-8ca02ff5-7633-47c1-8547-7d312ac19c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40274
37604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.4027437604
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3312767985
Short name T2136
Test name
Test status
Simulation time 275764132 ps
CPU time 0.93 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206180 kb
Host smart-495afdab-5f4a-4aee-9175-34054ca48c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33127
67985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3312767985
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.1717861045
Short name T29
Test name
Test status
Simulation time 197426407 ps
CPU time 0.95 seconds
Started Jul 02 09:09:39 AM PDT 24
Finished Jul 02 09:09:44 AM PDT 24
Peak memory 206180 kb
Host smart-a1542e17-36c8-4845-bf19-ffddf15516ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17178
61045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.1717861045
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2821921602
Short name T2377
Test name
Test status
Simulation time 7188458483 ps
CPU time 191.25 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206452 kb
Host smart-58c5821c-a31f-4b72-8809-d435d515de2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28219
21602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2821921602
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3757927999
Short name T2618
Test name
Test status
Simulation time 41721482 ps
CPU time 0.72 seconds
Started Jul 02 09:09:49 AM PDT 24
Finished Jul 02 09:09:52 AM PDT 24
Peak memory 206184 kb
Host smart-8e5e7a97-9114-4004-8942-acb292f9364a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3757927999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3757927999
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.42317837
Short name T621
Test name
Test status
Simulation time 4429935506 ps
CPU time 5.29 seconds
Started Jul 02 09:09:39 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206252 kb
Host smart-369274ce-d2eb-47be-82b0-b41a10a5f72b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=42317837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.42317837
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1244055724
Short name T2149
Test name
Test status
Simulation time 13345948083 ps
CPU time 14.95 seconds
Started Jul 02 09:09:42 AM PDT 24
Finished Jul 02 09:10:00 AM PDT 24
Peak memory 206160 kb
Host smart-b39183c2-1b00-499c-8fb0-9b7f10c97b44
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1244055724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1244055724
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1762317832
Short name T868
Test name
Test status
Simulation time 23370910651 ps
CPU time 21.44 seconds
Started Jul 02 09:09:52 AM PDT 24
Finished Jul 02 09:10:15 AM PDT 24
Peak memory 206536 kb
Host smart-a6de88b0-4efe-41fc-95f2-cdff54d40cd1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1762317832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.1762317832
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3117343735
Short name T925
Test name
Test status
Simulation time 177132692 ps
CPU time 0.8 seconds
Started Jul 02 09:09:39 AM PDT 24
Finished Jul 02 09:09:44 AM PDT 24
Peak memory 206220 kb
Host smart-35055567-ad3d-4597-98ce-cbe8df4e922d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31173
43735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3117343735
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2733318272
Short name T1370
Test name
Test status
Simulation time 143043098 ps
CPU time 0.76 seconds
Started Jul 02 09:09:45 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206184 kb
Host smart-4a4ef9b8-6006-4f26-bd61-51e3a218356b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27333
18272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2733318272
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1332132943
Short name T1217
Test name
Test status
Simulation time 328870047 ps
CPU time 1.26 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:49 AM PDT 24
Peak memory 206208 kb
Host smart-9c7c2301-78db-4b20-8f19-8c75ba552ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13321
32943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1332132943
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3774970166
Short name T1568
Test name
Test status
Simulation time 1458195420 ps
CPU time 3.32 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:09:49 AM PDT 24
Peak memory 206396 kb
Host smart-49d3f890-85fc-46c4-9f5b-425b181e8233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37749
70166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3774970166
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3654776583
Short name T1001
Test name
Test status
Simulation time 21584230004 ps
CPU time 37.06 seconds
Started Jul 02 09:09:47 AM PDT 24
Finished Jul 02 09:10:27 AM PDT 24
Peak memory 206424 kb
Host smart-9ba4d975-8e3a-4781-8171-c204332eb4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36547
76583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3654776583
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2736195425
Short name T1520
Test name
Test status
Simulation time 396535284 ps
CPU time 1.3 seconds
Started Jul 02 09:09:41 AM PDT 24
Finished Jul 02 09:09:46 AM PDT 24
Peak memory 206176 kb
Host smart-da280011-a2ad-43ca-9047-d979bd3a2335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27361
95425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2736195425
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.338225493
Short name T1057
Test name
Test status
Simulation time 188037530 ps
CPU time 0.79 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206212 kb
Host smart-8c9f6fee-95e9-4552-8466-ef4172beef68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33822
5493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.338225493
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.3793521991
Short name T1828
Test name
Test status
Simulation time 67114906 ps
CPU time 0.69 seconds
Started Jul 02 09:09:49 AM PDT 24
Finished Jul 02 09:09:52 AM PDT 24
Peak memory 206140 kb
Host smart-5756914a-6de2-4881-bcdb-1cea8c3cff4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37935
21991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3793521991
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.3757532073
Short name T898
Test name
Test status
Simulation time 778680491 ps
CPU time 1.9 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206588 kb
Host smart-67175d1d-acb7-4d48-bcbd-831c6026eb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37575
32073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.3757532073
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2123058003
Short name T2034
Test name
Test status
Simulation time 244716908 ps
CPU time 1.39 seconds
Started Jul 02 09:09:45 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 206352 kb
Host smart-e6c482fb-f9c7-4570-a0ec-7575667b69cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21230
58003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2123058003
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.65375017
Short name T1359
Test name
Test status
Simulation time 197535474 ps
CPU time 0.91 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:09:47 AM PDT 24
Peak memory 206208 kb
Host smart-16a3b666-8769-4454-862e-ba16bb1474bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65375
017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.65375017
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3174696380
Short name T976
Test name
Test status
Simulation time 151558697 ps
CPU time 0.76 seconds
Started Jul 02 09:09:47 AM PDT 24
Finished Jul 02 09:09:51 AM PDT 24
Peak memory 206136 kb
Host smart-7f727f27-7914-4bd8-8cad-5922486c0666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31746
96380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3174696380
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2820810000
Short name T1265
Test name
Test status
Simulation time 168886954 ps
CPU time 0.83 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:09:47 AM PDT 24
Peak memory 206124 kb
Host smart-ce819dd2-8e1e-4d28-8867-20a503cab33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28208
10000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2820810000
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2840321826
Short name T2407
Test name
Test status
Simulation time 164445391 ps
CPU time 0.84 seconds
Started Jul 02 09:09:42 AM PDT 24
Finished Jul 02 09:09:46 AM PDT 24
Peak memory 206224 kb
Host smart-49648b9a-e75f-42db-adff-6eb227307a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28403
21826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2840321826
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.2748894124
Short name T2611
Test name
Test status
Simulation time 23322854511 ps
CPU time 23.86 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:10:10 AM PDT 24
Peak memory 206220 kb
Host smart-0d2d8011-baff-4724-b274-d2f7d07915ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27488
94124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.2748894124
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.3465046165
Short name T2098
Test name
Test status
Simulation time 3336282758 ps
CPU time 3.5 seconds
Started Jul 02 09:09:47 AM PDT 24
Finished Jul 02 09:09:53 AM PDT 24
Peak memory 206248 kb
Host smart-578e43b3-c7eb-4319-8d3a-d153206b70d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34650
46165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3465046165
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.3918202383
Short name T1210
Test name
Test status
Simulation time 7615137974 ps
CPU time 212.6 seconds
Started Jul 02 09:09:48 AM PDT 24
Finished Jul 02 09:13:23 AM PDT 24
Peak memory 206516 kb
Host smart-093b550a-0971-40c6-948d-c186c2dace9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39182
02383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.3918202383
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.3297305727
Short name T1423
Test name
Test status
Simulation time 5162582969 ps
CPU time 50.02 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:10:36 AM PDT 24
Peak memory 206492 kb
Host smart-48cc6ac7-92dd-4f80-89b9-db3a3f07f37f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3297305727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.3297305727
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3666355614
Short name T1013
Test name
Test status
Simulation time 245047053 ps
CPU time 0.99 seconds
Started Jul 02 09:09:41 AM PDT 24
Finished Jul 02 09:09:46 AM PDT 24
Peak memory 206156 kb
Host smart-c129ac70-29e9-4139-b046-540a3dcf566e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3666355614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3666355614
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3406902021
Short name T2591
Test name
Test status
Simulation time 198882062 ps
CPU time 0.94 seconds
Started Jul 02 09:09:42 AM PDT 24
Finished Jul 02 09:09:46 AM PDT 24
Peak memory 206184 kb
Host smart-b373b181-9a93-475a-9b6c-2d841dd121a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
02021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3406902021
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.2702984780
Short name T592
Test name
Test status
Simulation time 4805613092 ps
CPU time 128.84 seconds
Started Jul 02 09:09:45 AM PDT 24
Finished Jul 02 09:11:57 AM PDT 24
Peak memory 206380 kb
Host smart-b8a94f55-3bf2-4db3-8909-9ba88f3207f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27029
84780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.2702984780
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.1042472823
Short name T1788
Test name
Test status
Simulation time 4099156368 ps
CPU time 109.76 seconds
Started Jul 02 09:09:43 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206428 kb
Host smart-feb8df74-a27a-4ff7-915e-3e76f6854c88
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1042472823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1042472823
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.4001829524
Short name T774
Test name
Test status
Simulation time 158717150 ps
CPU time 0.86 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206184 kb
Host smart-8dd76934-c0ca-4a8b-9bc8-f8b3941227ea
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4001829524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.4001829524
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3304314329
Short name T22
Test name
Test status
Simulation time 152658594 ps
CPU time 0.76 seconds
Started Jul 02 09:09:45 AM PDT 24
Finished Jul 02 09:09:49 AM PDT 24
Peak memory 206228 kb
Host smart-495d941d-d93d-478b-9f05-2e7460ec80d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33043
14329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3304314329
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1921537739
Short name T140
Test name
Test status
Simulation time 208074642 ps
CPU time 0.88 seconds
Started Jul 02 09:09:45 AM PDT 24
Finished Jul 02 09:09:49 AM PDT 24
Peak memory 206340 kb
Host smart-789546da-77d2-4e63-95ec-95314ea57646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
37739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1921537739
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.1845222283
Short name T2170
Test name
Test status
Simulation time 190819888 ps
CPU time 0.85 seconds
Started Jul 02 09:09:45 AM PDT 24
Finished Jul 02 09:09:49 AM PDT 24
Peak memory 206212 kb
Host smart-b5f5b81c-ab04-4b85-aeac-4b4d8d5cd200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18452
22283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1845222283
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1985728369
Short name T1626
Test name
Test status
Simulation time 208787022 ps
CPU time 0.82 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:48 AM PDT 24
Peak memory 206208 kb
Host smart-6c47405f-34e0-4dc3-814a-1c2f09e2207e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19857
28369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1985728369
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2019478191
Short name T837
Test name
Test status
Simulation time 179975303 ps
CPU time 0.79 seconds
Started Jul 02 09:09:44 AM PDT 24
Finished Jul 02 09:09:47 AM PDT 24
Peak memory 206120 kb
Host smart-a69f888f-42c0-487b-915a-c5d5fdc7cc49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20194
78191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2019478191
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.4228665819
Short name T201
Test name
Test status
Simulation time 154470544 ps
CPU time 0.8 seconds
Started Jul 02 09:09:47 AM PDT 24
Finished Jul 02 09:09:51 AM PDT 24
Peak memory 206196 kb
Host smart-8c6712e9-7273-4cb2-a9e3-c3c35ebbf772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42286
65819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.4228665819
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1849687932
Short name T502
Test name
Test status
Simulation time 268001468 ps
CPU time 0.93 seconds
Started Jul 02 09:09:51 AM PDT 24
Finished Jul 02 09:09:54 AM PDT 24
Peak memory 206192 kb
Host smart-17d47edc-8245-49d7-af15-40cf405f6894
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1849687932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1849687932
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3850213288
Short name T2267
Test name
Test status
Simulation time 141545150 ps
CPU time 0.8 seconds
Started Jul 02 09:09:45 AM PDT 24
Finished Jul 02 09:09:49 AM PDT 24
Peak memory 206224 kb
Host smart-3caab823-017f-4b0f-a203-34e13e5237df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38502
13288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3850213288
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2456036889
Short name T1063
Test name
Test status
Simulation time 37091445 ps
CPU time 0.64 seconds
Started Jul 02 09:09:56 AM PDT 24
Finished Jul 02 09:09:59 AM PDT 24
Peak memory 206200 kb
Host smart-ac0ee5fb-d9e6-4547-ab91-c484dad8b1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24560
36889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2456036889
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3727436441
Short name T1241
Test name
Test status
Simulation time 10809367527 ps
CPU time 26.85 seconds
Started Jul 02 09:09:48 AM PDT 24
Finished Jul 02 09:10:18 AM PDT 24
Peak memory 206456 kb
Host smart-90424b44-6db3-42f5-9095-a93ca6971aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37274
36441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3727436441
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1224833889
Short name T1912
Test name
Test status
Simulation time 188606046 ps
CPU time 0.97 seconds
Started Jul 02 09:09:46 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 206168 kb
Host smart-0d8f7d18-50bb-4239-8cc1-2207d09aac4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12248
33889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1224833889
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2278047975
Short name T1183
Test name
Test status
Simulation time 248887356 ps
CPU time 0.96 seconds
Started Jul 02 09:09:46 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 206188 kb
Host smart-c5365b31-e0ca-42ee-8eac-7290469042c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22780
47975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2278047975
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.189435939
Short name T776
Test name
Test status
Simulation time 247094495 ps
CPU time 0.93 seconds
Started Jul 02 09:09:49 AM PDT 24
Finished Jul 02 09:09:52 AM PDT 24
Peak memory 206200 kb
Host smart-270c4ad4-362b-4937-8777-4e8f9772e9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18943
5939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.189435939
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2368089982
Short name T2643
Test name
Test status
Simulation time 183368053 ps
CPU time 0.88 seconds
Started Jul 02 09:09:46 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 206212 kb
Host smart-ab964e87-c09a-4e0f-bc25-5dc3d12dcec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23680
89982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2368089982
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3486717373
Short name T2518
Test name
Test status
Simulation time 147788517 ps
CPU time 0.77 seconds
Started Jul 02 09:09:49 AM PDT 24
Finished Jul 02 09:09:52 AM PDT 24
Peak memory 206136 kb
Host smart-f6a9b4ba-f2d1-42a5-9a47-03f0a0db5dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34867
17373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3486717373
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1319045503
Short name T645
Test name
Test status
Simulation time 161795984 ps
CPU time 0.79 seconds
Started Jul 02 09:09:46 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 206168 kb
Host smart-5c80b4a6-cf5a-485e-a89c-d00ab35c8559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13190
45503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1319045503
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2255586178
Short name T586
Test name
Test status
Simulation time 144852245 ps
CPU time 0.81 seconds
Started Jul 02 09:09:48 AM PDT 24
Finished Jul 02 09:09:52 AM PDT 24
Peak memory 206208 kb
Host smart-01bdff2c-71d0-46d0-9cf6-23f6370dc250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22555
86178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2255586178
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.281670981
Short name T1673
Test name
Test status
Simulation time 253445754 ps
CPU time 0.91 seconds
Started Jul 02 09:09:49 AM PDT 24
Finished Jul 02 09:09:52 AM PDT 24
Peak memory 206188 kb
Host smart-b04bcc1e-eeca-4970-aa27-80eb6bd7eaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28167
0981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.281670981
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3708968473
Short name T1464
Test name
Test status
Simulation time 4915761021 ps
CPU time 130.57 seconds
Started Jul 02 09:09:51 AM PDT 24
Finished Jul 02 09:12:04 AM PDT 24
Peak memory 206520 kb
Host smart-aecec493-2ce9-45a9-893b-626f5299220c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3708968473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3708968473
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3007608593
Short name T425
Test name
Test status
Simulation time 240102421 ps
CPU time 0.85 seconds
Started Jul 02 09:09:48 AM PDT 24
Finished Jul 02 09:09:51 AM PDT 24
Peak memory 206208 kb
Host smart-1ca3ac6e-a763-4e33-a36f-2ad6dfeed63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30076
08593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3007608593
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3420975831
Short name T991
Test name
Test status
Simulation time 178100521 ps
CPU time 0.92 seconds
Started Jul 02 09:09:49 AM PDT 24
Finished Jul 02 09:09:52 AM PDT 24
Peak memory 206128 kb
Host smart-4aaef739-6233-438a-91c8-0c6b0482c692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34209
75831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3420975831
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1025080159
Short name T2682
Test name
Test status
Simulation time 1157891190 ps
CPU time 2.43 seconds
Started Jul 02 09:09:55 AM PDT 24
Finished Jul 02 09:09:59 AM PDT 24
Peak memory 206236 kb
Host smart-6bda5bb4-b543-4c86-b326-b6432d883099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10250
80159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1025080159
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3757808205
Short name T2140
Test name
Test status
Simulation time 5288559366 ps
CPU time 151.25 seconds
Started Jul 02 09:09:50 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206532 kb
Host smart-2fb2e80c-5180-4ac2-9cae-bc23f866e3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37578
08205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3757808205
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2097956046
Short name T2703
Test name
Test status
Simulation time 101564539 ps
CPU time 0.74 seconds
Started Jul 02 09:09:56 AM PDT 24
Finished Jul 02 09:09:59 AM PDT 24
Peak memory 206256 kb
Host smart-4e663226-7196-4a7b-9da2-f3a1819aae76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2097956046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2097956046
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1616963040
Short name T2055
Test name
Test status
Simulation time 3924410465 ps
CPU time 5.04 seconds
Started Jul 02 09:09:59 AM PDT 24
Finished Jul 02 09:10:05 AM PDT 24
Peak memory 206276 kb
Host smart-fd306488-90da-4e9a-b13b-c39621d54509
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1616963040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.1616963040
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2586927110
Short name T2648
Test name
Test status
Simulation time 13391302273 ps
CPU time 15.84 seconds
Started Jul 02 09:09:54 AM PDT 24
Finished Jul 02 09:10:11 AM PDT 24
Peak memory 206216 kb
Host smart-5f179bc2-d75f-449e-9a15-19439a1e6e93
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2586927110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2586927110
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.4170502384
Short name T1832
Test name
Test status
Simulation time 23320738967 ps
CPU time 23.05 seconds
Started Jul 02 09:09:55 AM PDT 24
Finished Jul 02 09:10:20 AM PDT 24
Peak memory 206204 kb
Host smart-2d440af2-eaa3-4012-bb3e-3f86655afebb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4170502384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.4170502384
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.598238895
Short name T1959
Test name
Test status
Simulation time 164440381 ps
CPU time 0.8 seconds
Started Jul 02 09:09:55 AM PDT 24
Finished Jul 02 09:09:58 AM PDT 24
Peak memory 206168 kb
Host smart-37c8740a-991f-46fc-a6b0-fd4c86ee41ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59823
8895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.598238895
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2217585675
Short name T522
Test name
Test status
Simulation time 148010389 ps
CPU time 0.78 seconds
Started Jul 02 09:09:55 AM PDT 24
Finished Jul 02 09:09:58 AM PDT 24
Peak memory 206016 kb
Host smart-15256a1a-b00f-42ba-b225-4e7eb44bfdbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22175
85675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2217585675
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.3723797952
Short name T2386
Test name
Test status
Simulation time 431474851 ps
CPU time 1.4 seconds
Started Jul 02 09:09:51 AM PDT 24
Finished Jul 02 09:09:54 AM PDT 24
Peak memory 206184 kb
Host smart-6d21ff6a-1fce-4eea-b9ad-3fbfb3975420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37237
97952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3723797952
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2279121252
Short name T2054
Test name
Test status
Simulation time 420169176 ps
CPU time 1.19 seconds
Started Jul 02 09:09:48 AM PDT 24
Finished Jul 02 09:09:52 AM PDT 24
Peak memory 206184 kb
Host smart-1b0d67c9-ef2a-4aca-82c1-feb94a0b65ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22791
21252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2279121252
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.2831054815
Short name T944
Test name
Test status
Simulation time 11301666446 ps
CPU time 20.78 seconds
Started Jul 02 09:09:47 AM PDT 24
Finished Jul 02 09:10:11 AM PDT 24
Peak memory 206524 kb
Host smart-29339fd8-839f-4bdc-b480-ce79522d0802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28310
54815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.2831054815
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1314215285
Short name T1935
Test name
Test status
Simulation time 452210463 ps
CPU time 1.39 seconds
Started Jul 02 09:09:48 AM PDT 24
Finished Jul 02 09:09:52 AM PDT 24
Peak memory 206216 kb
Host smart-9f2a25f5-2115-4e4a-8c11-08a95a24a792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13142
15285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1314215285
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_enable.2908891400
Short name T2059
Test name
Test status
Simulation time 34841352 ps
CPU time 0.68 seconds
Started Jul 02 09:09:46 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 206188 kb
Host smart-7f8d99c1-258e-4c9f-ac0d-ed0485698c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29088
91400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2908891400
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.2268306012
Short name T1225
Test name
Test status
Simulation time 902856733 ps
CPU time 2.19 seconds
Started Jul 02 09:09:49 AM PDT 24
Finished Jul 02 09:09:54 AM PDT 24
Peak memory 206424 kb
Host smart-94bf2513-327c-491e-8654-d58a7201ee07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22683
06012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.2268306012
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2005735243
Short name T2286
Test name
Test status
Simulation time 325234197 ps
CPU time 2.18 seconds
Started Jul 02 09:09:54 AM PDT 24
Finished Jul 02 09:09:58 AM PDT 24
Peak memory 206264 kb
Host smart-42fb72fd-9506-4f38-bbad-0b6f42d2e591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20057
35243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2005735243
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1532255129
Short name T1472
Test name
Test status
Simulation time 170769848 ps
CPU time 0.83 seconds
Started Jul 02 09:09:52 AM PDT 24
Finished Jul 02 09:09:55 AM PDT 24
Peak memory 206216 kb
Host smart-e71f5dfa-812d-4ebe-a12b-5ebabd9d79e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15322
55129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1532255129
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2676747026
Short name T1593
Test name
Test status
Simulation time 171616302 ps
CPU time 0.79 seconds
Started Jul 02 09:09:52 AM PDT 24
Finished Jul 02 09:09:55 AM PDT 24
Peak memory 206072 kb
Host smart-d86d59aa-be76-4346-9c96-5ef2f4d9f52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26767
47026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2676747026
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1369241260
Short name T2078
Test name
Test status
Simulation time 241191663 ps
CPU time 1.02 seconds
Started Jul 02 09:09:52 AM PDT 24
Finished Jul 02 09:09:55 AM PDT 24
Peak memory 206076 kb
Host smart-4f520808-4eff-431c-8ed0-32a0ceba7d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13692
41260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1369241260
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.3276391633
Short name T2126
Test name
Test status
Simulation time 7705237409 ps
CPU time 70.23 seconds
Started Jul 02 09:09:51 AM PDT 24
Finished Jul 02 09:11:03 AM PDT 24
Peak memory 206440 kb
Host smart-a00d5c32-7bd6-4df5-934a-26463e32af9e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3276391633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.3276391633
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2831770295
Short name T701
Test name
Test status
Simulation time 192228177 ps
CPU time 0.84 seconds
Started Jul 02 09:09:52 AM PDT 24
Finished Jul 02 09:09:55 AM PDT 24
Peak memory 206212 kb
Host smart-d6cb846a-0bb3-41a0-9e52-044343a665c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28317
70295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2831770295
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.4279825936
Short name T1545
Test name
Test status
Simulation time 23353794199 ps
CPU time 28.55 seconds
Started Jul 02 09:09:51 AM PDT 24
Finished Jul 02 09:10:22 AM PDT 24
Peak memory 206276 kb
Host smart-29d6931c-bdfa-4cf7-91d0-d091a4b6d9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42798
25936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.4279825936
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2268366433
Short name T1584
Test name
Test status
Simulation time 3322624915 ps
CPU time 3.54 seconds
Started Jul 02 09:09:50 AM PDT 24
Finished Jul 02 09:09:56 AM PDT 24
Peak memory 206268 kb
Host smart-bfc2b4bd-2529-4d87-b893-374a63b16863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22683
66433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2268366433
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.731804783
Short name T999
Test name
Test status
Simulation time 9411793134 ps
CPU time 255.86 seconds
Started Jul 02 09:09:53 AM PDT 24
Finished Jul 02 09:14:11 AM PDT 24
Peak memory 206524 kb
Host smart-df4b2680-1b88-436e-9a0b-eeb59c11da71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73180
4783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.731804783
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.657831552
Short name T524
Test name
Test status
Simulation time 4404211544 ps
CPU time 40.95 seconds
Started Jul 02 09:09:52 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206500 kb
Host smart-c67ee0d9-9bd1-4077-9fac-df861d903f67
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=657831552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.657831552
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3289980962
Short name T687
Test name
Test status
Simulation time 239273078 ps
CPU time 0.92 seconds
Started Jul 02 09:09:53 AM PDT 24
Finished Jul 02 09:09:55 AM PDT 24
Peak memory 206364 kb
Host smart-2bf2762a-a598-4ad7-a6cf-2c5f2e3d503b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3289980962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3289980962
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.578537651
Short name T775
Test name
Test status
Simulation time 226752517 ps
CPU time 0.92 seconds
Started Jul 02 09:09:51 AM PDT 24
Finished Jul 02 09:09:54 AM PDT 24
Peak memory 206180 kb
Host smart-9b7e0d91-a8aa-42b8-a27b-cac5c8d2037b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57853
7651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.578537651
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.1230847830
Short name T2404
Test name
Test status
Simulation time 7045402366 ps
CPU time 66 seconds
Started Jul 02 09:09:52 AM PDT 24
Finished Jul 02 09:11:00 AM PDT 24
Peak memory 206452 kb
Host smart-1d27592f-2c42-4a0b-9893-c8a2db0547bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12308
47830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.1230847830
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.4170278068
Short name T895
Test name
Test status
Simulation time 7884999006 ps
CPU time 227.44 seconds
Started Jul 02 09:09:53 AM PDT 24
Finished Jul 02 09:13:42 AM PDT 24
Peak memory 206416 kb
Host smart-4eb8b4e1-ba12-454b-b34d-9ce84b4c5d10
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4170278068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.4170278068
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2472732603
Short name T2420
Test name
Test status
Simulation time 157525434 ps
CPU time 0.79 seconds
Started Jul 02 09:09:51 AM PDT 24
Finished Jul 02 09:09:54 AM PDT 24
Peak memory 206192 kb
Host smart-bc863ce5-5953-4626-8d46-e9a877adc887
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2472732603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2472732603
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2037614312
Short name T1100
Test name
Test status
Simulation time 167478619 ps
CPU time 0.79 seconds
Started Jul 02 09:10:01 AM PDT 24
Finished Jul 02 09:10:02 AM PDT 24
Peak memory 206080 kb
Host smart-1b7a3ff2-f552-4f00-846a-4ce596d91854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20376
14312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2037614312
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1317417342
Short name T122
Test name
Test status
Simulation time 182251772 ps
CPU time 0.84 seconds
Started Jul 02 09:09:50 AM PDT 24
Finished Jul 02 09:09:53 AM PDT 24
Peak memory 206156 kb
Host smart-d4a85634-19a4-47ee-b4b7-681026e012ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13174
17342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1317417342
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1798634549
Short name T437
Test name
Test status
Simulation time 147705288 ps
CPU time 0.79 seconds
Started Jul 02 09:09:58 AM PDT 24
Finished Jul 02 09:10:00 AM PDT 24
Peak memory 206208 kb
Host smart-db416954-5a14-4009-8b78-0c7b8d7bc559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17986
34549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1798634549
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2269250940
Short name T2475
Test name
Test status
Simulation time 181112234 ps
CPU time 0.86 seconds
Started Jul 02 09:09:51 AM PDT 24
Finished Jul 02 09:09:54 AM PDT 24
Peak memory 206164 kb
Host smart-cde80a70-e318-424b-9e2b-825a1be2fb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22692
50940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2269250940
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2789819100
Short name T1758
Test name
Test status
Simulation time 174121549 ps
CPU time 0.83 seconds
Started Jul 02 09:10:06 AM PDT 24
Finished Jul 02 09:10:09 AM PDT 24
Peak memory 206188 kb
Host smart-34762259-bbe5-491c-8146-71b7b0240a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27898
19100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2789819100
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2534658283
Short name T1292
Test name
Test status
Simulation time 168166660 ps
CPU time 0.8 seconds
Started Jul 02 09:09:51 AM PDT 24
Finished Jul 02 09:09:54 AM PDT 24
Peak memory 206196 kb
Host smart-bbf38d88-b394-47fd-b721-08480804cb9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25346
58283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2534658283
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.3974881383
Short name T1854
Test name
Test status
Simulation time 255124829 ps
CPU time 0.96 seconds
Started Jul 02 09:09:53 AM PDT 24
Finished Jul 02 09:09:55 AM PDT 24
Peak memory 206156 kb
Host smart-0c3bd1f3-a207-4b6a-80ff-2c7db0b77dc5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3974881383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.3974881383
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.639688139
Short name T821
Test name
Test status
Simulation time 165175102 ps
CPU time 0.84 seconds
Started Jul 02 09:09:53 AM PDT 24
Finished Jul 02 09:09:55 AM PDT 24
Peak memory 206124 kb
Host smart-338739b1-c9c6-4c86-a1bf-b1e00385d884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63968
8139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.639688139
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.566856898
Short name T2281
Test name
Test status
Simulation time 40642013 ps
CPU time 0.67 seconds
Started Jul 02 09:09:52 AM PDT 24
Finished Jul 02 09:09:54 AM PDT 24
Peak memory 206184 kb
Host smart-c82687e1-bb50-4103-a8b3-4e90061cf6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56685
6898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.566856898
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2883792667
Short name T1642
Test name
Test status
Simulation time 10897459653 ps
CPU time 26.05 seconds
Started Jul 02 09:09:53 AM PDT 24
Finished Jul 02 09:10:21 AM PDT 24
Peak memory 206680 kb
Host smart-508fe44a-ff1e-4e29-b935-7b05ccd5de84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28837
92667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2883792667
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.353764132
Short name T2164
Test name
Test status
Simulation time 164210330 ps
CPU time 0.82 seconds
Started Jul 02 09:09:51 AM PDT 24
Finished Jul 02 09:09:54 AM PDT 24
Peak memory 206184 kb
Host smart-d4285ca8-fd5f-48d5-90a9-0ac5b8b4b1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35376
4132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.353764132
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.634200872
Short name T1010
Test name
Test status
Simulation time 199470001 ps
CPU time 0.89 seconds
Started Jul 02 09:09:55 AM PDT 24
Finished Jul 02 09:09:58 AM PDT 24
Peak memory 206172 kb
Host smart-aad25d34-de36-4184-a4a7-b372079cc957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63420
0872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.634200872
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.4085292607
Short name T1453
Test name
Test status
Simulation time 278022711 ps
CPU time 0.95 seconds
Started Jul 02 09:10:06 AM PDT 24
Finished Jul 02 09:10:09 AM PDT 24
Peak memory 206212 kb
Host smart-a2e112ed-af31-4683-a42a-3abdd01c8820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40852
92607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.4085292607
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.4019418127
Short name T2608
Test name
Test status
Simulation time 258661830 ps
CPU time 0.98 seconds
Started Jul 02 09:10:10 AM PDT 24
Finished Jul 02 09:10:12 AM PDT 24
Peak memory 206216 kb
Host smart-3b4759b0-035e-4c19-82f4-0b53f5c273d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40194
18127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.4019418127
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.667562417
Short name T269
Test name
Test status
Simulation time 181185187 ps
CPU time 0.91 seconds
Started Jul 02 09:09:57 AM PDT 24
Finished Jul 02 09:10:00 AM PDT 24
Peak memory 206176 kb
Host smart-8a7120c2-0551-4e0b-80a3-231771e96318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66756
2417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.667562417
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.67996046
Short name T2015
Test name
Test status
Simulation time 172256628 ps
CPU time 0.79 seconds
Started Jul 02 09:09:54 AM PDT 24
Finished Jul 02 09:09:57 AM PDT 24
Peak memory 206120 kb
Host smart-977d8f83-1aff-44c5-999d-f28fa6b54f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67996
046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.67996046
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.892137107
Short name T867
Test name
Test status
Simulation time 185004183 ps
CPU time 0.78 seconds
Started Jul 02 09:09:54 AM PDT 24
Finished Jul 02 09:09:57 AM PDT 24
Peak memory 206188 kb
Host smart-a7f60005-376f-4610-90f4-7ba7f73e5b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89213
7107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.892137107
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.339049542
Short name T2033
Test name
Test status
Simulation time 222030770 ps
CPU time 0.92 seconds
Started Jul 02 09:10:11 AM PDT 24
Finished Jul 02 09:10:13 AM PDT 24
Peak memory 206160 kb
Host smart-7277fe10-0e04-4745-a980-8fc3d28aa8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33904
9542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.339049542
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.1521907597
Short name T2260
Test name
Test status
Simulation time 5591501691 ps
CPU time 153.36 seconds
Started Jul 02 09:10:08 AM PDT 24
Finished Jul 02 09:12:44 AM PDT 24
Peak memory 206496 kb
Host smart-7bbf3c10-f986-4134-af0a-07548ccd9fe7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1521907597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.1521907597
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3839633534
Short name T2589
Test name
Test status
Simulation time 172083287 ps
CPU time 0.88 seconds
Started Jul 02 09:09:59 AM PDT 24
Finished Jul 02 09:10:01 AM PDT 24
Peak memory 206124 kb
Host smart-2a3a0de5-4110-4bb9-a7d7-a85f2a1d7858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38396
33534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3839633534
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1340085486
Short name T857
Test name
Test status
Simulation time 176649414 ps
CPU time 0.79 seconds
Started Jul 02 09:09:56 AM PDT 24
Finished Jul 02 09:09:59 AM PDT 24
Peak memory 206120 kb
Host smart-8ee7ce66-5d3b-484d-b361-61123b243825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13400
85486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1340085486
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.706578073
Short name T794
Test name
Test status
Simulation time 446247566 ps
CPU time 1.3 seconds
Started Jul 02 09:09:57 AM PDT 24
Finished Jul 02 09:10:01 AM PDT 24
Peak memory 206188 kb
Host smart-7feb125d-8a58-4a16-8472-a306840a1990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70657
8073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.706578073
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3814116030
Short name T670
Test name
Test status
Simulation time 4928023399 ps
CPU time 135.68 seconds
Started Jul 02 09:10:02 AM PDT 24
Finished Jul 02 09:12:18 AM PDT 24
Peak memory 206524 kb
Host smart-d4023445-b117-4e84-8af9-1d7af619f436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38141
16030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3814116030
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.591461902
Short name T790
Test name
Test status
Simulation time 41885618 ps
CPU time 0.69 seconds
Started Jul 02 09:10:17 AM PDT 24
Finished Jul 02 09:10:19 AM PDT 24
Peak memory 206256 kb
Host smart-ebffbdf2-e615-4314-b701-cdfd70814391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=591461902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.591461902
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3500574287
Short name T1726
Test name
Test status
Simulation time 4094053731 ps
CPU time 5.79 seconds
Started Jul 02 09:09:55 AM PDT 24
Finished Jul 02 09:10:03 AM PDT 24
Peak memory 206448 kb
Host smart-218509b9-f438-447d-83a8-2d66859e0ba0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3500574287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.3500574287
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2753000750
Short name T983
Test name
Test status
Simulation time 13426024174 ps
CPU time 13.26 seconds
Started Jul 02 09:09:55 AM PDT 24
Finished Jul 02 09:10:11 AM PDT 24
Peak memory 206228 kb
Host smart-5dc91499-9765-4db6-a6c2-512f5108d815
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2753000750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2753000750
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.3934523510
Short name T1355
Test name
Test status
Simulation time 23455472304 ps
CPU time 28.27 seconds
Started Jul 02 09:09:56 AM PDT 24
Finished Jul 02 09:10:26 AM PDT 24
Peak memory 206412 kb
Host smart-3bb53032-0e2f-4068-a8c4-37d3970eac0e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3934523510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.3934523510
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2557799651
Short name T2535
Test name
Test status
Simulation time 148625592 ps
CPU time 0.77 seconds
Started Jul 02 09:10:04 AM PDT 24
Finished Jul 02 09:10:05 AM PDT 24
Peak memory 206164 kb
Host smart-93674982-3baa-4fa8-b7cf-b6ec5f6b58ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25577
99651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2557799651
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1945960066
Short name T1261
Test name
Test status
Simulation time 189508303 ps
CPU time 0.83 seconds
Started Jul 02 09:09:56 AM PDT 24
Finished Jul 02 09:09:59 AM PDT 24
Peak memory 206156 kb
Host smart-a407fa78-a878-4e36-a2bf-6fdaaf03a22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19459
60066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1945960066
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2605459354
Short name T1676
Test name
Test status
Simulation time 333145384 ps
CPU time 1.17 seconds
Started Jul 02 09:09:57 AM PDT 24
Finished Jul 02 09:10:00 AM PDT 24
Peak memory 206156 kb
Host smart-33af255b-3d31-4f8c-a1a2-81e2e869c206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26054
59354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2605459354
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.2359889206
Short name T2672
Test name
Test status
Simulation time 1299677691 ps
CPU time 3.18 seconds
Started Jul 02 09:10:06 AM PDT 24
Finished Jul 02 09:10:11 AM PDT 24
Peak memory 206412 kb
Host smart-b51345e1-6350-4e51-af88-51a5952b0b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23598
89206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.2359889206
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.2529095246
Short name T1361
Test name
Test status
Simulation time 11410684600 ps
CPU time 22.74 seconds
Started Jul 02 09:10:09 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206516 kb
Host smart-9f57201e-38cf-4dc1-b960-fba1f5afed01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25290
95246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2529095246
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.2489772217
Short name T2558
Test name
Test status
Simulation time 408229253 ps
CPU time 1.25 seconds
Started Jul 02 09:10:06 AM PDT 24
Finished Jul 02 09:10:09 AM PDT 24
Peak memory 206128 kb
Host smart-12e5e8fe-6a87-4c5c-942a-dc9a05645b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24897
72217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.2489772217
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2860860843
Short name T1474
Test name
Test status
Simulation time 157870569 ps
CPU time 0.75 seconds
Started Jul 02 09:09:58 AM PDT 24
Finished Jul 02 09:10:00 AM PDT 24
Peak memory 206204 kb
Host smart-2c2faa67-d07f-48ea-bbf5-06f1dde8090f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28608
60843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2860860843
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.440506735
Short name T2336
Test name
Test status
Simulation time 42841450 ps
CPU time 0.68 seconds
Started Jul 02 09:10:10 AM PDT 24
Finished Jul 02 09:10:12 AM PDT 24
Peak memory 206208 kb
Host smart-68f077e5-58cc-4abb-8512-bb3298b8a8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44050
6735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.440506735
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2341272188
Short name T1513
Test name
Test status
Simulation time 795976186 ps
CPU time 2.12 seconds
Started Jul 02 09:09:59 AM PDT 24
Finished Jul 02 09:10:02 AM PDT 24
Peak memory 206352 kb
Host smart-8a537dba-4319-44d0-9796-5521d89bdc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23412
72188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2341272188
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2680064978
Short name T1219
Test name
Test status
Simulation time 346182690 ps
CPU time 1.95 seconds
Started Jul 02 09:10:13 AM PDT 24
Finished Jul 02 09:10:16 AM PDT 24
Peak memory 206388 kb
Host smart-2b5d8377-e5b6-49bf-90ad-f537eb5a31e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26800
64978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2680064978
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.747256674
Short name T2547
Test name
Test status
Simulation time 150451442 ps
CPU time 0.81 seconds
Started Jul 02 09:10:07 AM PDT 24
Finished Jul 02 09:10:11 AM PDT 24
Peak memory 206216 kb
Host smart-31ac44f0-30d6-46d0-bcfc-b589bdfb749d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74725
6674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.747256674
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.503866240
Short name T1762
Test name
Test status
Simulation time 164524548 ps
CPU time 0.82 seconds
Started Jul 02 09:10:07 AM PDT 24
Finished Jul 02 09:10:11 AM PDT 24
Peak memory 206120 kb
Host smart-9afcabc5-4878-46a7-968d-d41132dce5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50386
6240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.503866240
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1098819934
Short name T1710
Test name
Test status
Simulation time 262160056 ps
CPU time 0.92 seconds
Started Jul 02 09:10:00 AM PDT 24
Finished Jul 02 09:10:02 AM PDT 24
Peak memory 206164 kb
Host smart-4f87468d-a7cf-4623-96c8-8c94889c7dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10988
19934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1098819934
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.522187697
Short name T1625
Test name
Test status
Simulation time 233811566 ps
CPU time 0.97 seconds
Started Jul 02 09:10:00 AM PDT 24
Finished Jul 02 09:10:02 AM PDT 24
Peak memory 206188 kb
Host smart-dbd10d83-8ff7-4d4c-85bf-ec60b985eac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52218
7697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.522187697
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.2164773709
Short name T1591
Test name
Test status
Simulation time 23314394222 ps
CPU time 22.96 seconds
Started Jul 02 09:10:01 AM PDT 24
Finished Jul 02 09:10:25 AM PDT 24
Peak memory 206268 kb
Host smart-80157a0c-ec99-4501-973a-0d87c40670a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21647
73709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.2164773709
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.905013458
Short name T588
Test name
Test status
Simulation time 3309087367 ps
CPU time 4.19 seconds
Started Jul 02 09:10:00 AM PDT 24
Finished Jul 02 09:10:05 AM PDT 24
Peak memory 206244 kb
Host smart-c0a73376-1ae1-4b2c-a5ea-a5bed24266ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90501
3458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.905013458
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.4165894874
Short name T1970
Test name
Test status
Simulation time 12292852414 ps
CPU time 85.57 seconds
Started Jul 02 09:10:14 AM PDT 24
Finished Jul 02 09:11:42 AM PDT 24
Peak memory 206500 kb
Host smart-8f7a29a6-d5a7-444e-b5fa-2f0f0c870e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41658
94874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.4165894874
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2716678710
Short name T2422
Test name
Test status
Simulation time 4172533031 ps
CPU time 39.7 seconds
Started Jul 02 09:10:09 AM PDT 24
Finished Jul 02 09:10:51 AM PDT 24
Peak memory 206460 kb
Host smart-2aadc525-572d-4fff-a760-0ac53c746077
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2716678710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2716678710
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1363930043
Short name T869
Test name
Test status
Simulation time 245781371 ps
CPU time 0.94 seconds
Started Jul 02 09:10:15 AM PDT 24
Finished Jul 02 09:10:17 AM PDT 24
Peak memory 206136 kb
Host smart-72a5b0b1-f204-440a-ae16-c603fa0a6227
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1363930043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1363930043
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3213693145
Short name T2293
Test name
Test status
Simulation time 193121921 ps
CPU time 0.87 seconds
Started Jul 02 09:10:07 AM PDT 24
Finished Jul 02 09:10:11 AM PDT 24
Peak memory 206152 kb
Host smart-82f2393f-f9f4-4879-80fd-0e0c285f22ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32136
93145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3213693145
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.643912153
Short name T1232
Test name
Test status
Simulation time 6037729976 ps
CPU time 168.92 seconds
Started Jul 02 09:10:07 AM PDT 24
Finished Jul 02 09:12:59 AM PDT 24
Peak memory 206412 kb
Host smart-43ce6f77-48d1-438d-9e5e-653e9168a10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64391
2153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.643912153
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2089544942
Short name T679
Test name
Test status
Simulation time 2836308322 ps
CPU time 78.72 seconds
Started Jul 02 09:10:07 AM PDT 24
Finished Jul 02 09:11:28 AM PDT 24
Peak memory 206416 kb
Host smart-eefe1423-d75f-4f04-a79d-0ac277c64caa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2089544942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2089544942
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.441615446
Short name T819
Test name
Test status
Simulation time 173898594 ps
CPU time 0.82 seconds
Started Jul 02 09:10:06 AM PDT 24
Finished Jul 02 09:10:09 AM PDT 24
Peak memory 206168 kb
Host smart-79e7f958-87f1-4b75-a67e-180b3d7d431c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=441615446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.441615446
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1237186620
Short name T733
Test name
Test status
Simulation time 140733495 ps
CPU time 0.78 seconds
Started Jul 02 09:09:59 AM PDT 24
Finished Jul 02 09:10:01 AM PDT 24
Peak memory 206212 kb
Host smart-dfffc156-ab45-408e-bfcd-266653dc41f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12371
86620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1237186620
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.635789122
Short name T2623
Test name
Test status
Simulation time 237446857 ps
CPU time 0.88 seconds
Started Jul 02 09:10:08 AM PDT 24
Finished Jul 02 09:10:12 AM PDT 24
Peak memory 206196 kb
Host smart-1c256ab1-6a4b-4331-afeb-998bafab7a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63578
9122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.635789122
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1586349677
Short name T1995
Test name
Test status
Simulation time 169219618 ps
CPU time 0.85 seconds
Started Jul 02 09:10:12 AM PDT 24
Finished Jul 02 09:10:14 AM PDT 24
Peak memory 206216 kb
Host smart-d0145aa5-01aa-4340-b661-8acd58aa319f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15863
49677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1586349677
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1110103972
Short name T2048
Test name
Test status
Simulation time 162479457 ps
CPU time 0.78 seconds
Started Jul 02 09:10:07 AM PDT 24
Finished Jul 02 09:10:11 AM PDT 24
Peak memory 206128 kb
Host smart-8b9ef48e-b73c-473e-ae54-9996c6c47e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11101
03972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1110103972
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1589377466
Short name T2512
Test name
Test status
Simulation time 198414376 ps
CPU time 0.9 seconds
Started Jul 02 09:10:10 AM PDT 24
Finished Jul 02 09:10:13 AM PDT 24
Peak memory 206168 kb
Host smart-f0141e08-4d27-41af-9f2e-d5852803863f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15893
77466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1589377466
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1675377434
Short name T1903
Test name
Test status
Simulation time 172447225 ps
CPU time 0.79 seconds
Started Jul 02 09:10:08 AM PDT 24
Finished Jul 02 09:10:11 AM PDT 24
Peak memory 206196 kb
Host smart-b4e663ef-0851-49f6-b9d3-79a5c971863b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16753
77434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1675377434
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.902933033
Short name T1221
Test name
Test status
Simulation time 266703913 ps
CPU time 1.01 seconds
Started Jul 02 09:10:13 AM PDT 24
Finished Jul 02 09:10:15 AM PDT 24
Peak memory 206168 kb
Host smart-94bb318a-3a51-4eb9-8914-1a817b75d13c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=902933033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.902933033
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1867546792
Short name T2631
Test name
Test status
Simulation time 141339981 ps
CPU time 0.81 seconds
Started Jul 02 09:10:05 AM PDT 24
Finished Jul 02 09:10:07 AM PDT 24
Peak memory 206208 kb
Host smart-77a5ea0b-0383-4894-92ec-eebc5ce038c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18675
46792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1867546792
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2269578228
Short name T37
Test name
Test status
Simulation time 67506238 ps
CPU time 0.69 seconds
Started Jul 02 09:10:07 AM PDT 24
Finished Jul 02 09:10:10 AM PDT 24
Peak memory 206176 kb
Host smart-92bb104e-b575-4df7-b3e1-82fe3e9d21de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22695
78228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2269578228
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.375556131
Short name T1722
Test name
Test status
Simulation time 11702755576 ps
CPU time 28.08 seconds
Started Jul 02 09:10:07 AM PDT 24
Finished Jul 02 09:10:37 AM PDT 24
Peak memory 206472 kb
Host smart-1fb966a7-059d-4d93-91fd-17eb4cb3c985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555
6131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.375556131
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2828014541
Short name T511
Test name
Test status
Simulation time 171045150 ps
CPU time 0.82 seconds
Started Jul 02 09:10:05 AM PDT 24
Finished Jul 02 09:10:06 AM PDT 24
Peak memory 206212 kb
Host smart-4885d0c6-339b-4ba1-ad46-e76140520e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28280
14541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2828014541
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1155354137
Short name T2050
Test name
Test status
Simulation time 205542913 ps
CPU time 0.88 seconds
Started Jul 02 09:10:05 AM PDT 24
Finished Jul 02 09:10:06 AM PDT 24
Peak memory 206164 kb
Host smart-e54d70a4-7e02-4d2c-9e7c-f500415909e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11553
54137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1155354137
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1124457709
Short name T1955
Test name
Test status
Simulation time 204473332 ps
CPU time 0.85 seconds
Started Jul 02 09:10:06 AM PDT 24
Finished Jul 02 09:10:09 AM PDT 24
Peak memory 206208 kb
Host smart-b37389f5-9c25-4ecb-bd73-c58bf1347fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11244
57709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1124457709
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.364335907
Short name T2100
Test name
Test status
Simulation time 181373032 ps
CPU time 0.88 seconds
Started Jul 02 09:10:06 AM PDT 24
Finished Jul 02 09:10:09 AM PDT 24
Peak memory 206208 kb
Host smart-a4126e9c-b0da-4ac8-a1e3-11637e0e5d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36433
5907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.364335907
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.198737500
Short name T1872
Test name
Test status
Simulation time 136954151 ps
CPU time 0.74 seconds
Started Jul 02 09:10:04 AM PDT 24
Finished Jul 02 09:10:05 AM PDT 24
Peak memory 206192 kb
Host smart-d90aa87f-bfa8-4afa-991a-d7612c028112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19873
7500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.198737500
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1835793964
Short name T2685
Test name
Test status
Simulation time 157619106 ps
CPU time 0.81 seconds
Started Jul 02 09:10:06 AM PDT 24
Finished Jul 02 09:10:08 AM PDT 24
Peak memory 206200 kb
Host smart-d356371e-fe38-423c-b935-f96a159ba625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18357
93964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1835793964
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1914075100
Short name T1130
Test name
Test status
Simulation time 176138266 ps
CPU time 0.82 seconds
Started Jul 02 09:10:03 AM PDT 24
Finished Jul 02 09:10:04 AM PDT 24
Peak memory 206224 kb
Host smart-e6173a66-c006-4556-af9c-cc4bbb739d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19140
75100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1914075100
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1294499472
Short name T2563
Test name
Test status
Simulation time 197851331 ps
CPU time 0.94 seconds
Started Jul 02 09:10:05 AM PDT 24
Finished Jul 02 09:10:08 AM PDT 24
Peak memory 206204 kb
Host smart-becee8f9-bfb6-49c9-be4a-a69b846013a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12944
99472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1294499472
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.676564782
Short name T406
Test name
Test status
Simulation time 3284190843 ps
CPU time 32.1 seconds
Started Jul 02 09:10:06 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206448 kb
Host smart-77072b6f-5992-481b-83d6-c3434c2e5866
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=676564782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.676564782
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.4289555458
Short name T1396
Test name
Test status
Simulation time 169821243 ps
CPU time 0.83 seconds
Started Jul 02 09:10:04 AM PDT 24
Finished Jul 02 09:10:05 AM PDT 24
Peak memory 206168 kb
Host smart-2676df57-d6b0-4c10-bde2-26739089b162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42895
55458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.4289555458
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.644998256
Short name T2627
Test name
Test status
Simulation time 199961872 ps
CPU time 0.84 seconds
Started Jul 02 09:10:08 AM PDT 24
Finished Jul 02 09:10:12 AM PDT 24
Peak memory 206196 kb
Host smart-0db69d71-b7a3-4ae3-b5fa-c0d2f89588d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64499
8256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.644998256
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.2314932346
Short name T992
Test name
Test status
Simulation time 1265198960 ps
CPU time 2.79 seconds
Started Jul 02 09:10:09 AM PDT 24
Finished Jul 02 09:10:14 AM PDT 24
Peak memory 206392 kb
Host smart-ea64253f-1373-4ce3-a120-21c21d4a61e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23149
32346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.2314932346
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.4100593022
Short name T1206
Test name
Test status
Simulation time 6759720629 ps
CPU time 46.38 seconds
Started Jul 02 09:10:08 AM PDT 24
Finished Jul 02 09:10:57 AM PDT 24
Peak memory 206388 kb
Host smart-08cbce0c-e550-48da-abee-996e9b73fd90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41005
93022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.4100593022
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3132501579
Short name T1803
Test name
Test status
Simulation time 59291711 ps
CPU time 0.65 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:25 AM PDT 24
Peak memory 205780 kb
Host smart-7f9a6786-8fa8-4c09-9103-876b1f675f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3132501579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3132501579
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3021171863
Short name T886
Test name
Test status
Simulation time 3903881373 ps
CPU time 4.79 seconds
Started Jul 02 09:10:08 AM PDT 24
Finished Jul 02 09:10:15 AM PDT 24
Peak memory 206244 kb
Host smart-f2e118f7-9966-47e7-bc3f-0e801c5c7915
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3021171863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.3021171863
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.507478418
Short name T1452
Test name
Test status
Simulation time 13427722289 ps
CPU time 12.95 seconds
Started Jul 02 09:10:14 AM PDT 24
Finished Jul 02 09:10:29 AM PDT 24
Peak memory 206252 kb
Host smart-4aa667b2-a59c-4d2d-ab1d-0b7fa34c342f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=507478418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.507478418
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3693980170
Short name T1249
Test name
Test status
Simulation time 23335762994 ps
CPU time 27.77 seconds
Started Jul 02 09:10:18 AM PDT 24
Finished Jul 02 09:10:47 AM PDT 24
Peak memory 206248 kb
Host smart-b7886c53-8f5c-4e98-93bb-0757743dc075
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3693980170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.3693980170
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1695081226
Short name T1416
Test name
Test status
Simulation time 164686641 ps
CPU time 0.84 seconds
Started Jul 02 09:10:15 AM PDT 24
Finished Jul 02 09:10:17 AM PDT 24
Peak memory 206176 kb
Host smart-56e8ecc3-378b-4861-9305-0f47d5adbb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16950
81226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1695081226
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3783121012
Short name T1916
Test name
Test status
Simulation time 155534810 ps
CPU time 0.81 seconds
Started Jul 02 09:10:16 AM PDT 24
Finished Jul 02 09:10:18 AM PDT 24
Peak memory 206204 kb
Host smart-87fe2fcf-cfbd-457c-8726-f4325821f633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37831
21012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3783121012
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.3909138705
Short name T718
Test name
Test status
Simulation time 359811840 ps
CPU time 1.3 seconds
Started Jul 02 09:10:08 AM PDT 24
Finished Jul 02 09:10:12 AM PDT 24
Peak memory 206200 kb
Host smart-aa371f5e-8209-4abc-99ff-5854572abb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39091
38705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.3909138705
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3731175339
Short name T2230
Test name
Test status
Simulation time 317574266 ps
CPU time 1.08 seconds
Started Jul 02 09:10:19 AM PDT 24
Finished Jul 02 09:10:21 AM PDT 24
Peak memory 206216 kb
Host smart-dcc36c7c-393b-4ea8-a056-f9edd2a2133d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37311
75339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3731175339
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.1036529290
Short name T1691
Test name
Test status
Simulation time 22521342555 ps
CPU time 46.89 seconds
Started Jul 02 09:10:14 AM PDT 24
Finished Jul 02 09:11:02 AM PDT 24
Peak memory 206456 kb
Host smart-e081ecaa-8143-4ccb-b7be-908046507051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10365
29290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.1036529290
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3212197072
Short name T203
Test name
Test status
Simulation time 467524572 ps
CPU time 1.32 seconds
Started Jul 02 09:10:13 AM PDT 24
Finished Jul 02 09:10:15 AM PDT 24
Peak memory 206192 kb
Host smart-66e77661-1212-4cc5-aa4c-96939c7e2fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32121
97072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3212197072
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.2010739666
Short name T2201
Test name
Test status
Simulation time 145028933 ps
CPU time 0.74 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:25 AM PDT 24
Peak memory 206180 kb
Host smart-f8f8ada3-016e-4b92-b095-6475b9642bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20107
39666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2010739666
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.4052711694
Short name T960
Test name
Test status
Simulation time 85399571 ps
CPU time 0.71 seconds
Started Jul 02 09:10:13 AM PDT 24
Finished Jul 02 09:10:15 AM PDT 24
Peak memory 206336 kb
Host smart-a644fe4e-222a-41c8-b704-3a6a6f551468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40527
11694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.4052711694
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1125478714
Short name T1233
Test name
Test status
Simulation time 842005837 ps
CPU time 2.09 seconds
Started Jul 02 09:10:14 AM PDT 24
Finished Jul 02 09:10:18 AM PDT 24
Peak memory 206368 kb
Host smart-0a2a5fbc-350b-4e72-8ef0-ae66652dab7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11254
78714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1125478714
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.801247115
Short name T957
Test name
Test status
Simulation time 191601756 ps
CPU time 1.29 seconds
Started Jul 02 09:10:13 AM PDT 24
Finished Jul 02 09:10:15 AM PDT 24
Peak memory 206380 kb
Host smart-6fb4e228-2862-4951-98ec-986d3b9552dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80124
7115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.801247115
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.609797339
Short name T609
Test name
Test status
Simulation time 203716702 ps
CPU time 0.88 seconds
Started Jul 02 09:10:17 AM PDT 24
Finished Jul 02 09:10:19 AM PDT 24
Peak memory 206208 kb
Host smart-94480421-3cc5-4f09-a377-790a27698349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60979
7339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.609797339
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1402281986
Short name T2503
Test name
Test status
Simulation time 139584632 ps
CPU time 0.82 seconds
Started Jul 02 09:10:13 AM PDT 24
Finished Jul 02 09:10:16 AM PDT 24
Peak memory 206188 kb
Host smart-43e09203-dbcc-4df2-8f82-053f74ec0c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022
81986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1402281986
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3534834964
Short name T871
Test name
Test status
Simulation time 208985557 ps
CPU time 0.94 seconds
Started Jul 02 09:10:13 AM PDT 24
Finished Jul 02 09:10:15 AM PDT 24
Peak memory 206208 kb
Host smart-035dd0de-785c-4d8b-bdde-d1c3a94482bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35348
34964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3534834964
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.3601100668
Short name T1678
Test name
Test status
Simulation time 6088617959 ps
CPU time 58.37 seconds
Started Jul 02 09:10:09 AM PDT 24
Finished Jul 02 09:11:09 AM PDT 24
Peak memory 206476 kb
Host smart-068eb7cd-39e1-4367-9feb-e39297075c5c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3601100668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3601100668
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.1013340357
Short name T1228
Test name
Test status
Simulation time 227536568 ps
CPU time 0.94 seconds
Started Jul 02 09:10:20 AM PDT 24
Finished Jul 02 09:10:23 AM PDT 24
Peak memory 206180 kb
Host smart-7cc39919-41a4-4102-9fb0-1d57e6435797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10133
40357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1013340357
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.500821573
Short name T1389
Test name
Test status
Simulation time 23394690565 ps
CPU time 25.24 seconds
Started Jul 02 09:10:08 AM PDT 24
Finished Jul 02 09:10:36 AM PDT 24
Peak memory 206228 kb
Host smart-52ca138d-bc16-405d-8f21-b1b4a30f8706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50082
1573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.500821573
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.4088458735
Short name T388
Test name
Test status
Simulation time 3299088790 ps
CPU time 4.53 seconds
Started Jul 02 09:10:11 AM PDT 24
Finished Jul 02 09:10:16 AM PDT 24
Peak memory 206248 kb
Host smart-ac8ec688-725e-4a11-95a0-3e6da10b9027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40884
58735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.4088458735
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2119791867
Short name T571
Test name
Test status
Simulation time 8719153376 ps
CPU time 66.71 seconds
Started Jul 02 09:10:13 AM PDT 24
Finished Jul 02 09:11:21 AM PDT 24
Peak memory 206488 kb
Host smart-89a75093-9ad8-489b-a761-a45dd56daf4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21197
91867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2119791867
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3654056294
Short name T1150
Test name
Test status
Simulation time 3537822765 ps
CPU time 97.26 seconds
Started Jul 02 09:10:18 AM PDT 24
Finished Jul 02 09:11:57 AM PDT 24
Peak memory 206380 kb
Host smart-9c74d959-b056-4b5a-bfbd-579c6edd27bf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3654056294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3654056294
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.152748268
Short name T2356
Test name
Test status
Simulation time 236042813 ps
CPU time 0.91 seconds
Started Jul 02 09:10:12 AM PDT 24
Finished Jul 02 09:10:14 AM PDT 24
Peak memory 206176 kb
Host smart-7b85adf3-bfa9-48fd-8f52-6ce46be710bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=152748268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.152748268
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2531832908
Short name T1953
Test name
Test status
Simulation time 194140004 ps
CPU time 0.9 seconds
Started Jul 02 09:10:15 AM PDT 24
Finished Jul 02 09:10:17 AM PDT 24
Peak memory 206188 kb
Host smart-213cb37b-7261-421b-a5bf-ad86c25c815e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25318
32908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2531832908
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.2908646933
Short name T431
Test name
Test status
Simulation time 3430855328 ps
CPU time 31.99 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:55 AM PDT 24
Peak memory 206520 kb
Host smart-82c1bcaf-fe53-4918-9a0b-70c41c0ea1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29086
46933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.2908646933
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.4154019351
Short name T878
Test name
Test status
Simulation time 7246970706 ps
CPU time 196.94 seconds
Started Jul 02 09:10:12 AM PDT 24
Finished Jul 02 09:13:30 AM PDT 24
Peak memory 206460 kb
Host smart-b596747e-23a0-42c7-993a-3d9fe10af171
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4154019351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.4154019351
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.4261369336
Short name T2389
Test name
Test status
Simulation time 160189203 ps
CPU time 0.85 seconds
Started Jul 02 09:10:12 AM PDT 24
Finished Jul 02 09:10:14 AM PDT 24
Peak memory 206104 kb
Host smart-6070b558-57ba-4525-8680-d41238d333a3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4261369336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.4261369336
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3813434828
Short name T1582
Test name
Test status
Simulation time 186602475 ps
CPU time 0.81 seconds
Started Jul 02 09:10:20 AM PDT 24
Finished Jul 02 09:10:23 AM PDT 24
Peak memory 206212 kb
Host smart-3dac3ca3-c885-4b80-9d15-3ee259a7ec2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38134
34828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3813434828
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3340949773
Short name T146
Test name
Test status
Simulation time 173996611 ps
CPU time 0.85 seconds
Started Jul 02 09:10:23 AM PDT 24
Finished Jul 02 09:10:27 AM PDT 24
Peak memory 206224 kb
Host smart-393da70d-7068-4b0d-b67c-7d5cf8598ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33409
49773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3340949773
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2303974028
Short name T343
Test name
Test status
Simulation time 171585895 ps
CPU time 0.83 seconds
Started Jul 02 09:10:18 AM PDT 24
Finished Jul 02 09:10:20 AM PDT 24
Peak memory 206220 kb
Host smart-68aec5c6-e035-4801-bbae-7ecbf2f8465a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
74028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2303974028
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1820393987
Short name T467
Test name
Test status
Simulation time 191617878 ps
CPU time 0.87 seconds
Started Jul 02 09:10:22 AM PDT 24
Finished Jul 02 09:10:26 AM PDT 24
Peak memory 206208 kb
Host smart-b1f95101-9822-4812-a67d-a64c20d39406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18203
93987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1820393987
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2013711284
Short name T2445
Test name
Test status
Simulation time 165172999 ps
CPU time 0.79 seconds
Started Jul 02 09:10:19 AM PDT 24
Finished Jul 02 09:10:21 AM PDT 24
Peak memory 206212 kb
Host smart-c81e6621-b816-4a98-b451-789eedae5286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20137
11284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2013711284
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.605595219
Short name T666
Test name
Test status
Simulation time 146742141 ps
CPU time 0.75 seconds
Started Jul 02 09:10:19 AM PDT 24
Finished Jul 02 09:10:21 AM PDT 24
Peak memory 206204 kb
Host smart-f7c1b19c-6a98-4508-936c-4af8376a5952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60559
5219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.605595219
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3087777509
Short name T2041
Test name
Test status
Simulation time 239426171 ps
CPU time 1.14 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:25 AM PDT 24
Peak memory 206204 kb
Host smart-49a5f2ed-2ec9-4df2-b6cd-46fb988a26eb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3087777509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3087777509
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1358682190
Short name T1138
Test name
Test status
Simulation time 145517427 ps
CPU time 0.77 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:24 AM PDT 24
Peak memory 206220 kb
Host smart-e90a0152-b7e2-4d6f-ab8b-e8839494c1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13586
82190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1358682190
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2345421506
Short name T1766
Test name
Test status
Simulation time 41364082 ps
CPU time 0.71 seconds
Started Jul 02 09:10:19 AM PDT 24
Finished Jul 02 09:10:21 AM PDT 24
Peak memory 206172 kb
Host smart-a2b1d9b3-fa23-426c-bddc-05220c0c6762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23454
21506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2345421506
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2955940553
Short name T280
Test name
Test status
Simulation time 6493272439 ps
CPU time 14.1 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:38 AM PDT 24
Peak memory 206204 kb
Host smart-01bf6f70-5e9c-42c2-b5af-e412d14328ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29559
40553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2955940553
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3427323051
Short name T18
Test name
Test status
Simulation time 197216742 ps
CPU time 0.87 seconds
Started Jul 02 09:10:18 AM PDT 24
Finished Jul 02 09:10:21 AM PDT 24
Peak memory 206140 kb
Host smart-9b3ec352-c5e5-4def-9349-dbfc8d69fd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34273
23051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3427323051
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1297616485
Short name T1040
Test name
Test status
Simulation time 217001990 ps
CPU time 0.9 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:25 AM PDT 24
Peak memory 206180 kb
Host smart-b1e3323c-e0b0-4de4-90e2-cc87631a9149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12976
16485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1297616485
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3254271302
Short name T607
Test name
Test status
Simulation time 184442327 ps
CPU time 0.87 seconds
Started Jul 02 09:10:13 AM PDT 24
Finished Jul 02 09:10:16 AM PDT 24
Peak memory 206212 kb
Host smart-63cc5df5-706d-4a56-8a1f-334768b5c6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32542
71302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3254271302
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.648207901
Short name T757
Test name
Test status
Simulation time 222911567 ps
CPU time 0.83 seconds
Started Jul 02 09:10:12 AM PDT 24
Finished Jul 02 09:10:14 AM PDT 24
Peak memory 206220 kb
Host smart-53d7e825-67a4-4875-9580-f65a51792587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64820
7901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.648207901
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.163916627
Short name T97
Test name
Test status
Simulation time 177783675 ps
CPU time 0.8 seconds
Started Jul 02 09:10:18 AM PDT 24
Finished Jul 02 09:10:19 AM PDT 24
Peak memory 206176 kb
Host smart-1f88b389-6659-4b8a-9978-924472918bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16391
6627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.163916627
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.986708218
Short name T1078
Test name
Test status
Simulation time 168840812 ps
CPU time 0.8 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206200 kb
Host smart-3dd48864-98ee-41db-8d49-f847fa9f54ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98670
8218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.986708218
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.233882323
Short name T490
Test name
Test status
Simulation time 214195116 ps
CPU time 0.81 seconds
Started Jul 02 09:10:19 AM PDT 24
Finished Jul 02 09:10:21 AM PDT 24
Peak memory 206208 kb
Host smart-d6333c32-ff21-4a4c-b517-b4733b7e3376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23388
2323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.233882323
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.976820667
Short name T1045
Test name
Test status
Simulation time 247133557 ps
CPU time 0.95 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206208 kb
Host smart-1cb39124-c16f-4cb8-8248-f89fab589ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97682
0667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.976820667
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2451391200
Short name T829
Test name
Test status
Simulation time 3550211393 ps
CPU time 33.44 seconds
Started Jul 02 09:10:20 AM PDT 24
Finished Jul 02 09:10:56 AM PDT 24
Peak memory 206500 kb
Host smart-c08063f6-0cd6-4e9a-a174-cb1c71739ff9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2451391200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2451391200
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3950434002
Short name T743
Test name
Test status
Simulation time 164740953 ps
CPU time 0.81 seconds
Started Jul 02 09:10:19 AM PDT 24
Finished Jul 02 09:10:21 AM PDT 24
Peak memory 206212 kb
Host smart-2ab0d9b3-1cd6-4827-bc17-91f2d217820b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39504
34002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3950434002
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1888176510
Short name T725
Test name
Test status
Simulation time 182346567 ps
CPU time 0.86 seconds
Started Jul 02 09:10:30 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206076 kb
Host smart-76f79cd4-5c00-490d-9723-60fdbf0900b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18881
76510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1888176510
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.3592496694
Short name T1606
Test name
Test status
Simulation time 990514957 ps
CPU time 2.25 seconds
Started Jul 02 09:10:26 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206400 kb
Host smart-12319b49-08dc-4f2d-8cd2-cf98f946ebeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35924
96694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.3592496694
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.3991530782
Short name T1027
Test name
Test status
Simulation time 5487840120 ps
CPU time 37.88 seconds
Started Jul 02 09:10:26 AM PDT 24
Finished Jul 02 09:11:08 AM PDT 24
Peak memory 206524 kb
Host smart-871fbe5b-d73b-481f-b41d-9e92c05ca209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39915
30782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.3991530782
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.3443130924
Short name T537
Test name
Test status
Simulation time 115283600 ps
CPU time 0.74 seconds
Started Jul 02 09:10:22 AM PDT 24
Finished Jul 02 09:10:27 AM PDT 24
Peak memory 206224 kb
Host smart-414b4f58-54cc-4109-b085-b53b47ed6633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3443130924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3443130924
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3172230759
Short name T1463
Test name
Test status
Simulation time 4303567097 ps
CPU time 5.3 seconds
Started Jul 02 09:10:16 AM PDT 24
Finished Jul 02 09:10:23 AM PDT 24
Peak memory 206400 kb
Host smart-0928b27e-ae72-4c2d-a94b-42c2a919f0bf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3172230759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.3172230759
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1972392564
Short name T2538
Test name
Test status
Simulation time 13406789074 ps
CPU time 14.54 seconds
Started Jul 02 09:10:22 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206452 kb
Host smart-affd40d5-311d-4909-a2cb-4d7ed4447009
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1972392564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1972392564
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.949161536
Short name T881
Test name
Test status
Simulation time 23396344538 ps
CPU time 23.2 seconds
Started Jul 02 09:10:18 AM PDT 24
Finished Jul 02 09:10:42 AM PDT 24
Peak memory 206156 kb
Host smart-c63a8b60-b124-46ef-969f-81622cfe6d12
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=949161536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.949161536
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2976154618
Short name T1012
Test name
Test status
Simulation time 194100185 ps
CPU time 0.83 seconds
Started Jul 02 09:10:16 AM PDT 24
Finished Jul 02 09:10:18 AM PDT 24
Peak memory 206128 kb
Host smart-06fd5c17-6539-47b5-b689-c0d24a8e40a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761
54618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2976154618
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3409094288
Short name T2067
Test name
Test status
Simulation time 147303055 ps
CPU time 0.82 seconds
Started Jul 02 09:10:30 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206204 kb
Host smart-00c8edb2-c8df-4014-978d-67439fa48b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34090
94288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3409094288
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1638185083
Short name T2640
Test name
Test status
Simulation time 570364208 ps
CPU time 1.8 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:26 AM PDT 24
Peak memory 206024 kb
Host smart-0e8f473e-ba0a-4f92-a707-d7008ccc2c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16381
85083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1638185083
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3580518819
Short name T2104
Test name
Test status
Simulation time 1174886414 ps
CPU time 2.44 seconds
Started Jul 02 09:10:28 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206360 kb
Host smart-b02ed7ce-faf8-4334-91f1-1db2ce079044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35805
18819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3580518819
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2002539000
Short name T1780
Test name
Test status
Simulation time 6559867870 ps
CPU time 14.43 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:38 AM PDT 24
Peak memory 206512 kb
Host smart-d95d9550-0803-4b75-abcc-93dc600a1e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20025
39000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2002539000
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.4172534323
Short name T2527
Test name
Test status
Simulation time 402468294 ps
CPU time 1.2 seconds
Started Jul 02 09:10:19 AM PDT 24
Finished Jul 02 09:10:22 AM PDT 24
Peak memory 206208 kb
Host smart-0ccc2632-42e3-4062-b370-f70942c16bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41725
34323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.4172534323
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3806240448
Short name T888
Test name
Test status
Simulation time 131409977 ps
CPU time 0.75 seconds
Started Jul 02 09:10:24 AM PDT 24
Finished Jul 02 09:10:28 AM PDT 24
Peak memory 206208 kb
Host smart-008548f6-a714-4b2f-903e-daca79860d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38062
40448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3806240448
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2979269284
Short name T91
Test name
Test status
Simulation time 46299230 ps
CPU time 0.7 seconds
Started Jul 02 09:10:20 AM PDT 24
Finished Jul 02 09:10:22 AM PDT 24
Peak memory 206204 kb
Host smart-b682ab24-4690-4dc3-bcf8-af8c52f045af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29792
69284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2979269284
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1712460776
Short name T1511
Test name
Test status
Simulation time 821163784 ps
CPU time 1.96 seconds
Started Jul 02 09:10:28 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206476 kb
Host smart-c541eb75-a703-4463-9f2a-23ef6aa3a3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17124
60776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1712460776
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2027751374
Short name T713
Test name
Test status
Simulation time 296796016 ps
CPU time 2.07 seconds
Started Jul 02 09:10:17 AM PDT 24
Finished Jul 02 09:10:20 AM PDT 24
Peak memory 206356 kb
Host smart-291ca041-7dff-46cf-a89a-8bd884e95035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20277
51374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2027751374
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2549494003
Short name T884
Test name
Test status
Simulation time 218244407 ps
CPU time 1.03 seconds
Started Jul 02 09:10:18 AM PDT 24
Finished Jul 02 09:10:21 AM PDT 24
Peak memory 206208 kb
Host smart-3ab265bc-9978-4bc5-bbe3-0797ec184ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25494
94003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2549494003
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.249636414
Short name T1248
Test name
Test status
Simulation time 149728950 ps
CPU time 0.8 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:26 AM PDT 24
Peak memory 206200 kb
Host smart-c578a2a7-59d4-41b8-89bc-6126ef96b3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24963
6414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.249636414
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3083500938
Short name T1152
Test name
Test status
Simulation time 240009704 ps
CPU time 0.98 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:25 AM PDT 24
Peak memory 206188 kb
Host smart-17a68097-c196-4301-9abb-74ba80f4d7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30835
00938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3083500938
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2172846593
Short name T2235
Test name
Test status
Simulation time 174650886 ps
CPU time 0.82 seconds
Started Jul 02 09:10:17 AM PDT 24
Finished Jul 02 09:10:19 AM PDT 24
Peak memory 206220 kb
Host smart-336dc3ef-9ceb-4799-8ef9-77772f690b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21728
46593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2172846593
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.651291082
Short name T2699
Test name
Test status
Simulation time 23278578156 ps
CPU time 23.19 seconds
Started Jul 02 09:10:26 AM PDT 24
Finished Jul 02 09:10:54 AM PDT 24
Peak memory 206280 kb
Host smart-90929d4c-a9f5-4357-b45a-2d3fc6167eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65129
1082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.651291082
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.4237210520
Short name T1459
Test name
Test status
Simulation time 3283294973 ps
CPU time 4.52 seconds
Started Jul 02 09:10:22 AM PDT 24
Finished Jul 02 09:10:30 AM PDT 24
Peak memory 206140 kb
Host smart-929ede05-1c4a-4b25-b285-0cc8e54b1440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42372
10520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.4237210520
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.3507625943
Short name T1653
Test name
Test status
Simulation time 8083659493 ps
CPU time 240.3 seconds
Started Jul 02 09:10:18 AM PDT 24
Finished Jul 02 09:14:20 AM PDT 24
Peak memory 206488 kb
Host smart-ff205ac2-ad23-491c-9c81-128938a1e6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35076
25943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.3507625943
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3959563074
Short name T1761
Test name
Test status
Simulation time 4398973106 ps
CPU time 41.41 seconds
Started Jul 02 09:10:28 AM PDT 24
Finished Jul 02 09:11:14 AM PDT 24
Peak memory 206452 kb
Host smart-ed7702c9-c717-40d4-b209-2560063b169f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3959563074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3959563074
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.4014170512
Short name T351
Test name
Test status
Simulation time 270658327 ps
CPU time 0.88 seconds
Started Jul 02 09:10:26 AM PDT 24
Finished Jul 02 09:10:32 AM PDT 24
Peak memory 206196 kb
Host smart-591f97da-03b2-4b97-bbab-62a84497778f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4014170512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.4014170512
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.892270997
Short name T2604
Test name
Test status
Simulation time 202774322 ps
CPU time 0.86 seconds
Started Jul 02 09:10:24 AM PDT 24
Finished Jul 02 09:10:29 AM PDT 24
Peak memory 206212 kb
Host smart-48312754-842d-40f9-9fda-c67aea6db8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89227
0997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.892270997
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2724169957
Short name T2697
Test name
Test status
Simulation time 3580524404 ps
CPU time 93.84 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:11:58 AM PDT 24
Peak memory 206336 kb
Host smart-c3f15fc2-9351-471d-bcda-7315a1517eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27241
69957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2724169957
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.2355534437
Short name T1400
Test name
Test status
Simulation time 4686034722 ps
CPU time 34.22 seconds
Started Jul 02 09:10:19 AM PDT 24
Finished Jul 02 09:10:54 AM PDT 24
Peak memory 206444 kb
Host smart-649dcc8b-0dc6-4993-93e8-faa2876b71d9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2355534437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.2355534437
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.910293141
Short name T2425
Test name
Test status
Simulation time 154521591 ps
CPU time 0.83 seconds
Started Jul 02 09:10:22 AM PDT 24
Finished Jul 02 09:10:26 AM PDT 24
Peak memory 206188 kb
Host smart-74ca5935-35d5-4206-968e-c54f6f9bd971
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=910293141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.910293141
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2207759632
Short name T1048
Test name
Test status
Simulation time 143949430 ps
CPU time 0.76 seconds
Started Jul 02 09:10:26 AM PDT 24
Finished Jul 02 09:10:32 AM PDT 24
Peak memory 206184 kb
Host smart-5f1e0d37-6fbf-4065-9761-b182b8273c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22077
59632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2207759632
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2453211976
Short name T133
Test name
Test status
Simulation time 197584606 ps
CPU time 0.86 seconds
Started Jul 02 09:10:23 AM PDT 24
Finished Jul 02 09:10:27 AM PDT 24
Peak memory 206204 kb
Host smart-1ea676d0-70d6-446a-bd7f-cbec26e5edcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24532
11976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2453211976
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.364742999
Short name T2065
Test name
Test status
Simulation time 176839131 ps
CPU time 0.82 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:26 AM PDT 24
Peak memory 206184 kb
Host smart-9bf26794-a20b-488f-8226-ebffd2777b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36474
2999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.364742999
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1569273613
Short name T1002
Test name
Test status
Simulation time 195511584 ps
CPU time 0.83 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206180 kb
Host smart-01d02b43-f509-44a2-adab-b228dced1069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15692
73613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1569273613
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.409212416
Short name T1989
Test name
Test status
Simulation time 185531705 ps
CPU time 0.8 seconds
Started Jul 02 09:10:23 AM PDT 24
Finished Jul 02 09:10:28 AM PDT 24
Peak memory 206216 kb
Host smart-9a1e7428-9440-47be-8eae-b4425fa2b24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40921
2416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.409212416
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.4074871771
Short name T2250
Test name
Test status
Simulation time 164557823 ps
CPU time 0.78 seconds
Started Jul 02 09:10:25 AM PDT 24
Finished Jul 02 09:10:30 AM PDT 24
Peak memory 206224 kb
Host smart-cd16af12-e716-4d3b-b530-7a8650ab5360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40748
71771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.4074871771
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1288355595
Short name T2416
Test name
Test status
Simulation time 199633711 ps
CPU time 0.92 seconds
Started Jul 02 09:10:28 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206160 kb
Host smart-87dcb7d8-daa4-45f5-a1c3-bb61c87beea0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1288355595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1288355595
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2462641999
Short name T1731
Test name
Test status
Simulation time 144712131 ps
CPU time 0.76 seconds
Started Jul 02 09:10:25 AM PDT 24
Finished Jul 02 09:10:30 AM PDT 24
Peak memory 206168 kb
Host smart-80bef48b-01ff-4891-8bc0-7539cc50cfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24626
41999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2462641999
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1157066289
Short name T2380
Test name
Test status
Simulation time 39516992 ps
CPU time 0.66 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206164 kb
Host smart-ad05750e-467a-4ca2-963d-537d1314b56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11570
66289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1157066289
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3409765923
Short name T275
Test name
Test status
Simulation time 13497285675 ps
CPU time 30.6 seconds
Started Jul 02 09:10:24 AM PDT 24
Finished Jul 02 09:10:58 AM PDT 24
Peak memory 206516 kb
Host smart-fc6a4788-6007-4f58-907c-0928bf50cd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34097
65923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3409765923
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1912420573
Short name T379
Test name
Test status
Simulation time 160447681 ps
CPU time 0.79 seconds
Started Jul 02 09:10:30 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206340 kb
Host smart-e953fc14-1037-4aa3-9e98-11be04deb560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19124
20573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1912420573
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3866271814
Short name T2337
Test name
Test status
Simulation time 242447457 ps
CPU time 0.94 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206196 kb
Host smart-139ba0bd-2895-4a7f-a6f1-93c08731ae5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38662
71814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3866271814
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2061389854
Short name T1480
Test name
Test status
Simulation time 165597455 ps
CPU time 0.85 seconds
Started Jul 02 09:10:19 AM PDT 24
Finished Jul 02 09:10:21 AM PDT 24
Peak memory 206172 kb
Host smart-eead08e6-fda7-480f-8205-5a6e2388f6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20613
89854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2061389854
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.2144519101
Short name T1825
Test name
Test status
Simulation time 195558021 ps
CPU time 0.91 seconds
Started Jul 02 09:10:22 AM PDT 24
Finished Jul 02 09:10:27 AM PDT 24
Peak memory 206388 kb
Host smart-b67de721-64d8-4492-8977-5c436c748f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21445
19101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.2144519101
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.4116310915
Short name T2282
Test name
Test status
Simulation time 133507480 ps
CPU time 0.71 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:24 AM PDT 24
Peak memory 206196 kb
Host smart-726ede7d-ab44-4c6b-9f7d-6a41365f2cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41163
10915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.4116310915
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2899228370
Short name T2423
Test name
Test status
Simulation time 149086760 ps
CPU time 0.79 seconds
Started Jul 02 09:10:22 AM PDT 24
Finished Jul 02 09:10:26 AM PDT 24
Peak memory 206388 kb
Host smart-f3e68931-5919-4687-a4a4-83b435aa03a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28992
28370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2899228370
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.559722752
Short name T1634
Test name
Test status
Simulation time 175947639 ps
CPU time 0.79 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:26 AM PDT 24
Peak memory 206176 kb
Host smart-f5b502bd-491a-4313-a899-dc00043e2ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55972
2752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.559722752
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2731012455
Short name T825
Test name
Test status
Simulation time 218087764 ps
CPU time 0.9 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206200 kb
Host smart-ccd625ac-3b09-4b7d-a128-2ddc3ee6ec80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27310
12455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2731012455
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.3177899682
Short name T2120
Test name
Test status
Simulation time 5095372677 ps
CPU time 48.81 seconds
Started Jul 02 09:10:26 AM PDT 24
Finished Jul 02 09:11:20 AM PDT 24
Peak memory 206396 kb
Host smart-ff8ea3a9-f17b-4f25-b1df-f0c2545d351c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3177899682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.3177899682
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.971783470
Short name T1844
Test name
Test status
Simulation time 159231533 ps
CPU time 0.88 seconds
Started Jul 02 09:10:28 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206180 kb
Host smart-119c28c9-5ab5-444a-bbe3-9f4e43922df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97178
3470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.971783470
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.447479842
Short name T2500
Test name
Test status
Simulation time 152822615 ps
CPU time 0.83 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206196 kb
Host smart-35781abd-8f41-40dd-80af-77b2d3dc7173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44747
9842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.447479842
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.3593110661
Short name T233
Test name
Test status
Simulation time 206022982 ps
CPU time 0.97 seconds
Started Jul 02 09:10:22 AM PDT 24
Finished Jul 02 09:10:26 AM PDT 24
Peak memory 206188 kb
Host smart-a828f360-1d43-468c-9427-e7ffb9a98b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35931
10661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.3593110661
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3036325523
Short name T487
Test name
Test status
Simulation time 5471076803 ps
CPU time 37.69 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:11:12 AM PDT 24
Peak memory 206512 kb
Host smart-cbb5c199-76e5-4e54-ad3c-9be3fe11a8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30363
25523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3036325523
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.1689103730
Short name T2248
Test name
Test status
Simulation time 44844949 ps
CPU time 0.68 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206256 kb
Host smart-932c03af-9d0e-4d77-97ac-4de0c79aa39c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1689103730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1689103730
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.5118861
Short name T2644
Test name
Test status
Simulation time 3485144170 ps
CPU time 4.06 seconds
Started Jul 02 09:10:20 AM PDT 24
Finished Jul 02 09:10:27 AM PDT 24
Peak memory 206424 kb
Host smart-a3c1c1a8-6819-42bd-a332-17ba7a5b5d1a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=5118861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.5118861
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2224972454
Short name T1487
Test name
Test status
Simulation time 13351794691 ps
CPU time 13.61 seconds
Started Jul 02 09:10:28 AM PDT 24
Finished Jul 02 09:10:47 AM PDT 24
Peak memory 206412 kb
Host smart-9666eb1b-32fe-4e54-bdfd-008d84110b2c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2224972454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2224972454
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.137585088
Short name T2105
Test name
Test status
Simulation time 23391907403 ps
CPU time 24.14 seconds
Started Jul 02 09:10:28 AM PDT 24
Finished Jul 02 09:10:57 AM PDT 24
Peak memory 206472 kb
Host smart-a1233595-7777-42f1-be3f-e4225b3060d6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=137585088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.137585088
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3439707775
Short name T1455
Test name
Test status
Simulation time 150700873 ps
CPU time 0.75 seconds
Started Jul 02 09:10:20 AM PDT 24
Finished Jul 02 09:10:24 AM PDT 24
Peak memory 206160 kb
Host smart-f782dd0a-d7a3-41c2-8574-42474726b0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34397
07775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3439707775
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2912964054
Short name T1633
Test name
Test status
Simulation time 151468545 ps
CPU time 0.8 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:25 AM PDT 24
Peak memory 206176 kb
Host smart-f2457384-c176-41a5-8443-ae02f8d3d691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29129
64054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2912964054
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3213078050
Short name T1522
Test name
Test status
Simulation time 513205541 ps
CPU time 1.54 seconds
Started Jul 02 09:10:30 AM PDT 24
Finished Jul 02 09:10:36 AM PDT 24
Peak memory 206448 kb
Host smart-e2b82165-f9ba-4d9c-8b61-1456f6bee442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32130
78050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3213078050
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1270577918
Short name T179
Test name
Test status
Simulation time 1052179593 ps
CPU time 2.51 seconds
Started Jul 02 09:10:21 AM PDT 24
Finished Jul 02 09:10:27 AM PDT 24
Peak memory 206380 kb
Host smart-56d36b81-6f3d-452e-8f3a-bf8e61fa4ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12705
77918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1270577918
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3090221516
Short name T185
Test name
Test status
Simulation time 17265676974 ps
CPU time 33.73 seconds
Started Jul 02 09:10:20 AM PDT 24
Finished Jul 02 09:10:56 AM PDT 24
Peak memory 206532 kb
Host smart-7e6abde1-5d1e-43b7-a193-83f6058f7eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30902
21516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3090221516
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.2719994228
Short name T721
Test name
Test status
Simulation time 328273780 ps
CPU time 1.15 seconds
Started Jul 02 09:10:23 AM PDT 24
Finished Jul 02 09:10:28 AM PDT 24
Peak memory 206164 kb
Host smart-fe757649-8431-4be3-973b-741c3e499115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27199
94228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.2719994228
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.560964983
Short name T1528
Test name
Test status
Simulation time 140094138 ps
CPU time 0.76 seconds
Started Jul 02 09:10:24 AM PDT 24
Finished Jul 02 09:10:29 AM PDT 24
Peak memory 206200 kb
Host smart-66cca56f-7b5e-4002-8c1f-d6825e76faa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56096
4983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.560964983
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.512001873
Short name T1977
Test name
Test status
Simulation time 98664006 ps
CPU time 0.76 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:32 AM PDT 24
Peak memory 206204 kb
Host smart-4d64ac0d-ae8e-4d7e-a5c3-fd32420c59a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51200
1873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.512001873
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1971533291
Short name T2397
Test name
Test status
Simulation time 898069600 ps
CPU time 2.05 seconds
Started Jul 02 09:10:26 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206408 kb
Host smart-759551db-6f97-4c5f-8b9d-9a4b1b79e293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19715
33291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1971533291
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1761246281
Short name T1380
Test name
Test status
Simulation time 369077017 ps
CPU time 2.34 seconds
Started Jul 02 09:10:35 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206380 kb
Host smart-083bf440-9f94-4e99-bfab-f1bf410f0681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17612
46281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1761246281
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.50691822
Short name T805
Test name
Test status
Simulation time 192491167 ps
CPU time 0.82 seconds
Started Jul 02 09:10:25 AM PDT 24
Finished Jul 02 09:10:30 AM PDT 24
Peak memory 206176 kb
Host smart-2f9d55ea-fa73-4ded-b301-4711541da5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50691
822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.50691822
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.4155736303
Short name T583
Test name
Test status
Simulation time 165803214 ps
CPU time 0.81 seconds
Started Jul 02 09:10:23 AM PDT 24
Finished Jul 02 09:10:27 AM PDT 24
Peak memory 206176 kb
Host smart-bfc3c468-3394-4417-96ff-14fce2f442f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41557
36303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.4155736303
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.351010789
Short name T2365
Test name
Test status
Simulation time 238149277 ps
CPU time 0.89 seconds
Started Jul 02 09:10:28 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206136 kb
Host smart-29dc8181-abe7-41cc-a659-9b92b26fffb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35101
0789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.351010789
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.2627533667
Short name T1971
Test name
Test status
Simulation time 5912969738 ps
CPU time 58.9 seconds
Started Jul 02 09:10:23 AM PDT 24
Finished Jul 02 09:11:26 AM PDT 24
Peak memory 206360 kb
Host smart-aee789db-c2f8-4dc1-a13a-2cebf0c669bb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2627533667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.2627533667
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.759463694
Short name T2308
Test name
Test status
Simulation time 219535733 ps
CPU time 0.98 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206200 kb
Host smart-a5d398c2-4fe8-4a8d-8fa5-db95fea38f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75946
3694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.759463694
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1877827401
Short name T405
Test name
Test status
Simulation time 23333962941 ps
CPU time 29.2 seconds
Started Jul 02 09:10:33 AM PDT 24
Finished Jul 02 09:11:05 AM PDT 24
Peak memory 206240 kb
Host smart-e6457415-4156-473b-936f-acbeb7dcb2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18778
27401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1877827401
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1431881783
Short name T591
Test name
Test status
Simulation time 3328595392 ps
CPU time 3.86 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:36 AM PDT 24
Peak memory 206260 kb
Host smart-2a26f882-23f9-4480-b0af-d76ac04bb7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14318
81783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1431881783
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2519018448
Short name T1062
Test name
Test status
Simulation time 7572655942 ps
CPU time 57.11 seconds
Started Jul 02 09:10:24 AM PDT 24
Finished Jul 02 09:11:25 AM PDT 24
Peak memory 206564 kb
Host smart-a22b74b4-3e92-464f-b850-0ec4c84b6ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25190
18448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2519018448
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2080646288
Short name T2247
Test name
Test status
Simulation time 3822221126 ps
CPU time 28.05 seconds
Started Jul 02 09:10:23 AM PDT 24
Finished Jul 02 09:10:56 AM PDT 24
Peak memory 206488 kb
Host smart-b282cace-7203-4256-921b-6e7395eb1d2a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2080646288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2080646288
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.706467859
Short name T548
Test name
Test status
Simulation time 229892968 ps
CPU time 0.88 seconds
Started Jul 02 09:10:23 AM PDT 24
Finished Jul 02 09:10:27 AM PDT 24
Peak memory 206120 kb
Host smart-b4aa7278-a896-431e-919c-59170e3d4fa5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=706467859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.706467859
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1998895146
Short name T2499
Test name
Test status
Simulation time 193382218 ps
CPU time 0.84 seconds
Started Jul 02 09:10:31 AM PDT 24
Finished Jul 02 09:10:36 AM PDT 24
Peak memory 206160 kb
Host smart-a7d82cdf-318c-4a34-a7bd-1f09fe67c511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19988
95146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1998895146
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.498445691
Short name T159
Test name
Test status
Simulation time 3525975812 ps
CPU time 23.56 seconds
Started Jul 02 09:10:30 AM PDT 24
Finished Jul 02 09:10:58 AM PDT 24
Peak memory 206460 kb
Host smart-059c2763-f772-4c12-8868-66ae27681336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49844
5691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.498445691
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.1615157380
Short name T1456
Test name
Test status
Simulation time 4397692845 ps
CPU time 31.92 seconds
Started Jul 02 09:10:28 AM PDT 24
Finished Jul 02 09:11:04 AM PDT 24
Peak memory 206456 kb
Host smart-cf121320-5a74-49cf-bdea-9ae1b8cd1352
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1615157380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.1615157380
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1617189353
Short name T2340
Test name
Test status
Simulation time 154328142 ps
CPU time 0.84 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206192 kb
Host smart-4ab69382-5691-421b-83d4-0afbe6a0d7ea
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1617189353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1617189353
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3444676648
Short name T652
Test name
Test status
Simulation time 138921156 ps
CPU time 0.8 seconds
Started Jul 02 09:10:25 AM PDT 24
Finished Jul 02 09:10:30 AM PDT 24
Peak memory 206212 kb
Host smart-7e07c2bd-6889-4773-82be-11dce0cbfbb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34446
76648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3444676648
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1077005192
Short name T128
Test name
Test status
Simulation time 219318096 ps
CPU time 0.86 seconds
Started Jul 02 09:10:26 AM PDT 24
Finished Jul 02 09:10:31 AM PDT 24
Peak memory 206204 kb
Host smart-9c59bcd6-3a0f-4271-825b-0ef81e89a4a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10770
05192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1077005192
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3952755160
Short name T1595
Test name
Test status
Simulation time 167920052 ps
CPU time 0.86 seconds
Started Jul 02 09:10:25 AM PDT 24
Finished Jul 02 09:10:30 AM PDT 24
Peak memory 206392 kb
Host smart-e79ab8ef-c204-418f-a523-e54a824b2937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39527
55160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3952755160
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.994468446
Short name T2603
Test name
Test status
Simulation time 177606780 ps
CPU time 0.86 seconds
Started Jul 02 09:10:25 AM PDT 24
Finished Jul 02 09:10:31 AM PDT 24
Peak memory 206224 kb
Host smart-b441cf04-928a-4465-af60-1101e912c48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99446
8446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.994468446
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1243016139
Short name T550
Test name
Test status
Simulation time 179430941 ps
CPU time 0.81 seconds
Started Jul 02 09:10:31 AM PDT 24
Finished Jul 02 09:10:36 AM PDT 24
Peak memory 206216 kb
Host smart-7bbf6eb1-3d5e-4755-a48c-8748ab921716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12430
16139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1243016139
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.352916765
Short name T190
Test name
Test status
Simulation time 163552162 ps
CPU time 0.73 seconds
Started Jul 02 09:10:35 AM PDT 24
Finished Jul 02 09:10:38 AM PDT 24
Peak memory 206168 kb
Host smart-992d8ff4-ef1e-4312-a598-ae3524c5c2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35291
6765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.352916765
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2565295690
Short name T908
Test name
Test status
Simulation time 237652621 ps
CPU time 0.91 seconds
Started Jul 02 09:10:32 AM PDT 24
Finished Jul 02 09:10:36 AM PDT 24
Peak memory 206196 kb
Host smart-84cc1833-0f58-4084-be42-d8b9e2737537
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2565295690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2565295690
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3353248621
Short name T615
Test name
Test status
Simulation time 181967560 ps
CPU time 0.82 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:32 AM PDT 24
Peak memory 206208 kb
Host smart-6448cc70-41ae-4a3a-8f7b-8fd16b91efc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33532
48621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3353248621
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3975009703
Short name T1521
Test name
Test status
Simulation time 75463283 ps
CPU time 0.71 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206120 kb
Host smart-306174a6-e82d-4693-a331-79b6acd0548e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39750
09703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3975009703
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2929488937
Short name T2565
Test name
Test status
Simulation time 16022602159 ps
CPU time 36.91 seconds
Started Jul 02 09:10:30 AM PDT 24
Finished Jul 02 09:11:11 AM PDT 24
Peak memory 206544 kb
Host smart-c401600d-cb9e-4dfb-9db3-aa8832c53bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29294
88937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2929488937
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2406011168
Short name T1660
Test name
Test status
Simulation time 232694216 ps
CPU time 0.83 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206216 kb
Host smart-4e38d31e-7777-4718-96e8-e3617ba82f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24060
11168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2406011168
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3741929045
Short name T1531
Test name
Test status
Simulation time 218116050 ps
CPU time 0.88 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206220 kb
Host smart-7eb5f707-68dc-43e0-90c4-c44352fb2c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37419
29045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3741929045
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.377881153
Short name T2559
Test name
Test status
Simulation time 166599058 ps
CPU time 0.87 seconds
Started Jul 02 09:10:26 AM PDT 24
Finished Jul 02 09:10:32 AM PDT 24
Peak memory 206152 kb
Host smart-daf1d994-4c62-47b3-be8a-f75eb698cb98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37788
1153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.377881153
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.4273422665
Short name T2575
Test name
Test status
Simulation time 193817021 ps
CPU time 0.78 seconds
Started Jul 02 09:10:35 AM PDT 24
Finished Jul 02 09:10:38 AM PDT 24
Peak memory 206168 kb
Host smart-fb77b7be-e1e2-4d7e-ba5d-45ba65559b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42734
22665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.4273422665
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1889960450
Short name T493
Test name
Test status
Simulation time 281365430 ps
CPU time 0.89 seconds
Started Jul 02 09:10:26 AM PDT 24
Finished Jul 02 09:10:32 AM PDT 24
Peak memory 206124 kb
Host smart-ad2dddb7-1c3b-42f7-a11c-2d0e7196a0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18899
60450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1889960450
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.29950150
Short name T156
Test name
Test status
Simulation time 170407822 ps
CPU time 0.76 seconds
Started Jul 02 09:10:30 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206196 kb
Host smart-e0ed9bb8-85f0-43fc-8017-ba24490ac216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29950
150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.29950150
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.4023925561
Short name T430
Test name
Test status
Simulation time 209692218 ps
CPU time 0.81 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206184 kb
Host smart-fb849280-ed67-42d1-a7af-1072bfc85f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40239
25561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.4023925561
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.4046812392
Short name T856
Test name
Test status
Simulation time 243486904 ps
CPU time 0.92 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206172 kb
Host smart-618db3d8-97a9-43fe-b492-f6394c2b9a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40468
12392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.4046812392
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2338431274
Short name T2456
Test name
Test status
Simulation time 4148137166 ps
CPU time 39.57 seconds
Started Jul 02 09:10:25 AM PDT 24
Finished Jul 02 09:11:08 AM PDT 24
Peak memory 206452 kb
Host smart-54126615-5b5d-4efd-999f-2b74174680f8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2338431274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2338431274
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3392697213
Short name T1769
Test name
Test status
Simulation time 183393013 ps
CPU time 0.86 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206228 kb
Host smart-6d664eb1-63db-4f43-b54c-ecdb17c9f687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33926
97213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3392697213
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1894765803
Short name T629
Test name
Test status
Simulation time 185188374 ps
CPU time 0.91 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206128 kb
Host smart-0c6d238c-095b-48eb-a5a3-76fcf796fe53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18947
65803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1894765803
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.3029514149
Short name T2305
Test name
Test status
Simulation time 467282615 ps
CPU time 1.26 seconds
Started Jul 02 09:10:37 AM PDT 24
Finished Jul 02 09:10:41 AM PDT 24
Peak memory 206176 kb
Host smart-988fffd8-0037-461f-ab21-447b5c58335a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30295
14149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.3029514149
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.483357645
Short name T945
Test name
Test status
Simulation time 3513171579 ps
CPU time 33.66 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:11:06 AM PDT 24
Peak memory 206424 kb
Host smart-ac296f68-ec2c-4d56-89e3-6e8db42c93d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48335
7645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.483357645
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2186966744
Short name T1674
Test name
Test status
Simulation time 67600521 ps
CPU time 0.69 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:06:36 AM PDT 24
Peak memory 206224 kb
Host smart-efc40774-2369-4b1a-a31a-4ff0f7c90290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2186966744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2186966744
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3502861933
Short name T1796
Test name
Test status
Simulation time 4222281180 ps
CPU time 5.29 seconds
Started Jul 02 09:06:38 AM PDT 24
Finished Jul 02 09:06:44 AM PDT 24
Peak memory 206396 kb
Host smart-3e3d536f-b625-434d-9507-dc627a8a2162
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3502861933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3502861933
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1911313421
Short name T932
Test name
Test status
Simulation time 13358164766 ps
CPU time 12.72 seconds
Started Jul 02 09:06:34 AM PDT 24
Finished Jul 02 09:06:49 AM PDT 24
Peak memory 206284 kb
Host smart-630f197b-2487-436a-9530-9939a8945c62
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1911313421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1911313421
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.1412283032
Short name T2085
Test name
Test status
Simulation time 23453621982 ps
CPU time 21.51 seconds
Started Jul 02 09:06:29 AM PDT 24
Finished Jul 02 09:06:53 AM PDT 24
Peak memory 206456 kb
Host smart-e615966f-73ef-404d-b9a6-2e243b578608
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1412283032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.1412283032
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.4189982908
Short name T1096
Test name
Test status
Simulation time 186244287 ps
CPU time 0.81 seconds
Started Jul 02 09:06:30 AM PDT 24
Finished Jul 02 09:06:33 AM PDT 24
Peak memory 206196 kb
Host smart-26e07322-c38e-45d3-8e2e-0ccf797fb51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41899
82908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.4189982908
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3676036876
Short name T56
Test name
Test status
Simulation time 147095685 ps
CPU time 0.81 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:06:50 AM PDT 24
Peak memory 206192 kb
Host smart-c2ec4817-61d5-497a-91be-7669df6e8e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36760
36876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3676036876
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.3305684357
Short name T50
Test name
Test status
Simulation time 142387048 ps
CPU time 0.87 seconds
Started Jul 02 09:06:29 AM PDT 24
Finished Jul 02 09:06:32 AM PDT 24
Peak memory 206136 kb
Host smart-1c512136-bad7-44e1-834b-7caee1f79b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33056
84357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3305684357
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3255329306
Short name T1107
Test name
Test status
Simulation time 159084514 ps
CPU time 0.79 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:06:35 AM PDT 24
Peak memory 206220 kb
Host smart-2327481a-3a4f-4682-b645-acde3c8b861c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32553
29306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3255329306
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.2693603102
Short name T1786
Test name
Test status
Simulation time 489970394 ps
CPU time 1.47 seconds
Started Jul 02 09:06:29 AM PDT 24
Finished Jul 02 09:06:32 AM PDT 24
Peak memory 206440 kb
Host smart-df65f076-6d84-4075-90b3-e96e3a1f595e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26936
03102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.2693603102
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3040355144
Short name T108
Test name
Test status
Simulation time 757129557 ps
CPU time 1.8 seconds
Started Jul 02 09:06:29 AM PDT 24
Finished Jul 02 09:06:38 AM PDT 24
Peak memory 206396 kb
Host smart-2485cf20-027d-40a8-ac02-726a18843c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30403
55144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3040355144
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1088778005
Short name T1893
Test name
Test status
Simulation time 11205023885 ps
CPU time 24.75 seconds
Started Jul 02 09:06:32 AM PDT 24
Finished Jul 02 09:06:58 AM PDT 24
Peak memory 206424 kb
Host smart-d8a2cbd9-1ddb-4bf1-89ea-b11fb029c3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10887
78005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1088778005
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3578500357
Short name T1432
Test name
Test status
Simulation time 510871787 ps
CPU time 1.43 seconds
Started Jul 02 09:06:29 AM PDT 24
Finished Jul 02 09:06:32 AM PDT 24
Peak memory 206208 kb
Host smart-505d64b6-c35f-4014-835d-81bbf4ce613f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35785
00357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3578500357
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.3344025874
Short name T2530
Test name
Test status
Simulation time 143697909 ps
CPU time 0.77 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:06:31 AM PDT 24
Peak memory 206172 kb
Host smart-4ccca739-cfb1-41cc-be2f-41844f2b871f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33440
25874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.3344025874
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3063855594
Short name T1303
Test name
Test status
Simulation time 44081172 ps
CPU time 0.68 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:06:35 AM PDT 24
Peak memory 206216 kb
Host smart-40136b99-090a-4321-a74a-9b99718ca970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30638
55594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3063855594
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.4238799522
Short name T1306
Test name
Test status
Simulation time 846274945 ps
CPU time 2.19 seconds
Started Jul 02 09:06:30 AM PDT 24
Finished Jul 02 09:06:34 AM PDT 24
Peak memory 206464 kb
Host smart-4fb376f6-99d5-4e0f-8669-5270684f4114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42387
99522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.4238799522
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.862842379
Short name T1154
Test name
Test status
Simulation time 222160547 ps
CPU time 1.33 seconds
Started Jul 02 09:06:36 AM PDT 24
Finished Jul 02 09:06:39 AM PDT 24
Peak memory 206280 kb
Host smart-4169f15c-cb3a-42b7-852f-c3776e56af3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86284
2379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.862842379
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.2336270921
Short name T1186
Test name
Test status
Simulation time 89186441281 ps
CPU time 116.67 seconds
Started Jul 02 09:06:27 AM PDT 24
Finished Jul 02 09:08:24 AM PDT 24
Peak memory 206444 kb
Host smart-835edd94-a286-4ceb-9731-f4f34117077c
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2336270921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.2336270921
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3716271355
Short name T1365
Test name
Test status
Simulation time 118282859929 ps
CPU time 203.1 seconds
Started Jul 02 09:06:32 AM PDT 24
Finished Jul 02 09:09:57 AM PDT 24
Peak memory 206480 kb
Host smart-baa6dc95-8134-49f0-9c59-9543251e3688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716271355 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3716271355
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.3148971768
Short name T1061
Test name
Test status
Simulation time 118093494866 ps
CPU time 148.25 seconds
Started Jul 02 09:06:29 AM PDT 24
Finished Jul 02 09:09:00 AM PDT 24
Peak memory 206424 kb
Host smart-25621d17-bbf8-43c1-9b34-0b6955f42545
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3148971768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.3148971768
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.2469963170
Short name T673
Test name
Test status
Simulation time 90175038234 ps
CPU time 109.24 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:08:24 AM PDT 24
Peak memory 206416 kb
Host smart-13ca2020-cd56-4c59-8624-f756fd43fdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469963170 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.2469963170
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.634581688
Short name T41
Test name
Test status
Simulation time 108155392832 ps
CPU time 157.12 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:09:06 AM PDT 24
Peak memory 206464 kb
Host smart-4ef421d4-aac9-432e-8da1-85719d055626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63458
1688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.634581688
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3171365639
Short name T2344
Test name
Test status
Simulation time 195462239 ps
CPU time 0.84 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:06:36 AM PDT 24
Peak memory 206164 kb
Host smart-27b32c8d-b443-41af-a008-94a9e3cea8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31713
65639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3171365639
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2621147656
Short name T384
Test name
Test status
Simulation time 163242293 ps
CPU time 0.76 seconds
Started Jul 02 09:06:29 AM PDT 24
Finished Jul 02 09:06:32 AM PDT 24
Peak memory 206156 kb
Host smart-8a693bf0-9211-4484-86b1-d461c64bc296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26211
47656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2621147656
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3761826795
Short name T1581
Test name
Test status
Simulation time 235343897 ps
CPU time 0.9 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:06:35 AM PDT 24
Peak memory 206216 kb
Host smart-2c2daa71-7c35-4ea0-a24d-fc6f2c5e0db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37618
26795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3761826795
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3025018701
Short name T2488
Test name
Test status
Simulation time 267799633 ps
CPU time 0.92 seconds
Started Jul 02 09:06:34 AM PDT 24
Finished Jul 02 09:06:37 AM PDT 24
Peak memory 206000 kb
Host smart-4a716be9-8471-4782-81c9-1ebf585d3ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30250
18701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3025018701
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.4246714738
Short name T875
Test name
Test status
Simulation time 23353499517 ps
CPU time 28.21 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:06:59 AM PDT 24
Peak memory 206240 kb
Host smart-567d29af-5721-4706-9f2e-458a00d86f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42467
14738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.4246714738
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.4127892291
Short name T1675
Test name
Test status
Simulation time 3294210656 ps
CPU time 3.96 seconds
Started Jul 02 09:06:40 AM PDT 24
Finished Jul 02 09:06:45 AM PDT 24
Peak memory 206256 kb
Host smart-d20fe81e-47dc-4c5b-92c7-d26e73d431a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41278
92291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.4127892291
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.3772893967
Short name T1709
Test name
Test status
Simulation time 10081601247 ps
CPU time 101.11 seconds
Started Jul 02 09:06:36 AM PDT 24
Finished Jul 02 09:08:19 AM PDT 24
Peak memory 206400 kb
Host smart-386335f3-f0a4-4216-adce-e9de016b35f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37728
93967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.3772893967
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.2313914068
Short name T2647
Test name
Test status
Simulation time 6703017727 ps
CPU time 187.84 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:09:38 AM PDT 24
Peak memory 206416 kb
Host smart-6512781d-2940-48c0-b097-a8b82df7c25c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2313914068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.2313914068
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.969006096
Short name T879
Test name
Test status
Simulation time 255732032 ps
CPU time 0.91 seconds
Started Jul 02 09:06:34 AM PDT 24
Finished Jul 02 09:06:37 AM PDT 24
Peak memory 206176 kb
Host smart-8a09ee7d-9e28-41c2-9b93-5d96e41f8dcf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=969006096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.969006096
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2766182145
Short name T661
Test name
Test status
Simulation time 221270474 ps
CPU time 0.87 seconds
Started Jul 02 09:06:28 AM PDT 24
Finished Jul 02 09:06:31 AM PDT 24
Peak memory 206216 kb
Host smart-07933087-8440-459e-a97a-c02950063601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27661
82145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2766182145
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2943072685
Short name T2213
Test name
Test status
Simulation time 4355453996 ps
CPU time 42.99 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:07:30 AM PDT 24
Peak memory 206456 kb
Host smart-6d1824c7-b5a6-4fee-afa9-12146cef59a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29430
72685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2943072685
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3947933365
Short name T1567
Test name
Test status
Simulation time 3750488154 ps
CPU time 32.56 seconds
Started Jul 02 09:06:32 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206516 kb
Host smart-98934ddb-0213-4c6e-b83b-54baef9ce9ef
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3947933365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3947933365
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3742910684
Short name T834
Test name
Test status
Simulation time 165488319 ps
CPU time 0.77 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:06:35 AM PDT 24
Peak memory 206176 kb
Host smart-dab78f30-0927-4c9a-9f5c-f95d517880c3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3742910684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3742910684
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1170248306
Short name T382
Test name
Test status
Simulation time 167839623 ps
CPU time 0.78 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:06:47 AM PDT 24
Peak memory 206208 kb
Host smart-d5faccf8-ace9-4dd0-8208-5575ffb025e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11702
48306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1170248306
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1470839669
Short name T2376
Test name
Test status
Simulation time 214737219 ps
CPU time 0.93 seconds
Started Jul 02 09:06:34 AM PDT 24
Finished Jul 02 09:06:37 AM PDT 24
Peak memory 206160 kb
Host smart-f51ff5a3-f041-4d68-9725-0c85f0eb539f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14708
39669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1470839669
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2795594265
Short name T2692
Test name
Test status
Simulation time 173399158 ps
CPU time 0.8 seconds
Started Jul 02 09:06:31 AM PDT 24
Finished Jul 02 09:06:33 AM PDT 24
Peak memory 206216 kb
Host smart-a2efec51-2220-4f4a-ae8a-f458e30db542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27955
94265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2795594265
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3128694187
Short name T2476
Test name
Test status
Simulation time 202125304 ps
CPU time 0.86 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:06:48 AM PDT 24
Peak memory 206080 kb
Host smart-ffe0e708-3794-4192-a780-e516a1ffa329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31286
94187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3128694187
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.343134900
Short name T1632
Test name
Test status
Simulation time 174349705 ps
CPU time 0.83 seconds
Started Jul 02 09:06:32 AM PDT 24
Finished Jul 02 09:06:35 AM PDT 24
Peak memory 206200 kb
Host smart-cb03fe7c-0ca8-4639-8c1b-0be66d5f6bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34313
4900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.343134900
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2441629114
Short name T2394
Test name
Test status
Simulation time 161254458 ps
CPU time 0.79 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:06:45 AM PDT 24
Peak memory 206216 kb
Host smart-d67af5ea-312a-4c9a-92c9-898520e960ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24416
29114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2441629114
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.1092878044
Short name T612
Test name
Test status
Simulation time 191190929 ps
CPU time 0.85 seconds
Started Jul 02 09:06:32 AM PDT 24
Finished Jul 02 09:06:34 AM PDT 24
Peak memory 206192 kb
Host smart-01e8638c-6256-430d-9fdf-3014bac31d45
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1092878044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.1092878044
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.4101554633
Short name T220
Test name
Test status
Simulation time 278691624 ps
CPU time 0.95 seconds
Started Jul 02 09:06:34 AM PDT 24
Finished Jul 02 09:06:37 AM PDT 24
Peak memory 206172 kb
Host smart-cad073fe-2030-4ac0-b6c7-ced465218cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41015
54633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.4101554633
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2742972526
Short name T1376
Test name
Test status
Simulation time 153124443 ps
CPU time 0.8 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:06:49 AM PDT 24
Peak memory 206080 kb
Host smart-16a68c52-ad82-425c-a61b-407b216efdae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27429
72526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2742972526
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2747810088
Short name T1749
Test name
Test status
Simulation time 32756904 ps
CPU time 0.66 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:06:36 AM PDT 24
Peak memory 206220 kb
Host smart-3b80465d-9edd-4e2d-9036-43b59a1de530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27478
10088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2747810088
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1616379064
Short name T1022
Test name
Test status
Simulation time 11088619140 ps
CPU time 24.95 seconds
Started Jul 02 09:06:40 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206484 kb
Host smart-59e194ed-41e6-4dbf-a90a-8eadc16e6c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16163
79064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1616379064
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2795396174
Short name T1952
Test name
Test status
Simulation time 171896899 ps
CPU time 0.82 seconds
Started Jul 02 09:06:35 AM PDT 24
Finished Jul 02 09:06:38 AM PDT 24
Peak memory 206188 kb
Host smart-40baf4ea-4051-4218-8f6f-997619c6ef32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27953
96174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2795396174
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3614688589
Short name T1996
Test name
Test status
Simulation time 175952297 ps
CPU time 0.8 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:06:50 AM PDT 24
Peak memory 206200 kb
Host smart-55cdd910-5fbe-47f3-8a1a-ddf88751a2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36146
88589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3614688589
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.2787557642
Short name T996
Test name
Test status
Simulation time 19776252200 ps
CPU time 539.76 seconds
Started Jul 02 09:06:34 AM PDT 24
Finished Jul 02 09:15:35 AM PDT 24
Peak memory 206524 kb
Host smart-564d6330-d7ed-4ec8-9047-90e6cb380a14
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2787557642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2787557642
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.407146514
Short name T931
Test name
Test status
Simulation time 7805504901 ps
CPU time 111.45 seconds
Started Jul 02 09:06:33 AM PDT 24
Finished Jul 02 09:08:27 AM PDT 24
Peak memory 206520 kb
Host smart-b1842bb1-452c-410f-ba9f-c0a68a349900
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=407146514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.407146514
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.983767231
Short name T1099
Test name
Test status
Simulation time 190503060 ps
CPU time 0.95 seconds
Started Jul 02 09:06:38 AM PDT 24
Finished Jul 02 09:06:40 AM PDT 24
Peak memory 206204 kb
Host smart-8ad6ad29-10a7-4da4-a802-43c6c7358eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98376
7231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.983767231
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3044794505
Short name T2620
Test name
Test status
Simulation time 170761667 ps
CPU time 0.88 seconds
Started Jul 02 09:06:37 AM PDT 24
Finished Jul 02 09:06:39 AM PDT 24
Peak memory 206188 kb
Host smart-bcde1a75-ffd1-42e2-b9f4-f6d39e0e9d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30447
94505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3044794505
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.945054952
Short name T1382
Test name
Test status
Simulation time 191970365 ps
CPU time 0.82 seconds
Started Jul 02 09:06:32 AM PDT 24
Finished Jul 02 09:06:35 AM PDT 24
Peak memory 206172 kb
Host smart-cfad5309-f4f5-466b-9ec4-b9759fe75419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94505
4952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.945054952
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.3391990485
Short name T2131
Test name
Test status
Simulation time 177246651 ps
CPU time 0.81 seconds
Started Jul 02 09:06:36 AM PDT 24
Finished Jul 02 09:06:39 AM PDT 24
Peak memory 206208 kb
Host smart-324c6fe9-f11c-4984-b2d6-dd5c67bbe5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33919
90485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.3391990485
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2159332664
Short name T211
Test name
Test status
Simulation time 856402320 ps
CPU time 1.73 seconds
Started Jul 02 09:06:34 AM PDT 24
Finished Jul 02 09:06:37 AM PDT 24
Peak memory 225256 kb
Host smart-3318bd3f-6e2c-4699-980a-f8d5ed753d4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2159332664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2159332664
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.2106011084
Short name T1381
Test name
Test status
Simulation time 400553812 ps
CPU time 1.27 seconds
Started Jul 02 09:06:46 AM PDT 24
Finished Jul 02 09:06:50 AM PDT 24
Peak memory 206196 kb
Host smart-2a932ab7-7840-477c-975c-a1690e23ffc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21060
11084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.2106011084
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.3557768744
Short name T726
Test name
Test status
Simulation time 278899116 ps
CPU time 0.99 seconds
Started Jul 02 09:06:32 AM PDT 24
Finished Jul 02 09:06:35 AM PDT 24
Peak memory 206144 kb
Host smart-031dea4c-4841-4960-8519-acb85a1825ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35577
68744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.3557768744
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3082354417
Short name T1820
Test name
Test status
Simulation time 193680724 ps
CPU time 0.85 seconds
Started Jul 02 09:06:42 AM PDT 24
Finished Jul 02 09:06:44 AM PDT 24
Peak memory 206208 kb
Host smart-343a9efc-a671-4871-8987-054d21456f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30823
54417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3082354417
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.905656540
Short name T2163
Test name
Test status
Simulation time 178431356 ps
CPU time 0.76 seconds
Started Jul 02 09:06:35 AM PDT 24
Finished Jul 02 09:06:38 AM PDT 24
Peak memory 206188 kb
Host smart-a2e4ee47-ed43-4a7f-8204-6dd49bffecfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90565
6540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.905656540
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1989535428
Short name T832
Test name
Test status
Simulation time 183280785 ps
CPU time 0.88 seconds
Started Jul 02 09:06:38 AM PDT 24
Finished Jul 02 09:06:41 AM PDT 24
Peak memory 206164 kb
Host smart-a230eaa8-edbc-4817-bc3e-d36ccc249ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
35428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1989535428
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.2184204941
Short name T1742
Test name
Test status
Simulation time 5183753154 ps
CPU time 35.89 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:07:25 AM PDT 24
Peak memory 206508 kb
Host smart-a1f8046f-d67c-4b9f-93ed-828606c83515
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2184204941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2184204941
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1082648113
Short name T2543
Test name
Test status
Simulation time 228504919 ps
CPU time 0.95 seconds
Started Jul 02 09:06:31 AM PDT 24
Finished Jul 02 09:06:34 AM PDT 24
Peak memory 206204 kb
Host smart-326709e1-8d83-46e2-9421-2ba237119c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10826
48113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1082648113
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3752304258
Short name T2296
Test name
Test status
Simulation time 186831133 ps
CPU time 0.85 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:06:47 AM PDT 24
Peak memory 206076 kb
Host smart-459ab8c6-f089-43df-beb3-72e75e342ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37523
04258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3752304258
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3021455528
Short name T815
Test name
Test status
Simulation time 938725815 ps
CPU time 2.21 seconds
Started Jul 02 09:06:34 AM PDT 24
Finished Jul 02 09:06:38 AM PDT 24
Peak memory 206440 kb
Host smart-e5603b99-92fe-4131-83da-3ed0272d9e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30214
55528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3021455528
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.3192149969
Short name T1113
Test name
Test status
Simulation time 3585870899 ps
CPU time 24.15 seconds
Started Jul 02 09:06:42 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206524 kb
Host smart-8941a724-2b2c-41e2-9649-2cdc3649de9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31921
49969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.3192149969
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.166312229
Short name T174
Test name
Test status
Simulation time 15326611097 ps
CPU time 87.99 seconds
Started Jul 02 09:06:44 AM PDT 24
Finished Jul 02 09:08:13 AM PDT 24
Peak memory 206376 kb
Host smart-ad42385d-d4bc-41a7-80eb-af8b2426ac88
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=166312229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.166312229
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.600029608
Short name T844
Test name
Test status
Simulation time 36909034 ps
CPU time 0.66 seconds
Started Jul 02 09:10:38 AM PDT 24
Finished Jul 02 09:10:42 AM PDT 24
Peak memory 206396 kb
Host smart-ed237e2e-fb8d-4e89-81a0-fee36aa9a522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=600029608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.600029608
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1253031325
Short name T848
Test name
Test status
Simulation time 4363319607 ps
CPU time 5.96 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:45 AM PDT 24
Peak memory 206400 kb
Host smart-71196aeb-d726-428a-953b-baeddd8bc712
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1253031325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.1253031325
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2617343759
Short name T1290
Test name
Test status
Simulation time 13350984761 ps
CPU time 13.5 seconds
Started Jul 02 09:10:31 AM PDT 24
Finished Jul 02 09:10:48 AM PDT 24
Peak memory 206252 kb
Host smart-077ed991-e8ef-47bc-be1b-c50f0a29cff4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2617343759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2617343759
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1021327172
Short name T1155
Test name
Test status
Simulation time 23417761134 ps
CPU time 23.38 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:57 AM PDT 24
Peak memory 206456 kb
Host smart-b77a93d1-1082-47a4-828c-9d20b06696f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1021327172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1021327172
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.21591468
Short name T441
Test name
Test status
Simulation time 154769835 ps
CPU time 0.78 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206196 kb
Host smart-e508f5f1-a5f7-43b0-8741-0a7bff0a7186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21591
468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.21591468
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1476887556
Short name T2492
Test name
Test status
Simulation time 233818962 ps
CPU time 0.89 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206188 kb
Host smart-e64ca951-dd50-4328-822c-f04331986cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14768
87556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1476887556
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.2354487771
Short name T917
Test name
Test status
Simulation time 301146277 ps
CPU time 1.04 seconds
Started Jul 02 09:10:30 AM PDT 24
Finished Jul 02 09:10:36 AM PDT 24
Peak memory 206224 kb
Host smart-7c423b4c-2f2b-4965-9193-bf96978b5fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23544
87771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.2354487771
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2064982721
Short name T1907
Test name
Test status
Simulation time 883910517 ps
CPU time 2.29 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:36 AM PDT 24
Peak memory 206444 kb
Host smart-ebb944bb-8353-4517-a532-426122c9eba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20649
82721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2064982721
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.1593964390
Short name T1299
Test name
Test status
Simulation time 12799288975 ps
CPU time 25.92 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:58 AM PDT 24
Peak memory 206512 kb
Host smart-59acf732-74e2-46ad-a621-a7f5ae3c23fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15939
64390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.1593964390
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1368647932
Short name T1646
Test name
Test status
Simulation time 354251604 ps
CPU time 1.28 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206204 kb
Host smart-568cd3c2-e592-429f-bc3b-8496664d9cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13686
47932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1368647932
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1860544877
Short name T653
Test name
Test status
Simulation time 145241544 ps
CPU time 0.77 seconds
Started Jul 02 09:10:34 AM PDT 24
Finished Jul 02 09:10:38 AM PDT 24
Peak memory 206188 kb
Host smart-13921d7a-d248-4b21-aa42-865b8637818d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18605
44877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1860544877
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.24025224
Short name T355
Test name
Test status
Simulation time 77658071 ps
CPU time 0.68 seconds
Started Jul 02 09:10:35 AM PDT 24
Finished Jul 02 09:10:39 AM PDT 24
Peak memory 206180 kb
Host smart-68560d7c-a780-4e99-9b68-08409d20e0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24025
224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.24025224
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3952542866
Short name T634
Test name
Test status
Simulation time 716649838 ps
CPU time 1.89 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:34 AM PDT 24
Peak memory 206404 kb
Host smart-a8efb7a3-f7cd-46a8-b6d7-ffc1b3908950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39525
42866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3952542866
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.923959356
Short name T1442
Test name
Test status
Simulation time 389904003 ps
CPU time 2.49 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:41 AM PDT 24
Peak memory 206408 kb
Host smart-fe5bb00c-be33-41c6-a0a6-4865b3b2d656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92395
9356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.923959356
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.793085819
Short name T352
Test name
Test status
Simulation time 205641901 ps
CPU time 0.88 seconds
Started Jul 02 09:10:28 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 206196 kb
Host smart-71b68e7b-f395-4a01-8f10-47111cff3118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79308
5819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.793085819
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.357432240
Short name T1026
Test name
Test status
Simulation time 176998388 ps
CPU time 0.78 seconds
Started Jul 02 09:10:29 AM PDT 24
Finished Jul 02 09:10:35 AM PDT 24
Peak memory 206216 kb
Host smart-414e8ce5-ee4f-42b5-80a4-d00ff258d96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35743
2240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.357432240
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3601742504
Short name T2122
Test name
Test status
Simulation time 221883887 ps
CPU time 0.87 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206168 kb
Host smart-16446847-1c26-4e07-a5b5-da121edcb729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36017
42504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3601742504
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1927341782
Short name T2064
Test name
Test status
Simulation time 218045762 ps
CPU time 0.95 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206172 kb
Host smart-56c094c7-5b7c-4ff8-a653-e2a9f7ce4e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19273
41782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1927341782
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.1191523110
Short name T477
Test name
Test status
Simulation time 23387907216 ps
CPU time 22.22 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:11:02 AM PDT 24
Peak memory 206228 kb
Host smart-3289895b-2e88-46b2-a046-d59f0e3b8501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11915
23110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1191523110
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2181406043
Short name T2142
Test name
Test status
Simulation time 3296565657 ps
CPU time 3.78 seconds
Started Jul 02 09:10:27 AM PDT 24
Finished Jul 02 09:10:36 AM PDT 24
Peak memory 206264 kb
Host smart-a055055a-1dac-4c46-a37b-8c8ecd3feb96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21814
06043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2181406043
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.3751614045
Short name T1033
Test name
Test status
Simulation time 12691907634 ps
CPU time 126.72 seconds
Started Jul 02 09:10:34 AM PDT 24
Finished Jul 02 09:12:44 AM PDT 24
Peak memory 206532 kb
Host smart-e420fbb4-aa7c-419d-9a5d-b259e40a642f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37516
14045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.3751614045
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3066506710
Short name T2319
Test name
Test status
Simulation time 3816149900 ps
CPU time 28.85 seconds
Started Jul 02 09:10:37 AM PDT 24
Finished Jul 02 09:11:08 AM PDT 24
Peak memory 206312 kb
Host smart-d15aa145-a32e-4f51-a4dc-dfa3a0df29c4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3066506710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3066506710
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2203339509
Short name T1407
Test name
Test status
Simulation time 241826537 ps
CPU time 0.94 seconds
Started Jul 02 09:10:35 AM PDT 24
Finished Jul 02 09:10:39 AM PDT 24
Peak memory 206200 kb
Host smart-878c1fec-712a-4b10-8a65-afaab01d3534
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2203339509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2203339509
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.4207738826
Short name T2545
Test name
Test status
Simulation time 191867411 ps
CPU time 0.89 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:39 AM PDT 24
Peak memory 206228 kb
Host smart-516f2f63-8d84-4ff4-9420-088f7b1151f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42077
38826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.4207738826
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.3926529160
Short name T2491
Test name
Test status
Simulation time 5897391422 ps
CPU time 55.17 seconds
Started Jul 02 09:10:38 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206508 kb
Host smart-56884385-04c5-41ca-b7e4-ba94b10915ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265
29160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.3926529160
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2965805589
Short name T845
Test name
Test status
Simulation time 5256281153 ps
CPU time 36.86 seconds
Started Jul 02 09:10:39 AM PDT 24
Finished Jul 02 09:11:18 AM PDT 24
Peak memory 206496 kb
Host smart-1102e637-23b5-43a7-9de7-0bf2085a185b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2965805589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2965805589
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2082511820
Short name T2584
Test name
Test status
Simulation time 153703056 ps
CPU time 0.82 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206188 kb
Host smart-a4364fb4-2cd3-433c-8420-e662d92c1df8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2082511820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2082511820
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.125228384
Short name T1860
Test name
Test status
Simulation time 144747879 ps
CPU time 0.74 seconds
Started Jul 02 09:10:32 AM PDT 24
Finished Jul 02 09:10:37 AM PDT 24
Peak memory 206224 kb
Host smart-a4895979-77b6-4665-8e38-ea4af18c45b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12522
8384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.125228384
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3507351111
Short name T142
Test name
Test status
Simulation time 239417488 ps
CPU time 0.86 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206212 kb
Host smart-ca7fbcce-6a76-4146-b272-c7e0436d54b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35073
51111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3507351111
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1961933851
Short name T2192
Test name
Test status
Simulation time 142926418 ps
CPU time 0.77 seconds
Started Jul 02 09:10:40 AM PDT 24
Finished Jul 02 09:10:43 AM PDT 24
Peak memory 206172 kb
Host smart-eb0c9283-9a58-49aa-9787-f9d4c961a120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19619
33851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1961933851
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2293635473
Short name T2484
Test name
Test status
Simulation time 182787252 ps
CPU time 0.84 seconds
Started Jul 02 09:10:33 AM PDT 24
Finished Jul 02 09:10:37 AM PDT 24
Peak memory 206196 kb
Host smart-477301f2-c9be-407c-84bf-70828e10335c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22936
35473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2293635473
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2665096347
Short name T1727
Test name
Test status
Simulation time 190305993 ps
CPU time 0.89 seconds
Started Jul 02 09:10:37 AM PDT 24
Finished Jul 02 09:10:41 AM PDT 24
Peak memory 206176 kb
Host smart-87b574ca-6b79-478f-9c39-7b482b15f283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26650
96347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2665096347
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1866310530
Short name T1693
Test name
Test status
Simulation time 196624779 ps
CPU time 0.79 seconds
Started Jul 02 09:10:35 AM PDT 24
Finished Jul 02 09:10:38 AM PDT 24
Peak memory 206200 kb
Host smart-cf414086-55eb-4b1c-a4b7-a5edc151387f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18663
10530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1866310530
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.3612391247
Short name T1925
Test name
Test status
Simulation time 187543715 ps
CPU time 0.87 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206192 kb
Host smart-1f903ae9-9700-4f81-b941-1d3ce2bcdbea
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3612391247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3612391247
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2979337862
Short name T1134
Test name
Test status
Simulation time 180360613 ps
CPU time 0.8 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:10:40 AM PDT 24
Peak memory 206132 kb
Host smart-67484bbd-324b-4811-8254-a9cb9af871ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29793
37862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2979337862
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.7849298
Short name T38
Test name
Test status
Simulation time 44438284 ps
CPU time 0.67 seconds
Started Jul 02 09:10:35 AM PDT 24
Finished Jul 02 09:10:38 AM PDT 24
Peak memory 206384 kb
Host smart-df4d07c8-827e-4c7a-8306-5467875770af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78492
98 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.7849298
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3930150795
Short name T1405
Test name
Test status
Simulation time 20582213787 ps
CPU time 52.01 seconds
Started Jul 02 09:10:33 AM PDT 24
Finished Jul 02 09:11:28 AM PDT 24
Peak memory 206504 kb
Host smart-034a5066-6e06-4785-b8ce-5eca54b9e54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
50795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3930150795
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3449947328
Short name T495
Test name
Test status
Simulation time 177252364 ps
CPU time 0.86 seconds
Started Jul 02 09:10:39 AM PDT 24
Finished Jul 02 09:10:42 AM PDT 24
Peak memory 206204 kb
Host smart-cb486391-847e-4182-9052-d4f67ad30856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34499
47328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3449947328
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3927114654
Short name T1479
Test name
Test status
Simulation time 221775515 ps
CPU time 0.89 seconds
Started Jul 02 09:10:34 AM PDT 24
Finished Jul 02 09:10:38 AM PDT 24
Peak memory 206340 kb
Host smart-1632d736-5e19-4ced-b277-67b143c92451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39271
14654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3927114654
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3874307692
Short name T1321
Test name
Test status
Simulation time 201526125 ps
CPU time 0.88 seconds
Started Jul 02 09:10:35 AM PDT 24
Finished Jul 02 09:10:39 AM PDT 24
Peak memory 206180 kb
Host smart-037f4cf8-d882-41dd-8657-47bdac6b3fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38743
07692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3874307692
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.70504752
Short name T2207
Test name
Test status
Simulation time 199243500 ps
CPU time 0.87 seconds
Started Jul 02 09:10:35 AM PDT 24
Finished Jul 02 09:10:39 AM PDT 24
Peak memory 206204 kb
Host smart-e5c6740d-2950-4cdf-91bc-db363f9a3edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70504
752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.70504752
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2689700260
Short name T2272
Test name
Test status
Simulation time 152007237 ps
CPU time 0.85 seconds
Started Jul 02 09:10:33 AM PDT 24
Finished Jul 02 09:10:38 AM PDT 24
Peak memory 206212 kb
Host smart-65893c86-73b3-4827-81ab-245c871fc526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26897
00260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2689700260
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2348666468
Short name T2664
Test name
Test status
Simulation time 142658337 ps
CPU time 0.76 seconds
Started Jul 02 09:10:38 AM PDT 24
Finished Jul 02 09:10:42 AM PDT 24
Peak memory 206124 kb
Host smart-33651db0-8d49-4bb1-a63c-44bab279c67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23486
66468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2348666468
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.159209794
Short name T2096
Test name
Test status
Simulation time 197318330 ps
CPU time 0.8 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:10:44 AM PDT 24
Peak memory 206204 kb
Host smart-acd3dfb1-102e-4ad7-97c2-d203229a124f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15920
9794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.159209794
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.948425964
Short name T1236
Test name
Test status
Simulation time 245332461 ps
CPU time 0.94 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:10:44 AM PDT 24
Peak memory 206180 kb
Host smart-3267a6a9-40c7-4351-8606-329a6a839baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94842
5964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.948425964
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.3980339278
Short name T1921
Test name
Test status
Simulation time 6920521001 ps
CPU time 198.03 seconds
Started Jul 02 09:10:39 AM PDT 24
Finished Jul 02 09:14:00 AM PDT 24
Peak memory 206492 kb
Host smart-f6e2f482-45e3-4655-80bb-d07d299f9ca9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3980339278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.3980339278
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1472176055
Short name T1197
Test name
Test status
Simulation time 157121315 ps
CPU time 0.75 seconds
Started Jul 02 09:10:38 AM PDT 24
Finished Jul 02 09:10:41 AM PDT 24
Peak memory 206180 kb
Host smart-02c5648e-3119-4ac1-ab7a-385297673f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14721
76055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1472176055
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.851088779
Short name T1948
Test name
Test status
Simulation time 185561028 ps
CPU time 0.83 seconds
Started Jul 02 09:10:41 AM PDT 24
Finished Jul 02 09:10:44 AM PDT 24
Peak memory 206196 kb
Host smart-6adb4804-7f0b-44de-a89c-e1880f0baa0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85108
8779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.851088779
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.2959531713
Short name T2016
Test name
Test status
Simulation time 340823134 ps
CPU time 1.11 seconds
Started Jul 02 09:10:38 AM PDT 24
Finished Jul 02 09:10:42 AM PDT 24
Peak memory 206160 kb
Host smart-acedb08c-82d7-4b19-8ef2-8f0896b174b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29595
31713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.2959531713
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.1985396104
Short name T1170
Test name
Test status
Simulation time 4025441033 ps
CPU time 40.27 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:11:19 AM PDT 24
Peak memory 206432 kb
Host smart-fd7bda17-bfbb-486f-98ca-3e7d88f2fe15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19853
96104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.1985396104
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2343772637
Short name T2427
Test name
Test status
Simulation time 71777525 ps
CPU time 0.73 seconds
Started Jul 02 09:10:46 AM PDT 24
Finished Jul 02 09:10:48 AM PDT 24
Peak memory 206252 kb
Host smart-958f1147-0aac-4c6b-9554-908c5fefbc4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2343772637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2343772637
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.426549431
Short name T1900
Test name
Test status
Simulation time 3981127275 ps
CPU time 5 seconds
Started Jul 02 09:10:37 AM PDT 24
Finished Jul 02 09:10:45 AM PDT 24
Peak memory 206248 kb
Host smart-984f165a-d7dd-4942-bc65-85b048ca13b9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=426549431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.426549431
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1506121415
Short name T657
Test name
Test status
Simulation time 13338194473 ps
CPU time 13.16 seconds
Started Jul 02 09:10:38 AM PDT 24
Finished Jul 02 09:10:54 AM PDT 24
Peak memory 206224 kb
Host smart-a8d79261-70b9-4cdd-bdff-05561e63c0b4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1506121415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1506121415
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2391877700
Short name T2588
Test name
Test status
Simulation time 23373176725 ps
CPU time 23.13 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:11:02 AM PDT 24
Peak memory 206248 kb
Host smart-ca8f7a06-fb4a-4584-9813-fce6798e5bae
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2391877700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.2391877700
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1104326437
Short name T2184
Test name
Test status
Simulation time 179043503 ps
CPU time 0.82 seconds
Started Jul 02 09:10:37 AM PDT 24
Finished Jul 02 09:10:41 AM PDT 24
Peak memory 206220 kb
Host smart-9104fc66-a259-4976-81af-329ab03f08cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11043
26437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1104326437
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.724161151
Short name T2498
Test name
Test status
Simulation time 210872261 ps
CPU time 0.89 seconds
Started Jul 02 09:10:41 AM PDT 24
Finished Jul 02 09:10:43 AM PDT 24
Peak memory 206188 kb
Host smart-dafc068a-1439-42ab-827b-250a9bf3fa71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72416
1151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.724161151
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.331185998
Short name T193
Test name
Test status
Simulation time 462821992 ps
CPU time 1.38 seconds
Started Jul 02 09:10:37 AM PDT 24
Finished Jul 02 09:10:41 AM PDT 24
Peak memory 206180 kb
Host smart-654808e7-4241-4758-9a2d-a69d2af271c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33118
5998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.331185998
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3376688076
Short name T1559
Test name
Test status
Simulation time 1339874475 ps
CPU time 3.1 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:10:47 AM PDT 24
Peak memory 206380 kb
Host smart-2680f09d-aace-46fd-b0de-ea925e6de95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33766
88076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3376688076
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.983781656
Short name T1209
Test name
Test status
Simulation time 15296146293 ps
CPU time 27.62 seconds
Started Jul 02 09:10:36 AM PDT 24
Finished Jul 02 09:11:07 AM PDT 24
Peak memory 206520 kb
Host smart-1bcb6f4a-4bb5-459e-8dce-ffef0dce606d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98378
1656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.983781656
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3521927224
Short name T770
Test name
Test status
Simulation time 508610870 ps
CPU time 1.48 seconds
Started Jul 02 09:10:38 AM PDT 24
Finished Jul 02 09:10:42 AM PDT 24
Peak memory 206152 kb
Host smart-91351d92-86f1-49ae-8ea3-09c380b773d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35219
27224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3521927224
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1926682922
Short name T2070
Test name
Test status
Simulation time 160377918 ps
CPU time 0.75 seconds
Started Jul 02 09:10:39 AM PDT 24
Finished Jul 02 09:10:42 AM PDT 24
Peak memory 206208 kb
Host smart-7020d544-7eab-4a95-8bbc-cf1c8bba88a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19266
82922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1926682922
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3598215366
Short name T2399
Test name
Test status
Simulation time 40401843 ps
CPU time 0.67 seconds
Started Jul 02 09:10:37 AM PDT 24
Finished Jul 02 09:10:41 AM PDT 24
Peak memory 206208 kb
Host smart-717db055-a500-4d61-9814-3119cffc53d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35982
15366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3598215366
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1590429375
Short name T2523
Test name
Test status
Simulation time 816805784 ps
CPU time 2.2 seconds
Started Jul 02 09:10:43 AM PDT 24
Finished Jul 02 09:10:46 AM PDT 24
Peak memory 206356 kb
Host smart-ce4797a2-b806-4473-9cee-80f0ed286b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15904
29375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1590429375
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2708431868
Short name T451
Test name
Test status
Simulation time 158823503 ps
CPU time 1.41 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:10:45 AM PDT 24
Peak memory 206312 kb
Host smart-3ff9b9e0-b2b8-4af0-b286-1340f09b06a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27084
31868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2708431868
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3168648916
Short name T533
Test name
Test status
Simulation time 253450439 ps
CPU time 0.94 seconds
Started Jul 02 09:10:43 AM PDT 24
Finished Jul 02 09:10:46 AM PDT 24
Peak memory 206212 kb
Host smart-8a6a6428-050a-449d-9f04-732d5eb31256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31686
48916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3168648916
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.501344553
Short name T659
Test name
Test status
Simulation time 137519617 ps
CPU time 0.75 seconds
Started Jul 02 09:10:39 AM PDT 24
Finished Jul 02 09:10:42 AM PDT 24
Peak memory 206176 kb
Host smart-6ee60fd1-f847-46af-a642-f78251d0c86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50134
4553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.501344553
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1521077432
Short name T1203
Test name
Test status
Simulation time 250629578 ps
CPU time 0.93 seconds
Started Jul 02 09:10:38 AM PDT 24
Finished Jul 02 09:10:42 AM PDT 24
Peak memory 206216 kb
Host smart-8165ead7-11f5-42b1-bf25-b4763c342bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210
77432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1521077432
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.1198257509
Short name T1017
Test name
Test status
Simulation time 7386617487 ps
CPU time 65.03 seconds
Started Jul 02 09:10:38 AM PDT 24
Finished Jul 02 09:11:46 AM PDT 24
Peak memory 206452 kb
Host smart-28abcfb0-6b84-4691-8dc3-57e80f765ced
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1198257509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.1198257509
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.2153790004
Short name T624
Test name
Test status
Simulation time 223281972 ps
CPU time 0.91 seconds
Started Jul 02 09:10:43 AM PDT 24
Finished Jul 02 09:10:45 AM PDT 24
Peak memory 206196 kb
Host smart-9e1668d8-89f2-4f7e-bc42-6d4bdd13d0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21537
90004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.2153790004
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1363165870
Short name T923
Test name
Test status
Simulation time 23320579174 ps
CPU time 24.31 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:11:08 AM PDT 24
Peak memory 206236 kb
Host smart-b1d79ad2-a9c5-49ac-b76c-477e1cd1b02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13631
65870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1363165870
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3967257730
Short name T1493
Test name
Test status
Simulation time 3266968819 ps
CPU time 4.22 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:10:48 AM PDT 24
Peak memory 206264 kb
Host smart-f2152a97-66f8-4dc7-af1d-250071f90899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39672
57730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3967257730
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2441130033
Short name T1799
Test name
Test status
Simulation time 12327071963 ps
CPU time 85.26 seconds
Started Jul 02 09:10:45 AM PDT 24
Finished Jul 02 09:12:11 AM PDT 24
Peak memory 206528 kb
Host smart-3cc22732-db58-4488-9e7f-538c87373a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24411
30033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2441130033
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.3911559210
Short name T1575
Test name
Test status
Simulation time 3897856658 ps
CPU time 105.23 seconds
Started Jul 02 09:10:43 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206460 kb
Host smart-b94c9cf2-4cdf-48af-a982-935097ca53af
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3911559210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.3911559210
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3239478164
Short name T705
Test name
Test status
Simulation time 247823893 ps
CPU time 0.9 seconds
Started Jul 02 09:10:40 AM PDT 24
Finished Jul 02 09:10:43 AM PDT 24
Peak memory 206148 kb
Host smart-5837c7be-39fd-4b02-b090-73ad38108f4a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3239478164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3239478164
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3685170017
Short name T1892
Test name
Test status
Simulation time 212061758 ps
CPU time 0.89 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:10:45 AM PDT 24
Peak memory 206128 kb
Host smart-1d7a4565-c087-4730-9b5b-adbc561b2a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36851
70017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3685170017
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.541545076
Short name T2014
Test name
Test status
Simulation time 4030243845 ps
CPU time 39.88 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206440 kb
Host smart-cfceead0-3721-4bdd-b5d8-40000290b31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54154
5076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.541545076
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.615199050
Short name T573
Test name
Test status
Simulation time 5396303719 ps
CPU time 152.01 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:13:16 AM PDT 24
Peak memory 206428 kb
Host smart-46f7e06b-fc85-4506-adf4-882e3fc99f18
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=615199050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.615199050
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1775299973
Short name T357
Test name
Test status
Simulation time 158514452 ps
CPU time 0.81 seconds
Started Jul 02 09:10:40 AM PDT 24
Finished Jul 02 09:10:43 AM PDT 24
Peak memory 206144 kb
Host smart-b793bb75-5fae-44bd-bcec-5bf4c9f3347e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1775299973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1775299973
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2456270442
Short name T589
Test name
Test status
Simulation time 156280870 ps
CPU time 0.85 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:10:45 AM PDT 24
Peak memory 206172 kb
Host smart-1c8ea4c9-8c46-40ff-8ac1-105d6f5e495d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562
70442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2456270442
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2347207165
Short name T2544
Test name
Test status
Simulation time 170581020 ps
CPU time 0.78 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:10:44 AM PDT 24
Peak memory 206204 kb
Host smart-6e58bf24-2ab2-472c-9306-f60fedcc4e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23472
07165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2347207165
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.658285167
Short name T2141
Test name
Test status
Simulation time 187674002 ps
CPU time 0.83 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:10:44 AM PDT 24
Peak memory 206168 kb
Host smart-812751da-947e-4438-8dbf-578375f0fab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65828
5167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.658285167
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2539162613
Short name T380
Test name
Test status
Simulation time 190051255 ps
CPU time 0.83 seconds
Started Jul 02 09:10:41 AM PDT 24
Finished Jul 02 09:10:43 AM PDT 24
Peak memory 206196 kb
Host smart-1f56debb-8822-4974-b465-276beb29cd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25391
62613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2539162613
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.305027624
Short name T1247
Test name
Test status
Simulation time 176425891 ps
CPU time 0.84 seconds
Started Jul 02 09:10:42 AM PDT 24
Finished Jul 02 09:10:44 AM PDT 24
Peak memory 206220 kb
Host smart-c84edcc6-06b5-4e9c-bf52-9205a887b94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30502
7624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.305027624
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3725897414
Short name T202
Test name
Test status
Simulation time 160052516 ps
CPU time 0.79 seconds
Started Jul 02 09:10:45 AM PDT 24
Finished Jul 02 09:10:46 AM PDT 24
Peak memory 206204 kb
Host smart-051dbacb-61ff-44b3-b3b8-c90fe6c240f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37258
97414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3725897414
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.1831764809
Short name T2304
Test name
Test status
Simulation time 212727593 ps
CPU time 0.86 seconds
Started Jul 02 09:10:49 AM PDT 24
Finished Jul 02 09:10:51 AM PDT 24
Peak memory 206148 kb
Host smart-e166a5c9-c549-454f-a29d-a7212edaa1de
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1831764809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.1831764809
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1146592152
Short name T2202
Test name
Test status
Simulation time 143248395 ps
CPU time 0.76 seconds
Started Jul 02 09:10:47 AM PDT 24
Finished Jul 02 09:10:48 AM PDT 24
Peak memory 206212 kb
Host smart-cbb2b8b1-f73d-4dd8-b3c3-c5a26edfc423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11465
92152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1146592152
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.803299482
Short name T2481
Test name
Test status
Simulation time 35524036 ps
CPU time 0.68 seconds
Started Jul 02 09:10:48 AM PDT 24
Finished Jul 02 09:10:49 AM PDT 24
Peak memory 206208 kb
Host smart-780bc6c3-e860-4026-8bd9-d246e99b5313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80329
9482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.803299482
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.363479886
Short name T1300
Test name
Test status
Simulation time 7339077554 ps
CPU time 16.64 seconds
Started Jul 02 09:10:45 AM PDT 24
Finished Jul 02 09:11:03 AM PDT 24
Peak memory 206552 kb
Host smart-8baa93be-f96a-4b76-91e8-a4d9a450f1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36347
9886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.363479886
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2722005759
Short name T1972
Test name
Test status
Simulation time 148064344 ps
CPU time 0.77 seconds
Started Jul 02 09:10:53 AM PDT 24
Finished Jul 02 09:10:56 AM PDT 24
Peak memory 206160 kb
Host smart-b4ceee04-a98b-40eb-b85e-b03b5b9da3d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27220
05759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2722005759
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.69656627
Short name T2159
Test name
Test status
Simulation time 227364727 ps
CPU time 0.86 seconds
Started Jul 02 09:10:45 AM PDT 24
Finished Jul 02 09:10:47 AM PDT 24
Peak memory 206184 kb
Host smart-e31cb8bc-57cd-48ab-b339-ae8d0c962f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69656
627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.69656627
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.152686713
Short name T372
Test name
Test status
Simulation time 226567475 ps
CPU time 0.94 seconds
Started Jul 02 09:10:47 AM PDT 24
Finished Jul 02 09:10:49 AM PDT 24
Peak memory 206204 kb
Host smart-8d42b8ff-895a-4a30-8754-55155fcd6e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15268
6713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.152686713
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.1967810248
Short name T1102
Test name
Test status
Simulation time 197552830 ps
CPU time 0.86 seconds
Started Jul 02 09:10:49 AM PDT 24
Finished Jul 02 09:10:51 AM PDT 24
Peak memory 206172 kb
Host smart-143d789e-dc8e-476e-9da9-2831814c0359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19678
10248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1967810248
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.987743291
Short name T2315
Test name
Test status
Simulation time 153548906 ps
CPU time 0.78 seconds
Started Jul 02 09:10:46 AM PDT 24
Finished Jul 02 09:10:47 AM PDT 24
Peak memory 206220 kb
Host smart-0380219b-61ce-42af-97af-d19418833733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98774
3291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.987743291
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2371585921
Short name T438
Test name
Test status
Simulation time 203734133 ps
CPU time 0.88 seconds
Started Jul 02 09:10:47 AM PDT 24
Finished Jul 02 09:10:49 AM PDT 24
Peak memory 206208 kb
Host smart-c6789b4d-ff86-4fa2-8567-b7bdd2044a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23715
85921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2371585921
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.350895051
Short name T2121
Test name
Test status
Simulation time 156188861 ps
CPU time 0.84 seconds
Started Jul 02 09:11:05 AM PDT 24
Finished Jul 02 09:11:07 AM PDT 24
Peak memory 206072 kb
Host smart-5425dbd4-b9eb-492c-ba34-016e02f6d100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35089
5051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.350895051
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1138944817
Short name T2332
Test name
Test status
Simulation time 219760172 ps
CPU time 0.92 seconds
Started Jul 02 09:10:47 AM PDT 24
Finished Jul 02 09:10:49 AM PDT 24
Peak memory 206212 kb
Host smart-3a5b1931-8f8a-47e7-b568-84dc7e86a53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11389
44817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1138944817
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1816613977
Short name T164
Test name
Test status
Simulation time 4922271063 ps
CPU time 45.12 seconds
Started Jul 02 09:10:48 AM PDT 24
Finished Jul 02 09:11:35 AM PDT 24
Peak memory 206456 kb
Host smart-813e5a5e-53a5-4dbb-9ae7-eed321a05bdd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1816613977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1816613977
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1128062712
Short name T1845
Test name
Test status
Simulation time 214142135 ps
CPU time 0.83 seconds
Started Jul 02 09:10:48 AM PDT 24
Finished Jul 02 09:10:49 AM PDT 24
Peak memory 206172 kb
Host smart-8cf95e41-8e73-4edb-8d9a-137949f07c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11280
62712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1128062712
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1125528252
Short name T366
Test name
Test status
Simulation time 159508734 ps
CPU time 0.79 seconds
Started Jul 02 09:10:47 AM PDT 24
Finished Jul 02 09:10:48 AM PDT 24
Peak memory 206176 kb
Host smart-2e0b0e10-3b88-4e57-ade5-7e3813a7ee32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11255
28252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1125528252
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.3870932198
Short name T1324
Test name
Test status
Simulation time 325656120 ps
CPU time 1.18 seconds
Started Jul 02 09:10:48 AM PDT 24
Finished Jul 02 09:10:50 AM PDT 24
Peak memory 206212 kb
Host smart-6401e5fb-78fe-4c96-a534-7ac2b4ef2088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
32198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.3870932198
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.873433094
Short name T2412
Test name
Test status
Simulation time 5186466712 ps
CPU time 149.29 seconds
Started Jul 02 09:10:49 AM PDT 24
Finished Jul 02 09:13:19 AM PDT 24
Peak memory 206520 kb
Host smart-7ed8aa0c-375c-4a00-acd6-6b32aee89a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87343
3094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.873433094
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.1719284171
Short name T675
Test name
Test status
Simulation time 68534823 ps
CPU time 0.68 seconds
Started Jul 02 09:10:54 AM PDT 24
Finished Jul 02 09:10:57 AM PDT 24
Peak memory 206228 kb
Host smart-50ca1c1b-6047-478f-867f-b3569efecc52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1719284171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.1719284171
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3100987170
Short name T2667
Test name
Test status
Simulation time 3576722227 ps
CPU time 4.49 seconds
Started Jul 02 09:10:48 AM PDT 24
Finished Jul 02 09:10:54 AM PDT 24
Peak memory 206112 kb
Host smart-8415f70a-8734-46f5-acd8-3b8000a98c18
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3100987170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.3100987170
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3036663789
Short name T2542
Test name
Test status
Simulation time 13385899707 ps
CPU time 12.53 seconds
Started Jul 02 09:10:44 AM PDT 24
Finished Jul 02 09:10:58 AM PDT 24
Peak memory 206392 kb
Host smart-95dc186f-d071-4c17-9c88-ca9e42b0dd57
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3036663789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3036663789
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3467207801
Short name T1293
Test name
Test status
Simulation time 23392738845 ps
CPU time 23.31 seconds
Started Jul 02 09:10:47 AM PDT 24
Finished Jul 02 09:11:11 AM PDT 24
Peak memory 206436 kb
Host smart-53833c22-fdcd-4984-9765-292d9399892f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3467207801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.3467207801
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2489555125
Short name T1121
Test name
Test status
Simulation time 156903419 ps
CPU time 0.81 seconds
Started Jul 02 09:10:47 AM PDT 24
Finished Jul 02 09:10:48 AM PDT 24
Peak memory 206200 kb
Host smart-0b2e677b-f574-409e-82f6-8cd1c37f2630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24895
55125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2489555125
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2058810115
Short name T2653
Test name
Test status
Simulation time 146615553 ps
CPU time 0.74 seconds
Started Jul 02 09:10:47 AM PDT 24
Finished Jul 02 09:10:49 AM PDT 24
Peak memory 206076 kb
Host smart-e3b98b7a-f096-4748-be5d-04da4e079e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20588
10115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2058810115
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_device_address.3307519606
Short name T795
Test name
Test status
Simulation time 21553089584 ps
CPU time 42.57 seconds
Started Jul 02 09:10:46 AM PDT 24
Finished Jul 02 09:11:30 AM PDT 24
Peak memory 206452 kb
Host smart-25a2a4c7-a08d-4d1c-8211-12133d331705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33075
19606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3307519606
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.411331922
Short name T539
Test name
Test status
Simulation time 400564073 ps
CPU time 1.29 seconds
Started Jul 02 09:10:55 AM PDT 24
Finished Jul 02 09:10:59 AM PDT 24
Peak memory 206220 kb
Host smart-1f5d80d5-f637-42f6-9f03-6f54b4696154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41133
1922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.411331922
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.2814758078
Short name T742
Test name
Test status
Simulation time 143723350 ps
CPU time 0.81 seconds
Started Jul 02 09:10:51 AM PDT 24
Finished Jul 02 09:10:53 AM PDT 24
Peak memory 206112 kb
Host smart-cd9e206b-0fee-4f1c-b81d-46aa78acb7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28147
58078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2814758078
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2486604526
Short name T577
Test name
Test status
Simulation time 85425494 ps
CPU time 0.74 seconds
Started Jul 02 09:10:50 AM PDT 24
Finished Jul 02 09:10:51 AM PDT 24
Peak memory 206192 kb
Host smart-f6b4e8e1-72e0-4e84-9b61-2df8bae6e897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24866
04526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2486604526
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1898613938
Short name T2671
Test name
Test status
Simulation time 928385872 ps
CPU time 2.13 seconds
Started Jul 02 09:11:06 AM PDT 24
Finished Jul 02 09:11:10 AM PDT 24
Peak memory 206412 kb
Host smart-5c14b725-505a-4a1d-81c6-d23462517482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18986
13938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1898613938
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1912932850
Short name T1220
Test name
Test status
Simulation time 227793026 ps
CPU time 1.32 seconds
Started Jul 02 09:10:54 AM PDT 24
Finished Jul 02 09:10:56 AM PDT 24
Peak memory 206404 kb
Host smart-d0d4313d-d871-46ab-88de-c6af9a9c70f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19129
32850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1912932850
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.574067504
Short name T1126
Test name
Test status
Simulation time 181732248 ps
CPU time 0.93 seconds
Started Jul 02 09:10:51 AM PDT 24
Finished Jul 02 09:10:53 AM PDT 24
Peak memory 206092 kb
Host smart-2b5acb91-4a47-42fa-92d1-f32da7e4af46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57406
7504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.574067504
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1581780232
Short name T1883
Test name
Test status
Simulation time 154456675 ps
CPU time 0.79 seconds
Started Jul 02 09:10:54 AM PDT 24
Finished Jul 02 09:10:56 AM PDT 24
Peak memory 206200 kb
Host smart-a8ad955d-6faa-4875-8221-d46388d444c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15817
80232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1581780232
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2838607083
Short name T997
Test name
Test status
Simulation time 227390367 ps
CPU time 0.9 seconds
Started Jul 02 09:10:55 AM PDT 24
Finished Jul 02 09:10:58 AM PDT 24
Peak memory 206160 kb
Host smart-b43b2aca-ae4d-44c6-8eb3-cf7a6b891480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28386
07083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2838607083
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.9384167
Short name T249
Test name
Test status
Simulation time 6872576073 ps
CPU time 48.7 seconds
Started Jul 02 09:10:53 AM PDT 24
Finished Jul 02 09:11:44 AM PDT 24
Peak memory 206440 kb
Host smart-1dd4d1be-fc44-4216-b0dd-46897426c1e4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=9384167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.9384167
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.3220086931
Short name T272
Test name
Test status
Simulation time 221039669 ps
CPU time 0.85 seconds
Started Jul 02 09:11:00 AM PDT 24
Finished Jul 02 09:11:02 AM PDT 24
Peak memory 206180 kb
Host smart-97646d42-e47e-4be6-be90-04fd2fce80d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32200
86931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.3220086931
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.1859411615
Short name T1420
Test name
Test status
Simulation time 23326760148 ps
CPU time 23.12 seconds
Started Jul 02 09:11:00 AM PDT 24
Finished Jul 02 09:11:24 AM PDT 24
Peak memory 206248 kb
Host smart-b6db8e46-8ca7-44d2-8018-afd8500c3354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18594
11615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.1859411615
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2272084688
Short name T1020
Test name
Test status
Simulation time 3378139443 ps
CPU time 4.1 seconds
Started Jul 02 09:11:11 AM PDT 24
Finished Jul 02 09:11:17 AM PDT 24
Peak memory 206244 kb
Host smart-962acb39-cb2e-4795-9cca-0d2acec93465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22720
84688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2272084688
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.726933243
Short name T2464
Test name
Test status
Simulation time 9112988383 ps
CPU time 83.22 seconds
Started Jul 02 09:11:01 AM PDT 24
Finished Jul 02 09:12:26 AM PDT 24
Peak memory 206504 kb
Host smart-d129d3da-15a9-47cc-a8e9-ff2618237aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72693
3243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.726933243
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3052383133
Short name T723
Test name
Test status
Simulation time 5983307522 ps
CPU time 59.23 seconds
Started Jul 02 09:10:54 AM PDT 24
Finished Jul 02 09:11:55 AM PDT 24
Peak memory 206460 kb
Host smart-12469c11-23fe-4903-a0cc-b6361ab6e7b9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3052383133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3052383133
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.111086831
Short name T1269
Test name
Test status
Simulation time 258558723 ps
CPU time 1 seconds
Started Jul 02 09:10:51 AM PDT 24
Finished Jul 02 09:10:53 AM PDT 24
Peak memory 206104 kb
Host smart-34e2a820-f289-4d29-b661-2eef7b764f03
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=111086831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.111086831
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2677832696
Short name T995
Test name
Test status
Simulation time 186511722 ps
CPU time 0.9 seconds
Started Jul 02 09:11:01 AM PDT 24
Finished Jul 02 09:11:03 AM PDT 24
Peak memory 206184 kb
Host smart-36f6686a-0ba5-4031-9341-858200c17cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26778
32696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2677832696
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.574146515
Short name T2292
Test name
Test status
Simulation time 5179182245 ps
CPU time 143.81 seconds
Started Jul 02 09:10:50 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206504 kb
Host smart-046533cb-82c1-4743-9ae0-a7d58d7e4a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57414
6515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.574146515
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3532973567
Short name T2517
Test name
Test status
Simulation time 6722421125 ps
CPU time 193.23 seconds
Started Jul 02 09:11:04 AM PDT 24
Finished Jul 02 09:14:18 AM PDT 24
Peak memory 206444 kb
Host smart-25822032-ec24-4dd9-b1af-4a73670a1243
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3532973567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3532973567
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3485285820
Short name T942
Test name
Test status
Simulation time 188037141 ps
CPU time 0.87 seconds
Started Jul 02 09:10:54 AM PDT 24
Finished Jul 02 09:10:57 AM PDT 24
Peak memory 206192 kb
Host smart-8c70d8c0-db92-42af-9278-5eb4b9962222
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3485285820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3485285820
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.817666487
Short name T239
Test name
Test status
Simulation time 199484760 ps
CPU time 0.9 seconds
Started Jul 02 09:11:01 AM PDT 24
Finished Jul 02 09:11:02 AM PDT 24
Peak memory 206184 kb
Host smart-a27551f5-d191-4d96-b8ac-74d0c6585519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81766
6487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.817666487
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1914631590
Short name T129
Test name
Test status
Simulation time 183377162 ps
CPU time 0.85 seconds
Started Jul 02 09:10:59 AM PDT 24
Finished Jul 02 09:11:01 AM PDT 24
Peak memory 206212 kb
Host smart-03ed5d71-8208-4cc6-a9c0-103ca1f4602b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19146
31590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1914631590
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3764865105
Short name T420
Test name
Test status
Simulation time 150840257 ps
CPU time 0.82 seconds
Started Jul 02 09:10:52 AM PDT 24
Finished Jul 02 09:10:54 AM PDT 24
Peak memory 206212 kb
Host smart-8b25d6da-18c9-467a-87d2-67ee9662b718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37648
65105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3764865105
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3016851013
Short name T2185
Test name
Test status
Simulation time 171588954 ps
CPU time 0.84 seconds
Started Jul 02 09:11:00 AM PDT 24
Finished Jul 02 09:11:02 AM PDT 24
Peak memory 206212 kb
Host smart-e1b68c3e-345a-4dd8-81b2-210293ead563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30168
51013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3016851013
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.4208347336
Short name T373
Test name
Test status
Simulation time 157344852 ps
CPU time 0.79 seconds
Started Jul 02 09:10:57 AM PDT 24
Finished Jul 02 09:10:59 AM PDT 24
Peak memory 206212 kb
Host smart-8213cb8a-82c6-4e9a-bb36-17980cbd2869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42083
47336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.4208347336
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2674305056
Short name T1931
Test name
Test status
Simulation time 146307730 ps
CPU time 0.74 seconds
Started Jul 02 09:11:06 AM PDT 24
Finished Jul 02 09:11:09 AM PDT 24
Peak memory 206184 kb
Host smart-2b7f61f4-2abe-4ddc-a90e-1a525c77ba4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26743
05056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2674305056
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.1120297570
Short name T1694
Test name
Test status
Simulation time 207090397 ps
CPU time 0.9 seconds
Started Jul 02 09:10:53 AM PDT 24
Finished Jul 02 09:10:55 AM PDT 24
Peak memory 206184 kb
Host smart-9d4da243-d226-4219-b58b-f4307dddfedb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1120297570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.1120297570
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2462945050
Short name T1181
Test name
Test status
Simulation time 168034780 ps
CPU time 0.81 seconds
Started Jul 02 09:11:05 AM PDT 24
Finished Jul 02 09:11:07 AM PDT 24
Peak memory 206168 kb
Host smart-3e872dfc-6125-408b-8ecc-b5ac08a8dabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24629
45050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2462945050
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3362448203
Short name T1712
Test name
Test status
Simulation time 43264120 ps
CPU time 0.68 seconds
Started Jul 02 09:10:54 AM PDT 24
Finished Jul 02 09:10:56 AM PDT 24
Peak memory 206196 kb
Host smart-7a0e5443-53cd-40bf-92b0-3582efba4dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33624
48203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3362448203
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1777385823
Short name T2405
Test name
Test status
Simulation time 11071245933 ps
CPU time 26.71 seconds
Started Jul 02 09:10:55 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206464 kb
Host smart-cb9179b2-80d2-49b3-80c8-4c000b73ad40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17773
85823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1777385823
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1553307859
Short name T784
Test name
Test status
Simulation time 155406530 ps
CPU time 0.89 seconds
Started Jul 02 09:11:02 AM PDT 24
Finished Jul 02 09:11:04 AM PDT 24
Peak memory 206336 kb
Host smart-e081c684-7a44-4fb5-84ba-47270142931f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15533
07859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1553307859
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3278198642
Short name T1745
Test name
Test status
Simulation time 252952861 ps
CPU time 1.02 seconds
Started Jul 02 09:11:03 AM PDT 24
Finished Jul 02 09:11:05 AM PDT 24
Peak memory 206224 kb
Host smart-89e1e30b-ae93-42a3-98e9-6e5011869995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32781
98642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3278198642
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3859298571
Short name T1411
Test name
Test status
Simulation time 226605723 ps
CPU time 0.92 seconds
Started Jul 02 09:10:57 AM PDT 24
Finished Jul 02 09:10:59 AM PDT 24
Peak memory 206168 kb
Host smart-e040bf6f-401b-4074-8089-b4a1be17c8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38592
98571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3859298571
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2214815675
Short name T1497
Test name
Test status
Simulation time 173562245 ps
CPU time 0.83 seconds
Started Jul 02 09:11:10 AM PDT 24
Finished Jul 02 09:11:12 AM PDT 24
Peak memory 206188 kb
Host smart-fd7769ee-7470-4ef8-8250-1451e268db08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22148
15675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2214815675
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3815459929
Short name T1367
Test name
Test status
Simulation time 160896514 ps
CPU time 0.79 seconds
Started Jul 02 09:10:56 AM PDT 24
Finished Jul 02 09:10:59 AM PDT 24
Peak memory 206120 kb
Host smart-ed00e838-2579-40cd-b340-a5100f999753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38154
59929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3815459929
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3427461303
Short name T1914
Test name
Test status
Simulation time 179944002 ps
CPU time 0.86 seconds
Started Jul 02 09:11:03 AM PDT 24
Finished Jul 02 09:11:05 AM PDT 24
Peak memory 206208 kb
Host smart-460223ab-4a96-4fdf-b289-17b372c17a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34274
61303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3427461303
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.624708569
Short name T1490
Test name
Test status
Simulation time 156221454 ps
CPU time 0.81 seconds
Started Jul 02 09:10:59 AM PDT 24
Finished Jul 02 09:11:01 AM PDT 24
Peak memory 206184 kb
Host smart-1c2fd920-99a7-49ae-b2a5-71a864d953ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62470
8569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.624708569
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1651021212
Short name T1132
Test name
Test status
Simulation time 245424796 ps
CPU time 0.96 seconds
Started Jul 02 09:10:56 AM PDT 24
Finished Jul 02 09:10:59 AM PDT 24
Peak memory 206120 kb
Host smart-07df2de8-df74-49a7-b2c8-70ae51e16a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16510
21212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1651021212
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3569301245
Short name T1609
Test name
Test status
Simulation time 5829570473 ps
CPU time 55.61 seconds
Started Jul 02 09:10:54 AM PDT 24
Finished Jul 02 09:11:52 AM PDT 24
Peak memory 206488 kb
Host smart-c51d350d-9700-411b-9f70-465cb8cea5f7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3569301245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3569301245
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3244271219
Short name T2298
Test name
Test status
Simulation time 165827414 ps
CPU time 0.8 seconds
Started Jul 02 09:11:03 AM PDT 24
Finished Jul 02 09:11:05 AM PDT 24
Peak memory 206180 kb
Host smart-9df45a62-bf41-4b08-9945-99cd037a2274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32442
71219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3244271219
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3797318629
Short name T1566
Test name
Test status
Simulation time 182908739 ps
CPU time 0.85 seconds
Started Jul 02 09:11:04 AM PDT 24
Finished Jul 02 09:11:05 AM PDT 24
Peak memory 206196 kb
Host smart-a4f4cce8-04c9-4e26-8ab5-2ca8e5534d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37973
18629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3797318629
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.2536570690
Short name T755
Test name
Test status
Simulation time 189259858 ps
CPU time 0.87 seconds
Started Jul 02 09:10:53 AM PDT 24
Finished Jul 02 09:10:55 AM PDT 24
Peak memory 206168 kb
Host smart-873eac9c-99d3-4436-be41-e5e62bbfeb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25365
70690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.2536570690
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.1840438651
Short name T1906
Test name
Test status
Simulation time 4314786378 ps
CPU time 39.98 seconds
Started Jul 02 09:10:53 AM PDT 24
Finished Jul 02 09:11:34 AM PDT 24
Peak memory 206384 kb
Host smart-7ad6e384-ee3d-4a73-8d25-01f44920fc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18404
38651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.1840438651
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.558931323
Short name T1398
Test name
Test status
Simulation time 50969873 ps
CPU time 0.69 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:28 AM PDT 24
Peak memory 206184 kb
Host smart-d2a7031f-a4ff-4c65-8472-7743ebfef1c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=558931323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.558931323
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1835059367
Short name T13
Test name
Test status
Simulation time 4395974164 ps
CPU time 5.89 seconds
Started Jul 02 09:10:56 AM PDT 24
Finished Jul 02 09:11:04 AM PDT 24
Peak memory 206420 kb
Host smart-c379e187-c01e-47df-b507-8509170acce9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1835059367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1835059367
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.2454609861
Short name T684
Test name
Test status
Simulation time 13418011617 ps
CPU time 12.4 seconds
Started Jul 02 09:11:02 AM PDT 24
Finished Jul 02 09:11:15 AM PDT 24
Peak memory 206248 kb
Host smart-f580c8b4-bef6-40f6-9dd1-cff4e81773ab
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2454609861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.2454609861
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2436781481
Short name T1864
Test name
Test status
Simulation time 23378670175 ps
CPU time 24.23 seconds
Started Jul 02 09:10:55 AM PDT 24
Finished Jul 02 09:11:22 AM PDT 24
Peak memory 206244 kb
Host smart-b5208e25-74e2-49d9-a937-18f212d3c8b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2436781481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.2436781481
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.627518730
Short name T2393
Test name
Test status
Simulation time 186029121 ps
CPU time 0.87 seconds
Started Jul 02 09:10:54 AM PDT 24
Finished Jul 02 09:10:57 AM PDT 24
Peak memory 206208 kb
Host smart-9ab618b1-168b-4f9d-90da-daf807d7a24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62751
8730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.627518730
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3720994841
Short name T1734
Test name
Test status
Simulation time 141936000 ps
CPU time 0.78 seconds
Started Jul 02 09:10:56 AM PDT 24
Finished Jul 02 09:10:59 AM PDT 24
Peak memory 206204 kb
Host smart-a4c6a467-c42e-4136-9ccd-d99f8a795723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37209
94841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3720994841
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.2373769473
Short name T2128
Test name
Test status
Simulation time 441568951 ps
CPU time 1.38 seconds
Started Jul 02 09:11:03 AM PDT 24
Finished Jul 02 09:11:06 AM PDT 24
Peak memory 206156 kb
Host smart-51f6ee78-e457-41d7-8bda-fa4990cf44b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23737
69473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.2373769473
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.923312296
Short name T901
Test name
Test status
Simulation time 561451140 ps
CPU time 1.38 seconds
Started Jul 02 09:10:53 AM PDT 24
Finished Jul 02 09:10:56 AM PDT 24
Peak memory 206188 kb
Host smart-5e7ece05-b867-4272-ad28-72039169d7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92331
2296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.923312296
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2412880069
Short name T662
Test name
Test status
Simulation time 11672398558 ps
CPU time 19.11 seconds
Started Jul 02 09:10:56 AM PDT 24
Finished Jul 02 09:11:17 AM PDT 24
Peak memory 206520 kb
Host smart-9551b2d5-e8a8-4333-b2bf-4faa9ee6d6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24128
80069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2412880069
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.1071074071
Short name T697
Test name
Test status
Simulation time 362525449 ps
CPU time 1.31 seconds
Started Jul 02 09:11:10 AM PDT 24
Finished Jul 02 09:11:13 AM PDT 24
Peak memory 206136 kb
Host smart-a9d3551d-907f-451b-a282-bb6baa77710a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10710
74071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.1071074071
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2791192432
Short name T1470
Test name
Test status
Simulation time 189604338 ps
CPU time 0.84 seconds
Started Jul 02 09:10:58 AM PDT 24
Finished Jul 02 09:11:00 AM PDT 24
Peak memory 206212 kb
Host smart-7e087b72-2fbf-4694-ade8-341dbdfed6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27911
92432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2791192432
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2426383899
Short name T1289
Test name
Test status
Simulation time 46232455 ps
CPU time 0.7 seconds
Started Jul 02 09:10:57 AM PDT 24
Finished Jul 02 09:10:59 AM PDT 24
Peak memory 206192 kb
Host smart-ba6afb6e-1b5a-4930-b476-6b8d5c71fcb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24263
83899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2426383899
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1772798312
Short name T956
Test name
Test status
Simulation time 901582946 ps
CPU time 2.02 seconds
Started Jul 02 09:11:07 AM PDT 24
Finished Jul 02 09:11:11 AM PDT 24
Peak memory 206440 kb
Host smart-1d028600-2fd3-457f-b25e-a6254b1f408f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17727
98312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1772798312
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.187442237
Short name T2668
Test name
Test status
Simulation time 378299786 ps
CPU time 2.37 seconds
Started Jul 02 09:11:07 AM PDT 24
Finished Jul 02 09:11:11 AM PDT 24
Peak memory 206384 kb
Host smart-df79a6a0-e9c7-4fd4-b74e-d85a9000cea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18744
2237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.187442237
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3112669368
Short name T2160
Test name
Test status
Simulation time 228198701 ps
CPU time 0.93 seconds
Started Jul 02 09:11:08 AM PDT 24
Finished Jul 02 09:11:11 AM PDT 24
Peak memory 206220 kb
Host smart-44b92c0b-1627-4437-bf45-7f5ef12db036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31126
69368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3112669368
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3783361229
Short name T1880
Test name
Test status
Simulation time 205032598 ps
CPU time 0.8 seconds
Started Jul 02 09:10:58 AM PDT 24
Finished Jul 02 09:11:00 AM PDT 24
Peak memory 206172 kb
Host smart-a0cec622-fa17-4b61-b5d2-ef39807c8356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37833
61229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3783361229
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1422966614
Short name T1118
Test name
Test status
Simulation time 200131876 ps
CPU time 0.89 seconds
Started Jul 02 09:10:58 AM PDT 24
Finished Jul 02 09:11:01 AM PDT 24
Peak memory 206388 kb
Host smart-5006e757-d4b6-4745-861b-e8449a0f0c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14229
66614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1422966614
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.2728491328
Short name T2662
Test name
Test status
Simulation time 6124059802 ps
CPU time 171.21 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:14:14 AM PDT 24
Peak memory 206532 kb
Host smart-5d5173e6-3e7b-404a-9df2-c3a47fb654ab
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2728491328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.2728491328
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2685223005
Short name T2526
Test name
Test status
Simulation time 289911859 ps
CPU time 1.02 seconds
Started Jul 02 09:11:07 AM PDT 24
Finished Jul 02 09:11:10 AM PDT 24
Peak memory 206140 kb
Host smart-fb423c36-7c8d-416d-9efc-b153b405779e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26852
23005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2685223005
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.542414224
Short name T674
Test name
Test status
Simulation time 23299839951 ps
CPU time 24.3 seconds
Started Jul 02 09:11:09 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206272 kb
Host smart-91edd8bd-22a3-43c9-8f26-d9f0cc29f0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54241
4224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.542414224
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1449871421
Short name T1101
Test name
Test status
Simulation time 3372909636 ps
CPU time 3.97 seconds
Started Jul 02 09:11:04 AM PDT 24
Finished Jul 02 09:11:09 AM PDT 24
Peak memory 206276 kb
Host smart-644e3f12-bad8-4072-ab64-8281ddf2442b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14498
71421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1449871421
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.3092161881
Short name T2571
Test name
Test status
Simulation time 6473988797 ps
CPU time 66.39 seconds
Started Jul 02 09:10:57 AM PDT 24
Finished Jul 02 09:12:05 AM PDT 24
Peak memory 206516 kb
Host smart-ceb3371d-6642-4eab-897a-0135cea85c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30921
61881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.3092161881
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.2653741239
Short name T1282
Test name
Test status
Simulation time 4654632707 ps
CPU time 136.21 seconds
Started Jul 02 09:11:02 AM PDT 24
Finished Jul 02 09:13:20 AM PDT 24
Peak memory 206408 kb
Host smart-60ebd34c-e0d3-4638-aa16-230ef56f2601
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2653741239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2653741239
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1444202151
Short name T398
Test name
Test status
Simulation time 234923144 ps
CPU time 0.91 seconds
Started Jul 02 09:10:58 AM PDT 24
Finished Jul 02 09:11:01 AM PDT 24
Peak memory 206172 kb
Host smart-64c5fed9-cc26-44b7-9623-2b84e5289a21
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1444202151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1444202151
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3174630324
Short name T1540
Test name
Test status
Simulation time 188391148 ps
CPU time 0.88 seconds
Started Jul 02 09:11:02 AM PDT 24
Finished Jul 02 09:11:04 AM PDT 24
Peak memory 206132 kb
Host smart-f7ceb70b-4d4c-41cf-bd2a-ab1616a6564c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31746
30324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3174630324
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.2657932161
Short name T2705
Test name
Test status
Simulation time 4119734273 ps
CPU time 29.54 seconds
Started Jul 02 09:11:06 AM PDT 24
Finished Jul 02 09:11:37 AM PDT 24
Peak memory 206432 kb
Host smart-0f2f5600-1bbf-4028-910d-8fe38f0f8c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26579
32161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.2657932161
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3570891429
Short name T1050
Test name
Test status
Simulation time 5002892626 ps
CPU time 133.85 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:13:32 AM PDT 24
Peak memory 206408 kb
Host smart-ec1807d6-4b9b-4197-9e82-42a9315f8526
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3570891429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3570891429
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3083900955
Short name T2403
Test name
Test status
Simulation time 152104136 ps
CPU time 0.77 seconds
Started Jul 02 09:11:03 AM PDT 24
Finished Jul 02 09:11:05 AM PDT 24
Peak memory 206100 kb
Host smart-3b09a9cd-f913-491e-a8f3-78e3c6735f99
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3083900955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3083900955
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.178637120
Short name T2073
Test name
Test status
Simulation time 162676427 ps
CPU time 0.8 seconds
Started Jul 02 09:11:01 AM PDT 24
Finished Jul 02 09:11:03 AM PDT 24
Peak memory 206216 kb
Host smart-cc4c05f1-1fff-4bc5-9b51-11e56c94e562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17863
7120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.178637120
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3127133188
Short name T145
Test name
Test status
Simulation time 174284891 ps
CPU time 0.82 seconds
Started Jul 02 09:11:08 AM PDT 24
Finished Jul 02 09:11:10 AM PDT 24
Peak memory 206180 kb
Host smart-3397659f-df21-4e5c-97fd-0483f2e24363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31271
33188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3127133188
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.1550787290
Short name T1406
Test name
Test status
Simulation time 169182621 ps
CPU time 0.81 seconds
Started Jul 02 09:11:06 AM PDT 24
Finished Jul 02 09:11:09 AM PDT 24
Peak memory 206224 kb
Host smart-a895aac0-4415-450a-86f4-6e3249fe9fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15507
87290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.1550787290
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3920823596
Short name T1081
Test name
Test status
Simulation time 187437680 ps
CPU time 0.88 seconds
Started Jul 02 09:11:02 AM PDT 24
Finished Jul 02 09:11:03 AM PDT 24
Peak memory 206180 kb
Host smart-ed6a7e47-66e1-47bc-911d-03ae8cebb8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39208
23596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3920823596
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2003718435
Short name T1202
Test name
Test status
Simulation time 194046307 ps
CPU time 0.82 seconds
Started Jul 02 09:11:09 AM PDT 24
Finished Jul 02 09:11:12 AM PDT 24
Peak memory 206140 kb
Host smart-1f71c64a-a1d9-453e-a948-992c613a1935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20037
18435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2003718435
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1895607567
Short name T1666
Test name
Test status
Simulation time 144412523 ps
CPU time 0.79 seconds
Started Jul 02 09:11:06 AM PDT 24
Finished Jul 02 09:11:09 AM PDT 24
Peak memory 206208 kb
Host smart-cd405683-81d0-4716-87ce-0bc2b02ecf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18956
07567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1895607567
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2813190933
Short name T1759
Test name
Test status
Simulation time 208809000 ps
CPU time 0.92 seconds
Started Jul 02 09:11:01 AM PDT 24
Finished Jul 02 09:11:03 AM PDT 24
Peak memory 206156 kb
Host smart-093092f8-59f3-427d-a068-af5b48f749f2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2813190933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2813190933
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2644247391
Short name T787
Test name
Test status
Simulation time 143965075 ps
CPU time 0.78 seconds
Started Jul 02 09:11:05 AM PDT 24
Finished Jul 02 09:11:07 AM PDT 24
Peak memory 206188 kb
Host smart-370ded17-6f0f-4846-ba3e-7f34283a4f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26442
47391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2644247391
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2475460333
Short name T1149
Test name
Test status
Simulation time 34216646 ps
CPU time 0.7 seconds
Started Jul 02 09:11:04 AM PDT 24
Finished Jul 02 09:11:05 AM PDT 24
Peak memory 206192 kb
Host smart-04670619-2029-4378-aa88-558cc7b55ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
60333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2475460333
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.4223826402
Short name T92
Test name
Test status
Simulation time 21224629395 ps
CPU time 47.97 seconds
Started Jul 02 09:11:10 AM PDT 24
Finished Jul 02 09:12:00 AM PDT 24
Peak memory 206484 kb
Host smart-a13b8b01-cd54-4b48-9043-159339c3f595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42238
26402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.4223826402
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3796825334
Short name T1465
Test name
Test status
Simulation time 182674413 ps
CPU time 0.88 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:17 AM PDT 24
Peak memory 206208 kb
Host smart-6c8d2e1a-abc0-44ca-bc8c-8d8f4ce4842d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37968
25334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3796825334
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3996237104
Short name T151
Test name
Test status
Simulation time 242133825 ps
CPU time 0.89 seconds
Started Jul 02 09:11:02 AM PDT 24
Finished Jul 02 09:11:04 AM PDT 24
Peak memory 206220 kb
Host smart-7df63fc2-30e8-495b-b1ee-27474725f7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39962
37104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3996237104
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.203350748
Short name T1594
Test name
Test status
Simulation time 213828639 ps
CPU time 0.88 seconds
Started Jul 02 09:11:04 AM PDT 24
Finished Jul 02 09:11:06 AM PDT 24
Peak memory 206156 kb
Host smart-a501195d-ebef-44cc-a9aa-ad901a0bf08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20335
0748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.203350748
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3909266056
Short name T2326
Test name
Test status
Simulation time 181703242 ps
CPU time 0.85 seconds
Started Jul 02 09:11:10 AM PDT 24
Finished Jul 02 09:11:12 AM PDT 24
Peak memory 206212 kb
Host smart-a82e9811-397b-42db-b2b5-bd3985d5b16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39092
66056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3909266056
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2079717132
Short name T1055
Test name
Test status
Simulation time 177879432 ps
CPU time 0.84 seconds
Started Jul 02 09:11:04 AM PDT 24
Finished Jul 02 09:11:06 AM PDT 24
Peak memory 206208 kb
Host smart-bf51cf2f-1344-45f7-ad94-abbba608582a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20797
17132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2079717132
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3012960662
Short name T1760
Test name
Test status
Simulation time 149338680 ps
CPU time 0.78 seconds
Started Jul 02 09:11:14 AM PDT 24
Finished Jul 02 09:11:15 AM PDT 24
Peak memory 206220 kb
Host smart-a206a3aa-feb4-432d-be76-c9cefaff13c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30129
60662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3012960662
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.4259320161
Short name T620
Test name
Test status
Simulation time 152198801 ps
CPU time 0.78 seconds
Started Jul 02 09:11:04 AM PDT 24
Finished Jul 02 09:11:06 AM PDT 24
Peak memory 206208 kb
Host smart-556a2c1b-bab1-4f1b-a5f0-ad19425337af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42593
20161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.4259320161
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2638244367
Short name T1448
Test name
Test status
Simulation time 233437980 ps
CPU time 1.01 seconds
Started Jul 02 09:11:02 AM PDT 24
Finished Jul 02 09:11:05 AM PDT 24
Peak memory 206176 kb
Host smart-97a16639-da4d-4a17-9fe3-5d92635b9946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26382
44367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2638244367
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2583611774
Short name T2572
Test name
Test status
Simulation time 167706401 ps
CPU time 0.83 seconds
Started Jul 02 09:11:05 AM PDT 24
Finished Jul 02 09:11:07 AM PDT 24
Peak memory 206212 kb
Host smart-789df3c4-be95-4f3b-ad39-6b816d8dd3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25836
11774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2583611774
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2980644858
Short name T400
Test name
Test status
Simulation time 165068367 ps
CPU time 0.78 seconds
Started Jul 02 09:11:09 AM PDT 24
Finished Jul 02 09:11:11 AM PDT 24
Peak memory 206180 kb
Host smart-e3cf5469-9f69-444d-a114-8a599f00d0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29806
44858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2980644858
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1545776129
Short name T2229
Test name
Test status
Simulation time 859452465 ps
CPU time 1.84 seconds
Started Jul 02 09:11:09 AM PDT 24
Finished Jul 02 09:11:13 AM PDT 24
Peak memory 206364 kb
Host smart-9bf4c737-483a-48dd-b6bc-ce9c08ba44a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15457
76129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1545776129
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1609349462
Short name T1555
Test name
Test status
Simulation time 8063990153 ps
CPU time 226.44 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:15:08 AM PDT 24
Peak memory 206492 kb
Host smart-2ead0a96-7385-4c1a-afdb-b441953a8616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16093
49462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1609349462
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.2460229418
Short name T1573
Test name
Test status
Simulation time 35733658 ps
CPU time 0.66 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:11:22 AM PDT 24
Peak memory 206216 kb
Host smart-7f4efae3-859f-40f6-bba4-af6ce5d1762c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2460229418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.2460229418
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1101885730
Short name T1793
Test name
Test status
Simulation time 3622670198 ps
CPU time 4.26 seconds
Started Jul 02 09:11:07 AM PDT 24
Finished Jul 02 09:11:13 AM PDT 24
Peak memory 206244 kb
Host smart-8263c213-004c-4c56-b931-8fdcf86cd3c9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1101885730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1101885730
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.2415293996
Short name T716
Test name
Test status
Simulation time 13384750513 ps
CPU time 11.73 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:27 AM PDT 24
Peak memory 206436 kb
Host smart-226814b1-3e8d-42ea-93b5-230a3b73a589
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2415293996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.2415293996
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1290317216
Short name T2443
Test name
Test status
Simulation time 23385734391 ps
CPU time 23.79 seconds
Started Jul 02 09:11:10 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206220 kb
Host smart-94118c4f-b9dc-4aa3-9d0f-f4d5c069685e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1290317216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.1290317216
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2321401493
Short name T458
Test name
Test status
Simulation time 174555394 ps
CPU time 0.85 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:11:20 AM PDT 24
Peak memory 206208 kb
Host smart-92d2d957-4858-4ee4-8cd6-0e79fe4fbdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23214
01493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2321401493
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1666232221
Short name T2324
Test name
Test status
Simulation time 156519425 ps
CPU time 0.78 seconds
Started Jul 02 09:11:09 AM PDT 24
Finished Jul 02 09:11:11 AM PDT 24
Peak memory 206216 kb
Host smart-57eaf917-0272-47d0-b89c-9ba55d674f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16662
32221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1666232221
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2829282045
Short name T1110
Test name
Test status
Simulation time 137507578 ps
CPU time 0.8 seconds
Started Jul 02 09:11:11 AM PDT 24
Finished Jul 02 09:11:14 AM PDT 24
Peak memory 206200 kb
Host smart-bfd5352f-7c02-45e5-8705-aa5e85d0bc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28292
82045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2829282045
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2829820055
Short name T2188
Test name
Test status
Simulation time 1290466784 ps
CPU time 2.94 seconds
Started Jul 02 09:11:07 AM PDT 24
Finished Jul 02 09:11:11 AM PDT 24
Peak memory 206460 kb
Host smart-ce24d7c2-6bbf-4a7c-8c5b-52eb936c75a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28298
20055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2829820055
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2219118276
Short name T2431
Test name
Test status
Simulation time 10251971473 ps
CPU time 20.52 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:43 AM PDT 24
Peak memory 206488 kb
Host smart-212a8259-175d-4be0-81a9-20a745bdbad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22191
18276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2219118276
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.19758215
Short name T2621
Test name
Test status
Simulation time 472052606 ps
CPU time 1.46 seconds
Started Jul 02 09:11:05 AM PDT 24
Finished Jul 02 09:11:08 AM PDT 24
Peak memory 206216 kb
Host smart-4f594f5c-7207-4664-b05b-d23b8db7f330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19758
215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.19758215
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1247656567
Short name T780
Test name
Test status
Simulation time 159225888 ps
CPU time 0.78 seconds
Started Jul 02 09:11:07 AM PDT 24
Finished Jul 02 09:11:09 AM PDT 24
Peak memory 206208 kb
Host smart-2f25a99f-457e-400b-ab61-f81c49f96f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12476
56567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1247656567
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3965070947
Short name T2520
Test name
Test status
Simulation time 47014905 ps
CPU time 0.67 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:29 AM PDT 24
Peak memory 206200 kb
Host smart-9b6822bf-8412-45f9-8dea-e1b202c73888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39650
70947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3965070947
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2937284822
Short name T1841
Test name
Test status
Simulation time 798270651 ps
CPU time 1.8 seconds
Started Jul 02 09:11:22 AM PDT 24
Finished Jul 02 09:11:29 AM PDT 24
Peak memory 206380 kb
Host smart-463911e3-a31e-4c4d-99f0-cf4873a7df65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29372
84822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2937284822
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2272516228
Short name T86
Test name
Test status
Simulation time 172526965 ps
CPU time 1.61 seconds
Started Jul 02 09:11:16 AM PDT 24
Finished Jul 02 09:11:19 AM PDT 24
Peak memory 206396 kb
Host smart-e380be93-1f2d-44b3-a628-12ec549bd06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22725
16228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2272516228
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2305478091
Short name T2616
Test name
Test status
Simulation time 203427637 ps
CPU time 0.9 seconds
Started Jul 02 09:11:11 AM PDT 24
Finished Jul 02 09:11:14 AM PDT 24
Peak memory 206188 kb
Host smart-7e121a22-f767-4767-8d77-1ebdb7faaccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23054
78091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2305478091
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2244867050
Short name T1466
Test name
Test status
Simulation time 157322555 ps
CPU time 0.76 seconds
Started Jul 02 09:11:05 AM PDT 24
Finished Jul 02 09:11:07 AM PDT 24
Peak memory 206192 kb
Host smart-c4414729-7bea-4b49-b1d4-12bc2ed33d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22448
67050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2244867050
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1833248679
Short name T1936
Test name
Test status
Simulation time 246515712 ps
CPU time 0.92 seconds
Started Jul 02 09:11:11 AM PDT 24
Finished Jul 02 09:11:14 AM PDT 24
Peak memory 206208 kb
Host smart-da75abb6-10ba-4c2c-9508-8de5974455dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18332
48679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1833248679
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.3332687143
Short name T2549
Test name
Test status
Simulation time 6094277858 ps
CPU time 167.59 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:14:09 AM PDT 24
Peak memory 206452 kb
Host smart-fbfbd8be-e22b-4d40-a6e3-76aa6cfa0972
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3332687143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3332687143
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2241320550
Short name T368
Test name
Test status
Simulation time 155381407 ps
CPU time 0.87 seconds
Started Jul 02 09:11:06 AM PDT 24
Finished Jul 02 09:11:09 AM PDT 24
Peak memory 206160 kb
Host smart-193f8651-9570-43e3-b80d-c014627cca97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22413
20550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2241320550
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.2978898957
Short name T938
Test name
Test status
Simulation time 23351922822 ps
CPU time 23.19 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:46 AM PDT 24
Peak memory 206284 kb
Host smart-c7a5fd94-192a-4bd1-a5ca-1d1d1eb3cebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29788
98957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.2978898957
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3824667192
Short name T150
Test name
Test status
Simulation time 3315906408 ps
CPU time 3.77 seconds
Started Jul 02 09:11:07 AM PDT 24
Finished Jul 02 09:11:12 AM PDT 24
Peak memory 206240 kb
Host smart-a0e5b3a0-8c4b-489f-a43f-90066af76346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38246
67192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3824667192
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.1649400002
Short name T1157
Test name
Test status
Simulation time 5870000623 ps
CPU time 156.7 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:14:06 AM PDT 24
Peak memory 206404 kb
Host smart-eedf82fd-0eb1-4e0c-a2a2-51ee5c1677dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16494
00002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.1649400002
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.174416208
Short name T1947
Test name
Test status
Simulation time 4566173849 ps
CPU time 121.08 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:13:29 AM PDT 24
Peak memory 206484 kb
Host smart-90798c9e-5c5a-4457-840f-3002cda3f913
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=174416208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.174416208
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.3962512632
Short name T698
Test name
Test status
Simulation time 274296657 ps
CPU time 0.94 seconds
Started Jul 02 09:11:16 AM PDT 24
Finished Jul 02 09:11:19 AM PDT 24
Peak memory 206176 kb
Host smart-f016dcaf-43d1-45b0-a123-cb7c4047cbe1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3962512632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.3962512632
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1174601884
Short name T2232
Test name
Test status
Simulation time 226901206 ps
CPU time 0.92 seconds
Started Jul 02 09:11:09 AM PDT 24
Finished Jul 02 09:11:12 AM PDT 24
Peak memory 206224 kb
Host smart-6882ed82-5871-4570-96eb-a61f4f33191f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11746
01884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1174601884
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1055707897
Short name T1227
Test name
Test status
Simulation time 5929704904 ps
CPU time 55.18 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206464 kb
Host smart-36245425-fd83-4a61-b44b-d3d2602783c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10557
07897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1055707897
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.376162591
Short name T2419
Test name
Test status
Simulation time 3289159624 ps
CPU time 31.74 seconds
Started Jul 02 09:11:06 AM PDT 24
Finished Jul 02 09:11:40 AM PDT 24
Peak memory 206468 kb
Host smart-aea7d7fd-c0dd-45ed-9ec1-df4c94118df5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=376162591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.376162591
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.295579752
Short name T1036
Test name
Test status
Simulation time 153873907 ps
CPU time 0.77 seconds
Started Jul 02 09:11:08 AM PDT 24
Finished Jul 02 09:11:10 AM PDT 24
Peak memory 206160 kb
Host smart-b2612d07-9490-49c0-96fb-a7370f5a80c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=295579752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.295579752
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2785775236
Short name T2327
Test name
Test status
Simulation time 166478749 ps
CPU time 0.8 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:11:31 AM PDT 24
Peak memory 206144 kb
Host smart-fd6980c9-9d2e-4cb9-8fa0-d7f465a70e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27857
75236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2785775236
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1030115907
Short name T125
Test name
Test status
Simulation time 203468125 ps
CPU time 0.9 seconds
Started Jul 02 09:11:21 AM PDT 24
Finished Jul 02 09:11:26 AM PDT 24
Peak memory 206196 kb
Host smart-0646e324-b440-4907-8785-685e2c7212bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10301
15907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1030115907
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.89580445
Short name T954
Test name
Test status
Simulation time 195495642 ps
CPU time 0.86 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:11:21 AM PDT 24
Peak memory 206144 kb
Host smart-5faaf2ca-67b5-4277-8bfd-0c83d0377966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89580
445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.89580445
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1520908351
Short name T1204
Test name
Test status
Simulation time 157706817 ps
CPU time 0.8 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:11:24 AM PDT 24
Peak memory 206224 kb
Host smart-60ca0164-97c8-446f-909d-94bcf669057b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15209
08351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1520908351
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.4102035433
Short name T510
Test name
Test status
Simulation time 178810060 ps
CPU time 0.84 seconds
Started Jul 02 09:11:06 AM PDT 24
Finished Jul 02 09:11:08 AM PDT 24
Peak memory 206180 kb
Host smart-e499abce-381e-4b57-b357-8077d843b458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41020
35433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.4102035433
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3113135347
Short name T2655
Test name
Test status
Simulation time 186581136 ps
CPU time 0.81 seconds
Started Jul 02 09:11:06 AM PDT 24
Finished Jul 02 09:11:08 AM PDT 24
Peak memory 206124 kb
Host smart-20d5869e-7228-4609-b193-851b013c0ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31131
35347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3113135347
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.3229422746
Short name T403
Test name
Test status
Simulation time 241426253 ps
CPU time 0.96 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:11:25 AM PDT 24
Peak memory 206184 kb
Host smart-f3981fc1-245e-4684-bbfe-3f8dc1938f67
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3229422746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.3229422746
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.245701624
Short name T42
Test name
Test status
Simulation time 148330306 ps
CPU time 0.74 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:11:35 AM PDT 24
Peak memory 206200 kb
Host smart-f7bdb826-3d27-4449-9740-addbff5e1b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24570
1624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.245701624
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2794012758
Short name T2436
Test name
Test status
Simulation time 29888011 ps
CPU time 0.67 seconds
Started Jul 02 09:11:16 AM PDT 24
Finished Jul 02 09:11:19 AM PDT 24
Peak memory 206140 kb
Host smart-7d058bfd-bb74-47af-9bd6-68e7b21d6271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27940
12758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2794012758
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1471142969
Short name T1075
Test name
Test status
Simulation time 10300130808 ps
CPU time 22.75 seconds
Started Jul 02 09:11:14 AM PDT 24
Finished Jul 02 09:11:37 AM PDT 24
Peak memory 214688 kb
Host smart-a73c38ad-890c-40bc-b159-5c535e11bb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14711
42969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1471142969
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1611289401
Short name T1774
Test name
Test status
Simulation time 199207267 ps
CPU time 0.89 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:11:22 AM PDT 24
Peak memory 206140 kb
Host smart-86c19c92-4e63-49c0-a8bb-7486ac2f34b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16112
89401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1611289401
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.4127871747
Short name T866
Test name
Test status
Simulation time 170790834 ps
CPU time 0.82 seconds
Started Jul 02 09:11:05 AM PDT 24
Finished Jul 02 09:11:07 AM PDT 24
Peak memory 206196 kb
Host smart-c9a367d2-5423-4a87-b839-b457678bd7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41278
71747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.4127871747
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3695875478
Short name T2116
Test name
Test status
Simulation time 242291401 ps
CPU time 0.88 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:29 AM PDT 24
Peak memory 206144 kb
Host smart-7a0164e2-14ca-4cd3-9d08-6a3ecb259c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36958
75478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3695875478
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2959818199
Short name T1962
Test name
Test status
Simulation time 191743056 ps
CPU time 0.88 seconds
Started Jul 02 09:11:10 AM PDT 24
Finished Jul 02 09:11:13 AM PDT 24
Peak memory 206172 kb
Host smart-a90560af-7069-4a82-884a-e6f9df43d817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29598
18199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2959818199
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1815704836
Short name T1652
Test name
Test status
Simulation time 160135561 ps
CPU time 0.79 seconds
Started Jul 02 09:11:16 AM PDT 24
Finished Jul 02 09:11:19 AM PDT 24
Peak memory 206204 kb
Host smart-ff6a13fd-caac-49fc-ba2c-4740590e82c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18157
04836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1815704836
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.6544204
Short name T840
Test name
Test status
Simulation time 151047448 ps
CPU time 0.76 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:18 AM PDT 24
Peak memory 206208 kb
Host smart-db62d386-f23d-4d57-a00b-16ef2906833a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65442
04 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.6544204
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1474686910
Short name T520
Test name
Test status
Simulation time 146882115 ps
CPU time 0.75 seconds
Started Jul 02 09:11:10 AM PDT 24
Finished Jul 02 09:11:13 AM PDT 24
Peak memory 206132 kb
Host smart-b4159962-e8b4-4b89-97ff-65ddd1e352aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14746
86910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1474686910
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1531768971
Short name T1052
Test name
Test status
Simulation time 219933073 ps
CPU time 0.95 seconds
Started Jul 02 09:11:24 AM PDT 24
Finished Jul 02 09:11:29 AM PDT 24
Peak memory 206200 kb
Host smart-5d298b52-b2e7-4ce9-b39d-e6dd8b740801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15317
68971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1531768971
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1287359346
Short name T1092
Test name
Test status
Simulation time 3408302769 ps
CPU time 23.81 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:11:48 AM PDT 24
Peak memory 206456 kb
Host smart-335622ba-ec5b-4124-9a0d-d549ac13cf6e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1287359346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1287359346
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2784642967
Short name T902
Test name
Test status
Simulation time 187786296 ps
CPU time 0.82 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:11:21 AM PDT 24
Peak memory 206172 kb
Host smart-447e15f4-d929-47b0-91fd-69875f41faf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27846
42967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2784642967
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1780578784
Short name T603
Test name
Test status
Simulation time 171103461 ps
CPU time 0.8 seconds
Started Jul 02 09:11:12 AM PDT 24
Finished Jul 02 09:11:14 AM PDT 24
Peak memory 206208 kb
Host smart-f884faab-2d1e-4a60-a744-f118e5ca68ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17805
78784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1780578784
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.2589746180
Short name T1647
Test name
Test status
Simulation time 758129787 ps
CPU time 1.9 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:11:31 AM PDT 24
Peak memory 206448 kb
Host smart-a5913d3d-bf36-4ec1-94f6-1b3426bad9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
46180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.2589746180
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.761174721
Short name T2696
Test name
Test status
Simulation time 6230302514 ps
CPU time 176.78 seconds
Started Jul 02 09:11:10 AM PDT 24
Finished Jul 02 09:14:09 AM PDT 24
Peak memory 206524 kb
Host smart-12df17ff-e75f-4c0f-aea5-9c93aa68e961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76117
4721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.761174721
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2366899921
Short name T205
Test name
Test status
Simulation time 98936832 ps
CPU time 0.71 seconds
Started Jul 02 09:11:16 AM PDT 24
Finished Jul 02 09:11:19 AM PDT 24
Peak memory 206204 kb
Host smart-0eea7902-bcbc-4fd9-89e6-04f4ba630fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2366899921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2366899921
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1930602382
Short name T862
Test name
Test status
Simulation time 4216336857 ps
CPU time 5.51 seconds
Started Jul 02 09:11:12 AM PDT 24
Finished Jul 02 09:11:19 AM PDT 24
Peak memory 206480 kb
Host smart-d4b9666f-27c3-4119-8c6d-3b9aea4a43a1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1930602382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.1930602382
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2492143513
Short name T1887
Test name
Test status
Simulation time 13384788607 ps
CPU time 13.04 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206540 kb
Host smart-4b1b113f-2f31-4b11-a63a-4d938766f822
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2492143513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2492143513
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3579073277
Short name T1165
Test name
Test status
Simulation time 23412362669 ps
CPU time 28.9 seconds
Started Jul 02 09:11:21 AM PDT 24
Finished Jul 02 09:11:54 AM PDT 24
Peak memory 206248 kb
Host smart-2506e46a-060d-4738-a540-a1d0202cad8f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3579073277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.3579073277
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1414789232
Short name T1287
Test name
Test status
Simulation time 170294351 ps
CPU time 0.81 seconds
Started Jul 02 09:11:10 AM PDT 24
Finished Jul 02 09:11:13 AM PDT 24
Peak memory 206124 kb
Host smart-267d0c84-23a8-4038-8587-b30be330ea5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14147
89232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1414789232
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2106031782
Short name T1713
Test name
Test status
Simulation time 168634676 ps
CPU time 0.8 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:11:20 AM PDT 24
Peak memory 206212 kb
Host smart-e3b964fd-4bb0-40d4-8608-27685821483e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21060
31782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2106031782
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.544644989
Short name T2507
Test name
Test status
Simulation time 303430747 ps
CPU time 1.19 seconds
Started Jul 02 09:11:21 AM PDT 24
Finished Jul 02 09:11:26 AM PDT 24
Peak memory 206220 kb
Host smart-18745d34-8c40-4eeb-8923-5e968e2cf0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54464
4989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.544644989
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.602915065
Short name T512
Test name
Test status
Simulation time 353496746 ps
CPU time 1.04 seconds
Started Jul 02 09:11:10 AM PDT 24
Finished Jul 02 09:11:13 AM PDT 24
Peak memory 206208 kb
Host smart-f9e9612b-918e-429f-8ff7-c8b6e83a57d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60291
5065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.602915065
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.2435945150
Short name T1257
Test name
Test status
Simulation time 17713503750 ps
CPU time 33.18 seconds
Started Jul 02 09:11:11 AM PDT 24
Finished Jul 02 09:11:46 AM PDT 24
Peak memory 206384 kb
Host smart-7a8fa542-68cc-4f2a-a011-b55f20be306d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24359
45150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.2435945150
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1177673542
Short name T2132
Test name
Test status
Simulation time 371266942 ps
CPU time 1.21 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:11:20 AM PDT 24
Peak memory 206204 kb
Host smart-703888b8-2700-425b-b199-7764acfb3ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11776
73542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1177673542
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1521674564
Short name T979
Test name
Test status
Simulation time 171465917 ps
CPU time 0.82 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206340 kb
Host smart-7917553f-f7c4-426c-b992-b16fa0d78c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15216
74564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1521674564
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1982222685
Short name T1684
Test name
Test status
Simulation time 59740637 ps
CPU time 0.72 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:17 AM PDT 24
Peak memory 206384 kb
Host smart-6fc7ec73-2cdf-4a69-8d2c-0831d4e25a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
22685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1982222685
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2111944462
Short name T444
Test name
Test status
Simulation time 787865496 ps
CPU time 1.99 seconds
Started Jul 02 09:11:16 AM PDT 24
Finished Jul 02 09:11:20 AM PDT 24
Peak memory 206384 kb
Host smart-ca0a4199-2277-41d1-aaf4-dd06d38c03f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21119
44462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2111944462
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2033735356
Short name T1315
Test name
Test status
Simulation time 394883681 ps
CPU time 2.53 seconds
Started Jul 02 09:11:21 AM PDT 24
Finished Jul 02 09:11:28 AM PDT 24
Peak memory 206416 kb
Host smart-4725eb03-d09b-49e1-9171-5b382ad5aba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20337
35356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2033735356
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.317748662
Short name T2040
Test name
Test status
Simulation time 205529279 ps
CPU time 0.86 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:18 AM PDT 24
Peak memory 206216 kb
Host smart-0efc916a-393b-44d5-bda8-fb969f4d297d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31774
8662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.317748662
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1863593978
Short name T1999
Test name
Test status
Simulation time 140022575 ps
CPU time 0.81 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:11:20 AM PDT 24
Peak memory 206072 kb
Host smart-efdce2cc-fa11-4983-b6be-353fa3034a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18635
93978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1863593978
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.63972279
Short name T1836
Test name
Test status
Simulation time 195664264 ps
CPU time 0.85 seconds
Started Jul 02 09:11:14 AM PDT 24
Finished Jul 02 09:11:15 AM PDT 24
Peak memory 206212 kb
Host smart-78463e09-0228-449a-b6cf-b58e3ad99a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63972
279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.63972279
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.3184387426
Short name T1556
Test name
Test status
Simulation time 7022473237 ps
CPU time 49.23 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:12:11 AM PDT 24
Peak memory 206520 kb
Host smart-274b2d4e-9a69-485d-aa97-8a4175d0abe9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3184387426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3184387426
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.695138574
Short name T958
Test name
Test status
Simulation time 246995849 ps
CPU time 0.94 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:18 AM PDT 24
Peak memory 206388 kb
Host smart-8ba53af8-65d6-4ed0-ae36-ab50c7155def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69513
8574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.695138574
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1573492410
Short name T1981
Test name
Test status
Simulation time 23313225916 ps
CPU time 23.37 seconds
Started Jul 02 09:11:13 AM PDT 24
Finished Jul 02 09:11:37 AM PDT 24
Peak memory 206248 kb
Host smart-3b51a8e2-0aeb-4599-9d9d-aa1aa739e591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15734
92410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1573492410
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.225270962
Short name T508
Test name
Test status
Simulation time 3323192693 ps
CPU time 3.54 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:11:22 AM PDT 24
Peak memory 206276 kb
Host smart-98e3eb59-effa-41f3-9c4f-9e868e260056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
0962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.225270962
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.717901120
Short name T1746
Test name
Test status
Simulation time 8152461161 ps
CPU time 64.63 seconds
Started Jul 02 09:11:22 AM PDT 24
Finished Jul 02 09:12:32 AM PDT 24
Peak memory 206500 kb
Host smart-893af170-e564-439c-b60e-d793ef95dc41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71790
1120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.717901120
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2220411416
Short name T1536
Test name
Test status
Simulation time 7189319282 ps
CPU time 199.38 seconds
Started Jul 02 09:11:24 AM PDT 24
Finished Jul 02 09:14:49 AM PDT 24
Peak memory 206360 kb
Host smart-3072b038-c32b-4f1c-8ee4-2cfe39cbe286
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2220411416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2220411416
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1374442656
Short name T907
Test name
Test status
Simulation time 232972554 ps
CPU time 0.93 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:17 AM PDT 24
Peak memory 206364 kb
Host smart-3c7cd82d-4da6-48e1-81cd-76ff0f3a6be9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1374442656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1374442656
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3429180418
Short name T394
Test name
Test status
Simulation time 204031895 ps
CPU time 0.91 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:24 AM PDT 24
Peak memory 206228 kb
Host smart-295bd3a5-1cc0-43b2-9c11-af24381636ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34291
80418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3429180418
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.3966285264
Short name T1482
Test name
Test status
Simulation time 5165247713 ps
CPU time 37.39 seconds
Started Jul 02 09:11:21 AM PDT 24
Finished Jul 02 09:12:03 AM PDT 24
Peak memory 206440 kb
Host smart-1f46a3df-2d8d-41db-b95c-d74627f12cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39662
85264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.3966285264
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2928573752
Short name T1532
Test name
Test status
Simulation time 4983686471 ps
CPU time 47.12 seconds
Started Jul 02 09:11:22 AM PDT 24
Finished Jul 02 09:12:14 AM PDT 24
Peak memory 206512 kb
Host smart-2f023c89-1756-4903-9ab1-a66427ff5e73
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2928573752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2928573752
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.1332863858
Short name T1302
Test name
Test status
Simulation time 173632251 ps
CPU time 0.84 seconds
Started Jul 02 09:11:22 AM PDT 24
Finished Jul 02 09:11:27 AM PDT 24
Peak memory 206200 kb
Host smart-a89c2962-1d90-4442-9b90-99cee33a9a63
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1332863858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.1332863858
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2225664180
Short name T939
Test name
Test status
Simulation time 145013835 ps
CPU time 0.83 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206176 kb
Host smart-0f2d9e3b-3c23-4255-aaae-b340c6e65a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22256
64180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2225664180
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3796796489
Short name T2401
Test name
Test status
Simulation time 232675450 ps
CPU time 0.84 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:28 AM PDT 24
Peak memory 206212 kb
Host smart-131387e5-c619-4910-80d8-d8a4c38de8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37967
96489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3796796489
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1750621594
Short name T769
Test name
Test status
Simulation time 160793123 ps
CPU time 0.78 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:11:20 AM PDT 24
Peak memory 206184 kb
Host smart-32c3672d-978a-4dbe-8d2a-ebc2ba2aa6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17506
21594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1750621594
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3248717768
Short name T1467
Test name
Test status
Simulation time 149644102 ps
CPU time 0.76 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:11:24 AM PDT 24
Peak memory 206200 kb
Host smart-1866fae4-d844-44bc-a9ae-b146aef554a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32487
17768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3248717768
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3949604790
Short name T2536
Test name
Test status
Simulation time 183401387 ps
CPU time 0.82 seconds
Started Jul 02 09:11:16 AM PDT 24
Finished Jul 02 09:11:18 AM PDT 24
Peak memory 206392 kb
Host smart-ec5b9c26-75e1-4e59-9cf8-5219de585b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39496
04790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3949604790
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1765612814
Short name T184
Test name
Test status
Simulation time 194507165 ps
CPU time 0.77 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:18 AM PDT 24
Peak memory 206132 kb
Host smart-56c6fa6b-bde1-4a65-a6f9-f24ab96628c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17656
12814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1765612814
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.4121499795
Short name T81
Test name
Test status
Simulation time 218952059 ps
CPU time 0.94 seconds
Started Jul 02 09:11:16 AM PDT 24
Finished Jul 02 09:11:19 AM PDT 24
Peak memory 206172 kb
Host smart-3ab7ba83-478b-406e-9cfe-27e6c34e7eef
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4121499795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.4121499795
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3763144484
Short name T209
Test name
Test status
Simulation time 143862225 ps
CPU time 0.82 seconds
Started Jul 02 09:11:21 AM PDT 24
Finished Jul 02 09:11:27 AM PDT 24
Peak memory 206196 kb
Host smart-ad442f26-4747-41e7-8462-8ca0d61eda50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37631
44484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3763144484
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2753318817
Short name T2277
Test name
Test status
Simulation time 59495090 ps
CPU time 0.66 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:28 AM PDT 24
Peak memory 205980 kb
Host smart-a5a7d709-7c01-4583-95ae-b1e7fe2ad466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27533
18817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2753318817
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.848092151
Short name T1783
Test name
Test status
Simulation time 9720306062 ps
CPU time 21.57 seconds
Started Jul 02 09:11:24 AM PDT 24
Finished Jul 02 09:11:51 AM PDT 24
Peak memory 206548 kb
Host smart-36160103-3fb5-48d5-9a64-4f504fa29d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84809
2151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.848092151
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1060048685
Short name T374
Test name
Test status
Simulation time 198150959 ps
CPU time 0.79 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206140 kb
Host smart-ec06a68e-07e5-4d04-a466-5bb4e22eae4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10600
48685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1060048685
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2595414678
Short name T2244
Test name
Test status
Simulation time 173457081 ps
CPU time 0.81 seconds
Started Jul 02 09:11:14 AM PDT 24
Finished Jul 02 09:11:16 AM PDT 24
Peak memory 206172 kb
Host smart-e6909376-09f9-4799-ab72-89613a5b81c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25954
14678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2595414678
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2320507541
Short name T899
Test name
Test status
Simulation time 188230261 ps
CPU time 0.83 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206220 kb
Host smart-c719c8a2-5f87-4550-bbac-f505ab3f06a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23205
07541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2320507541
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.1909554142
Short name T2251
Test name
Test status
Simulation time 180797481 ps
CPU time 0.82 seconds
Started Jul 02 09:11:21 AM PDT 24
Finished Jul 02 09:11:26 AM PDT 24
Peak memory 206184 kb
Host smart-078d09f3-560a-4c1b-b6aa-5b87ff6a5490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19095
54142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.1909554142
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2850556844
Short name T836
Test name
Test status
Simulation time 147081400 ps
CPU time 0.78 seconds
Started Jul 02 09:11:24 AM PDT 24
Finished Jul 02 09:11:30 AM PDT 24
Peak memory 206208 kb
Host smart-32019468-66ba-493c-b471-3561337a2445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28505
56844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2850556844
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2957460136
Short name T1383
Test name
Test status
Simulation time 164341897 ps
CPU time 0.78 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206172 kb
Host smart-3c6d7553-9613-47dc-b195-7aa9cde36be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29574
60136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2957460136
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.734439118
Short name T745
Test name
Test status
Simulation time 152986273 ps
CPU time 0.81 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:16 AM PDT 24
Peak memory 206200 kb
Host smart-065f3bc6-992e-4bdb-8c5a-da38aed721d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73443
9118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.734439118
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2825170611
Short name T2239
Test name
Test status
Simulation time 196782178 ps
CPU time 0.88 seconds
Started Jul 02 09:11:22 AM PDT 24
Finished Jul 02 09:11:28 AM PDT 24
Peak memory 206200 kb
Host smart-06b03aeb-a5b2-4591-8c9b-6cef481b00eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28251
70611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2825170611
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.3698355249
Short name T1809
Test name
Test status
Simulation time 5407614696 ps
CPU time 47.69 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:12:10 AM PDT 24
Peak memory 206520 kb
Host smart-0b826194-9454-4cb2-9771-6d03dc947c16
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3698355249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3698355249
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3899152171
Short name T2155
Test name
Test status
Simulation time 177447525 ps
CPU time 0.91 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:11:24 AM PDT 24
Peak memory 206212 kb
Host smart-d403d981-39fd-4c43-b3ae-2b404e2bd472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38991
52171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3899152171
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.196464828
Short name T1685
Test name
Test status
Simulation time 208966592 ps
CPU time 0.86 seconds
Started Jul 02 09:11:22 AM PDT 24
Finished Jul 02 09:11:27 AM PDT 24
Peak memory 206076 kb
Host smart-a6b84ec5-44a4-43c2-bbab-749cc41fe066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19646
4828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.196464828
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.4221864242
Short name T409
Test name
Test status
Simulation time 670363072 ps
CPU time 1.58 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206404 kb
Host smart-59c58d5e-4f24-4ee0-956c-8da28211dbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42218
64242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.4221864242
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2856937768
Short name T2191
Test name
Test status
Simulation time 2938193356 ps
CPU time 21.04 seconds
Started Jul 02 09:11:16 AM PDT 24
Finished Jul 02 09:11:39 AM PDT 24
Peak memory 206512 kb
Host smart-383828f5-43a1-4422-9718-728a50909f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28569
37768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2856937768
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.365023093
Short name T693
Test name
Test status
Simulation time 42533072 ps
CPU time 0.7 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:11:31 AM PDT 24
Peak memory 206252 kb
Host smart-412c55c4-59c8-4baf-8e8c-6dddd2d1598a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=365023093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.365023093
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3341732830
Short name T1330
Test name
Test status
Simulation time 13511149539 ps
CPU time 12.92 seconds
Started Jul 02 09:11:24 AM PDT 24
Finished Jul 02 09:11:41 AM PDT 24
Peak memory 206444 kb
Host smart-88f8aa1f-d959-4eed-8da6-c21609938f17
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3341732830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3341732830
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.4065620606
Short name T9
Test name
Test status
Simulation time 23410027966 ps
CPU time 21.57 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:11:43 AM PDT 24
Peak memory 206396 kb
Host smart-ea8bd14f-5bdb-4eda-951a-8f99a1779d2a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4065620606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.4065620606
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.607431098
Short name T1457
Test name
Test status
Simulation time 184086071 ps
CPU time 0.84 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206172 kb
Host smart-63a622ff-78b4-4140-a0ea-5f6877c850e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60743
1098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.607431098
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.2590215481
Short name T390
Test name
Test status
Simulation time 146079502 ps
CPU time 0.77 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:16 AM PDT 24
Peak memory 206204 kb
Host smart-b6f124a4-e3db-4bc8-88c6-29a76819cc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25902
15481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.2590215481
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3862065132
Short name T110
Test name
Test status
Simulation time 227326405 ps
CPU time 0.94 seconds
Started Jul 02 09:11:28 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206156 kb
Host smart-beefaead-908a-4e8f-a4b6-3eb2bdede89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38620
65132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3862065132
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2929827845
Short name T195
Test name
Test status
Simulation time 1232221929 ps
CPU time 2.59 seconds
Started Jul 02 09:11:15 AM PDT 24
Finished Jul 02 09:11:18 AM PDT 24
Peak memory 206428 kb
Host smart-bfd02f52-aa8d-44d7-9e38-620ec903effd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29298
27845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2929827845
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2264192097
Short name T1019
Test name
Test status
Simulation time 20861709886 ps
CPU time 41.28 seconds
Started Jul 02 09:11:24 AM PDT 24
Finished Jul 02 09:12:11 AM PDT 24
Peak memory 206476 kb
Host smart-fc38b68c-4182-4a75-8d63-24e33c0c098a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22641
92097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2264192097
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.892950750
Short name T2168
Test name
Test status
Simulation time 349149429 ps
CPU time 1.23 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:11:20 AM PDT 24
Peak memory 206216 kb
Host smart-c784c0ee-cfd3-43de-83d2-3ed92a16d3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89295
0750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.892950750
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.4110722497
Short name T43
Test name
Test status
Simulation time 162873748 ps
CPU time 0.87 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206216 kb
Host smart-3515815b-f870-471b-9cd3-2d20d38f7fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41107
22497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.4110722497
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.4169429591
Short name T1670
Test name
Test status
Simulation time 38929654 ps
CPU time 0.64 seconds
Started Jul 02 09:11:28 AM PDT 24
Finished Jul 02 09:11:32 AM PDT 24
Peak memory 206200 kb
Host smart-36f2d260-2adc-4834-a518-6b4f18d525ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41694
29591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.4169429591
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3125977740
Short name T1151
Test name
Test status
Simulation time 259164730 ps
CPU time 1.59 seconds
Started Jul 02 09:11:21 AM PDT 24
Finished Jul 02 09:11:26 AM PDT 24
Peak memory 206604 kb
Host smart-82c379ee-b998-46c1-86d1-ed65014ea32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31259
77740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3125977740
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1283947268
Short name T1349
Test name
Test status
Simulation time 156659128 ps
CPU time 0.88 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:11:25 AM PDT 24
Peak memory 206156 kb
Host smart-6d60adf2-db93-499a-9ad3-2c1557c5fe96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12839
47268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1283947268
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.818539943
Short name T1277
Test name
Test status
Simulation time 139074066 ps
CPU time 0.79 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206148 kb
Host smart-444f80b2-2314-4f9d-918c-3f9ad9b45463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81853
9943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.818539943
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3244531547
Short name T2358
Test name
Test status
Simulation time 159655391 ps
CPU time 0.8 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206180 kb
Host smart-754bad1d-a4fa-4ee6-9e4b-74566a0ebb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32445
31547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3244531547
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.4177532848
Short name T1239
Test name
Test status
Simulation time 6581328416 ps
CPU time 59.87 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:12:23 AM PDT 24
Peak memory 206472 kb
Host smart-c05608fd-c8ea-4062-92d1-94d45323e7b1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4177532848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.4177532848
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2286252005
Short name T415
Test name
Test status
Simulation time 204456371 ps
CPU time 0.84 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:11:22 AM PDT 24
Peak memory 206224 kb
Host smart-85267a51-f6a9-4581-b8c9-4891611e19aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
52005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2286252005
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1177910944
Short name T1105
Test name
Test status
Simulation time 23278472081 ps
CPU time 22.75 seconds
Started Jul 02 09:11:17 AM PDT 24
Finished Jul 02 09:11:42 AM PDT 24
Peak memory 206192 kb
Host smart-74694ebb-dcc1-4399-883f-48a6e9f3e267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11779
10944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1177910944
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2048174607
Short name T378
Test name
Test status
Simulation time 3270530205 ps
CPU time 3.92 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:32 AM PDT 24
Peak memory 206276 kb
Host smart-d567bbd2-7142-462c-bff4-b5eb85899961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20481
74607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2048174607
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.1502206605
Short name T1802
Test name
Test status
Simulation time 9082816841 ps
CPU time 91.04 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:12:54 AM PDT 24
Peak memory 206484 kb
Host smart-bfd148ed-bd75-4617-a4a0-53bd9a3773ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15022
06605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.1502206605
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1258513220
Short name T2316
Test name
Test status
Simulation time 4007277463 ps
CPU time 106.06 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206488 kb
Host smart-c4994fcc-0c2e-4b86-aa16-234a152988f6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1258513220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1258513220
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.19009276
Short name T1514
Test name
Test status
Simulation time 245464798 ps
CPU time 0.94 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206192 kb
Host smart-f2af7c7d-33a0-4ca1-a02c-04a7ce3a5a0a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=19009276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.19009276
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.591642257
Short name T793
Test name
Test status
Simulation time 208774106 ps
CPU time 0.88 seconds
Started Jul 02 09:11:18 AM PDT 24
Finished Jul 02 09:11:22 AM PDT 24
Peak memory 206128 kb
Host smart-ba6cc749-b9ae-477a-a0c3-75a40a69ee17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59164
2257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.591642257
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1519683229
Short name T2361
Test name
Test status
Simulation time 5822909129 ps
CPU time 41.72 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:12:14 AM PDT 24
Peak memory 206432 kb
Host smart-79719a22-66b4-4aff-bc20-4bbd2ecb0c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15196
83229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1519683229
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.2109438730
Short name T2240
Test name
Test status
Simulation time 4728040802 ps
CPU time 47.52 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:12:17 AM PDT 24
Peak memory 206436 kb
Host smart-74d43b11-8e8f-4844-9b66-2a759d76f7c6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2109438730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.2109438730
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1739936745
Short name T1087
Test name
Test status
Simulation time 210910787 ps
CPU time 0.86 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:11:24 AM PDT 24
Peak memory 206144 kb
Host smart-a531134a-c5df-42f6-b532-8c5b6fd46c46
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1739936745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1739936745
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3373197433
Short name T23
Test name
Test status
Simulation time 145365099 ps
CPU time 0.8 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:11:31 AM PDT 24
Peak memory 206176 kb
Host smart-fc029310-625b-41c0-9061-50928e65e170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33731
97433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3373197433
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1868860471
Short name T143
Test name
Test status
Simulation time 231120238 ps
CPU time 0.92 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:23 AM PDT 24
Peak memory 206196 kb
Host smart-b6752997-a8e9-4ace-8b4e-10306f184282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18688
60471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1868860471
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1362901690
Short name T1334
Test name
Test status
Simulation time 156670844 ps
CPU time 0.77 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:11:30 AM PDT 24
Peak memory 206200 kb
Host smart-fc03cb74-c0a0-4135-9878-59ccd82b2965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13629
01690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1362901690
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.311958923
Short name T2666
Test name
Test status
Simulation time 151606245 ps
CPU time 0.73 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:11:24 AM PDT 24
Peak memory 206200 kb
Host smart-9f49f896-e6a0-4e1f-9e88-1f640c513bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31195
8923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.311958923
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2505656898
Short name T1812
Test name
Test status
Simulation time 194635505 ps
CPU time 0.78 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:11:31 AM PDT 24
Peak memory 206196 kb
Host smart-9ad86d7b-cd34-4c87-a30a-1cf5d55db52e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25056
56898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2505656898
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1167486351
Short name T517
Test name
Test status
Simulation time 187809295 ps
CPU time 0.8 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:11:31 AM PDT 24
Peak memory 206196 kb
Host smart-7625db61-76b2-46a0-aa1f-fc5d63c02408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11674
86351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1167486351
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1949352463
Short name T546
Test name
Test status
Simulation time 210811774 ps
CPU time 0.99 seconds
Started Jul 02 09:11:26 AM PDT 24
Finished Jul 02 09:11:31 AM PDT 24
Peak memory 206192 kb
Host smart-2a70f4d5-d190-47ae-a86b-5e29e88b1090
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1949352463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1949352463
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2622095365
Short name T353
Test name
Test status
Simulation time 141928764 ps
CPU time 0.78 seconds
Started Jul 02 09:11:19 AM PDT 24
Finished Jul 02 09:11:24 AM PDT 24
Peak memory 206160 kb
Host smart-5297c68d-59d3-432d-8c02-a0611fcb4c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26220
95365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2622095365
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1544277792
Short name T756
Test name
Test status
Simulation time 32234015 ps
CPU time 0.64 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:11:24 AM PDT 24
Peak memory 206204 kb
Host smart-7160140b-3cda-4151-b70f-0ac1559415bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15442
77792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1544277792
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3525216970
Short name T1069
Test name
Test status
Simulation time 12774879944 ps
CPU time 27.92 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:56 AM PDT 24
Peak memory 214756 kb
Host smart-fcfb194c-589e-458c-a7ec-b6cc74a5e43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35252
16970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3525216970
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3111005863
Short name T900
Test name
Test status
Simulation time 173092529 ps
CPU time 0.85 seconds
Started Jul 02 09:11:21 AM PDT 24
Finished Jul 02 09:11:27 AM PDT 24
Peak memory 206168 kb
Host smart-41263986-a8c5-4208-82d7-37aab9e7817c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31110
05863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3111005863
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.983601795
Short name T1496
Test name
Test status
Simulation time 211669567 ps
CPU time 0.87 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:29 AM PDT 24
Peak memory 205948 kb
Host smart-a2f970ea-0790-488b-86f3-ef4ccadfa543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98360
1795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.983601795
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.2000574782
Short name T1648
Test name
Test status
Simulation time 167832646 ps
CPU time 0.83 seconds
Started Jul 02 09:11:20 AM PDT 24
Finished Jul 02 09:11:24 AM PDT 24
Peak memory 206168 kb
Host smart-dc8b004c-5fd9-40ba-a768-11b610cfe6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20005
74782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2000574782
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.1477125328
Short name T1308
Test name
Test status
Simulation time 154131675 ps
CPU time 0.81 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206176 kb
Host smart-6dbc58cb-1f55-4e69-9b94-ced2d1c5efa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14771
25328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.1477125328
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.4054634691
Short name T497
Test name
Test status
Simulation time 196781631 ps
CPU time 0.81 seconds
Started Jul 02 09:11:24 AM PDT 24
Finished Jul 02 09:11:30 AM PDT 24
Peak memory 206192 kb
Host smart-71b00bba-06f2-4b7f-9300-87f9a78f5605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40546
34691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.4054634691
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1775393388
Short name T804
Test name
Test status
Simulation time 221364577 ps
CPU time 0.85 seconds
Started Jul 02 09:11:31 AM PDT 24
Finished Jul 02 09:11:34 AM PDT 24
Peak memory 206216 kb
Host smart-bd0996f7-247f-4dc6-92a3-b5b84eaeb055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17753
93388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1775393388
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3769042268
Short name T753
Test name
Test status
Simulation time 145780467 ps
CPU time 0.74 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:11:30 AM PDT 24
Peak memory 206216 kb
Host smart-8d653c6d-0fed-440a-b20d-e1ca8398cc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37690
42268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3769042268
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1734682259
Short name T929
Test name
Test status
Simulation time 199490972 ps
CPU time 0.88 seconds
Started Jul 02 09:11:26 AM PDT 24
Finished Jul 02 09:11:32 AM PDT 24
Peak memory 206196 kb
Host smart-2fc8c4f5-9d4a-43e0-95ed-ef4b3a88e9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17346
82259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1734682259
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2812269498
Short name T2594
Test name
Test status
Simulation time 3121297534 ps
CPU time 28.63 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:56 AM PDT 24
Peak memory 206508 kb
Host smart-60dbb6c8-ca62-40f3-a6a9-5206f98e1958
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2812269498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2812269498
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2380646249
Short name T2226
Test name
Test status
Simulation time 182596346 ps
CPU time 0.83 seconds
Started Jul 02 09:11:22 AM PDT 24
Finished Jul 02 09:11:28 AM PDT 24
Peak memory 206208 kb
Host smart-0cd18578-a708-4f84-8951-d89a405e036f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23806
46249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2380646249
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3620368317
Short name T2460
Test name
Test status
Simulation time 176038404 ps
CPU time 0.9 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:29 AM PDT 24
Peak memory 206168 kb
Host smart-bf13c42e-25e6-424e-9560-363d8e5ed729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36203
68317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3620368317
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.291463476
Short name T1535
Test name
Test status
Simulation time 337383801 ps
CPU time 1.12 seconds
Started Jul 02 09:11:22 AM PDT 24
Finished Jul 02 09:11:28 AM PDT 24
Peak memory 206344 kb
Host smart-c1a5b432-e699-4c9f-aee0-047995721ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29146
3476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.291463476
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.344305808
Short name T2348
Test name
Test status
Simulation time 7115897898 ps
CPU time 55.36 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206524 kb
Host smart-50ab9223-3ccb-452a-bd31-66175086d185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34430
5808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.344305808
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.1245703686
Short name T1003
Test name
Test status
Simulation time 49051564 ps
CPU time 0.68 seconds
Started Jul 02 09:11:34 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206160 kb
Host smart-4ed392b9-2719-4d89-a64a-29e7eb2ac172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1245703686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.1245703686
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.73300413
Short name T2166
Test name
Test status
Simulation time 4374242207 ps
CPU time 5.17 seconds
Started Jul 02 09:11:26 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206256 kb
Host smart-b5776ac9-bf62-4752-8d25-77619f5ea0ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=73300413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.73300413
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1466941250
Short name T2262
Test name
Test status
Simulation time 13449681761 ps
CPU time 12.63 seconds
Started Jul 02 09:11:23 AM PDT 24
Finished Jul 02 09:11:40 AM PDT 24
Peak memory 206456 kb
Host smart-0cacad28-0eee-4acb-8c1d-8a4bf6e21ddd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1466941250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1466941250
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2942722857
Short name T2190
Test name
Test status
Simulation time 23383907312 ps
CPU time 29.74 seconds
Started Jul 02 09:11:24 AM PDT 24
Finished Jul 02 09:11:59 AM PDT 24
Peak memory 206252 kb
Host smart-d3a02cb5-46cc-496e-affd-908b8ab4c10b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2942722857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.2942722857
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.651723874
Short name T1273
Test name
Test status
Simulation time 200480819 ps
CPU time 0.85 seconds
Started Jul 02 09:11:25 AM PDT 24
Finished Jul 02 09:11:30 AM PDT 24
Peak memory 206196 kb
Host smart-a37adda4-f677-4528-92e6-a19daed3f50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65172
3874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.651723874
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3392239426
Short name T1414
Test name
Test status
Simulation time 181175042 ps
CPU time 0.86 seconds
Started Jul 02 09:11:28 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206204 kb
Host smart-debf432e-6b26-424b-9555-26405d072776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33922
39426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3392239426
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2262002066
Short name T1750
Test name
Test status
Simulation time 336735735 ps
CPU time 1.15 seconds
Started Jul 02 09:11:26 AM PDT 24
Finished Jul 02 09:11:32 AM PDT 24
Peak memory 206216 kb
Host smart-3b90b793-00b2-44b6-9863-9954c7892e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620
02066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2262002066
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.750415111
Short name T1787
Test name
Test status
Simulation time 628604862 ps
CPU time 1.52 seconds
Started Jul 02 09:11:26 AM PDT 24
Finished Jul 02 09:11:32 AM PDT 24
Peak memory 206164 kb
Host smart-10aea03c-830e-448f-ad1a-7c0d794ea28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75041
5111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.750415111
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1023886295
Short name T2432
Test name
Test status
Simulation time 8066179063 ps
CPU time 16.34 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:11:49 AM PDT 24
Peak memory 206484 kb
Host smart-e3845f5e-aea3-4efb-91bf-3148b8dc2a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10238
86295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1023886295
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.532768770
Short name T1775
Test name
Test status
Simulation time 350247841 ps
CPU time 1.16 seconds
Started Jul 02 09:11:27 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206188 kb
Host smart-76d8b2b3-50f6-4002-89f2-102f4ff6bf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53276
8770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.532768770
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1201610784
Short name T1109
Test name
Test status
Simulation time 168233453 ps
CPU time 0.88 seconds
Started Jul 02 09:11:28 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206184 kb
Host smart-1259594d-0e93-40f4-85cb-234d3b1d09db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12016
10784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1201610784
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2467877878
Short name T1108
Test name
Test status
Simulation time 36331896 ps
CPU time 0.7 seconds
Started Jul 02 09:11:27 AM PDT 24
Finished Jul 02 09:11:32 AM PDT 24
Peak memory 206184 kb
Host smart-221d8711-e368-4706-8feb-1da986ff2e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24678
77878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2467877878
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3036301887
Short name T842
Test name
Test status
Simulation time 897058328 ps
CPU time 2.04 seconds
Started Jul 02 09:11:34 AM PDT 24
Finished Jul 02 09:11:38 AM PDT 24
Peak memory 206468 kb
Host smart-25bf43c6-c1dc-48e0-993a-c16ae5c8b9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30363
01887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3036301887
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2719631012
Short name T1421
Test name
Test status
Simulation time 290028817 ps
CPU time 1.96 seconds
Started Jul 02 09:11:28 AM PDT 24
Finished Jul 02 09:11:34 AM PDT 24
Peak memory 206416 kb
Host smart-a2e891c1-cb5a-449a-902c-703054142344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27196
31012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2719631012
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2367705101
Short name T955
Test name
Test status
Simulation time 206917560 ps
CPU time 0.88 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206172 kb
Host smart-9546705c-9036-47fc-9f32-4d7113e5b755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23677
05101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2367705101
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3026544113
Short name T2561
Test name
Test status
Simulation time 173767012 ps
CPU time 0.82 seconds
Started Jul 02 09:11:31 AM PDT 24
Finished Jul 02 09:11:35 AM PDT 24
Peak memory 206072 kb
Host smart-92636007-f63f-4164-890e-86f94150b860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30265
44113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3026544113
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3696181082
Short name T637
Test name
Test status
Simulation time 246533631 ps
CPU time 0.92 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206212 kb
Host smart-7c26e118-585c-48a4-b8ca-d92451113861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36961
81082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3696181082
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.65478213
Short name T243
Test name
Test status
Simulation time 6595369101 ps
CPU time 62.47 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:12:35 AM PDT 24
Peak memory 206412 kb
Host smart-83242fdf-1a97-4b38-b8f2-70abd9d0e3f9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=65478213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.65478213
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1248067172
Short name T541
Test name
Test status
Simulation time 190784657 ps
CPU time 0.89 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:11:38 AM PDT 24
Peak memory 206208 kb
Host smart-167c4ff5-d4f0-47ea-95e6-96609295b466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12480
67172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1248067172
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1053928585
Short name T1663
Test name
Test status
Simulation time 23358642162 ps
CPU time 28.79 seconds
Started Jul 02 09:11:34 AM PDT 24
Finished Jul 02 09:12:04 AM PDT 24
Peak memory 206272 kb
Host smart-97bf7d0d-7f18-4601-9bc3-27d5c06de147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10539
28585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1053928585
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.441627494
Short name T1031
Test name
Test status
Simulation time 3346963220 ps
CPU time 4.06 seconds
Started Jul 02 09:11:28 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206276 kb
Host smart-068e4606-51f1-4029-99ce-5405f6b12760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44162
7494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.441627494
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.3164518895
Short name T1701
Test name
Test status
Simulation time 10520358243 ps
CPU time 303.29 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:16:38 AM PDT 24
Peak memory 206496 kb
Host smart-1aecc8c2-c470-46e5-9896-a0ba72626be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645
18895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.3164518895
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.4142347943
Short name T2233
Test name
Test status
Simulation time 5225609296 ps
CPU time 38.91 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:12:14 AM PDT 24
Peak memory 206464 kb
Host smart-5ab45674-943c-4713-a8d2-09f791bcd1be
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4142347943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.4142347943
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.3355851007
Short name T485
Test name
Test status
Simulation time 286550377 ps
CPU time 0.91 seconds
Started Jul 02 09:11:26 AM PDT 24
Finished Jul 02 09:11:32 AM PDT 24
Peak memory 206156 kb
Host smart-aec08cc6-8ac3-4cb5-8452-1a68ec76f165
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3355851007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.3355851007
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.953382179
Short name T767
Test name
Test status
Simulation time 195297696 ps
CPU time 0.88 seconds
Started Jul 02 09:11:29 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206200 kb
Host smart-b50ab981-8515-442c-93de-6a6a5be677e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95338
2179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.953382179
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.4212587430
Short name T1708
Test name
Test status
Simulation time 4887859283 ps
CPU time 45.09 seconds
Started Jul 02 09:11:30 AM PDT 24
Finished Jul 02 09:12:18 AM PDT 24
Peak memory 206468 kb
Host smart-a6304f23-ae05-4434-8f08-2acc6975444e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42125
87430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.4212587430
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1509675367
Short name T1067
Test name
Test status
Simulation time 6097903819 ps
CPU time 57.6 seconds
Started Jul 02 09:11:28 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206452 kb
Host smart-438cf7d4-29dc-42e7-81a9-0bca363bd5ea
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1509675367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1509675367
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3781909230
Short name T972
Test name
Test status
Simulation time 155877475 ps
CPU time 0.78 seconds
Started Jul 02 09:11:28 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 206136 kb
Host smart-cde6168c-f95a-4e36-aaa9-a9a7e937b2e1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3781909230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3781909230
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1321466834
Short name T518
Test name
Test status
Simulation time 152751912 ps
CPU time 0.8 seconds
Started Jul 02 09:11:27 AM PDT 24
Finished Jul 02 09:11:32 AM PDT 24
Peak memory 206224 kb
Host smart-60900de3-8e5d-4c68-9fbf-87fe43ca86d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13214
66834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1321466834
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.4172679338
Short name T1795
Test name
Test status
Simulation time 213929001 ps
CPU time 0.84 seconds
Started Jul 02 09:11:27 AM PDT 24
Finished Jul 02 09:11:32 AM PDT 24
Peak memory 206212 kb
Host smart-0d772ca1-cf07-4709-97a6-e9ddcc0fe28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41726
79338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.4172679338
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.946176380
Short name T826
Test name
Test status
Simulation time 190056929 ps
CPU time 0.86 seconds
Started Jul 02 09:11:33 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206220 kb
Host smart-04f7f9d3-36d9-4e09-9fd9-6c7955bdbd29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94617
6380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.946176380
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.804364537
Short name T21
Test name
Test status
Simulation time 169474758 ps
CPU time 0.79 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:11:35 AM PDT 24
Peak memory 206192 kb
Host smart-325fb29f-68c0-47f1-89cd-469c9721018e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80436
4537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.804364537
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2973645809
Short name T1473
Test name
Test status
Simulation time 200438970 ps
CPU time 0.83 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:11:35 AM PDT 24
Peak memory 206196 kb
Host smart-256dfbe1-a3cb-48fa-8f52-a9d2b79a521e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29736
45809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2973645809
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2266318775
Short name T760
Test name
Test status
Simulation time 151339181 ps
CPU time 0.76 seconds
Started Jul 02 09:11:31 AM PDT 24
Finished Jul 02 09:11:35 AM PDT 24
Peak memory 206212 kb
Host smart-ffda2afc-4caa-429e-a8a2-70814095f698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22663
18775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2266318775
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.3733923232
Short name T2031
Test name
Test status
Simulation time 225969377 ps
CPU time 0.95 seconds
Started Jul 02 09:11:38 AM PDT 24
Finished Jul 02 09:11:40 AM PDT 24
Peak memory 206196 kb
Host smart-a3642c1c-5dbb-4279-929f-fb54291ac99c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3733923232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.3733923232
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2523696755
Short name T2556
Test name
Test status
Simulation time 149345577 ps
CPU time 0.78 seconds
Started Jul 02 09:11:31 AM PDT 24
Finished Jul 02 09:11:35 AM PDT 24
Peak memory 206216 kb
Host smart-50552eff-6c8e-490e-a134-d5e73ccd2823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25236
96755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2523696755
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3625479295
Short name T2087
Test name
Test status
Simulation time 69758438 ps
CPU time 0.66 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206160 kb
Host smart-54f18f37-8f3c-4915-8f5d-728ec9d85e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36254
79295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3625479295
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2558276605
Short name T298
Test name
Test status
Simulation time 10343587998 ps
CPU time 23.22 seconds
Started Jul 02 09:11:31 AM PDT 24
Finished Jul 02 09:11:57 AM PDT 24
Peak memory 206452 kb
Host smart-1eb247aa-dca9-4939-bcde-b8dab0302e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25582
76605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2558276605
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.82816813
Short name T696
Test name
Test status
Simulation time 193944236 ps
CPU time 0.87 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206196 kb
Host smart-9ec25476-5f9d-4c9c-9ad6-f14ced4aa5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82816
813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.82816813
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3461660637
Short name T2482
Test name
Test status
Simulation time 227992448 ps
CPU time 0.88 seconds
Started Jul 02 09:11:31 AM PDT 24
Finished Jul 02 09:11:35 AM PDT 24
Peak memory 206212 kb
Host smart-3f5ffa22-1216-44b3-b06c-ac04face9acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34616
60637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3461660637
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1297684132
Short name T2167
Test name
Test status
Simulation time 220184994 ps
CPU time 0.84 seconds
Started Jul 02 09:11:31 AM PDT 24
Finished Jul 02 09:11:35 AM PDT 24
Peak memory 206212 kb
Host smart-87564839-244b-475a-95d2-872585469962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12976
84132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1297684132
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.484804806
Short name T812
Test name
Test status
Simulation time 163316184 ps
CPU time 0.78 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206128 kb
Host smart-b9a2a691-25f4-4d6f-8177-ef602c43d0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48480
4806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.484804806
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.456753781
Short name T1776
Test name
Test status
Simulation time 194530738 ps
CPU time 0.84 seconds
Started Jul 02 09:11:33 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206336 kb
Host smart-6ec8409b-16b3-4220-943e-4a0a0747feec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45675
3781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.456753781
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3224122625
Short name T1352
Test name
Test status
Simulation time 177479480 ps
CPU time 0.8 seconds
Started Jul 02 09:11:36 AM PDT 24
Finished Jul 02 09:11:38 AM PDT 24
Peak memory 205236 kb
Host smart-de1f07a0-b4a1-479c-9627-1a472a17da51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32241
22625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3224122625
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2371030576
Short name T2279
Test name
Test status
Simulation time 149612649 ps
CPU time 0.76 seconds
Started Jul 02 09:11:31 AM PDT 24
Finished Jul 02 09:11:35 AM PDT 24
Peak memory 206208 kb
Host smart-4c51b258-94d0-4ac8-868d-d28e60155935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23710
30576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2371030576
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.4250949725
Short name T2681
Test name
Test status
Simulation time 240443853 ps
CPU time 0.99 seconds
Started Jul 02 09:11:36 AM PDT 24
Finished Jul 02 09:11:42 AM PDT 24
Peak memory 205376 kb
Host smart-8449f6fb-0605-4194-96a4-12785c1ffdb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42509
49725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.4250949725
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.2653098688
Short name T2268
Test name
Test status
Simulation time 4064164776 ps
CPU time 39.89 seconds
Started Jul 02 09:11:35 AM PDT 24
Finished Jul 02 09:12:17 AM PDT 24
Peak memory 206512 kb
Host smart-cb1b6283-3688-4d90-bcd3-f8969ae40c09
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2653098688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.2653098688
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3631494349
Short name T2162
Test name
Test status
Simulation time 161917996 ps
CPU time 0.81 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206128 kb
Host smart-18582856-c680-42e0-aee7-b4b006b2fcaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36314
94349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3631494349
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1921960428
Short name T2307
Test name
Test status
Simulation time 152876148 ps
CPU time 0.82 seconds
Started Jul 02 09:11:31 AM PDT 24
Finished Jul 02 09:11:34 AM PDT 24
Peak memory 206204 kb
Host smart-743741a6-d0f2-4ed0-81b2-67b077dbdab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19219
60428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1921960428
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.870656018
Short name T864
Test name
Test status
Simulation time 209772410 ps
CPU time 0.89 seconds
Started Jul 02 09:11:34 AM PDT 24
Finished Jul 02 09:11:36 AM PDT 24
Peak memory 206164 kb
Host smart-e7f3c4b3-5244-48c5-a68f-ea9df79277f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87065
6018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.870656018
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3451342092
Short name T792
Test name
Test status
Simulation time 4288060693 ps
CPU time 39.43 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:12:14 AM PDT 24
Peak memory 206452 kb
Host smart-ba0adb27-7b07-4f88-aca5-e2a359a2ad61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34513
42092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3451342092
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1712735787
Short name T552
Test name
Test status
Simulation time 78477570 ps
CPU time 0.77 seconds
Started Jul 02 09:11:53 AM PDT 24
Finished Jul 02 09:11:54 AM PDT 24
Peak memory 206160 kb
Host smart-28b603a3-17d9-43af-98aa-fa44dc7ca07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1712735787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1712735787
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3598824663
Short name T1662
Test name
Test status
Simulation time 4210130860 ps
CPU time 5.56 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:11:40 AM PDT 24
Peak memory 206232 kb
Host smart-0f9d7300-02cb-40b4-ac42-e7b8dad4e371
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3598824663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.3598824663
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2302468764
Short name T1730
Test name
Test status
Simulation time 13326798998 ps
CPU time 13.02 seconds
Started Jul 02 09:11:33 AM PDT 24
Finished Jul 02 09:11:48 AM PDT 24
Peak memory 206408 kb
Host smart-b5c0ae5a-d395-4cc1-8e5d-c261e792959f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2302468764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2302468764
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.983577935
Short name T2346
Test name
Test status
Simulation time 23404702799 ps
CPU time 23.09 seconds
Started Jul 02 09:11:32 AM PDT 24
Finished Jul 02 09:11:57 AM PDT 24
Peak memory 206432 kb
Host smart-cd0a2ab9-163e-4935-b8cb-20dee3e12f08
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=983577935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.983577935
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3657155860
Short name T2447
Test name
Test status
Simulation time 160833114 ps
CPU time 0.78 seconds
Started Jul 02 09:11:37 AM PDT 24
Finished Jul 02 09:11:39 AM PDT 24
Peak memory 206072 kb
Host smart-048bbfcf-30b8-48d4-8e15-720fcb350160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36571
55860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3657155860
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1202854334
Short name T1617
Test name
Test status
Simulation time 190051959 ps
CPU time 0.79 seconds
Started Jul 02 09:11:36 AM PDT 24
Finished Jul 02 09:11:38 AM PDT 24
Peak memory 206176 kb
Host smart-39b1a107-11f9-41aa-b2ce-5a08844d09f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12028
54334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1202854334
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.4103731520
Short name T1797
Test name
Test status
Simulation time 276149846 ps
CPU time 1.06 seconds
Started Jul 02 09:11:52 AM PDT 24
Finished Jul 02 09:11:54 AM PDT 24
Peak memory 206208 kb
Host smart-752da9f6-1aa4-45be-89d4-cba7a53fe4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41037
31520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.4103731520
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3703697424
Short name T1331
Test name
Test status
Simulation time 1538196254 ps
CPU time 3.36 seconds
Started Jul 02 09:11:39 AM PDT 24
Finished Jul 02 09:11:43 AM PDT 24
Peak memory 206448 kb
Host smart-454594ed-09a7-4d1a-bfa0-7a95d828c82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37036
97424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3703697424
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1749565354
Short name T171
Test name
Test status
Simulation time 13596695935 ps
CPU time 23.73 seconds
Started Jul 02 09:11:43 AM PDT 24
Finished Jul 02 09:12:08 AM PDT 24
Peak memory 206460 kb
Host smart-c38204ae-0863-46dc-a667-02327e470251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17495
65354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1749565354
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2745174320
Short name T2379
Test name
Test status
Simulation time 341909885 ps
CPU time 1.13 seconds
Started Jul 02 09:11:39 AM PDT 24
Finished Jul 02 09:11:41 AM PDT 24
Peak memory 206212 kb
Host smart-00f61aca-c137-4dee-a83e-bbf63225d502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27451
74320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2745174320
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3163231603
Short name T1781
Test name
Test status
Simulation time 144081089 ps
CPU time 0.73 seconds
Started Jul 02 09:11:37 AM PDT 24
Finished Jul 02 09:11:39 AM PDT 24
Peak memory 206212 kb
Host smart-4838c59b-6a68-4ceb-9ded-347191283631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31632
31603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3163231603
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.1049299828
Short name T385
Test name
Test status
Simulation time 45669620 ps
CPU time 0.64 seconds
Started Jul 02 09:11:34 AM PDT 24
Finished Jul 02 09:11:37 AM PDT 24
Peak memory 206160 kb
Host smart-0082ec48-428d-4581-bf75-cc81a981b8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10492
99828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1049299828
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.4210550083
Short name T2598
Test name
Test status
Simulation time 925363699 ps
CPU time 2.04 seconds
Started Jul 02 09:11:37 AM PDT 24
Finished Jul 02 09:11:40 AM PDT 24
Peak memory 206488 kb
Host smart-b9cdbf9f-6984-402a-a684-556a81e7a23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42105
50083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.4210550083
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.345368449
Short name T1847
Test name
Test status
Simulation time 158200907 ps
CPU time 1.2 seconds
Started Jul 02 09:11:43 AM PDT 24
Finished Jul 02 09:11:45 AM PDT 24
Peak memory 206356 kb
Host smart-eb7e07a6-c0c8-49c7-b9c0-d90a64ec434c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34536
8449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.345368449
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.1262040465
Short name T464
Test name
Test status
Simulation time 238131560 ps
CPU time 0.91 seconds
Started Jul 02 09:11:42 AM PDT 24
Finished Jul 02 09:11:44 AM PDT 24
Peak memory 206224 kb
Host smart-c970b812-6144-4b63-bb01-ec4dc0a7da2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12620
40465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.1262040465
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.621636082
Short name T234
Test name
Test status
Simulation time 147036369 ps
CPU time 0.78 seconds
Started Jul 02 09:11:43 AM PDT 24
Finished Jul 02 09:11:45 AM PDT 24
Peak memory 206152 kb
Host smart-1ee3a588-3121-41d2-96f0-eae67d0550ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62163
6082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.621636082
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.4061000970
Short name T1111
Test name
Test status
Simulation time 237303691 ps
CPU time 1 seconds
Started Jul 02 09:11:49 AM PDT 24
Finished Jul 02 09:11:50 AM PDT 24
Peak memory 206184 kb
Host smart-4ce6605d-a2e7-4ffd-9302-460fb3579e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40610
00970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.4061000970
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.3718214736
Short name T2092
Test name
Test status
Simulation time 7354227013 ps
CPU time 70.26 seconds
Started Jul 02 09:11:45 AM PDT 24
Finished Jul 02 09:12:56 AM PDT 24
Peak memory 206472 kb
Host smart-e16474ce-b6fc-4b30-9472-b9085cb1af1d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3718214736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.3718214736
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3945952469
Short name T1268
Test name
Test status
Simulation time 244332070 ps
CPU time 0.85 seconds
Started Jul 02 09:11:39 AM PDT 24
Finished Jul 02 09:11:41 AM PDT 24
Peak memory 206188 kb
Host smart-78b6d6cf-3915-4694-906b-c9ab47515762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39459
52469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3945952469
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.491258907
Short name T1373
Test name
Test status
Simulation time 23329407115 ps
CPU time 25.33 seconds
Started Jul 02 09:11:38 AM PDT 24
Finished Jul 02 09:12:04 AM PDT 24
Peak memory 206244 kb
Host smart-1b4a6aa3-faf7-438a-8b83-afae036236e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49125
8907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.491258907
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1769940618
Short name T347
Test name
Test status
Simulation time 3318147588 ps
CPU time 3.63 seconds
Started Jul 02 09:11:37 AM PDT 24
Finished Jul 02 09:11:42 AM PDT 24
Peak memory 206252 kb
Host smart-c2d846d1-b985-481b-9374-d9112e43a6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17699
40618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1769940618
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1284365653
Short name T686
Test name
Test status
Simulation time 11519785974 ps
CPU time 332.84 seconds
Started Jul 02 09:11:40 AM PDT 24
Finished Jul 02 09:17:14 AM PDT 24
Peak memory 206528 kb
Host smart-8fd74848-b47b-486a-b05d-7eeb35253ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12843
65653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1284365653
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.1030771713
Short name T1258
Test name
Test status
Simulation time 6013186942 ps
CPU time 169.52 seconds
Started Jul 02 09:11:50 AM PDT 24
Finished Jul 02 09:14:40 AM PDT 24
Peak memory 206412 kb
Host smart-712d1d6c-4630-401c-97b1-f87c717eb072
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1030771713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.1030771713
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.4224526385
Short name T2210
Test name
Test status
Simulation time 259013752 ps
CPU time 1.01 seconds
Started Jul 02 09:11:47 AM PDT 24
Finished Jul 02 09:11:49 AM PDT 24
Peak memory 206188 kb
Host smart-baa5d25f-37b3-4337-bff8-1ef42d69d664
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4224526385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.4224526385
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.357650096
Short name T1810
Test name
Test status
Simulation time 188107771 ps
CPU time 0.87 seconds
Started Jul 02 09:11:48 AM PDT 24
Finished Jul 02 09:11:50 AM PDT 24
Peak memory 206208 kb
Host smart-fe060a72-dd3a-48c4-97db-4df0cf74760f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35765
0096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.357650096
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3379172536
Short name T1298
Test name
Test status
Simulation time 4870261570 ps
CPU time 140.66 seconds
Started Jul 02 09:11:34 AM PDT 24
Finished Jul 02 09:13:57 AM PDT 24
Peak memory 206456 kb
Host smart-4803ab51-2c96-4946-9c0f-0c15ec1839e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33791
72536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3379172536
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.3304525678
Short name T2469
Test name
Test status
Simulation time 7134124685 ps
CPU time 54.44 seconds
Started Jul 02 09:11:39 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206460 kb
Host smart-b5fd26aa-61dd-4ae0-b644-93bbd01c6f78
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3304525678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.3304525678
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.2549424310
Short name T2657
Test name
Test status
Simulation time 172390956 ps
CPU time 0.8 seconds
Started Jul 02 09:11:48 AM PDT 24
Finished Jul 02 09:11:50 AM PDT 24
Peak memory 206160 kb
Host smart-c5dd1605-5b36-4b56-a27a-224dbbe04734
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2549424310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2549424310
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.280705843
Short name T754
Test name
Test status
Simulation time 169964412 ps
CPU time 0.79 seconds
Started Jul 02 09:11:40 AM PDT 24
Finished Jul 02 09:11:42 AM PDT 24
Peak memory 206192 kb
Host smart-373b7485-0248-4e4f-817d-63735dd88cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28070
5843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.280705843
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.241193435
Short name T119
Test name
Test status
Simulation time 202352507 ps
CPU time 0.9 seconds
Started Jul 02 09:11:44 AM PDT 24
Finished Jul 02 09:11:46 AM PDT 24
Peak memory 206196 kb
Host smart-9ff9b582-4820-46d2-8248-4abe5ac8811a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24119
3435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.241193435
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3232336863
Short name T271
Test name
Test status
Simulation time 194351725 ps
CPU time 0.88 seconds
Started Jul 02 09:11:39 AM PDT 24
Finished Jul 02 09:11:41 AM PDT 24
Peak memory 206180 kb
Host smart-bfcb4dda-5d64-4697-b4c1-9e2d71722558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32323
36863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3232336863
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1813007543
Short name T270
Test name
Test status
Simulation time 156410732 ps
CPU time 0.81 seconds
Started Jul 02 09:11:43 AM PDT 24
Finished Jul 02 09:11:45 AM PDT 24
Peak memory 206204 kb
Host smart-4716a75c-9b89-498a-bc91-7e0b96e4f332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18130
07543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1813007543
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.161058199
Short name T2638
Test name
Test status
Simulation time 174719744 ps
CPU time 0.81 seconds
Started Jul 02 09:11:54 AM PDT 24
Finished Jul 02 09:11:55 AM PDT 24
Peak memory 206200 kb
Host smart-52089fd2-f4a5-4e8a-b148-5126165390e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16105
8199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.161058199
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.381380748
Short name T1495
Test name
Test status
Simulation time 158781235 ps
CPU time 0.79 seconds
Started Jul 02 09:11:51 AM PDT 24
Finished Jul 02 09:11:52 AM PDT 24
Peak memory 206172 kb
Host smart-d6054cbd-aca8-4d7a-906a-b42db7ea189f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38138
0748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.381380748
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2266214150
Short name T1489
Test name
Test status
Simulation time 238002568 ps
CPU time 1.03 seconds
Started Jul 02 09:11:42 AM PDT 24
Finished Jul 02 09:11:44 AM PDT 24
Peak memory 206104 kb
Host smart-4d761fcb-ef92-4fe5-a95f-08180de099b3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2266214150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2266214150
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1870693598
Short name T481
Test name
Test status
Simulation time 149906686 ps
CPU time 0.78 seconds
Started Jul 02 09:11:44 AM PDT 24
Finished Jul 02 09:11:46 AM PDT 24
Peak memory 206220 kb
Host smart-07917f5c-5b22-4813-b8ab-67152745cc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18706
93598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1870693598
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3248822715
Short name T1284
Test name
Test status
Simulation time 36977012 ps
CPU time 0.68 seconds
Started Jul 02 09:11:42 AM PDT 24
Finished Jul 02 09:11:44 AM PDT 24
Peak memory 206120 kb
Host smart-3a1d2512-ea1d-4c15-98e1-df6e9155a685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32488
22715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3248822715
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1944583903
Short name T2548
Test name
Test status
Simulation time 17231402238 ps
CPU time 38.66 seconds
Started Jul 02 09:11:51 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206460 kb
Host smart-1ee67dfe-3544-4aae-a956-4836f7a0ebd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19445
83903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1944583903
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.928425110
Short name T974
Test name
Test status
Simulation time 186651986 ps
CPU time 0.83 seconds
Started Jul 02 09:11:44 AM PDT 24
Finished Jul 02 09:11:46 AM PDT 24
Peak memory 206188 kb
Host smart-1c5b49b5-5cb5-4f42-a0c1-83add8b11c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92842
5110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.928425110
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.820269121
Short name T2351
Test name
Test status
Simulation time 244306117 ps
CPU time 0.98 seconds
Started Jul 02 09:11:58 AM PDT 24
Finished Jul 02 09:11:59 AM PDT 24
Peak memory 206208 kb
Host smart-c5de15c3-5333-4e09-8bc4-9bdb9e3044ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82026
9121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.820269121
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.1785065846
Short name T663
Test name
Test status
Simulation time 196990120 ps
CPU time 0.87 seconds
Started Jul 02 09:11:40 AM PDT 24
Finished Jul 02 09:11:42 AM PDT 24
Peak memory 206216 kb
Host smart-310b8dfb-5bd3-4f1a-bb31-e464a08fad2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17850
65846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.1785065846
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3680555256
Short name T241
Test name
Test status
Simulation time 222255712 ps
CPU time 0.9 seconds
Started Jul 02 09:11:38 AM PDT 24
Finished Jul 02 09:11:39 AM PDT 24
Peak memory 206388 kb
Host smart-2cfc113c-4d5b-4934-8476-1fc56e35d2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36805
55256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3680555256
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1282707965
Short name T1
Test name
Test status
Simulation time 159421451 ps
CPU time 0.82 seconds
Started Jul 02 09:11:43 AM PDT 24
Finished Jul 02 09:11:45 AM PDT 24
Peak memory 206204 kb
Host smart-9673ae20-fc04-421b-a6b5-589f27766f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12827
07965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1282707965
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2724472112
Short name T2525
Test name
Test status
Simulation time 159765566 ps
CPU time 0.8 seconds
Started Jul 02 09:11:40 AM PDT 24
Finished Jul 02 09:11:41 AM PDT 24
Peak memory 206176 kb
Host smart-6614d7c7-b4dd-4ccf-98a3-6653b49167d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27244
72112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2724472112
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3842268606
Short name T389
Test name
Test status
Simulation time 158839704 ps
CPU time 0.83 seconds
Started Jul 02 09:11:48 AM PDT 24
Finished Jul 02 09:11:49 AM PDT 24
Peak memory 206200 kb
Host smart-c7ac79db-05e1-4cf1-97a6-e93e9b1b93f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38422
68606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3842268606
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3074239302
Short name T1161
Test name
Test status
Simulation time 197546940 ps
CPU time 0.9 seconds
Started Jul 02 09:11:43 AM PDT 24
Finished Jul 02 09:11:45 AM PDT 24
Peak memory 206204 kb
Host smart-a6ba0c32-8dae-4d71-9321-4c536fc7bed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30742
39302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3074239302
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.568922957
Short name T1214
Test name
Test status
Simulation time 3823566488 ps
CPU time 111.97 seconds
Started Jul 02 09:11:55 AM PDT 24
Finished Jul 02 09:13:48 AM PDT 24
Peak memory 206524 kb
Host smart-989cbab5-5c9e-4c02-a23a-2d368c75eec7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=568922957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.568922957
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2353116017
Short name T2634
Test name
Test status
Simulation time 175533175 ps
CPU time 0.82 seconds
Started Jul 02 09:11:42 AM PDT 24
Finished Jul 02 09:11:43 AM PDT 24
Peak memory 206128 kb
Host smart-bce1a0b1-97b6-4b20-a570-6bd0075e1506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23531
16017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2353116017
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.902360997
Short name T348
Test name
Test status
Simulation time 175733769 ps
CPU time 0.8 seconds
Started Jul 02 09:11:53 AM PDT 24
Finished Jul 02 09:11:54 AM PDT 24
Peak memory 206212 kb
Host smart-fb52f6d7-e583-4ad7-af95-b71bce91ac07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90236
0997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.902360997
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.3490599011
Short name T2473
Test name
Test status
Simulation time 455259068 ps
CPU time 1.23 seconds
Started Jul 02 09:11:40 AM PDT 24
Finished Jul 02 09:11:42 AM PDT 24
Peak memory 206220 kb
Host smart-33187faa-81d8-4b51-911f-51acbd645548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34905
99011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.3490599011
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2241402840
Short name T2099
Test name
Test status
Simulation time 5153812825 ps
CPU time 143.76 seconds
Started Jul 02 09:11:44 AM PDT 24
Finished Jul 02 09:14:09 AM PDT 24
Peak memory 206508 kb
Host smart-4ffc85bb-120c-42de-9510-fcd131d00a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22414
02840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2241402840
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1990211859
Short name T1890
Test name
Test status
Simulation time 42779209 ps
CPU time 0.67 seconds
Started Jul 02 09:12:07 AM PDT 24
Finished Jul 02 09:12:09 AM PDT 24
Peak memory 206200 kb
Host smart-ac22aebc-92c1-46d9-be32-b3b3afec1927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1990211859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1990211859
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1969182463
Short name T247
Test name
Test status
Simulation time 3592417339 ps
CPU time 4.14 seconds
Started Jul 02 09:11:43 AM PDT 24
Finished Jul 02 09:11:47 AM PDT 24
Peak memory 206444 kb
Host smart-4d4a77ab-9dd6-491f-9d92-e9482c066aeb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1969182463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1969182463
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2573508647
Short name T798
Test name
Test status
Simulation time 13367868685 ps
CPU time 13.85 seconds
Started Jul 02 09:11:44 AM PDT 24
Finished Jul 02 09:11:59 AM PDT 24
Peak memory 206244 kb
Host smart-d3ca2b64-6333-4f7f-987c-225106c98ce7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2573508647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2573508647
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.528842014
Short name T2444
Test name
Test status
Simulation time 23413212363 ps
CPU time 28.82 seconds
Started Jul 02 09:11:47 AM PDT 24
Finished Jul 02 09:12:16 AM PDT 24
Peak memory 206240 kb
Host smart-3fe799f9-210e-4538-82e2-6d6a42f5e447
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=528842014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.528842014
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1750610057
Short name T402
Test name
Test status
Simulation time 153912795 ps
CPU time 0.8 seconds
Started Jul 02 09:11:44 AM PDT 24
Finished Jul 02 09:11:46 AM PDT 24
Peak memory 206196 kb
Host smart-f11393fd-48b1-4ef7-bccc-8eabfa8fe0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17506
10057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1750610057
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1523250674
Short name T2652
Test name
Test status
Simulation time 170427388 ps
CPU time 0.81 seconds
Started Jul 02 09:11:55 AM PDT 24
Finished Jul 02 09:11:57 AM PDT 24
Peak memory 206176 kb
Host smart-70efebe3-d4ec-4332-9b24-9ce54f39752d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15232
50674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1523250674
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3674620616
Short name T1975
Test name
Test status
Simulation time 146728904 ps
CPU time 0.76 seconds
Started Jul 02 09:11:57 AM PDT 24
Finished Jul 02 09:11:58 AM PDT 24
Peak memory 206168 kb
Host smart-33ff865e-71c5-4747-acee-f4fe89ed4433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36746
20616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3674620616
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.4170430944
Short name T1834
Test name
Test status
Simulation time 587270000 ps
CPU time 1.63 seconds
Started Jul 02 09:11:43 AM PDT 24
Finished Jul 02 09:11:45 AM PDT 24
Peak memory 206196 kb
Host smart-76b4db01-e9df-419f-86a5-2c2cdbde072f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41704
30944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.4170430944
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.338075298
Short name T1871
Test name
Test status
Simulation time 15726522039 ps
CPU time 27.13 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206512 kb
Host smart-6b89335f-6c06-442a-85f8-a66efe9861df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33807
5298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.338075298
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.3947210808
Short name T695
Test name
Test status
Simulation time 464316479 ps
CPU time 1.46 seconds
Started Jul 02 09:11:57 AM PDT 24
Finished Jul 02 09:11:59 AM PDT 24
Peak memory 206120 kb
Host smart-f1a81e87-ebe3-40bc-bc3a-1ae2fcd0ed9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39472
10808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.3947210808
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3076003254
Short name T1687
Test name
Test status
Simulation time 143880646 ps
CPU time 0.81 seconds
Started Jul 02 09:11:47 AM PDT 24
Finished Jul 02 09:11:49 AM PDT 24
Peak memory 206216 kb
Host smart-af172ac2-39aa-4f31-be2e-1e5139572dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30760
03254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3076003254
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.4224581782
Short name T1347
Test name
Test status
Simulation time 57296425 ps
CPU time 0.71 seconds
Started Jul 02 09:12:02 AM PDT 24
Finished Jul 02 09:12:04 AM PDT 24
Peak memory 206340 kb
Host smart-6f847d84-4470-4efa-87df-d1e177b18495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42245
81782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.4224581782
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.712643764
Short name T2442
Test name
Test status
Simulation time 841998042 ps
CPU time 2.17 seconds
Started Jul 02 09:11:54 AM PDT 24
Finished Jul 02 09:11:56 AM PDT 24
Peak memory 206452 kb
Host smart-e7b24296-cc6c-4541-80ca-0f3d3b44a0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71264
3764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.712643764
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3613386376
Short name T2264
Test name
Test status
Simulation time 192827988 ps
CPU time 1.82 seconds
Started Jul 02 09:11:44 AM PDT 24
Finished Jul 02 09:11:47 AM PDT 24
Peak memory 206396 kb
Host smart-d2dd40fe-4190-4ded-aa27-d8bccaba1dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36133
86376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3613386376
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3537851684
Short name T863
Test name
Test status
Simulation time 289789405 ps
CPU time 0.96 seconds
Started Jul 02 09:11:45 AM PDT 24
Finished Jul 02 09:11:47 AM PDT 24
Peak memory 206168 kb
Host smart-f0556867-6bc6-478d-80e8-d3e0d84987ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35378
51684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3537851684
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1402576352
Short name T112
Test name
Test status
Simulation time 160186299 ps
CPU time 0.81 seconds
Started Jul 02 09:11:47 AM PDT 24
Finished Jul 02 09:11:48 AM PDT 24
Peak memory 206204 kb
Host smart-42ebac1c-db7f-4ce0-be03-53dc638b251a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14025
76352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1402576352
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2027044239
Short name T817
Test name
Test status
Simulation time 258122542 ps
CPU time 1 seconds
Started Jul 02 09:11:49 AM PDT 24
Finished Jul 02 09:11:50 AM PDT 24
Peak memory 206212 kb
Host smart-66ea1f8b-260a-493b-9be8-164563d9fb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20270
44239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2027044239
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3192410512
Short name T1909
Test name
Test status
Simulation time 191911585 ps
CPU time 0.84 seconds
Started Jul 02 09:11:51 AM PDT 24
Finished Jul 02 09:11:52 AM PDT 24
Peak memory 206212 kb
Host smart-5c8d542c-cb4a-4b29-80b9-9fb915afc165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31924
10512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3192410512
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.3801595673
Short name T994
Test name
Test status
Simulation time 23355875578 ps
CPU time 25.67 seconds
Started Jul 02 09:11:43 AM PDT 24
Finished Jul 02 09:12:09 AM PDT 24
Peak memory 206220 kb
Host smart-060a986a-0287-4f89-a8f4-74e5a604c890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38015
95673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.3801595673
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3275318749
Short name T1255
Test name
Test status
Simulation time 3334068541 ps
CPU time 4.25 seconds
Started Jul 02 09:11:52 AM PDT 24
Finished Jul 02 09:11:56 AM PDT 24
Peak memory 206268 kb
Host smart-57f6a77c-7507-4ecb-9d4a-7c128eb449af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32753
18749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3275318749
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.635097406
Short name T2649
Test name
Test status
Simulation time 9064277633 ps
CPU time 83.64 seconds
Started Jul 02 09:11:59 AM PDT 24
Finished Jul 02 09:13:23 AM PDT 24
Peak memory 206504 kb
Host smart-2f627368-e910-4b87-81c4-7f44cb69c15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63509
7406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.635097406
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.334669869
Short name T2312
Test name
Test status
Simulation time 6136582150 ps
CPU time 57.92 seconds
Started Jul 02 09:11:56 AM PDT 24
Finished Jul 02 09:12:54 AM PDT 24
Peak memory 206464 kb
Host smart-53c73d34-2f9d-4329-a305-b0572f50eab4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=334669869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.334669869
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.1083397145
Short name T499
Test name
Test status
Simulation time 250044531 ps
CPU time 0.91 seconds
Started Jul 02 09:11:55 AM PDT 24
Finished Jul 02 09:11:57 AM PDT 24
Peak memory 206188 kb
Host smart-d3e3f392-8bb8-4ac0-81eb-b1967cc7fa7f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1083397145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.1083397145
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1908364940
Short name T2622
Test name
Test status
Simulation time 218812272 ps
CPU time 0.96 seconds
Started Jul 02 09:11:44 AM PDT 24
Finished Jul 02 09:11:47 AM PDT 24
Peak memory 206128 kb
Host smart-ddf3eaac-ce1f-41fe-b4ed-6b7d11736c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19083
64940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1908364940
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.387608137
Short name T2366
Test name
Test status
Simulation time 5696691406 ps
CPU time 54.83 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:12:56 AM PDT 24
Peak memory 206380 kb
Host smart-348bd412-2c51-4b8c-8b92-47db49d35c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38760
8137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.387608137
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.2961746934
Short name T1894
Test name
Test status
Simulation time 3954480963 ps
CPU time 108.79 seconds
Started Jul 02 09:11:42 AM PDT 24
Finished Jul 02 09:13:32 AM PDT 24
Peak memory 206400 kb
Host smart-bb9e06e0-ddaa-4be7-8ed4-a85179bd8951
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2961746934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.2961746934
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.53506462
Short name T345
Test name
Test status
Simulation time 154906556 ps
CPU time 0.8 seconds
Started Jul 02 09:11:50 AM PDT 24
Finished Jul 02 09:11:52 AM PDT 24
Peak memory 206148 kb
Host smart-1812b18b-18a7-4d7d-a4d2-847659da22a0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=53506462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.53506462
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1176853781
Short name T2698
Test name
Test status
Simulation time 158931966 ps
CPU time 0.81 seconds
Started Jul 02 09:11:44 AM PDT 24
Finished Jul 02 09:11:46 AM PDT 24
Peak memory 206208 kb
Host smart-e73392dc-dfed-43a3-848c-431bb2187b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11768
53781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1176853781
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1385089532
Short name T138
Test name
Test status
Simulation time 236515318 ps
CPU time 0.84 seconds
Started Jul 02 09:11:44 AM PDT 24
Finished Jul 02 09:11:46 AM PDT 24
Peak memory 206188 kb
Host smart-80a674e9-0147-4e1c-b2a2-de5e68080e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13850
89532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1385089532
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1191992772
Short name T1295
Test name
Test status
Simulation time 178613085 ps
CPU time 0.92 seconds
Started Jul 02 09:11:58 AM PDT 24
Finished Jul 02 09:11:59 AM PDT 24
Peak memory 206124 kb
Host smart-9ef9867a-d0c9-4def-959a-13914b34da93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11919
92772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1191992772
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1521912742
Short name T1807
Test name
Test status
Simulation time 173878758 ps
CPU time 0.84 seconds
Started Jul 02 09:12:03 AM PDT 24
Finished Jul 02 09:12:05 AM PDT 24
Peak memory 206208 kb
Host smart-37229e54-38da-4363-9dab-9308043302c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15219
12742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1521912742
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3288409251
Short name T2532
Test name
Test status
Simulation time 218623359 ps
CPU time 0.81 seconds
Started Jul 02 09:11:58 AM PDT 24
Finished Jul 02 09:11:59 AM PDT 24
Peak memory 206208 kb
Host smart-d1eb80f7-6bac-48e3-adf8-ef8df0da34eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32884
09251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3288409251
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1504640152
Short name T1089
Test name
Test status
Simulation time 159847178 ps
CPU time 0.8 seconds
Started Jul 02 09:12:02 AM PDT 24
Finished Jul 02 09:12:04 AM PDT 24
Peak memory 206160 kb
Host smart-68578d11-ae17-4f0b-a463-a69a5504af0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15046
40152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1504640152
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.520015955
Short name T1488
Test name
Test status
Simulation time 191041167 ps
CPU time 0.87 seconds
Started Jul 02 09:11:54 AM PDT 24
Finished Jul 02 09:11:55 AM PDT 24
Peak memory 206148 kb
Host smart-59fb75c4-9191-449c-8ecd-08c98e1c8051
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=520015955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.520015955
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3757941269
Short name T800
Test name
Test status
Simulation time 165622263 ps
CPU time 0.86 seconds
Started Jul 02 09:11:48 AM PDT 24
Finished Jul 02 09:11:49 AM PDT 24
Peak memory 206180 kb
Host smart-43f73d77-bef6-4a45-8803-013728dac445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37579
41269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3757941269
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1885854593
Short name T2172
Test name
Test status
Simulation time 37231382 ps
CPU time 0.65 seconds
Started Jul 02 09:11:55 AM PDT 24
Finished Jul 02 09:11:56 AM PDT 24
Peak memory 206072 kb
Host smart-c106a2cf-4da0-468c-a003-cf8f2ed95512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18858
54593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1885854593
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1357557577
Short name T2221
Test name
Test status
Simulation time 13368832085 ps
CPU time 29.11 seconds
Started Jul 02 09:11:59 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206512 kb
Host smart-8c9b828a-e474-483d-af89-abaa582472b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13575
57577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1357557577
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1703837433
Short name T52
Test name
Test status
Simulation time 194967899 ps
CPU time 0.85 seconds
Started Jul 02 09:11:53 AM PDT 24
Finished Jul 02 09:11:54 AM PDT 24
Peak memory 206212 kb
Host smart-02501cb6-5600-4b42-9baf-0a22a0de759c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17038
37433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1703837433
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2677890953
Short name T335
Test name
Test status
Simulation time 221924091 ps
CPU time 0.85 seconds
Started Jul 02 09:12:03 AM PDT 24
Finished Jul 02 09:12:05 AM PDT 24
Peak memory 206216 kb
Host smart-89d194e9-e477-49b8-9037-987cfc86c22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26778
90953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2677890953
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.4193816735
Short name T473
Test name
Test status
Simulation time 164756298 ps
CPU time 0.83 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:12:08 AM PDT 24
Peak memory 206220 kb
Host smart-5493cf57-ec34-4445-bcb8-2b57a63f700a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41938
16735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.4193816735
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2092834555
Short name T1938
Test name
Test status
Simulation time 164875682 ps
CPU time 0.85 seconds
Started Jul 02 09:12:07 AM PDT 24
Finished Jul 02 09:12:09 AM PDT 24
Peak memory 206160 kb
Host smart-06408426-2a82-4df2-a94e-74ed3e1ecc6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20928
34555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2092834555
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.4230205588
Short name T2175
Test name
Test status
Simulation time 145740827 ps
CPU time 0.77 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:12:03 AM PDT 24
Peak memory 206200 kb
Host smart-4d0febf7-fe80-4b8e-a3b7-1355c895fc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42302
05588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.4230205588
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3482158345
Short name T2679
Test name
Test status
Simulation time 171689689 ps
CPU time 0.83 seconds
Started Jul 02 09:11:59 AM PDT 24
Finished Jul 02 09:12:00 AM PDT 24
Peak memory 206208 kb
Host smart-02e36eb8-0109-46df-91ee-ccfbda387251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34821
58345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3482158345
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1118452894
Short name T1000
Test name
Test status
Simulation time 198326402 ps
CPU time 0.89 seconds
Started Jul 02 09:11:55 AM PDT 24
Finished Jul 02 09:12:02 AM PDT 24
Peak memory 206212 kb
Host smart-95cb080b-4533-4d61-86a3-622ffecaeba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11184
52894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1118452894
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3021044966
Short name T1940
Test name
Test status
Simulation time 235432198 ps
CPU time 1.01 seconds
Started Jul 02 09:11:57 AM PDT 24
Finished Jul 02 09:11:58 AM PDT 24
Peak memory 206180 kb
Host smart-1571f18c-ff56-477e-bc0d-addf09cd9056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30210
44966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3021044966
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.1414727441
Short name T2511
Test name
Test status
Simulation time 6275768018 ps
CPU time 58.12 seconds
Started Jul 02 09:11:57 AM PDT 24
Finished Jul 02 09:12:56 AM PDT 24
Peak memory 206520 kb
Host smart-42806f44-0080-4b27-b2fb-1fe838a22c9a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1414727441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.1414727441
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.888151534
Short name T2580
Test name
Test status
Simulation time 166143516 ps
CPU time 0.82 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:12:03 AM PDT 24
Peak memory 206184 kb
Host smart-e61d2eda-4123-499e-a7f4-462893d0e8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88815
1534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.888151534
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3680553652
Short name T926
Test name
Test status
Simulation time 202013363 ps
CPU time 0.85 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:12:03 AM PDT 24
Peak memory 206188 kb
Host smart-15039040-0546-4d61-b714-ff8bda68716a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36805
53652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3680553652
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.219983067
Short name T2449
Test name
Test status
Simulation time 822842439 ps
CPU time 1.95 seconds
Started Jul 02 09:11:50 AM PDT 24
Finished Jul 02 09:11:52 AM PDT 24
Peak memory 206428 kb
Host smart-6d36c895-bcf4-4fb2-aead-c1cab175ac00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21998
3067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.219983067
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2870752050
Short name T562
Test name
Test status
Simulation time 4164297466 ps
CPU time 118.69 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:14:06 AM PDT 24
Peak memory 206384 kb
Host smart-e99f8f41-5d77-4004-a8b3-471a396321e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28707
52050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2870752050
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.2143072544
Short name T1562
Test name
Test status
Simulation time 41919569 ps
CPU time 0.7 seconds
Started Jul 02 09:06:51 AM PDT 24
Finished Jul 02 09:06:54 AM PDT 24
Peak memory 206248 kb
Host smart-0816f0eb-c815-4f7d-877c-017a510c3e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2143072544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.2143072544
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1239702084
Short name T1123
Test name
Test status
Simulation time 3733110897 ps
CPU time 4.6 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:06:49 AM PDT 24
Peak memory 206244 kb
Host smart-ed830423-bd62-4902-9bbe-cf4fe9af042e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1239702084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.1239702084
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2009881087
Short name T2310
Test name
Test status
Simulation time 13472187309 ps
CPU time 12.26 seconds
Started Jul 02 09:06:38 AM PDT 24
Finished Jul 02 09:06:52 AM PDT 24
Peak memory 206456 kb
Host smart-c04356d8-c40b-4278-b1a0-aacbe8236ee0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2009881087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2009881087
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3380420987
Short name T724
Test name
Test status
Simulation time 23392862556 ps
CPU time 24.56 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:07:14 AM PDT 24
Peak memory 206116 kb
Host smart-f95bbf75-0aa7-4b11-995f-1e44022834d4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3380420987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3380420987
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3871867991
Short name T2241
Test name
Test status
Simulation time 166018766 ps
CPU time 0.79 seconds
Started Jul 02 09:06:38 AM PDT 24
Finished Jul 02 09:06:40 AM PDT 24
Peak memory 206212 kb
Host smart-0ba99cfd-221a-4eae-92ec-b363b69fbc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38718
67991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3871867991
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.1635286698
Short name T55
Test name
Test status
Simulation time 183552764 ps
CPU time 0.83 seconds
Started Jul 02 09:06:44 AM PDT 24
Finished Jul 02 09:06:46 AM PDT 24
Peak memory 206208 kb
Host smart-35109afd-df3f-41e1-bb95-4ae77926bf03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16352
86698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.1635286698
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.168732472
Short name T87
Test name
Test status
Simulation time 167698979 ps
CPU time 0.78 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:06:45 AM PDT 24
Peak memory 206160 kb
Host smart-91467cfd-9bb9-4b81-84d4-ab3997ffb8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16873
2472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.168732472
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1169786257
Short name T1885
Test name
Test status
Simulation time 183833714 ps
CPU time 0.84 seconds
Started Jul 02 09:06:46 AM PDT 24
Finished Jul 02 09:06:49 AM PDT 24
Peak memory 206080 kb
Host smart-0534b9e7-77b4-4bdb-9f84-83ffc4ebe344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11697
86257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1169786257
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.4062185701
Short name T1707
Test name
Test status
Simulation time 163862071 ps
CPU time 0.82 seconds
Started Jul 02 09:06:46 AM PDT 24
Finished Jul 02 09:06:49 AM PDT 24
Peak memory 206208 kb
Host smart-1afbeaa4-7abb-42cc-970e-8f7b7daf23ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40621
85701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.4062185701
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1406184166
Short name T1021
Test name
Test status
Simulation time 749443212 ps
CPU time 1.78 seconds
Started Jul 02 09:06:40 AM PDT 24
Finished Jul 02 09:06:42 AM PDT 24
Peak memory 206400 kb
Host smart-97b8a8fe-67f6-4324-844e-fe324c8506e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14061
84166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1406184166
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1412354001
Short name T99
Test name
Test status
Simulation time 19722802387 ps
CPU time 32.68 seconds
Started Jul 02 09:06:37 AM PDT 24
Finished Jul 02 09:07:11 AM PDT 24
Peak memory 206508 kb
Host smart-434849a8-14a6-473a-987d-4fd53718edc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14123
54001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1412354001
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1108883045
Short name T730
Test name
Test status
Simulation time 322400015 ps
CPU time 1.18 seconds
Started Jul 02 09:06:36 AM PDT 24
Finished Jul 02 09:06:39 AM PDT 24
Peak memory 206344 kb
Host smart-71c4b88a-27c7-4b78-aa22-786613d050b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11088
83045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1108883045
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3787623756
Short name T2483
Test name
Test status
Simulation time 144326686 ps
CPU time 0.77 seconds
Started Jul 02 09:06:34 AM PDT 24
Finished Jul 02 09:06:36 AM PDT 24
Peak memory 206208 kb
Host smart-c562c2a7-666f-4658-bac7-c84f6853a839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37876
23756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3787623756
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1577940968
Short name T256
Test name
Test status
Simulation time 31629892 ps
CPU time 0.69 seconds
Started Jul 02 09:06:35 AM PDT 24
Finished Jul 02 09:06:38 AM PDT 24
Peak memory 206192 kb
Host smart-387e86cf-1a27-4fa9-b639-0c282fdc8565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15779
40968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1577940968
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.984311313
Short name T623
Test name
Test status
Simulation time 1104076710 ps
CPU time 2.65 seconds
Started Jul 02 09:06:49 AM PDT 24
Finished Jul 02 09:06:54 AM PDT 24
Peak memory 206472 kb
Host smart-fff49a57-9867-4b5a-a144-e6d6c2eb4a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98431
1313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.984311313
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.227891305
Short name T88
Test name
Test status
Simulation time 255026346 ps
CPU time 1.77 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:06:46 AM PDT 24
Peak memory 206448 kb
Host smart-a94be7c0-4ef6-4a26-b3c7-a172019e5270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22789
1305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.227891305
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2885615343
Short name T2339
Test name
Test status
Simulation time 91236567659 ps
CPU time 138.57 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:09:02 AM PDT 24
Peak memory 206444 kb
Host smart-58006641-c63c-4e54-9d73-7d5255aac75b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2885615343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2885615343
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.1728452877
Short name T1957
Test name
Test status
Simulation time 119049185803 ps
CPU time 172.95 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:09:43 AM PDT 24
Peak memory 206624 kb
Host smart-ac27b7af-4a43-4c6c-9084-ac1a74cb9959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728452877 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.1728452877
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.4276411602
Short name T2119
Test name
Test status
Simulation time 87119516278 ps
CPU time 124.98 seconds
Started Jul 02 09:06:49 AM PDT 24
Finished Jul 02 09:08:56 AM PDT 24
Peak memory 206428 kb
Host smart-1359b2d1-f6ed-4ddb-b792-571a4fe3a3b4
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4276411602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.4276411602
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1988455812
Short name T1824
Test name
Test status
Simulation time 96191084890 ps
CPU time 139.13 seconds
Started Jul 02 09:06:39 AM PDT 24
Finished Jul 02 09:08:59 AM PDT 24
Peak memory 206400 kb
Host smart-0d5491f0-5ab1-4559-ad24-569773a07e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988455812 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1988455812
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.2166527225
Short name T633
Test name
Test status
Simulation time 83185864526 ps
CPU time 103.15 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:08:31 AM PDT 24
Peak memory 206452 kb
Host smart-8f1fa2f1-ec8f-4b07-9818-2433c1809090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21665
27225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.2166527225
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.43992517
Short name T488
Test name
Test status
Simulation time 214844225 ps
CPU time 0.87 seconds
Started Jul 02 09:06:38 AM PDT 24
Finished Jul 02 09:06:40 AM PDT 24
Peak memory 206216 kb
Host smart-c1218036-6ec4-4e18-a875-1312c0473a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43992
517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.43992517
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1627991946
Short name T1791
Test name
Test status
Simulation time 147600028 ps
CPU time 0.77 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:06:48 AM PDT 24
Peak memory 206188 kb
Host smart-7b36e974-87d7-4b00-b048-3472943166ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16279
91946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1627991946
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2240330438
Short name T2619
Test name
Test status
Simulation time 193027705 ps
CPU time 0.88 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:06:45 AM PDT 24
Peak memory 206200 kb
Host smart-93b61ed3-1b4e-4d25-b2a0-c7d8c3953c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22403
30438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2240330438
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.651400742
Short name T597
Test name
Test status
Simulation time 6024488403 ps
CPU time 56.73 seconds
Started Jul 02 09:06:46 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206436 kb
Host smart-26133c61-320f-41a1-83bb-84a1f8ffb9a7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=651400742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.651400742
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1186121540
Short name T2474
Test name
Test status
Simulation time 243507421 ps
CPU time 0.92 seconds
Started Jul 02 09:06:49 AM PDT 24
Finished Jul 02 09:06:52 AM PDT 24
Peak memory 206164 kb
Host smart-cd33ee60-5ea6-4421-b8ee-0fea1567d7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11861
21540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1186121540
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3686001017
Short name T2095
Test name
Test status
Simulation time 23373533464 ps
CPU time 24.32 seconds
Started Jul 02 09:06:42 AM PDT 24
Finished Jul 02 09:07:07 AM PDT 24
Peak memory 206268 kb
Host smart-11f4dc60-0bd9-4795-a83c-f1488009ac32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36860
01017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3686001017
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1380502008
Short name T1403
Test name
Test status
Simulation time 3344480624 ps
CPU time 4.26 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:06:52 AM PDT 24
Peak memory 206256 kb
Host smart-df201dc6-0053-4750-a832-96dd4731664d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13805
02008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1380502008
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.1069121472
Short name T2382
Test name
Test status
Simulation time 7960253658 ps
CPU time 76.8 seconds
Started Jul 02 09:06:56 AM PDT 24
Finished Jul 02 09:08:15 AM PDT 24
Peak memory 206504 kb
Host smart-077d3c13-45c5-4de0-bca5-abc2ad3b51ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10691
21472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.1069121472
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1333883959
Short name T1417
Test name
Test status
Simulation time 5940032987 ps
CPU time 170.05 seconds
Started Jul 02 09:06:36 AM PDT 24
Finished Jul 02 09:09:28 AM PDT 24
Peak memory 206404 kb
Host smart-ee62f6af-926a-43c0-8dcd-3e11202ee1d6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1333883959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1333883959
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.1394872955
Short name T1409
Test name
Test status
Simulation time 241392379 ps
CPU time 0.93 seconds
Started Jul 02 09:06:40 AM PDT 24
Finished Jul 02 09:06:42 AM PDT 24
Peak memory 206144 kb
Host smart-dc8a5d4e-023c-4b7a-a2d4-ba6fc3678988
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1394872955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.1394872955
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2581041395
Short name T2613
Test name
Test status
Simulation time 209248111 ps
CPU time 0.91 seconds
Started Jul 02 09:06:42 AM PDT 24
Finished Jul 02 09:06:43 AM PDT 24
Peak memory 206224 kb
Host smart-0b0fe2d8-43b5-4d67-afe7-96faca1af02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25810
41395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2581041395
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.4155304491
Short name T2496
Test name
Test status
Simulation time 6148782909 ps
CPU time 43.47 seconds
Started Jul 02 09:06:49 AM PDT 24
Finished Jul 02 09:07:34 AM PDT 24
Peak memory 206444 kb
Host smart-bada96e4-eed2-43b3-b4ae-42118791c867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41553
04491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.4155304491
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.1851735089
Short name T386
Test name
Test status
Simulation time 6836220268 ps
CPU time 48.56 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:07:38 AM PDT 24
Peak memory 206444 kb
Host smart-91f9afa7-350b-4c57-9252-bf0831866aba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1851735089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.1851735089
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1018149037
Short name T1621
Test name
Test status
Simulation time 154632046 ps
CPU time 0.77 seconds
Started Jul 02 09:06:50 AM PDT 24
Finished Jul 02 09:06:53 AM PDT 24
Peak memory 206184 kb
Host smart-a026cbff-dd93-49a7-8f91-a815e1a40148
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1018149037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1018149037
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1844351696
Short name T2458
Test name
Test status
Simulation time 139302069 ps
CPU time 0.81 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:06:45 AM PDT 24
Peak memory 206180 kb
Host smart-952562b2-72a9-4a59-8580-40ba6b017b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18443
51696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1844351696
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2185776693
Short name T2157
Test name
Test status
Simulation time 258575667 ps
CPU time 1.01 seconds
Started Jul 02 09:06:51 AM PDT 24
Finished Jul 02 09:06:54 AM PDT 24
Peak memory 206216 kb
Host smart-31128afc-b7a7-47c2-a886-5d07e89327c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21857
76693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2185776693
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.4284228909
Short name T720
Test name
Test status
Simulation time 200867209 ps
CPU time 0.97 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:06:45 AM PDT 24
Peak memory 206184 kb
Host smart-8758c6d3-0953-4159-a4b7-462da62438c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42842
28909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.4284228909
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.4261905750
Short name T2553
Test name
Test status
Simulation time 181939724 ps
CPU time 0.81 seconds
Started Jul 02 09:06:38 AM PDT 24
Finished Jul 02 09:06:40 AM PDT 24
Peak memory 206192 kb
Host smart-b330b9ae-e03d-4ae5-b180-36908583955b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42619
05750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.4261905750
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3483356808
Short name T346
Test name
Test status
Simulation time 171175732 ps
CPU time 0.81 seconds
Started Jul 02 09:06:49 AM PDT 24
Finished Jul 02 09:06:52 AM PDT 24
Peak memory 206196 kb
Host smart-d3e924fa-8688-41fe-9bb4-319e6c1f47dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34833
56808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3483356808
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2869872696
Short name T2113
Test name
Test status
Simulation time 150980389 ps
CPU time 0.78 seconds
Started Jul 02 09:06:36 AM PDT 24
Finished Jul 02 09:06:39 AM PDT 24
Peak memory 206216 kb
Host smart-2a0a4a7f-4be6-4cb0-bace-005e40163ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28698
72696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2869872696
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2414411366
Short name T2012
Test name
Test status
Simulation time 233489598 ps
CPU time 0.99 seconds
Started Jul 02 09:06:39 AM PDT 24
Finished Jul 02 09:06:41 AM PDT 24
Peak memory 206188 kb
Host smart-a8f9703c-7c24-4d01-a440-f6283ba52d69
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2414411366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2414411366
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.751122248
Short name T1125
Test name
Test status
Simulation time 200281557 ps
CPU time 0.9 seconds
Started Jul 02 09:06:48 AM PDT 24
Finished Jul 02 09:06:51 AM PDT 24
Peak memory 206196 kb
Host smart-2290eaa4-bb1f-42ee-90f1-7395b1c8631f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75112
2248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.751122248
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.737392880
Short name T411
Test name
Test status
Simulation time 161869982 ps
CPU time 0.78 seconds
Started Jul 02 09:06:42 AM PDT 24
Finished Jul 02 09:06:44 AM PDT 24
Peak memory 206172 kb
Host smart-e97a32c3-94e6-476b-922b-5b5b20ede09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73739
2880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.737392880
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3075882995
Short name T2156
Test name
Test status
Simulation time 41280543 ps
CPU time 0.67 seconds
Started Jul 02 09:06:42 AM PDT 24
Finished Jul 02 09:06:44 AM PDT 24
Peak memory 206200 kb
Host smart-0fd858ce-31ed-41cf-b8e6-983fe287577e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30758
82995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3075882995
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1569614590
Short name T648
Test name
Test status
Simulation time 13150228185 ps
CPU time 28.26 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:07:13 AM PDT 24
Peak memory 206504 kb
Host smart-64f60bdf-8352-4e5e-a619-86369ecc3215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15696
14590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1569614590
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.106904197
Short name T516
Test name
Test status
Simulation time 184961808 ps
CPU time 0.85 seconds
Started Jul 02 09:06:54 AM PDT 24
Finished Jul 02 09:06:57 AM PDT 24
Peak memory 206192 kb
Host smart-c703e4c6-9c76-4cca-95b7-83d9122b47f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10690
4197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.106904197
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.991131834
Short name T1863
Test name
Test status
Simulation time 211000870 ps
CPU time 0.9 seconds
Started Jul 02 09:06:53 AM PDT 24
Finished Jul 02 09:06:55 AM PDT 24
Peak memory 206216 kb
Host smart-9c82390f-5016-4f5b-b8bd-bf967e7a8b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99113
1834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.991131834
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.4222458751
Short name T2076
Test name
Test status
Simulation time 8571439454 ps
CPU time 45.42 seconds
Started Jul 02 09:06:46 AM PDT 24
Finished Jul 02 09:07:34 AM PDT 24
Peak memory 206464 kb
Host smart-0639315d-6ec1-4a5a-b87f-0829fbb18a12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4222458751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.4222458751
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.888885155
Short name T632
Test name
Test status
Simulation time 7471749318 ps
CPU time 46.56 seconds
Started Jul 02 09:06:41 AM PDT 24
Finished Jul 02 09:07:28 AM PDT 24
Peak memory 206660 kb
Host smart-4d8aeddb-1f81-42cc-aa4e-870a0a73c8f3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=888885155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.888885155
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2489701242
Short name T2261
Test name
Test status
Simulation time 13034280389 ps
CPU time 71.79 seconds
Started Jul 02 09:06:51 AM PDT 24
Finished Jul 02 09:08:04 AM PDT 24
Peak memory 206480 kb
Host smart-ae75ae8a-1aa1-415d-9bc4-55953547dc26
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2489701242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2489701242
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1950471144
Short name T1182
Test name
Test status
Simulation time 213793688 ps
CPU time 0.88 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:06:48 AM PDT 24
Peak memory 206168 kb
Host smart-19e0eca9-75e0-4e36-9ec7-54a3d384d8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19504
71144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1950471144
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3162955575
Short name T408
Test name
Test status
Simulation time 156309124 ps
CPU time 0.8 seconds
Started Jul 02 09:06:53 AM PDT 24
Finished Jul 02 09:06:56 AM PDT 24
Peak memory 206216 kb
Host smart-284b86e2-844b-4735-a4da-6223b3889a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31629
55575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3162955575
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.878989077
Short name T333
Test name
Test status
Simulation time 182994708 ps
CPU time 0.83 seconds
Started Jul 02 09:06:52 AM PDT 24
Finished Jul 02 09:06:55 AM PDT 24
Peak memory 206204 kb
Host smart-30b909f4-df4d-4b72-8655-e56f05e69317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87898
9077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.878989077
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.4108983847
Short name T76
Test name
Test status
Simulation time 239855825 ps
CPU time 0.9 seconds
Started Jul 02 09:06:54 AM PDT 24
Finished Jul 02 09:06:57 AM PDT 24
Peak memory 206176 kb
Host smart-df9beca2-63ca-4652-ab85-039e1f389495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089
83847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.4108983847
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.858991210
Short name T59
Test name
Test status
Simulation time 453420757 ps
CPU time 1.36 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:06:45 AM PDT 24
Peak memory 206176 kb
Host smart-effa4684-a260-4c6d-9216-3d311d8be658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85899
1210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.858991210
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2924438760
Short name T33
Test name
Test status
Simulation time 207643970 ps
CPU time 0.9 seconds
Started Jul 02 09:06:54 AM PDT 24
Finished Jul 02 09:06:57 AM PDT 24
Peak memory 206212 kb
Host smart-980cc920-c5df-426e-be3b-0cb6e327af97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29244
38760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2924438760
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3806677102
Short name T1965
Test name
Test status
Simulation time 148733720 ps
CPU time 0.75 seconds
Started Jul 02 09:06:52 AM PDT 24
Finished Jul 02 09:06:54 AM PDT 24
Peak memory 206184 kb
Host smart-46dbd2b9-8154-4c00-946b-65919af98b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38066
77102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3806677102
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.4248078833
Short name T340
Test name
Test status
Simulation time 161642993 ps
CPU time 0.78 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:06:50 AM PDT 24
Peak memory 206176 kb
Host smart-60e3777c-e605-4eb0-b872-1f5fa99ac02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42480
78833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.4248078833
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1157026326
Short name T569
Test name
Test status
Simulation time 216845228 ps
CPU time 0.9 seconds
Started Jul 02 09:06:42 AM PDT 24
Finished Jul 02 09:06:44 AM PDT 24
Peak memory 206200 kb
Host smart-32e460c5-ed01-4697-bc01-6385b4e9e6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11570
26326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1157026326
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.448456165
Short name T934
Test name
Test status
Simulation time 5146395983 ps
CPU time 51.55 seconds
Started Jul 02 09:06:53 AM PDT 24
Finished Jul 02 09:07:47 AM PDT 24
Peak memory 206408 kb
Host smart-b862541f-2b84-43b9-8dd6-1d9f53fbfd71
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=448456165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.448456165
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.328140342
Short name T783
Test name
Test status
Simulation time 168754083 ps
CPU time 0.81 seconds
Started Jul 02 09:06:46 AM PDT 24
Finished Jul 02 09:06:49 AM PDT 24
Peak memory 206216 kb
Host smart-ef0ce0a7-14da-46ba-a014-82b0a5011db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32814
0342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.328140342
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3912992404
Short name T407
Test name
Test status
Simulation time 188252701 ps
CPU time 0.86 seconds
Started Jul 02 09:06:44 AM PDT 24
Finished Jul 02 09:06:46 AM PDT 24
Peak memory 206184 kb
Host smart-ceff5fa8-e849-4b15-ab6a-53f5be1e9e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39129
92404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3912992404
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.3415561686
Short name T2106
Test name
Test status
Simulation time 441908804 ps
CPU time 1.49 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:06:48 AM PDT 24
Peak memory 206168 kb
Host smart-96b2633c-2966-46cc-bff3-9840f2a48f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34155
61686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.3415561686
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.2846077791
Short name T1772
Test name
Test status
Simulation time 3901016676 ps
CPU time 36.05 seconds
Started Jul 02 09:06:51 AM PDT 24
Finished Jul 02 09:07:29 AM PDT 24
Peak memory 206532 kb
Host smart-9d535eef-a896-4108-8fc8-116260ff772a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28460
77791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2846077791
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.650733572
Short name T206
Test name
Test status
Simulation time 96226542 ps
CPU time 0.76 seconds
Started Jul 02 09:12:07 AM PDT 24
Finished Jul 02 09:12:09 AM PDT 24
Peak memory 206252 kb
Host smart-941948e5-21d2-45f9-8977-69f8fde722ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=650733572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.650733572
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1433797090
Short name T15
Test name
Test status
Simulation time 3924512616 ps
CPU time 4.96 seconds
Started Jul 02 09:12:08 AM PDT 24
Finished Jul 02 09:12:15 AM PDT 24
Peak memory 206244 kb
Host smart-81d45370-1366-42b1-8249-827531519a25
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1433797090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1433797090
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2765955312
Short name T2392
Test name
Test status
Simulation time 13378710353 ps
CPU time 12.06 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:12:19 AM PDT 24
Peak memory 206448 kb
Host smart-83558a9f-aeed-47ff-a687-1a4acc6b7d69
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2765955312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2765955312
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2701265363
Short name T2387
Test name
Test status
Simulation time 23333383906 ps
CPU time 24.57 seconds
Started Jul 02 09:12:00 AM PDT 24
Finished Jul 02 09:12:25 AM PDT 24
Peak memory 206372 kb
Host smart-9cf9aaf6-2ca1-457f-a610-7d28b3da2005
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2701265363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.2701265363
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1487418287
Short name T1978
Test name
Test status
Simulation time 156932128 ps
CPU time 0.86 seconds
Started Jul 02 09:12:08 AM PDT 24
Finished Jul 02 09:12:10 AM PDT 24
Peak memory 206168 kb
Host smart-6f8c4f62-1cd4-4b95-8a96-72d3cc8a8530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14874
18287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1487418287
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.874042723
Short name T1187
Test name
Test status
Simulation time 189475703 ps
CPU time 0.82 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:12:08 AM PDT 24
Peak memory 206168 kb
Host smart-fadd7801-849b-40a8-8434-94f32361157b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87404
2723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.874042723
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.203581517
Short name T1572
Test name
Test status
Simulation time 483076030 ps
CPU time 1.37 seconds
Started Jul 02 09:12:08 AM PDT 24
Finished Jul 02 09:12:11 AM PDT 24
Peak memory 206196 kb
Host smart-42d1b4f1-8ddf-45e7-81a2-867833ca35e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20358
1517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.203581517
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.1406697232
Short name T2683
Test name
Test status
Simulation time 888232940 ps
CPU time 2.26 seconds
Started Jul 02 09:12:07 AM PDT 24
Finished Jul 02 09:12:11 AM PDT 24
Peak memory 206436 kb
Host smart-c18ff4bd-e6b8-42e0-9772-777d2691e4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14066
97232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.1406697232
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1454624973
Short name T1005
Test name
Test status
Simulation time 16841754200 ps
CPU time 33.93 seconds
Started Jul 02 09:12:09 AM PDT 24
Finished Jul 02 09:12:45 AM PDT 24
Peak memory 206444 kb
Host smart-d04c0a47-c814-4b41-a830-58eceaf64ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14546
24973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1454624973
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2739706710
Short name T1481
Test name
Test status
Simulation time 296893493 ps
CPU time 1.08 seconds
Started Jul 02 09:11:58 AM PDT 24
Finished Jul 02 09:12:00 AM PDT 24
Peak memory 206216 kb
Host smart-6723db9f-908f-40f2-b9e7-10b7a209f454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27397
06710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2739706710
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.981773986
Short name T1919
Test name
Test status
Simulation time 166892141 ps
CPU time 0.76 seconds
Started Jul 02 09:12:07 AM PDT 24
Finished Jul 02 09:12:09 AM PDT 24
Peak memory 206144 kb
Host smart-d9d01dea-584f-4471-8917-9a4a28a5b06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98177
3986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.981773986
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.4204480291
Short name T273
Test name
Test status
Simulation time 70359576 ps
CPU time 0.68 seconds
Started Jul 02 09:12:07 AM PDT 24
Finished Jul 02 09:12:09 AM PDT 24
Peak memory 206140 kb
Host smart-b54c0f89-724e-4437-b8be-0942f0c4122e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42044
80291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.4204480291
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.1667332502
Short name T1728
Test name
Test status
Simulation time 681092212 ps
CPU time 1.81 seconds
Started Jul 02 09:12:03 AM PDT 24
Finished Jul 02 09:12:06 AM PDT 24
Peak memory 206436 kb
Host smart-7f55e8ee-259a-49a5-afe3-e29e7e7dabc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16673
32502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.1667332502
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1401157204
Short name T2008
Test name
Test status
Simulation time 246540206 ps
CPU time 1.58 seconds
Started Jul 02 09:12:04 AM PDT 24
Finished Jul 02 09:12:07 AM PDT 24
Peak memory 206360 kb
Host smart-9789aa0c-fdb0-41e4-84b0-ec59f3effd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14011
57204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1401157204
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.594966741
Short name T2633
Test name
Test status
Simulation time 212032008 ps
CPU time 0.88 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:12:04 AM PDT 24
Peak memory 206208 kb
Host smart-8e293495-ed54-4cef-bb76-0f6e97cfcbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59496
6741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.594966741
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1370746950
Short name T1413
Test name
Test status
Simulation time 143364880 ps
CPU time 0.81 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:12:03 AM PDT 24
Peak memory 206124 kb
Host smart-cbeb6eed-d418-4884-bf0b-36f034edce91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13707
46950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1370746950
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.4197312299
Short name T2468
Test name
Test status
Simulation time 168610881 ps
CPU time 0.87 seconds
Started Jul 02 09:11:59 AM PDT 24
Finished Jul 02 09:12:01 AM PDT 24
Peak memory 206140 kb
Host smart-4ddedb4e-2d02-4c84-a0a8-73b9ccac4f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41973
12299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.4197312299
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1470935788
Short name T1602
Test name
Test status
Simulation time 183638648 ps
CPU time 0.84 seconds
Started Jul 02 09:12:10 AM PDT 24
Finished Jul 02 09:12:12 AM PDT 24
Peak memory 206124 kb
Host smart-4cd4b8a3-c29b-4a86-bbfb-e341284b7304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14709
35788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1470935788
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.2630348574
Short name T882
Test name
Test status
Simulation time 23333822097 ps
CPU time 24.45 seconds
Started Jul 02 09:11:57 AM PDT 24
Finished Jul 02 09:12:22 AM PDT 24
Peak memory 206272 kb
Host smart-ad26636a-8157-4d7a-b08f-82237f26569e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26303
48574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.2630348574
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.284555175
Short name T1368
Test name
Test status
Simulation time 3326902972 ps
CPU time 3.5 seconds
Started Jul 02 09:12:00 AM PDT 24
Finished Jul 02 09:12:04 AM PDT 24
Peak memory 206256 kb
Host smart-f31ffb1d-78c6-4e8c-956b-66e0d7901867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28455
5175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.284555175
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1252108903
Short name T2374
Test name
Test status
Simulation time 10596436748 ps
CPU time 95.26 seconds
Started Jul 02 09:12:09 AM PDT 24
Finished Jul 02 09:13:46 AM PDT 24
Peak memory 206516 kb
Host smart-dedb4d40-60f0-44ed-9c8b-fbca83249e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12521
08903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1252108903
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1360065851
Short name T1344
Test name
Test status
Simulation time 7850403053 ps
CPU time 78.76 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:13:39 AM PDT 24
Peak memory 206448 kb
Host smart-5ff28eb5-dda6-47f0-bc08-ed3e75a6fdf1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1360065851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1360065851
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.1882953023
Short name T468
Test name
Test status
Simulation time 246115342 ps
CPU time 0.92 seconds
Started Jul 02 09:12:07 AM PDT 24
Finished Jul 02 09:12:09 AM PDT 24
Peak memory 206200 kb
Host smart-49276ae8-a190-4da5-9a23-34e68dc3d572
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1882953023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.1882953023
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2795733674
Short name T528
Test name
Test status
Simulation time 190699375 ps
CPU time 0.87 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:12:03 AM PDT 24
Peak memory 206132 kb
Host smart-da489c15-cc1f-4c55-9b7b-991d8ceca6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27957
33674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2795733674
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.2773397690
Short name T2187
Test name
Test status
Simulation time 6107875934 ps
CPU time 44.73 seconds
Started Jul 02 09:11:59 AM PDT 24
Finished Jul 02 09:12:45 AM PDT 24
Peak memory 206472 kb
Host smart-aa9a353b-53dc-4326-b989-79c27c12efdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27733
97690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.2773397690
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.377359184
Short name T667
Test name
Test status
Simulation time 5666286013 ps
CPU time 154.62 seconds
Started Jul 02 09:11:57 AM PDT 24
Finished Jul 02 09:14:33 AM PDT 24
Peak memory 206448 kb
Host smart-26b18025-5314-4568-984f-19f3da7a7380
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=377359184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.377359184
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.425389358
Short name T2091
Test name
Test status
Simulation time 162140483 ps
CPU time 0.83 seconds
Started Jul 02 09:12:04 AM PDT 24
Finished Jul 02 09:12:06 AM PDT 24
Peak memory 206188 kb
Host smart-d7c4c32a-8ae6-436c-ae47-f868430523d5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=425389358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.425389358
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.4172312621
Short name T1076
Test name
Test status
Simulation time 144688860 ps
CPU time 0.8 seconds
Started Jul 02 09:12:09 AM PDT 24
Finished Jul 02 09:12:11 AM PDT 24
Peak memory 206228 kb
Host smart-04a0a03a-59d7-4786-bd54-40098a74110e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41723
12621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.4172312621
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2634489391
Short name T124
Test name
Test status
Simulation time 181793933 ps
CPU time 0.8 seconds
Started Jul 02 09:12:10 AM PDT 24
Finished Jul 02 09:12:13 AM PDT 24
Peak memory 206204 kb
Host smart-143524f9-02e9-4d29-bbbe-5e939b7f8806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26344
89391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2634489391
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1052609814
Short name T391
Test name
Test status
Simulation time 174978182 ps
CPU time 0.83 seconds
Started Jul 02 09:12:09 AM PDT 24
Finished Jul 02 09:12:11 AM PDT 24
Peak memory 206212 kb
Host smart-726cf59a-9011-429a-99bb-0eb42408a9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526
09814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1052609814
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2582727086
Short name T1189
Test name
Test status
Simulation time 213299186 ps
CPU time 0.83 seconds
Started Jul 02 09:12:09 AM PDT 24
Finished Jul 02 09:12:12 AM PDT 24
Peak memory 206128 kb
Host smart-008d3ea9-70bb-41d2-9bc4-047129aab315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25827
27086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2582727086
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.765576975
Short name T739
Test name
Test status
Simulation time 169558384 ps
CPU time 0.77 seconds
Started Jul 02 09:12:04 AM PDT 24
Finished Jul 02 09:12:06 AM PDT 24
Peak memory 206188 kb
Host smart-caa6d756-ebe0-449c-a311-c161f535b639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76557
6975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.765576975
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2246882151
Short name T2677
Test name
Test status
Simulation time 167593613 ps
CPU time 0.83 seconds
Started Jul 02 09:12:12 AM PDT 24
Finished Jul 02 09:12:15 AM PDT 24
Peak memory 206124 kb
Host smart-b47f38d3-6137-4ea7-b156-f708ab8ece79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22468
82151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2246882151
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.2131549442
Short name T2295
Test name
Test status
Simulation time 242047674 ps
CPU time 0.91 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:16 AM PDT 24
Peak memory 206168 kb
Host smart-13fe0e47-9c74-4b51-a01b-9bf183506576
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2131549442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.2131549442
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.903081565
Short name T1357
Test name
Test status
Simulation time 154638662 ps
CPU time 0.8 seconds
Started Jul 02 09:12:10 AM PDT 24
Finished Jul 02 09:12:12 AM PDT 24
Peak memory 206136 kb
Host smart-d8cc2e72-a9f0-4ceb-b175-4415e5687979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90308
1565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.903081565
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.4172494480
Short name T1560
Test name
Test status
Simulation time 41670710 ps
CPU time 0.68 seconds
Started Jul 02 09:12:02 AM PDT 24
Finished Jul 02 09:12:04 AM PDT 24
Peak memory 206188 kb
Host smart-c7ee5d22-ae03-4e03-882d-e60cf106e713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41724
94480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.4172494480
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2295404024
Short name T2161
Test name
Test status
Simulation time 19276315170 ps
CPU time 46.69 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:13:08 AM PDT 24
Peak memory 214632 kb
Host smart-3983b105-e184-4fe5-b5e1-ac3941e3858f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22954
04024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2295404024
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.4131421467
Short name T1553
Test name
Test status
Simulation time 147960520 ps
CPU time 0.78 seconds
Started Jul 02 09:12:05 AM PDT 24
Finished Jul 02 09:12:06 AM PDT 24
Peak memory 206196 kb
Host smart-413da96b-41ed-444a-af6b-1db79a8cd4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41314
21467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.4131421467
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.141061737
Short name T2334
Test name
Test status
Simulation time 178067447 ps
CPU time 0.84 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:16 AM PDT 24
Peak memory 206204 kb
Host smart-23f5ca8f-485e-42a8-a0b5-515bba33b289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14106
1737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.141061737
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.492433633
Short name T2674
Test name
Test status
Simulation time 217612934 ps
CPU time 0.81 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:12:08 AM PDT 24
Peak memory 206128 kb
Host smart-8a0742b4-5f6e-4a54-bae2-634d5cf10f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49243
3633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.492433633
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.2345755966
Short name T967
Test name
Test status
Simulation time 239870494 ps
CPU time 0.85 seconds
Started Jul 02 09:12:10 AM PDT 24
Finished Jul 02 09:12:13 AM PDT 24
Peak memory 206144 kb
Host smart-d3b5586f-5715-400a-8020-3883533bfede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23457
55966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.2345755966
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1957427974
Short name T73
Test name
Test status
Simulation time 174127064 ps
CPU time 0.77 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:12:07 AM PDT 24
Peak memory 206056 kb
Host smart-477834ec-bfa0-4dd9-aeb8-d5394b24e76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19574
27974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1957427974
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2893569096
Short name T2276
Test name
Test status
Simulation time 162651994 ps
CPU time 0.78 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:22 AM PDT 24
Peak memory 206020 kb
Host smart-10f3425a-c94d-4c1c-ae0d-694ad104fdcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28935
69096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2893569096
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.4015064084
Short name T2047
Test name
Test status
Simulation time 153103022 ps
CPU time 0.78 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:12:08 AM PDT 24
Peak memory 206164 kb
Host smart-3f648b9d-ae74-4672-a6a8-49f80a912bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40150
64084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4015064084
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3358774248
Short name T1018
Test name
Test status
Simulation time 222969949 ps
CPU time 0.94 seconds
Started Jul 02 09:12:03 AM PDT 24
Finished Jul 02 09:12:05 AM PDT 24
Peak memory 206200 kb
Host smart-95a0a93a-f7e6-4573-8682-d0882b4f0b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33587
74248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3358774248
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.3115952103
Short name T2158
Test name
Test status
Simulation time 3877656406 ps
CPU time 107.41 seconds
Started Jul 02 09:12:10 AM PDT 24
Finished Jul 02 09:13:59 AM PDT 24
Peak memory 206436 kb
Host smart-395e81a8-7219-448d-b516-f16268391d34
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3115952103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3115952103
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2127519837
Short name T1901
Test name
Test status
Simulation time 218128726 ps
CPU time 0.82 seconds
Started Jul 02 09:12:04 AM PDT 24
Finished Jul 02 09:12:06 AM PDT 24
Peak memory 206228 kb
Host smart-35c6857e-4a34-40a4-8d06-aafd9b989807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21275
19837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2127519837
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.798110736
Short name T671
Test name
Test status
Simulation time 197945650 ps
CPU time 0.9 seconds
Started Jul 02 09:12:04 AM PDT 24
Finished Jul 02 09:12:06 AM PDT 24
Peak memory 206184 kb
Host smart-64c56dce-afc6-4f9e-82dc-8074dade6a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79811
0736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.798110736
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.3866400558
Short name T606
Test name
Test status
Simulation time 982733110 ps
CPU time 2.26 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:17 AM PDT 24
Peak memory 206384 kb
Host smart-49a257ae-d7ee-4dc4-a7f8-80e0b90a6cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38664
00558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3866400558
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.380859913
Short name T680
Test name
Test status
Simulation time 5068330335 ps
CPU time 151.11 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:14:34 AM PDT 24
Peak memory 206496 kb
Host smart-3cba5137-6215-4335-8313-14991e0df648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38085
9913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.380859913
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.4233907634
Short name T1627
Test name
Test status
Simulation time 48992923 ps
CPU time 0.67 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:23 AM PDT 24
Peak memory 206160 kb
Host smart-35dc2aae-75b6-4538-801f-3800bba223eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4233907634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.4233907634
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2936158075
Short name T2360
Test name
Test status
Simulation time 4260676301 ps
CPU time 5.77 seconds
Started Jul 02 09:12:04 AM PDT 24
Finished Jul 02 09:12:11 AM PDT 24
Peak memory 206252 kb
Host smart-5bb18ab5-ac66-4d43-9fc5-c99ffe0bb65f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2936158075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.2936158075
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3057528763
Short name T904
Test name
Test status
Simulation time 13367612520 ps
CPU time 12.27 seconds
Started Jul 02 09:12:10 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206172 kb
Host smart-7f46d676-e386-43dc-ace7-31c649fe89ea
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3057528763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3057528763
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.811005280
Short name T828
Test name
Test status
Simulation time 23393474856 ps
CPU time 27.59 seconds
Started Jul 02 09:12:02 AM PDT 24
Finished Jul 02 09:12:31 AM PDT 24
Peak memory 206240 kb
Host smart-dcbb6b96-f439-4b95-b95f-92fdcaaa5326
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=811005280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.811005280
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.801720103
Short name T567
Test name
Test status
Simulation time 154433742 ps
CPU time 0.81 seconds
Started Jul 02 09:12:03 AM PDT 24
Finished Jul 02 09:12:05 AM PDT 24
Peak memory 206200 kb
Host smart-099a6108-77dd-4774-8e3b-60a2f8877452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80172
0103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.801720103
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1954284686
Short name T599
Test name
Test status
Simulation time 161250256 ps
CPU time 0.74 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:12:03 AM PDT 24
Peak memory 206192 kb
Host smart-538ddc01-f0ea-44ca-8de2-aaec924d4eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19542
84686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1954284686
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.413570690
Short name T2183
Test name
Test status
Simulation time 302099520 ps
CPU time 1.09 seconds
Started Jul 02 09:12:03 AM PDT 24
Finished Jul 02 09:12:06 AM PDT 24
Peak memory 206204 kb
Host smart-73ec20a1-c60d-43d5-b477-2d569fa4785a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
0690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.413570690
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.390412397
Short name T183
Test name
Test status
Simulation time 1425629515 ps
CPU time 3.54 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:12:10 AM PDT 24
Peak memory 206216 kb
Host smart-04426b2f-edfb-4fb3-a19f-c10d12aeb0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39041
2397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.390412397
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1863588567
Short name T1077
Test name
Test status
Simulation time 22796700434 ps
CPU time 53.34 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:13:00 AM PDT 24
Peak memory 206340 kb
Host smart-53456fa5-e4cc-41da-9487-c99e112286da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18635
88567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1863588567
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.1743238358
Short name T535
Test name
Test status
Simulation time 492952196 ps
CPU time 1.54 seconds
Started Jul 02 09:12:09 AM PDT 24
Finished Jul 02 09:12:13 AM PDT 24
Peak memory 206184 kb
Host smart-e0e37ea7-61f6-4bcd-ba6f-b1a25f9dfcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17432
38358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.1743238358
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.330765355
Short name T2514
Test name
Test status
Simulation time 159490849 ps
CPU time 0.8 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:21 AM PDT 24
Peak memory 206228 kb
Host smart-fefbdb22-2248-41a8-b198-df81c959c4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33076
5355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.330765355
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.1392573981
Short name T3
Test name
Test status
Simulation time 43943455 ps
CPU time 0.64 seconds
Started Jul 02 09:12:12 AM PDT 24
Finished Jul 02 09:12:15 AM PDT 24
Peak memory 206212 kb
Host smart-14b7b9dc-9ed0-4257-a9f6-8908a32e1678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13925
73981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1392573981
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.256714622
Short name T1725
Test name
Test status
Simulation time 869660055 ps
CPU time 2.18 seconds
Started Jul 02 09:12:01 AM PDT 24
Finished Jul 02 09:12:04 AM PDT 24
Peak memory 206368 kb
Host smart-28a1a7e1-2af0-4686-bf26-8ed7f0db2a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25671
4622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.256714622
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.757809567
Short name T613
Test name
Test status
Simulation time 268721676 ps
CPU time 1.56 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:12:09 AM PDT 24
Peak memory 206396 kb
Host smart-de65bf90-d835-4ab2-87c5-0c24903dcab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75780
9567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.757809567
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1061374319
Short name T350
Test name
Test status
Simulation time 164247894 ps
CPU time 0.85 seconds
Started Jul 02 09:12:06 AM PDT 24
Finished Jul 02 09:12:08 AM PDT 24
Peak memory 206220 kb
Host smart-aa5f75d7-dff2-4e2b-8709-2139b260a685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10613
74319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1061374319
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1814966559
Short name T558
Test name
Test status
Simulation time 214179561 ps
CPU time 0.79 seconds
Started Jul 02 09:12:04 AM PDT 24
Finished Jul 02 09:12:06 AM PDT 24
Peak memory 206152 kb
Host smart-21accdd2-cec0-4149-8405-1d44931003b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18149
66559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1814966559
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3433254720
Short name T1191
Test name
Test status
Simulation time 310617193 ps
CPU time 0.99 seconds
Started Jul 02 09:12:10 AM PDT 24
Finished Jul 02 09:12:13 AM PDT 24
Peak memory 206124 kb
Host smart-4f7c5847-e853-4aa5-bb3c-4ea4a24d9c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34332
54720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3433254720
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.3112330544
Short name T1251
Test name
Test status
Simulation time 6513183456 ps
CPU time 59.99 seconds
Started Jul 02 09:12:18 AM PDT 24
Finished Jul 02 09:13:25 AM PDT 24
Peak memory 206516 kb
Host smart-0aa0e89c-c200-46a4-870f-258d80c2f6ef
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3112330544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.3112330544
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.763116372
Short name T874
Test name
Test status
Simulation time 172675784 ps
CPU time 0.83 seconds
Started Jul 02 09:12:08 AM PDT 24
Finished Jul 02 09:12:11 AM PDT 24
Peak memory 206208 kb
Host smart-14553a33-7962-4f34-babb-d345983e83c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76311
6372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.763116372
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3858366348
Short name T654
Test name
Test status
Simulation time 23315346562 ps
CPU time 22.1 seconds
Started Jul 02 09:12:08 AM PDT 24
Finished Jul 02 09:12:31 AM PDT 24
Peak memory 206052 kb
Host smart-e67de2f5-d892-4af4-8ed0-a1cfadf775ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38583
66348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3858366348
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2394139091
Short name T738
Test name
Test status
Simulation time 3310317334 ps
CPU time 3.55 seconds
Started Jul 02 09:11:59 AM PDT 24
Finished Jul 02 09:12:04 AM PDT 24
Peak memory 206188 kb
Host smart-6dc39070-cb4a-4aac-9b7b-3567089134db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23941
39091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2394139091
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1674097874
Short name T2694
Test name
Test status
Simulation time 15852836910 ps
CPU time 447.94 seconds
Started Jul 02 09:12:09 AM PDT 24
Finished Jul 02 09:19:39 AM PDT 24
Peak memory 206524 kb
Host smart-4683e8f0-b420-4ec4-a6ce-a7a8c8439b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16740
97874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1674097874
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.87177841
Short name T1949
Test name
Test status
Simulation time 3850224111 ps
CPU time 35.31 seconds
Started Jul 02 09:12:11 AM PDT 24
Finished Jul 02 09:12:48 AM PDT 24
Peak memory 206484 kb
Host smart-9145da81-1886-4fc4-b0ef-faeb43a00fe2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=87177841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.87177841
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.2057971147
Short name T975
Test name
Test status
Simulation time 261036217 ps
CPU time 1.03 seconds
Started Jul 02 09:12:04 AM PDT 24
Finished Jul 02 09:12:06 AM PDT 24
Peak memory 206340 kb
Host smart-a31b95ea-5410-4b22-ac45-1c90f9e96de4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2057971147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.2057971147
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3874469358
Short name T359
Test name
Test status
Simulation time 226429235 ps
CPU time 0.92 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:17 AM PDT 24
Peak memory 206204 kb
Host smart-f1a749c0-466c-4ac3-afe3-98bdf111b917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38744
69358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3874469358
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.4222128640
Short name T1015
Test name
Test status
Simulation time 4517399895 ps
CPU time 44.9 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:13:00 AM PDT 24
Peak memory 206444 kb
Host smart-8579adff-9835-4383-b5cc-3cb2b8b50609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42221
28640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.4222128640
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.4069255526
Short name T1283
Test name
Test status
Simulation time 6336499981 ps
CPU time 65.76 seconds
Started Jul 02 09:12:00 AM PDT 24
Finished Jul 02 09:13:07 AM PDT 24
Peak memory 206452 kb
Host smart-9e405441-16ff-4f57-91fb-80ec4bb0dc13
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4069255526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.4069255526
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.3587399921
Short name T2217
Test name
Test status
Simulation time 161070537 ps
CPU time 0.81 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:16 AM PDT 24
Peak memory 206188 kb
Host smart-0157683f-2e53-4387-a2cc-10b6fdd92cd1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3587399921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3587399921
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3936390716
Short name T656
Test name
Test status
Simulation time 178758896 ps
CPU time 0.85 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:18 AM PDT 24
Peak memory 206200 kb
Host smart-619b1aa0-64f0-4eb1-9203-497ee761b1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39363
90716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3936390716
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.3551763248
Short name T1128
Test name
Test status
Simulation time 197508884 ps
CPU time 0.88 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:20 AM PDT 24
Peak memory 206080 kb
Host smart-abbe2c4a-2c6a-4542-b2d0-b5cff15fb49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35517
63248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.3551763248
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.572248344
Short name T2452
Test name
Test status
Simulation time 161786337 ps
CPU time 0.79 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206156 kb
Host smart-9b414c02-dc85-44c3-8db0-dcf7822f5951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57224
8344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.572248344
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2866938303
Short name T988
Test name
Test status
Simulation time 191486445 ps
CPU time 0.82 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:18 AM PDT 24
Peak memory 206176 kb
Host smart-5628fdb8-84b0-4fd5-90bc-64600b7b1a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28669
38303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2866938303
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2792373815
Short name T1443
Test name
Test status
Simulation time 188385887 ps
CPU time 0.84 seconds
Started Jul 02 09:12:05 AM PDT 24
Finished Jul 02 09:12:07 AM PDT 24
Peak memory 206212 kb
Host smart-9b9721ea-6f3f-4c4f-953b-28651cbee86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
73815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2792373815
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.1110496057
Short name T2302
Test name
Test status
Simulation time 241020124 ps
CPU time 0.95 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:16 AM PDT 24
Peak memory 206368 kb
Host smart-8236015c-50e8-457f-87a4-770d3d239395
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1110496057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.1110496057
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2293957703
Short name T1629
Test name
Test status
Simulation time 159918329 ps
CPU time 0.75 seconds
Started Jul 02 09:12:12 AM PDT 24
Finished Jul 02 09:12:15 AM PDT 24
Peak memory 206168 kb
Host smart-3f18e02d-8f8c-48e0-8a87-d4599b381361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22939
57703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2293957703
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3552149221
Short name T933
Test name
Test status
Simulation time 78500804 ps
CPU time 0.71 seconds
Started Jul 02 09:12:11 AM PDT 24
Finished Jul 02 09:12:13 AM PDT 24
Peak memory 206208 kb
Host smart-7a3aeb81-c7ca-4493-abe4-ad924151c333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35521
49221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3552149221
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.204952824
Short name T2656
Test name
Test status
Simulation time 9571842146 ps
CPU time 24.72 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:51 AM PDT 24
Peak memory 206548 kb
Host smart-eab22320-f270-42fe-aa3e-739a85160cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20495
2824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.204952824
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2458876163
Short name T1867
Test name
Test status
Simulation time 188764330 ps
CPU time 0.88 seconds
Started Jul 02 09:12:09 AM PDT 24
Finished Jul 02 09:12:12 AM PDT 24
Peak memory 206172 kb
Host smart-4e179974-ee09-4ecd-9906-78b5674f70d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24588
76163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2458876163
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3521803051
Short name T1408
Test name
Test status
Simulation time 249685053 ps
CPU time 0.84 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:16 AM PDT 24
Peak memory 206184 kb
Host smart-7cb0d474-8d03-4386-afa7-00f2e0cb0630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35218
03051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3521803051
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.2563290927
Short name T1656
Test name
Test status
Simulation time 203614287 ps
CPU time 0.83 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206196 kb
Host smart-d1361511-cba0-4cd6-8d11-6ffbee89e9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25632
90927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.2563290927
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.4190274959
Short name T2597
Test name
Test status
Simulation time 187605404 ps
CPU time 0.87 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:17 AM PDT 24
Peak memory 206144 kb
Host smart-36cf5e91-61a4-4f48-9044-45a1ce188d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41902
74959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.4190274959
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.4239879624
Short name T1519
Test name
Test status
Simulation time 141440445 ps
CPU time 0.74 seconds
Started Jul 02 09:12:11 AM PDT 24
Finished Jul 02 09:12:13 AM PDT 24
Peak memory 206216 kb
Host smart-288c3dc6-a8c2-4871-b775-df0086c70b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42398
79624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.4239879624
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3457121997
Short name T935
Test name
Test status
Simulation time 167260539 ps
CPU time 0.81 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:22 AM PDT 24
Peak memory 206116 kb
Host smart-3ce734a6-4f1a-49bb-a9fb-a87edb7c804f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34571
21997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3457121997
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3808531419
Short name T2695
Test name
Test status
Simulation time 153097023 ps
CPU time 0.79 seconds
Started Jul 02 09:12:12 AM PDT 24
Finished Jul 02 09:12:14 AM PDT 24
Peak memory 206212 kb
Host smart-868a0c0a-5afb-481e-98f0-ef00a102d007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38085
31419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3808531419
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.749611927
Short name T625
Test name
Test status
Simulation time 174587842 ps
CPU time 0.88 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:16 AM PDT 24
Peak memory 206388 kb
Host smart-148faf7a-6f69-46e7-91d9-7edbdad7144e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74961
1927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.749611927
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3820199368
Short name T2114
Test name
Test status
Simulation time 5662664637 ps
CPU time 156.44 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:14:52 AM PDT 24
Peak memory 206500 kb
Host smart-8f9fb9db-654c-41f1-a001-933540b92c13
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3820199368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3820199368
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1038198709
Short name T2660
Test name
Test status
Simulation time 208808207 ps
CPU time 0.86 seconds
Started Jul 02 09:12:09 AM PDT 24
Finished Jul 02 09:12:12 AM PDT 24
Peak memory 206180 kb
Host smart-a5c4fa02-e68c-4cde-a50a-671a7f9fa831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10381
98709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1038198709
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.720823028
Short name T729
Test name
Test status
Simulation time 174834603 ps
CPU time 0.88 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:17 AM PDT 24
Peak memory 206164 kb
Host smart-7d315085-2b6a-456c-a7e3-41a86f8dc52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72082
3028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.720823028
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.1098339983
Short name T1097
Test name
Test status
Simulation time 1082620710 ps
CPU time 2.26 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206572 kb
Host smart-2e2e695f-d926-438a-9560-9c213249979f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10983
39983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.1098339983
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.1138516336
Short name T689
Test name
Test status
Simulation time 6396935294 ps
CPU time 47.2 seconds
Started Jul 02 09:12:21 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206520 kb
Host smart-bfef2bd4-188f-415b-8393-ba50f9309ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11385
16336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.1138516336
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2812034930
Short name T2462
Test name
Test status
Simulation time 41346828 ps
CPU time 0.67 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:23 AM PDT 24
Peak memory 206220 kb
Host smart-3c1e79b2-45a4-4b62-9955-6b165384052d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2812034930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2812034930
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3328763334
Short name T2350
Test name
Test status
Simulation time 4387010165 ps
CPU time 5.22 seconds
Started Jul 02 09:12:10 AM PDT 24
Finished Jul 02 09:12:17 AM PDT 24
Peak memory 206468 kb
Host smart-61f5f844-1275-4d6e-aad6-df9e21ebd304
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3328763334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3328763334
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2051808707
Short name T1577
Test name
Test status
Simulation time 13374023400 ps
CPU time 12.98 seconds
Started Jul 02 09:12:08 AM PDT 24
Finished Jul 02 09:12:22 AM PDT 24
Peak memory 206120 kb
Host smart-57da6780-4541-43d8-ac0a-2234e346bc21
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2051808707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2051808707
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3188546701
Short name T685
Test name
Test status
Simulation time 23415860674 ps
CPU time 27.21 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:52 AM PDT 24
Peak memory 206432 kb
Host smart-bc21a34e-4848-4611-9707-3bdff3b55f5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3188546701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.3188546701
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3705257491
Short name T1638
Test name
Test status
Simulation time 184161665 ps
CPU time 0.86 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:21 AM PDT 24
Peak memory 206388 kb
Host smart-d2cbd82c-06e2-43b8-bd8a-d5e21e0589e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37052
57491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3705257491
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3220620396
Short name T2093
Test name
Test status
Simulation time 155883122 ps
CPU time 0.8 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:21 AM PDT 24
Peak memory 206212 kb
Host smart-fd0cad32-cb1a-4d8d-9310-2eb34af9bb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32206
20396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3220620396
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.164473365
Short name T168
Test name
Test status
Simulation time 399394744 ps
CPU time 1.27 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:23 AM PDT 24
Peak memory 206204 kb
Host smart-f901db97-4577-4ff4-a5b8-67861de60ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16447
3365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.164473365
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3473710707
Short name T2203
Test name
Test status
Simulation time 369836870 ps
CPU time 1.1 seconds
Started Jul 02 09:12:10 AM PDT 24
Finished Jul 02 09:12:13 AM PDT 24
Peak memory 206212 kb
Host smart-6771590d-9c0b-4bf4-913a-96eb91993df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34737
10707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3473710707
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.1205289330
Short name T965
Test name
Test status
Simulation time 15906876221 ps
CPU time 29.97 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:51 AM PDT 24
Peak memory 206436 kb
Host smart-bb2f5c7e-b883-438f-a3fd-2c3c33cbb262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12052
89330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1205289330
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.2669729718
Short name T436
Test name
Test status
Simulation time 474390108 ps
CPU time 1.27 seconds
Started Jul 02 09:12:12 AM PDT 24
Finished Jul 02 09:12:15 AM PDT 24
Peak memory 206180 kb
Host smart-fbd67289-03f7-41ab-a119-2a33f0b981e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26697
29718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.2669729718
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1998511806
Short name T1148
Test name
Test status
Simulation time 187442803 ps
CPU time 0.82 seconds
Started Jul 02 09:12:12 AM PDT 24
Finished Jul 02 09:12:14 AM PDT 24
Peak memory 206120 kb
Host smart-a6143628-51b8-41a7-8fa3-310b8dfe0cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19985
11806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1998511806
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1577607259
Short name T1690
Test name
Test status
Simulation time 46868857 ps
CPU time 0.64 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:21 AM PDT 24
Peak memory 206188 kb
Host smart-4d99404b-e624-4f47-94f7-388021a5159b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15776
07259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1577607259
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.4111395911
Short name T1504
Test name
Test status
Simulation time 919284077 ps
CPU time 2.39 seconds
Started Jul 02 09:12:11 AM PDT 24
Finished Jul 02 09:12:15 AM PDT 24
Peak memory 206392 kb
Host smart-f9d0b740-5601-4a15-b219-e405deded3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41113
95911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.4111395911
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.42906773
Short name T412
Test name
Test status
Simulation time 181517033 ps
CPU time 1.26 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:23 AM PDT 24
Peak memory 206328 kb
Host smart-e90c414c-f3b5-4c83-a993-287a28cf0302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42906
773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.42906773
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.4190386623
Short name T1615
Test name
Test status
Simulation time 264436369 ps
CPU time 0.92 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:22 AM PDT 24
Peak memory 206148 kb
Host smart-cc85b14e-5570-46d1-828e-dc689fcd483e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41903
86623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.4190386623
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1921328562
Short name T2567
Test name
Test status
Simulation time 160344236 ps
CPU time 0.77 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206192 kb
Host smart-c76ec0af-5ab9-4f19-be33-8f6c62f647eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19213
28562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1921328562
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1269855014
Short name T1366
Test name
Test status
Simulation time 187655283 ps
CPU time 0.85 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:25 AM PDT 24
Peak memory 206212 kb
Host smart-4505c751-dd6a-4a97-82fb-8e512a88dad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12698
55014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1269855014
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.4257595395
Short name T831
Test name
Test status
Simulation time 7604580751 ps
CPU time 59.35 seconds
Started Jul 02 09:12:12 AM PDT 24
Finished Jul 02 09:13:13 AM PDT 24
Peak memory 206448 kb
Host smart-3233bb99-eab6-4c18-9f10-d1e5eeeb353a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4257595395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.4257595395
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.447692398
Short name T2645
Test name
Test status
Simulation time 229963079 ps
CPU time 0.9 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206176 kb
Host smart-b31011ac-231b-423c-a454-214bfdff0fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44769
2398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.447692398
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.2632620618
Short name T2318
Test name
Test status
Simulation time 23329224735 ps
CPU time 24.53 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:39 AM PDT 24
Peak memory 206260 kb
Host smart-a1d5d7aa-d9c4-4d5a-b383-48a35a1f8ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26326
20618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2632620618
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.3129503592
Short name T364
Test name
Test status
Simulation time 3325205529 ps
CPU time 3.95 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:26 AM PDT 24
Peak memory 206232 kb
Host smart-6331e455-df1f-4d40-b4d8-87460e35c3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31295
03592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3129503592
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2502705750
Short name T1190
Test name
Test status
Simulation time 9339697607 ps
CPU time 88.14 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:13:53 AM PDT 24
Peak memory 206532 kb
Host smart-0a372a65-0b85-49b1-b7e9-66b725df9613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25027
05750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2502705750
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.2615777079
Short name T987
Test name
Test status
Simulation time 5417135053 ps
CPU time 54.47 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206472 kb
Host smart-6c50ddcc-d4fe-4568-a271-a6f4289e1378
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2615777079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.2615777079
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2003366126
Short name T640
Test name
Test status
Simulation time 253602716 ps
CPU time 0.96 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:19 AM PDT 24
Peak memory 206148 kb
Host smart-c11ec7bf-4e86-4799-90ea-3d26e0a34efc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2003366126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2003366126
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2921254154
Short name T596
Test name
Test status
Simulation time 194365409 ps
CPU time 0.92 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206228 kb
Host smart-78685e01-da04-4000-bf25-db16890a7fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29212
54154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2921254154
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1120659945
Short name T2485
Test name
Test status
Simulation time 4056320306 ps
CPU time 113.42 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:14:09 AM PDT 24
Peak memory 206428 kb
Host smart-46449f8a-67d1-4cde-a68b-40e32b63900d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11206
59945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1120659945
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3534103747
Short name T2370
Test name
Test status
Simulation time 4852523930 ps
CPU time 33.69 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:54 AM PDT 24
Peak memory 206444 kb
Host smart-667d0413-41b9-4a4b-accd-64ab6dfce796
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3534103747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3534103747
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.1927305513
Short name T1848
Test name
Test status
Simulation time 157202110 ps
CPU time 0.8 seconds
Started Jul 02 09:12:20 AM PDT 24
Finished Jul 02 09:12:28 AM PDT 24
Peak memory 206200 kb
Host smart-e02e87b5-1641-4a68-893c-945880745cf5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1927305513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.1927305513
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2371858
Short name T1259
Test name
Test status
Simulation time 158312887 ps
CPU time 0.75 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:27 AM PDT 24
Peak memory 206180 kb
Host smart-50b893e5-57ea-4368-bc2e-c76c037e3c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23718
58 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2371858
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1207309414
Short name T1530
Test name
Test status
Simulation time 189741700 ps
CPU time 0.86 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:17 AM PDT 24
Peak memory 206188 kb
Host smart-0194d2ad-ec5c-4f1d-be88-60b8b0162ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12073
09414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1207309414
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1734953732
Short name T1025
Test name
Test status
Simulation time 238621479 ps
CPU time 0.91 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:25 AM PDT 24
Peak memory 206216 kb
Host smart-68b1855c-a013-48c7-915f-308511bdb7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17349
53732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1734953732
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3027760305
Short name T1943
Test name
Test status
Simulation time 155354354 ps
CPU time 0.75 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:23 AM PDT 24
Peak memory 206196 kb
Host smart-be4fdbd4-7c0b-4f1a-a333-116749125a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30277
60305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3027760305
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2508366966
Short name T1006
Test name
Test status
Simulation time 192876774 ps
CPU time 0.85 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206140 kb
Host smart-907e5f48-9c3a-4185-af30-eab653ac7aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25083
66966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2508366966
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2193089096
Short name T1601
Test name
Test status
Simulation time 149470563 ps
CPU time 0.75 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206196 kb
Host smart-6e1ee36e-501f-44c9-825b-01c1c30bffc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21930
89096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2193089096
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.1481687886
Short name T1698
Test name
Test status
Simulation time 242805955 ps
CPU time 1.01 seconds
Started Jul 02 09:12:12 AM PDT 24
Finished Jul 02 09:12:14 AM PDT 24
Peak memory 206140 kb
Host smart-8e933f6f-6adc-4821-918e-c1cc391e1ab5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1481687886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.1481687886
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.335895195
Short name T2152
Test name
Test status
Simulation time 153711627 ps
CPU time 0.8 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206192 kb
Host smart-cd126003-7816-4498-bab2-c2e50c769c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33589
5195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.335895195
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2738746034
Short name T1424
Test name
Test status
Simulation time 62862089 ps
CPU time 0.68 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:20 AM PDT 24
Peak memory 206192 kb
Host smart-cf8061a5-2423-427e-a756-5e3fd229f900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27387
46034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2738746034
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2027799150
Short name T2263
Test name
Test status
Simulation time 10771390925 ps
CPU time 26.78 seconds
Started Jul 02 09:12:18 AM PDT 24
Finished Jul 02 09:12:52 AM PDT 24
Peak memory 206448 kb
Host smart-6d9cc632-de2a-480e-9cd3-b997dba4248e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20277
99150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2027799150
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.920212377
Short name T1325
Test name
Test status
Simulation time 176813834 ps
CPU time 0.81 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:19 AM PDT 24
Peak memory 206224 kb
Host smart-79f99fd9-141f-4290-beb2-656f60c23c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92021
2377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.920212377
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.151667935
Short name T1266
Test name
Test status
Simulation time 161962011 ps
CPU time 0.82 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:18 AM PDT 24
Peak memory 206196 kb
Host smart-62a50faa-baae-4126-b28b-8f166872a530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15166
7935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.151667935
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.1525362119
Short name T602
Test name
Test status
Simulation time 215819295 ps
CPU time 0.87 seconds
Started Jul 02 09:12:20 AM PDT 24
Finished Jul 02 09:12:28 AM PDT 24
Peak memory 206212 kb
Host smart-da3395fe-f4ef-4198-ba71-1dfe1b66da02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15253
62119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.1525362119
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.842963199
Short name T521
Test name
Test status
Simulation time 168305939 ps
CPU time 0.86 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:19 AM PDT 24
Peak memory 206224 kb
Host smart-d6877030-4ad1-48f4-81e4-146d8374b395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84296
3199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.842963199
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1010433696
Short name T766
Test name
Test status
Simulation time 148863357 ps
CPU time 0.83 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:19 AM PDT 24
Peak memory 206180 kb
Host smart-c586fe00-d907-4f2c-a5dd-17a27b119517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10104
33696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1010433696
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2547591572
Short name T1721
Test name
Test status
Simulation time 188229626 ps
CPU time 0.79 seconds
Started Jul 02 09:12:12 AM PDT 24
Finished Jul 02 09:12:15 AM PDT 24
Peak memory 206184 kb
Host smart-6c808c82-026f-4f45-96c0-506a8b42d892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25475
91572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2547591572
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3378442088
Short name T1667
Test name
Test status
Simulation time 151071779 ps
CPU time 0.74 seconds
Started Jul 02 09:12:18 AM PDT 24
Finished Jul 02 09:12:27 AM PDT 24
Peak memory 206180 kb
Host smart-5fa2ae20-ca32-4220-8d07-097715f47960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33784
42088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3378442088
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2392771080
Short name T162
Test name
Test status
Simulation time 268150333 ps
CPU time 0.91 seconds
Started Jul 02 09:12:18 AM PDT 24
Finished Jul 02 09:12:26 AM PDT 24
Peak memory 206156 kb
Host smart-72af2fbd-c5b8-42a8-910b-4f9df3acc478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23927
71080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2392771080
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.4168502940
Short name T482
Test name
Test status
Simulation time 4835671386 ps
CPU time 32.02 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:55 AM PDT 24
Peak memory 206420 kb
Host smart-74d64e08-a218-4458-8750-9af503b07c1a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4168502940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.4168502940
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.197021411
Short name T147
Test name
Test status
Simulation time 169501349 ps
CPU time 0.81 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:19 AM PDT 24
Peak memory 206200 kb
Host smart-441f389c-34ef-4ff9-80b5-e87db3502662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19702
1411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.197021411
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.284877354
Short name T446
Test name
Test status
Simulation time 181425316 ps
CPU time 0.94 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:25 AM PDT 24
Peak memory 206200 kb
Host smart-224fdd4c-14d9-4179-be1f-7de85bcfb113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28487
7354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.284877354
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.3028576511
Short name T2062
Test name
Test status
Simulation time 1323460562 ps
CPU time 2.8 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:26 AM PDT 24
Peak memory 206448 kb
Host smart-18230e4b-9ab2-491c-8dc8-b8c1adfa98aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30285
76511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.3028576511
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.618142599
Short name T1743
Test name
Test status
Simulation time 4476614668 ps
CPU time 39.56 seconds
Started Jul 02 09:12:21 AM PDT 24
Finished Jul 02 09:13:10 AM PDT 24
Peak memory 206468 kb
Host smart-7dfd41cc-4b30-4653-8f23-0d87aecbc40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61814
2599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.618142599
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.4048400803
Short name T2446
Test name
Test status
Simulation time 89012034 ps
CPU time 0.76 seconds
Started Jul 02 09:12:22 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206256 kb
Host smart-bb787981-d56d-459a-bc0b-61d27892c356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4048400803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.4048400803
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1529987676
Short name T1576
Test name
Test status
Simulation time 4425119417 ps
CPU time 5.85 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:23 AM PDT 24
Peak memory 206432 kb
Host smart-2cb13ab8-275f-4763-b94b-70093ef357ad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1529987676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.1529987676
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1839985066
Short name T1610
Test name
Test status
Simulation time 13387496527 ps
CPU time 13.11 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:37 AM PDT 24
Peak memory 206264 kb
Host smart-56e081ca-48d7-4edd-b7d9-f1d649942d40
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1839985066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1839985066
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3792001510
Short name T1773
Test name
Test status
Simulation time 23440554742 ps
CPU time 25.23 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:46 AM PDT 24
Peak memory 206408 kb
Host smart-f2bdd304-87b1-4b51-b935-f9d451f7eecc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3792001510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3792001510
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3594696371
Short name T1518
Test name
Test status
Simulation time 153536139 ps
CPU time 0.79 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:12:19 AM PDT 24
Peak memory 206136 kb
Host smart-b8cef56f-033b-4e38-80cb-19c508005ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35946
96371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3594696371
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.3605324282
Short name T946
Test name
Test status
Simulation time 160647736 ps
CPU time 0.81 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:25 AM PDT 24
Peak memory 206156 kb
Host smart-54df8630-b689-4975-8250-5031bf79d670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36053
24282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.3605324282
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.116467919
Short name T1599
Test name
Test status
Simulation time 546631499 ps
CPU time 1.45 seconds
Started Jul 02 09:12:18 AM PDT 24
Finished Jul 02 09:12:27 AM PDT 24
Peak memory 206408 kb
Host smart-fb79a904-f900-4aea-81dc-4dac559afc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11646
7919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.116467919
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3630023957
Short name T1476
Test name
Test status
Simulation time 1523148869 ps
CPU time 3.51 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:25 AM PDT 24
Peak memory 206468 kb
Host smart-76212fd8-889f-415a-9b33-c2a19aee4fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36300
23957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3630023957
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.4133067386
Short name T1735
Test name
Test status
Simulation time 19732155253 ps
CPU time 37.23 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:57 AM PDT 24
Peak memory 206604 kb
Host smart-88f9ff2b-5f34-421c-8dfc-36a953305ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41330
67386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.4133067386
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.261497903
Short name T1275
Test name
Test status
Simulation time 511882945 ps
CPU time 1.36 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:16 AM PDT 24
Peak memory 206204 kb
Host smart-c8319443-d3c5-400a-a03f-9f99f1b1d1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26149
7903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.261497903
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.2151412053
Short name T566
Test name
Test status
Simulation time 146491478 ps
CPU time 0.76 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:17 AM PDT 24
Peak memory 206212 kb
Host smart-154c6dce-ac05-4e75-9726-9a6365b67609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21514
12053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2151412053
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.469808486
Short name T2441
Test name
Test status
Simulation time 49065493 ps
CPU time 0.69 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206152 kb
Host smart-4c38107f-ab66-4c7d-a1e7-feae24fb4175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46980
8486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.469808486
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.2943727487
Short name T1144
Test name
Test status
Simulation time 995626105 ps
CPU time 2.23 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:27 AM PDT 24
Peak memory 206408 kb
Host smart-e2fd461b-2173-4c65-850e-2c5cd2f41533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29437
27487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.2943727487
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.247232008
Short name T1719
Test name
Test status
Simulation time 174315244 ps
CPU time 1.52 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206408 kb
Host smart-f39adf53-99d3-4c8f-ac57-b8d684185637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24723
2008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.247232008
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2114687417
Short name T668
Test name
Test status
Simulation time 203489172 ps
CPU time 0.84 seconds
Started Jul 02 09:12:25 AM PDT 24
Finished Jul 02 09:12:31 AM PDT 24
Peak memory 206156 kb
Host smart-43e4b003-1d16-41b0-8519-42a6cff4f1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21146
87417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2114687417
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.4067296073
Short name T802
Test name
Test status
Simulation time 138556793 ps
CPU time 0.72 seconds
Started Jul 02 09:12:20 AM PDT 24
Finished Jul 02 09:12:28 AM PDT 24
Peak memory 206152 kb
Host smart-296c7e57-55de-446e-be3d-6c751f7ede54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40672
96073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.4067296073
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.80930728
Short name T2314
Test name
Test status
Simulation time 167285938 ps
CPU time 0.79 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:25 AM PDT 24
Peak memory 206152 kb
Host smart-9e6b5a82-f193-475f-9b82-33936a647f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80930
728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.80930728
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.1212968844
Short name T1029
Test name
Test status
Simulation time 178438267 ps
CPU time 0.83 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:27 AM PDT 24
Peak memory 206192 kb
Host smart-57ea628a-ee95-487d-8c85-b73ff69c02ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12129
68844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1212968844
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.3194118982
Short name T758
Test name
Test status
Simulation time 23268461032 ps
CPU time 24.71 seconds
Started Jul 02 09:12:20 AM PDT 24
Finished Jul 02 09:12:52 AM PDT 24
Peak memory 206236 kb
Host smart-14852f65-1bc2-4d37-b296-5db12a88a9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31941
18982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.3194118982
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.239991804
Short name T797
Test name
Test status
Simulation time 3299086865 ps
CPU time 3.98 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:12:19 AM PDT 24
Peak memory 206224 kb
Host smart-00d771c3-b7b2-480d-8aaf-24713015389b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23999
1804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.239991804
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2177459380
Short name T2707
Test name
Test status
Simulation time 7902659752 ps
CPU time 225.95 seconds
Started Jul 02 09:12:13 AM PDT 24
Finished Jul 02 09:16:02 AM PDT 24
Peak memory 206484 kb
Host smart-2857d3ab-b310-4772-bab5-c6d3b0466514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21774
59380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2177459380
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.2581220436
Short name T665
Test name
Test status
Simulation time 5765190572 ps
CPU time 44.97 seconds
Started Jul 02 09:12:14 AM PDT 24
Finished Jul 02 09:13:03 AM PDT 24
Peak memory 206512 kb
Host smart-b54297c0-d19a-4a61-a74a-fa90bdb1a973
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2581220436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.2581220436
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.1133129423
Short name T2049
Test name
Test status
Simulation time 255851179 ps
CPU time 1.07 seconds
Started Jul 02 09:12:20 AM PDT 24
Finished Jul 02 09:12:28 AM PDT 24
Peak memory 206104 kb
Host smart-5f320c12-6e05-475b-9d4f-188ffa97fb23
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1133129423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.1133129423
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3382633074
Short name T1044
Test name
Test status
Simulation time 195776773 ps
CPU time 0.83 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:25 AM PDT 24
Peak memory 206212 kb
Host smart-da322871-697b-4b4f-abf4-ad2374978310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33826
33074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3382633074
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.1639501234
Short name T1135
Test name
Test status
Simulation time 5131339904 ps
CPU time 137.32 seconds
Started Jul 02 09:12:23 AM PDT 24
Finished Jul 02 09:14:47 AM PDT 24
Peak memory 206448 kb
Host smart-2c4ca6d2-430c-41d0-abb6-b87390ba7773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16395
01234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.1639501234
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.2661765418
Short name T1384
Test name
Test status
Simulation time 4392862142 ps
CPU time 30.04 seconds
Started Jul 02 09:12:25 AM PDT 24
Finished Jul 02 09:13:01 AM PDT 24
Peak memory 206436 kb
Host smart-4093b641-4956-4c5a-aba1-84ca11246981
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2661765418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.2661765418
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1102364884
Short name T2384
Test name
Test status
Simulation time 158697277 ps
CPU time 0.75 seconds
Started Jul 02 09:12:25 AM PDT 24
Finished Jul 02 09:12:31 AM PDT 24
Peak memory 206136 kb
Host smart-87ee2d4d-e1bf-4130-a26f-a4d13c53afdc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1102364884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1102364884
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1246324546
Short name T1053
Test name
Test status
Simulation time 152387900 ps
CPU time 0.87 seconds
Started Jul 02 09:12:22 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206172 kb
Host smart-505d6b51-bfff-4461-a8a8-76f14b940442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12463
24546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1246324546
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1135260772
Short name T132
Test name
Test status
Simulation time 196827438 ps
CPU time 0.91 seconds
Started Jul 02 09:12:12 AM PDT 24
Finished Jul 02 09:12:15 AM PDT 24
Peak memory 206188 kb
Host smart-63253581-b9ac-4f00-b137-3e831d6847cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11352
60772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1135260772
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.3629981521
Short name T2493
Test name
Test status
Simulation time 212507358 ps
CPU time 0.87 seconds
Started Jul 02 09:12:18 AM PDT 24
Finished Jul 02 09:12:26 AM PDT 24
Peak memory 206144 kb
Host smart-9654eaaf-4b80-40e0-958d-8f8b60c43be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36299
81521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.3629981521
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3393071604
Short name T1114
Test name
Test status
Simulation time 157987131 ps
CPU time 0.76 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:23 AM PDT 24
Peak memory 206208 kb
Host smart-c5aa737d-c5e4-49c2-b7ea-27ef21de2462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33930
71604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3393071604
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1829475383
Short name T1819
Test name
Test status
Simulation time 176962770 ps
CPU time 0.82 seconds
Started Jul 02 09:12:20 AM PDT 24
Finished Jul 02 09:12:28 AM PDT 24
Peak memory 206200 kb
Host smart-795938bb-ae7d-4029-addb-142f32a3afc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18294
75383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1829475383
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.602758222
Short name T990
Test name
Test status
Simulation time 194045532 ps
CPU time 0.8 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:27 AM PDT 24
Peak memory 206160 kb
Host smart-257117c9-bdab-4dd6-94a5-e37ff8d2b67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60275
8222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.602758222
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3732398489
Short name T914
Test name
Test status
Simulation time 205501636 ps
CPU time 0.88 seconds
Started Jul 02 09:12:25 AM PDT 24
Finished Jul 02 09:12:31 AM PDT 24
Peak memory 205936 kb
Host smart-6e944f8a-8563-4d76-ada3-996b8ce106b1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3732398489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3732398489
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3943865956
Short name T619
Test name
Test status
Simulation time 144088274 ps
CPU time 0.84 seconds
Started Jul 02 09:12:20 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206164 kb
Host smart-a5589327-6944-4092-bb5f-7684fb33a150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39438
65956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3943865956
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2784642668
Short name T1129
Test name
Test status
Simulation time 43332133 ps
CPU time 0.68 seconds
Started Jul 02 09:12:22 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206120 kb
Host smart-dcc1f7d7-35f9-465c-9b9a-582a9b344612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27846
42668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2784642668
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.4241628916
Short name T279
Test name
Test status
Simulation time 8366002083 ps
CPU time 20.65 seconds
Started Jul 02 09:12:21 AM PDT 24
Finished Jul 02 09:12:49 AM PDT 24
Peak memory 206516 kb
Host smart-eff2ed6d-23bb-45bc-82b3-65c2c41b2507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42416
28916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.4241628916
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.689953729
Short name T703
Test name
Test status
Simulation time 150560580 ps
CPU time 0.76 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:20 AM PDT 24
Peak memory 206204 kb
Host smart-9fcb051f-714c-4cf2-8fed-24b251eb98c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68995
3729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.689953729
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.44671536
Short name T2186
Test name
Test status
Simulation time 217821981 ps
CPU time 0.84 seconds
Started Jul 02 09:12:24 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206164 kb
Host smart-791f0331-5350-41c0-90fe-709d710a51f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44671
536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.44671536
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3475102740
Short name T2266
Test name
Test status
Simulation time 210162155 ps
CPU time 0.88 seconds
Started Jul 02 09:12:20 AM PDT 24
Finished Jul 02 09:12:28 AM PDT 24
Peak memory 206200 kb
Host smart-2f63d369-a553-4db7-909e-51397bdb3286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34751
02740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3475102740
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.752068959
Short name T554
Test name
Test status
Simulation time 168399896 ps
CPU time 0.82 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:20 AM PDT 24
Peak memory 206184 kb
Host smart-162fa0de-07aa-48eb-9c67-30c236595048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75206
8959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.752068959
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.4129807650
Short name T582
Test name
Test status
Simulation time 167529883 ps
CPU time 0.8 seconds
Started Jul 02 09:12:21 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206084 kb
Host smart-80efe3fe-e585-4a92-bee6-8c3f7f5ba6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41298
07650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.4129807650
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3116154846
Short name T2550
Test name
Test status
Simulation time 165949061 ps
CPU time 0.75 seconds
Started Jul 02 09:12:23 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206204 kb
Host smart-3f669ed8-7b04-4e3c-8b67-5207f74072b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31161
54846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3116154846
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2927137464
Short name T1234
Test name
Test status
Simulation time 156373783 ps
CPU time 0.79 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206180 kb
Host smart-835b5f06-c6e3-4d45-a658-915d2d564774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29271
37464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2927137464
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1444885603
Short name T1744
Test name
Test status
Simulation time 226757886 ps
CPU time 0.96 seconds
Started Jul 02 09:12:16 AM PDT 24
Finished Jul 02 09:12:22 AM PDT 24
Peak memory 206196 kb
Host smart-97a16302-57f4-466e-8034-92cf5c00a9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14448
85603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1444885603
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.3708212651
Short name T1435
Test name
Test status
Simulation time 3415905151 ps
CPU time 29.86 seconds
Started Jul 02 09:12:21 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206436 kb
Host smart-3d393866-cbbf-4d73-95de-2cc896b2b2c5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3708212651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.3708212651
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1765514522
Short name T1091
Test name
Test status
Simulation time 158925504 ps
CPU time 0.76 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:25 AM PDT 24
Peak memory 206184 kb
Host smart-4325fd8f-9c39-4d4d-8d46-a48a3426f82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17655
14522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1765514522
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2239700576
Short name T2107
Test name
Test status
Simulation time 177117650 ps
CPU time 0.82 seconds
Started Jul 02 09:12:25 AM PDT 24
Finished Jul 02 09:12:31 AM PDT 24
Peak memory 205908 kb
Host smart-dc604372-6301-45b1-95ee-4a5f1ba882ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22397
00576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2239700576
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1407457525
Short name T1305
Test name
Test status
Simulation time 201025576 ps
CPU time 0.87 seconds
Started Jul 02 09:12:17 AM PDT 24
Finished Jul 02 09:12:25 AM PDT 24
Peak memory 206344 kb
Host smart-1314ce38-dc59-4550-9404-12f6493c6661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14074
57525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1407457525
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1575778532
Short name T1391
Test name
Test status
Simulation time 3156878863 ps
CPU time 27.98 seconds
Started Jul 02 09:12:25 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206480 kb
Host smart-3bca0078-33ec-4762-a6dd-94ebe8448aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15757
78532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1575778532
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.2612797096
Short name T2585
Test name
Test status
Simulation time 72382939 ps
CPU time 0.72 seconds
Started Jul 02 09:12:30 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206240 kb
Host smart-d3af44fd-f4ec-44b8-84a6-334fb2a55807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2612797096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2612797096
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2192074291
Short name T2323
Test name
Test status
Simulation time 3838757915 ps
CPU time 4.38 seconds
Started Jul 02 09:12:15 AM PDT 24
Finished Jul 02 09:12:24 AM PDT 24
Peak memory 206444 kb
Host smart-1faa9fb6-08f2-4e27-b783-229885c83985
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2192074291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2192074291
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.4263971025
Short name T2245
Test name
Test status
Simulation time 13476437400 ps
CPU time 15.17 seconds
Started Jul 02 09:12:25 AM PDT 24
Finished Jul 02 09:12:46 AM PDT 24
Peak memory 206500 kb
Host smart-e689a709-bc82-407c-8377-37f8476282c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4263971025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.4263971025
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3627411388
Short name T2228
Test name
Test status
Simulation time 23392238843 ps
CPU time 24.37 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:51 AM PDT 24
Peak memory 206256 kb
Host smart-92743cc1-a133-4775-93d3-e5ad13d23d47
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3627411388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.3627411388
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3952700215
Short name T1564
Test name
Test status
Simulation time 184401633 ps
CPU time 0.83 seconds
Started Jul 02 09:12:20 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206216 kb
Host smart-43314012-7151-40b2-98d2-4f39fd114c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39527
00215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3952700215
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.764510974
Short name T2661
Test name
Test status
Simulation time 205010065 ps
CPU time 0.82 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:27 AM PDT 24
Peak memory 206192 kb
Host smart-5524e913-4d10-4de6-ba3e-7cab6690f9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76451
0974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.764510974
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.479250647
Short name T1830
Test name
Test status
Simulation time 448569563 ps
CPU time 1.34 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:28 AM PDT 24
Peak memory 206188 kb
Host smart-d5d65581-d662-40f5-b6ea-d529900d9bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47925
0647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.479250647
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1844762404
Short name T1800
Test name
Test status
Simulation time 753087813 ps
CPU time 1.95 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:28 AM PDT 24
Peak memory 206396 kb
Host smart-2c55a224-9e8a-4668-97b3-3b5a779cebe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18447
62404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1844762404
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1106468217
Short name T1179
Test name
Test status
Simulation time 7297675245 ps
CPU time 16.27 seconds
Started Jul 02 09:12:24 AM PDT 24
Finished Jul 02 09:12:46 AM PDT 24
Peak memory 206464 kb
Host smart-079b343b-d6ad-4010-b1fc-c9ad8a484695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11064
68217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1106468217
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.1229900975
Short name T483
Test name
Test status
Simulation time 313883703 ps
CPU time 1.06 seconds
Started Jul 02 09:12:25 AM PDT 24
Finished Jul 02 09:12:32 AM PDT 24
Peak memory 206180 kb
Host smart-0caecf23-b9c4-48d9-8ec9-ff8ccb5e14b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12299
00975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.1229900975
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.533683926
Short name T2641
Test name
Test status
Simulation time 136794373 ps
CPU time 0.75 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:27 AM PDT 24
Peak memory 206184 kb
Host smart-1ff40330-47bf-4835-ad90-dee31deaa90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53368
3926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.533683926
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2328212634
Short name T885
Test name
Test status
Simulation time 41195044 ps
CPU time 0.65 seconds
Started Jul 02 09:12:22 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206216 kb
Host smart-425abdb0-ae09-4a57-a563-ec39afb4fd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
12634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2328212634
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.462468509
Short name T2573
Test name
Test status
Simulation time 813352800 ps
CPU time 2.34 seconds
Started Jul 02 09:12:24 AM PDT 24
Finished Jul 02 09:12:32 AM PDT 24
Peak memory 206396 kb
Host smart-5090cf1d-a015-49f2-a15f-b33f66a15ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46246
8509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.462468509
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3159522980
Short name T2036
Test name
Test status
Simulation time 180663636 ps
CPU time 2.13 seconds
Started Jul 02 09:12:18 AM PDT 24
Finished Jul 02 09:12:27 AM PDT 24
Peak memory 206436 kb
Host smart-e8a273d0-54fb-4bbb-88d8-6080a841081a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31595
22980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3159522980
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2250319487
Short name T237
Test name
Test status
Simulation time 221573719 ps
CPU time 0.9 seconds
Started Jul 02 09:12:22 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206216 kb
Host smart-fa3d6619-b4d2-499b-beb0-d93a2ed5ee22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22503
19487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2250319487
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3477825426
Short name T2630
Test name
Test status
Simulation time 142991159 ps
CPU time 0.79 seconds
Started Jul 02 09:12:21 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206120 kb
Host smart-153b0b5e-167f-4a3b-a23b-368ce1cb2bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34778
25426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3477825426
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1819615207
Short name T598
Test name
Test status
Simulation time 184619164 ps
CPU time 0.8 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:27 AM PDT 24
Peak memory 206208 kb
Host smart-e2f550a8-94ca-47df-8e94-020263a6c50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18196
15207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1819615207
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.754214783
Short name T1164
Test name
Test status
Simulation time 8346880142 ps
CPU time 76.31 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:13:43 AM PDT 24
Peak memory 206452 kb
Host smart-a83a5e4f-e976-4f3a-a6c0-dbf8b179097c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=754214783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.754214783
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.866389259
Short name T1093
Test name
Test status
Simulation time 167423133 ps
CPU time 0.79 seconds
Started Jul 02 09:12:21 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206180 kb
Host smart-50e724bc-9242-499d-93fc-fe8e085159ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86638
9259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.866389259
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1437575449
Short name T2273
Test name
Test status
Simulation time 23328281708 ps
CPU time 22.23 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:48 AM PDT 24
Peak memory 206256 kb
Host smart-e753f7a9-b661-4287-8363-369564c3f036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14375
75449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1437575449
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3711686467
Short name T1103
Test name
Test status
Simulation time 3300185670 ps
CPU time 3.58 seconds
Started Jul 02 09:12:22 AM PDT 24
Finished Jul 02 09:12:32 AM PDT 24
Peak memory 206276 kb
Host smart-7f491c07-1467-4edc-97af-c9f6a704110b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37116
86467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3711686467
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.292803695
Short name T496
Test name
Test status
Simulation time 13466693639 ps
CPU time 136.49 seconds
Started Jul 02 09:12:22 AM PDT 24
Finished Jul 02 09:14:45 AM PDT 24
Peak memory 206740 kb
Host smart-f050a432-8b60-4191-9e81-b972517b4e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29280
3695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.292803695
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.452433279
Short name T1818
Test name
Test status
Simulation time 2835728049 ps
CPU time 19 seconds
Started Jul 02 09:12:25 AM PDT 24
Finished Jul 02 09:12:49 AM PDT 24
Peak memory 206604 kb
Host smart-fafc619c-aef2-4dcc-b669-3ab8a7fd969b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=452433279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.452433279
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.2802591189
Short name T1913
Test name
Test status
Simulation time 286656876 ps
CPU time 0.94 seconds
Started Jul 02 09:12:21 AM PDT 24
Finished Jul 02 09:12:29 AM PDT 24
Peak memory 206164 kb
Host smart-4e36665d-e70e-49be-8c75-bc13ff153181
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2802591189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.2802591189
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.4231175814
Short name T1250
Test name
Test status
Simulation time 189707235 ps
CPU time 0.9 seconds
Started Jul 02 09:12:20 AM PDT 24
Finished Jul 02 09:12:28 AM PDT 24
Peak memory 206184 kb
Host smart-2f7a72b8-a64c-485b-899d-6dd85c98db14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42311
75814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.4231175814
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1135745209
Short name T1677
Test name
Test status
Simulation time 3852739012 ps
CPU time 36.09 seconds
Started Jul 02 09:12:24 AM PDT 24
Finished Jul 02 09:13:06 AM PDT 24
Peak memory 206388 kb
Host smart-a3edfec0-5caf-4510-8df2-6db3e082cc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11357
45209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1135745209
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.1932506678
Short name T2606
Test name
Test status
Simulation time 4556397219 ps
CPU time 31.46 seconds
Started Jul 02 09:12:19 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206484 kb
Host smart-b6f2d4a4-31d7-4cad-9050-04de661458c0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1932506678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.1932506678
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1365052696
Short name T1557
Test name
Test status
Simulation time 214289514 ps
CPU time 0.85 seconds
Started Jul 02 09:12:41 AM PDT 24
Finished Jul 02 09:12:43 AM PDT 24
Peak memory 206188 kb
Host smart-9c5e35f4-1cd2-4620-a209-6bf08c0ae647
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1365052696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1365052696
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2209280085
Short name T232
Test name
Test status
Simulation time 136654925 ps
CPU time 0.78 seconds
Started Jul 02 09:12:24 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206224 kb
Host smart-d51cc646-fe2b-4f9e-8244-3c1691c4ec93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22092
80085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2209280085
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1558505002
Short name T2255
Test name
Test status
Simulation time 210254065 ps
CPU time 0.93 seconds
Started Jul 02 09:12:25 AM PDT 24
Finished Jul 02 09:12:31 AM PDT 24
Peak memory 206212 kb
Host smart-80641bb8-b1f3-463e-a532-a8cc5b155a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
05002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1558505002
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.1812707488
Short name T1910
Test name
Test status
Simulation time 169998440 ps
CPU time 0.82 seconds
Started Jul 02 09:12:28 AM PDT 24
Finished Jul 02 09:12:32 AM PDT 24
Peak memory 206188 kb
Host smart-d12c84af-8ca6-4098-9699-767743a8fd38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18127
07488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.1812707488
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3373163683
Short name T360
Test name
Test status
Simulation time 165000720 ps
CPU time 0.82 seconds
Started Jul 02 09:12:30 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206176 kb
Host smart-e3722035-5970-478a-b2f2-67a81448d568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33731
63683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3373163683
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.996386781
Short name T617
Test name
Test status
Simulation time 179296251 ps
CPU time 0.83 seconds
Started Jul 02 09:12:29 AM PDT 24
Finished Jul 02 09:12:33 AM PDT 24
Peak memory 206156 kb
Host smart-32f36c37-9ed3-4121-ac71-151f9a5184a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99638
6781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.996386781
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2109053692
Short name T2125
Test name
Test status
Simulation time 179798867 ps
CPU time 0.82 seconds
Started Jul 02 09:12:28 AM PDT 24
Finished Jul 02 09:12:32 AM PDT 24
Peak memory 206208 kb
Host smart-fc4dabd4-9a28-42d5-a871-332e7ecd9d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21090
53692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2109053692
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1041276409
Short name T1705
Test name
Test status
Simulation time 217204217 ps
CPU time 0.88 seconds
Started Jul 02 09:12:24 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206180 kb
Host smart-47830e32-7567-4e38-a281-12d389a0bb2d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1041276409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1041276409
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1343285915
Short name T851
Test name
Test status
Simulation time 191193502 ps
CPU time 0.8 seconds
Started Jul 02 09:12:23 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206208 kb
Host smart-14e71245-1d1f-4907-b4d7-e51c129d2df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13432
85915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1343285915
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3154800660
Short name T2596
Test name
Test status
Simulation time 33021354 ps
CPU time 0.66 seconds
Started Jul 02 09:12:30 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206192 kb
Host smart-b981fdb7-676b-47b7-9feb-2342545e8dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31548
00660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3154800660
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.428214205
Short name T299
Test name
Test status
Simulation time 8032473596 ps
CPU time 19.89 seconds
Started Jul 02 09:12:31 AM PDT 24
Finished Jul 02 09:12:53 AM PDT 24
Peak memory 206564 kb
Host smart-56903df3-e306-4a8b-a0cd-4a773da35c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42821
4205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.428214205
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.545474853
Short name T1060
Test name
Test status
Simulation time 195866688 ps
CPU time 0.88 seconds
Started Jul 02 09:12:26 AM PDT 24
Finished Jul 02 09:12:32 AM PDT 24
Peak memory 206212 kb
Host smart-222d116d-d70b-4721-8b60-2baeb585305c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54547
4853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.545474853
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2635801271
Short name T1858
Test name
Test status
Simulation time 208981745 ps
CPU time 0.82 seconds
Started Jul 02 09:12:23 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206160 kb
Host smart-f2b2ef25-7483-44bb-8622-47585973c030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26358
01271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2635801271
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.639225974
Short name T1512
Test name
Test status
Simulation time 204106585 ps
CPU time 0.87 seconds
Started Jul 02 09:12:29 AM PDT 24
Finished Jul 02 09:12:33 AM PDT 24
Peak memory 206196 kb
Host smart-de7477fb-5080-42e3-b226-4f09a976173a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63922
5974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.639225974
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3546125324
Short name T549
Test name
Test status
Simulation time 157274504 ps
CPU time 0.81 seconds
Started Jul 02 09:12:30 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206192 kb
Host smart-dcf46429-0224-43f2-bbf3-3a20b48bb381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35461
25324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3546125324
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3068623626
Short name T1244
Test name
Test status
Simulation time 217243621 ps
CPU time 0.81 seconds
Started Jul 02 09:12:29 AM PDT 24
Finished Jul 02 09:12:33 AM PDT 24
Peak memory 206216 kb
Host smart-927cb19a-8c15-4c46-80fc-d0cc04f314cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30686
23626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3068623626
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.302202688
Short name T2461
Test name
Test status
Simulation time 156192843 ps
CPU time 0.77 seconds
Started Jul 02 09:12:32 AM PDT 24
Finished Jul 02 09:12:35 AM PDT 24
Peak memory 206120 kb
Host smart-e3a875b2-8013-472d-8d10-e9b7238017a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30220
2688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.302202688
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2496479199
Short name T887
Test name
Test status
Simulation time 156756830 ps
CPU time 0.77 seconds
Started Jul 02 09:12:23 AM PDT 24
Finished Jul 02 09:12:30 AM PDT 24
Peak memory 206140 kb
Host smart-3439fb8e-85f5-41da-974f-37a83acb56e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24964
79199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2496479199
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.600671930
Short name T865
Test name
Test status
Simulation time 223560572 ps
CPU time 0.92 seconds
Started Jul 02 09:12:30 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206208 kb
Host smart-ed79ebec-064b-4cb9-a72e-fc78458f0256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60067
1930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.600671930
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2970867777
Short name T1042
Test name
Test status
Simulation time 5475151017 ps
CPU time 48.9 seconds
Started Jul 02 09:12:31 AM PDT 24
Finished Jul 02 09:13:22 AM PDT 24
Peak memory 206468 kb
Host smart-cead6263-460e-4e24-bf2f-6fece3ec5462
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2970867777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2970867777
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1958600583
Short name T2528
Test name
Test status
Simulation time 200673307 ps
CPU time 0.87 seconds
Started Jul 02 09:12:29 AM PDT 24
Finished Jul 02 09:12:33 AM PDT 24
Peak memory 206392 kb
Host smart-bbcfa2cc-0f3a-408c-a29b-702826f6eb13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19586
00583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1958600583
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2857244615
Short name T1428
Test name
Test status
Simulation time 160534517 ps
CPU time 0.88 seconds
Started Jul 02 09:12:28 AM PDT 24
Finished Jul 02 09:12:33 AM PDT 24
Peak memory 206204 kb
Host smart-fff2eb4f-1070-46e1-9401-df5fb2926962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28572
44615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2857244615
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.1209219251
Short name T453
Test name
Test status
Simulation time 351651064 ps
CPU time 1.08 seconds
Started Jul 02 09:12:30 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206344 kb
Host smart-5e63ca71-725f-40cd-9d90-dc1643b1c7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
19251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.1209219251
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.4273601404
Short name T764
Test name
Test status
Simulation time 6723418999 ps
CPU time 59.47 seconds
Started Jul 02 09:12:35 AM PDT 24
Finished Jul 02 09:13:36 AM PDT 24
Peak memory 206424 kb
Host smart-75c6ccc3-3486-4ff4-8f95-2777334c532b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42736
01404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.4273601404
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.1148709066
Short name T1973
Test name
Test status
Simulation time 86887240 ps
CPU time 0.77 seconds
Started Jul 02 09:12:53 AM PDT 24
Finished Jul 02 09:12:55 AM PDT 24
Peak memory 206256 kb
Host smart-320f9343-4632-49f9-b2f8-f762377035e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1148709066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.1148709066
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1242780836
Short name T1703
Test name
Test status
Simulation time 4177856760 ps
CPU time 4.55 seconds
Started Jul 02 09:12:26 AM PDT 24
Finished Jul 02 09:12:35 AM PDT 24
Peak memory 206520 kb
Host smart-ce025c7c-b197-40d2-ab83-e41ae34bfe32
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1242780836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.1242780836
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1768643687
Short name T1771
Test name
Test status
Simulation time 13360054744 ps
CPU time 14.68 seconds
Started Jul 02 09:12:34 AM PDT 24
Finished Jul 02 09:12:50 AM PDT 24
Peak memory 206252 kb
Host smart-31179bed-fd65-478c-b3ac-45a753843b70
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1768643687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1768643687
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.743487232
Short name T1441
Test name
Test status
Simulation time 23332686881 ps
CPU time 23.68 seconds
Started Jul 02 09:12:32 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206492 kb
Host smart-d03574e5-aafc-4741-b191-b6cbcea66bfa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=743487232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.743487232
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.326895536
Short name T1813
Test name
Test status
Simulation time 159748640 ps
CPU time 0.77 seconds
Started Jul 02 09:12:31 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206208 kb
Host smart-2001ab8e-949a-4419-9129-68eea9987738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32689
5536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.326895536
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.4030388318
Short name T64
Test name
Test status
Simulation time 153306512 ps
CPU time 0.77 seconds
Started Jul 02 09:12:29 AM PDT 24
Finished Jul 02 09:12:33 AM PDT 24
Peak memory 206184 kb
Host smart-0da9ffc5-f271-4c19-b3a0-421677afd366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40303
88318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.4030388318
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2476145782
Short name T2396
Test name
Test status
Simulation time 588641273 ps
CPU time 1.64 seconds
Started Jul 02 09:12:37 AM PDT 24
Finished Jul 02 09:12:39 AM PDT 24
Peak memory 206408 kb
Host smart-ad4ee09a-ce63-4ce0-b08d-15e51ac6a2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24761
45782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2476145782
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1249743869
Short name T2027
Test name
Test status
Simulation time 528145500 ps
CPU time 1.45 seconds
Started Jul 02 09:12:32 AM PDT 24
Finished Jul 02 09:12:36 AM PDT 24
Peak memory 206220 kb
Host smart-7c0ee345-89a7-4196-9268-8709b9547a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12497
43869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1249743869
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.1885038469
Short name T2701
Test name
Test status
Simulation time 10757888682 ps
CPU time 21.6 seconds
Started Jul 02 09:12:42 AM PDT 24
Finished Jul 02 09:13:04 AM PDT 24
Peak memory 206468 kb
Host smart-734688f7-b3e1-4cf6-85c6-867665b0e8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18850
38469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1885038469
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.4084375912
Short name T2516
Test name
Test status
Simulation time 471092635 ps
CPU time 1.45 seconds
Started Jul 02 09:12:29 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206176 kb
Host smart-be81ad23-1d94-4c2a-966d-e09d4dafdadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40843
75912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.4084375912
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.3918400234
Short name T2522
Test name
Test status
Simulation time 166123736 ps
CPU time 0.76 seconds
Started Jul 02 09:12:31 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206196 kb
Host smart-dd8838c3-2047-4fea-9343-b37219210413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39184
00234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3918400234
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.524880100
Short name T736
Test name
Test status
Simulation time 30034637 ps
CPU time 0.64 seconds
Started Jul 02 09:12:38 AM PDT 24
Finished Jul 02 09:12:39 AM PDT 24
Peak memory 206208 kb
Host smart-1fa28a2b-5c30-4fa6-a118-65b52cf13c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52488
0100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.524880100
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1805435089
Short name T2434
Test name
Test status
Simulation time 856457579 ps
CPU time 2.18 seconds
Started Jul 02 09:12:31 AM PDT 24
Finished Jul 02 09:12:35 AM PDT 24
Peak memory 206412 kb
Host smart-77f00a27-a228-4d91-bb89-db1ccb6f9e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18054
35089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1805435089
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2167241043
Short name T928
Test name
Test status
Simulation time 351840220 ps
CPU time 2.09 seconds
Started Jul 02 09:12:36 AM PDT 24
Finished Jul 02 09:12:39 AM PDT 24
Peak memory 206264 kb
Host smart-288197d7-50de-45ed-906d-3bcfde615f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21672
41043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2167241043
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2276624099
Short name T2046
Test name
Test status
Simulation time 189323172 ps
CPU time 0.84 seconds
Started Jul 02 09:12:33 AM PDT 24
Finished Jul 02 09:12:36 AM PDT 24
Peak memory 206164 kb
Host smart-fd32f97b-db47-4639-8a57-7754179be547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22766
24099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2276624099
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2507116405
Short name T235
Test name
Test status
Simulation time 145301212 ps
CPU time 0.76 seconds
Started Jul 02 09:12:30 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206196 kb
Host smart-d6f9283e-2629-44af-bbd4-9b756fc7bd38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25071
16405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2507116405
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2210961226
Short name T971
Test name
Test status
Simulation time 209030098 ps
CPU time 0.84 seconds
Started Jul 02 09:12:32 AM PDT 24
Finished Jul 02 09:12:35 AM PDT 24
Peak memory 206124 kb
Host smart-a29f1c9f-a418-4090-83f1-0cc44d135d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22109
61226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2210961226
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1210963481
Short name T456
Test name
Test status
Simulation time 246448216 ps
CPU time 0.99 seconds
Started Jul 02 09:12:30 AM PDT 24
Finished Jul 02 09:12:34 AM PDT 24
Peak memory 206168 kb
Host smart-b68a95cb-1289-4bf0-aeca-84ad3dc585b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12109
63481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1210963481
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.1138580586
Short name T1124
Test name
Test status
Simulation time 23291211939 ps
CPU time 26.65 seconds
Started Jul 02 09:12:33 AM PDT 24
Finished Jul 02 09:13:02 AM PDT 24
Peak memory 206228 kb
Host smart-a1786565-a69a-4311-aebe-67fd7bdb3245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11385
80586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.1138580586
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.751814606
Short name T2259
Test name
Test status
Simulation time 3311418646 ps
CPU time 3.98 seconds
Started Jul 02 09:12:32 AM PDT 24
Finished Jul 02 09:12:39 AM PDT 24
Peak memory 206192 kb
Host smart-68f52e43-68d6-40e7-bca4-55671322e6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75181
4606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.751814606
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.895366796
Short name T2066
Test name
Test status
Simulation time 8140778509 ps
CPU time 227.61 seconds
Started Jul 02 09:12:31 AM PDT 24
Finished Jul 02 09:16:21 AM PDT 24
Peak memory 206488 kb
Host smart-1b035a0e-9ec8-4fd0-bead-0d2a5f2c86fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89536
6796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.895366796
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2640549012
Short name T2169
Test name
Test status
Simulation time 5429370756 ps
CPU time 41.85 seconds
Started Jul 02 09:12:31 AM PDT 24
Finished Jul 02 09:13:16 AM PDT 24
Peak memory 206312 kb
Host smart-0c52fa7b-c156-4237-b4dc-d7ed2ac6f0e2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2640549012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2640549012
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.27041776
Short name T1814
Test name
Test status
Simulation time 283020253 ps
CPU time 0.94 seconds
Started Jul 02 09:12:31 AM PDT 24
Finished Jul 02 09:12:35 AM PDT 24
Peak memory 206196 kb
Host smart-cde26957-ca27-47f2-a823-017168f6d179
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=27041776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.27041776
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1893242224
Short name T336
Test name
Test status
Simulation time 187271780 ps
CPU time 0.85 seconds
Started Jul 02 09:12:37 AM PDT 24
Finished Jul 02 09:12:38 AM PDT 24
Peak memory 206176 kb
Host smart-38d6c589-ca33-4a38-a260-7e8a36e44830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18932
42224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1893242224
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3017517892
Short name T1230
Test name
Test status
Simulation time 6274033377 ps
CPU time 43.62 seconds
Started Jul 02 09:12:32 AM PDT 24
Finished Jul 02 09:13:18 AM PDT 24
Peak memory 206532 kb
Host smart-45c2d3a5-89af-41cb-a02e-0fb5e1b2cb94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30175
17892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3017517892
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.3706641855
Short name T1932
Test name
Test status
Simulation time 3939324996 ps
CPU time 28.44 seconds
Started Jul 02 09:12:31 AM PDT 24
Finished Jul 02 09:13:03 AM PDT 24
Peak memory 206456 kb
Host smart-b348fa4a-0b34-4c88-a158-66ad8cce6e0c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3706641855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.3706641855
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.287487973
Short name T2227
Test name
Test status
Simulation time 156375464 ps
CPU time 0.81 seconds
Started Jul 02 09:12:37 AM PDT 24
Finished Jul 02 09:12:38 AM PDT 24
Peak memory 206152 kb
Host smart-e11a810c-736f-4565-986a-7fb41ed63b4f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=287487973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.287487973
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2781083484
Short name T728
Test name
Test status
Simulation time 141995871 ps
CPU time 0.8 seconds
Started Jul 02 09:12:37 AM PDT 24
Finished Jul 02 09:12:38 AM PDT 24
Peak memory 206124 kb
Host smart-f7eeb9fc-741d-44d6-b72e-d6abfd01175d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27810
83484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2781083484
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1194800307
Short name T126
Test name
Test status
Simulation time 180902246 ps
CPU time 0.81 seconds
Started Jul 02 09:12:49 AM PDT 24
Finished Jul 02 09:12:51 AM PDT 24
Peak memory 206168 kb
Host smart-9b6d4bbe-9ee0-4bcd-b3b1-6158910c1a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11948
00307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1194800307
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2254597075
Short name T2090
Test name
Test status
Simulation time 175004601 ps
CPU time 0.86 seconds
Started Jul 02 09:12:48 AM PDT 24
Finished Jul 02 09:12:49 AM PDT 24
Peak memory 206184 kb
Host smart-d9c65125-d1d6-437b-9c4e-bda9edba5ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22545
97075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2254597075
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1584917470
Short name T1997
Test name
Test status
Simulation time 176594756 ps
CPU time 0.83 seconds
Started Jul 02 09:12:34 AM PDT 24
Finished Jul 02 09:12:36 AM PDT 24
Peak memory 206196 kb
Host smart-19f036cf-5aff-4cc8-82b0-1a213dc58116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15849
17470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1584917470
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2510194252
Short name T838
Test name
Test status
Simulation time 174473310 ps
CPU time 0.84 seconds
Started Jul 02 09:12:46 AM PDT 24
Finished Jul 02 09:12:47 AM PDT 24
Peak memory 206140 kb
Host smart-0c060aa5-8fc1-4f45-8059-cdfbc9cd1f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25101
94252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2510194252
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.4230706776
Short name T1574
Test name
Test status
Simulation time 156400406 ps
CPU time 0.77 seconds
Started Jul 02 09:12:47 AM PDT 24
Finished Jul 02 09:12:48 AM PDT 24
Peak memory 206208 kb
Host smart-c3d0a0cf-ccce-4d6c-af6f-8e6ed928edb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42307
06776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.4230706776
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.140207164
Short name T1243
Test name
Test status
Simulation time 246010199 ps
CPU time 1 seconds
Started Jul 02 09:12:40 AM PDT 24
Finished Jul 02 09:12:42 AM PDT 24
Peak memory 206188 kb
Host smart-758efe3c-b5b5-4985-959f-a1e7e5c7e5dd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=140207164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.140207164
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2192513076
Short name T2433
Test name
Test status
Simulation time 139431204 ps
CPU time 0.78 seconds
Started Jul 02 09:12:35 AM PDT 24
Finished Jul 02 09:12:37 AM PDT 24
Peak memory 206212 kb
Host smart-352b0218-6e42-4193-95f2-5dd49f8d3249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21925
13076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2192513076
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.483567288
Short name T40
Test name
Test status
Simulation time 38330985 ps
CPU time 0.7 seconds
Started Jul 02 09:12:35 AM PDT 24
Finished Jul 02 09:12:37 AM PDT 24
Peak memory 206208 kb
Host smart-d956c49a-9735-4895-8de7-df89aacb0910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48356
7288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.483567288
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1752485892
Short name T1618
Test name
Test status
Simulation time 10280398212 ps
CPU time 22.82 seconds
Started Jul 02 09:12:44 AM PDT 24
Finished Jul 02 09:13:07 AM PDT 24
Peak memory 206504 kb
Host smart-52f7d132-f0b1-42a0-a591-c87e4ba6c452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17524
85892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1752485892
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.4031602833
Short name T1218
Test name
Test status
Simulation time 184264967 ps
CPU time 0.86 seconds
Started Jul 02 09:12:34 AM PDT 24
Finished Jul 02 09:12:37 AM PDT 24
Peak memory 206216 kb
Host smart-673ed681-0a74-41e4-89c3-1023edc14f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40316
02833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.4031602833
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1007136673
Short name T855
Test name
Test status
Simulation time 175324649 ps
CPU time 0.85 seconds
Started Jul 02 09:12:37 AM PDT 24
Finished Jul 02 09:12:38 AM PDT 24
Peak memory 206204 kb
Host smart-649b5928-62dc-4202-80f2-9d7bb25dfb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10071
36673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1007136673
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3317485381
Short name T448
Test name
Test status
Simulation time 245565922 ps
CPU time 0.9 seconds
Started Jul 02 09:12:37 AM PDT 24
Finished Jul 02 09:12:39 AM PDT 24
Peak memory 206208 kb
Host smart-42647fb7-6c8d-45a5-bdbf-9e570e13355b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33174
85381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3317485381
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.4177598416
Short name T1589
Test name
Test status
Simulation time 182923004 ps
CPU time 0.84 seconds
Started Jul 02 09:12:35 AM PDT 24
Finished Jul 02 09:12:37 AM PDT 24
Peak memory 206212 kb
Host smart-f12403df-ae32-4599-8de2-f0238723845f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41775
98416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.4177598416
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.4107732442
Short name T1524
Test name
Test status
Simulation time 148150925 ps
CPU time 0.77 seconds
Started Jul 02 09:12:34 AM PDT 24
Finished Jul 02 09:12:36 AM PDT 24
Peak memory 206204 kb
Host smart-8b13ef19-fddf-479d-9c2d-14c50c37931f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41077
32442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.4107732442
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2922388246
Short name T2333
Test name
Test status
Simulation time 146176017 ps
CPU time 0.75 seconds
Started Jul 02 09:12:45 AM PDT 24
Finished Jul 02 09:12:46 AM PDT 24
Peak memory 206168 kb
Host smart-ce4f222a-4987-4044-ade1-8b80053ea727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29223
88246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2922388246
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2019778105
Short name T2138
Test name
Test status
Simulation time 216045157 ps
CPU time 0.83 seconds
Started Jul 02 09:12:43 AM PDT 24
Finished Jul 02 09:12:45 AM PDT 24
Peak memory 206192 kb
Host smart-73a2de4a-cde0-4ce1-9fd7-f6419bad90c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20197
78105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2019778105
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1790202
Short name T616
Test name
Test status
Simulation time 250161561 ps
CPU time 0.99 seconds
Started Jul 02 09:12:51 AM PDT 24
Finished Jul 02 09:12:53 AM PDT 24
Peak memory 206220 kb
Host smart-021cf858-f330-4e29-97d6-6c3b1a536487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17902
02 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1790202
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.840363159
Short name T1238
Test name
Test status
Simulation time 5744965438 ps
CPU time 160.39 seconds
Started Jul 02 09:12:39 AM PDT 24
Finished Jul 02 09:15:20 AM PDT 24
Peak memory 206524 kb
Host smart-a391e236-0d51-470d-9ad9-4ac7166e3517
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=840363159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.840363159
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.719151219
Short name T1548
Test name
Test status
Simulation time 155013387 ps
CPU time 0.77 seconds
Started Jul 02 09:13:03 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206080 kb
Host smart-224caf14-4f52-4470-926e-123bf0ca3f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71915
1219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.719151219
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1243637940
Short name T2011
Test name
Test status
Simulation time 220445065 ps
CPU time 0.84 seconds
Started Jul 02 09:12:54 AM PDT 24
Finished Jul 02 09:12:57 AM PDT 24
Peak memory 206172 kb
Host smart-070a3658-7b9f-4fdd-976e-f259332628f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12436
37940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1243637940
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.324562362
Short name T1106
Test name
Test status
Simulation time 972408633 ps
CPU time 2.14 seconds
Started Jul 02 09:12:50 AM PDT 24
Finished Jul 02 09:12:54 AM PDT 24
Peak memory 206252 kb
Host smart-899adf13-14e8-43ae-aedf-cffd2747b475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32456
2362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.324562362
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.2585274701
Short name T1821
Test name
Test status
Simulation time 6869324718 ps
CPU time 63.23 seconds
Started Jul 02 09:12:45 AM PDT 24
Finished Jul 02 09:13:49 AM PDT 24
Peak memory 206452 kb
Host smart-a64f7d0f-d9e6-4e48-b6da-95a6484b6e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
74701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.2585274701
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.2204599799
Short name T2222
Test name
Test status
Simulation time 36243916 ps
CPU time 0.67 seconds
Started Jul 02 09:12:58 AM PDT 24
Finished Jul 02 09:13:00 AM PDT 24
Peak memory 206208 kb
Host smart-354376d7-f526-4e29-a725-a11f17b64ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2204599799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.2204599799
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3918302585
Short name T1895
Test name
Test status
Simulation time 4360204492 ps
CPU time 4.91 seconds
Started Jul 02 09:12:42 AM PDT 24
Finished Jul 02 09:12:48 AM PDT 24
Peak memory 206196 kb
Host smart-7334e2e7-d0cd-437d-916d-5d11f3bb183a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3918302585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3918302585
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2969191579
Short name T1926
Test name
Test status
Simulation time 13367693111 ps
CPU time 15.92 seconds
Started Jul 02 09:12:53 AM PDT 24
Finished Jul 02 09:13:11 AM PDT 24
Peak memory 206244 kb
Host smart-156eca3e-09ad-4d72-8590-3ba65e14ad73
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2969191579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2969191579
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3571011776
Short name T519
Test name
Test status
Simulation time 23403497047 ps
CPU time 23.07 seconds
Started Jul 02 09:12:49 AM PDT 24
Finished Jul 02 09:13:13 AM PDT 24
Peak memory 206432 kb
Host smart-af3157a4-8093-4e49-af39-da848d29c2d6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3571011776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.3571011776
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2040129072
Short name T2313
Test name
Test status
Simulation time 249328782 ps
CPU time 1 seconds
Started Jul 02 09:12:40 AM PDT 24
Finished Jul 02 09:12:42 AM PDT 24
Peak memory 206388 kb
Host smart-25812646-d4cd-45c3-85b7-91f7a6480374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20401
29072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2040129072
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3200415892
Short name T791
Test name
Test status
Simulation time 201627436 ps
CPU time 0.86 seconds
Started Jul 02 09:12:46 AM PDT 24
Finished Jul 02 09:12:47 AM PDT 24
Peak memory 206124 kb
Host smart-37727596-865e-4301-b36a-74ee698db3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32004
15892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3200415892
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.1190781948
Short name T1434
Test name
Test status
Simulation time 503534637 ps
CPU time 1.54 seconds
Started Jul 02 09:12:54 AM PDT 24
Finished Jul 02 09:12:57 AM PDT 24
Peak memory 206404 kb
Host smart-e767ded7-9284-44bd-b8e8-b3520a5da090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11907
81948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.1190781948
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2526957750
Short name T2284
Test name
Test status
Simulation time 1356837104 ps
CPU time 2.94 seconds
Started Jul 02 09:12:46 AM PDT 24
Finished Jul 02 09:12:50 AM PDT 24
Peak memory 206372 kb
Host smart-4f3f35b6-c468-4d51-89e5-ab1fa5507b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25269
57750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2526957750
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.575977858
Short name T1960
Test name
Test status
Simulation time 8470112937 ps
CPU time 16 seconds
Started Jul 02 09:12:55 AM PDT 24
Finished Jul 02 09:13:12 AM PDT 24
Peak memory 206468 kb
Host smart-6dee157c-080c-4e04-ab1e-0a0d0134e626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57597
7858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.575977858
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3364901671
Short name T717
Test name
Test status
Simulation time 424980920 ps
CPU time 1.33 seconds
Started Jul 02 09:12:39 AM PDT 24
Finished Jul 02 09:12:40 AM PDT 24
Peak memory 206116 kb
Host smart-0cbb983b-ab18-4841-873e-b18f6c0a30cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33649
01671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3364901671
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.901245858
Short name T46
Test name
Test status
Simulation time 143214289 ps
CPU time 0.73 seconds
Started Jul 02 09:12:48 AM PDT 24
Finished Jul 02 09:12:49 AM PDT 24
Peak memory 206212 kb
Host smart-9ceb5025-9d06-40d8-bc38-538447d0bc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90124
5858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.901245858
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1016415709
Short name T1016
Test name
Test status
Simulation time 30164163 ps
CPU time 0.64 seconds
Started Jul 02 09:12:37 AM PDT 24
Finished Jul 02 09:12:39 AM PDT 24
Peak memory 206164 kb
Host smart-a6674204-4094-4162-adf8-f3363a648988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10164
15709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1016415709
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.470766513
Short name T423
Test name
Test status
Simulation time 793544127 ps
CPU time 1.96 seconds
Started Jul 02 09:12:39 AM PDT 24
Finished Jul 02 09:12:41 AM PDT 24
Peak memory 206420 kb
Host smart-f2dfc0f5-c66c-4cde-90b6-9ef3a8801e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47076
6513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.470766513
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3891473393
Short name T816
Test name
Test status
Simulation time 162447196 ps
CPU time 1.33 seconds
Started Jul 02 09:12:39 AM PDT 24
Finished Jul 02 09:12:40 AM PDT 24
Peak memory 206360 kb
Host smart-f33cd121-4566-4146-897b-9c277cfa9ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38914
73393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3891473393
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1106898880
Short name T2094
Test name
Test status
Simulation time 226888989 ps
CPU time 0.91 seconds
Started Jul 02 09:12:48 AM PDT 24
Finished Jul 02 09:12:49 AM PDT 24
Peak memory 206344 kb
Host smart-a844e80d-56f8-4ab2-a50f-35b07bab4d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11068
98880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1106898880
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3831718917
Short name T719
Test name
Test status
Simulation time 142213912 ps
CPU time 0.75 seconds
Started Jul 02 09:12:54 AM PDT 24
Finished Jul 02 09:12:57 AM PDT 24
Peak memory 206200 kb
Host smart-3c1b18cc-93a0-4fdc-8728-1a8a175b743e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38317
18917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3831718917
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.72820231
Short name T2471
Test name
Test status
Simulation time 214678130 ps
CPU time 0.91 seconds
Started Jul 02 09:12:52 AM PDT 24
Finished Jul 02 09:12:54 AM PDT 24
Peak memory 206120 kb
Host smart-d04aef6a-0264-48b6-94a8-814344f51866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72820
231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.72820231
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1793815823
Short name T463
Test name
Test status
Simulation time 185640399 ps
CPU time 0.81 seconds
Started Jul 02 09:12:52 AM PDT 24
Finished Jul 02 09:12:54 AM PDT 24
Peak memory 206224 kb
Host smart-206b2588-51cd-4ee7-ad6a-76d64187dca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17938
15823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1793815823
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.508585652
Short name T2579
Test name
Test status
Simulation time 23335473920 ps
CPU time 21.38 seconds
Started Jul 02 09:12:54 AM PDT 24
Finished Jul 02 09:13:18 AM PDT 24
Peak memory 206264 kb
Host smart-b9af5c99-4421-47a8-ad13-01179f40da9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50858
5652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.508585652
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2390215878
Short name T1176
Test name
Test status
Simulation time 3328740226 ps
CPU time 3.78 seconds
Started Jul 02 09:12:45 AM PDT 24
Finished Jul 02 09:12:49 AM PDT 24
Peak memory 206220 kb
Host smart-f3a98099-7f50-4492-827f-4012eeae1618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23902
15878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2390215878
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.879734608
Short name T2562
Test name
Test status
Simulation time 8087025200 ps
CPU time 57.24 seconds
Started Jul 02 09:12:55 AM PDT 24
Finished Jul 02 09:13:54 AM PDT 24
Peak memory 206476 kb
Host smart-220d7060-83b4-4009-bbda-42c3777f521f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87973
4608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.879734608
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.1869040766
Short name T970
Test name
Test status
Simulation time 5478409112 ps
CPU time 152.8 seconds
Started Jul 02 09:12:58 AM PDT 24
Finished Jul 02 09:15:33 AM PDT 24
Peak memory 206448 kb
Host smart-0a70f16c-913f-4cad-a531-d3c78c9f213b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1869040766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.1869040766
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.932201456
Short name T2663
Test name
Test status
Simulation time 275412122 ps
CPU time 0.93 seconds
Started Jul 02 09:12:53 AM PDT 24
Finished Jul 02 09:12:56 AM PDT 24
Peak memory 206192 kb
Host smart-2d7c70d8-c5d7-4d85-abfc-c1397a9c8cb6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=932201456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.932201456
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.4454007
Short name T1049
Test name
Test status
Simulation time 190438536 ps
CPU time 0.9 seconds
Started Jul 02 09:12:59 AM PDT 24
Finished Jul 02 09:13:02 AM PDT 24
Peak memory 206220 kb
Host smart-9559adf0-1af3-4977-82f8-63b1c0763a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44540
07 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.4454007
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2532911111
Short name T460
Test name
Test status
Simulation time 4824078983 ps
CPU time 33.62 seconds
Started Jul 02 09:12:53 AM PDT 24
Finished Jul 02 09:13:28 AM PDT 24
Peak memory 206432 kb
Host smart-0b0fadb3-ec82-4bac-b30d-cc2bbd6926f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
11111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2532911111
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3299573739
Short name T2574
Test name
Test status
Simulation time 7046058354 ps
CPU time 46.52 seconds
Started Jul 02 09:12:54 AM PDT 24
Finished Jul 02 09:13:42 AM PDT 24
Peak memory 206444 kb
Host smart-d069ab5d-ac20-4c7e-88bb-934b7e88f398
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3299573739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3299573739
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1106867564
Short name T2569
Test name
Test status
Simulation time 183752287 ps
CPU time 0.84 seconds
Started Jul 02 09:13:00 AM PDT 24
Finished Jul 02 09:13:02 AM PDT 24
Peak memory 206152 kb
Host smart-bcfb3091-7f11-4c53-9faf-897d662ec0b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1106867564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1106867564
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1342714903
Short name T1311
Test name
Test status
Simulation time 148264293 ps
CPU time 0.8 seconds
Started Jul 02 09:12:55 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206144 kb
Host smart-1021e641-02cb-4804-9d1a-7185af8e3eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13427
14903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1342714903
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.4272497340
Short name T116
Test name
Test status
Simulation time 201752028 ps
CPU time 0.87 seconds
Started Jul 02 09:12:57 AM PDT 24
Finished Jul 02 09:12:59 AM PDT 24
Peak memory 206164 kb
Host smart-1caa890a-976b-4cfd-9352-770abcfa9515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42724
97340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.4272497340
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3178160301
Short name T416
Test name
Test status
Simulation time 157917959 ps
CPU time 0.84 seconds
Started Jul 02 09:12:55 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206208 kb
Host smart-17d3f034-da93-4e3f-93cc-098e22f91ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31781
60301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3178160301
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.582294734
Short name T1778
Test name
Test status
Simulation time 167212794 ps
CPU time 0.8 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206340 kb
Host smart-aea5a6fd-054b-4957-b858-23f2bd7032e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58229
4734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.582294734
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3164346025
Short name T1312
Test name
Test status
Simulation time 237488088 ps
CPU time 0.87 seconds
Started Jul 02 09:12:51 AM PDT 24
Finished Jul 02 09:12:53 AM PDT 24
Peak memory 206176 kb
Host smart-5eb8caa5-b3b1-49b4-a312-9d251fb0771d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31643
46025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3164346025
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.248537874
Short name T1462
Test name
Test status
Simulation time 162622836 ps
CPU time 0.77 seconds
Started Jul 02 09:12:55 AM PDT 24
Finished Jul 02 09:12:57 AM PDT 24
Peak memory 206188 kb
Host smart-3464288e-c82c-4647-89f3-fc24d7f103fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24853
7874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.248537874
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1503526498
Short name T915
Test name
Test status
Simulation time 223646086 ps
CPU time 0.97 seconds
Started Jul 02 09:12:53 AM PDT 24
Finished Jul 02 09:12:56 AM PDT 24
Peak memory 206164 kb
Host smart-c9b349a7-cf90-45ed-b90b-fafbeec1b819
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1503526498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1503526498
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2568231277
Short name T1485
Test name
Test status
Simulation time 166874143 ps
CPU time 0.8 seconds
Started Jul 02 09:12:52 AM PDT 24
Finished Jul 02 09:12:54 AM PDT 24
Peak memory 206184 kb
Host smart-675707a3-726a-4d0c-a089-40e62392c88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25682
31277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2568231277
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3147882727
Short name T2018
Test name
Test status
Simulation time 45753371 ps
CPU time 0.69 seconds
Started Jul 02 09:12:56 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206212 kb
Host smart-18d88f37-5c38-463b-86a4-a35cbb5418c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31478
82727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3147882727
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2316364074
Short name T94
Test name
Test status
Simulation time 23610908931 ps
CPU time 53.71 seconds
Started Jul 02 09:12:49 AM PDT 24
Finished Jul 02 09:13:43 AM PDT 24
Peak memory 206488 kb
Host smart-7516968e-c092-4de3-b071-efabd88f4513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
64074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2316364074
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1935020883
Short name T1898
Test name
Test status
Simulation time 158577674 ps
CPU time 0.8 seconds
Started Jul 02 09:12:56 AM PDT 24
Finished Jul 02 09:12:59 AM PDT 24
Peak memory 206200 kb
Host smart-423aef6b-7983-42ea-bcc3-fa957004e9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19350
20883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1935020883
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2383977073
Short name T2118
Test name
Test status
Simulation time 188312594 ps
CPU time 0.85 seconds
Started Jul 02 09:13:01 AM PDT 24
Finished Jul 02 09:13:03 AM PDT 24
Peak memory 206200 kb
Host smart-9a15a925-56fe-41d8-b952-e1834bb3c3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23839
77073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2383977073
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3658384484
Short name T2223
Test name
Test status
Simulation time 283875820 ps
CPU time 0.99 seconds
Started Jul 02 09:12:53 AM PDT 24
Finished Jul 02 09:12:56 AM PDT 24
Peak memory 206228 kb
Host smart-259c7737-4e6a-4cc2-9c12-1e75327f2d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36583
84484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3658384484
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.154283929
Short name T1498
Test name
Test status
Simulation time 192553703 ps
CPU time 0.87 seconds
Started Jul 02 09:12:50 AM PDT 24
Finished Jul 02 09:12:52 AM PDT 24
Peak memory 206184 kb
Host smart-f5419ed5-0bf2-4eca-900c-2e447fc2649f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15428
3929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.154283929
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3916681481
Short name T2381
Test name
Test status
Simulation time 215256583 ps
CPU time 0.88 seconds
Started Jul 02 09:12:48 AM PDT 24
Finished Jul 02 09:12:50 AM PDT 24
Peak memory 206212 kb
Host smart-fddd2427-90f9-415d-a774-fbad6c927dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39166
81481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3916681481
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.4265543137
Short name T699
Test name
Test status
Simulation time 184168428 ps
CPU time 0.86 seconds
Started Jul 02 09:12:51 AM PDT 24
Finished Jul 02 09:12:53 AM PDT 24
Peak memory 206180 kb
Host smart-1d602a18-3400-444f-98ed-118734b7257d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655
43137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.4265543137
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2741009322
Short name T1542
Test name
Test status
Simulation time 150760868 ps
CPU time 0.77 seconds
Started Jul 02 09:13:04 AM PDT 24
Finished Jul 02 09:13:06 AM PDT 24
Peak memory 206128 kb
Host smart-bbaea44d-b985-4d5d-8c45-6dcf12ecdc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27410
09322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2741009322
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3082428136
Short name T2238
Test name
Test status
Simulation time 215191306 ps
CPU time 0.95 seconds
Started Jul 02 09:12:48 AM PDT 24
Finished Jul 02 09:12:50 AM PDT 24
Peak memory 206180 kb
Host smart-d74415aa-448d-474d-bdc7-cb1ef70f5215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30824
28136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3082428136
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.2586039880
Short name T702
Test name
Test status
Simulation time 6418937487 ps
CPU time 58.22 seconds
Started Jul 02 09:12:54 AM PDT 24
Finished Jul 02 09:13:54 AM PDT 24
Peak memory 206480 kb
Host smart-5f294907-bad5-43f8-9f7b-85f361f34d91
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2586039880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.2586039880
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.767768553
Short name T2437
Test name
Test status
Simulation time 173535538 ps
CPU time 0.8 seconds
Started Jul 02 09:12:42 AM PDT 24
Finished Jul 02 09:12:44 AM PDT 24
Peak memory 206192 kb
Host smart-720fc71d-bd71-4a71-9a45-0fedf4c70217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76776
8553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.767768553
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2063418584
Short name T968
Test name
Test status
Simulation time 168992299 ps
CPU time 0.82 seconds
Started Jul 02 09:12:47 AM PDT 24
Finished Jul 02 09:12:55 AM PDT 24
Peak memory 206196 kb
Host smart-c47f8b7a-0051-42d5-9ec9-a73464c1cb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20634
18584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2063418584
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2626933945
Short name T1779
Test name
Test status
Simulation time 1197312998 ps
CPU time 2.6 seconds
Started Jul 02 09:12:49 AM PDT 24
Finished Jul 02 09:12:53 AM PDT 24
Peak memory 206440 kb
Host smart-3f9ffee4-ac18-4e4b-8ccb-443a3918224a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26269
33945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2626933945
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.421949049
Short name T2347
Test name
Test status
Simulation time 5213178248 ps
CPU time 146.42 seconds
Started Jul 02 09:12:48 AM PDT 24
Finished Jul 02 09:15:16 AM PDT 24
Peak memory 206536 kb
Host smart-20ed4ee5-60a1-477a-92e1-c03733500504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42194
9049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.421949049
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.1549039280
Short name T461
Test name
Test status
Simulation time 54096492 ps
CPU time 0.68 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:04 AM PDT 24
Peak memory 206172 kb
Host smart-9f98c0ad-d7bc-4bae-b6f2-0fc342b10f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1549039280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.1549039280
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2964239097
Short name T1478
Test name
Test status
Simulation time 3921300754 ps
CPU time 4.44 seconds
Started Jul 02 09:13:03 AM PDT 24
Finished Jul 02 09:13:09 AM PDT 24
Peak memory 206260 kb
Host smart-c7db63e9-2873-42c9-9172-d973992d290f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2964239097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.2964239097
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2742345517
Short name T786
Test name
Test status
Simulation time 13379175307 ps
CPU time 15.1 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:22 AM PDT 24
Peak memory 206216 kb
Host smart-7a1d047e-d9d3-4d2b-a8b2-b4ca2ea8c2b0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2742345517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2742345517
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1473843424
Short name T2504
Test name
Test status
Simulation time 23436420723 ps
CPU time 24.63 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:28 AM PDT 24
Peak memory 206248 kb
Host smart-8a4d25c7-da9f-4acc-920c-70d4c7af15a5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1473843424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1473843424
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1883537718
Short name T1079
Test name
Test status
Simulation time 196846750 ps
CPU time 0.86 seconds
Started Jul 02 09:12:58 AM PDT 24
Finished Jul 02 09:13:01 AM PDT 24
Peak memory 206212 kb
Host smart-b1861e9e-b20f-485c-a669-52d5043a1571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18835
37718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1883537718
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2000931100
Short name T1276
Test name
Test status
Simulation time 184129132 ps
CPU time 0.77 seconds
Started Jul 02 09:13:03 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206200 kb
Host smart-9a7fcdac-a5be-4cca-8c8b-474dfa3a8e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20009
31100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2000931100
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.1668019400
Short name T2023
Test name
Test status
Simulation time 136630704 ps
CPU time 0.76 seconds
Started Jul 02 09:12:59 AM PDT 24
Finished Jul 02 09:13:01 AM PDT 24
Peak memory 206188 kb
Host smart-8927eb7c-2890-4e60-9dcc-1cbf37368b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16680
19400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.1668019400
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3002871047
Short name T1958
Test name
Test status
Simulation time 1121211759 ps
CPU time 2.59 seconds
Started Jul 02 09:12:56 AM PDT 24
Finished Jul 02 09:13:01 AM PDT 24
Peak memory 206408 kb
Host smart-bdac4639-17d8-4ba6-9007-cf322fe32780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30028
71047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3002871047
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.2390107178
Short name T1486
Test name
Test status
Simulation time 11434664306 ps
CPU time 22.52 seconds
Started Jul 02 09:13:01 AM PDT 24
Finished Jul 02 09:13:25 AM PDT 24
Peak memory 206404 kb
Host smart-a9c12b4b-c404-4967-8987-bbd10807f4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23901
07178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.2390107178
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.656420061
Short name T1034
Test name
Test status
Simulation time 483743581 ps
CPU time 1.4 seconds
Started Jul 02 09:12:56 AM PDT 24
Finished Jul 02 09:12:59 AM PDT 24
Peak memory 206216 kb
Host smart-aee47748-2759-4809-ac11-82d0ef88fb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65642
0061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.656420061
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2988190742
Short name T2058
Test name
Test status
Simulation time 139586593 ps
CPU time 0.75 seconds
Started Jul 02 09:13:01 AM PDT 24
Finished Jul 02 09:13:03 AM PDT 24
Peak memory 206208 kb
Host smart-200d7d44-99dd-4aa9-99c3-96ba74d22589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
90742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2988190742
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3411171117
Short name T1587
Test name
Test status
Simulation time 35943025 ps
CPU time 0.7 seconds
Started Jul 02 09:12:59 AM PDT 24
Finished Jul 02 09:13:01 AM PDT 24
Peak memory 206192 kb
Host smart-b6ad1f92-5ce8-4cfc-8c5f-37f9588debfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34111
71117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3411171117
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.144459239
Short name T2625
Test name
Test status
Simulation time 797542782 ps
CPU time 1.96 seconds
Started Jul 02 09:13:00 AM PDT 24
Finished Jul 02 09:13:04 AM PDT 24
Peak memory 206460 kb
Host smart-1688fe1e-ea65-4953-b515-81c359c3b515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14445
9239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.144459239
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1739482323
Short name T445
Test name
Test status
Simulation time 268647846 ps
CPU time 1.76 seconds
Started Jul 02 09:13:07 AM PDT 24
Finished Jul 02 09:13:12 AM PDT 24
Peak memory 206440 kb
Host smart-0bd4d4de-7f05-4e4c-9520-be06e4bc7c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17394
82323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1739482323
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.540191117
Short name T492
Test name
Test status
Simulation time 218906197 ps
CPU time 0.93 seconds
Started Jul 02 09:13:00 AM PDT 24
Finished Jul 02 09:13:02 AM PDT 24
Peak memory 206224 kb
Host smart-e58beb63-5e1f-4fcd-89d0-7a7a268cc095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54019
1117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.540191117
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.4256266833
Short name T1169
Test name
Test status
Simulation time 147906469 ps
CPU time 0.85 seconds
Started Jul 02 09:13:03 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206180 kb
Host smart-afe87d7d-eb1a-4548-a4cc-e13b1ce46375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42562
66833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.4256266833
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.4075165470
Short name T1954
Test name
Test status
Simulation time 230739563 ps
CPU time 0.87 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:12 AM PDT 24
Peak memory 206212 kb
Host smart-fce167d4-a0d9-42af-9ad5-8faf023e7560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40751
65470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.4075165470
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.278144271
Short name T2331
Test name
Test status
Simulation time 9244582103 ps
CPU time 265.26 seconds
Started Jul 02 09:12:53 AM PDT 24
Finished Jul 02 09:17:21 AM PDT 24
Peak memory 206488 kb
Host smart-549b896d-9223-4f74-ae30-ad8ea64f0252
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=278144271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.278144271
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3430956721
Short name T737
Test name
Test status
Simulation time 206372526 ps
CPU time 0.91 seconds
Started Jul 02 09:12:58 AM PDT 24
Finished Jul 02 09:13:01 AM PDT 24
Peak memory 206184 kb
Host smart-c698691d-b632-477c-b6ee-32252980911c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34309
56721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3430956721
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.2142412402
Short name T980
Test name
Test status
Simulation time 23288306007 ps
CPU time 23.26 seconds
Started Jul 02 09:12:56 AM PDT 24
Finished Jul 02 09:13:21 AM PDT 24
Peak memory 206276 kb
Host smart-93872fdb-4be3-4542-8ec0-163d9d8d87af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21424
12402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.2142412402
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.475268492
Short name T847
Test name
Test status
Simulation time 3316637845 ps
CPU time 4.43 seconds
Started Jul 02 09:12:48 AM PDT 24
Finished Jul 02 09:12:53 AM PDT 24
Peak memory 206284 kb
Host smart-f6320bb4-9b60-4e91-8bf9-48b561b325f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47526
8492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.475268492
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.2133512364
Short name T2320
Test name
Test status
Simulation time 9612633930 ps
CPU time 261.43 seconds
Started Jul 02 09:12:54 AM PDT 24
Finished Jul 02 09:17:17 AM PDT 24
Peak memory 206544 kb
Host smart-b37ad19a-a132-43b2-b3ef-a0be530e4944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21335
12364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2133512364
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2873572811
Short name T2135
Test name
Test status
Simulation time 4066150854 ps
CPU time 31.04 seconds
Started Jul 02 09:12:55 AM PDT 24
Finished Jul 02 09:13:27 AM PDT 24
Peak memory 206460 kb
Host smart-b77c2688-64bf-4d41-a352-e7782edef50c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2873572811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2873572811
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.2070881003
Short name T1035
Test name
Test status
Simulation time 239295331 ps
CPU time 0.88 seconds
Started Jul 02 09:12:55 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206196 kb
Host smart-3c2afb4d-a8b6-462c-9c27-ccfc1bef4b5e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2070881003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.2070881003
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.496622877
Short name T1768
Test name
Test status
Simulation time 217892978 ps
CPU time 0.88 seconds
Started Jul 02 09:12:53 AM PDT 24
Finished Jul 02 09:13:00 AM PDT 24
Peak memory 206188 kb
Host smart-7d42195e-fb10-48bf-920e-655d9b85665a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49662
2877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.496622877
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.563927763
Short name T1537
Test name
Test status
Simulation time 3155422702 ps
CPU time 27.62 seconds
Started Jul 02 09:13:00 AM PDT 24
Finished Jul 02 09:13:29 AM PDT 24
Peak memory 206472 kb
Host smart-6192a5af-a7f1-4fff-8890-1310eb4d7e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56392
7763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.563927763
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3689529307
Short name T2509
Test name
Test status
Simulation time 2967053181 ps
CPU time 85.28 seconds
Started Jul 02 09:12:56 AM PDT 24
Finished Jul 02 09:14:23 AM PDT 24
Peak memory 206504 kb
Host smart-0889b9a6-1426-4a1d-856d-9b32243b0ab5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3689529307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3689529307
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.4235606245
Short name T710
Test name
Test status
Simulation time 155032887 ps
CPU time 0.78 seconds
Started Jul 02 09:12:58 AM PDT 24
Finished Jul 02 09:13:01 AM PDT 24
Peak memory 206200 kb
Host smart-ef66a671-400f-4bd7-a8d6-66428f1826e7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4235606245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.4235606245
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2071666734
Short name T587
Test name
Test status
Simulation time 148921418 ps
CPU time 0.77 seconds
Started Jul 02 09:12:57 AM PDT 24
Finished Jul 02 09:13:00 AM PDT 24
Peak memory 206208 kb
Host smart-ed3e7d26-43b3-47f7-917f-1b7776f49de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20716
66734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2071666734
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.658841244
Short name T2006
Test name
Test status
Simulation time 219988895 ps
CPU time 0.99 seconds
Started Jul 02 09:13:07 AM PDT 24
Finished Jul 02 09:13:10 AM PDT 24
Peak memory 206224 kb
Host smart-b4def01d-cd74-49e8-80ab-e1b0d5f47878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65884
1244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.658841244
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.741247553
Short name T419
Test name
Test status
Simulation time 210648724 ps
CPU time 0.85 seconds
Started Jul 02 09:12:56 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206392 kb
Host smart-34db7f4f-6790-485b-af47-0bb8fa3a28cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74124
7553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.741247553
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1124407242
Short name T2072
Test name
Test status
Simulation time 174145456 ps
CPU time 0.81 seconds
Started Jul 02 09:12:57 AM PDT 24
Finished Jul 02 09:13:00 AM PDT 24
Peak memory 206192 kb
Host smart-c5e7d2f3-c390-4780-a3c9-e85b1882539b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11244
07242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1124407242
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.528805257
Short name T525
Test name
Test status
Simulation time 175771305 ps
CPU time 0.83 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206224 kb
Host smart-5b8197f4-e0b1-4358-b76f-cc4612f96d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52880
5257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.528805257
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.849609058
Short name T906
Test name
Test status
Simulation time 162521039 ps
CPU time 0.85 seconds
Started Jul 02 09:13:06 AM PDT 24
Finished Jul 02 09:13:09 AM PDT 24
Peak memory 206212 kb
Host smart-2870f068-d790-4864-a082-13b3997e2d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84960
9058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.849609058
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.4011601565
Short name T969
Test name
Test status
Simulation time 242915233 ps
CPU time 1.01 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:08 AM PDT 24
Peak memory 206184 kb
Host smart-aefb5832-e494-4896-bc70-ce7c9f8a3f89
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4011601565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.4011601565
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.651643508
Short name T208
Test name
Test status
Simulation time 142732623 ps
CPU time 0.73 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206208 kb
Host smart-27d9e28b-a1b9-4042-9392-f741aff878ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65164
3508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.651643508
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1177699653
Short name T1980
Test name
Test status
Simulation time 38380082 ps
CPU time 0.64 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:12 AM PDT 24
Peak memory 206124 kb
Host smart-3c1f6268-8b6a-4f24-a02e-fc485c8e8a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11776
99653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1177699653
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.336328814
Short name T1961
Test name
Test status
Simulation time 8103795682 ps
CPU time 18.28 seconds
Started Jul 02 09:12:55 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206400 kb
Host smart-b7d6e2c3-497a-4701-9c6b-3d393a219987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33632
8814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.336328814
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1533492258
Short name T559
Test name
Test status
Simulation time 201795328 ps
CPU time 0.91 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:08 AM PDT 24
Peak memory 206220 kb
Host smart-e821d45c-b1e5-4832-a5d3-f6e3763ae383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15334
92258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1533492258
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1208280781
Short name T1706
Test name
Test status
Simulation time 240343205 ps
CPU time 0.92 seconds
Started Jul 02 09:13:01 AM PDT 24
Finished Jul 02 09:13:03 AM PDT 24
Peak memory 206180 kb
Host smart-f41a9050-e198-4242-91ec-d4c4819efb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12082
80781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1208280781
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.3064854394
Short name T2450
Test name
Test status
Simulation time 228001775 ps
CPU time 0.86 seconds
Started Jul 02 09:12:55 AM PDT 24
Finished Jul 02 09:12:58 AM PDT 24
Peak memory 206192 kb
Host smart-cfd659aa-9b44-4413-ab87-3e44de7698d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30648
54394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.3064854394
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3200868666
Short name T1342
Test name
Test status
Simulation time 184111221 ps
CPU time 0.81 seconds
Started Jul 02 09:13:00 AM PDT 24
Finished Jul 02 09:13:02 AM PDT 24
Peak memory 206164 kb
Host smart-56c72b31-4ac1-4124-8373-e94f2fb76e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32008
68666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3200868666
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1358654314
Short name T2225
Test name
Test status
Simulation time 146329293 ps
CPU time 0.78 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:07 AM PDT 24
Peak memory 206192 kb
Host smart-137dd1dd-2d4d-4197-8e64-d3f8ef27a17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13586
54314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1358654314
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1989465554
Short name T1439
Test name
Test status
Simulation time 142841624 ps
CPU time 0.78 seconds
Started Jul 02 09:12:58 AM PDT 24
Finished Jul 02 09:13:01 AM PDT 24
Peak memory 206172 kb
Host smart-faec79ab-b2cc-4b7e-9722-c5cadf3fbf9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19894
65554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1989465554
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1822643414
Short name T2137
Test name
Test status
Simulation time 161247808 ps
CPU time 0.79 seconds
Started Jul 02 09:13:03 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206224 kb
Host smart-45179f6d-56c9-4ec1-8b23-ccd45aeeae66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18226
43414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1822643414
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3759986094
Short name T155
Test name
Test status
Simulation time 184697144 ps
CPU time 0.88 seconds
Started Jul 02 09:12:59 AM PDT 24
Finished Jul 02 09:13:01 AM PDT 24
Peak memory 206208 kb
Host smart-da6ebd49-c3f1-42e3-a385-bf3fb39811fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37599
86094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3759986094
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.1547530525
Short name T1237
Test name
Test status
Simulation time 4755522661 ps
CPU time 130.35 seconds
Started Jul 02 09:13:06 AM PDT 24
Finished Jul 02 09:15:18 AM PDT 24
Peak memory 206508 kb
Host smart-c6fe2eac-2294-4482-b1e5-de884e51cebb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1547530525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.1547530525
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1655848786
Short name T2017
Test name
Test status
Simulation time 181415357 ps
CPU time 0.82 seconds
Started Jul 02 09:12:57 AM PDT 24
Finished Jul 02 09:12:59 AM PDT 24
Peak memory 206124 kb
Host smart-1c880c5a-1f42-4ff0-8f30-79253b7caf08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16558
48786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1655848786
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.4270017639
Short name T422
Test name
Test status
Simulation time 156930041 ps
CPU time 0.78 seconds
Started Jul 02 09:13:04 AM PDT 24
Finished Jul 02 09:13:06 AM PDT 24
Peak memory 206124 kb
Host smart-89b673eb-3b00-4335-94a8-d477f4891c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42700
17639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.4270017639
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1796304396
Short name T827
Test name
Test status
Simulation time 1094808067 ps
CPU time 2.6 seconds
Started Jul 02 09:12:56 AM PDT 24
Finished Jul 02 09:13:00 AM PDT 24
Peak memory 206468 kb
Host smart-685bce1b-9e19-419d-9d59-becf33922607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963
04396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1796304396
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1834436394
Short name T605
Test name
Test status
Simulation time 4783374763 ps
CPU time 44.52 seconds
Started Jul 02 09:13:07 AM PDT 24
Finished Jul 02 09:13:55 AM PDT 24
Peak memory 206440 kb
Host smart-f1ebcc34-8662-46ff-bb7a-8f407a082912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18344
36394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1834436394
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.1459865854
Short name T1884
Test name
Test status
Simulation time 41198914 ps
CPU time 0.69 seconds
Started Jul 02 09:13:03 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206244 kb
Host smart-461d4baa-b2f3-4626-9d4a-434c338a42a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1459865854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.1459865854
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3821939679
Short name T2321
Test name
Test status
Simulation time 3985901323 ps
CPU time 4.85 seconds
Started Jul 02 09:13:00 AM PDT 24
Finished Jul 02 09:13:07 AM PDT 24
Peak memory 206424 kb
Host smart-64112647-e2bb-417d-af53-b05976994690
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3821939679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3821939679
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.996621411
Short name T1263
Test name
Test status
Simulation time 13396263321 ps
CPU time 12.6 seconds
Started Jul 02 09:13:01 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206228 kb
Host smart-2b0657e6-d98f-47cd-8e85-ed2f8d55b48d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=996621411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.996621411
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3690522709
Short name T534
Test name
Test status
Simulation time 23329323181 ps
CPU time 24.07 seconds
Started Jul 02 09:12:56 AM PDT 24
Finished Jul 02 09:13:22 AM PDT 24
Peak memory 206248 kb
Host smart-b47f5e80-b286-469e-94b1-5740e6882b87
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3690522709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3690522709
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.187270589
Short name T1286
Test name
Test status
Simulation time 156856160 ps
CPU time 0.8 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:08 AM PDT 24
Peak memory 206172 kb
Host smart-6360b107-f1c2-4181-8ceb-e1211ed82597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18727
0589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.187270589
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.4083582023
Short name T1184
Test name
Test status
Simulation time 164365994 ps
CPU time 0.9 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:08 AM PDT 24
Peak memory 206188 kb
Host smart-dd55ae20-8e08-4027-8e7b-c5dcf26457d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40835
82023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4083582023
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2862251394
Short name T365
Test name
Test status
Simulation time 344365674 ps
CPU time 1.15 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206048 kb
Host smart-b2afed77-1c4e-4a27-9c43-18a6b28efef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28622
51394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2862251394
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1359390145
Short name T2029
Test name
Test status
Simulation time 746752411 ps
CPU time 1.76 seconds
Started Jul 02 09:13:03 AM PDT 24
Finished Jul 02 09:13:07 AM PDT 24
Peak memory 206412 kb
Host smart-21030eb5-39ef-4ea9-b895-77da15ff1ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13593
90145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1359390145
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.337528091
Short name T1207
Test name
Test status
Simulation time 20256827324 ps
CPU time 36.11 seconds
Started Jul 02 09:13:10 AM PDT 24
Finished Jul 02 09:13:51 AM PDT 24
Peak memory 206496 kb
Host smart-8c23c386-39af-4fe9-9988-ee573f3d588e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33752
8091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.337528091
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.83653428
Short name T529
Test name
Test status
Simulation time 427840013 ps
CPU time 1.31 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:17 AM PDT 24
Peak memory 206056 kb
Host smart-7c9d2a2f-9ae0-4fa5-8a4e-8650fc731e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83653
428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.83653428
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1724650236
Short name T1471
Test name
Test status
Simulation time 187034706 ps
CPU time 0.81 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:04 AM PDT 24
Peak memory 206200 kb
Host smart-d0e3e629-b1bd-4c8d-a9c1-3b6f8c5b0969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17246
50236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1724650236
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1577754651
Short name T643
Test name
Test status
Simulation time 46931652 ps
CPU time 0.71 seconds
Started Jul 02 09:13:07 AM PDT 24
Finished Jul 02 09:13:10 AM PDT 24
Peak memory 206184 kb
Host smart-cfe93ec3-2cfc-4ca6-be46-b12b376e36dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15777
54651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1577754651
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3992064758
Short name T1904
Test name
Test status
Simulation time 891461087 ps
CPU time 2.11 seconds
Started Jul 02 09:13:12 AM PDT 24
Finished Jul 02 09:13:19 AM PDT 24
Peak memory 206380 kb
Host smart-da355dbf-e45b-4d6f-9faa-3b19dc689c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39920
64758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3992064758
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2581880359
Short name T631
Test name
Test status
Simulation time 233924826 ps
CPU time 1.25 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:13 AM PDT 24
Peak memory 206400 kb
Host smart-a37d143f-8119-4e8f-a4b6-95a216941442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25818
80359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2581880359
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3150584498
Short name T2150
Test name
Test status
Simulation time 206403309 ps
CPU time 0.87 seconds
Started Jul 02 09:13:04 AM PDT 24
Finished Jul 02 09:13:07 AM PDT 24
Peak memory 206188 kb
Host smart-b5ca15f4-1d53-4f3a-9223-f47b0bddf3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31505
84498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3150584498
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.396076156
Short name T1816
Test name
Test status
Simulation time 134340212 ps
CPU time 0.77 seconds
Started Jul 02 09:13:12 AM PDT 24
Finished Jul 02 09:13:18 AM PDT 24
Peak memory 206368 kb
Host smart-0f47be7f-2abd-4e3c-ac0b-642e34b94be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607
6156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.396076156
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1029323354
Short name T604
Test name
Test status
Simulation time 249295348 ps
CPU time 0.95 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:07 AM PDT 24
Peak memory 206196 kb
Host smart-5facf110-af17-4f67-92d1-6e24cf0a4041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10293
23354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1029323354
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3467424130
Short name T658
Test name
Test status
Simulation time 232131822 ps
CPU time 0.93 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:14 AM PDT 24
Peak memory 206128 kb
Host smart-401b9ec2-2c43-42cf-8ab6-09895b06b875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34674
24130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3467424130
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.4207771202
Short name T1941
Test name
Test status
Simulation time 23289854063 ps
CPU time 29.66 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:43 AM PDT 24
Peak memory 206188 kb
Host smart-3c72590d-207c-4f36-a8dd-fcd90e4bbae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42077
71202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.4207771202
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1137346006
Short name T2145
Test name
Test status
Simulation time 3324217989 ps
CPU time 4.11 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:11 AM PDT 24
Peak memory 206284 kb
Host smart-f9edb9e9-9700-46df-a396-0deac37b4ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11373
46006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1137346006
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1796548667
Short name T1358
Test name
Test status
Simulation time 9546837221 ps
CPU time 94.04 seconds
Started Jul 02 09:13:00 AM PDT 24
Finished Jul 02 09:14:35 AM PDT 24
Peak memory 206540 kb
Host smart-71e2fcea-098c-4c3c-bf05-df09730c1c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17965
48667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1796548667
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2913419475
Short name T6
Test name
Test status
Simulation time 4460465573 ps
CPU time 33.38 seconds
Started Jul 02 09:13:00 AM PDT 24
Finished Jul 02 09:13:35 AM PDT 24
Peak memory 206444 kb
Host smart-0b198e89-c462-457b-ae85-1b9f5e9dfc5c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2913419475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2913419475
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3524043066
Short name T1614
Test name
Test status
Simulation time 233248875 ps
CPU time 0.89 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:12 AM PDT 24
Peak memory 206180 kb
Host smart-c5badbd7-8a05-4a98-81b2-ef7e905a2177
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3524043066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3524043066
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1017427628
Short name T1082
Test name
Test status
Simulation time 185858366 ps
CPU time 0.9 seconds
Started Jul 02 09:12:56 AM PDT 24
Finished Jul 02 09:12:59 AM PDT 24
Peak memory 206132 kb
Host smart-c247d5af-b14e-48b3-a9dd-6182c4b4e948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10174
27628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1017427628
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.683287310
Short name T905
Test name
Test status
Simulation time 3875208366 ps
CPU time 26.52 seconds
Started Jul 02 09:13:10 AM PDT 24
Finished Jul 02 09:13:41 AM PDT 24
Peak memory 206460 kb
Host smart-1baab6c9-b127-4304-956b-2c1ef2b3832a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68328
7310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.683287310
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.3495653814
Short name T2395
Test name
Test status
Simulation time 3791378379 ps
CPU time 105.11 seconds
Started Jul 02 09:12:57 AM PDT 24
Finished Jul 02 09:14:44 AM PDT 24
Peak memory 206448 kb
Host smart-556ff0e5-d2d9-4b66-aca6-c975cf06a52a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3495653814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.3495653814
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.975970993
Short name T1888
Test name
Test status
Simulation time 164195758 ps
CPU time 0.83 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:04 AM PDT 24
Peak memory 206108 kb
Host smart-0500da75-be90-42ae-89c7-acac49738b32
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=975970993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.975970993
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3581960688
Short name T2074
Test name
Test status
Simulation time 152309666 ps
CPU time 0.76 seconds
Started Jul 02 09:13:06 AM PDT 24
Finished Jul 02 09:13:09 AM PDT 24
Peak memory 206220 kb
Host smart-9192e86e-5cd4-4a05-b2c9-b42530937a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35819
60688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3581960688
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.820047443
Short name T2021
Test name
Test status
Simulation time 207874081 ps
CPU time 0.88 seconds
Started Jul 02 09:13:12 AM PDT 24
Finished Jul 02 09:13:19 AM PDT 24
Peak memory 206176 kb
Host smart-25213e1b-d00e-40e7-9ab2-a1cf6706124d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82004
7443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.820047443
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3130952641
Short name T1070
Test name
Test status
Simulation time 171995452 ps
CPU time 0.8 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:18 AM PDT 24
Peak memory 205988 kb
Host smart-fcd2e1bf-de67-458f-aadd-3ea8adefb1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31309
52641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3130952641
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3755175857
Short name T1720
Test name
Test status
Simulation time 179452274 ps
CPU time 0.83 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:13 AM PDT 24
Peak memory 206200 kb
Host smart-b1ea1bfc-262c-4f2e-8c87-ecadd567823e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37551
75857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3755175857
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2912161390
Short name T105
Test name
Test status
Simulation time 152985881 ps
CPU time 0.77 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:18 AM PDT 24
Peak memory 206024 kb
Host smart-1e6ed7ea-d85a-402c-aedb-3c4e0f4cba0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29121
61390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2912161390
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2370531088
Short name T1988
Test name
Test status
Simulation time 179381059 ps
CPU time 0.78 seconds
Started Jul 02 09:13:06 AM PDT 24
Finished Jul 02 09:13:09 AM PDT 24
Peak memory 206160 kb
Host smart-56b43e8e-3314-48f8-ad19-14c8906e6607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23705
31088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2370531088
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.2779596415
Short name T576
Test name
Test status
Simulation time 221538261 ps
CPU time 0.97 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:07 AM PDT 24
Peak memory 206160 kb
Host smart-5c9dad3f-fa87-41f7-aa7c-1c238fcc6562
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2779596415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.2779596415
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.847166524
Short name T778
Test name
Test status
Simulation time 150470549 ps
CPU time 0.77 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206216 kb
Host smart-3c93905e-5a42-4308-a27d-e9bde79c4608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84716
6524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.847166524
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.70385105
Short name T2124
Test name
Test status
Simulation time 53543472 ps
CPU time 0.69 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206176 kb
Host smart-80e4e0f7-2b57-4542-895c-cb3ffb42861d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70385
105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.70385105
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.499223675
Short name T2252
Test name
Test status
Simulation time 9895834138 ps
CPU time 21.17 seconds
Started Jul 02 09:13:12 AM PDT 24
Finished Jul 02 09:13:39 AM PDT 24
Peak memory 206348 kb
Host smart-72c3eb39-3c01-465f-a1f6-9774ac8bce73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49922
3675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.499223675
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2437180784
Short name T2583
Test name
Test status
Simulation time 160522566 ps
CPU time 0.81 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206188 kb
Host smart-66580f87-15ad-4082-9b85-80f4c5c213b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24371
80784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2437180784
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1171969027
Short name T2035
Test name
Test status
Simulation time 191762839 ps
CPU time 0.87 seconds
Started Jul 02 09:13:03 AM PDT 24
Finished Jul 02 09:13:06 AM PDT 24
Peak memory 206172 kb
Host smart-7d868c72-46a3-411f-870b-0999bdfd2b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11719
69027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1171969027
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.338785072
Short name T1792
Test name
Test status
Simulation time 180104215 ps
CPU time 0.85 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:17 AM PDT 24
Peak memory 206180 kb
Host smart-44dd9da5-03b8-4951-a0ca-c67398a4c1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33878
5072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.338785072
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3147626616
Short name T2322
Test name
Test status
Simulation time 246572308 ps
CPU time 0.86 seconds
Started Jul 02 09:13:07 AM PDT 24
Finished Jul 02 09:13:10 AM PDT 24
Peak memory 206220 kb
Host smart-27faa392-e06d-4deb-8712-b7ffdbefbb83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31476
26616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3147626616
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1173087848
Short name T1279
Test name
Test status
Simulation time 145210039 ps
CPU time 0.82 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206192 kb
Host smart-d48feacc-8946-4926-86b5-67ae0a16b0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11730
87848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1173087848
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1608112769
Short name T1086
Test name
Test status
Simulation time 169590981 ps
CPU time 0.8 seconds
Started Jul 02 09:13:10 AM PDT 24
Finished Jul 02 09:13:16 AM PDT 24
Peak memory 206192 kb
Host smart-2b9f38c4-61c9-4c6f-8342-9022c2e86b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16081
12769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1608112769
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2292835982
Short name T700
Test name
Test status
Simulation time 145997530 ps
CPU time 0.76 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:18 AM PDT 24
Peak memory 206048 kb
Host smart-3dcc818a-9e0f-44d7-bccb-f7673b868573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22928
35982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2292835982
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1031700890
Short name T2177
Test name
Test status
Simulation time 228570357 ps
CPU time 0.93 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:14 AM PDT 24
Peak memory 206208 kb
Host smart-37d8fbbc-ee8d-4ce3-8695-45d9e7de6313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10317
00890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1031700890
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.952999150
Short name T163
Test name
Test status
Simulation time 5911669959 ps
CPU time 56.4 seconds
Started Jul 02 09:13:04 AM PDT 24
Finished Jul 02 09:14:02 AM PDT 24
Peak memory 206508 kb
Host smart-ccf4e388-41cb-4def-ae4d-670dff3f1901
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=952999150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.952999150
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2506629275
Short name T2198
Test name
Test status
Simulation time 174803667 ps
CPU time 0.82 seconds
Started Jul 02 09:13:12 AM PDT 24
Finished Jul 02 09:13:18 AM PDT 24
Peak memory 206388 kb
Host smart-06023dfd-6587-4361-8bb5-afe4c566390a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25066
29275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2506629275
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.4136627377
Short name T501
Test name
Test status
Simulation time 203821518 ps
CPU time 0.84 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206188 kb
Host smart-abbb513a-e01d-485e-b5c6-d19e8b76d334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41366
27377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.4136627377
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.4288421599
Short name T253
Test name
Test status
Simulation time 748491046 ps
CPU time 1.76 seconds
Started Jul 02 09:13:04 AM PDT 24
Finished Jul 02 09:13:08 AM PDT 24
Peak memory 206388 kb
Host smart-019fb59f-527f-4c21-927c-447437c141af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42884
21599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.4288421599
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.4243769221
Short name T2269
Test name
Test status
Simulation time 4296582848 ps
CPU time 39.02 seconds
Started Jul 02 09:13:12 AM PDT 24
Finished Jul 02 09:13:56 AM PDT 24
Peak memory 206268 kb
Host smart-0e3124c4-9f6f-473b-a963-e0b07265c070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42437
69221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.4243769221
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.1150526120
Short name T890
Test name
Test status
Simulation time 40971678 ps
CPU time 0.68 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:12 AM PDT 24
Peak memory 206216 kb
Host smart-38193203-b71e-4034-b338-e72c0dd19fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1150526120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1150526120
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.587698863
Short name T2154
Test name
Test status
Simulation time 4033676993 ps
CPU time 4.63 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:21 AM PDT 24
Peak memory 206056 kb
Host smart-05463ff6-4389-4ac3-b77c-e30ce7e45efa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=587698863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.587698863
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3100916697
Short name T1270
Test name
Test status
Simulation time 13373124966 ps
CPU time 15.66 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:32 AM PDT 24
Peak memory 206032 kb
Host smart-8ec0f2ec-1df4-49d6-aaab-d1fc18ea6956
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3100916697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3100916697
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.760975420
Short name T248
Test name
Test status
Simulation time 23414787562 ps
CPU time 28.61 seconds
Started Jul 02 09:13:06 AM PDT 24
Finished Jul 02 09:13:36 AM PDT 24
Peak memory 206436 kb
Host smart-aa070cbf-098f-4ba2-a55a-1041b54af177
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=760975420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.760975420
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.513258808
Short name T2328
Test name
Test status
Simulation time 182991197 ps
CPU time 0.85 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:08 AM PDT 24
Peak memory 206176 kb
Host smart-1d666f0f-90b9-4471-bb97-38df610bc64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51325
8808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.513258808
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.3223763767
Short name T2429
Test name
Test status
Simulation time 162074249 ps
CPU time 0.84 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:05 AM PDT 24
Peak memory 206204 kb
Host smart-fbf36bd9-ac27-48f0-b8c4-61b22f5ea3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32237
63767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.3223763767
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.119689711
Short name T2330
Test name
Test status
Simulation time 472390489 ps
CPU time 1.43 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:13 AM PDT 24
Peak memory 206400 kb
Host smart-999eea6b-cb43-4567-afcc-19208ab6e0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11968
9711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.119689711
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.509820871
Short name T166
Test name
Test status
Simulation time 892824335 ps
CPU time 2.04 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:06 AM PDT 24
Peak memory 206368 kb
Host smart-a85339a0-6942-4155-b8d2-1c4075de9fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50982
0871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.509820871
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.2217691600
Short name T1119
Test name
Test status
Simulation time 493383502 ps
CPU time 1.36 seconds
Started Jul 02 09:13:10 AM PDT 24
Finished Jul 02 09:13:17 AM PDT 24
Peak memory 206052 kb
Host smart-5fb73482-88e4-4752-a7b3-cce0fb0d5baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22176
91600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.2217691600
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2669917119
Short name T2329
Test name
Test status
Simulation time 161773166 ps
CPU time 0.89 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:12 AM PDT 24
Peak memory 206212 kb
Host smart-a2b8ab99-62f0-4dd9-8f4e-945aa71b4e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26699
17119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2669917119
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.675560342
Short name T642
Test name
Test status
Simulation time 33429479 ps
CPU time 0.67 seconds
Started Jul 02 09:13:13 AM PDT 24
Finished Jul 02 09:13:19 AM PDT 24
Peak memory 206048 kb
Host smart-ff3e9d51-0009-49b6-9b39-d9615c88e696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67556
0342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.675560342
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3279775202
Short name T660
Test name
Test status
Simulation time 967201379 ps
CPU time 2.66 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206392 kb
Host smart-046e87e6-5828-45cd-99ba-60c3daaba921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32797
75202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3279775202
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3777752132
Short name T2089
Test name
Test status
Simulation time 317658006 ps
CPU time 1.96 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:09 AM PDT 24
Peak memory 206416 kb
Host smart-2494e375-7369-4ce0-8488-4b0bb4915567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37777
52132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3777752132
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3266839995
Short name T2256
Test name
Test status
Simulation time 248574510 ps
CPU time 0.88 seconds
Started Jul 02 09:13:06 AM PDT 24
Finished Jul 02 09:13:09 AM PDT 24
Peak memory 206180 kb
Host smart-6eb1e051-f661-49a8-b593-5471c091c0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32668
39995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3266839995
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.301867446
Short name T1043
Test name
Test status
Simulation time 133879029 ps
CPU time 0.81 seconds
Started Jul 02 09:13:12 AM PDT 24
Finished Jul 02 09:13:18 AM PDT 24
Peak memory 206196 kb
Host smart-60b1671f-b3ce-4bcc-bab6-393e2fcb5c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30186
7446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.301867446
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1059029853
Short name T1145
Test name
Test status
Simulation time 186847468 ps
CPU time 0.87 seconds
Started Jul 02 09:13:15 AM PDT 24
Finished Jul 02 09:13:21 AM PDT 24
Peak memory 206124 kb
Host smart-0e650f7d-5bd4-45b8-98cc-51a55179444b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10590
29853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1059029853
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1732378500
Short name T922
Test name
Test status
Simulation time 232372895 ps
CPU time 0.9 seconds
Started Jul 02 09:13:12 AM PDT 24
Finished Jul 02 09:13:18 AM PDT 24
Peak memory 206212 kb
Host smart-148d9a2d-7981-4fc5-82d0-6600df5917e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17323
78500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1732378500
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3584921402
Short name T1897
Test name
Test status
Simulation time 23327070574 ps
CPU time 24.27 seconds
Started Jul 02 09:13:07 AM PDT 24
Finished Jul 02 09:13:35 AM PDT 24
Peak memory 206288 kb
Host smart-32392bf1-9271-4240-9d93-763b83c82fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35849
21402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3584921402
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3555620323
Short name T1899
Test name
Test status
Simulation time 3365741201 ps
CPU time 3.83 seconds
Started Jul 02 09:13:06 AM PDT 24
Finished Jul 02 09:13:12 AM PDT 24
Peak memory 206268 kb
Host smart-c793f0de-dd29-47c5-84e6-3d5929851b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35556
20323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3555620323
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1578714851
Short name T1732
Test name
Test status
Simulation time 10280670405 ps
CPU time 278.95 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:17:53 AM PDT 24
Peak memory 206532 kb
Host smart-e02b63db-4941-4feb-a3f1-129c231c61d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15787
14851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1578714851
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.4248988825
Short name T2086
Test name
Test status
Simulation time 7143093442 ps
CPU time 199.77 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:16:34 AM PDT 24
Peak memory 206480 kb
Host smart-017f0118-161e-4268-b94b-29db6be3b7f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4248988825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.4248988825
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2170355106
Short name T1613
Test name
Test status
Simulation time 236592810 ps
CPU time 0.89 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206188 kb
Host smart-423f63d2-b130-4ace-b9c1-a4360e53cd6a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2170355106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2170355106
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.256574535
Short name T1297
Test name
Test status
Simulation time 194269193 ps
CPU time 0.88 seconds
Started Jul 02 09:13:14 AM PDT 24
Finished Jul 02 09:13:20 AM PDT 24
Peak memory 206212 kb
Host smart-b7e5482a-8e61-43e5-9fd1-95e2ca3632a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25657
4535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.256574535
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.4102935831
Short name T731
Test name
Test status
Simulation time 5048304647 ps
CPU time 48.16 seconds
Started Jul 02 09:13:06 AM PDT 24
Finished Jul 02 09:13:56 AM PDT 24
Peak memory 206464 kb
Host smart-cc0aede2-2ff5-40ee-bd8f-c188be500f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
35831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.4102935831
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.2710170506
Short name T796
Test name
Test status
Simulation time 4637245280 ps
CPU time 130.35 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:15:21 AM PDT 24
Peak memory 206416 kb
Host smart-a97306ec-7c59-4924-bbf3-6935601a68c3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2710170506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.2710170506
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.4090086994
Short name T1451
Test name
Test status
Simulation time 168624087 ps
CPU time 0.78 seconds
Started Jul 02 09:13:12 AM PDT 24
Finished Jul 02 09:13:19 AM PDT 24
Peak memory 206176 kb
Host smart-e0d8ad77-0383-4254-86a0-51ee4488e090
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4090086994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.4090086994
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.287681176
Short name T810
Test name
Test status
Simulation time 145934806 ps
CPU time 0.8 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:14 AM PDT 24
Peak memory 206340 kb
Host smart-a7feb644-f890-49d3-b4fd-eeb3ef109bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28768
1176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.287681176
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2068220445
Short name T2306
Test name
Test status
Simulation time 185299160 ps
CPU time 0.87 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:14 AM PDT 24
Peak memory 206080 kb
Host smart-a35d0830-bbfa-4424-abf4-2505b689ff6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20682
20445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2068220445
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3462992358
Short name T1208
Test name
Test status
Simulation time 172783032 ps
CPU time 0.84 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:17 AM PDT 24
Peak memory 206184 kb
Host smart-97721ddb-54ef-44a9-b3ee-2d4edfddc54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34629
92358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3462992358
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3478364346
Short name T447
Test name
Test status
Simulation time 199733287 ps
CPU time 0.82 seconds
Started Jul 02 09:13:10 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206204 kb
Host smart-e3c191d2-be06-4490-922d-95f33028e7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34783
64346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3478364346
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2645643120
Short name T1622
Test name
Test status
Simulation time 158891849 ps
CPU time 0.76 seconds
Started Jul 02 09:13:15 AM PDT 24
Finished Jul 02 09:13:21 AM PDT 24
Peak memory 206212 kb
Host smart-034260b6-05e0-4a71-9ca9-2d22b54c14d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26456
43120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2645643120
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1217284106
Short name T1193
Test name
Test status
Simulation time 259692109 ps
CPU time 0.98 seconds
Started Jul 02 09:13:09 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206164 kb
Host smart-4b08e6a7-6872-4e0a-a233-c65fd9327e70
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1217284106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1217284106
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1733601125
Short name T2171
Test name
Test status
Simulation time 140314709 ps
CPU time 0.75 seconds
Started Jul 02 09:13:15 AM PDT 24
Finished Jul 02 09:13:21 AM PDT 24
Peak memory 206212 kb
Host smart-f2adc3da-5633-43b2-8002-6b13351835cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17336
01125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1733601125
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.807923284
Short name T1412
Test name
Test status
Simulation time 44532806 ps
CPU time 0.67 seconds
Started Jul 02 09:13:06 AM PDT 24
Finished Jul 02 09:13:09 AM PDT 24
Peak memory 206136 kb
Host smart-54c749cd-1dab-4cef-b1f8-082ad3599cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80792
3284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.807923284
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1174910699
Short name T2081
Test name
Test status
Simulation time 14598498050 ps
CPU time 33.54 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:50 AM PDT 24
Peak memory 206564 kb
Host smart-0e45b641-2c79-42ec-9ae3-04df7c7d643b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11749
10699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1174910699
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.227747280
Short name T2636
Test name
Test status
Simulation time 198665792 ps
CPU time 0.88 seconds
Started Jul 02 09:13:10 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206196 kb
Host smart-79cad1ce-f2f1-41e6-baf0-c9c798c47bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22774
7280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.227747280
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3684936336
Short name T1505
Test name
Test status
Simulation time 242217873 ps
CPU time 0.92 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:12 AM PDT 24
Peak memory 206208 kb
Host smart-c6b1235e-7470-46a6-b468-f791c4adecb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36849
36336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3684936336
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1835251285
Short name T332
Test name
Test status
Simulation time 228403152 ps
CPU time 0.89 seconds
Started Jul 02 09:13:21 AM PDT 24
Finished Jul 02 09:13:23 AM PDT 24
Peak memory 206196 kb
Host smart-eb802c8c-2cf6-4070-968c-d38d27bb577b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18352
51285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1835251285
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.3715148029
Short name T2003
Test name
Test status
Simulation time 182364893 ps
CPU time 0.81 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:18 AM PDT 24
Peak memory 206124 kb
Host smart-7b7ab6c7-5643-44d0-9527-ac85bc0c0cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37151
48029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.3715148029
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2368189368
Short name T1429
Test name
Test status
Simulation time 147230172 ps
CPU time 0.78 seconds
Started Jul 02 09:13:11 AM PDT 24
Finished Jul 02 09:13:17 AM PDT 24
Peak memory 206196 kb
Host smart-6c14451f-bebd-4264-8e28-e43e8683bd05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23681
89368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2368189368
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.493439
Short name T1336
Test name
Test status
Simulation time 151334103 ps
CPU time 0.84 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:13 AM PDT 24
Peak memory 206188 kb
Host smart-43307422-6bb3-468f-a7c9-43b59c19cf5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49343
9 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.493439
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3470464436
Short name T2115
Test name
Test status
Simulation time 169614226 ps
CPU time 0.78 seconds
Started Jul 02 09:13:13 AM PDT 24
Finished Jul 02 09:13:19 AM PDT 24
Peak memory 206196 kb
Host smart-c5b68bdf-a94c-423f-97c9-e69f614d6c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34704
64436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3470464436
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1545524767
Short name T1998
Test name
Test status
Simulation time 207914863 ps
CPU time 0.94 seconds
Started Jul 02 09:13:08 AM PDT 24
Finished Jul 02 09:13:13 AM PDT 24
Peak memory 206220 kb
Host smart-fec91557-f04a-40b7-8e90-a96eaabeb8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15455
24767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1545524767
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1571512351
Short name T1624
Test name
Test status
Simulation time 174509237 ps
CPU time 0.98 seconds
Started Jul 02 09:13:05 AM PDT 24
Finished Jul 02 09:13:09 AM PDT 24
Peak memory 206228 kb
Host smart-f475072d-a7ca-43cd-8292-25ad67e0bcdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15715
12351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1571512351
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.4082244057
Short name T2367
Test name
Test status
Simulation time 181804574 ps
CPU time 0.79 seconds
Started Jul 02 09:13:10 AM PDT 24
Finished Jul 02 09:13:15 AM PDT 24
Peak memory 206204 kb
Host smart-dd5361f4-1b0f-473e-872a-0e4d02df2d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40822
44057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.4082244057
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.4234394500
Short name T1198
Test name
Test status
Simulation time 1155100922 ps
CPU time 2.23 seconds
Started Jul 02 09:13:02 AM PDT 24
Finished Jul 02 09:13:06 AM PDT 24
Peak memory 206456 kb
Host smart-050ae17c-ce3c-46c2-b228-265bc3d8c0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42343
94500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.4234394500
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1723930027
Short name T1156
Test name
Test status
Simulation time 4773153524 ps
CPU time 137.75 seconds
Started Jul 02 09:13:16 AM PDT 24
Finished Jul 02 09:15:38 AM PDT 24
Peak memory 206488 kb
Host smart-e7e5b234-381b-4cb6-901a-7638fe90f71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17239
30027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1723930027
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.3741953401
Short name T2274
Test name
Test status
Simulation time 101637341 ps
CPU time 0.78 seconds
Started Jul 02 09:07:02 AM PDT 24
Finished Jul 02 09:07:04 AM PDT 24
Peak memory 206212 kb
Host smart-8553f1cf-d5e1-4417-8d7e-80a8f13dc1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3741953401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3741953401
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.40370944
Short name T1494
Test name
Test status
Simulation time 3694114107 ps
CPU time 4.82 seconds
Started Jul 02 09:06:51 AM PDT 24
Finished Jul 02 09:06:57 AM PDT 24
Peak memory 206444 kb
Host smart-76dddcaf-a160-4367-865e-b6e20e600474
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=40370944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.40370944
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.995656453
Short name T2237
Test name
Test status
Simulation time 23454812284 ps
CPU time 24.14 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:07:14 AM PDT 24
Peak memory 206252 kb
Host smart-e1e2ef5c-6f75-4489-b298-bf8205f9283e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=995656453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.995656453
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1491658542
Short name T1450
Test name
Test status
Simulation time 205907765 ps
CPU time 0.87 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:06:45 AM PDT 24
Peak memory 206188 kb
Host smart-2af37906-af99-483b-8b80-25ef8036a65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14916
58542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1491658542
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.710971624
Short name T1782
Test name
Test status
Simulation time 182411783 ps
CPU time 0.9 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:06:51 AM PDT 24
Peak memory 206196 kb
Host smart-da7f5263-2928-4754-900a-0dfff14f4a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71097
1624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.710971624
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.4009497804
Short name T63
Test name
Test status
Simulation time 460611426 ps
CPU time 1.36 seconds
Started Jul 02 09:06:52 AM PDT 24
Finished Jul 02 09:06:56 AM PDT 24
Peak memory 206200 kb
Host smart-2db02247-33e9-4aa1-b766-45f1f5a36b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40094
97804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.4009497804
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2408340258
Short name T1640
Test name
Test status
Simulation time 1510532723 ps
CPU time 3.2 seconds
Started Jul 02 09:06:52 AM PDT 24
Finished Jul 02 09:06:57 AM PDT 24
Peak memory 206472 kb
Host smart-84238b65-52d0-4ed9-bf86-8a7d2a0e9487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24083
40258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2408340258
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.2341798076
Short name T2123
Test name
Test status
Simulation time 10872752426 ps
CPU time 21.31 seconds
Started Jul 02 09:06:43 AM PDT 24
Finished Jul 02 09:07:05 AM PDT 24
Peak memory 206516 kb
Host smart-656547b2-9248-4795-ba0e-03ace4e4b2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23417
98076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.2341798076
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.242409832
Short name T2224
Test name
Test status
Simulation time 442381950 ps
CPU time 1.29 seconds
Started Jul 02 09:06:49 AM PDT 24
Finished Jul 02 09:06:52 AM PDT 24
Peak memory 206212 kb
Host smart-360be067-40ed-438d-8b46-03bdff792b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24240
9832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.242409832
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3194397827
Short name T1127
Test name
Test status
Simulation time 149057514 ps
CPU time 0.78 seconds
Started Jul 02 09:06:51 AM PDT 24
Finished Jul 02 09:06:54 AM PDT 24
Peak memory 206212 kb
Host smart-47b92150-3da4-4cff-a0fa-5cf7368c447a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31943
97827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3194397827
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.124554357
Short name T1007
Test name
Test status
Simulation time 44014924 ps
CPU time 0.68 seconds
Started Jul 02 09:06:52 AM PDT 24
Finished Jul 02 09:06:54 AM PDT 24
Peak memory 206156 kb
Host smart-3a18c689-1f6b-4a31-9bda-f24eff6e3e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12455
4357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.124554357
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.2649810675
Short name T393
Test name
Test status
Simulation time 872269541 ps
CPU time 2.08 seconds
Started Jul 02 09:06:57 AM PDT 24
Finished Jul 02 09:07:01 AM PDT 24
Peak memory 206424 kb
Host smart-485d7f8d-63e7-442d-9184-f6e4263ac2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26498
10675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.2649810675
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1364149779
Short name T1865
Test name
Test status
Simulation time 254066891 ps
CPU time 1.71 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:06:49 AM PDT 24
Peak memory 206468 kb
Host smart-9bbc0ccc-1e93-4b72-8ced-411e71844e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13641
49779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1364149779
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.957514462
Short name T114
Test name
Test status
Simulation time 190215393 ps
CPU time 0.88 seconds
Started Jul 02 09:06:46 AM PDT 24
Finished Jul 02 09:06:50 AM PDT 24
Peak memory 206212 kb
Host smart-3df7ba26-1dea-46c9-8682-d09a8d7e912c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95751
4462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.957514462
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3057051091
Short name T1665
Test name
Test status
Simulation time 136960048 ps
CPU time 0.74 seconds
Started Jul 02 09:06:56 AM PDT 24
Finished Jul 02 09:06:59 AM PDT 24
Peak memory 206172 kb
Host smart-7bb5fbbc-6ecb-4635-ba6c-5222d6d5a72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30570
51091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3057051091
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1945286964
Short name T486
Test name
Test status
Simulation time 245012369 ps
CPU time 0.96 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:06:50 AM PDT 24
Peak memory 206192 kb
Host smart-958773dd-aa2b-4bb8-99f6-d8447b08015c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19452
86964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1945286964
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.1519035890
Short name T1881
Test name
Test status
Simulation time 6239404460 ps
CPU time 62.22 seconds
Started Jul 02 09:06:51 AM PDT 24
Finished Jul 02 09:07:55 AM PDT 24
Peak memory 206500 kb
Host smart-518b3a24-1fea-4228-babe-6a5337c06d63
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1519035890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.1519035890
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2755937867
Short name T2287
Test name
Test status
Simulation time 162843758 ps
CPU time 0.76 seconds
Started Jul 02 09:06:54 AM PDT 24
Finished Jul 02 09:06:57 AM PDT 24
Peak memory 206172 kb
Host smart-79d3a8a7-ae2e-42c9-a1d3-87f9750bd9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27559
37867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2755937867
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1673215537
Short name T2515
Test name
Test status
Simulation time 23349136499 ps
CPU time 25.45 seconds
Started Jul 02 09:06:44 AM PDT 24
Finished Jul 02 09:07:11 AM PDT 24
Peak memory 206232 kb
Host smart-b4daaa02-1845-47d9-b1fe-f6ff1d5de652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16732
15537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1673215537
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2680633747
Short name T2139
Test name
Test status
Simulation time 3277344231 ps
CPU time 4.37 seconds
Started Jul 02 09:06:55 AM PDT 24
Finished Jul 02 09:07:02 AM PDT 24
Peak memory 206276 kb
Host smart-e361608f-d1f1-4deb-97cf-2c2051557b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26806
33747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2680633747
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1462455731
Short name T1436
Test name
Test status
Simulation time 9729257647 ps
CPU time 66.16 seconds
Started Jul 02 09:06:58 AM PDT 24
Finished Jul 02 09:08:06 AM PDT 24
Peak memory 206532 kb
Host smart-1e81b9a9-bd30-4470-9358-c8792dd1512b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14624
55731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1462455731
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.394781551
Short name T2359
Test name
Test status
Simulation time 4746068569 ps
CPU time 46.73 seconds
Started Jul 02 09:06:49 AM PDT 24
Finished Jul 02 09:07:38 AM PDT 24
Peak memory 206436 kb
Host smart-372f1982-83cf-4c4d-8735-9ccdfd4157bf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=394781551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.394781551
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1740755406
Short name T337
Test name
Test status
Simulation time 239771799 ps
CPU time 0.9 seconds
Started Jul 02 09:07:00 AM PDT 24
Finished Jul 02 09:07:03 AM PDT 24
Peak memory 206156 kb
Host smart-025bd8e8-7f7d-4819-8ccc-8d40ce8fb9b3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1740755406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1740755406
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.893150235
Short name T1477
Test name
Test status
Simulation time 198211635 ps
CPU time 0.86 seconds
Started Jul 02 09:06:46 AM PDT 24
Finished Jul 02 09:06:49 AM PDT 24
Peak memory 206216 kb
Host smart-7a3c836d-2795-41cd-acf1-948f2f3b357f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89315
0235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.893150235
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1323675179
Short name T951
Test name
Test status
Simulation time 5367403804 ps
CPU time 149.76 seconds
Started Jul 02 09:06:51 AM PDT 24
Finished Jul 02 09:09:22 AM PDT 24
Peak memory 206448 kb
Host smart-f8785c6e-030f-45d1-a4f3-b7f84850fc77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13236
75179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1323675179
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2737356285
Short name T1756
Test name
Test status
Simulation time 5726795787 ps
CPU time 51.54 seconds
Started Jul 02 09:06:57 AM PDT 24
Finished Jul 02 09:07:51 AM PDT 24
Peak memory 206504 kb
Host smart-066de3e6-c2a7-4e7e-b558-3a4e77e17130
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2737356285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2737356285
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3952196350
Short name T1659
Test name
Test status
Simulation time 157452713 ps
CPU time 0.81 seconds
Started Jul 02 09:06:53 AM PDT 24
Finished Jul 02 09:06:56 AM PDT 24
Peak memory 206160 kb
Host smart-b281d017-8057-4b81-8d32-d66ce2b6a2c0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3952196350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3952196350
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2102054726
Short name T2576
Test name
Test status
Simulation time 142898681 ps
CPU time 0.76 seconds
Started Jul 02 09:06:50 AM PDT 24
Finished Jul 02 09:06:52 AM PDT 24
Peak memory 206184 kb
Host smart-136164eb-807f-40af-a6a5-695035e37237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21020
54726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2102054726
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1333651166
Short name T131
Test name
Test status
Simulation time 240184388 ps
CPU time 0.9 seconds
Started Jul 02 09:06:45 AM PDT 24
Finished Jul 02 09:06:48 AM PDT 24
Peak memory 206216 kb
Host smart-c0424e28-6869-466d-a4df-25ab753fd1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13336
51166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1333651166
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3447596263
Short name T1173
Test name
Test status
Simulation time 227045101 ps
CPU time 0.88 seconds
Started Jul 02 09:06:54 AM PDT 24
Finished Jul 02 09:06:58 AM PDT 24
Peak memory 206204 kb
Host smart-0490ddb9-21ae-4452-ae90-f5f8c2471ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34475
96263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3447596263
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.313671688
Short name T2414
Test name
Test status
Simulation time 149547260 ps
CPU time 0.76 seconds
Started Jul 02 09:06:53 AM PDT 24
Finished Jul 02 09:06:56 AM PDT 24
Peak memory 206164 kb
Host smart-cfaf6afc-21af-4926-8e45-62d37b965e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31367
1688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.313671688
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.18377763
Short name T20
Test name
Test status
Simulation time 190529789 ps
CPU time 0.84 seconds
Started Jul 02 09:06:55 AM PDT 24
Finished Jul 02 09:06:58 AM PDT 24
Peak memory 206204 kb
Host smart-76da8d05-f773-4394-b1c7-0bb0a4029f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18377
763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.18377763
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2539416227
Short name T177
Test name
Test status
Simulation time 204272542 ps
CPU time 0.83 seconds
Started Jul 02 09:06:48 AM PDT 24
Finished Jul 02 09:06:51 AM PDT 24
Peak memory 206212 kb
Host smart-6bd36633-b006-4337-9673-08bed39de520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25394
16227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2539416227
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1077908577
Short name T2642
Test name
Test status
Simulation time 264616285 ps
CPU time 0.94 seconds
Started Jul 02 09:06:47 AM PDT 24
Finished Jul 02 09:06:50 AM PDT 24
Peak memory 206188 kb
Host smart-7da29889-b8f1-4743-96de-f79b33b754c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1077908577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1077908577
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.597084451
Short name T1402
Test name
Test status
Simulation time 158495034 ps
CPU time 0.82 seconds
Started Jul 02 09:06:49 AM PDT 24
Finished Jul 02 09:06:52 AM PDT 24
Peak memory 206176 kb
Host smart-5dfec879-4114-454f-b92f-e67cbbc6d988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59708
4451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.597084451
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2636746314
Short name T1460
Test name
Test status
Simulation time 26762316 ps
CPU time 0.67 seconds
Started Jul 02 09:06:57 AM PDT 24
Finished Jul 02 09:07:00 AM PDT 24
Peak memory 206136 kb
Host smart-22d616d4-404e-41f8-af63-065a6b9f5755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26367
46314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2636746314
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3729563705
Short name T2345
Test name
Test status
Simulation time 18281589697 ps
CPU time 47.32 seconds
Started Jul 02 09:06:58 AM PDT 24
Finished Jul 02 09:07:47 AM PDT 24
Peak memory 206532 kb
Host smart-5bf24db6-f4fb-40f1-9c0e-7a64b78048f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37295
63705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3729563705
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2148065286
Short name T2045
Test name
Test status
Simulation time 203456138 ps
CPU time 0.95 seconds
Started Jul 02 09:06:55 AM PDT 24
Finished Jul 02 09:06:58 AM PDT 24
Peak memory 206124 kb
Host smart-9c221b0a-0c91-490d-b0a4-9eff299951ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21480
65286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2148065286
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3831960460
Short name T1304
Test name
Test status
Simulation time 189108921 ps
CPU time 0.86 seconds
Started Jul 02 09:06:51 AM PDT 24
Finished Jul 02 09:06:54 AM PDT 24
Peak memory 206120 kb
Host smart-70737e46-f3e5-4c4b-8e15-31e86d695ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38319
60460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3831960460
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.4134948181
Short name T2383
Test name
Test status
Simulation time 18554866912 ps
CPU time 128.55 seconds
Started Jul 02 09:07:01 AM PDT 24
Finished Jul 02 09:09:12 AM PDT 24
Peak memory 206480 kb
Host smart-41e50e45-b5c0-4134-95fe-e78752c9632e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4134948181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.4134948181
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3885634371
Short name T2294
Test name
Test status
Simulation time 12337695873 ps
CPU time 243.74 seconds
Started Jul 02 09:06:55 AM PDT 24
Finished Jul 02 09:11:02 AM PDT 24
Peak memory 206448 kb
Host smart-ab357a19-8f98-4249-866b-49a11b8e2c68
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3885634371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3885634371
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3262213793
Short name T818
Test name
Test status
Simulation time 18031121315 ps
CPU time 410.51 seconds
Started Jul 02 09:06:50 AM PDT 24
Finished Jul 02 09:13:42 AM PDT 24
Peak memory 206516 kb
Host smart-e9d8794b-4e41-4e97-9480-9b48e109fcc8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3262213793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3262213793
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3210986403
Short name T1323
Test name
Test status
Simulation time 235847428 ps
CPU time 0.89 seconds
Started Jul 02 09:06:54 AM PDT 24
Finished Jul 02 09:06:57 AM PDT 24
Peak memory 206220 kb
Host smart-8b915ff4-f901-4d6e-ab5c-94cdb37b0c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109
86403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3210986403
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1027573371
Short name T2601
Test name
Test status
Simulation time 192292749 ps
CPU time 0.89 seconds
Started Jul 02 09:07:00 AM PDT 24
Finished Jul 02 09:07:03 AM PDT 24
Peak memory 206176 kb
Host smart-5177c087-9916-4a1c-8dfa-c45fe1be6eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10275
73371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1027573371
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.3388574155
Short name T964
Test name
Test status
Simulation time 202306937 ps
CPU time 0.85 seconds
Started Jul 02 09:06:55 AM PDT 24
Finished Jul 02 09:06:58 AM PDT 24
Peak memory 206196 kb
Host smart-f9f49b0a-9fef-459c-862e-3a15d3cda1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33885
74155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.3388574155
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3004288615
Short name T2353
Test name
Test status
Simulation time 162911218 ps
CPU time 0.83 seconds
Started Jul 02 09:07:01 AM PDT 24
Finished Jul 02 09:07:04 AM PDT 24
Peak memory 206204 kb
Host smart-42151d78-d464-483e-bc9e-01933cbdc1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30042
88615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3004288615
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3360751838
Short name T341
Test name
Test status
Simulation time 202563995 ps
CPU time 0.84 seconds
Started Jul 02 09:06:58 AM PDT 24
Finished Jul 02 09:07:01 AM PDT 24
Peak memory 206140 kb
Host smart-1375dc8c-e128-4880-84b8-f9130cadaac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33607
51838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3360751838
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1579921199
Short name T504
Test name
Test status
Simulation time 234784794 ps
CPU time 0.92 seconds
Started Jul 02 09:06:59 AM PDT 24
Finished Jul 02 09:07:02 AM PDT 24
Peak memory 206212 kb
Host smart-7d7f5c4d-8e63-47a7-b85c-48d5b868739f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15799
21199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1579921199
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1111820430
Short name T978
Test name
Test status
Simulation time 4489097417 ps
CPU time 121.4 seconds
Started Jul 02 09:06:53 AM PDT 24
Finished Jul 02 09:08:56 AM PDT 24
Peak memory 206508 kb
Host smart-9456ab82-ac05-444d-a1d6-5a113220b71f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1111820430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1111820430
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.4223747474
Short name T2013
Test name
Test status
Simulation time 183973654 ps
CPU time 0.91 seconds
Started Jul 02 09:06:59 AM PDT 24
Finished Jul 02 09:07:02 AM PDT 24
Peak memory 206184 kb
Host smart-e9e31d1b-379e-47a0-8e0f-a92469f46dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42237
47474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.4223747474
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3804057261
Short name T2146
Test name
Test status
Simulation time 160485833 ps
CPU time 0.8 seconds
Started Jul 02 09:06:59 AM PDT 24
Finished Jul 02 09:07:02 AM PDT 24
Peak memory 206212 kb
Host smart-7bf561e5-99ac-493c-8409-b8173ba87c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38040
57261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3804057261
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.89025390
Short name T2199
Test name
Test status
Simulation time 1259258408 ps
CPU time 2.81 seconds
Started Jul 02 09:06:54 AM PDT 24
Finished Jul 02 09:06:59 AM PDT 24
Peak memory 206356 kb
Host smart-fc54c09d-b4a5-4383-994b-77f03d30ef85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89025
390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.89025390
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.388866825
Short name T2088
Test name
Test status
Simulation time 4769178031 ps
CPU time 45.04 seconds
Started Jul 02 09:06:53 AM PDT 24
Finished Jul 02 09:07:40 AM PDT 24
Peak memory 206436 kb
Host smart-1ad2bc2d-b465-466b-be78-15df9b9ccd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38886
6825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.388866825
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.3834454854
Short name T846
Test name
Test status
Simulation time 50756613 ps
CPU time 0.68 seconds
Started Jul 02 09:07:07 AM PDT 24
Finished Jul 02 09:07:10 AM PDT 24
Peak memory 206104 kb
Host smart-69e6be61-afa1-4827-83ff-9e61ee8f72d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3834454854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.3834454854
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.406027026
Short name T1449
Test name
Test status
Simulation time 3920689452 ps
CPU time 4.58 seconds
Started Jul 02 09:06:55 AM PDT 24
Finished Jul 02 09:07:02 AM PDT 24
Peak memory 206240 kb
Host smart-2ec460c8-83de-4a24-be98-cbfc2241d09a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=406027026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.406027026
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.392700596
Short name T1051
Test name
Test status
Simulation time 13577179035 ps
CPU time 14.84 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:19 AM PDT 24
Peak memory 206488 kb
Host smart-bbd3b812-e5ec-4681-89c1-81b91c5f8f1a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=392700596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.392700596
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3100312300
Short name T8
Test name
Test status
Simulation time 23390023663 ps
CPU time 24.24 seconds
Started Jul 02 09:06:56 AM PDT 24
Finished Jul 02 09:07:22 AM PDT 24
Peak memory 206208 kb
Host smart-adaf30ac-7ce5-45dd-926e-607164971b0c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3100312300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3100312300
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2643973662
Short name T2205
Test name
Test status
Simulation time 162031956 ps
CPU time 0.83 seconds
Started Jul 02 09:06:55 AM PDT 24
Finished Jul 02 09:06:59 AM PDT 24
Peak memory 206172 kb
Host smart-6219c2dc-023a-4459-8521-7136ae9b34bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26439
73662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2643973662
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1859596375
Short name T894
Test name
Test status
Simulation time 180115317 ps
CPU time 0.85 seconds
Started Jul 02 09:07:01 AM PDT 24
Finished Jul 02 09:07:04 AM PDT 24
Peak memory 206200 kb
Host smart-d27be7ef-6535-41d0-b5ed-6bbc58a80831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18595
96375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1859596375
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.3852106540
Short name T1616
Test name
Test status
Simulation time 572372074 ps
CPU time 1.82 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:07 AM PDT 24
Peak memory 206060 kb
Host smart-cfc2cedb-b828-496e-b600-689a6e620ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38521
06540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3852106540
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1224036813
Short name T1963
Test name
Test status
Simulation time 926007594 ps
CPU time 2.28 seconds
Started Jul 02 09:06:55 AM PDT 24
Finished Jul 02 09:06:59 AM PDT 24
Peak memory 206416 kb
Host smart-8db4bb4c-681a-48e7-bc54-84b130ccce3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12240
36813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1224036813
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.1285220053
Short name T1987
Test name
Test status
Simulation time 16401646889 ps
CPU time 36.56 seconds
Started Jul 02 09:07:01 AM PDT 24
Finished Jul 02 09:07:40 AM PDT 24
Peak memory 206476 kb
Host smart-851b84fa-7b58-4743-8f2d-becf075cf454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12852
20053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.1285220053
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3899190671
Short name T1733
Test name
Test status
Simulation time 468692156 ps
CPU time 1.31 seconds
Started Jul 02 09:06:55 AM PDT 24
Finished Jul 02 09:06:59 AM PDT 24
Peak memory 206200 kb
Host smart-41ee2b1f-b608-4c79-9ddf-32da3742a44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38991
90671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3899190671
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3099586997
Short name T1851
Test name
Test status
Simulation time 141033392 ps
CPU time 0.74 seconds
Started Jul 02 09:06:59 AM PDT 24
Finished Jul 02 09:07:01 AM PDT 24
Peak memory 206160 kb
Host smart-ec4546fc-719f-4f8f-b648-ad6f20544143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30995
86997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3099586997
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2435280750
Short name T489
Test name
Test status
Simulation time 37583946 ps
CPU time 0.68 seconds
Started Jul 02 09:06:59 AM PDT 24
Finished Jul 02 09:07:01 AM PDT 24
Peak memory 206176 kb
Host smart-9fecf411-3dff-4d57-9ff3-423d798135b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24352
80750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2435280750
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2512534413
Short name T1639
Test name
Test status
Simulation time 953381910 ps
CPU time 2.26 seconds
Started Jul 02 09:07:02 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206364 kb
Host smart-cff44f71-7ef6-4edb-bb28-ce3fe4c2b116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25125
34413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2512534413
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1316008811
Short name T1920
Test name
Test status
Simulation time 219473001 ps
CPU time 2.28 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:07 AM PDT 24
Peak memory 205952 kb
Host smart-5e683761-68b7-43e7-a8ac-917a1205df3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13160
08811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1316008811
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1523250461
Short name T2290
Test name
Test status
Simulation time 174030558 ps
CPU time 0.83 seconds
Started Jul 02 09:06:56 AM PDT 24
Finished Jul 02 09:06:59 AM PDT 24
Peak memory 206204 kb
Host smart-2b34e19a-e70d-46ce-a748-994d1147afe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15232
50461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1523250461
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.4182124839
Short name T1444
Test name
Test status
Simulation time 152206548 ps
CPU time 0.81 seconds
Started Jul 02 09:06:57 AM PDT 24
Finished Jul 02 09:06:59 AM PDT 24
Peak memory 206196 kb
Host smart-87820836-fdec-4b75-8dd2-000df3c9836b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41821
24839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.4182124839
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.390522735
Short name T1598
Test name
Test status
Simulation time 231171280 ps
CPU time 0.91 seconds
Started Jul 02 09:06:55 AM PDT 24
Finished Jul 02 09:06:59 AM PDT 24
Peak memory 206180 kb
Host smart-604a12e1-20a8-4dea-a6b5-d1ebed29e50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39052
2735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.390522735
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.2188600450
Short name T250
Test name
Test status
Simulation time 9417261998 ps
CPU time 91.17 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:08:36 AM PDT 24
Peak memory 206444 kb
Host smart-e7d25ccb-45f0-461e-8407-ce12468d3b24
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2188600450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.2188600450
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.517817229
Short name T1822
Test name
Test status
Simulation time 252168940 ps
CPU time 0.9 seconds
Started Jul 02 09:07:01 AM PDT 24
Finished Jul 02 09:07:04 AM PDT 24
Peak memory 206224 kb
Host smart-97a5723e-7eee-422f-b60b-9ec32024a922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51781
7229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.517817229
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.357990917
Short name T1213
Test name
Test status
Simulation time 23285808683 ps
CPU time 23.85 seconds
Started Jul 02 09:06:57 AM PDT 24
Finished Jul 02 09:07:23 AM PDT 24
Peak memory 206268 kb
Host smart-ba6db08c-7fa2-48e9-8e9b-f58113b0bb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35799
0917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.357990917
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1423763499
Short name T2430
Test name
Test status
Simulation time 3318319914 ps
CPU time 3.75 seconds
Started Jul 02 09:07:05 AM PDT 24
Finished Jul 02 09:07:09 AM PDT 24
Peak memory 206276 kb
Host smart-882fe793-3d87-406c-a527-c37a9f927260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14237
63499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1423763499
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1307733692
Short name T913
Test name
Test status
Simulation time 9272048778 ps
CPU time 65.84 seconds
Started Jul 02 09:07:10 AM PDT 24
Finished Jul 02 09:08:17 AM PDT 24
Peak memory 206456 kb
Host smart-8a04930d-bc6d-4360-b350-ad23e981c867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13077
33692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1307733692
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.659425886
Short name T392
Test name
Test status
Simulation time 4844559785 ps
CPU time 139.34 seconds
Started Jul 02 09:07:02 AM PDT 24
Finished Jul 02 09:09:23 AM PDT 24
Peak memory 206448 kb
Host smart-ddc5f9d0-9945-4ad2-a2f9-1764fbb2e9c6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=659425886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.659425886
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.4218685398
Short name T782
Test name
Test status
Simulation time 237731157 ps
CPU time 0.91 seconds
Started Jul 02 09:07:00 AM PDT 24
Finished Jul 02 09:07:03 AM PDT 24
Peak memory 206144 kb
Host smart-42a5505f-3360-40fb-9671-3b75748f4f36
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4218685398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.4218685398
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.754101224
Short name T2362
Test name
Test status
Simulation time 203185257 ps
CPU time 0.92 seconds
Started Jul 02 09:07:00 AM PDT 24
Finished Jul 02 09:07:02 AM PDT 24
Peak memory 206180 kb
Host smart-df5d36b1-946f-472f-90a8-6c05181eac67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75410
1224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.754101224
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3617839845
Short name T1425
Test name
Test status
Simulation time 5091595701 ps
CPU time 34.4 seconds
Started Jul 02 09:07:05 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206500 kb
Host smart-70d6d450-7153-4180-979b-fd326dcca373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178
39845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3617839845
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.1787352427
Short name T1386
Test name
Test status
Simulation time 3942247278 ps
CPU time 36.44 seconds
Started Jul 02 09:07:01 AM PDT 24
Finished Jul 02 09:07:39 AM PDT 24
Peak memory 206380 kb
Host smart-05a6d7e8-03f9-4732-82a6-60d33de983a1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1787352427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.1787352427
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2933184257
Short name T2435
Test name
Test status
Simulation time 201767098 ps
CPU time 0.82 seconds
Started Jul 02 09:07:04 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206168 kb
Host smart-87b0aece-6e85-4638-a646-be9ff911a558
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2933184257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2933184257
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.441334306
Short name T1469
Test name
Test status
Simulation time 168579247 ps
CPU time 0.79 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:05 AM PDT 24
Peak memory 205748 kb
Host smart-b604bfc7-2959-4836-aab4-ae0c46ccb9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44133
4306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.441334306
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3103869469
Short name T141
Test name
Test status
Simulation time 171566144 ps
CPU time 0.82 seconds
Started Jul 02 09:07:01 AM PDT 24
Finished Jul 02 09:07:04 AM PDT 24
Peak memory 206192 kb
Host smart-ef847e23-5c04-466d-bfde-84b97e8ef8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31038
69469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3103869469
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.6504390
Short name T2568
Test name
Test status
Simulation time 151425277 ps
CPU time 0.82 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206196 kb
Host smart-8a29bded-31a9-4955-add0-d09e8a72d315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65043
90 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.6504390
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3093758426
Short name T2024
Test name
Test status
Simulation time 191072453 ps
CPU time 0.85 seconds
Started Jul 02 09:06:59 AM PDT 24
Finished Jul 02 09:07:02 AM PDT 24
Peak memory 206208 kb
Host smart-7b40eb59-cb4e-444f-bf98-c3effc64313c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30937
58426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3093758426
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1959370641
Short name T1967
Test name
Test status
Simulation time 185559102 ps
CPU time 0.83 seconds
Started Jul 02 09:07:04 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206208 kb
Host smart-18f3db68-1138-40bd-8bcf-9e63fea90697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19593
70641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1959370641
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2020307621
Short name T89
Test name
Test status
Simulation time 150393269 ps
CPU time 0.78 seconds
Started Jul 02 09:06:59 AM PDT 24
Finished Jul 02 09:07:02 AM PDT 24
Peak memory 206128 kb
Host smart-06f00c8b-9ce8-4b82-8686-394ff7523af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20203
07621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2020307621
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.944980741
Short name T2077
Test name
Test status
Simulation time 206160652 ps
CPU time 0.91 seconds
Started Jul 02 09:06:59 AM PDT 24
Finished Jul 02 09:07:01 AM PDT 24
Peak memory 206096 kb
Host smart-a184b562-788c-4373-ac3c-af8026f32622
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=944980741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.944980741
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3666974334
Short name T2204
Test name
Test status
Simulation time 163241778 ps
CPU time 0.79 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206208 kb
Host smart-3324d678-a9a2-42d3-aca6-bc375a8138c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36669
74334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3666974334
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3678385392
Short name T27
Test name
Test status
Simulation time 37193825 ps
CPU time 0.73 seconds
Started Jul 02 09:07:05 AM PDT 24
Finished Jul 02 09:07:07 AM PDT 24
Peak memory 206220 kb
Host smart-e3d60b47-9410-44d4-9b1f-62a70cd4effa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36783
85392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3678385392
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1104732490
Short name T941
Test name
Test status
Simulation time 13220608301 ps
CPU time 31.15 seconds
Started Jul 02 09:07:05 AM PDT 24
Finished Jul 02 09:07:38 AM PDT 24
Peak memory 206572 kb
Host smart-a80422f9-44aa-4166-aec8-6191370c3b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11047
32490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1104732490
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2917955829
Short name T2688
Test name
Test status
Simulation time 142002483 ps
CPU time 0.82 seconds
Started Jul 02 09:07:01 AM PDT 24
Finished Jul 02 09:07:04 AM PDT 24
Peak memory 206108 kb
Host smart-baad9315-0db9-4c46-b500-e71f16961a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29179
55829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2917955829
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.55049733
Short name T1668
Test name
Test status
Simulation time 227974534 ps
CPU time 0.91 seconds
Started Jul 02 09:06:59 AM PDT 24
Finished Jul 02 09:07:02 AM PDT 24
Peak memory 206208 kb
Host smart-0574e9d1-a750-484e-9a19-bf0c7833ba7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55049
733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.55049733
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1859765002
Short name T2109
Test name
Test status
Simulation time 11371864722 ps
CPU time 52.4 seconds
Started Jul 02 09:06:59 AM PDT 24
Finished Jul 02 09:07:53 AM PDT 24
Peak memory 206456 kb
Host smart-80da20a2-d538-4f21-9b28-df4d58eec8d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1859765002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1859765002
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3659423253
Short name T169
Test name
Test status
Simulation time 9305931772 ps
CPU time 45.18 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:50 AM PDT 24
Peak memory 206472 kb
Host smart-70046169-1b64-4d88-a9ec-555d41aa7094
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3659423253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3659423253
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2959154040
Short name T1607
Test name
Test status
Simulation time 12896407389 ps
CPU time 245.79 seconds
Started Jul 02 09:07:08 AM PDT 24
Finished Jul 02 09:11:16 AM PDT 24
Peak memory 206476 kb
Host smart-570518a2-90b8-4a4f-a776-ef0fcbda6edf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2959154040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2959154040
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2642918002
Short name T1669
Test name
Test status
Simulation time 178667416 ps
CPU time 0.87 seconds
Started Jul 02 09:07:05 AM PDT 24
Finished Jul 02 09:07:07 AM PDT 24
Peak memory 206180 kb
Host smart-1f9d14f6-0f42-4ff0-ad5c-6ddfb16be707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26429
18002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2642918002
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1116150762
Short name T2646
Test name
Test status
Simulation time 160719960 ps
CPU time 0.81 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:05 AM PDT 24
Peak memory 206192 kb
Host smart-54334c0a-dc60-4f16-b640-a74267ebcb32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11161
50762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1116150762
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2853417195
Short name T1046
Test name
Test status
Simulation time 186004830 ps
CPU time 0.85 seconds
Started Jul 02 09:07:04 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206160 kb
Host smart-da2078f5-0639-45ad-8510-893b7ec5b864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28534
17195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2853417195
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1255235084
Short name T2537
Test name
Test status
Simulation time 152288832 ps
CPU time 0.78 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:05 AM PDT 24
Peak memory 206212 kb
Host smart-6f86f219-4ad9-42b0-9768-9bd8515e3b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12552
35084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1255235084
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.282566244
Short name T500
Test name
Test status
Simulation time 167667209 ps
CPU time 0.83 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206180 kb
Host smart-8d9425f7-e356-457f-a248-0fdbb77a26d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28256
6244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.282566244
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3780430827
Short name T1291
Test name
Test status
Simulation time 234531193 ps
CPU time 0.95 seconds
Started Jul 02 09:07:08 AM PDT 24
Finished Jul 02 09:07:11 AM PDT 24
Peak memory 206180 kb
Host smart-829a8fc2-0d3d-4b5a-899a-1c84fd306c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37804
30827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3780430827
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1056140099
Short name T608
Test name
Test status
Simulation time 6275279451 ps
CPU time 58.63 seconds
Started Jul 02 09:07:02 AM PDT 24
Finished Jul 02 09:08:03 AM PDT 24
Peak memory 206500 kb
Host smart-22810a21-8a91-47ec-9c8d-c8cc386edc72
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1056140099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1056140099
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3386231840
Short name T1360
Test name
Test status
Simulation time 187298100 ps
CPU time 0.79 seconds
Started Jul 02 09:07:08 AM PDT 24
Finished Jul 02 09:07:11 AM PDT 24
Peak memory 206184 kb
Host smart-3c5be6b1-35ac-4e87-b190-30c178a28da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33862
31840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3386231840
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2458325583
Short name T2439
Test name
Test status
Simulation time 171265652 ps
CPU time 0.8 seconds
Started Jul 02 09:07:03 AM PDT 24
Finished Jul 02 09:07:06 AM PDT 24
Peak memory 206160 kb
Host smart-4d503d50-7611-4aef-9779-09872f0615e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24583
25583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2458325583
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.1915644184
Short name T2194
Test name
Test status
Simulation time 715060036 ps
CPU time 1.66 seconds
Started Jul 02 09:07:11 AM PDT 24
Finished Jul 02 09:07:14 AM PDT 24
Peak memory 206388 kb
Host smart-87ddad5f-e291-44e9-8dfe-1b11ab50222f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19156
44184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.1915644184
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.554862044
Short name T1372
Test name
Test status
Simulation time 4362674763 ps
CPU time 31.34 seconds
Started Jul 02 09:07:02 AM PDT 24
Finished Jul 02 09:07:35 AM PDT 24
Peak memory 206600 kb
Host smart-9a032f5c-4336-421e-8738-db68560e80cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55486
2044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.554862044
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2999765600
Short name T681
Test name
Test status
Simulation time 39903444 ps
CPU time 0.72 seconds
Started Jul 02 09:07:15 AM PDT 24
Finished Jul 02 09:07:18 AM PDT 24
Peak memory 206256 kb
Host smart-bdf776c2-a766-43dc-b030-5c8f1b89d590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2999765600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2999765600
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2834086847
Short name T1307
Test name
Test status
Simulation time 4082046923 ps
CPU time 4.64 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:07:20 AM PDT 24
Peak memory 206148 kb
Host smart-88692828-1302-4070-8013-9000c6d6365d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2834086847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.2834086847
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1927647865
Short name T749
Test name
Test status
Simulation time 13462356835 ps
CPU time 12.64 seconds
Started Jul 02 09:07:07 AM PDT 24
Finished Jul 02 09:07:21 AM PDT 24
Peak memory 206540 kb
Host smart-beaf1345-ab14-4b5b-bc48-0e408da64d78
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1927647865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1927647865
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2802448716
Short name T2684
Test name
Test status
Simulation time 23304393492 ps
CPU time 22.34 seconds
Started Jul 02 09:07:06 AM PDT 24
Finished Jul 02 09:07:30 AM PDT 24
Peak memory 206392 kb
Host smart-39681011-7f2b-4a82-aced-84e0d194f1a9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2802448716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.2802448716
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.911678715
Short name T84
Test name
Test status
Simulation time 200342564 ps
CPU time 0.83 seconds
Started Jul 02 09:07:09 AM PDT 24
Finished Jul 02 09:07:11 AM PDT 24
Peak memory 206164 kb
Host smart-60d8bf7a-2f37-462a-b28a-52f1b4e7a431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91167
8715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.911678715
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.740761642
Short name T2084
Test name
Test status
Simulation time 145135416 ps
CPU time 0.78 seconds
Started Jul 02 09:07:09 AM PDT 24
Finished Jul 02 09:07:11 AM PDT 24
Peak memory 206164 kb
Host smart-f82143a9-59c9-4be6-a4f9-4a9dab47156d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74076
1642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.740761642
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.1222457904
Short name T198
Test name
Test status
Simulation time 590164611 ps
CPU time 1.7 seconds
Started Jul 02 09:07:06 AM PDT 24
Finished Jul 02 09:07:09 AM PDT 24
Peak memory 206464 kb
Host smart-d76b2f11-5d59-4c42-bff4-66ecd5d1de91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12224
57904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.1222457904
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.262133170
Short name T192
Test name
Test status
Simulation time 543329004 ps
CPU time 1.54 seconds
Started Jul 02 09:07:07 AM PDT 24
Finished Jul 02 09:07:10 AM PDT 24
Peak memory 206120 kb
Host smart-dd53b089-52a7-4623-98e9-1af9f2f681ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26213
3170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.262133170
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.4082360947
Short name T2373
Test name
Test status
Simulation time 9563681460 ps
CPU time 17.56 seconds
Started Jul 02 09:07:11 AM PDT 24
Finished Jul 02 09:07:29 AM PDT 24
Peak memory 206484 kb
Host smart-4f819632-dd70-446c-bdfb-2fc9224feb9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40823
60947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.4082360947
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.2407074692
Short name T1991
Test name
Test status
Simulation time 360597651 ps
CPU time 1.33 seconds
Started Jul 02 09:07:09 AM PDT 24
Finished Jul 02 09:07:12 AM PDT 24
Peak memory 206216 kb
Host smart-832a36e4-c986-4a85-a1f3-13b7b367b571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24070
74692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.2407074692
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3604737945
Short name T709
Test name
Test status
Simulation time 155652497 ps
CPU time 0.79 seconds
Started Jul 02 09:07:07 AM PDT 24
Finished Jul 02 09:07:09 AM PDT 24
Peak memory 206184 kb
Host smart-b5bb8e34-37d1-4a7d-8dd0-6435e17c8cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36047
37945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3604737945
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3631803352
Short name T1422
Test name
Test status
Simulation time 48477973 ps
CPU time 0.71 seconds
Started Jul 02 09:07:09 AM PDT 24
Finished Jul 02 09:07:11 AM PDT 24
Peak memory 206172 kb
Host smart-7c5b2b65-c006-4b33-b5fe-3705387397f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36318
03352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3631803352
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2282324905
Short name T984
Test name
Test status
Simulation time 763398957 ps
CPU time 1.78 seconds
Started Jul 02 09:07:14 AM PDT 24
Finished Jul 02 09:07:18 AM PDT 24
Peak memory 206320 kb
Host smart-c65a57d2-db48-417e-81e3-465181bcbf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22823
24905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2282324905
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2919913957
Short name T2400
Test name
Test status
Simulation time 218430975 ps
CPU time 1.35 seconds
Started Jul 02 09:07:07 AM PDT 24
Finished Jul 02 09:07:10 AM PDT 24
Peak memory 206364 kb
Host smart-26c1ee81-7fa9-4178-9ab0-418454e48482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29199
13957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2919913957
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3608445402
Short name T542
Test name
Test status
Simulation time 214028618 ps
CPU time 0.89 seconds
Started Jul 02 09:07:08 AM PDT 24
Finished Jul 02 09:07:10 AM PDT 24
Peak memory 206208 kb
Host smart-3987ffde-7c6f-4535-8245-f96008e325cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36084
45402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3608445402
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.422393157
Short name T2368
Test name
Test status
Simulation time 161705166 ps
CPU time 0.81 seconds
Started Jul 02 09:07:06 AM PDT 24
Finished Jul 02 09:07:08 AM PDT 24
Peak memory 206184 kb
Host smart-b33c1262-ca5b-4fb5-a302-1089a1b0f25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42239
3157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.422393157
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2908955999
Short name T1664
Test name
Test status
Simulation time 217466149 ps
CPU time 0.95 seconds
Started Jul 02 09:07:08 AM PDT 24
Finished Jul 02 09:07:11 AM PDT 24
Peak memory 206384 kb
Host smart-994696fc-d950-49f0-a0ea-2746f63a1d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29089
55999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2908955999
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.243816596
Short name T34
Test name
Test status
Simulation time 239578750 ps
CPU time 0.9 seconds
Started Jul 02 09:07:09 AM PDT 24
Finished Jul 02 09:07:11 AM PDT 24
Peak memory 206160 kb
Host smart-11c69633-5d5e-49e1-b692-e273ff8d880c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24381
6596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.243816596
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2310879589
Short name T2060
Test name
Test status
Simulation time 23334875145 ps
CPU time 26.81 seconds
Started Jul 02 09:07:11 AM PDT 24
Finished Jul 02 09:07:39 AM PDT 24
Peak memory 206244 kb
Host smart-80e55854-b84f-40f7-844c-881e6acf6b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23108
79589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2310879589
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3705376823
Short name T342
Test name
Test status
Simulation time 3262148577 ps
CPU time 3.84 seconds
Started Jul 02 09:07:08 AM PDT 24
Finished Jul 02 09:07:14 AM PDT 24
Peak memory 206272 kb
Host smart-09ae44aa-09e4-468e-a1b2-b8528e3b9cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37053
76823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3705376823
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1854556691
Short name T752
Test name
Test status
Simulation time 9719434823 ps
CPU time 93.2 seconds
Started Jul 02 09:07:09 AM PDT 24
Finished Jul 02 09:08:44 AM PDT 24
Peak memory 206520 kb
Host smart-3a9b51cc-7aba-48d1-a022-0ad5306ac227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18545
56691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1854556691
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.1178879374
Short name T2689
Test name
Test status
Simulation time 4893274121 ps
CPU time 140.97 seconds
Started Jul 02 09:07:11 AM PDT 24
Finished Jul 02 09:09:33 AM PDT 24
Peak memory 206420 kb
Host smart-a12841af-8c3a-4dac-a7f8-a400ab29f4f4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1178879374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.1178879374
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.1563794130
Short name T1073
Test name
Test status
Simulation time 274514004 ps
CPU time 0.98 seconds
Started Jul 02 09:07:11 AM PDT 24
Finished Jul 02 09:07:13 AM PDT 24
Peak memory 206192 kb
Host smart-afce9180-0b08-44a3-95c7-4dc88cafae02
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1563794130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.1563794130
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.482542208
Short name T820
Test name
Test status
Simulation time 209064877 ps
CPU time 0.88 seconds
Started Jul 02 09:07:12 AM PDT 24
Finished Jul 02 09:07:15 AM PDT 24
Peak memory 206196 kb
Host smart-6e3d8e20-ffb0-48b3-9da3-def840dc0584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48254
2208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.482542208
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.699952900
Short name T2451
Test name
Test status
Simulation time 5236569865 ps
CPU time 146.34 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:09:42 AM PDT 24
Peak memory 206456 kb
Host smart-0800dd54-50df-4c49-ac80-757890f45ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69995
2900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.699952900
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.607135350
Short name T1320
Test name
Test status
Simulation time 4351441063 ps
CPU time 44.85 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:08:00 AM PDT 24
Peak memory 206428 kb
Host smart-d6e9b50f-50b5-4d54-87c9-174f9a5feb1e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=607135350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.607135350
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3177088579
Short name T1166
Test name
Test status
Simulation time 158172489 ps
CPU time 0.76 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:07:16 AM PDT 24
Peak memory 206184 kb
Host smart-08beff18-b5e6-408a-92e0-1376f9fc77fe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3177088579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3177088579
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.4273001707
Short name T708
Test name
Test status
Simulation time 149464428 ps
CPU time 0.73 seconds
Started Jul 02 09:07:11 AM PDT 24
Finished Jul 02 09:07:13 AM PDT 24
Peak memory 206224 kb
Host smart-8db565b6-f04e-42b8-ab7f-23c2d3f5c76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42730
01707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.4273001707
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3339018518
Short name T118
Test name
Test status
Simulation time 238812159 ps
CPU time 0.83 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:07:16 AM PDT 24
Peak memory 206200 kb
Host smart-e5be1bcc-3f53-4ea9-9610-6a00b186f32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33390
18518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3339018518
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2047237864
Short name T1724
Test name
Test status
Simulation time 161818938 ps
CPU time 0.76 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:07:16 AM PDT 24
Peak memory 205576 kb
Host smart-c87bd652-80ce-417b-b47c-0ffeac60857f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20472
37864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2047237864
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.4245860100
Short name T19
Test name
Test status
Simulation time 164720199 ps
CPU time 0.79 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:07:17 AM PDT 24
Peak memory 205656 kb
Host smart-e2cdf951-193f-47cb-969c-9ce7738dcf34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42458
60100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.4245860100
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1989931357
Short name T1945
Test name
Test status
Simulation time 178527205 ps
CPU time 0.79 seconds
Started Jul 02 09:07:14 AM PDT 24
Finished Jul 02 09:07:17 AM PDT 24
Peak memory 206184 kb
Host smart-7ca855f9-002c-4759-8605-e8eee2a85366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19899
31357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1989931357
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1341889096
Short name T2582
Test name
Test status
Simulation time 205953432 ps
CPU time 0.98 seconds
Started Jul 02 09:07:12 AM PDT 24
Finished Jul 02 09:07:14 AM PDT 24
Peak memory 206116 kb
Host smart-ac712bb0-8154-4911-9bd3-8ee40c63f381
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1341889096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1341889096
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1671713808
Short name T936
Test name
Test status
Simulation time 147233431 ps
CPU time 0.81 seconds
Started Jul 02 09:07:12 AM PDT 24
Finished Jul 02 09:07:15 AM PDT 24
Peak memory 206192 kb
Host smart-9c6dcff6-63b8-4b3a-a8e2-a71167b1b627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16717
13808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1671713808
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3854775683
Short name T1415
Test name
Test status
Simulation time 39769871 ps
CPU time 0.67 seconds
Started Jul 02 09:07:12 AM PDT 24
Finished Jul 02 09:07:14 AM PDT 24
Peak memory 206204 kb
Host smart-c95f1295-ca9c-4cc9-81de-9a15adfe2ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38547
75683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3854775683
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1882257667
Short name T691
Test name
Test status
Simulation time 10047927157 ps
CPU time 23.41 seconds
Started Jul 02 09:07:12 AM PDT 24
Finished Jul 02 09:07:37 AM PDT 24
Peak memory 206532 kb
Host smart-c59a144e-c6ac-494c-b4e1-fa5ef744bfa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18822
57667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1882257667
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3129259555
Short name T644
Test name
Test status
Simulation time 200102311 ps
CPU time 0.88 seconds
Started Jul 02 09:07:16 AM PDT 24
Finished Jul 02 09:07:19 AM PDT 24
Peak memory 206132 kb
Host smart-1afe9412-0382-49c5-a955-86a84b0cd062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31292
59555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3129259555
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.117625688
Short name T450
Test name
Test status
Simulation time 244709008 ps
CPU time 0.89 seconds
Started Jul 02 09:07:10 AM PDT 24
Finished Jul 02 09:07:12 AM PDT 24
Peak memory 206228 kb
Host smart-b5d265eb-1048-4089-856a-d2cd19cd8248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11762
5688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.117625688
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1394962722
Short name T187
Test name
Test status
Simulation time 7230435552 ps
CPU time 53.08 seconds
Started Jul 02 09:07:14 AM PDT 24
Finished Jul 02 09:08:09 AM PDT 24
Peak memory 206492 kb
Host smart-82f09987-6349-4e24-b7db-471b89164e35
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1394962722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1394962722
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2159238240
Short name T200
Test name
Test status
Simulation time 9960608866 ps
CPU time 167.88 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:10:03 AM PDT 24
Peak memory 206536 kb
Host smart-f053558f-e1c4-447d-8dab-ea61d06f97ac
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2159238240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2159238240
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2901875770
Short name T44
Test name
Test status
Simulation time 23871566425 ps
CPU time 578.24 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:16:53 AM PDT 24
Peak memory 206504 kb
Host smart-b0335f57-dd63-4f1c-a1fc-71c3e941d58e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2901875770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2901875770
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.212443993
Short name T1499
Test name
Test status
Simulation time 154395923 ps
CPU time 0.76 seconds
Started Jul 02 09:07:15 AM PDT 24
Finished Jul 02 09:07:18 AM PDT 24
Peak memory 206128 kb
Host smart-63ef2db8-7962-4508-88fc-213a6612c45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21244
3993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.212443993
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.974106028
Short name T1579
Test name
Test status
Simulation time 176698505 ps
CPU time 0.84 seconds
Started Jul 02 09:07:11 AM PDT 24
Finished Jul 02 09:07:13 AM PDT 24
Peak memory 206196 kb
Host smart-695c4f92-49e1-42b5-ac5b-0edfdb38f8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97410
6028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.974106028
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3838309745
Short name T2039
Test name
Test status
Simulation time 150318231 ps
CPU time 0.8 seconds
Started Jul 02 09:07:12 AM PDT 24
Finished Jul 02 09:07:14 AM PDT 24
Peak memory 206216 kb
Host smart-6a8bdee7-1965-4c6a-bd65-41e24a841b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38383
09745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3838309745
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3937775348
Short name T1433
Test name
Test status
Simulation time 165007658 ps
CPU time 0.84 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:07:16 AM PDT 24
Peak memory 206140 kb
Host smart-39812c73-621a-43b1-8c8e-215642c68648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39377
75348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3937775348
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1237846232
Short name T459
Test name
Test status
Simulation time 175362901 ps
CPU time 0.86 seconds
Started Jul 02 09:07:14 AM PDT 24
Finished Jul 02 09:07:17 AM PDT 24
Peak memory 206212 kb
Host smart-944b6ebd-167c-45bd-97e7-02d0b500807f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
46232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1237846232
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3338011364
Short name T1738
Test name
Test status
Simulation time 228940681 ps
CPU time 0.97 seconds
Started Jul 02 09:07:16 AM PDT 24
Finished Jul 02 09:07:19 AM PDT 24
Peak memory 206128 kb
Host smart-9b4468c4-6ecd-40d4-8cf8-50fb0487f65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33380
11364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3338011364
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2008385064
Short name T2354
Test name
Test status
Simulation time 5872501344 ps
CPU time 171.44 seconds
Started Jul 02 09:07:11 AM PDT 24
Finished Jul 02 09:10:04 AM PDT 24
Peak memory 206468 kb
Host smart-76032bcc-bd9f-4382-8439-2ee71d80bef7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2008385064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2008385064
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.4250278315
Short name T2143
Test name
Test status
Simulation time 176758649 ps
CPU time 0.87 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:07:17 AM PDT 24
Peak memory 206144 kb
Host smart-13a14e41-9ecb-45f4-987d-63ac60f9d47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42502
78315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.4250278315
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.4234864977
Short name T427
Test name
Test status
Simulation time 193855963 ps
CPU time 0.78 seconds
Started Jul 02 09:07:09 AM PDT 24
Finished Jul 02 09:07:11 AM PDT 24
Peak memory 206156 kb
Host smart-f42b8e94-7025-4c41-badf-a140cd3ec9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348
64977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.4234864977
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.3222784746
Short name T1546
Test name
Test status
Simulation time 1347981513 ps
CPU time 2.8 seconds
Started Jul 02 09:07:11 AM PDT 24
Finished Jul 02 09:07:15 AM PDT 24
Peak memory 206464 kb
Host smart-c99daa8e-0f64-42d1-9376-c054bb208c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32227
84746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.3222784746
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2367539493
Short name T962
Test name
Test status
Simulation time 4239783883 ps
CPU time 40.58 seconds
Started Jul 02 09:07:13 AM PDT 24
Finished Jul 02 09:07:56 AM PDT 24
Peak memory 206448 kb
Host smart-17ded030-2348-43f4-a54a-1d23289ed3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
39493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2367539493
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.4090998751
Short name T531
Test name
Test status
Simulation time 29295379 ps
CPU time 0.66 seconds
Started Jul 02 09:07:27 AM PDT 24
Finished Jul 02 09:07:29 AM PDT 24
Peak memory 206240 kb
Host smart-5edef5b4-ad7a-4b64-b922-6c88deadf9d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4090998751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.4090998751
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3177026690
Short name T1777
Test name
Test status
Simulation time 3709704821 ps
CPU time 4.71 seconds
Started Jul 02 09:07:15 AM PDT 24
Finished Jul 02 09:07:22 AM PDT 24
Peak memory 206232 kb
Host smart-9a3a03fb-8f1d-4a7a-afcc-e86c96447821
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3177026690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3177026690
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2554287171
Short name T221
Test name
Test status
Simulation time 13299414059 ps
CPU time 14.92 seconds
Started Jul 02 09:07:17 AM PDT 24
Finished Jul 02 09:07:34 AM PDT 24
Peak memory 206440 kb
Host smart-53e9dc88-7d94-42bd-ab23-c076ddac8d3a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2554287171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2554287171
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.349252129
Short name T655
Test name
Test status
Simulation time 23327597129 ps
CPU time 23.14 seconds
Started Jul 02 09:07:17 AM PDT 24
Finished Jul 02 09:07:42 AM PDT 24
Peak memory 206404 kb
Host smart-ef995017-18fc-45b5-ae63-3333cf9403bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=349252129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.349252129
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1123609169
Short name T2219
Test name
Test status
Simulation time 152618031 ps
CPU time 0.83 seconds
Started Jul 02 09:07:21 AM PDT 24
Finished Jul 02 09:07:23 AM PDT 24
Peak memory 206188 kb
Host smart-95c425ab-eeb4-47ce-abd1-e92dd36d6496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11236
09169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1123609169
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1093453133
Short name T921
Test name
Test status
Simulation time 219408157 ps
CPU time 0.8 seconds
Started Jul 02 09:07:15 AM PDT 24
Finished Jul 02 09:07:18 AM PDT 24
Peak memory 206200 kb
Host smart-f4912179-1c28-43b9-9b8f-af41397e7e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10934
53133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1093453133
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.236232943
Short name T2218
Test name
Test status
Simulation time 549132311 ps
CPU time 1.62 seconds
Started Jul 02 09:07:16 AM PDT 24
Finished Jul 02 09:07:19 AM PDT 24
Peak memory 206440 kb
Host smart-b67560d1-974b-4fb8-9ecf-568260c0e546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23623
2943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.236232943
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.15785900
Short name T2590
Test name
Test status
Simulation time 418867499 ps
CPU time 1.17 seconds
Started Jul 02 09:07:20 AM PDT 24
Finished Jul 02 09:07:22 AM PDT 24
Peak memory 206140 kb
Host smart-7122dd17-467b-40f4-ac72-feb517bf439f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15785
900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.15785900
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.1472127555
Short name T2391
Test name
Test status
Simulation time 13668639013 ps
CPU time 28.07 seconds
Started Jul 02 09:07:17 AM PDT 24
Finished Jul 02 09:07:46 AM PDT 24
Peak memory 206472 kb
Host smart-7364ce13-4967-4163-a9cc-38db57104cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14721
27555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1472127555
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.697251325
Short name T669
Test name
Test status
Simulation time 455344996 ps
CPU time 1.39 seconds
Started Jul 02 09:07:18 AM PDT 24
Finished Jul 02 09:07:21 AM PDT 24
Peak memory 206192 kb
Host smart-fe311d96-97ca-401a-98bb-705995d534e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69725
1325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.697251325
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.438649710
Short name T2632
Test name
Test status
Simulation time 157909595 ps
CPU time 0.83 seconds
Started Jul 02 09:07:21 AM PDT 24
Finished Jul 02 09:07:22 AM PDT 24
Peak memory 206172 kb
Host smart-e22931e4-e83f-4610-8e3d-af80847f31a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43864
9710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.438649710
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2949141642
Short name T1329
Test name
Test status
Simulation time 77471018 ps
CPU time 0.78 seconds
Started Jul 02 09:07:22 AM PDT 24
Finished Jul 02 09:07:24 AM PDT 24
Peak memory 206156 kb
Host smart-8a2a594b-e4cb-47e4-960f-fb35571d6879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29491
41642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2949141642
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3961029927
Short name T1529
Test name
Test status
Simulation time 781756805 ps
CPU time 1.91 seconds
Started Jul 02 09:07:20 AM PDT 24
Finished Jul 02 09:07:22 AM PDT 24
Peak memory 206408 kb
Host smart-afee9ecc-e390-4bd5-9790-88790dde6da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39610
29927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3961029927
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3250327776
Short name T82
Test name
Test status
Simulation time 217675833 ps
CPU time 1.44 seconds
Started Jul 02 09:07:22 AM PDT 24
Finished Jul 02 09:07:24 AM PDT 24
Peak memory 206424 kb
Host smart-b7ce7900-19ad-43e4-93ca-c390cc9cd71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32503
27776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3250327776
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.4109625240
Short name T2111
Test name
Test status
Simulation time 180260164 ps
CPU time 0.88 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:31 AM PDT 24
Peak memory 206216 kb
Host smart-c3387edc-2414-4328-b400-30c930e23507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096
25240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.4109625240
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3715344545
Short name T2216
Test name
Test status
Simulation time 164835574 ps
CPU time 0.81 seconds
Started Jul 02 09:07:21 AM PDT 24
Finished Jul 02 09:07:23 AM PDT 24
Peak memory 206216 kb
Host smart-9092a7d3-8606-49ad-ac6a-e478eea6c81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37153
44545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3715344545
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3106647414
Short name T2174
Test name
Test status
Simulation time 183286133 ps
CPU time 0.92 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:27 AM PDT 24
Peak memory 206200 kb
Host smart-dcf617ff-a3f6-4a51-92b1-dab0ee5accdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066
47414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3106647414
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.1168326617
Short name T1371
Test name
Test status
Simulation time 8361357345 ps
CPU time 58.94 seconds
Started Jul 02 09:07:23 AM PDT 24
Finished Jul 02 09:08:22 AM PDT 24
Peak memory 206484 kb
Host smart-09f1f157-0e29-4e16-a627-65fec09082ba
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1168326617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.1168326617
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3004854812
Short name T1192
Test name
Test status
Simulation time 224624586 ps
CPU time 0.89 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:31 AM PDT 24
Peak memory 206216 kb
Host smart-a619fa6c-1819-4f20-b0aa-5aef312b497e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30048
54812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3004854812
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2674727385
Short name T505
Test name
Test status
Simulation time 23302821817 ps
CPU time 22.39 seconds
Started Jul 02 09:07:21 AM PDT 24
Finished Jul 02 09:07:44 AM PDT 24
Peak memory 206284 kb
Host smart-88bc722a-48c8-4ed9-aed0-2acaa344b7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26747
27385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2674727385
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3301084620
Short name T1080
Test name
Test status
Simulation time 3355610576 ps
CPU time 3.7 seconds
Started Jul 02 09:07:19 AM PDT 24
Finished Jul 02 09:07:24 AM PDT 24
Peak memory 206272 kb
Host smart-1b3c7afa-a61f-4954-932f-f3ecf7068099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33010
84620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3301084620
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2673604359
Short name T861
Test name
Test status
Simulation time 6812303766 ps
CPU time 66.95 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:08:33 AM PDT 24
Peak memory 206552 kb
Host smart-c57ffb2f-ff75-4f61-a6e8-ff1fdbdff871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26736
04359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2673604359
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.610550850
Short name T257
Test name
Test status
Simulation time 6001442259 ps
CPU time 55.72 seconds
Started Jul 02 09:07:19 AM PDT 24
Finished Jul 02 09:08:16 AM PDT 24
Peak memory 206408 kb
Host smart-0b066d2b-37cf-45d8-be6c-6b62f6f4a6b7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=610550850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.610550850
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1723151755
Short name T1137
Test name
Test status
Simulation time 237088488 ps
CPU time 0.94 seconds
Started Jul 02 09:07:21 AM PDT 24
Finished Jul 02 09:07:23 AM PDT 24
Peak memory 206180 kb
Host smart-261f446b-1838-47b9-bd1b-c9501f5b6268
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1723151755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1723151755
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3233239614
Short name T850
Test name
Test status
Simulation time 189516437 ps
CPU time 0.83 seconds
Started Jul 02 09:07:22 AM PDT 24
Finished Jul 02 09:07:23 AM PDT 24
Peak memory 206188 kb
Host smart-778d1b17-9361-4db7-99c2-5f453264bf9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32332
39614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3233239614
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2892364928
Short name T1547
Test name
Test status
Simulation time 5706158921 ps
CPU time 53.74 seconds
Started Jul 02 09:07:23 AM PDT 24
Finished Jul 02 09:08:17 AM PDT 24
Peak memory 206472 kb
Host smart-a7323e6c-aa05-4832-a1ae-65cbb06bdfb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28923
64928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2892364928
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2076428473
Short name T1874
Test name
Test status
Simulation time 5331635443 ps
CPU time 148.08 seconds
Started Jul 02 09:07:21 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 206376 kb
Host smart-ef3d0628-bc4c-4081-96e1-4d1c834374b8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2076428473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2076428473
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.2240895947
Short name T2602
Test name
Test status
Simulation time 181339536 ps
CPU time 0.85 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:31 AM PDT 24
Peak memory 206144 kb
Host smart-325f61f7-737a-4f6a-9a27-3a8c6b7fd64a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2240895947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.2240895947
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.4290383153
Short name T1364
Test name
Test status
Simulation time 158275277 ps
CPU time 0.84 seconds
Started Jul 02 09:07:21 AM PDT 24
Finished Jul 02 09:07:23 AM PDT 24
Peak memory 206204 kb
Host smart-371d89c4-1b67-4448-b36d-6d525f7ab68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42903
83153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.4290383153
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.378342541
Short name T139
Test name
Test status
Simulation time 217115846 ps
CPU time 0.93 seconds
Started Jul 02 09:07:22 AM PDT 24
Finished Jul 02 09:07:24 AM PDT 24
Peak memory 206164 kb
Host smart-57696f63-24e2-4520-8e5c-3a6f0cff471f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37834
2541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.378342541
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.726727925
Short name T334
Test name
Test status
Simulation time 182803278 ps
CPU time 0.91 seconds
Started Jul 02 09:07:20 AM PDT 24
Finished Jul 02 09:07:22 AM PDT 24
Peak memory 206184 kb
Host smart-cc72b33c-4aa9-4395-ada2-38babc333c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72672
7925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.726727925
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1209216042
Short name T370
Test name
Test status
Simulation time 207958423 ps
CPU time 0.83 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:31 AM PDT 24
Peak memory 206152 kb
Host smart-6073bc3f-175d-49f4-ab15-f7fc98a56aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
16042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1209216042
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3471558369
Short name T1739
Test name
Test status
Simulation time 184778601 ps
CPU time 0.82 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:31 AM PDT 24
Peak memory 206216 kb
Host smart-91735324-e6dd-4509-a8d4-cc4d32350809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34715
58369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3471558369
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.744430843
Short name T2658
Test name
Test status
Simulation time 157503962 ps
CPU time 0.83 seconds
Started Jul 02 09:07:20 AM PDT 24
Finished Jul 02 09:07:21 AM PDT 24
Peak memory 206208 kb
Host smart-c182ec0b-16c2-40dd-ad1c-49681b5ba54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74443
0843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.744430843
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3462344407
Short name T1944
Test name
Test status
Simulation time 256473866 ps
CPU time 0.94 seconds
Started Jul 02 09:07:19 AM PDT 24
Finished Jul 02 09:07:21 AM PDT 24
Peak memory 206196 kb
Host smart-58ddbef4-4fb5-48d3-810a-16024753ca9a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3462344407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3462344407
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.996867915
Short name T581
Test name
Test status
Simulation time 152148423 ps
CPU time 0.76 seconds
Started Jul 02 09:07:28 AM PDT 24
Finished Jul 02 09:07:29 AM PDT 24
Peak memory 206212 kb
Host smart-c0666948-0325-4763-a0ec-7250a2757078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99686
7915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.996867915
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1932063302
Short name T712
Test name
Test status
Simulation time 39722365 ps
CPU time 0.69 seconds
Started Jul 02 09:07:23 AM PDT 24
Finished Jul 02 09:07:24 AM PDT 24
Peak memory 206200 kb
Host smart-9206c3ca-70d6-4313-b068-4741260209c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19320
63302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1932063302
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3875225378
Short name T1037
Test name
Test status
Simulation time 20140553006 ps
CPU time 43.51 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:08:10 AM PDT 24
Peak memory 206524 kb
Host smart-adeff572-b5b8-4ddf-9fc8-37361233ef85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38752
25378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3875225378
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1460976514
Short name T1539
Test name
Test status
Simulation time 194418731 ps
CPU time 0.86 seconds
Started Jul 02 09:07:26 AM PDT 24
Finished Jul 02 09:07:28 AM PDT 24
Peak memory 206196 kb
Host smart-f740db8d-d23b-4cd7-ba3d-73ab39405677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14609
76514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1460976514
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2846513322
Short name T397
Test name
Test status
Simulation time 225423242 ps
CPU time 0.85 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:27 AM PDT 24
Peak memory 206172 kb
Host smart-d42dfd06-235c-47e4-8eff-c478c2fb4f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28465
13322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2846513322
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.3693112774
Short name T197
Test name
Test status
Simulation time 12321583862 ps
CPU time 114.06 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:09:20 AM PDT 24
Peak memory 206532 kb
Host smart-d3b7f34c-7153-4ca2-aed8-b91bd5c29ee3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3693112774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3693112774
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1013035874
Short name T538
Test name
Test status
Simulation time 4445316758 ps
CPU time 31.92 seconds
Started Jul 02 09:07:27 AM PDT 24
Finished Jul 02 09:07:59 AM PDT 24
Peak memory 206496 kb
Host smart-f5620db0-cd38-4162-89c4-8daa41186f47
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1013035874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1013035874
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1273286931
Short name T1933
Test name
Test status
Simulation time 11366988234 ps
CPU time 232.73 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:11:19 AM PDT 24
Peak memory 206512 kb
Host smart-f1b6bc87-e3be-400e-95a3-1f339660a84b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1273286931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1273286931
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2277654655
Short name T1974
Test name
Test status
Simulation time 218676397 ps
CPU time 0.91 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:27 AM PDT 24
Peak memory 206204 kb
Host smart-5635b7f6-2b6c-4b3a-b77a-2f7dd07b870d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22776
54655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2277654655
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.586570448
Short name T788
Test name
Test status
Simulation time 193328946 ps
CPU time 0.87 seconds
Started Jul 02 09:07:27 AM PDT 24
Finished Jul 02 09:07:28 AM PDT 24
Peak memory 206208 kb
Host smart-5e15bab9-6d3f-4522-97cc-2f76ab80d5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58657
0448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.586570448
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3631561085
Short name T2030
Test name
Test status
Simulation time 161583275 ps
CPU time 0.85 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:27 AM PDT 24
Peak memory 206168 kb
Host smart-71ae09e8-f587-4617-a709-60c50caf51c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36315
61085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3631561085
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2049912776
Short name T2551
Test name
Test status
Simulation time 173506304 ps
CPU time 0.82 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:27 AM PDT 24
Peak memory 206200 kb
Host smart-614286bd-1b09-4632-95a2-a56501269bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20499
12776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2049912776
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3960773443
Short name T2271
Test name
Test status
Simulation time 158150325 ps
CPU time 0.76 seconds
Started Jul 02 09:07:22 AM PDT 24
Finished Jul 02 09:07:24 AM PDT 24
Peak memory 206216 kb
Host smart-da4585ed-4c18-4ce0-a944-d067af37ca0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607
73443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3960773443
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1636527855
Short name T157
Test name
Test status
Simulation time 212406705 ps
CPU time 0.95 seconds
Started Jul 02 09:07:26 AM PDT 24
Finished Jul 02 09:07:28 AM PDT 24
Peak memory 206176 kb
Host smart-e5c86d32-1605-4ede-95ee-d9edfabd1062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16365
27855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1636527855
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3194648075
Short name T1196
Test name
Test status
Simulation time 5171722926 ps
CPU time 143.86 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 206480 kb
Host smart-3b049bc1-f15d-4941-906f-7b2c3400cb25
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3194648075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3194648075
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2631819960
Short name T647
Test name
Test status
Simulation time 198885230 ps
CPU time 0.82 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:27 AM PDT 24
Peak memory 206168 kb
Host smart-803c879e-2c97-4c9f-a9f2-285b86154a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26318
19960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2631819960
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2049442419
Short name T1059
Test name
Test status
Simulation time 176433200 ps
CPU time 0.88 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:27 AM PDT 24
Peak memory 206196 kb
Host smart-c07f6f32-6ace-4bf1-9f9d-17506290dc51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20494
42419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2049442419
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.1197983069
Short name T690
Test name
Test status
Simulation time 1096740891 ps
CPU time 2.23 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:29 AM PDT 24
Peak memory 206404 kb
Host smart-414301d3-5ddc-48fb-ad74-99d35afe6283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11979
83069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.1197983069
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.1711749718
Short name T985
Test name
Test status
Simulation time 4852793132 ps
CPU time 32.41 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:08:03 AM PDT 24
Peak memory 206524 kb
Host smart-d5e51bd9-981f-405e-8f82-a02dc939fb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17117
49718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1711749718
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.2577885004
Short name T870
Test name
Test status
Simulation time 48624148 ps
CPU time 0.66 seconds
Started Jul 02 09:07:40 AM PDT 24
Finished Jul 02 09:07:43 AM PDT 24
Peak memory 206184 kb
Host smart-ce4c3001-4b03-4666-a788-7aa189f15fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2577885004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.2577885004
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2322029882
Short name T872
Test name
Test status
Simulation time 4231252291 ps
CPU time 5.19 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:31 AM PDT 24
Peak memory 206252 kb
Host smart-135629cb-45e9-4ff4-a5c2-58fdf8339e4b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2322029882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2322029882
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3126570744
Short name T7
Test name
Test status
Simulation time 13423231620 ps
CPU time 14.28 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206224 kb
Host smart-c2cb2fbf-d8bd-42b6-8a2d-c919641b98ed
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3126570744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3126570744
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.2286716577
Short name T2587
Test name
Test status
Simulation time 23472334588 ps
CPU time 28.01 seconds
Started Jul 02 09:07:23 AM PDT 24
Finished Jul 02 09:07:52 AM PDT 24
Peak memory 206456 kb
Host smart-a724c3d2-0cdc-4c31-894d-dd09e2f730b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2286716577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.2286716577
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1017028921
Short name T2342
Test name
Test status
Simulation time 147878480 ps
CPU time 0.77 seconds
Started Jul 02 09:07:24 AM PDT 24
Finished Jul 02 09:07:26 AM PDT 24
Peak memory 206128 kb
Host smart-7d8a5b1e-e1e1-4e6c-9c31-b70b70435023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10170
28921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1017028921
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.3163702264
Short name T65
Test name
Test status
Simulation time 158668097 ps
CPU time 0.86 seconds
Started Jul 02 09:07:24 AM PDT 24
Finished Jul 02 09:07:25 AM PDT 24
Peak memory 206204 kb
Host smart-ac820615-ac02-465a-906c-8b02a34d1eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31637
02264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3163702264
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.1989184641
Short name T2042
Test name
Test status
Simulation time 235898403 ps
CPU time 0.91 seconds
Started Jul 02 09:07:25 AM PDT 24
Finished Jul 02 09:07:27 AM PDT 24
Peak memory 206212 kb
Host smart-f95a3574-4ba4-4744-8d95-b6c20113cde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19891
84641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.1989184641
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1241517807
Short name T947
Test name
Test status
Simulation time 912519597 ps
CPU time 2.21 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:33 AM PDT 24
Peak memory 206444 kb
Host smart-dedf7aee-4215-4486-b3c0-468d95d8fec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12415
17807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1241517807
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1181253783
Short name T1688
Test name
Test status
Simulation time 12339502472 ps
CPU time 22.8 seconds
Started Jul 02 09:07:30 AM PDT 24
Finished Jul 02 09:07:53 AM PDT 24
Peak memory 206528 kb
Host smart-e9d58c6d-24ba-45a6-ad01-be49b3c04274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11812
53783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1181253783
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3586740206
Short name T475
Test name
Test status
Simulation time 428372647 ps
CPU time 1.45 seconds
Started Jul 02 09:07:32 AM PDT 24
Finished Jul 02 09:07:34 AM PDT 24
Peak memory 206184 kb
Host smart-e348acba-a927-4009-a63d-c7450ceacfd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35867
40206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3586740206
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.4205345683
Short name T1285
Test name
Test status
Simulation time 150216249 ps
CPU time 0.83 seconds
Started Jul 02 09:07:35 AM PDT 24
Finished Jul 02 09:07:36 AM PDT 24
Peak memory 206224 kb
Host smart-3477a15f-df63-46fa-9951-0a7c922767e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42053
45683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.4205345683
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.4008359762
Short name T1316
Test name
Test status
Simulation time 43420174 ps
CPU time 0.71 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:07:42 AM PDT 24
Peak memory 206192 kb
Host smart-c4695b80-4bb3-4ff5-8692-82064c927b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40083
59762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.4008359762
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3739487577
Short name T646
Test name
Test status
Simulation time 1129234465 ps
CPU time 2.56 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:32 AM PDT 24
Peak memory 206448 kb
Host smart-fb35d643-eb56-4962-ba59-3945ba5eea4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37394
87577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3739487577
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2866166380
Short name T433
Test name
Test status
Simulation time 206857463 ps
CPU time 1.4 seconds
Started Jul 02 09:07:28 AM PDT 24
Finished Jul 02 09:07:30 AM PDT 24
Peak memory 206388 kb
Host smart-84cb7415-6fad-433c-82b5-cf2c8d08a150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28661
66380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2866166380
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2375281041
Short name T2448
Test name
Test status
Simulation time 198745860 ps
CPU time 1 seconds
Started Jul 02 09:07:33 AM PDT 24
Finished Jul 02 09:07:34 AM PDT 24
Peak memory 206204 kb
Host smart-279bd88d-938a-4e72-81db-6e8206e92106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23752
81041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2375281041
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3963326845
Short name T2179
Test name
Test status
Simulation time 139133693 ps
CPU time 0.78 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:30 AM PDT 24
Peak memory 206196 kb
Host smart-cded6ff1-3715-4f9c-a590-b8c4e64f230d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39633
26845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3963326845
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.995100325
Short name T849
Test name
Test status
Simulation time 258030969 ps
CPU time 0.96 seconds
Started Jul 02 09:07:36 AM PDT 24
Finished Jul 02 09:07:38 AM PDT 24
Peak memory 206208 kb
Host smart-c9c66c95-9413-4da5-a0c2-e95037ca394e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99510
0325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.995100325
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.911449891
Short name T75
Test name
Test status
Simulation time 10041007589 ps
CPU time 261.1 seconds
Started Jul 02 09:07:37 AM PDT 24
Finished Jul 02 09:12:00 AM PDT 24
Peak memory 206544 kb
Host smart-516a7c8c-cedd-4efa-9e69-7c0e378ddfef
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=911449891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.911449891
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.712735448
Short name T2564
Test name
Test status
Simulation time 225920384 ps
CPU time 0.98 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206136 kb
Host smart-2285dc02-d4db-4cca-917b-2bd48cf40c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71273
5448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.712735448
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.2323105655
Short name T1122
Test name
Test status
Simulation time 23354617600 ps
CPU time 23.49 seconds
Started Jul 02 09:07:36 AM PDT 24
Finished Jul 02 09:08:01 AM PDT 24
Peak memory 206228 kb
Host smart-43e55e98-b0d2-4311-bb1f-cf6622e8c6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23231
05655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.2323105655
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3179654921
Short name T1065
Test name
Test status
Simulation time 3352696019 ps
CPU time 3.97 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:34 AM PDT 24
Peak memory 206232 kb
Host smart-08a1a93f-6517-47e0-8afa-a32f906c1bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31796
54921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3179654921
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2728989110
Short name T1223
Test name
Test status
Simulation time 5405652177 ps
CPU time 153.99 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:10:16 AM PDT 24
Peak memory 206572 kb
Host smart-64078da5-9a79-4f85-af5e-95e6a665ff77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27289
89110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2728989110
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.134363200
Short name T873
Test name
Test status
Simulation time 2895753820 ps
CPU time 28.8 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:08:10 AM PDT 24
Peak memory 206652 kb
Host smart-f2b91b71-de1f-4297-86b6-86cdf07a3268
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=134363200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.134363200
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.58762570
Short name T1399
Test name
Test status
Simulation time 237650303 ps
CPU time 0.96 seconds
Started Jul 02 09:07:33 AM PDT 24
Finished Jul 02 09:07:35 AM PDT 24
Peak memory 206184 kb
Host smart-7467a914-e497-4130-83fa-a308d64fb338
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=58762570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.58762570
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1710640072
Short name T404
Test name
Test status
Simulation time 196026903 ps
CPU time 0.83 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:31 AM PDT 24
Peak memory 206212 kb
Host smart-c867250d-f15b-44dc-9146-9fe8f94bdecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17106
40072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1710640072
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.1669608215
Short name T2406
Test name
Test status
Simulation time 6034502209 ps
CPU time 57.32 seconds
Started Jul 02 09:07:37 AM PDT 24
Finished Jul 02 09:08:36 AM PDT 24
Peak memory 206468 kb
Host smart-3af374a5-da94-45b1-a539-4e5b9d6420e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16696
08215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.1669608215
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.2370280573
Short name T1683
Test name
Test status
Simulation time 5695645073 ps
CPU time 54.37 seconds
Started Jul 02 09:07:28 AM PDT 24
Finished Jul 02 09:08:23 AM PDT 24
Peak memory 206488 kb
Host smart-89ccce23-9800-40b8-b9d1-cf4fc44000e9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2370280573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.2370280573
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3099165615
Short name T1354
Test name
Test status
Simulation time 162630211 ps
CPU time 0.8 seconds
Started Jul 02 09:07:36 AM PDT 24
Finished Jul 02 09:07:38 AM PDT 24
Peak memory 206176 kb
Host smart-0fc5574f-9b24-4417-ad27-a6ca971b173b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3099165615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3099165615
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2342079179
Short name T1794
Test name
Test status
Simulation time 183523500 ps
CPU time 0.78 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206204 kb
Host smart-bd8d2241-6ac3-4c8c-bd0f-c34a2ff3ecba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23420
79179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2342079179
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1583221075
Short name T136
Test name
Test status
Simulation time 211164765 ps
CPU time 0.88 seconds
Started Jul 02 09:07:29 AM PDT 24
Finished Jul 02 09:07:31 AM PDT 24
Peak memory 206200 kb
Host smart-72399dd0-6108-4ca1-ad9c-d1ee2222b196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15832
21075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1583221075
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2894905519
Short name T714
Test name
Test status
Simulation time 180054791 ps
CPU time 0.89 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206144 kb
Host smart-9a4dd684-98d8-475a-9bc9-85bbfb93af75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28949
05519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2894905519
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.463005668
Short name T2007
Test name
Test status
Simulation time 166156389 ps
CPU time 0.79 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206212 kb
Host smart-504358d6-a9c4-4a5a-a9fd-657887805969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46300
5668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.463005668
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3575606684
Short name T896
Test name
Test status
Simulation time 176611833 ps
CPU time 0.82 seconds
Started Jul 02 09:07:37 AM PDT 24
Finished Jul 02 09:07:38 AM PDT 24
Peak memory 206168 kb
Host smart-b37fce96-4382-4aeb-89be-7433e664fc69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35756
06684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3575606684
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.849644489
Short name T841
Test name
Test status
Simulation time 167084556 ps
CPU time 0.8 seconds
Started Jul 02 09:07:37 AM PDT 24
Finished Jul 02 09:07:40 AM PDT 24
Peak memory 206216 kb
Host smart-a57c16eb-75e4-43ca-9992-eb464a828152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84964
4489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.849644489
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.1944137945
Short name T1068
Test name
Test status
Simulation time 197830249 ps
CPU time 0.87 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206200 kb
Host smart-93602a72-1461-4014-be34-5295534c5e0b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1944137945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1944137945
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1314455994
Short name T2490
Test name
Test status
Simulation time 173920117 ps
CPU time 0.77 seconds
Started Jul 02 09:07:33 AM PDT 24
Finished Jul 02 09:07:35 AM PDT 24
Peak memory 206128 kb
Host smart-a0a9da4e-ae79-45e3-b45f-d0b333fbde87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13144
55994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1314455994
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.4069021932
Short name T953
Test name
Test status
Simulation time 31112820 ps
CPU time 0.66 seconds
Started Jul 02 09:07:41 AM PDT 24
Finished Jul 02 09:07:45 AM PDT 24
Peak memory 206188 kb
Host smart-a076dced-ccbd-4cf2-b232-c121c24a2f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40690
21932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.4069021932
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.4098034036
Short name T255
Test name
Test status
Simulation time 20730069338 ps
CPU time 44.18 seconds
Started Jul 02 09:07:35 AM PDT 24
Finished Jul 02 09:08:19 AM PDT 24
Peak memory 206504 kb
Host smart-cee81f11-df15-4809-a3fa-b38adfdbfdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40980
34036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.4098034036
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3000268927
Short name T1074
Test name
Test status
Simulation time 206176278 ps
CPU time 0.9 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:42 AM PDT 24
Peak memory 206172 kb
Host smart-f24108d2-74ee-4284-8458-c4893071cfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30002
68927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3000268927
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1441751081
Short name T727
Test name
Test status
Simulation time 247944621 ps
CPU time 0.88 seconds
Started Jul 02 09:07:37 AM PDT 24
Finished Jul 02 09:07:40 AM PDT 24
Peak memory 206176 kb
Host smart-ac4eb3cb-c7b8-4f53-bf34-5d17e95feaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14417
51081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1441751081
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1598961233
Short name T2513
Test name
Test status
Simulation time 6376313286 ps
CPU time 54.66 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:08:37 AM PDT 24
Peak memory 206384 kb
Host smart-6b1d5b13-319b-44a0-a36d-d0bfdc0e60d0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1598961233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1598961233
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.4241516114
Short name T704
Test name
Test status
Simulation time 20791316909 ps
CPU time 151.19 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:10:12 AM PDT 24
Peak memory 206512 kb
Host smart-c95fcec0-f24e-4ee3-9ccd-6b6d2291d1b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4241516114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.4241516114
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2373571803
Short name T2521
Test name
Test status
Simulation time 232968359 ps
CPU time 0.94 seconds
Started Jul 02 09:07:35 AM PDT 24
Finished Jul 02 09:07:36 AM PDT 24
Peak memory 206124 kb
Host smart-4578cfb4-fd13-49c1-9739-ffe044f5d971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23735
71803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2373571803
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2887690087
Short name T854
Test name
Test status
Simulation time 148285499 ps
CPU time 0.78 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:41 AM PDT 24
Peak memory 206212 kb
Host smart-ddc89dd9-61c5-4927-9684-ac0ca60c8c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28876
90087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2887690087
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1983637361
Short name T961
Test name
Test status
Simulation time 170793035 ps
CPU time 0.81 seconds
Started Jul 02 09:07:32 AM PDT 24
Finished Jul 02 09:07:33 AM PDT 24
Peak memory 206200 kb
Host smart-5e6c54d3-5a97-4f2f-a2ca-73da2f1ad519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19836
37361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1983637361
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.294339206
Short name T362
Test name
Test status
Simulation time 171034109 ps
CPU time 0.76 seconds
Started Jul 02 09:07:43 AM PDT 24
Finished Jul 02 09:07:46 AM PDT 24
Peak memory 206212 kb
Host smart-63a7b63a-b562-472c-87cb-fe7f8425aab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29433
9206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.294339206
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.926655563
Short name T2200
Test name
Test status
Simulation time 156031159 ps
CPU time 0.79 seconds
Started Jul 02 09:07:43 AM PDT 24
Finished Jul 02 09:07:46 AM PDT 24
Peak memory 206172 kb
Host smart-9a043406-4996-467c-afb1-cb662c739abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92665
5563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.926655563
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1105363575
Short name T777
Test name
Test status
Simulation time 229319893 ps
CPU time 1.05 seconds
Started Jul 02 09:07:33 AM PDT 24
Finished Jul 02 09:07:35 AM PDT 24
Peak memory 206188 kb
Host smart-a2b7d2a6-8439-44f2-a1ed-c0791ec2db30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11053
63575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1105363575
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.1166843881
Short name T544
Test name
Test status
Simulation time 3417260608 ps
CPU time 23.2 seconds
Started Jul 02 09:07:42 AM PDT 24
Finished Jul 02 09:08:08 AM PDT 24
Peak memory 206452 kb
Host smart-aaec1932-9e6a-414c-bf2e-e38473014e1e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1166843881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.1166843881
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.623001425
Short name T2133
Test name
Test status
Simulation time 177006256 ps
CPU time 0.81 seconds
Started Jul 02 09:07:38 AM PDT 24
Finished Jul 02 09:07:42 AM PDT 24
Peak memory 206200 kb
Host smart-a673d982-1b90-4bd9-84dd-968d58c3c47e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62300
1425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.623001425
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3099879586
Short name T1332
Test name
Test status
Simulation time 140824507 ps
CPU time 0.75 seconds
Started Jul 02 09:07:34 AM PDT 24
Finished Jul 02 09:07:35 AM PDT 24
Peak memory 206172 kb
Host smart-bbf5af69-dcf3-4e9e-bb5a-a587aa08b79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30998
79586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3099879586
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3732586342
Short name T1335
Test name
Test status
Simulation time 330509711 ps
CPU time 1.07 seconds
Started Jul 02 09:07:39 AM PDT 24
Finished Jul 02 09:07:43 AM PDT 24
Peak memory 206344 kb
Host smart-1a219ff5-c8d6-46dd-9905-1ede6a75e78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37325
86342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3732586342
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2072220150
Short name T358
Test name
Test status
Simulation time 7873627519 ps
CPU time 59.19 seconds
Started Jul 02 09:07:37 AM PDT 24
Finished Jul 02 09:08:38 AM PDT 24
Peak memory 206448 kb
Host smart-df85e517-bcf4-4d11-bf29-36495bbb88f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20722
20150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2072220150
Directory /workspace/9.usbdev_streaming_out/latest
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