Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	168263	1		T1	2		T2	2		T3	2
all_values[1]	168263	1		T1	2		T2	2		T3	2
all_values[2]	168263	1		T1	2		T2	2		T3	2
all_values[3]	168263	1		T1	2		T2	2		T3	2
all_values[4]	168263	1		T1	2		T2	2		T3	2
all_values[5]	168263	1		T1	2		T2	2		T3	2
all_values[6]	168263	1		T1	2		T2	2		T3	2
all_values[7]	168263	1		T1	2		T2	2		T3	2
all_values[8]	168263	1		T1	2		T2	2		T3	2
all_values[9]	168263	1		T1	2		T2	2		T3	2
all_values[10]	168263	1		T1	2		T2	2		T3	2
all_values[11]	168263	1		T1	2		T2	2		T3	2
all_values[12]	168263	1		T1	2		T2	2		T3	2
all_values[13]	168263	1		T1	2		T2	2		T3	2
all_values[14]	168263	1		T1	2		T2	2		T3	2
all_values[15]	168263	1		T1	2		T2	2		T3	2
all_values[16]	168263	1		T1	2		T2	2		T3	2
all_values[17]	168263	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3022128	1		T1	36		T2	36		T3	36
auto[1]	6606	1		T33	3		T57	2		T58	5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3024117	1		T1	36		T2	36		T3	36
auto[1]	4617	1		T230	71		T231	72		T227	122

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	167304	1		T1	2		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	109	1		T230	1		T231	3		T227	3
all_values[0]	auto[1]	auto[0]	699	1		T56	4		T18	3		T60	3
all_values[0]	auto[1]	auto[1]	151	1		T230	4		T231	2		T227	5
all_values[1]	auto[0]	auto[0]	166484	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	145	1		T230	1		T231	3		T227	5
all_values[1]	auto[1]	auto[0]	1526	1		T33	3		T42	2		T5	2
all_values[1]	auto[1]	auto[1]	108	1		T230	4		T227	3		T232	1
all_values[2]	auto[0]	auto[0]	167880	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	126	1		T231	3		T227	1		T232	3
all_values[2]	auto[1]	auto[0]	136	1		T52	2		T53	2		T54	2
all_values[2]	auto[1]	auto[1]	121	1		T227	5		T228	5		T229	5
all_values[3]	auto[0]	auto[0]	166589	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	133	1		T230	4		T227	3		T228	1
all_values[3]	auto[1]	auto[0]	1424	1		T78	1396		T231	1		T227	2
all_values[3]	auto[1]	auto[1]	117	1		T230	1		T227	1		T228	4
all_values[4]	auto[0]	auto[0]	167977	1		T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	150	1		T230	4		T231	4		T227	4
all_values[4]	auto[1]	auto[0]	23	1		T79	2		T227	2		T307	1
all_values[4]	auto[1]	auto[1]	113	1		T230	1		T227	1		T229	3
all_values[5]	auto[0]	auto[0]	167986	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	135	1		T231	4		T227	4		T232	4
all_values[5]	auto[1]	auto[0]	29	1		T230	1		T227	1		T311	1
all_values[5]	auto[1]	auto[1]	113	1		T231	1		T227	2		T228	2
all_values[6]	auto[0]	auto[0]	167988	1		T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	120	1		T230	2		T227	4		T232	1
all_values[6]	auto[1]	auto[0]	31	1		T227	1		T232	1		T229	2
all_values[6]	auto[1]	auto[1]	124	1		T230	3		T231	5		T227	2
all_values[7]	auto[0]	auto[0]	167984	1		T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	110	1		T230	1		T231	5		T227	5
all_values[7]	auto[1]	auto[0]	36	1		T63	2		T64	2		T65	2
all_values[7]	auto[1]	auto[1]	133	1		T230	4		T227	1		T229	2
all_values[8]	auto[0]	auto[0]	167956	1		T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	122	1		T230	4		T231	4		T227	6
all_values[8]	auto[1]	auto[0]	31	1		T68	11		T230	1		T227	1
all_values[8]	auto[1]	auto[1]	154	1		T231	1		T227	1		T232	4
all_values[9]	auto[0]	auto[0]	167946	1		T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	136	1		T230	4		T231	1		T227	7
all_values[9]	auto[1]	auto[0]	43	1		T58	5		T76	5		T77	5
all_values[9]	auto[1]	auto[1]	138	1		T230	1		T231	4		T227	1
all_values[10]	auto[0]	auto[0]	167973	1		T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	129	1		T230	4		T227	5		T232	2
all_values[10]	auto[1]	auto[0]	23	1		T228	1		T307	1		T312	1
all_values[10]	auto[1]	auto[1]	138	1		T231	5		T227	3		T232	3
all_values[11]	auto[0]	auto[0]	167882	1		T1	2		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	123	1		T230	4		T231	5		T227	2
all_values[11]	auto[1]	auto[0]	123	1		T57	2		T82	2		T83	2
all_values[11]	auto[1]	auto[1]	135	1		T227	5		T232	3		T229	7
all_values[12]	auto[0]	auto[0]	167962	1		T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	124	1		T231	1		T227	2		T232	2
all_values[12]	auto[1]	auto[0]	40	1		T86	3		T87	3		T88	3
all_values[12]	auto[1]	auto[1]	137	1		T231	3		T227	6		T232	3
all_values[13]	auto[0]	auto[0]	167982	1		T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	154	1		T230	4		T227	5		T232	3
all_values[13]	auto[1]	auto[0]	23	1		T231	3		T227	1		T313	4
all_values[13]	auto[1]	auto[1]	104	1		T227	2		T232	1		T228	2
all_values[14]	auto[0]	auto[0]	167982	1		T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	125	1		T230	4		T231	1		T227	2
all_values[14]	auto[1]	auto[0]	30	1		T227	1		T232	1		T229	2
all_values[14]	auto[1]	auto[1]	126	1		T230	1		T231	4		T227	4
all_values[15]	auto[0]	auto[0]	167986	1		T1	2		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	130	1		T230	2		T231	4		T227	7
all_values[15]	auto[1]	auto[0]	20	1		T228	1		T311	1		T308	1
all_values[15]	auto[1]	auto[1]	127	1		T230	3		T227	1		T228	1
all_values[16]	auto[0]	auto[0]	167958	1		T1	2		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	136	1		T230	1		T231	5		T227	5
all_values[16]	auto[1]	auto[0]	52	1		T59	8		T80	8		T81	8
all_values[16]	auto[1]	auto[1]	117	1		T230	4		T227	2		T232	4
all_values[17]	auto[0]	auto[0]	167974	1		T1	2		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	128	1		T230	3		T231	3		T227	3
all_values[17]	auto[1]	auto[0]	35	1		T70	2		T71	2		T227	1
all_values[17]	auto[1]	auto[1]	126	1		T230	2		T231	1		T227	4