Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	168263	1		T1	2		T2	2		T3	2
all_pins[1]	168263	1		T1	2		T2	2		T3	2
all_pins[2]	168263	1		T1	2		T2	2		T3	2
all_pins[3]	168263	1		T1	2		T2	2		T3	2
all_pins[4]	168263	1		T1	2		T2	2		T3	2
all_pins[5]	168263	1		T1	2		T2	2		T3	2
all_pins[6]	168263	1		T1	2		T2	2		T3	2
all_pins[7]	168263	1		T1	2		T2	2		T3	2
all_pins[8]	168263	1		T1	2		T2	2		T3	2
all_pins[9]	168263	1		T1	2		T2	2		T3	2
all_pins[10]	168263	1		T1	2		T2	2		T3	2
all_pins[11]	168263	1		T1	2		T2	2		T3	2
all_pins[12]	168263	1		T1	2		T2	2		T3	2
all_pins[13]	168263	1		T1	2		T2	2		T3	2
all_pins[14]	168263	1		T1	2		T2	2		T3	2
all_pins[15]	168263	1		T1	2		T2	2		T3	2
all_pins[16]	168263	1		T1	2		T2	2		T3	2
all_pins[17]	168263	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3026504	1		T1	36		T2	36		T3	36
values[0x1]	2230	1		T33	1		T57	1		T58	2
transitions[0x0=>0x1]	1945	1		T33	1		T57	1		T58	2
transitions[0x1=>0x0]	1959	1		T33	1		T57	1		T58	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	168150	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	113	1		T56	1		T314	1		T315	1
all_pins[0]	transitions[0x0=>0x1]	98	1		T56	1		T314	1		T315	1
all_pins[0]	transitions[0x1=>0x0]	989	1		T33	1		T42	1		T5	1
all_pins[1]	values[0x0]	167259	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	1004	1		T33	1		T42	1		T5	1
all_pins[1]	transitions[0x0=>0x1]	990	1		T33	1		T42	1		T5	1
all_pins[1]	transitions[0x1=>0x0]	105	1		T52	1		T53	1		T54	1
all_pins[2]	values[0x0]	168144	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	119	1		T52	1		T53	1		T54	1
all_pins[2]	transitions[0x0=>0x1]	102	1		T52	1		T53	1		T54	1
all_pins[2]	transitions[0x1=>0x0]	48	1		T78	1		T230	1		T228	1
all_pins[3]	values[0x0]	168198	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	65	1		T78	1		T230	1		T227	1
all_pins[3]	transitions[0x0=>0x1]	55	1		T78	1		T230	1		T227	1
all_pins[3]	transitions[0x1=>0x0]	44	1		T79	1		T230	1		T227	1
all_pins[4]	values[0x0]	168209	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	54	1		T79	1		T230	1		T227	1
all_pins[4]	transitions[0x0=>0x1]	40	1		T79	1		T230	1		T227	1
all_pins[4]	transitions[0x1=>0x0]	39	1		T231	1		T227	1		T228	2
all_pins[5]	values[0x0]	168210	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	53	1		T231	1		T227	1		T228	2
all_pins[5]	transitions[0x0=>0x1]	43	1		T227	1		T228	1		T229	1
all_pins[5]	transitions[0x1=>0x0]	39	1		T227	1		T229	1		T311	4
all_pins[6]	values[0x0]	168214	1		T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	49	1		T231	1		T227	1		T228	1
all_pins[6]	transitions[0x0=>0x1]	40	1		T231	1		T227	1		T228	1
all_pins[6]	transitions[0x1=>0x0]	41	1		T63	1		T64	1		T65	1
all_pins[7]	values[0x0]	168213	1		T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	50	1		T63	1		T64	1		T65	1
all_pins[7]	transitions[0x0=>0x1]	33	1		T63	1		T64	1		T65	1
all_pins[7]	transitions[0x1=>0x0]	52	1		T68	1		T231	1		T232	2
all_pins[8]	values[0x0]	168194	1		T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	69	1		T68	1		T231	1		T232	2
all_pins[8]	transitions[0x0=>0x1]	48	1		T68	1		T232	2		T228	1
all_pins[8]	transitions[0x1=>0x0]	63	1		T58	2		T76	2		T77	2
all_pins[9]	values[0x0]	168179	1		T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	84	1		T58	2		T76	2		T77	2
all_pins[9]	transitions[0x0=>0x1]	69	1		T58	2		T76	2		T77	2
all_pins[9]	transitions[0x1=>0x0]	41	1		T227	1		T311	1		T316	1
all_pins[10]	values[0x0]	168207	1		T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	56	1		T231	1		T227	1		T311	2
all_pins[10]	transitions[0x0=>0x1]	37	1		T231	1		T227	1		T311	2
all_pins[10]	transitions[0x1=>0x0]	109	1		T57	1		T82	1		T83	1
all_pins[11]	values[0x0]	168135	1		T1	2		T2	2		T3	2
all_pins[11]	values[0x1]	128	1		T57	1		T82	1		T83	1
all_pins[11]	transitions[0x0=>0x1]	107	1		T57	1		T82	1		T83	1
all_pins[11]	transitions[0x1=>0x0]	51	1		T86	1		T87	1		T88	1
all_pins[12]	values[0x0]	168191	1		T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	72	1		T86	1		T87	1		T88	1
all_pins[12]	transitions[0x0=>0x1]	59	1		T86	1		T87	1		T88	1
all_pins[12]	transitions[0x1=>0x0]	37	1		T227	1		T232	1		T228	1
all_pins[13]	values[0x0]	168213	1		T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	50	1		T227	1		T232	1		T228	1
all_pins[13]	transitions[0x0=>0x1]	34	1		T227	1		T228	1		T229	4
all_pins[13]	transitions[0x1=>0x0]	60	1		T230	1		T231	2		T227	3
all_pins[14]	values[0x0]	168187	1		T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	76	1		T230	1		T231	2		T227	3
all_pins[14]	transitions[0x0=>0x1]	53	1		T230	1		T231	2		T227	3
all_pins[14]	transitions[0x1=>0x0]	38	1		T227	1		T228	1		T229	1
all_pins[15]	values[0x0]	168202	1		T1	2		T2	2		T3	2
all_pins[15]	values[0x1]	61	1		T227	1		T228	1		T229	1
all_pins[15]	transitions[0x0=>0x1]	47	1		T227	1		T307	2		T313	1
all_pins[15]	transitions[0x1=>0x0]	60	1		T59	4		T80	4		T81	4
all_pins[16]	values[0x0]	168189	1		T1	2		T2	2		T3	2
all_pins[16]	values[0x1]	74	1		T59	4		T80	4		T81	4
all_pins[16]	transitions[0x0=>0x1]	64	1		T59	4		T80	4		T81	4
all_pins[16]	transitions[0x1=>0x0]	43	1		T70	1		T71	1		T230	1
all_pins[17]	values[0x0]	168210	1		T1	2		T2	2		T3	2
all_pins[17]	values[0x1]	53	1		T70	1		T71	1		T230	2
all_pins[17]	transitions[0x0=>0x1]	26	1		T70	1		T71	1		T227	1
all_pins[17]	transitions[0x1=>0x0]	100	1		T56	1		T314	1		T315	1