Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.59 97.84 93.81 97.44 75.00 96.26 98.17 96.58


Total test records in report: 2815
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T2760 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2223075252 Jul 03 04:31:59 PM PDT 24 Jul 03 04:32:02 PM PDT 24 113976293 ps
T2761 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2034678395 Jul 03 04:32:18 PM PDT 24 Jul 03 04:32:19 PM PDT 24 47417350 ps
T2762 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.87227274 Jul 03 04:31:41 PM PDT 24 Jul 03 04:31:48 PM PDT 24 150052242 ps
T2763 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3443608934 Jul 03 04:32:10 PM PDT 24 Jul 03 04:32:11 PM PDT 24 42294728 ps
T2764 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3654060787 Jul 03 04:32:45 PM PDT 24 Jul 03 04:32:48 PM PDT 24 109484611 ps
T2765 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.943895379 Jul 03 04:31:47 PM PDT 24 Jul 03 04:31:48 PM PDT 24 92563724 ps
T326 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2631398234 Jul 03 04:31:48 PM PDT 24 Jul 03 04:31:51 PM PDT 24 457884526 ps
T2766 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2253751137 Jul 03 04:31:53 PM PDT 24 Jul 03 04:31:54 PM PDT 24 77821066 ps
T2767 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1569538462 Jul 03 04:31:56 PM PDT 24 Jul 03 04:31:59 PM PDT 24 847334463 ps
T286 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2707714915 Jul 03 04:32:06 PM PDT 24 Jul 03 04:32:08 PM PDT 24 183574288 ps
T328 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1294687105 Jul 03 04:32:14 PM PDT 24 Jul 03 04:32:18 PM PDT 24 1052775235 ps
T2768 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.922669991 Jul 03 04:31:56 PM PDT 24 Jul 03 04:32:00 PM PDT 24 214197000 ps
T2769 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2238612860 Jul 03 04:31:42 PM PDT 24 Jul 03 04:31:44 PM PDT 24 130672309 ps
T2770 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1593182835 Jul 03 04:31:48 PM PDT 24 Jul 03 04:31:55 PM PDT 24 139555411 ps
T2771 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.546220243 Jul 03 04:32:46 PM PDT 24 Jul 03 04:32:48 PM PDT 24 61904745 ps
T2772 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.119715789 Jul 03 04:31:58 PM PDT 24 Jul 03 04:32:01 PM PDT 24 147545224 ps
T2773 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.875734861 Jul 03 04:31:53 PM PDT 24 Jul 03 04:31:54 PM PDT 24 40118096 ps
T2774 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2274199108 Jul 03 04:31:47 PM PDT 24 Jul 03 04:31:48 PM PDT 24 42012166 ps
T2775 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3706368238 Jul 03 04:32:17 PM PDT 24 Jul 03 04:32:24 PM PDT 24 137419326 ps
T2776 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2079034720 Jul 03 04:32:15 PM PDT 24 Jul 03 04:32:16 PM PDT 24 111971369 ps
T2777 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2301574434 Jul 03 04:31:48 PM PDT 24 Jul 03 04:31:50 PM PDT 24 123972893 ps
T2778 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2508679796 Jul 03 04:32:10 PM PDT 24 Jul 03 04:32:11 PM PDT 24 35593666 ps
T2779 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4292432609 Jul 03 04:31:47 PM PDT 24 Jul 03 04:31:49 PM PDT 24 50125578 ps
T2780 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2552859751 Jul 03 04:31:57 PM PDT 24 Jul 03 04:32:01 PM PDT 24 101577747 ps
T2781 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3466632853 Jul 03 04:32:24 PM PDT 24 Jul 03 04:32:25 PM PDT 24 47141320 ps
T2782 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1777149732 Jul 03 04:31:39 PM PDT 24 Jul 03 04:31:43 PM PDT 24 531925102 ps
T2783 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.870163315 Jul 03 04:31:39 PM PDT 24 Jul 03 04:31:40 PM PDT 24 116536194 ps
T2784 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3133899891 Jul 03 04:31:58 PM PDT 24 Jul 03 04:32:00 PM PDT 24 101255425 ps
T2785 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3194148959 Jul 03 04:31:48 PM PDT 24 Jul 03 04:31:51 PM PDT 24 117640354 ps
T2786 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2005325280 Jul 03 04:31:48 PM PDT 24 Jul 03 04:31:50 PM PDT 24 77179466 ps
T2787 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3551736542 Jul 03 04:32:00 PM PDT 24 Jul 03 04:32:03 PM PDT 24 122640024 ps
T2788 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1080655711 Jul 03 04:31:52 PM PDT 24 Jul 03 04:31:54 PM PDT 24 53360030 ps
T2789 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2800255787 Jul 03 04:31:47 PM PDT 24 Jul 03 04:31:48 PM PDT 24 40642859 ps
T2790 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2315483560 Jul 03 04:33:06 PM PDT 24 Jul 03 04:33:09 PM PDT 24 233638351 ps
T2791 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.166745924 Jul 03 04:31:59 PM PDT 24 Jul 03 04:32:00 PM PDT 24 42355836 ps
T2792 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1113780437 Jul 03 04:31:43 PM PDT 24 Jul 03 04:31:51 PM PDT 24 184135089 ps
T325 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2111834515 Jul 03 04:31:53 PM PDT 24 Jul 03 04:31:57 PM PDT 24 1012832403 ps
T287 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1224500964 Jul 03 04:32:16 PM PDT 24 Jul 03 04:32:25 PM PDT 24 1162852394 ps
T2793 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3104859932 Jul 03 04:31:52 PM PDT 24 Jul 03 04:31:53 PM PDT 24 50059896 ps
T329 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.4076331034 Jul 03 04:31:56 PM PDT 24 Jul 03 04:32:00 PM PDT 24 497128960 ps
T2794 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1156415507 Jul 03 04:32:21 PM PDT 24 Jul 03 04:32:22 PM PDT 24 55471997 ps
T2795 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.363116522 Jul 03 04:31:40 PM PDT 24 Jul 03 04:31:41 PM PDT 24 76015110 ps
T2796 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.867673789 Jul 03 04:31:36 PM PDT 24 Jul 03 04:31:37 PM PDT 24 133376339 ps
T2797 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.765332412 Jul 03 04:31:44 PM PDT 24 Jul 03 04:31:47 PM PDT 24 114984122 ps
T2798 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1391545115 Jul 03 04:32:14 PM PDT 24 Jul 03 04:32:15 PM PDT 24 34065535 ps
T2799 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.4048398218 Jul 03 04:32:12 PM PDT 24 Jul 03 04:32:15 PM PDT 24 240748259 ps
T330 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2267682304 Jul 03 04:31:38 PM PDT 24 Jul 03 04:31:44 PM PDT 24 890254687 ps
T2800 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2459987692 Jul 03 04:31:45 PM PDT 24 Jul 03 04:31:46 PM PDT 24 48743557 ps
T2801 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3940847614 Jul 03 04:32:01 PM PDT 24 Jul 03 04:32:02 PM PDT 24 133740691 ps
T2802 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.320342798 Jul 03 04:31:48 PM PDT 24 Jul 03 04:31:50 PM PDT 24 39473658 ps
T331 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2840167011 Jul 03 04:31:43 PM PDT 24 Jul 03 04:31:48 PM PDT 24 966503579 ps
T2803 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.480233294 Jul 03 04:31:34 PM PDT 24 Jul 03 04:31:37 PM PDT 24 160742238 ps
T288 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3006934793 Jul 03 04:31:44 PM PDT 24 Jul 03 04:31:53 PM PDT 24 1058207180 ps
T2804 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.600294446 Jul 03 04:31:44 PM PDT 24 Jul 03 04:31:45 PM PDT 24 42369667 ps
T2805 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2978777586 Jul 03 04:32:03 PM PDT 24 Jul 03 04:32:05 PM PDT 24 105956995 ps
T2806 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1458222007 Jul 03 04:31:40 PM PDT 24 Jul 03 04:31:41 PM PDT 24 35407202 ps
T2807 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3284415415 Jul 03 04:32:14 PM PDT 24 Jul 03 04:32:16 PM PDT 24 39080360 ps
T2808 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3438470596 Jul 03 04:31:36 PM PDT 24 Jul 03 04:31:39 PM PDT 24 286302310 ps
T2809 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.954809856 Jul 03 04:31:50 PM PDT 24 Jul 03 04:31:54 PM PDT 24 168441715 ps
T2810 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2246853861 Jul 03 04:31:56 PM PDT 24 Jul 03 04:31:58 PM PDT 24 110318671 ps
T2811 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2926791168 Jul 03 04:32:06 PM PDT 24 Jul 03 04:32:08 PM PDT 24 211737128 ps
T2812 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1818975991 Jul 03 04:31:53 PM PDT 24 Jul 03 04:31:55 PM PDT 24 61712478 ps
T2813 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1758317072 Jul 03 04:32:12 PM PDT 24 Jul 03 04:32:14 PM PDT 24 61297751 ps
T2814 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2357016779 Jul 03 04:31:57 PM PDT 24 Jul 03 04:31:59 PM PDT 24 43723786 ps
T2815 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1894711146 Jul 03 04:32:11 PM PDT 24 Jul 03 04:32:12 PM PDT 24 44391552 ps

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1587281350
Short name T1
Test name
Test status
Simulation time 5140627511 ps
CPU time 46.26 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:52:13 PM PDT 24
Peak memory 206384 kb
Host smart-517912dc-6b42-49ec-b392-2a1f1fe3925c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1587281350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1587281350
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2458510242
Short name T227
Test name
Test status
Simulation time 58133749 ps
CPU time 0.7 seconds
Started Jul 03 04:32:10 PM PDT 24
Finished Jul 03 04:32:11 PM PDT 24
Peak memory 205696 kb
Host smart-77ed9475-ba57-491a-ab7a-cd8323bb3da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2458510242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2458510242
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3845245472
Short name T7
Test name
Test status
Simulation time 13305275188 ps
CPU time 15.27 seconds
Started Jul 03 04:56:29 PM PDT 24
Finished Jul 03 04:56:44 PM PDT 24
Peak memory 206184 kb
Host smart-4ca30736-9d0a-4fb0-909c-b43877d46094
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3845245472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3845245472
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3872643614
Short name T92
Test name
Test status
Simulation time 12621228987 ps
CPU time 28.92 seconds
Started Jul 03 04:53:35 PM PDT 24
Finished Jul 03 04:54:04 PM PDT 24
Peak memory 206220 kb
Host smart-cf2ab8ed-10b9-4126-8647-9dd65c3a01db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38726
43614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3872643614
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1488149752
Short name T217
Test name
Test status
Simulation time 303697866 ps
CPU time 2.94 seconds
Started Jul 03 04:32:07 PM PDT 24
Finished Jul 03 04:32:10 PM PDT 24
Peak memory 222132 kb
Host smart-526a14ea-9274-4151-af13-108a64d3e7bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1488149752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1488149752
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1965969985
Short name T109
Test name
Test status
Simulation time 179741033 ps
CPU time 0.85 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:36 PM PDT 24
Peak memory 206116 kb
Host smart-f255e4a4-d08d-4942-b819-b096a8d071cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19659
69985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1965969985
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.357012128
Short name T662
Test name
Test status
Simulation time 245289665 ps
CPU time 0.91 seconds
Started Jul 03 04:53:28 PM PDT 24
Finished Jul 03 04:53:29 PM PDT 24
Peak memory 206096 kb
Host smart-b1110a37-3eed-4b01-9c55-bf21c1bb340b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35701
2128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.357012128
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.349172919
Short name T368
Test name
Test status
Simulation time 144317196 ps
CPU time 0.78 seconds
Started Jul 03 04:54:40 PM PDT 24
Finished Jul 03 04:54:42 PM PDT 24
Peak memory 206092 kb
Host smart-c5cb2185-d9f5-469e-b487-429fbc587add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34917
2919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.349172919
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1871714323
Short name T250
Test name
Test status
Simulation time 676499395 ps
CPU time 4.54 seconds
Started Jul 03 04:31:33 PM PDT 24
Finished Jul 03 04:31:38 PM PDT 24
Peak memory 205852 kb
Host smart-620ececa-38be-497a-8807-fea86e7ceaac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1871714323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1871714323
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.866124614
Short name T116
Test name
Test status
Simulation time 403348536 ps
CPU time 1.21 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 206076 kb
Host smart-ed7e0739-2038-49b2-a6a2-c0cc81b5e47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86612
4614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.866124614
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1387038097
Short name T8
Test name
Test status
Simulation time 4214501937 ps
CPU time 5.48 seconds
Started Jul 03 04:54:16 PM PDT 24
Finished Jul 03 04:54:22 PM PDT 24
Peak memory 206404 kb
Host smart-236d1e16-8318-4e6e-b343-43368f4d8368
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1387038097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.1387038097
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3603146276
Short name T25
Test name
Test status
Simulation time 186091441 ps
CPU time 0.85 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206112 kb
Host smart-4dfeae46-0971-42a2-9cd2-d2478c8605d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36031
46276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3603146276
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2439072446
Short name T316
Test name
Test status
Simulation time 43888051 ps
CPU time 0.77 seconds
Started Jul 03 04:32:06 PM PDT 24
Finished Jul 03 04:32:07 PM PDT 24
Peak memory 205732 kb
Host smart-64bce78b-34ff-4379-b63b-0586accd8fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2439072446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2439072446
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3643293436
Short name T214
Test name
Test status
Simulation time 519242784 ps
CPU time 1.57 seconds
Started Jul 03 04:51:32 PM PDT 24
Finished Jul 03 04:51:36 PM PDT 24
Peak memory 225024 kb
Host smart-1e708c34-a0ba-446c-bba5-b28e61f87f5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3643293436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3643293436
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1902409065
Short name T22
Test name
Test status
Simulation time 39413039 ps
CPU time 0.67 seconds
Started Jul 03 04:51:33 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206120 kb
Host smart-a0f5b774-83f1-4156-aa7a-af43ca96ae3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19024
09065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1902409065
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3464935926
Short name T277
Test name
Test status
Simulation time 104421004 ps
CPU time 0.86 seconds
Started Jul 03 04:31:44 PM PDT 24
Finished Jul 03 04:31:45 PM PDT 24
Peak memory 205708 kb
Host smart-5ac03d81-81d1-46ba-9bc4-fea87533ff51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3464935926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3464935926
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.4180410715
Short name T89
Test name
Test status
Simulation time 309893764 ps
CPU time 0.97 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 206088 kb
Host smart-1b12c79c-cf32-49db-a5fd-629b29788814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41804
10715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.4180410715
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2339950887
Short name T51
Test name
Test status
Simulation time 14937004345 ps
CPU time 311.05 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:57:14 PM PDT 24
Peak memory 206384 kb
Host smart-3e57e759-9cae-4d38-93b1-053f3f503490
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2339950887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2339950887
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2286799797
Short name T308
Test name
Test status
Simulation time 68650728 ps
CPU time 0.7 seconds
Started Jul 03 04:32:13 PM PDT 24
Finished Jul 03 04:32:15 PM PDT 24
Peak memory 205672 kb
Host smart-18de7d41-efb4-4a54-9f82-2637f5602446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2286799797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2286799797
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.168327185
Short name T55
Test name
Test status
Simulation time 20159289381 ps
CPU time 21.4 seconds
Started Jul 03 04:51:38 PM PDT 24
Finished Jul 03 04:52:00 PM PDT 24
Peak memory 206188 kb
Host smart-1d66383b-68e0-4ed5-a2c4-aa30fdd3827f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16832
7185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.168327185
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2274199108
Short name T2774
Test name
Test status
Simulation time 42012166 ps
CPU time 0.66 seconds
Started Jul 03 04:31:47 PM PDT 24
Finished Jul 03 04:31:48 PM PDT 24
Peak memory 205732 kb
Host smart-35b2692c-3411-4c7e-89ee-7e1af9e60f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2274199108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2274199108
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1343035060
Short name T314
Test name
Test status
Simulation time 181256977 ps
CPU time 0.85 seconds
Started Jul 03 04:52:20 PM PDT 24
Finished Jul 03 04:52:21 PM PDT 24
Peak memory 206132 kb
Host smart-3aed1e53-48b0-4359-9d5e-7675d4397e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13430
35060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1343035060
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.3134191461
Short name T420
Test name
Test status
Simulation time 150812856 ps
CPU time 0.78 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 206132 kb
Host smart-ba498bc0-6212-41da-be0e-5b81c454d1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31341
91461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.3134191461
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1951740314
Short name T267
Test name
Test status
Simulation time 1755331251 ps
CPU time 5.83 seconds
Started Jul 03 04:31:54 PM PDT 24
Finished Jul 03 04:32:00 PM PDT 24
Peak memory 205936 kb
Host smart-c45b5e11-edd8-4b74-96f3-5e06303b9c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1951740314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1951740314
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.411340501
Short name T254
Test name
Test status
Simulation time 18685237304 ps
CPU time 42.24 seconds
Started Jul 03 04:55:04 PM PDT 24
Finished Jul 03 04:55:46 PM PDT 24
Peak memory 214648 kb
Host smart-f2780fac-c1e0-4f96-b027-581adaf39920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
0501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.411340501
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1939853334
Short name T85
Test name
Test status
Simulation time 25788692553 ps
CPU time 611.98 seconds
Started Jul 03 04:51:58 PM PDT 24
Finished Jul 03 05:02:10 PM PDT 24
Peak memory 206344 kb
Host smart-8fda12b1-dcdf-4a69-8583-0586794aa089
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1939853334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1939853334
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.624525260
Short name T400
Test name
Test status
Simulation time 63480854 ps
CPU time 0.75 seconds
Started Jul 03 04:53:12 PM PDT 24
Finished Jul 03 04:53:13 PM PDT 24
Peak memory 206104 kb
Host smart-20044e74-cdfc-41b6-956d-92caa05f7f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=624525260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.624525260
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2479206190
Short name T259
Test name
Test status
Simulation time 220263622 ps
CPU time 1.72 seconds
Started Jul 03 04:31:52 PM PDT 24
Finished Jul 03 04:31:54 PM PDT 24
Peak memory 214156 kb
Host smart-2a2e757e-aba0-4322-b78a-f939ac8cfb1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479206190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2479206190
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.814035718
Short name T68
Test name
Test status
Simulation time 257168710 ps
CPU time 1.04 seconds
Started Jul 03 04:51:24 PM PDT 24
Finished Jul 03 04:51:26 PM PDT 24
Peak memory 206112 kb
Host smart-eca8dbfb-4fd6-4be4-ab03-c9b1a671074c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81403
5718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.814035718
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2278535796
Short name T80
Test name
Test status
Simulation time 470489059 ps
CPU time 1.34 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:32 PM PDT 24
Peak memory 206028 kb
Host smart-5aef54ca-fc87-46eb-94e8-117be304d26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22785
35796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2278535796
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2187552103
Short name T2756
Test name
Test status
Simulation time 36957443 ps
CPU time 0.69 seconds
Started Jul 03 04:33:06 PM PDT 24
Finished Jul 03 04:33:08 PM PDT 24
Peak memory 205560 kb
Host smart-738c08a4-5a45-4130-87dd-7e46c21cbfee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2187552103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2187552103
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1614299675
Short name T220
Test name
Test status
Simulation time 64478084 ps
CPU time 0.95 seconds
Started Jul 03 04:31:58 PM PDT 24
Finished Jul 03 04:31:59 PM PDT 24
Peak memory 205912 kb
Host smart-5d84611d-31cb-48dc-a1ed-d5b7008777cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1614299675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1614299675
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.656211521
Short name T114
Test name
Test status
Simulation time 1227390966 ps
CPU time 2.81 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:54:47 PM PDT 24
Peak memory 206348 kb
Host smart-8108b6f7-1564-416a-bbfa-f3a4579f4b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65621
1521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.656211521
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3862812451
Short name T58
Test name
Test status
Simulation time 138758917 ps
CPU time 0.79 seconds
Started Jul 03 04:51:27 PM PDT 24
Finished Jul 03 04:51:29 PM PDT 24
Peak memory 206088 kb
Host smart-7b2282f8-ede8-4905-9dfa-80fb4bdeeed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38628
12451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3862812451
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.3794536943
Short name T170
Test name
Test status
Simulation time 8165026552 ps
CPU time 212 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:55:40 PM PDT 24
Peak memory 206456 kb
Host smart-c84e6e69-7723-4e42-864b-2148f49cde13
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3794536943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.3794536943
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2111834515
Short name T325
Test name
Test status
Simulation time 1012832403 ps
CPU time 3 seconds
Started Jul 03 04:31:53 PM PDT 24
Finished Jul 03 04:31:57 PM PDT 24
Peak memory 205908 kb
Host smart-9215ea91-9b40-4860-8ec8-1652a96813c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2111834515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2111834515
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2267682304
Short name T330
Test name
Test status
Simulation time 890254687 ps
CPU time 5.19 seconds
Started Jul 03 04:31:38 PM PDT 24
Finished Jul 03 04:31:44 PM PDT 24
Peak memory 205852 kb
Host smart-73eddb12-83a4-4e50-b486-4426214062d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2267682304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2267682304
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1213981104
Short name T261
Test name
Test status
Simulation time 209528722 ps
CPU time 2.74 seconds
Started Jul 03 04:32:12 PM PDT 24
Finished Jul 03 04:32:16 PM PDT 24
Peak memory 205996 kb
Host smart-9cd4247a-bd16-4f63-b095-6829e6c2eec3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1213981104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1213981104
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.4285946588
Short name T339
Test name
Test status
Simulation time 879769850 ps
CPU time 2.01 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206364 kb
Host smart-96d72d2b-8a8d-437a-b319-3999d158b275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42859
46588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.4285946588
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2850756219
Short name T2389
Test name
Test status
Simulation time 1436313748 ps
CPU time 3.04 seconds
Started Jul 03 04:56:59 PM PDT 24
Finished Jul 03 04:57:02 PM PDT 24
Peak memory 206264 kb
Host smart-d1dc4841-bd53-4042-beb3-e919602a7fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28507
56219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2850756219
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1840498570
Short name T45
Test name
Test status
Simulation time 152613221 ps
CPU time 0.76 seconds
Started Jul 03 04:53:15 PM PDT 24
Finished Jul 03 04:53:16 PM PDT 24
Peak memory 206112 kb
Host smart-d5370aae-3622-4fda-94e6-8ef7cbe51d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18404
98570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1840498570
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.3698565157
Short name T76
Test name
Test status
Simulation time 148747365 ps
CPU time 0.81 seconds
Started Jul 03 04:51:38 PM PDT 24
Finished Jul 03 04:51:40 PM PDT 24
Peak memory 206124 kb
Host smart-05ac44b4-021c-4eec-a502-fa3a3273e5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36985
65157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.3698565157
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1824820117
Short name T208
Test name
Test status
Simulation time 298698395 ps
CPU time 2.05 seconds
Started Jul 03 04:52:49 PM PDT 24
Finished Jul 03 04:52:52 PM PDT 24
Peak memory 206276 kb
Host smart-b766d0d2-dbb1-4fa7-85c8-75aa02d4d0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18248
20117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1824820117
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_device_address.913073063
Short name T108
Test name
Test status
Simulation time 10611924705 ps
CPU time 22.92 seconds
Started Jul 03 04:56:07 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206376 kb
Host smart-c43df634-2cbe-4d3b-8c2e-c416eed31c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91307
3063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.913073063
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3166254157
Short name T50
Test name
Test status
Simulation time 17291575766 ps
CPU time 118.58 seconds
Started Jul 03 04:52:14 PM PDT 24
Finished Jul 03 04:54:12 PM PDT 24
Peak memory 206424 kb
Host smart-fe25397a-b4ac-4506-8b99-37a00c4298b3
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3166254157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3166254157
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3544782078
Short name T70
Test name
Test status
Simulation time 157599030 ps
CPU time 0.79 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 206124 kb
Host smart-51a9a1a5-c3d2-4fd3-9726-825ec9b28a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35447
82078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3544782078
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.933311329
Short name T1868
Test name
Test status
Simulation time 1128284545 ps
CPU time 2.76 seconds
Started Jul 03 04:51:23 PM PDT 24
Finished Jul 03 04:51:26 PM PDT 24
Peak memory 206252 kb
Host smart-c77f2212-3fb7-4914-9173-6b56644cb02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93331
1329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.933311329
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1586540812
Short name T78
Test name
Test status
Simulation time 4170962766 ps
CPU time 9.6 seconds
Started Jul 03 04:51:19 PM PDT 24
Finished Jul 03 04:51:29 PM PDT 24
Peak memory 206460 kb
Host smart-bdda23b4-ce27-41c5-8699-a31f880f6bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15865
40812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1586540812
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1820520189
Short name T79
Test name
Test status
Simulation time 171070472 ps
CPU time 0.8 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:32 PM PDT 24
Peak memory 206096 kb
Host smart-dcd25fd0-fc3b-48f5-890a-24ec4b12ccf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18205
20189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1820520189
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.180871057
Short name T1692
Test name
Test status
Simulation time 150422912 ps
CPU time 0.8 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 206104 kb
Host smart-e5e8950b-6597-45d2-8310-9cac68ce9cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18087
1057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.180871057
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.3969003214
Short name T64
Test name
Test status
Simulation time 173263053 ps
CPU time 0.78 seconds
Started Jul 03 04:51:36 PM PDT 24
Finished Jul 03 04:51:38 PM PDT 24
Peak memory 206104 kb
Host smart-f8fbb6de-5ed1-4db7-984e-4c290c05d4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39690
03214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.3969003214
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1153617586
Short name T192
Test name
Test status
Simulation time 18739698890 ps
CPU time 117.7 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:53:30 PM PDT 24
Peak memory 206376 kb
Host smart-5b6f1d65-3a2a-4d25-ad27-691fc6d95a67
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1153617586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1153617586
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.470284955
Short name T718
Test name
Test status
Simulation time 62652456 ps
CPU time 0.68 seconds
Started Jul 03 04:53:09 PM PDT 24
Finished Jul 03 04:53:10 PM PDT 24
Peak memory 206096 kb
Host smart-9e838883-1b05-4f37-90c3-55a240b68c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47028
4955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.470284955
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1224500964
Short name T287
Test name
Test status
Simulation time 1162852394 ps
CPU time 7.74 seconds
Started Jul 03 04:32:16 PM PDT 24
Finished Jul 03 04:32:25 PM PDT 24
Peak memory 205920 kb
Host smart-fa0e4eac-d7d6-488d-989b-1acf1c8b2be9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1224500964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1224500964
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.240081655
Short name T262
Test name
Test status
Simulation time 338176247 ps
CPU time 2.4 seconds
Started Jul 03 04:32:45 PM PDT 24
Finished Jul 03 04:32:49 PM PDT 24
Peak memory 204092 kb
Host smart-f01e098a-fd2d-4be1-843c-8d6ff08e7601
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=240081655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.240081655
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3914824837
Short name T145
Test name
Test status
Simulation time 183523339 ps
CPU time 0.9 seconds
Started Jul 03 04:51:25 PM PDT 24
Finished Jul 03 04:51:27 PM PDT 24
Peak memory 206144 kb
Host smart-d1426186-6345-44b0-baa8-68fdcd9d545d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148
24837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3914824837
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.130705092
Short name T69
Test name
Test status
Simulation time 316832146 ps
CPU time 1.06 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 205972 kb
Host smart-176208fa-8284-4c4a-97f4-385c75edb7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13070
5092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.130705092
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1143011286
Short name T130
Test name
Test status
Simulation time 209216315 ps
CPU time 0.88 seconds
Started Jul 03 04:51:39 PM PDT 24
Finished Jul 03 04:51:40 PM PDT 24
Peak memory 206132 kb
Host smart-10447020-3634-4f35-9ca9-9bc2e35e995c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11430
11286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1143011286
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.475020535
Short name T273
Test name
Test status
Simulation time 9985906762 ps
CPU time 23.2 seconds
Started Jul 03 04:51:37 PM PDT 24
Finished Jul 03 04:52:01 PM PDT 24
Peak memory 206428 kb
Host smart-d69b2584-62ee-49aa-84ff-e79fdee4267a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47502
0535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.475020535
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2208601149
Short name T128
Test name
Test status
Simulation time 201878115 ps
CPU time 1.01 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 206072 kb
Host smart-51534843-31df-4c7c-b639-082968fa385c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22086
01149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2208601149
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3614028944
Short name T13
Test name
Test status
Simulation time 3896526959 ps
CPU time 4.4 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206164 kb
Host smart-41c243ee-d7cb-4e44-8c49-d782a957ea9f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3614028944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.3614028944
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.4253434537
Short name T805
Test name
Test status
Simulation time 167759876 ps
CPU time 0.79 seconds
Started Jul 03 04:53:06 PM PDT 24
Finished Jul 03 04:53:07 PM PDT 24
Peak memory 206104 kb
Host smart-f908df5e-9f6b-4091-990d-92ebee703360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42534
34537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.4253434537
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3301799607
Short name T136
Test name
Test status
Simulation time 193049766 ps
CPU time 0.79 seconds
Started Jul 03 04:53:12 PM PDT 24
Finished Jul 03 04:53:13 PM PDT 24
Peak memory 206112 kb
Host smart-399f8e62-fcf5-48d2-b195-a1e1edadaff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33017
99607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3301799607
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3899669926
Short name T167
Test name
Test status
Simulation time 1061870057 ps
CPU time 2.4 seconds
Started Jul 03 04:53:13 PM PDT 24
Finished Jul 03 04:53:16 PM PDT 24
Peak memory 206380 kb
Host smart-7596a162-924f-4d1e-bc23-f4b9d24733bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38996
69926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3899669926
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1314011294
Short name T144
Test name
Test status
Simulation time 184600036 ps
CPU time 0.82 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 206388 kb
Host smart-71ad5081-2d59-4c3e-885e-6d0c2d2ba445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13140
11294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1314011294
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3542879440
Short name T569
Test name
Test status
Simulation time 229131156 ps
CPU time 0.93 seconds
Started Jul 03 04:53:59 PM PDT 24
Finished Jul 03 04:54:01 PM PDT 24
Peak memory 206104 kb
Host smart-1cb71206-56a0-4a3b-8c91-c66af9276adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35428
79440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3542879440
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4043579344
Short name T152
Test name
Test status
Simulation time 193812395 ps
CPU time 0.81 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:52:01 PM PDT 24
Peak memory 206128 kb
Host smart-f1486f18-550b-4d4d-b5ce-c0f9acb5dad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40435
79344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4043579344
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3421885645
Short name T140
Test name
Test status
Simulation time 233137966 ps
CPU time 0.89 seconds
Started Jul 03 04:54:16 PM PDT 24
Finished Jul 03 04:54:18 PM PDT 24
Peak memory 206104 kb
Host smart-fe424082-a832-44f0-9190-71a4204dd0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34218
85645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3421885645
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.384586140
Short name T150
Test name
Test status
Simulation time 225892758 ps
CPU time 0.88 seconds
Started Jul 03 04:55:21 PM PDT 24
Finished Jul 03 04:55:22 PM PDT 24
Peak memory 206112 kb
Host smart-89b4990f-292d-437d-ab86-59a700f59962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38458
6140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.384586140
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2991262571
Short name T191
Test name
Test status
Simulation time 8307368732 ps
CPU time 48.43 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206448 kb
Host smart-5acfe0a2-1544-4f1c-95e5-62b4035da501
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2991262571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2991262571
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.4145770998
Short name T137
Test name
Test status
Simulation time 190570738 ps
CPU time 0.82 seconds
Started Jul 03 04:56:30 PM PDT 24
Finished Jul 03 04:56:31 PM PDT 24
Peak memory 206132 kb
Host smart-dc9093d1-e177-4e85-b840-02251949125e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41457
70998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.4145770998
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.480233294
Short name T2803
Test name
Test status
Simulation time 160742238 ps
CPU time 2.13 seconds
Started Jul 03 04:31:34 PM PDT 24
Finished Jul 03 04:31:37 PM PDT 24
Peak memory 205820 kb
Host smart-e5657bd8-54d3-445a-a96e-22d16f909c31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=480233294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.480233294
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2281402247
Short name T222
Test name
Test status
Simulation time 96934476 ps
CPU time 0.83 seconds
Started Jul 03 04:32:13 PM PDT 24
Finished Jul 03 04:32:15 PM PDT 24
Peak memory 205736 kb
Host smart-9407a3c0-2c7d-4245-b3ef-de58f86a34a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2281402247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2281402247
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2238612860
Short name T2769
Test name
Test status
Simulation time 130672309 ps
CPU time 1.3 seconds
Started Jul 03 04:31:42 PM PDT 24
Finished Jul 03 04:31:44 PM PDT 24
Peak memory 214120 kb
Host smart-ca6aae18-12dc-4cf5-b063-7228286dd182
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238612860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2238612860
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1458222007
Short name T2806
Test name
Test status
Simulation time 35407202 ps
CPU time 0.66 seconds
Started Jul 03 04:31:40 PM PDT 24
Finished Jul 03 04:31:41 PM PDT 24
Peak memory 205696 kb
Host smart-d3596f16-66ef-40d3-b54e-7c8ac40d0734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1458222007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1458222007
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1554799145
Short name T2724
Test name
Test status
Simulation time 100989962 ps
CPU time 1.49 seconds
Started Jul 03 04:31:43 PM PDT 24
Finished Jul 03 04:31:45 PM PDT 24
Peak memory 214116 kb
Host smart-5a24af1d-17e6-4f9d-bb99-663153304bab
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1554799145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1554799145
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.265804648
Short name T2721
Test name
Test status
Simulation time 794562962 ps
CPU time 4.9 seconds
Started Jul 03 04:32:02 PM PDT 24
Finished Jul 03 04:32:07 PM PDT 24
Peak memory 205880 kb
Host smart-3d983a7a-a9bf-4b34-a772-96c391591eee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=265804648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.265804648
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2839283608
Short name T2737
Test name
Test status
Simulation time 125350529 ps
CPU time 1.14 seconds
Started Jul 03 04:31:45 PM PDT 24
Finished Jul 03 04:31:46 PM PDT 24
Peak memory 205860 kb
Host smart-cb91b734-4698-47c4-a0dc-aa2d17d98952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2839283608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2839283608
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3796516386
Short name T2749
Test name
Test status
Simulation time 97261824 ps
CPU time 1.33 seconds
Started Jul 03 04:31:43 PM PDT 24
Finished Jul 03 04:31:45 PM PDT 24
Peak memory 205972 kb
Host smart-c9899bdb-08cd-440b-bd35-94b3ee3551c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3796516386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3796516386
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.11387458
Short name T306
Test name
Test status
Simulation time 1337344138 ps
CPU time 5.31 seconds
Started Jul 03 04:32:13 PM PDT 24
Finished Jul 03 04:32:20 PM PDT 24
Peak memory 205940 kb
Host smart-03d5678d-1aa0-4376-a9e0-025a7613396e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=11387458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.11387458
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3886190871
Short name T305
Test name
Test status
Simulation time 372964555 ps
CPU time 3.47 seconds
Started Jul 03 04:32:03 PM PDT 24
Finished Jul 03 04:32:12 PM PDT 24
Peak memory 205916 kb
Host smart-9aae34cb-b4eb-4d62-bfba-d421e47b1aac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3886190871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3886190871
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3006934793
Short name T288
Test name
Test status
Simulation time 1058207180 ps
CPU time 7.98 seconds
Started Jul 03 04:31:44 PM PDT 24
Finished Jul 03 04:31:53 PM PDT 24
Peak memory 205888 kb
Host smart-69656a31-6853-4462-845a-b6480b360aec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3006934793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3006934793
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.870163315
Short name T2783
Test name
Test status
Simulation time 116536194 ps
CPU time 0.85 seconds
Started Jul 03 04:31:39 PM PDT 24
Finished Jul 03 04:31:40 PM PDT 24
Peak memory 205652 kb
Host smart-ea4ce0fa-dbb1-4547-9f2e-486841df3cd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=870163315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.870163315
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2112689862
Short name T2742
Test name
Test status
Simulation time 51994317 ps
CPU time 0.8 seconds
Started Jul 03 04:31:48 PM PDT 24
Finished Jul 03 04:31:49 PM PDT 24
Peak memory 205688 kb
Host smart-b2878a8b-c64a-438d-b069-bc26b2c1696a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2112689862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2112689862
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.600294446
Short name T2804
Test name
Test status
Simulation time 42369667 ps
CPU time 0.65 seconds
Started Jul 03 04:31:44 PM PDT 24
Finished Jul 03 04:31:45 PM PDT 24
Peak memory 205676 kb
Host smart-833e40c0-19c6-46b6-b424-5312284440c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=600294446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.600294446
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1818975991
Short name T2812
Test name
Test status
Simulation time 61712478 ps
CPU time 1.26 seconds
Started Jul 03 04:31:53 PM PDT 24
Finished Jul 03 04:31:55 PM PDT 24
Peak memory 214108 kb
Host smart-3e292955-6e79-4941-89b4-531d5341dc42
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1818975991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1818975991
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.421828856
Short name T2720
Test name
Test status
Simulation time 757464125 ps
CPU time 4.68 seconds
Started Jul 03 04:32:07 PM PDT 24
Finished Jul 03 04:32:12 PM PDT 24
Peak memory 205888 kb
Host smart-357121b2-9775-4177-b477-edd07e28591e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=421828856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.421828856
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4158499384
Short name T303
Test name
Test status
Simulation time 121284813 ps
CPU time 1.25 seconds
Started Jul 03 04:32:23 PM PDT 24
Finished Jul 03 04:32:25 PM PDT 24
Peak memory 205904 kb
Host smart-7fcff8bd-85af-423c-8c25-2344beb22ac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4158499384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.4158499384
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3647840225
Short name T2731
Test name
Test status
Simulation time 50637511 ps
CPU time 1.17 seconds
Started Jul 03 04:32:08 PM PDT 24
Finished Jul 03 04:32:10 PM PDT 24
Peak memory 214152 kb
Host smart-1f47c884-07ab-41ae-814e-414cb8d9bd63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647840225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3647840225
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3018149673
Short name T2751
Test name
Test status
Simulation time 69226409 ps
CPU time 0.95 seconds
Started Jul 03 04:31:34 PM PDT 24
Finished Jul 03 04:31:35 PM PDT 24
Peak memory 205852 kb
Host smart-7d603ccd-80a1-4104-91c1-568c24d64b98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3018149673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3018149673
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3104859932
Short name T2793
Test name
Test status
Simulation time 50059896 ps
CPU time 0.68 seconds
Started Jul 03 04:31:52 PM PDT 24
Finished Jul 03 04:31:53 PM PDT 24
Peak memory 205716 kb
Host smart-9197d776-c462-426b-9eed-6bac0b909395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3104859932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3104859932
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2301574434
Short name T2777
Test name
Test status
Simulation time 123972893 ps
CPU time 1.27 seconds
Started Jul 03 04:31:48 PM PDT 24
Finished Jul 03 04:31:50 PM PDT 24
Peak memory 205936 kb
Host smart-e56b3037-0e0f-4401-b279-c4037999a49e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2301574434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2301574434
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1402844593
Short name T256
Test name
Test status
Simulation time 69718652 ps
CPU time 1.45 seconds
Started Jul 03 04:33:12 PM PDT 24
Finished Jul 03 04:33:15 PM PDT 24
Peak memory 205832 kb
Host smart-df44dc8a-3406-4ac4-a1fb-470d95287f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1402844593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1402844593
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1777149732
Short name T2782
Test name
Test status
Simulation time 531925102 ps
CPU time 4.27 seconds
Started Jul 03 04:31:39 PM PDT 24
Finished Jul 03 04:31:43 PM PDT 24
Peak memory 205880 kb
Host smart-bbb85d09-3205-4dd7-8c75-5baf1eba4a03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1777149732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1777149732
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2246853861
Short name T2810
Test name
Test status
Simulation time 110318671 ps
CPU time 1.24 seconds
Started Jul 03 04:31:56 PM PDT 24
Finished Jul 03 04:31:58 PM PDT 24
Peak memory 214220 kb
Host smart-e86b1ade-9d78-4af7-b6de-f76bfe07b206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246853861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2246853861
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.488089639
Short name T278
Test name
Test status
Simulation time 133918278 ps
CPU time 0.9 seconds
Started Jul 03 04:31:53 PM PDT 24
Finished Jul 03 04:32:00 PM PDT 24
Peak memory 205716 kb
Host smart-757ffe1c-cb15-4796-ac88-fd1b0c4976d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=488089639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.488089639
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3030748278
Short name T289
Test name
Test status
Simulation time 79117036 ps
CPU time 1.07 seconds
Started Jul 03 04:31:58 PM PDT 24
Finished Jul 03 04:31:59 PM PDT 24
Peak memory 205840 kb
Host smart-1db880c8-b95b-4b59-b03c-06f9d94d4543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3030748278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3030748278
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.401539566
Short name T263
Test name
Test status
Simulation time 273257870 ps
CPU time 3.27 seconds
Started Jul 03 04:33:19 PM PDT 24
Finished Jul 03 04:33:22 PM PDT 24
Peak memory 214044 kb
Host smart-1ae12e8b-b83b-4f0e-9b07-0c202ab959a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=401539566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.401539566
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3600409374
Short name T310
Test name
Test status
Simulation time 465379774 ps
CPU time 2.86 seconds
Started Jul 03 04:31:52 PM PDT 24
Finished Jul 03 04:31:55 PM PDT 24
Peak memory 205936 kb
Host smart-985eb45e-9d74-4986-b649-716507365303
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3600409374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3600409374
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.323561724
Short name T266
Test name
Test status
Simulation time 72465018 ps
CPU time 1.65 seconds
Started Jul 03 04:32:02 PM PDT 24
Finished Jul 03 04:32:04 PM PDT 24
Peak memory 214160 kb
Host smart-b488129f-5dc4-4600-9e27-2ade89e9fd9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323561724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.323561724
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4292432609
Short name T2779
Test name
Test status
Simulation time 50125578 ps
CPU time 0.93 seconds
Started Jul 03 04:31:47 PM PDT 24
Finished Jul 03 04:31:49 PM PDT 24
Peak memory 205920 kb
Host smart-de75eca6-ec15-4c25-ac56-b6d6eeca273c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4292432609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.4292432609
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1468347596
Short name T317
Test name
Test status
Simulation time 61130514 ps
CPU time 0.68 seconds
Started Jul 03 04:32:03 PM PDT 24
Finished Jul 03 04:32:04 PM PDT 24
Peak memory 205668 kb
Host smart-b368443b-b89e-4a67-83fe-c6ff30462782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1468347596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1468347596
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2459987692
Short name T2800
Test name
Test status
Simulation time 48743557 ps
CPU time 0.98 seconds
Started Jul 03 04:31:45 PM PDT 24
Finished Jul 03 04:31:46 PM PDT 24
Peak memory 206156 kb
Host smart-fd11641d-0e9d-4d5f-8f65-77eebb9bd12e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2459987692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2459987692
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3194148959
Short name T2785
Test name
Test status
Simulation time 117640354 ps
CPU time 2.62 seconds
Started Jul 03 04:31:48 PM PDT 24
Finished Jul 03 04:31:51 PM PDT 24
Peak memory 221968 kb
Host smart-2599e462-ea99-4284-88e5-69e7ed185874
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3194148959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3194148959
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3133899891
Short name T2784
Test name
Test status
Simulation time 101255425 ps
CPU time 1.27 seconds
Started Jul 03 04:31:58 PM PDT 24
Finished Jul 03 04:32:00 PM PDT 24
Peak memory 214180 kb
Host smart-79542e2f-b816-4e1b-8a3f-5955bbae2695
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133899891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3133899891
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3209782778
Short name T279
Test name
Test status
Simulation time 125915770 ps
CPU time 1.02 seconds
Started Jul 03 04:33:12 PM PDT 24
Finished Jul 03 04:33:15 PM PDT 24
Peak memory 205784 kb
Host smart-d40a3d1d-cf00-4f2d-aa1e-2247a82f5f5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3209782778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3209782778
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3053977200
Short name T318
Test name
Test status
Simulation time 41168866 ps
CPU time 0.66 seconds
Started Jul 03 04:33:03 PM PDT 24
Finished Jul 03 04:33:04 PM PDT 24
Peak memory 205556 kb
Host smart-c219773d-77cf-469c-834b-e4ea0ca8bbdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3053977200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3053977200
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2315483560
Short name T2790
Test name
Test status
Simulation time 233638351 ps
CPU time 1.42 seconds
Started Jul 03 04:33:06 PM PDT 24
Finished Jul 03 04:33:09 PM PDT 24
Peak memory 205744 kb
Host smart-7390b74f-ecf2-4c79-b202-3c734deca833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2315483560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2315483560
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.119715789
Short name T2772
Test name
Test status
Simulation time 147545224 ps
CPU time 2.82 seconds
Started Jul 03 04:31:58 PM PDT 24
Finished Jul 03 04:32:01 PM PDT 24
Peak memory 221812 kb
Host smart-b935646b-8410-4176-b855-dfb2fbf2f2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=119715789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.119715789
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2631398234
Short name T326
Test name
Test status
Simulation time 457884526 ps
CPU time 2.7 seconds
Started Jul 03 04:31:48 PM PDT 24
Finished Jul 03 04:31:51 PM PDT 24
Peak memory 206176 kb
Host smart-bc78df16-3705-4d3e-862d-f0059b97018c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2631398234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2631398234
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2552859751
Short name T2780
Test name
Test status
Simulation time 101577747 ps
CPU time 2.7 seconds
Started Jul 03 04:31:57 PM PDT 24
Finished Jul 03 04:32:01 PM PDT 24
Peak memory 214152 kb
Host smart-feb30000-990d-483b-80f8-189190037e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552859751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2552859751
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3652190029
Short name T292
Test name
Test status
Simulation time 66331189 ps
CPU time 0.82 seconds
Started Jul 03 04:31:54 PM PDT 24
Finished Jul 03 04:31:55 PM PDT 24
Peak memory 205760 kb
Host smart-0748e389-5c38-4541-9d77-b690ca76b0dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3652190029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3652190029
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3443608934
Short name T2763
Test name
Test status
Simulation time 42294728 ps
CPU time 0.67 seconds
Started Jul 03 04:32:10 PM PDT 24
Finished Jul 03 04:32:11 PM PDT 24
Peak memory 205692 kb
Host smart-5272958d-8b12-4e1b-a5cc-027619408807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3443608934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3443608934
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3706368238
Short name T2775
Test name
Test status
Simulation time 137419326 ps
CPU time 1.09 seconds
Started Jul 03 04:32:17 PM PDT 24
Finished Jul 03 04:32:24 PM PDT 24
Peak memory 205924 kb
Host smart-d73d030b-7e9c-4034-b527-186e8aa04f7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3706368238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3706368238
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.765332412
Short name T2797
Test name
Test status
Simulation time 114984122 ps
CPU time 3.14 seconds
Started Jul 03 04:31:44 PM PDT 24
Finished Jul 03 04:31:47 PM PDT 24
Peak memory 221724 kb
Host smart-f040ec4b-4918-4046-a139-2b311209bdd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=765332412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.765332412
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1569538462
Short name T2767
Test name
Test status
Simulation time 847334463 ps
CPU time 2.93 seconds
Started Jul 03 04:31:56 PM PDT 24
Finished Jul 03 04:31:59 PM PDT 24
Peak memory 205932 kb
Host smart-708af7f6-0e38-43d8-98b1-7502a498698a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1569538462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1569538462
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1057006096
Short name T2757
Test name
Test status
Simulation time 103955185 ps
CPU time 1.26 seconds
Started Jul 03 04:32:00 PM PDT 24
Finished Jul 03 04:32:02 PM PDT 24
Peak memory 214520 kb
Host smart-a56f4f05-fd18-4300-914d-06a4acffa469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057006096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1057006096
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1894711146
Short name T2815
Test name
Test status
Simulation time 44391552 ps
CPU time 0.67 seconds
Started Jul 03 04:32:11 PM PDT 24
Finished Jul 03 04:32:12 PM PDT 24
Peak memory 205668 kb
Host smart-80ef428f-08bb-4781-a0f3-ac1fda0d38a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1894711146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1894711146
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.731267407
Short name T301
Test name
Test status
Simulation time 173743504 ps
CPU time 1.48 seconds
Started Jul 03 04:31:48 PM PDT 24
Finished Jul 03 04:31:50 PM PDT 24
Peak memory 205924 kb
Host smart-1557132f-4279-4546-bb06-931a8a96a061
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=731267407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.731267407
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2229633976
Short name T2740
Test name
Test status
Simulation time 245645118 ps
CPU time 3.05 seconds
Started Jul 03 04:32:04 PM PDT 24
Finished Jul 03 04:32:08 PM PDT 24
Peak memory 222084 kb
Host smart-14ce2e66-2501-4d29-a1a6-60c90732f875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2229633976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2229633976
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.457210587
Short name T218
Test name
Test status
Simulation time 436798344 ps
CPU time 2.93 seconds
Started Jul 03 04:31:51 PM PDT 24
Finished Jul 03 04:31:55 PM PDT 24
Peak memory 205908 kb
Host smart-e6e2497b-3a89-494d-a79b-a7304fe10a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=457210587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.457210587
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2926791168
Short name T2811
Test name
Test status
Simulation time 211737128 ps
CPU time 1.84 seconds
Started Jul 03 04:32:06 PM PDT 24
Finished Jul 03 04:32:08 PM PDT 24
Peak memory 214188 kb
Host smart-3a82f809-f135-4611-a04f-b2c9e8b6e1f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926791168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2926791168
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1818220045
Short name T285
Test name
Test status
Simulation time 40125599 ps
CPU time 0.99 seconds
Started Jul 03 04:32:09 PM PDT 24
Finished Jul 03 04:32:10 PM PDT 24
Peak memory 205956 kb
Host smart-d912ce54-fdb5-4bb7-b08b-38ad224ff458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1818220045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1818220045
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3053091000
Short name T2728
Test name
Test status
Simulation time 456426074 ps
CPU time 1.67 seconds
Started Jul 03 04:32:05 PM PDT 24
Finished Jul 03 04:32:07 PM PDT 24
Peak memory 205884 kb
Host smart-5b365a6b-be62-4e4d-bda5-f0178dafa563
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3053091000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3053091000
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3295955250
Short name T246
Test name
Test status
Simulation time 105765503 ps
CPU time 2.75 seconds
Started Jul 03 04:32:12 PM PDT 24
Finished Jul 03 04:32:15 PM PDT 24
Peak memory 205916 kb
Host smart-5d895e9e-d86d-4f26-aecd-d9526673323a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3295955250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3295955250
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.4076331034
Short name T329
Test name
Test status
Simulation time 497128960 ps
CPU time 2.73 seconds
Started Jul 03 04:31:56 PM PDT 24
Finished Jul 03 04:32:00 PM PDT 24
Peak memory 205804 kb
Host smart-1b21709f-0f86-460a-a098-741ab311ca5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4076331034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.4076331034
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2252813239
Short name T265
Test name
Test status
Simulation time 102172045 ps
CPU time 1.29 seconds
Started Jul 03 04:31:57 PM PDT 24
Finished Jul 03 04:31:59 PM PDT 24
Peak memory 214156 kb
Host smart-c3015c66-c509-43ca-bfd5-22ae05e36809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252813239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2252813239
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2649093822
Short name T2722
Test name
Test status
Simulation time 84724752 ps
CPU time 0.86 seconds
Started Jul 03 04:32:08 PM PDT 24
Finished Jul 03 04:32:09 PM PDT 24
Peak memory 205720 kb
Host smart-1bd2bd36-be18-474e-85d8-e74284504ede
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2649093822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2649093822
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.4133184415
Short name T2736
Test name
Test status
Simulation time 71610876 ps
CPU time 0.67 seconds
Started Jul 03 04:31:56 PM PDT 24
Finished Jul 03 04:31:57 PM PDT 24
Peak memory 205728 kb
Host smart-77b6e484-a2c0-45e0-a437-2bbb42d51631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4133184415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.4133184415
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2498527378
Short name T2743
Test name
Test status
Simulation time 51489940 ps
CPU time 1.09 seconds
Started Jul 03 04:32:13 PM PDT 24
Finished Jul 03 04:32:15 PM PDT 24
Peak memory 205856 kb
Host smart-711849e7-0f37-437c-acec-81b35434a050
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2498527378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2498527378
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4066307408
Short name T260
Test name
Test status
Simulation time 173860680 ps
CPU time 1.93 seconds
Started Jul 03 04:31:54 PM PDT 24
Finished Jul 03 04:31:57 PM PDT 24
Peak memory 214180 kb
Host smart-800e4d64-e802-43b4-9cd9-c9765e32bc3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4066307408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.4066307408
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3986878775
Short name T2726
Test name
Test status
Simulation time 256617223 ps
CPU time 2.41 seconds
Started Jul 03 04:32:07 PM PDT 24
Finished Jul 03 04:32:10 PM PDT 24
Peak memory 205848 kb
Host smart-7a73229e-72ea-4c4e-a2f3-9ba671a387b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3986878775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3986878775
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2978777586
Short name T2805
Test name
Test status
Simulation time 105956995 ps
CPU time 1.83 seconds
Started Jul 03 04:32:03 PM PDT 24
Finished Jul 03 04:32:05 PM PDT 24
Peak memory 214180 kb
Host smart-0ed0c855-b309-46cd-b5a4-72843a911b81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978777586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2978777586
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.232229661
Short name T280
Test name
Test status
Simulation time 48128110 ps
CPU time 0.85 seconds
Started Jul 03 04:32:13 PM PDT 24
Finished Jul 03 04:32:14 PM PDT 24
Peak memory 205728 kb
Host smart-2df25044-714b-46c0-8738-6110af925928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=232229661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.232229661
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2058098538
Short name T2734
Test name
Test status
Simulation time 65533800 ps
CPU time 0.7 seconds
Started Jul 03 04:31:50 PM PDT 24
Finished Jul 03 04:31:51 PM PDT 24
Peak memory 205732 kb
Host smart-2a95c6a7-91e7-4e3e-ab99-e095e0ce94b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2058098538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2058098538
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1030599010
Short name T221
Test name
Test status
Simulation time 169167709 ps
CPU time 1.59 seconds
Started Jul 03 04:32:03 PM PDT 24
Finished Jul 03 04:32:05 PM PDT 24
Peak memory 205840 kb
Host smart-187fa473-744d-40a6-8a7c-7c392f8a9295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1030599010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1030599010
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2223075252
Short name T2760
Test name
Test status
Simulation time 113976293 ps
CPU time 2.93 seconds
Started Jul 03 04:31:59 PM PDT 24
Finished Jul 03 04:32:02 PM PDT 24
Peak memory 214124 kb
Host smart-81dc72e4-c68f-4e8a-bb7f-90ed61a64c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2223075252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2223075252
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1294687105
Short name T328
Test name
Test status
Simulation time 1052775235 ps
CPU time 2.96 seconds
Started Jul 03 04:32:14 PM PDT 24
Finished Jul 03 04:32:18 PM PDT 24
Peak memory 205912 kb
Host smart-152b281b-e6bd-4460-a9a2-993fd170ea67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1294687105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1294687105
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3263475147
Short name T2754
Test name
Test status
Simulation time 102575192 ps
CPU time 2.39 seconds
Started Jul 03 04:32:16 PM PDT 24
Finished Jul 03 04:32:19 PM PDT 24
Peak memory 214164 kb
Host smart-7973c066-f5f2-4182-af62-68f1e1ca0de5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263475147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3263475147
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3430811236
Short name T283
Test name
Test status
Simulation time 45397674 ps
CPU time 0.79 seconds
Started Jul 03 04:32:17 PM PDT 24
Finished Jul 03 04:32:18 PM PDT 24
Peak memory 205732 kb
Host smart-b35e28cc-7075-4824-8672-138ea838534f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3430811236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3430811236
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.503042238
Short name T321
Test name
Test status
Simulation time 50166454 ps
CPU time 0.68 seconds
Started Jul 03 04:31:56 PM PDT 24
Finished Jul 03 04:31:57 PM PDT 24
Peak memory 205696 kb
Host smart-760d7694-7ae5-4ad1-a5ae-80693df0e830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=503042238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.503042238
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1264686617
Short name T293
Test name
Test status
Simulation time 329335051 ps
CPU time 1.74 seconds
Started Jul 03 04:31:57 PM PDT 24
Finished Jul 03 04:31:59 PM PDT 24
Peak memory 205808 kb
Host smart-a4d616a6-b264-421b-a532-d3cc3624fd14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1264686617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1264686617
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3551736542
Short name T2787
Test name
Test status
Simulation time 122640024 ps
CPU time 2.78 seconds
Started Jul 03 04:32:00 PM PDT 24
Finished Jul 03 04:32:03 PM PDT 24
Peak memory 221932 kb
Host smart-d3c684bb-0398-4dd6-aa4e-0bd86a4e1093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3551736542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3551736542
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3845737961
Short name T327
Test name
Test status
Simulation time 1879753358 ps
CPU time 6.28 seconds
Started Jul 03 04:32:09 PM PDT 24
Finished Jul 03 04:32:15 PM PDT 24
Peak memory 205872 kb
Host smart-80a88def-8431-4be9-b350-f61551a6ca25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3845737961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3845737961
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2707714915
Short name T286
Test name
Test status
Simulation time 183574288 ps
CPU time 2.13 seconds
Started Jul 03 04:32:06 PM PDT 24
Finished Jul 03 04:32:08 PM PDT 24
Peak memory 205928 kb
Host smart-a0d0ff76-8375-4ec1-ac51-0af34bf5b5ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2707714915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2707714915
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4083081509
Short name T2752
Test name
Test status
Simulation time 897210553 ps
CPU time 4.48 seconds
Started Jul 03 04:31:34 PM PDT 24
Finished Jul 03 04:31:39 PM PDT 24
Peak memory 205864 kb
Host smart-5b0cb51e-c98c-4bbb-b21b-b4a92625f296
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4083081509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.4083081509
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2253751137
Short name T2766
Test name
Test status
Simulation time 77821066 ps
CPU time 0.78 seconds
Started Jul 03 04:31:53 PM PDT 24
Finished Jul 03 04:31:54 PM PDT 24
Peak memory 205724 kb
Host smart-33976fae-0541-41fe-b6f3-956e2cfd93a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2253751137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2253751137
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1593182835
Short name T2770
Test name
Test status
Simulation time 139555411 ps
CPU time 1.85 seconds
Started Jul 03 04:31:48 PM PDT 24
Finished Jul 03 04:31:55 PM PDT 24
Peak memory 214172 kb
Host smart-227350a2-6bd2-4be2-8a48-6bb3273a82d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593182835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1593182835
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.363116522
Short name T2795
Test name
Test status
Simulation time 76015110 ps
CPU time 0.85 seconds
Started Jul 03 04:31:40 PM PDT 24
Finished Jul 03 04:31:41 PM PDT 24
Peak memory 205736 kb
Host smart-94f39c77-70fd-44ed-b250-846c9cb73fbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=363116522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.363116522
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2427057679
Short name T322
Test name
Test status
Simulation time 41517584 ps
CPU time 0.69 seconds
Started Jul 03 04:32:13 PM PDT 24
Finished Jul 03 04:32:14 PM PDT 24
Peak memory 205712 kb
Host smart-b30f9403-43af-4af7-a992-73ffe8e46616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2427057679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2427057679
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2576203046
Short name T275
Test name
Test status
Simulation time 92361500 ps
CPU time 2.21 seconds
Started Jul 03 04:32:03 PM PDT 24
Finished Jul 03 04:32:06 PM PDT 24
Peak memory 214096 kb
Host smart-006ecb0a-d151-4b6d-a341-13aa8c333fc0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2576203046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2576203046
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.954809856
Short name T2809
Test name
Test status
Simulation time 168441715 ps
CPU time 3.94 seconds
Started Jul 03 04:31:50 PM PDT 24
Finished Jul 03 04:31:54 PM PDT 24
Peak memory 205780 kb
Host smart-7edb5ac6-6ae0-40da-b40f-723dc6b15c37
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=954809856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.954809856
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.229119146
Short name T291
Test name
Test status
Simulation time 224770987 ps
CPU time 1.6 seconds
Started Jul 03 04:31:58 PM PDT 24
Finished Jul 03 04:32:00 PM PDT 24
Peak memory 205844 kb
Host smart-65a5f1c3-5a7a-4758-9985-a272269575d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=229119146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.229119146
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3814502128
Short name T257
Test name
Test status
Simulation time 157129061 ps
CPU time 2.87 seconds
Started Jul 03 04:32:01 PM PDT 24
Finished Jul 03 04:32:04 PM PDT 24
Peak memory 222336 kb
Host smart-216dbd9e-15bf-4543-9deb-0607abb1757b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3814502128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3814502128
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2840167011
Short name T331
Test name
Test status
Simulation time 966503579 ps
CPU time 4.88 seconds
Started Jul 03 04:31:43 PM PDT 24
Finished Jul 03 04:31:48 PM PDT 24
Peak memory 205860 kb
Host smart-81588560-09da-4c6b-9fe7-b4d93409ee69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2840167011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2840167011
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1395811416
Short name T2748
Test name
Test status
Simulation time 38192089 ps
CPU time 0.65 seconds
Started Jul 03 04:32:22 PM PDT 24
Finished Jul 03 04:32:23 PM PDT 24
Peak memory 205732 kb
Host smart-ee8a109f-0e7f-4a9d-b7a4-5f5d041ce364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1395811416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1395811416
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1263882047
Short name T319
Test name
Test status
Simulation time 40612017 ps
CPU time 0.66 seconds
Started Jul 03 04:31:57 PM PDT 24
Finished Jul 03 04:31:58 PM PDT 24
Peak memory 205724 kb
Host smart-02e2896c-175d-4078-84e7-74da3f30cf4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1263882047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1263882047
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2915486945
Short name T229
Test name
Test status
Simulation time 53534122 ps
CPU time 0.7 seconds
Started Jul 03 04:31:50 PM PDT 24
Finished Jul 03 04:31:51 PM PDT 24
Peak memory 205692 kb
Host smart-955c476b-cd96-49b0-b0d7-288ec6280dfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2915486945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2915486945
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.4255840825
Short name T231
Test name
Test status
Simulation time 39689397 ps
CPU time 0.66 seconds
Started Jul 03 04:32:10 PM PDT 24
Finished Jul 03 04:32:11 PM PDT 24
Peak memory 205732 kb
Host smart-d19e1c8d-f94b-4c16-92f8-2e03c7d9fca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4255840825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.4255840825
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1198555973
Short name T2730
Test name
Test status
Simulation time 53451138 ps
CPU time 0.67 seconds
Started Jul 03 04:31:54 PM PDT 24
Finished Jul 03 04:31:55 PM PDT 24
Peak memory 205708 kb
Host smart-bd909f5b-88f3-4fa2-91a2-38912d5de147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1198555973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1198555973
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.59454533
Short name T2732
Test name
Test status
Simulation time 50089150 ps
CPU time 0.69 seconds
Started Jul 03 04:32:08 PM PDT 24
Finished Jul 03 04:32:09 PM PDT 24
Peak memory 205712 kb
Host smart-f630c38a-883b-4f2a-802a-09495d945dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=59454533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.59454533
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1156415507
Short name T2794
Test name
Test status
Simulation time 55471997 ps
CPU time 0.71 seconds
Started Jul 03 04:32:21 PM PDT 24
Finished Jul 03 04:32:22 PM PDT 24
Peak memory 205732 kb
Host smart-33dc87f2-ac3f-4225-bb6a-d7860865c222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1156415507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1156415507
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2357016779
Short name T2814
Test name
Test status
Simulation time 43723786 ps
CPU time 0.66 seconds
Started Jul 03 04:31:57 PM PDT 24
Finished Jul 03 04:31:59 PM PDT 24
Peak memory 205704 kb
Host smart-ddb04662-ab85-464e-ae3b-ef51dea26697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2357016779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2357016779
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2158529975
Short name T2758
Test name
Test status
Simulation time 86787276 ps
CPU time 0.73 seconds
Started Jul 03 04:32:12 PM PDT 24
Finished Jul 03 04:32:13 PM PDT 24
Peak memory 205684 kb
Host smart-366e95e2-8909-45ce-a1d1-fb4788531a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2158529975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2158529975
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2454120482
Short name T300
Test name
Test status
Simulation time 200629172 ps
CPU time 2.01 seconds
Started Jul 03 04:31:35 PM PDT 24
Finished Jul 03 04:31:37 PM PDT 24
Peak memory 205860 kb
Host smart-bbf8b61a-b59e-400b-999f-11cf83531001
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2454120482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2454120482
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1291618368
Short name T276
Test name
Test status
Simulation time 1176028021 ps
CPU time 7.99 seconds
Started Jul 03 04:31:46 PM PDT 24
Finished Jul 03 04:31:54 PM PDT 24
Peak memory 205848 kb
Host smart-f3516aee-f5cb-49f8-a5e3-1209d42708ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1291618368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1291618368
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3201321733
Short name T2723
Test name
Test status
Simulation time 117617465 ps
CPU time 0.97 seconds
Started Jul 03 04:31:48 PM PDT 24
Finished Jul 03 04:31:49 PM PDT 24
Peak memory 205708 kb
Host smart-2d67cc21-3fbc-43cc-ba40-edbeed518206
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3201321733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3201321733
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2268190891
Short name T264
Test name
Test status
Simulation time 212156099 ps
CPU time 1.97 seconds
Started Jul 03 04:31:44 PM PDT 24
Finished Jul 03 04:31:46 PM PDT 24
Peak memory 214120 kb
Host smart-fb549db9-95c6-4e0f-a5fa-9232c9de26fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268190891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2268190891
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2005325280
Short name T2786
Test name
Test status
Simulation time 77179466 ps
CPU time 0.98 seconds
Started Jul 03 04:31:48 PM PDT 24
Finished Jul 03 04:31:50 PM PDT 24
Peak memory 205900 kb
Host smart-2dc435c2-c6e1-48d8-8440-ee60a64545c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2005325280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2005325280
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1484250924
Short name T312
Test name
Test status
Simulation time 50780738 ps
CPU time 0.67 seconds
Started Jul 03 04:32:16 PM PDT 24
Finished Jul 03 04:32:17 PM PDT 24
Peak memory 205692 kb
Host smart-f41e3a5e-e674-4c7d-aab4-4ae198277af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1484250924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1484250924
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1501267040
Short name T284
Test name
Test status
Simulation time 158693386 ps
CPU time 2.22 seconds
Started Jul 03 04:31:33 PM PDT 24
Finished Jul 03 04:31:36 PM PDT 24
Peak memory 214124 kb
Host smart-0ce2c8b1-a453-491b-9cf1-ce1625a1f903
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1501267040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1501267040
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.922669991
Short name T2768
Test name
Test status
Simulation time 214197000 ps
CPU time 3.79 seconds
Started Jul 03 04:31:56 PM PDT 24
Finished Jul 03 04:32:00 PM PDT 24
Peak memory 205800 kb
Host smart-15b03af9-4a70-428c-9682-0c012bdbd8d7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=922669991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.922669991
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2889054899
Short name T2747
Test name
Test status
Simulation time 140534670 ps
CPU time 1.63 seconds
Started Jul 03 04:31:46 PM PDT 24
Finished Jul 03 04:31:48 PM PDT 24
Peak memory 205912 kb
Host smart-eeb8bb7e-da68-468f-81e4-7bf8af9a9b28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2889054899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2889054899
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1361057589
Short name T247
Test name
Test status
Simulation time 128885761 ps
CPU time 2.27 seconds
Started Jul 03 04:32:14 PM PDT 24
Finished Jul 03 04:32:17 PM PDT 24
Peak memory 222204 kb
Host smart-4abf24a2-10fe-4a34-b8a8-3834da2f15fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1361057589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1361057589
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.81206269
Short name T219
Test name
Test status
Simulation time 269672283 ps
CPU time 2.18 seconds
Started Jul 03 04:32:05 PM PDT 24
Finished Jul 03 04:32:07 PM PDT 24
Peak memory 205888 kb
Host smart-9a99861f-6c68-45af-b0c8-70ef944e20da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=81206269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.81206269
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3429918163
Short name T307
Test name
Test status
Simulation time 34785164 ps
CPU time 0.64 seconds
Started Jul 03 04:32:04 PM PDT 24
Finished Jul 03 04:32:05 PM PDT 24
Peak memory 205732 kb
Host smart-4c649e07-a67f-4fbe-81fe-ffd770cc0903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3429918163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3429918163
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4154495350
Short name T232
Test name
Test status
Simulation time 77976670 ps
CPU time 0.69 seconds
Started Jul 03 04:31:59 PM PDT 24
Finished Jul 03 04:32:01 PM PDT 24
Peak memory 205692 kb
Host smart-9cdc6892-093a-476f-b34a-2e84768d724f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4154495350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.4154495350
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2508679796
Short name T2778
Test name
Test status
Simulation time 35593666 ps
CPU time 0.63 seconds
Started Jul 03 04:32:10 PM PDT 24
Finished Jul 03 04:32:11 PM PDT 24
Peak memory 205708 kb
Host smart-c7a8dad5-13b3-4b13-9577-e381c1ff5eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2508679796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2508679796
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2788986340
Short name T230
Test name
Test status
Simulation time 40928249 ps
CPU time 0.67 seconds
Started Jul 03 04:32:13 PM PDT 24
Finished Jul 03 04:32:15 PM PDT 24
Peak memory 205668 kb
Host smart-c79d4c90-05c4-45bf-9ac5-f8207c19c221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2788986340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2788986340
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2098552706
Short name T2755
Test name
Test status
Simulation time 36491140 ps
CPU time 0.67 seconds
Started Jul 03 04:31:56 PM PDT 24
Finished Jul 03 04:31:58 PM PDT 24
Peak memory 205656 kb
Host smart-a7d2dfa4-1a1e-424b-a8e9-a8ad29d1f5df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2098552706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2098552706
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3284415415
Short name T2807
Test name
Test status
Simulation time 39080360 ps
CPU time 0.7 seconds
Started Jul 03 04:32:14 PM PDT 24
Finished Jul 03 04:32:16 PM PDT 24
Peak memory 205736 kb
Host smart-d00e1c15-06e6-42ab-b9dd-256505d19c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3284415415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3284415415
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1391545115
Short name T2798
Test name
Test status
Simulation time 34065535 ps
CPU time 0.65 seconds
Started Jul 03 04:32:14 PM PDT 24
Finished Jul 03 04:32:15 PM PDT 24
Peak memory 205728 kb
Host smart-3027bc24-67e9-43f3-acb4-c4522031b83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1391545115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1391545115
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.875734861
Short name T2773
Test name
Test status
Simulation time 40118096 ps
CPU time 0.69 seconds
Started Jul 03 04:31:53 PM PDT 24
Finished Jul 03 04:31:54 PM PDT 24
Peak memory 205684 kb
Host smart-0a21a61a-cc74-4ca7-a637-eda373f62ba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=875734861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.875734861
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.768289413
Short name T2739
Test name
Test status
Simulation time 47941988 ps
CPU time 0.71 seconds
Started Jul 03 04:32:14 PM PDT 24
Finished Jul 03 04:32:16 PM PDT 24
Peak memory 205616 kb
Host smart-7aa12e04-f073-459e-bcda-31b12bde3a42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=768289413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.768289413
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3845641201
Short name T2759
Test name
Test status
Simulation time 63945015 ps
CPU time 0.65 seconds
Started Jul 03 04:32:23 PM PDT 24
Finished Jul 03 04:32:24 PM PDT 24
Peak memory 205648 kb
Host smart-b0350057-fb1b-4a04-9059-6174c6e83119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3845641201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3845641201
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.236780974
Short name T2753
Test name
Test status
Simulation time 242842193 ps
CPU time 2.09 seconds
Started Jul 03 04:31:55 PM PDT 24
Finished Jul 03 04:31:58 PM PDT 24
Peak memory 205868 kb
Host smart-430e5128-cdff-41e4-8474-6de3c17549ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=236780974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.236780974
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.924236159
Short name T249
Test name
Test status
Simulation time 805106223 ps
CPU time 5.04 seconds
Started Jul 03 04:31:43 PM PDT 24
Finished Jul 03 04:31:49 PM PDT 24
Peak memory 205900 kb
Host smart-cac90bd0-d208-47d1-9d85-46fd3a23cc0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=924236159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.924236159
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3554197600
Short name T304
Test name
Test status
Simulation time 129552935 ps
CPU time 0.85 seconds
Started Jul 03 04:31:47 PM PDT 24
Finished Jul 03 04:31:48 PM PDT 24
Peak memory 205708 kb
Host smart-af2c5865-0fa9-4147-9cff-a09a6b39a9e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3554197600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3554197600
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.882874479
Short name T2727
Test name
Test status
Simulation time 99419368 ps
CPU time 1.2 seconds
Started Jul 03 04:31:49 PM PDT 24
Finished Jul 03 04:31:50 PM PDT 24
Peak memory 215884 kb
Host smart-01247af1-886e-4f81-8b41-f3e9bec073d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882874479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.882874479
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.166745924
Short name T2791
Test name
Test status
Simulation time 42355836 ps
CPU time 0.79 seconds
Started Jul 03 04:31:59 PM PDT 24
Finished Jul 03 04:32:00 PM PDT 24
Peak memory 205728 kb
Host smart-b7e74e8f-af09-4277-ad4e-f547b6dacbd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=166745924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.166745924
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3410513105
Short name T281
Test name
Test status
Simulation time 206286999 ps
CPU time 2.37 seconds
Started Jul 03 04:31:57 PM PDT 24
Finished Jul 03 04:32:00 PM PDT 24
Peak memory 214124 kb
Host smart-aa39795e-47c9-4d6a-9e4a-8fe08f79d652
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3410513105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3410513105
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1192521092
Short name T2725
Test name
Test status
Simulation time 702470547 ps
CPU time 4.43 seconds
Started Jul 03 04:31:47 PM PDT 24
Finished Jul 03 04:31:51 PM PDT 24
Peak memory 205904 kb
Host smart-42535fe8-f6ad-4ba4-96a7-9f75096e682c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1192521092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1192521092
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1080655711
Short name T2788
Test name
Test status
Simulation time 53360030 ps
CPU time 0.99 seconds
Started Jul 03 04:31:52 PM PDT 24
Finished Jul 03 04:31:54 PM PDT 24
Peak memory 205860 kb
Host smart-0a5d6e83-9fa7-4799-a4b6-730341d8576d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1080655711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1080655711
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2034678395
Short name T2761
Test name
Test status
Simulation time 47417350 ps
CPU time 0.67 seconds
Started Jul 03 04:32:18 PM PDT 24
Finished Jul 03 04:32:19 PM PDT 24
Peak memory 205716 kb
Host smart-935b51f8-02a6-4b2d-a659-070a314c2a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2034678395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2034678395
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2063971077
Short name T2745
Test name
Test status
Simulation time 42917558 ps
CPU time 0.69 seconds
Started Jul 03 04:32:01 PM PDT 24
Finished Jul 03 04:32:02 PM PDT 24
Peak memory 205736 kb
Host smart-f894924e-0eb7-4c34-88f1-3327e18fbe73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2063971077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2063971077
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3466632853
Short name T2781
Test name
Test status
Simulation time 47141320 ps
CPU time 0.68 seconds
Started Jul 03 04:32:24 PM PDT 24
Finished Jul 03 04:32:25 PM PDT 24
Peak memory 205732 kb
Host smart-6b91e71f-5b57-4af1-a132-01bc484ce367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3466632853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3466632853
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3438117393
Short name T313
Test name
Test status
Simulation time 44067407 ps
CPU time 0.66 seconds
Started Jul 03 04:31:57 PM PDT 24
Finished Jul 03 04:31:59 PM PDT 24
Peak memory 205704 kb
Host smart-f20cb43b-84c1-43f6-9070-6f9e1f51b00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3438117393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3438117393
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1609963076
Short name T228
Test name
Test status
Simulation time 40900488 ps
CPU time 0.68 seconds
Started Jul 03 04:32:12 PM PDT 24
Finished Jul 03 04:32:13 PM PDT 24
Peak memory 205688 kb
Host smart-fedb8584-4968-4b52-80fe-fb9c25a6edc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609963076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1609963076
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.636658465
Short name T320
Test name
Test status
Simulation time 40313235 ps
CPU time 0.7 seconds
Started Jul 03 04:31:50 PM PDT 24
Finished Jul 03 04:31:51 PM PDT 24
Peak memory 205692 kb
Host smart-a16c2224-9287-40e1-ad22-4d3c4fdba14f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=636658465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.636658465
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3187549077
Short name T323
Test name
Test status
Simulation time 39850134 ps
CPU time 0.66 seconds
Started Jul 03 04:32:01 PM PDT 24
Finished Jul 03 04:32:02 PM PDT 24
Peak memory 205700 kb
Host smart-b775d7a5-f845-429b-86a5-d1e6eb9eb5b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3187549077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3187549077
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2079034720
Short name T2776
Test name
Test status
Simulation time 111971369 ps
CPU time 0.75 seconds
Started Jul 03 04:32:15 PM PDT 24
Finished Jul 03 04:32:16 PM PDT 24
Peak memory 205736 kb
Host smart-a658dc20-6f08-4b00-a729-0aec1bf35bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2079034720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2079034720
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.412829048
Short name T2733
Test name
Test status
Simulation time 61705183 ps
CPU time 0.68 seconds
Started Jul 03 04:32:10 PM PDT 24
Finished Jul 03 04:32:12 PM PDT 24
Peak memory 205696 kb
Host smart-3edf19d1-c380-431d-add6-a199f048e53b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=412829048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.412829048
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.87227274
Short name T2762
Test name
Test status
Simulation time 150052242 ps
CPU time 1.33 seconds
Started Jul 03 04:31:41 PM PDT 24
Finished Jul 03 04:31:48 PM PDT 24
Peak memory 214028 kb
Host smart-73be52bd-9653-4cca-8f47-77058f38a1ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87227274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_
csr_mem_rw_with_rand_reset.87227274
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1758317072
Short name T2813
Test name
Test status
Simulation time 61297751 ps
CPU time 0.89 seconds
Started Jul 03 04:32:12 PM PDT 24
Finished Jul 03 04:32:14 PM PDT 24
Peak memory 205660 kb
Host smart-b3fe53e7-ae27-4f05-9de5-c482249b964f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1758317072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1758317072
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2800255787
Short name T2789
Test name
Test status
Simulation time 40642859 ps
CPU time 0.66 seconds
Started Jul 03 04:31:47 PM PDT 24
Finished Jul 03 04:31:48 PM PDT 24
Peak memory 205732 kb
Host smart-bd8feee7-790d-45a5-b1b7-38fa88641694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2800255787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2800255787
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.726964435
Short name T295
Test name
Test status
Simulation time 191898956 ps
CPU time 1.56 seconds
Started Jul 03 04:32:07 PM PDT 24
Finished Jul 03 04:32:09 PM PDT 24
Peak memory 205868 kb
Host smart-f6fca5fb-1906-4ad5-a023-889031d3b4c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=726964435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.726964435
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1113780437
Short name T2792
Test name
Test status
Simulation time 184135089 ps
CPU time 2.02 seconds
Started Jul 03 04:31:43 PM PDT 24
Finished Jul 03 04:31:51 PM PDT 24
Peak memory 221568 kb
Host smart-e9f88bb7-7577-44e9-9e11-16fc7660342d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1113780437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1113780437
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3940847614
Short name T2801
Test name
Test status
Simulation time 133740691 ps
CPU time 1.29 seconds
Started Jul 03 04:32:01 PM PDT 24
Finished Jul 03 04:32:02 PM PDT 24
Peak memory 214160 kb
Host smart-4752fa6c-7d2b-462e-bdf3-ed1770698126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940847614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3940847614
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4157535759
Short name T282
Test name
Test status
Simulation time 51222329 ps
CPU time 0.98 seconds
Started Jul 03 04:32:04 PM PDT 24
Finished Jul 03 04:32:06 PM PDT 24
Peak memory 205908 kb
Host smart-d2941e29-812d-4500-9e0a-1b7729f7d906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4157535759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4157535759
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.520606238
Short name T311
Test name
Test status
Simulation time 48600507 ps
CPU time 0.65 seconds
Started Jul 03 04:31:56 PM PDT 24
Finished Jul 03 04:31:57 PM PDT 24
Peak memory 205716 kb
Host smart-bd8bc052-0b4b-4e1a-a50e-3667af725e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=520606238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.520606238
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2451530300
Short name T2735
Test name
Test status
Simulation time 149635610 ps
CPU time 1.38 seconds
Started Jul 03 04:31:53 PM PDT 24
Finished Jul 03 04:32:05 PM PDT 24
Peak memory 205872 kb
Host smart-6e694cbd-e2d7-4484-94ce-9bf0b51c03ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2451530300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2451530300
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.4048398218
Short name T2799
Test name
Test status
Simulation time 240748259 ps
CPU time 2.57 seconds
Started Jul 03 04:32:12 PM PDT 24
Finished Jul 03 04:32:15 PM PDT 24
Peak memory 214128 kb
Host smart-00898f3a-9922-4032-90e3-aa409ec30794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4048398218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.4048398218
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2928420663
Short name T302
Test name
Test status
Simulation time 649052884 ps
CPU time 2.88 seconds
Started Jul 03 04:32:08 PM PDT 24
Finished Jul 03 04:32:11 PM PDT 24
Peak memory 205860 kb
Host smart-249b01cd-a942-4895-a0d2-64854c40758d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2928420663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2928420663
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.943895379
Short name T2765
Test name
Test status
Simulation time 92563724 ps
CPU time 1.25 seconds
Started Jul 03 04:31:47 PM PDT 24
Finished Jul 03 04:31:48 PM PDT 24
Peak memory 214148 kb
Host smart-6e14b0ac-8826-449e-b48a-dab2520e3e9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943895379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.943895379
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.871978999
Short name T2729
Test name
Test status
Simulation time 62843484 ps
CPU time 0.8 seconds
Started Jul 03 04:31:41 PM PDT 24
Finished Jul 03 04:31:42 PM PDT 24
Peak memory 205704 kb
Host smart-1880557c-6d34-4fa9-af9b-eecf59e25ac8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=871978999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.871978999
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.320342798
Short name T2802
Test name
Test status
Simulation time 39473658 ps
CPU time 0.66 seconds
Started Jul 03 04:31:48 PM PDT 24
Finished Jul 03 04:31:50 PM PDT 24
Peak memory 205680 kb
Host smart-d312525b-3d58-4dbc-942d-a38284f58238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=320342798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.320342798
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3007882810
Short name T2744
Test name
Test status
Simulation time 165083642 ps
CPU time 1.64 seconds
Started Jul 03 04:32:03 PM PDT 24
Finished Jul 03 04:32:05 PM PDT 24
Peak memory 205836 kb
Host smart-0baf9411-ddf0-4ec3-b5fb-3dd022f07331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3007882810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3007882810
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3438470596
Short name T2808
Test name
Test status
Simulation time 286302310 ps
CPU time 2.61 seconds
Started Jul 03 04:31:36 PM PDT 24
Finished Jul 03 04:31:39 PM PDT 24
Peak memory 222064 kb
Host smart-c76c2b48-2743-493d-a330-e187d7d8dca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3438470596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3438470596
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.867673789
Short name T2796
Test name
Test status
Simulation time 133376339 ps
CPU time 1.24 seconds
Started Jul 03 04:31:36 PM PDT 24
Finished Jul 03 04:31:37 PM PDT 24
Peak memory 214148 kb
Host smart-a0427305-ce08-4a5e-a980-42ea9ef5f19e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867673789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.867673789
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3777185438
Short name T290
Test name
Test status
Simulation time 49280812 ps
CPU time 0.8 seconds
Started Jul 03 04:32:19 PM PDT 24
Finished Jul 03 04:32:20 PM PDT 24
Peak memory 205716 kb
Host smart-e9564803-09d6-4645-a61f-4c5518ca049d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3777185438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3777185438
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3480967812
Short name T309
Test name
Test status
Simulation time 69276655 ps
CPU time 0.74 seconds
Started Jul 03 04:32:12 PM PDT 24
Finished Jul 03 04:32:13 PM PDT 24
Peak memory 205720 kb
Host smart-52fd400f-d27a-4963-a038-8e1e99929569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3480967812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3480967812
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3361475503
Short name T2738
Test name
Test status
Simulation time 128111427 ps
CPU time 1.62 seconds
Started Jul 03 04:31:58 PM PDT 24
Finished Jul 03 04:32:00 PM PDT 24
Peak memory 205904 kb
Host smart-a9aef2d2-3a53-4e08-9253-f92c5cb17cd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3361475503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3361475503
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3333430851
Short name T258
Test name
Test status
Simulation time 127461705 ps
CPU time 1.39 seconds
Started Jul 03 04:31:41 PM PDT 24
Finished Jul 03 04:31:43 PM PDT 24
Peak memory 221580 kb
Host smart-69716e45-b9d2-4809-8106-683c58d47da6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3333430851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3333430851
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3705554213
Short name T324
Test name
Test status
Simulation time 866395097 ps
CPU time 5.05 seconds
Started Jul 03 04:31:52 PM PDT 24
Finished Jul 03 04:31:58 PM PDT 24
Peak memory 205876 kb
Host smart-ad1f6f3c-c626-4128-bbfa-895e8dc63892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3705554213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3705554213
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3591330726
Short name T2750
Test name
Test status
Simulation time 171763942 ps
CPU time 1.36 seconds
Started Jul 03 04:31:58 PM PDT 24
Finished Jul 03 04:32:00 PM PDT 24
Peak memory 214176 kb
Host smart-ba9b908b-d698-40fa-9ecd-7133d4fa77d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591330726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3591330726
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.969895705
Short name T2741
Test name
Test status
Simulation time 55079950 ps
CPU time 0.84 seconds
Started Jul 03 04:31:46 PM PDT 24
Finished Jul 03 04:31:47 PM PDT 24
Peak memory 205716 kb
Host smart-c3953c28-5805-4a0a-93c9-59ee44fe29d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=969895705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.969895705
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.546220243
Short name T2771
Test name
Test status
Simulation time 61904745 ps
CPU time 0.69 seconds
Started Jul 03 04:32:46 PM PDT 24
Finished Jul 03 04:32:48 PM PDT 24
Peak memory 204300 kb
Host smart-b1c047e3-3ee2-42ec-ad8e-4003f2af04a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=546220243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.546220243
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4194584882
Short name T294
Test name
Test status
Simulation time 198899980 ps
CPU time 1.23 seconds
Started Jul 03 04:31:33 PM PDT 24
Finished Jul 03 04:31:35 PM PDT 24
Peak memory 205936 kb
Host smart-9797dd25-3eb0-45cb-80f8-ddf808faebc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4194584882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.4194584882
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3654060787
Short name T2764
Test name
Test status
Simulation time 109484611 ps
CPU time 1.61 seconds
Started Jul 03 04:32:45 PM PDT 24
Finished Jul 03 04:32:48 PM PDT 24
Peak memory 204160 kb
Host smart-421a597f-4207-424b-a93b-08740cea92b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3654060787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3654060787
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1502954108
Short name T2746
Test name
Test status
Simulation time 1087772298 ps
CPU time 4.75 seconds
Started Jul 03 04:32:45 PM PDT 24
Finished Jul 03 04:32:52 PM PDT 24
Peak memory 203972 kb
Host smart-b6bd75ad-fd58-44b9-a052-1829cc2e90ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1502954108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1502954108
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.4138588175
Short name T2195
Test name
Test status
Simulation time 36513737 ps
CPU time 0.69 seconds
Started Jul 03 04:51:40 PM PDT 24
Finished Jul 03 04:51:41 PM PDT 24
Peak memory 206152 kb
Host smart-db3412dd-f462-4988-8caa-5c33dab0f932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4138588175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.4138588175
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.387091905
Short name T548
Test name
Test status
Simulation time 3961468910 ps
CPU time 4.42 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:51:32 PM PDT 24
Peak memory 206324 kb
Host smart-14d7e1f9-7bd6-44b5-ae29-5978d18f5124
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=387091905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.387091905
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2797871400
Short name T2194
Test name
Test status
Simulation time 13307862341 ps
CPU time 11.44 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:51:40 PM PDT 24
Peak memory 206368 kb
Host smart-db10fde3-3bfb-4c2a-94a0-0c4fef779d1b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2797871400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2797871400
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2533889339
Short name T213
Test name
Test status
Simulation time 23320601463 ps
CPU time 22.6 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:51:50 PM PDT 24
Peak memory 206148 kb
Host smart-503ed9b2-2164-46f0-ae08-398389e20e89
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2533889339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.2533889339
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2775834079
Short name T1528
Test name
Test status
Simulation time 194284404 ps
CPU time 0.87 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:51:29 PM PDT 24
Peak memory 206084 kb
Host smart-31d784cb-8e2c-4aaf-9e52-885ab5c07fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27758
34079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2775834079
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1804398627
Short name T2338
Test name
Test status
Simulation time 143188929 ps
CPU time 0.74 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:32 PM PDT 24
Peak memory 206104 kb
Host smart-f7f486b8-ed05-4a25-be2d-fa1cee57a10a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18043
98627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1804398627
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3091512475
Short name T1686
Test name
Test status
Simulation time 284131565 ps
CPU time 1.04 seconds
Started Jul 03 04:51:14 PM PDT 24
Finished Jul 03 04:51:16 PM PDT 24
Peak memory 205980 kb
Host smart-54dc7eef-1870-4c4a-b252-71c81c251c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30915
12475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3091512475
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_device_address.1310925135
Short name T2252
Test name
Test status
Simulation time 9109468633 ps
CPU time 17.34 seconds
Started Jul 03 04:51:36 PM PDT 24
Finished Jul 03 04:51:54 PM PDT 24
Peak memory 206436 kb
Host smart-dde840e7-2542-4b25-9266-7873cb62cc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13109
25135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.1310925135
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2775334049
Short name T579
Test name
Test status
Simulation time 379727235 ps
CPU time 1.23 seconds
Started Jul 03 04:51:25 PM PDT 24
Finished Jul 03 04:51:27 PM PDT 24
Peak memory 206092 kb
Host smart-51e1cd48-cbf4-4752-8afb-8eb998fbcae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27753
34049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2775334049
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1560137374
Short name T519
Test name
Test status
Simulation time 150686642 ps
CPU time 0.79 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 206108 kb
Host smart-25e7590e-efbe-4f24-935a-6d97519d67de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15601
37374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1560137374
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1100632475
Short name T2337
Test name
Test status
Simulation time 5118361281 ps
CPU time 132.95 seconds
Started Jul 03 04:51:19 PM PDT 24
Finished Jul 03 04:53:33 PM PDT 24
Peak memory 206424 kb
Host smart-0d302b9f-4e48-4971-adaa-f24112bd7364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11006
32475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1100632475
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.2288570742
Short name T1807
Test name
Test status
Simulation time 39265623 ps
CPU time 0.7 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:51:27 PM PDT 24
Peak memory 206084 kb
Host smart-fccafc9a-ef4f-4795-a540-147166f7454b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22885
70742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2288570742
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.4014701476
Short name T498
Test name
Test status
Simulation time 841673576 ps
CPU time 2.06 seconds
Started Jul 03 04:51:19 PM PDT 24
Finished Jul 03 04:51:22 PM PDT 24
Peak memory 206344 kb
Host smart-efcc2684-c493-44bc-bd17-879f37bb5b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40147
01476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.4014701476
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1417330159
Short name T1481
Test name
Test status
Simulation time 187347531 ps
CPU time 1.98 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206372 kb
Host smart-f232bb9b-ec35-47f2-a6d1-a2f3b8ff7ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14173
30159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1417330159
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2804355253
Short name T1135
Test name
Test status
Simulation time 111258635358 ps
CPU time 165.81 seconds
Started Jul 03 04:51:32 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206344 kb
Host smart-f81d6316-778d-4ded-a2ee-6dc7f85fe11a
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2804355253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2804355253
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2650437547
Short name T1222
Test name
Test status
Simulation time 83211395062 ps
CPU time 117.97 seconds
Started Jul 03 04:51:25 PM PDT 24
Finished Jul 03 04:53:23 PM PDT 24
Peak memory 206400 kb
Host smart-1b905844-6c95-4ef4-8a63-21436096d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650437547 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2650437547
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.3234766006
Short name T2475
Test name
Test status
Simulation time 102100002769 ps
CPU time 136.68 seconds
Started Jul 03 04:51:17 PM PDT 24
Finished Jul 03 04:53:34 PM PDT 24
Peak memory 206300 kb
Host smart-b6132b82-4794-4513-80cb-542382df6137
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3234766006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3234766006
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.1482909416
Short name T2629
Test name
Test status
Simulation time 97199591314 ps
CPU time 131.83 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:53:45 PM PDT 24
Peak memory 206396 kb
Host smart-04576e16-fd9a-44ce-9a6e-28b4dc7edc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482909416 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.1482909416
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.2127769870
Short name T2392
Test name
Test status
Simulation time 111135399817 ps
CPU time 156.08 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:54:06 PM PDT 24
Peak memory 206392 kb
Host smart-0b45ea85-3535-4e19-ad06-39edea40ca8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21277
69870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.2127769870
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.545863198
Short name T759
Test name
Test status
Simulation time 254868159 ps
CPU time 0.99 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 206080 kb
Host smart-bda2fd69-69ce-41d9-a681-178ab6509b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54586
3198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.545863198
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2776133549
Short name T678
Test name
Test status
Simulation time 160516232 ps
CPU time 0.79 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 206092 kb
Host smart-4ab1d5f4-6146-4041-851e-7d7d603e2ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27761
33549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2776133549
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1120735705
Short name T19
Test name
Test status
Simulation time 206205068 ps
CPU time 0.88 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:51:28 PM PDT 24
Peak memory 206088 kb
Host smart-9ee9ff5c-4668-48e9-b470-89407d655876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11207
35705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1120735705
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1649201427
Short name T2581
Test name
Test status
Simulation time 201283906 ps
CPU time 0.81 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:32 PM PDT 24
Peak memory 206048 kb
Host smart-2f5799fc-894d-42b4-aaf5-3b3337436e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16492
01427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1649201427
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.3148962725
Short name T81
Test name
Test status
Simulation time 442392806 ps
CPU time 1.24 seconds
Started Jul 03 04:51:36 PM PDT 24
Finished Jul 03 04:51:39 PM PDT 24
Peak memory 206088 kb
Host smart-77f34e65-31ff-4fca-8b8b-e8e0f397019e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31489
62725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.3148962725
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2879132540
Short name T1810
Test name
Test status
Simulation time 23408967118 ps
CPU time 24.69 seconds
Started Jul 03 04:51:18 PM PDT 24
Finished Jul 03 04:51:43 PM PDT 24
Peak memory 206180 kb
Host smart-226a9501-f653-452b-83f5-bab79bcaa1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28791
32540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2879132540
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1177270623
Short name T418
Test name
Test status
Simulation time 3295934522 ps
CPU time 3.95 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:37 PM PDT 24
Peak memory 206204 kb
Host smart-0f71cdf7-be3e-4989-bf2b-56d19a2dd0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11772
70623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1177270623
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.1104570845
Short name T583
Test name
Test status
Simulation time 7178180087 ps
CPU time 55.05 seconds
Started Jul 03 04:51:24 PM PDT 24
Finished Jul 03 04:52:20 PM PDT 24
Peak memory 206464 kb
Host smart-b75f0fd1-1382-4cfb-84b9-2665b069d38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11045
70845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.1104570845
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.1764021510
Short name T960
Test name
Test status
Simulation time 7720456966 ps
CPU time 54.01 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:52:27 PM PDT 24
Peak memory 206384 kb
Host smart-7407e527-618d-4dcd-aed0-537136b47fcb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1764021510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.1764021510
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.735121003
Short name T1273
Test name
Test status
Simulation time 236459910 ps
CPU time 0.92 seconds
Started Jul 03 04:51:32 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206104 kb
Host smart-505780fc-7977-4d37-9ee5-5fb6ff83c900
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=735121003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.735121003
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.692055774
Short name T1513
Test name
Test status
Simulation time 189122939 ps
CPU time 0.86 seconds
Started Jul 03 04:51:18 PM PDT 24
Finished Jul 03 04:51:20 PM PDT 24
Peak memory 206116 kb
Host smart-340aeba0-d5c1-4759-bd24-c1d47cab3256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69205
5774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.692055774
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.3939337694
Short name T1147
Test name
Test status
Simulation time 4436422338 ps
CPU time 32.55 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:52:04 PM PDT 24
Peak memory 206372 kb
Host smart-fbef45c2-d760-4b2f-ba9e-b619372ae34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39393
37694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3939337694
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.4160752771
Short name T34
Test name
Test status
Simulation time 5198675294 ps
CPU time 35.4 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:52:04 PM PDT 24
Peak memory 206348 kb
Host smart-13a3d29f-161c-48b3-96cf-8e242b004e7c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4160752771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.4160752771
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.2653565896
Short name T2119
Test name
Test status
Simulation time 147708169 ps
CPU time 0.77 seconds
Started Jul 03 04:51:19 PM PDT 24
Finished Jul 03 04:51:20 PM PDT 24
Peak memory 206132 kb
Host smart-a9c97376-8aae-4799-988b-307b81909136
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2653565896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.2653565896
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1726887557
Short name T1505
Test name
Test status
Simulation time 167447032 ps
CPU time 0.82 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 206112 kb
Host smart-f813e9b3-56e7-447a-9a4c-51ac493ea40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17268
87557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1726887557
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1731592810
Short name T59
Test name
Test status
Simulation time 530035161 ps
CPU time 1.37 seconds
Started Jul 03 04:51:20 PM PDT 24
Finished Jul 03 04:51:22 PM PDT 24
Peak memory 205996 kb
Host smart-4766fa8f-db29-49d3-bcdd-ba45377a9c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17315
92810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1731592810
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3999947978
Short name T436
Test name
Test status
Simulation time 173583554 ps
CPU time 0.82 seconds
Started Jul 03 04:51:24 PM PDT 24
Finished Jul 03 04:51:26 PM PDT 24
Peak memory 206064 kb
Host smart-297f36a6-8d80-4937-9a8f-4819e37c9d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39999
47978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3999947978
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3751787612
Short name T841
Test name
Test status
Simulation time 178104861 ps
CPU time 0.84 seconds
Started Jul 03 04:51:41 PM PDT 24
Finished Jul 03 04:51:42 PM PDT 24
Peak memory 205640 kb
Host smart-8a5c5290-5ad1-46fe-bb74-9af64c6af542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37517
87612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3751787612
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3773641532
Short name T870
Test name
Test status
Simulation time 190067301 ps
CPU time 0.92 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 206092 kb
Host smart-c85728e3-86ad-4332-8e5f-fbc7523a3786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37736
41532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3773641532
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3507086441
Short name T184
Test name
Test status
Simulation time 179936057 ps
CPU time 0.87 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:32 PM PDT 24
Peak memory 206108 kb
Host smart-05981d35-0da5-43a9-9ca2-9b96185ecba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35070
86441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3507086441
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.337871182
Short name T2412
Test name
Test status
Simulation time 220377122 ps
CPU time 0.87 seconds
Started Jul 03 04:51:32 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206108 kb
Host smart-3662263d-32cc-47f5-9d6b-be82b4923add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33787
1182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.337871182
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1879262333
Short name T891
Test name
Test status
Simulation time 229435425 ps
CPU time 0.96 seconds
Started Jul 03 04:51:42 PM PDT 24
Finished Jul 03 04:51:43 PM PDT 24
Peak memory 206104 kb
Host smart-f2109fee-9e48-468a-9112-e72f78f2b787
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1879262333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1879262333
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1151954547
Short name T2696
Test name
Test status
Simulation time 230406465 ps
CPU time 0.92 seconds
Started Jul 03 04:51:33 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206112 kb
Host smart-b44a1f7e-016b-44ce-aee2-03ba32cc2103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11519
54547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1151954547
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.2413982087
Short name T2228
Test name
Test status
Simulation time 216906745 ps
CPU time 0.93 seconds
Started Jul 03 04:51:41 PM PDT 24
Finished Jul 03 04:51:42 PM PDT 24
Peak memory 205720 kb
Host smart-c7b946ed-441e-4eaf-9b49-9055f67c53f4
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2413982087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.2413982087
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.585660649
Short name T223
Test name
Test status
Simulation time 204645426 ps
CPU time 0.97 seconds
Started Jul 03 04:51:36 PM PDT 24
Finished Jul 03 04:51:38 PM PDT 24
Peak memory 206060 kb
Host smart-007072b0-2f23-463d-a59f-e2860f0b457c
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=585660649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.585660649
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.567980479
Short name T2185
Test name
Test status
Simulation time 161089907 ps
CPU time 0.77 seconds
Started Jul 03 04:51:41 PM PDT 24
Finished Jul 03 04:51:42 PM PDT 24
Peak memory 206124 kb
Host smart-0e4d6b2e-05c1-4b94-9a0a-8d0cd49e5d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56798
0479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.567980479
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3352248358
Short name T1298
Test name
Test status
Simulation time 63717778 ps
CPU time 0.66 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 206096 kb
Host smart-44d2a6dc-f32a-4091-bc41-d8823a02ff9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33522
48358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3352248358
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.1179059731
Short name T1592
Test name
Test status
Simulation time 10738511481 ps
CPU time 22.83 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:51:49 PM PDT 24
Peak memory 206436 kb
Host smart-3fb4db38-5ff0-4767-ab69-7117f2360cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11790
59731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1179059731
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2722267598
Short name T1364
Test name
Test status
Simulation time 193624037 ps
CPU time 0.9 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 206128 kb
Host smart-ad6d32d2-4a41-4376-be72-21c266e13f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27222
67598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2722267598
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.286854186
Short name T1842
Test name
Test status
Simulation time 169622613 ps
CPU time 0.79 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 206128 kb
Host smart-ae05cfd3-5b48-4c19-a8a8-2f2e58059464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28685
4186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.286854186
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2931141879
Short name T1769
Test name
Test status
Simulation time 9543904806 ps
CPU time 62.55 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:52:36 PM PDT 24
Peak memory 206348 kb
Host smart-eac07606-79f5-4b31-a93d-77a52f14c2ac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2931141879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2931141879
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.434338088
Short name T193
Test name
Test status
Simulation time 5897296257 ps
CPU time 38.21 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:52:07 PM PDT 24
Peak memory 206716 kb
Host smart-3461077f-43af-46de-b914-ccb2883faa23
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=434338088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.434338088
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.4127354330
Short name T1105
Test name
Test status
Simulation time 7340879102 ps
CPU time 37.59 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206308 kb
Host smart-ded0d84b-a06c-4497-94cc-c4df25b63636
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4127354330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.4127354330
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1296202448
Short name T2433
Test name
Test status
Simulation time 240336714 ps
CPU time 0.9 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 206104 kb
Host smart-e8d7af46-78da-4cd0-9065-9e6289fd8517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12962
02448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1296202448
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.2384886639
Short name T1959
Test name
Test status
Simulation time 151543536 ps
CPU time 0.78 seconds
Started Jul 03 04:51:32 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 205972 kb
Host smart-57835d21-8d30-4a1b-b835-60df870d864c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23848
86639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.2384886639
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.1614982063
Short name T2636
Test name
Test status
Simulation time 318307109 ps
CPU time 0.95 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:51:30 PM PDT 24
Peak memory 206120 kb
Host smart-fd44aecb-1646-4d47-97b1-5bacf83c1347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16149
82063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.1614982063
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2282861074
Short name T731
Test name
Test status
Simulation time 150366913 ps
CPU time 0.82 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 206104 kb
Host smart-c155e0d3-6bf6-4967-97cb-62a42f66770a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22828
61074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2282861074
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1512149973
Short name T1244
Test name
Test status
Simulation time 165482530 ps
CPU time 0.77 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:51:28 PM PDT 24
Peak memory 206128 kb
Host smart-d09601d2-bb85-4d1a-8eaa-e015b58ff99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15121
49973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1512149973
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2579478192
Short name T2203
Test name
Test status
Simulation time 247862674 ps
CPU time 1.01 seconds
Started Jul 03 04:51:44 PM PDT 24
Finished Jul 03 04:51:46 PM PDT 24
Peak memory 206104 kb
Host smart-17f85bcc-041f-4b0b-97ab-ec2069944b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25794
78192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2579478192
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2974048371
Short name T2575
Test name
Test status
Simulation time 6665155320 ps
CPU time 183.79 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:54:37 PM PDT 24
Peak memory 206424 kb
Host smart-68965132-56da-4442-94ec-cf597896de14
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2974048371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2974048371
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1325308442
Short name T1951
Test name
Test status
Simulation time 179926568 ps
CPU time 0.81 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 205976 kb
Host smart-413dd130-a625-490a-9d96-b8c167397596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13253
08442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1325308442
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3735267079
Short name T2351
Test name
Test status
Simulation time 212535499 ps
CPU time 0.79 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 206108 kb
Host smart-5ce628c4-fb3a-4755-8252-300673eba487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37352
67079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3735267079
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.999397392
Short name T2644
Test name
Test status
Simulation time 265696319 ps
CPU time 0.98 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 206044 kb
Host smart-d9ce751f-14d1-413c-8712-656d9158e5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99939
7392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.999397392
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.308145878
Short name T581
Test name
Test status
Simulation time 4427352702 ps
CPU time 118.9 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206416 kb
Host smart-7ae565eb-f763-4c26-a3ba-c9937a0b6d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30814
5878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.308145878
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3236556952
Short name T188
Test name
Test status
Simulation time 10979330751 ps
CPU time 64.78 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:52:37 PM PDT 24
Peak memory 206356 kb
Host smart-2b70f1f6-1bcb-4d55-889b-7e5ea47f27b9
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3236556952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3236556952
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.3452115687
Short name T1048
Test name
Test status
Simulation time 53992316 ps
CPU time 0.74 seconds
Started Jul 03 04:51:33 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206160 kb
Host smart-6af2d5a3-4b37-4d27-98df-22ed6410398c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3452115687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.3452115687
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.671117451
Short name T1238
Test name
Test status
Simulation time 3515592718 ps
CPU time 4.28 seconds
Started Jul 03 04:51:36 PM PDT 24
Finished Jul 03 04:51:41 PM PDT 24
Peak memory 206420 kb
Host smart-98c0254f-f161-42b3-ac45-947a9ddc00fd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=671117451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.671117451
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.769498575
Short name T1146
Test name
Test status
Simulation time 13294313179 ps
CPU time 16.23 seconds
Started Jul 03 04:51:37 PM PDT 24
Finished Jul 03 04:51:54 PM PDT 24
Peak memory 206176 kb
Host smart-82f81149-849f-4cd0-9b63-2f36eb74135d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=769498575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.769498575
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.199726684
Short name T557
Test name
Test status
Simulation time 23419179510 ps
CPU time 23.03 seconds
Started Jul 03 04:51:36 PM PDT 24
Finished Jul 03 04:52:00 PM PDT 24
Peak memory 206364 kb
Host smart-c4c50060-9ab7-4fd2-b832-b899e216155b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=199726684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.199726684
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1780549869
Short name T1659
Test name
Test status
Simulation time 160447521 ps
CPU time 0.77 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:32 PM PDT 24
Peak memory 206104 kb
Host smart-ed1d57cd-5b71-44fd-b53d-d2c79a0790ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17805
49869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1780549869
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.4018719520
Short name T352
Test name
Test status
Simulation time 161802634 ps
CPU time 0.82 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 206096 kb
Host smart-71671426-fa79-4bb8-a6ce-4aa32b047479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40187
19520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.4018719520
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.4082937355
Short name T391
Test name
Test status
Simulation time 266813834 ps
CPU time 1.06 seconds
Started Jul 03 04:51:32 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206076 kb
Host smart-565ca947-5953-4f14-9b64-9cc22c6a962c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40829
37355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.4082937355
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1619633873
Short name T2603
Test name
Test status
Simulation time 664192896 ps
CPU time 1.69 seconds
Started Jul 03 04:51:27 PM PDT 24
Finished Jul 03 04:51:30 PM PDT 24
Peak memory 206128 kb
Host smart-e2540689-d21b-4edd-acd7-f438af50f1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16196
33873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1619633873
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.366413063
Short name T1645
Test name
Test status
Simulation time 9753159875 ps
CPU time 18.63 seconds
Started Jul 03 04:51:27 PM PDT 24
Finished Jul 03 04:51:47 PM PDT 24
Peak memory 206432 kb
Host smart-bd780675-36c2-4efb-8882-b2ff46e4e633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36641
3063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.366413063
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.11152021
Short name T550
Test name
Test status
Simulation time 445085619 ps
CPU time 1.3 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 206096 kb
Host smart-8a27612b-1ca0-485d-96e7-a9f895191586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11152
021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.11152021
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2556975065
Short name T425
Test name
Test status
Simulation time 146052662 ps
CPU time 0.88 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:32 PM PDT 24
Peak memory 206140 kb
Host smart-ef44b355-8b11-4394-9333-df071f4a6a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25569
75065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2556975065
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1235810574
Short name T724
Test name
Test status
Simulation time 83095912 ps
CPU time 0.73 seconds
Started Jul 03 04:51:39 PM PDT 24
Finished Jul 03 04:51:40 PM PDT 24
Peak memory 205992 kb
Host smart-4b263cdb-a78b-42a8-98c0-ac8a077be6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12358
10574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1235810574
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.666882447
Short name T2511
Test name
Test status
Simulation time 810800225 ps
CPU time 2.13 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 206308 kb
Host smart-cdac6696-0702-44d5-bfd9-337cf1d77816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66688
2447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.666882447
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2959147534
Short name T1352
Test name
Test status
Simulation time 159522629 ps
CPU time 1.54 seconds
Started Jul 03 04:51:33 PM PDT 24
Finished Jul 03 04:51:36 PM PDT 24
Peak memory 206376 kb
Host smart-15fbdb85-c636-4d5f-a334-83499438bd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29591
47534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2959147534
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.502380281
Short name T2471
Test name
Test status
Simulation time 94211853958 ps
CPU time 154.13 seconds
Started Jul 03 04:51:39 PM PDT 24
Finished Jul 03 04:54:13 PM PDT 24
Peak memory 206384 kb
Host smart-71d1c2f9-91c3-4b2e-888d-b00929d8e07b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=502380281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.502380281
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.819382308
Short name T1609
Test name
Test status
Simulation time 98340376899 ps
CPU time 140.69 seconds
Started Jul 03 04:51:35 PM PDT 24
Finished Jul 03 04:53:56 PM PDT 24
Peak memory 206392 kb
Host smart-1c04ab7a-de0c-4b20-ac3f-c0ad684983ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819382308 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.819382308
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.1290687740
Short name T2547
Test name
Test status
Simulation time 119098160592 ps
CPU time 173.71 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:54:21 PM PDT 24
Peak memory 206348 kb
Host smart-93b53f90-6890-4484-afa6-ed44077c3280
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1290687740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.1290687740
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.293789560
Short name T486
Test name
Test status
Simulation time 96216823990 ps
CPU time 119 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:53:32 PM PDT 24
Peak memory 206396 kb
Host smart-923d2244-9b92-4013-9359-43ea34c5de05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293789560 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.293789560
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.3158005197
Short name T2598
Test name
Test status
Simulation time 114134620183 ps
CPU time 156.75 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:54:09 PM PDT 24
Peak memory 206316 kb
Host smart-d4d7545e-7c0e-44bb-9293-41e5ba90b808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31580
05197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.3158005197
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2704309392
Short name T2003
Test name
Test status
Simulation time 201772354 ps
CPU time 0.86 seconds
Started Jul 03 04:51:32 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206100 kb
Host smart-f9aaae4f-f5a5-4d2c-8890-54aa97d9434b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27043
09392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2704309392
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.77513934
Short name T1001
Test name
Test status
Simulation time 145863720 ps
CPU time 0.75 seconds
Started Jul 03 04:51:36 PM PDT 24
Finished Jul 03 04:51:37 PM PDT 24
Peak memory 206088 kb
Host smart-19fb0edd-ba5b-4cf2-8b53-f65e83a41ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77513
934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.77513934
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2268145033
Short name T2335
Test name
Test status
Simulation time 180213613 ps
CPU time 0.82 seconds
Started Jul 03 04:51:40 PM PDT 24
Finished Jul 03 04:51:41 PM PDT 24
Peak memory 206088 kb
Host smart-552cfc42-bfe6-44ae-91b7-5a6e1d55de94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22681
45033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2268145033
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.1331306068
Short name T1987
Test name
Test status
Simulation time 8910670810 ps
CPU time 62.79 seconds
Started Jul 03 04:51:42 PM PDT 24
Finished Jul 03 04:52:45 PM PDT 24
Peak memory 206460 kb
Host smart-12c7a6fc-3ae2-412e-be39-f8db8bccee07
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1331306068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.1331306068
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2444639917
Short name T1059
Test name
Test status
Simulation time 231940854 ps
CPU time 0.91 seconds
Started Jul 03 04:51:34 PM PDT 24
Finished Jul 03 04:51:36 PM PDT 24
Peak memory 206132 kb
Host smart-f7c1c2ad-16f5-4383-a334-59f7445b006c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24446
39917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2444639917
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.308084837
Short name T1663
Test name
Test status
Simulation time 23375688577 ps
CPU time 30.02 seconds
Started Jul 03 04:51:34 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206196 kb
Host smart-55d57bdb-e366-4bbf-bf28-6fc26ccfeef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30808
4837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.308084837
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.2481899561
Short name T2484
Test name
Test status
Simulation time 3310411865 ps
CPU time 4.13 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:51:32 PM PDT 24
Peak memory 206192 kb
Host smart-0824d847-7512-4756-93eb-5fb7327a8c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24818
99561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.2481899561
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2888135940
Short name T2332
Test name
Test status
Simulation time 12727013414 ps
CPU time 118.69 seconds
Started Jul 03 04:51:26 PM PDT 24
Finished Jul 03 04:53:26 PM PDT 24
Peak memory 206300 kb
Host smart-a35fe0a7-ab77-4856-9c0f-df727be2d03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881
35940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2888135940
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1048371557
Short name T1220
Test name
Test status
Simulation time 7102436012 ps
CPU time 189.5 seconds
Started Jul 03 04:51:27 PM PDT 24
Finished Jul 03 04:54:38 PM PDT 24
Peak memory 206384 kb
Host smart-0b3f3d09-72ab-4008-8aba-057ef42680fb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1048371557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1048371557
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.716894048
Short name T1136
Test name
Test status
Simulation time 252768963 ps
CPU time 0.97 seconds
Started Jul 03 04:51:27 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 206112 kb
Host smart-b63c73ae-245e-478f-9b45-4d10e92f45f9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=716894048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.716894048
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3258303689
Short name T1391
Test name
Test status
Simulation time 199160546 ps
CPU time 0.85 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 206076 kb
Host smart-f2f75acc-e278-4b30-b7a1-2e1d1fca2d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32583
03689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3258303689
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3871250126
Short name T640
Test name
Test status
Simulation time 4960597223 ps
CPU time 37.55 seconds
Started Jul 03 04:51:39 PM PDT 24
Finished Jul 03 04:52:17 PM PDT 24
Peak memory 206380 kb
Host smart-dce6c3b9-d574-4fd9-b591-3c41c0b52518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
50126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3871250126
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2474220944
Short name T1055
Test name
Test status
Simulation time 6252131530 ps
CPU time 46.6 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:52:19 PM PDT 24
Peak memory 206340 kb
Host smart-2c05f2e7-1b1f-499e-a645-71d5289361fa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2474220944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2474220944
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.622636822
Short name T2543
Test name
Test status
Simulation time 164811781 ps
CPU time 0.83 seconds
Started Jul 03 04:51:34 PM PDT 24
Finished Jul 03 04:51:36 PM PDT 24
Peak memory 206072 kb
Host smart-6d5c1ff5-c218-484b-a1ec-90fd96c49cc5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=622636822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.622636822
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1413618277
Short name T1527
Test name
Test status
Simulation time 153031072 ps
CPU time 0.77 seconds
Started Jul 03 04:51:33 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206028 kb
Host smart-8211b443-9c81-42d7-87a1-f0f8bf128348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14136
18277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1413618277
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.2387025507
Short name T1888
Test name
Test status
Simulation time 157972521 ps
CPU time 0.81 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 206072 kb
Host smart-634c097a-09b3-4e1a-a356-b45f6e88899b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23870
25507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2387025507
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.337203986
Short name T1553
Test name
Test status
Simulation time 179452413 ps
CPU time 0.79 seconds
Started Jul 03 04:51:37 PM PDT 24
Finished Jul 03 04:51:39 PM PDT 24
Peak memory 206104 kb
Host smart-fe670ef5-3ca6-4a54-8b16-b83f9109204e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33720
3986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.337203986
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.604231036
Short name T958
Test name
Test status
Simulation time 183165735 ps
CPU time 0.88 seconds
Started Jul 03 04:51:37 PM PDT 24
Finished Jul 03 04:51:39 PM PDT 24
Peak memory 206084 kb
Host smart-534bd837-0c5c-46b1-8e91-235394a62cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60423
1036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.604231036
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3398957573
Short name T202
Test name
Test status
Simulation time 154910646 ps
CPU time 0.8 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:31 PM PDT 24
Peak memory 206108 kb
Host smart-a66290cc-3620-43ad-a434-86dc0eca963a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33989
57573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3398957573
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.1702711921
Short name T1946
Test name
Test status
Simulation time 198828646 ps
CPU time 0.91 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 206052 kb
Host smart-37ee0942-9486-409c-aea6-9be5912291b2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1702711921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1702711921
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.368063619
Short name T224
Test name
Test status
Simulation time 194873175 ps
CPU time 0.87 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 206084 kb
Host smart-1973571a-3799-486e-9b59-89392e8b9df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36806
3619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.368063619
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.427684090
Short name T1044
Test name
Test status
Simulation time 157379974 ps
CPU time 0.77 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 206076 kb
Host smart-cb5418b6-6303-4cfd-90db-44e75a2e50e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42768
4090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.427684090
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2588309746
Short name T1011
Test name
Test status
Simulation time 175703463 ps
CPU time 0.83 seconds
Started Jul 03 04:51:34 PM PDT 24
Finished Jul 03 04:51:36 PM PDT 24
Peak memory 206112 kb
Host smart-7a157184-f978-40c9-aacb-b835a599ffe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25883
09746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2588309746
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2946249853
Short name T1791
Test name
Test status
Simulation time 225039486 ps
CPU time 0.87 seconds
Started Jul 03 04:51:37 PM PDT 24
Finished Jul 03 04:51:39 PM PDT 24
Peak memory 206100 kb
Host smart-58045d44-803d-4641-9067-967bb67d57e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29462
49853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2946249853
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.1209938647
Short name T169
Test name
Test status
Simulation time 11079241339 ps
CPU time 69.91 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:52:40 PM PDT 24
Peak memory 206456 kb
Host smart-1aac7350-179d-42f1-be2d-b4862b5428c6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1209938647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.1209938647
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.2776307391
Short name T932
Test name
Test status
Simulation time 8889986962 ps
CPU time 131.5 seconds
Started Jul 03 04:51:33 PM PDT 24
Finished Jul 03 04:53:46 PM PDT 24
Peak memory 206492 kb
Host smart-909d1872-3f87-4577-a6df-934a21bee2af
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2776307391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2776307391
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.2941051970
Short name T1415
Test name
Test status
Simulation time 214463481 ps
CPU time 0.82 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 206104 kb
Host smart-ca9ac418-f93b-4106-854b-45cb133b6656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29410
51970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.2941051970
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2053846347
Short name T2036
Test name
Test status
Simulation time 174551285 ps
CPU time 0.79 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:51:33 PM PDT 24
Peak memory 206112 kb
Host smart-2d1a0d0a-667e-4501-8bb4-4f4f7e62e835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20538
46347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2053846347
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3972526453
Short name T466
Test name
Test status
Simulation time 142401565 ps
CPU time 0.79 seconds
Started Jul 03 04:51:29 PM PDT 24
Finished Jul 03 04:51:32 PM PDT 24
Peak memory 205992 kb
Host smart-6adf05c3-f7bc-4bbb-9c8a-b3f8d6b1b68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
26453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3972526453
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3595352909
Short name T88
Test name
Test status
Simulation time 143938955 ps
CPU time 0.81 seconds
Started Jul 03 04:51:34 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206136 kb
Host smart-1c220c41-b086-48a1-9943-e83320063708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35953
52909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3595352909
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1008618649
Short name T215
Test name
Test status
Simulation time 345907049 ps
CPU time 1.2 seconds
Started Jul 03 04:51:52 PM PDT 24
Finished Jul 03 04:51:53 PM PDT 24
Peak memory 223984 kb
Host smart-eb479774-d13c-4903-bacb-c66eef602e0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1008618649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1008618649
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1089641376
Short name T2456
Test name
Test status
Simulation time 415525442 ps
CPU time 1.29 seconds
Started Jul 03 04:51:39 PM PDT 24
Finished Jul 03 04:51:41 PM PDT 24
Peak memory 206112 kb
Host smart-cef66aa6-8086-468a-932e-bfb01260d9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10896
41376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1089641376
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.1777804245
Short name T2448
Test name
Test status
Simulation time 202425225 ps
CPU time 0.88 seconds
Started Jul 03 04:51:38 PM PDT 24
Finished Jul 03 04:51:40 PM PDT 24
Peak memory 206076 kb
Host smart-0434ad32-b16e-44a6-a923-24b0b2cb1c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17778
04245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.1777804245
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.625520847
Short name T648
Test name
Test status
Simulation time 165115856 ps
CPU time 0.8 seconds
Started Jul 03 04:51:32 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206044 kb
Host smart-bcb7befb-96b8-468d-834f-8a842d3b0581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62552
0847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.625520847
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3383444087
Short name T2031
Test name
Test status
Simulation time 159232786 ps
CPU time 0.81 seconds
Started Jul 03 04:51:31 PM PDT 24
Finished Jul 03 04:51:34 PM PDT 24
Peak memory 205960 kb
Host smart-2d5bb16a-7217-4c1f-8365-194cbbc7277d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33834
44087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3383444087
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3359119327
Short name T1209
Test name
Test status
Simulation time 234080843 ps
CPU time 0.97 seconds
Started Jul 03 04:51:33 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206076 kb
Host smart-40c874cd-1d35-43b5-b55f-d76c1f02e79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33591
19327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3359119327
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.3641457135
Short name T1025
Test name
Test status
Simulation time 5398852281 ps
CPU time 35.75 seconds
Started Jul 03 04:51:28 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206380 kb
Host smart-27afd772-869f-4245-93af-5829ceddce22
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3641457135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.3641457135
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2933249782
Short name T2382
Test name
Test status
Simulation time 171631724 ps
CPU time 0.83 seconds
Started Jul 03 04:51:36 PM PDT 24
Finished Jul 03 04:51:37 PM PDT 24
Peak memory 206132 kb
Host smart-b0842c09-9c03-4d89-885b-818787dd9b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29332
49782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2933249782
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1517905656
Short name T407
Test name
Test status
Simulation time 177417714 ps
CPU time 0.84 seconds
Started Jul 03 04:51:36 PM PDT 24
Finished Jul 03 04:51:37 PM PDT 24
Peak memory 206108 kb
Host smart-5923a921-8a77-42ee-9b96-6250c0fd5632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15179
05656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1517905656
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.3574754510
Short name T2170
Test name
Test status
Simulation time 974577174 ps
CPU time 2.11 seconds
Started Jul 03 04:51:32 PM PDT 24
Finished Jul 03 04:51:36 PM PDT 24
Peak memory 206360 kb
Host smart-b9bc8a9e-a573-42a5-8c33-5dfa5769db78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35747
54510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.3574754510
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2426960488
Short name T2496
Test name
Test status
Simulation time 5051901118 ps
CPU time 38.93 seconds
Started Jul 03 04:51:30 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206444 kb
Host smart-0c996cc5-3725-4d57-a6e8-29747f8ca02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269
60488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2426960488
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.729959226
Short name T2399
Test name
Test status
Simulation time 10684491117 ps
CPU time 270.78 seconds
Started Jul 03 04:51:32 PM PDT 24
Finished Jul 03 04:56:05 PM PDT 24
Peak memory 206392 kb
Host smart-35026a8d-3d9d-431e-aa35-265c522b2044
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=729959226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.729959226
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.1389810779
Short name T1935
Test name
Test status
Simulation time 42653015 ps
CPU time 0.67 seconds
Started Jul 03 04:53:03 PM PDT 24
Finished Jul 03 04:53:05 PM PDT 24
Peak memory 206144 kb
Host smart-c5177160-7b53-4c93-94db-f729aa3d6915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1389810779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.1389810779
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.568985741
Short name T961
Test name
Test status
Simulation time 3838969104 ps
CPU time 4.86 seconds
Started Jul 03 04:52:50 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206384 kb
Host smart-d4a18985-568f-4ecd-9873-227c4141d651
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=568985741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.568985741
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2549392088
Short name T1919
Test name
Test status
Simulation time 13331827154 ps
CPU time 14.6 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:53:13 PM PDT 24
Peak memory 206192 kb
Host smart-640a9e52-864c-4b3e-8eb6-a55225ae2b95
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2549392088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2549392088
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1749944273
Short name T2014
Test name
Test status
Simulation time 23357791856 ps
CPU time 26.19 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:53:22 PM PDT 24
Peak memory 206120 kb
Host smart-9dd4c7bf-8b87-4af0-96ba-ac33900d1904
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1749944273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1749944273
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2914840502
Short name T1713
Test name
Test status
Simulation time 236764156 ps
CPU time 0.95 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:55 PM PDT 24
Peak memory 206092 kb
Host smart-93b5502c-f2d8-45c9-8c2c-2412b7dbfb3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29148
40502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2914840502
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3486378272
Short name T490
Test name
Test status
Simulation time 176037356 ps
CPU time 0.82 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 205940 kb
Host smart-14d5c556-c145-468f-b12c-0bd497fbc4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34863
78272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3486378272
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.697310318
Short name T182
Test name
Test status
Simulation time 608005763 ps
CPU time 1.78 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206288 kb
Host smart-8ae39a2c-57e3-436f-8d3c-9181a0b1624a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69731
0318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.697310318
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1597813763
Short name T2156
Test name
Test status
Simulation time 662235799 ps
CPU time 1.8 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:55 PM PDT 24
Peak memory 206272 kb
Host smart-fd79cb09-8123-4866-9823-9054243ab074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15978
13763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1597813763
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.2354134899
Short name T2213
Test name
Test status
Simulation time 6323683875 ps
CPU time 13.04 seconds
Started Jul 03 04:52:45 PM PDT 24
Finished Jul 03 04:52:58 PM PDT 24
Peak memory 206352 kb
Host smart-d1a18c60-7e92-4595-8d9c-415ff1a20d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23541
34899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.2354134899
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2046342648
Short name T801
Test name
Test status
Simulation time 353929371 ps
CPU time 1.17 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:55 PM PDT 24
Peak memory 206084 kb
Host smart-ff3b57ee-23bf-49ee-97da-3daaa480684b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20463
42648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2046342648
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.522182008
Short name T1410
Test name
Test status
Simulation time 145841380 ps
CPU time 0.76 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:55 PM PDT 24
Peak memory 206092 kb
Host smart-b853d8b4-a71e-4051-905a-bda0e6c432fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52218
2008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.522182008
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1654129996
Short name T2637
Test name
Test status
Simulation time 29843412 ps
CPU time 0.67 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:52:57 PM PDT 24
Peak memory 206116 kb
Host smart-e0d33d3a-918f-4a1a-95b4-aefd13dd4943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16541
29996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1654129996
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3526694860
Short name T1208
Test name
Test status
Simulation time 773978177 ps
CPU time 2.14 seconds
Started Jul 03 04:52:48 PM PDT 24
Finished Jul 03 04:52:50 PM PDT 24
Peak memory 206344 kb
Host smart-40ab8156-396c-47be-af67-c97c108a42e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35266
94860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3526694860
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1530737510
Short name T2625
Test name
Test status
Simulation time 195886897 ps
CPU time 0.82 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:53:00 PM PDT 24
Peak memory 206112 kb
Host smart-0459cf5f-8568-4c25-a927-3559648cbbb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15307
37510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1530737510
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3649869925
Short name T791
Test name
Test status
Simulation time 162918208 ps
CPU time 0.78 seconds
Started Jul 03 04:52:50 PM PDT 24
Finished Jul 03 04:52:51 PM PDT 24
Peak memory 206128 kb
Host smart-ce9e2e24-78be-4f48-b65c-97cb691545d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36498
69925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3649869925
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3993986141
Short name T2552
Test name
Test status
Simulation time 210930353 ps
CPU time 0.87 seconds
Started Jul 03 04:52:54 PM PDT 24
Finished Jul 03 04:52:57 PM PDT 24
Peak memory 206088 kb
Host smart-4a5aec2e-ccc4-4f32-9bc7-1c11a80d6894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39939
86141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3993986141
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.2928385749
Short name T837
Test name
Test status
Simulation time 230610857 ps
CPU time 0.95 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:53 PM PDT 24
Peak memory 206132 kb
Host smart-29e48b6a-792f-4bba-aa44-b69f46083e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29283
85749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.2928385749
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2278728452
Short name T46
Test name
Test status
Simulation time 23342231681 ps
CPU time 23.38 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:53:15 PM PDT 24
Peak memory 206128 kb
Host smart-d879f251-8a39-4c44-84b9-b0612ead4ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22787
28452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2278728452
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3026436814
Short name T2092
Test name
Test status
Simulation time 3358008251 ps
CPU time 4.34 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 206208 kb
Host smart-988612f5-d5b6-4c82-921d-0e1a62412e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30264
36814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3026436814
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.1347579344
Short name T1337
Test name
Test status
Simulation time 5212197394 ps
CPU time 46.65 seconds
Started Jul 03 04:52:59 PM PDT 24
Finished Jul 03 04:53:47 PM PDT 24
Peak memory 206428 kb
Host smart-dbb9c31d-32e4-4294-97d0-59a4d0fbe67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13475
79344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.1347579344
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.755518552
Short name T1976
Test name
Test status
Simulation time 3657466760 ps
CPU time 96.42 seconds
Started Jul 03 04:52:54 PM PDT 24
Finished Jul 03 04:54:32 PM PDT 24
Peak memory 206248 kb
Host smart-441bb790-8086-4e8d-8f4d-2d1900069f5f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=755518552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.755518552
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1959573791
Short name T2085
Test name
Test status
Simulation time 290531553 ps
CPU time 0.99 seconds
Started Jul 03 04:52:49 PM PDT 24
Finished Jul 03 04:52:50 PM PDT 24
Peak memory 206112 kb
Host smart-aefda52b-741d-426e-b1f1-9bd4f483400e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1959573791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1959573791
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2606231727
Short name T1965
Test name
Test status
Simulation time 222025744 ps
CPU time 0.88 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:52:58 PM PDT 24
Peak memory 206044 kb
Host smart-7f37198e-61a6-4da6-ba6d-2276c17d33d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26062
31727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2606231727
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.726326457
Short name T1312
Test name
Test status
Simulation time 6652225482 ps
CPU time 46.41 seconds
Started Jul 03 04:52:48 PM PDT 24
Finished Jul 03 04:53:35 PM PDT 24
Peak memory 206392 kb
Host smart-3b19a7c6-63a2-4868-9648-2b5fc6abccf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72632
6457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.726326457
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.3251829434
Short name T1028
Test name
Test status
Simulation time 4449593983 ps
CPU time 120.49 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:54:54 PM PDT 24
Peak memory 206380 kb
Host smart-9fae76b7-721c-4f01-8648-a2872ed8905e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3251829434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3251829434
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.3289970897
Short name T1658
Test name
Test status
Simulation time 150318224 ps
CPU time 0.78 seconds
Started Jul 03 04:53:07 PM PDT 24
Finished Jul 03 04:53:08 PM PDT 24
Peak memory 206128 kb
Host smart-74ac009e-f3af-4f05-a7b8-a5aa14b30ee1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3289970897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.3289970897
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2536581479
Short name T2553
Test name
Test status
Simulation time 164116920 ps
CPU time 0.78 seconds
Started Jul 03 04:52:47 PM PDT 24
Finished Jul 03 04:52:48 PM PDT 24
Peak memory 206100 kb
Host smart-8d603ab4-b1ee-4f2e-8f38-6dbc214caa67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25365
81479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2536581479
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.4229959870
Short name T2434
Test name
Test status
Simulation time 153043330 ps
CPU time 0.8 seconds
Started Jul 03 04:53:02 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 205972 kb
Host smart-28777276-0752-4fd9-a722-ee9506112330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42299
59870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.4229959870
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.317729925
Short name T527
Test name
Test status
Simulation time 154187873 ps
CPU time 0.8 seconds
Started Jul 03 04:53:00 PM PDT 24
Finished Jul 03 04:53:02 PM PDT 24
Peak memory 206076 kb
Host smart-ee77e223-e52a-43dc-9743-def32dbd0bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31772
9925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.317729925
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1075467872
Short name T1867
Test name
Test status
Simulation time 167891474 ps
CPU time 0.89 seconds
Started Jul 03 04:52:54 PM PDT 24
Finished Jul 03 04:52:57 PM PDT 24
Peak memory 206136 kb
Host smart-3f46ba2b-d455-48b9-aba5-f616c9479622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10754
67872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1075467872
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2087943441
Short name T159
Test name
Test status
Simulation time 189538371 ps
CPU time 0.86 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 206112 kb
Host smart-314798c2-ebfc-4e37-8b13-bf38d15b4f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20879
43441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2087943441
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.3627470690
Short name T1979
Test name
Test status
Simulation time 215144350 ps
CPU time 0.91 seconds
Started Jul 03 04:52:54 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206100 kb
Host smart-708b85e8-b498-4ff5-a096-a4563bb0a253
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3627470690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3627470690
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1553844416
Short name T892
Test name
Test status
Simulation time 148032402 ps
CPU time 0.79 seconds
Started Jul 03 04:52:59 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206036 kb
Host smart-7a5d3c4d-97ac-4427-becc-962ce3b91817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15538
44416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1553844416
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2290278995
Short name T1331
Test name
Test status
Simulation time 106999423 ps
CPU time 0.73 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:52:57 PM PDT 24
Peak memory 206084 kb
Host smart-cd0171cc-b80b-4c37-878f-4a13a1b2ba18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22902
78995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2290278995
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1139019695
Short name T2443
Test name
Test status
Simulation time 21631775320 ps
CPU time 50.83 seconds
Started Jul 03 04:52:56 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 214552 kb
Host smart-317fc08e-e4d7-4d92-86c0-d915771ddb39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11390
19695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1139019695
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.198417644
Short name T1573
Test name
Test status
Simulation time 203443137 ps
CPU time 0.85 seconds
Started Jul 03 04:53:08 PM PDT 24
Finished Jul 03 04:53:09 PM PDT 24
Peak memory 206072 kb
Host smart-96476689-a3a3-4692-9e50-746ca954cc84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19841
7644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.198417644
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2365259710
Short name T2615
Test name
Test status
Simulation time 221088048 ps
CPU time 0.86 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206112 kb
Host smart-4bf79787-f4db-4d06-97e9-e8e4a36ef342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23652
59710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2365259710
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.29925809
Short name T1823
Test name
Test status
Simulation time 224592540 ps
CPU time 0.86 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206092 kb
Host smart-c8ac7726-af1c-4aad-bb32-7ce1078498c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29925
809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.29925809
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3887676460
Short name T2293
Test name
Test status
Simulation time 173659337 ps
CPU time 0.86 seconds
Started Jul 03 04:52:54 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206092 kb
Host smart-20b45882-470c-4a7c-bb97-e42f30f0532b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38876
76460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3887676460
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.724300405
Short name T443
Test name
Test status
Simulation time 141331853 ps
CPU time 0.76 seconds
Started Jul 03 04:52:54 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206092 kb
Host smart-e332e81d-b2b2-4352-b66f-e78b17717796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72430
0405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.724300405
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1097765026
Short name T1688
Test name
Test status
Simulation time 156591548 ps
CPU time 0.78 seconds
Started Jul 03 04:52:54 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206100 kb
Host smart-50b19e54-887b-4584-a5eb-dc9ef1fcc2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10977
65026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1097765026
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1275177637
Short name T2124
Test name
Test status
Simulation time 209837566 ps
CPU time 0.87 seconds
Started Jul 03 04:53:04 PM PDT 24
Finished Jul 03 04:53:05 PM PDT 24
Peak memory 206128 kb
Host smart-b127a853-3051-4484-b6a1-24662fe576e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12751
77637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1275177637
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1243717755
Short name T2189
Test name
Test status
Simulation time 213885598 ps
CPU time 0.91 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:52:58 PM PDT 24
Peak memory 206132 kb
Host smart-ee2b0463-a238-4cd3-9486-14899c54ea5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12437
17755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1243717755
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.1558239340
Short name T1129
Test name
Test status
Simulation time 4933723396 ps
CPU time 34.95 seconds
Started Jul 03 04:53:09 PM PDT 24
Finished Jul 03 04:53:44 PM PDT 24
Peak memory 206432 kb
Host smart-3a181b99-d23c-4f4e-a73a-cb80decaebb8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1558239340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.1558239340
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2611381817
Short name T952
Test name
Test status
Simulation time 204797983 ps
CPU time 0.83 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 205944 kb
Host smart-950aeaa9-14f5-4d7b-b48f-79e82f19bad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26113
81817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2611381817
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.722662258
Short name T1625
Test name
Test status
Simulation time 207932536 ps
CPU time 0.87 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:55 PM PDT 24
Peak memory 206116 kb
Host smart-64c5c838-2cd6-4a27-9dd9-f0ec106fcd99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72266
2258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.722662258
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.2779335005
Short name T1804
Test name
Test status
Simulation time 915653917 ps
CPU time 2.09 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:53:02 PM PDT 24
Peak memory 206340 kb
Host smart-2775eff9-eb82-47d2-a46e-0a3506fb1868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27793
35005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.2779335005
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3433231398
Short name T255
Test name
Test status
Simulation time 5501829579 ps
CPU time 146.75 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:55:25 PM PDT 24
Peak memory 206432 kb
Host smart-c2d01235-82a9-4337-b86e-d4c83efbe989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34332
31398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3433231398
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.4240946849
Short name T1379
Test name
Test status
Simulation time 107948336 ps
CPU time 0.72 seconds
Started Jul 03 04:53:11 PM PDT 24
Finished Jul 03 04:53:12 PM PDT 24
Peak memory 206188 kb
Host smart-22ba185a-ce45-4e44-96c7-4051fd510258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4240946849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.4240946849
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1152863239
Short name T226
Test name
Test status
Simulation time 13409375980 ps
CPU time 12.44 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:53:11 PM PDT 24
Peak memory 206372 kb
Host smart-cc97b3de-beff-489c-8490-11468704a74c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1152863239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1152863239
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1465147142
Short name T14
Test name
Test status
Simulation time 23331991636 ps
CPU time 22.39 seconds
Started Jul 03 04:52:56 PM PDT 24
Finished Jul 03 04:53:19 PM PDT 24
Peak memory 206388 kb
Host smart-29942f66-c624-4481-a0d6-477440f16695
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1465147142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1465147142
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2086888168
Short name T2230
Test name
Test status
Simulation time 190642621 ps
CPU time 0.84 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206128 kb
Host smart-d1b65784-bfe1-4d8e-a943-9b742cab9269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20868
88168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2086888168
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2054875857
Short name T2341
Test name
Test status
Simulation time 149253168 ps
CPU time 0.76 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:52:57 PM PDT 24
Peak memory 206132 kb
Host smart-2a5802e8-f954-4bdc-b144-9de0f5bb9145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20548
75857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2054875857
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3197278378
Short name T20
Test name
Test status
Simulation time 314078354 ps
CPU time 1.28 seconds
Started Jul 03 04:52:59 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206112 kb
Host smart-d3fc633b-6ee6-4e2d-a66c-6a2d89d473d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31972
78378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3197278378
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3109137179
Short name T185
Test name
Test status
Simulation time 1452686531 ps
CPU time 3.13 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206356 kb
Host smart-7af4a66e-ec45-439b-afc2-3d78c7336fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31091
37179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3109137179
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1084324900
Short name T107
Test name
Test status
Simulation time 6731174421 ps
CPU time 13.11 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:53:12 PM PDT 24
Peak memory 206424 kb
Host smart-81910a6e-5772-43c5-9f1d-887e0c047581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843
24900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1084324900
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2111320267
Short name T1537
Test name
Test status
Simulation time 406060966 ps
CPU time 1.3 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:55 PM PDT 24
Peak memory 206116 kb
Host smart-479d3884-f68b-4c96-a8a6-8f1c084890d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21113
20267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2111320267
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2804323092
Short name T736
Test name
Test status
Simulation time 162157650 ps
CPU time 0.85 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:55 PM PDT 24
Peak memory 206100 kb
Host smart-ca4c32e2-900e-421d-9e88-9bbdf7817b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28043
23092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2804323092
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.478170075
Short name T1072
Test name
Test status
Simulation time 45720550 ps
CPU time 0.65 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:52:58 PM PDT 24
Peak memory 206096 kb
Host smart-d4966f28-1841-4cf0-853d-f0d7d174356c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47817
0075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.478170075
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2246503985
Short name T623
Test name
Test status
Simulation time 989729321 ps
CPU time 2.21 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:04 PM PDT 24
Peak memory 206304 kb
Host smart-811873ad-b441-4f21-a8b9-5ef54f975d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22465
03985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2246503985
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1871501378
Short name T206
Test name
Test status
Simulation time 218004495 ps
CPU time 1.29 seconds
Started Jul 03 04:52:59 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206372 kb
Host smart-d25e6bf3-7fa1-479e-a0d2-05714599ba35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18715
01378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1871501378
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1117661204
Short name T2526
Test name
Test status
Simulation time 183599132 ps
CPU time 0.84 seconds
Started Jul 03 04:52:59 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206112 kb
Host smart-08f85527-3d33-494c-85ee-452826ef3d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
61204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1117661204
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3525682386
Short name T1436
Test name
Test status
Simulation time 153940378 ps
CPU time 0.76 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206124 kb
Host smart-96c1085e-f10f-4edc-8ea5-889bf1d1d6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35256
82386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3525682386
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.432419273
Short name T1939
Test name
Test status
Simulation time 260417440 ps
CPU time 0.95 seconds
Started Jul 03 04:52:59 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206132 kb
Host smart-35df0edd-268a-443b-b913-a79816c97c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43241
9273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.432419273
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1774051390
Short name T1251
Test name
Test status
Simulation time 9091962714 ps
CPU time 84.01 seconds
Started Jul 03 04:52:59 PM PDT 24
Finished Jul 03 04:54:24 PM PDT 24
Peak memory 206448 kb
Host smart-821ac606-3735-4c0d-bbcf-efa6916340fc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1774051390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1774051390
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1224739771
Short name T1010
Test name
Test status
Simulation time 197411137 ps
CPU time 0.85 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:06 PM PDT 24
Peak memory 206148 kb
Host smart-45fd71db-795c-4840-b763-c798994f29bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12247
39771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1224739771
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.2486672514
Short name T1338
Test name
Test status
Simulation time 23283859639 ps
CPU time 21.54 seconds
Started Jul 03 04:53:02 PM PDT 24
Finished Jul 03 04:53:24 PM PDT 24
Peak memory 206168 kb
Host smart-26026b7f-732d-4749-aafb-ff11277549a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24866
72514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.2486672514
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2506043746
Short name T916
Test name
Test status
Simulation time 3319081476 ps
CPU time 4.04 seconds
Started Jul 03 04:53:00 PM PDT 24
Finished Jul 03 04:53:05 PM PDT 24
Peak memory 206188 kb
Host smart-8f8ee688-e554-483b-8b03-7a8759dbf2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25060
43746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2506043746
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3789960434
Short name T1098
Test name
Test status
Simulation time 5709071423 ps
CPU time 153.43 seconds
Started Jul 03 04:53:04 PM PDT 24
Finished Jul 03 04:55:38 PM PDT 24
Peak memory 206412 kb
Host smart-0bbb7c0c-0c5b-40ff-8eb4-a70bbca2e644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37899
60434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3789960434
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3740692181
Short name T2167
Test name
Test status
Simulation time 4242806090 ps
CPU time 30.28 seconds
Started Jul 03 04:53:03 PM PDT 24
Finished Jul 03 04:53:34 PM PDT 24
Peak memory 206408 kb
Host smart-335e37eb-7f68-45df-af0f-a7605f876f94
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3740692181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3740692181
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.295734247
Short name T2065
Test name
Test status
Simulation time 235953425 ps
CPU time 0.99 seconds
Started Jul 03 04:52:59 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206128 kb
Host smart-1e2e2055-b770-439b-bd78-9fb8e290e9b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=295734247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.295734247
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2045029333
Short name T268
Test name
Test status
Simulation time 206543206 ps
CPU time 0.89 seconds
Started Jul 03 04:53:07 PM PDT 24
Finished Jul 03 04:53:08 PM PDT 24
Peak memory 206096 kb
Host smart-5528f188-6832-4237-b387-2fe0c0380cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20450
29333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2045029333
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.165659713
Short name T681
Test name
Test status
Simulation time 6208271440 ps
CPU time 58.31 seconds
Started Jul 03 04:53:03 PM PDT 24
Finished Jul 03 04:54:02 PM PDT 24
Peak memory 206380 kb
Host smart-4ed61423-c94a-47d3-b45c-0d279fb29701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16565
9713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.165659713
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.1167507526
Short name T2462
Test name
Test status
Simulation time 6054705149 ps
CPU time 57.2 seconds
Started Jul 03 04:53:07 PM PDT 24
Finished Jul 03 04:54:04 PM PDT 24
Peak memory 206320 kb
Host smart-78a0f9d5-e1cc-4a84-b7c2-5222191f65f5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1167507526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.1167507526
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2410280235
Short name T675
Test name
Test status
Simulation time 182527672 ps
CPU time 0.84 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206388 kb
Host smart-0a724bcf-147b-4f65-b520-8f9121bbc287
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2410280235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2410280235
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1166079520
Short name T1094
Test name
Test status
Simulation time 150857628 ps
CPU time 0.79 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:06 PM PDT 24
Peak memory 206124 kb
Host smart-1c040499-ba1a-455f-b208-64b968613a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11660
79520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1166079520
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3010178870
Short name T708
Test name
Test status
Simulation time 181025501 ps
CPU time 0.83 seconds
Started Jul 03 04:53:07 PM PDT 24
Finished Jul 03 04:53:09 PM PDT 24
Peak memory 206068 kb
Host smart-5bb225b7-7d03-413f-9f1f-91f3db9cf876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30101
78870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3010178870
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3246409189
Short name T2134
Test name
Test status
Simulation time 183092509 ps
CPU time 0.81 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:07 PM PDT 24
Peak memory 206128 kb
Host smart-90844fa6-f4d2-4125-8007-52f93beef2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32464
09189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3246409189
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1443558440
Short name T635
Test name
Test status
Simulation time 196379902 ps
CPU time 0.81 seconds
Started Jul 03 04:53:03 PM PDT 24
Finished Jul 03 04:53:04 PM PDT 24
Peak memory 206004 kb
Host smart-9c2f0c81-0d66-44e1-aa82-84d6526c2fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14435
58440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1443558440
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1511859100
Short name T2094
Test name
Test status
Simulation time 156250416 ps
CPU time 0.78 seconds
Started Jul 03 04:53:11 PM PDT 24
Finished Jul 03 04:53:12 PM PDT 24
Peak memory 206084 kb
Host smart-0d86c6d5-22b5-400e-862e-a13aeeb1c786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15118
59100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1511859100
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2849790502
Short name T1948
Test name
Test status
Simulation time 235387856 ps
CPU time 0.96 seconds
Started Jul 03 04:53:02 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 206132 kb
Host smart-7da40d53-6940-4c76-9a8c-99f86cba7110
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2849790502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2849790502
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.958516921
Short name T888
Test name
Test status
Simulation time 140986595 ps
CPU time 0.75 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:02 PM PDT 24
Peak memory 206092 kb
Host smart-8b5f8a2b-5062-4329-9ed0-9160c90ffdfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95851
6921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.958516921
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3014702504
Short name T1640
Test name
Test status
Simulation time 19304152113 ps
CPU time 44.05 seconds
Started Jul 03 04:53:06 PM PDT 24
Finished Jul 03 04:53:51 PM PDT 24
Peak memory 206420 kb
Host smart-a0e29007-dda8-4279-a1b9-cc025403fced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30147
02504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3014702504
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3052154635
Short name T1021
Test name
Test status
Simulation time 190330439 ps
CPU time 0.86 seconds
Started Jul 03 04:53:06 PM PDT 24
Finished Jul 03 04:53:08 PM PDT 24
Peak memory 206092 kb
Host smart-515fde2b-6d2b-41d5-b566-d193739b3448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30521
54635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3052154635
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3618345159
Short name T2160
Test name
Test status
Simulation time 287692876 ps
CPU time 0.94 seconds
Started Jul 03 04:53:02 PM PDT 24
Finished Jul 03 04:53:04 PM PDT 24
Peak memory 206104 kb
Host smart-2bc5d37e-e30a-4819-977f-9a4630a520d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36183
45159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3618345159
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.22494289
Short name T770
Test name
Test status
Simulation time 207963148 ps
CPU time 0.87 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:02 PM PDT 24
Peak memory 206048 kb
Host smart-b5f1405b-eb47-4408-aafd-533fd7315c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22494
289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.22494289
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.3243249881
Short name T1884
Test name
Test status
Simulation time 143999109 ps
CPU time 0.77 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:07 PM PDT 24
Peak memory 206088 kb
Host smart-ac58b34e-e940-4f3a-9b62-73b19053b607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32432
49881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.3243249881
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.903331167
Short name T1392
Test name
Test status
Simulation time 183546900 ps
CPU time 0.85 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 206132 kb
Host smart-61442cc0-0801-44b9-944d-405eea046bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90333
1167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.903331167
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1029125339
Short name T1618
Test name
Test status
Simulation time 158985369 ps
CPU time 0.76 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 206128 kb
Host smart-22219063-d0ec-4cf4-8148-d2c8e05d8b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10291
25339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1029125339
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1467161104
Short name T877
Test name
Test status
Simulation time 156102980 ps
CPU time 0.9 seconds
Started Jul 03 04:53:03 PM PDT 24
Finished Jul 03 04:53:04 PM PDT 24
Peak memory 206096 kb
Host smart-b580f89e-a489-435e-8b16-2dcd0dcca6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14671
61104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1467161104
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2085378213
Short name T1708
Test name
Test status
Simulation time 198730292 ps
CPU time 0.86 seconds
Started Jul 03 04:53:04 PM PDT 24
Finished Jul 03 04:53:05 PM PDT 24
Peak memory 206088 kb
Host smart-842a7bfc-6cfe-4efb-ae3a-36420d4afbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20853
78213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2085378213
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.1581630628
Short name T981
Test name
Test status
Simulation time 3899855612 ps
CPU time 104.87 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:54:50 PM PDT 24
Peak memory 206448 kb
Host smart-73ee27ec-38aa-406a-b44d-144a2d6d0c3b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1581630628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.1581630628
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.422952986
Short name T1761
Test name
Test status
Simulation time 204393703 ps
CPU time 0.92 seconds
Started Jul 03 04:53:07 PM PDT 24
Finished Jul 03 04:53:09 PM PDT 24
Peak memory 206068 kb
Host smart-3d260c2b-d262-4166-882f-d2779b5c91ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42295
2986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.422952986
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.855381046
Short name T1785
Test name
Test status
Simulation time 204088684 ps
CPU time 0.87 seconds
Started Jul 03 04:53:02 PM PDT 24
Finished Jul 03 04:53:04 PM PDT 24
Peak memory 206136 kb
Host smart-8fb28cbe-b0f7-4508-80fe-6ff02a18efbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85538
1046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.855381046
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.274939596
Short name T2215
Test name
Test status
Simulation time 1259466005 ps
CPU time 2.72 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:04 PM PDT 24
Peak memory 206336 kb
Host smart-f7885514-63ee-45b3-b0ae-f4e8fa57489b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27493
9596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.274939596
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3729989136
Short name T405
Test name
Test status
Simulation time 4866488583 ps
CPU time 47 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:53 PM PDT 24
Peak memory 206336 kb
Host smart-e527b052-49ea-4c88-abdc-30a116a238bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37299
89136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3729989136
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.89905418
Short name T2147
Test name
Test status
Simulation time 3788033723 ps
CPU time 4.33 seconds
Started Jul 03 04:53:08 PM PDT 24
Finished Jul 03 04:53:13 PM PDT 24
Peak memory 206460 kb
Host smart-d23d78ca-54ea-42bd-9ff5-a1e1e0fcb3c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=89905418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.89905418
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3111554854
Short name T1687
Test name
Test status
Simulation time 13308792670 ps
CPU time 12.66 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:19 PM PDT 24
Peak memory 206180 kb
Host smart-0f1601c3-ebf6-4db2-88bf-4e51bb46a03c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3111554854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3111554854
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1869746197
Short name T1083
Test name
Test status
Simulation time 23313815819 ps
CPU time 26.88 seconds
Started Jul 03 04:53:03 PM PDT 24
Finished Jul 03 04:53:31 PM PDT 24
Peak memory 206152 kb
Host smart-6345fc9f-874b-4118-9d7d-601c22dd352e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1869746197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.1869746197
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2206065833
Short name T2436
Test name
Test status
Simulation time 177963152 ps
CPU time 0.81 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:02 PM PDT 24
Peak memory 206132 kb
Host smart-c9c9be96-268e-481d-a5d5-9947d8c98571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22060
65833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2206065833
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.2443820387
Short name T1756
Test name
Test status
Simulation time 210628564 ps
CPU time 0.88 seconds
Started Jul 03 04:53:11 PM PDT 24
Finished Jul 03 04:53:12 PM PDT 24
Peak memory 206132 kb
Host smart-1ab2f185-4ab7-439f-83c4-5b517ece58ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24438
20387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.2443820387
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2901836593
Short name T2007
Test name
Test status
Simulation time 219478131 ps
CPU time 1 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:02 PM PDT 24
Peak memory 206060 kb
Host smart-7f5c0f35-ddae-4e0d-ba50-e88f00db9ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29018
36593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2901836593
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2706982172
Short name T1491
Test name
Test status
Simulation time 302244406 ps
CPU time 0.93 seconds
Started Jul 03 04:53:13 PM PDT 24
Finished Jul 03 04:53:14 PM PDT 24
Peak memory 206068 kb
Host smart-7de03756-096d-409c-8211-92b7430b224f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27069
82172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2706982172
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.2305015105
Short name T2166
Test name
Test status
Simulation time 8430336517 ps
CPU time 14.93 seconds
Started Jul 03 04:53:07 PM PDT 24
Finished Jul 03 04:53:22 PM PDT 24
Peak memory 206360 kb
Host smart-3dfa3c0b-35b4-44de-b8b8-7f2a77386fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23050
15105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2305015105
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.1040265949
Short name T908
Test name
Test status
Simulation time 481279223 ps
CPU time 1.35 seconds
Started Jul 03 04:53:11 PM PDT 24
Finished Jul 03 04:53:13 PM PDT 24
Peak memory 206108 kb
Host smart-cdcf50c8-81e3-46f6-94c3-3e71698b58ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10402
65949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.1040265949
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2258241873
Short name T2583
Test name
Test status
Simulation time 162393727 ps
CPU time 0.77 seconds
Started Jul 03 04:53:08 PM PDT 24
Finished Jul 03 04:53:09 PM PDT 24
Peak memory 206080 kb
Host smart-8dc13fcb-cf57-4bdf-98d6-33b4f8602851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22582
41873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2258241873
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3172354251
Short name T2612
Test name
Test status
Simulation time 46785523 ps
CPU time 0.68 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:02 PM PDT 24
Peak memory 206084 kb
Host smart-601b2a51-96f2-4c8f-a182-ac624d0498ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31723
54251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3172354251
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2980845552
Short name T1446
Test name
Test status
Simulation time 874488127 ps
CPU time 2.07 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:07 PM PDT 24
Peak memory 206256 kb
Host smart-d597e06f-a5b6-4942-b18d-1704f8e0dae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29808
45552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2980845552
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1176033772
Short name T1870
Test name
Test status
Simulation time 219466155 ps
CPU time 2.08 seconds
Started Jul 03 04:53:15 PM PDT 24
Finished Jul 03 04:53:17 PM PDT 24
Peak memory 206316 kb
Host smart-bc73823e-e007-462a-8904-56122040093b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11760
33772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1176033772
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3988047956
Short name T1920
Test name
Test status
Simulation time 205932332 ps
CPU time 0.87 seconds
Started Jul 03 04:53:09 PM PDT 24
Finished Jul 03 04:53:10 PM PDT 24
Peak memory 206084 kb
Host smart-18121a5e-83ea-4817-a411-2ccd75812c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39880
47956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3988047956
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2420269294
Short name T653
Test name
Test status
Simulation time 175033081 ps
CPU time 0.82 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:53:18 PM PDT 24
Peak memory 206124 kb
Host smart-e38358ef-671c-40f3-868d-cf8e91a68217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24202
69294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2420269294
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.427172173
Short name T833
Test name
Test status
Simulation time 223203479 ps
CPU time 0.88 seconds
Started Jul 03 04:53:00 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206088 kb
Host smart-8ad36323-5317-40ee-b0c1-612edee52437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42717
2173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.427172173
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.1123845535
Short name T245
Test name
Test status
Simulation time 7040686365 ps
CPU time 202.11 seconds
Started Jul 03 04:53:07 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206400 kb
Host smart-3011124f-4154-4be7-8b0f-cc7722c577d3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1123845535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1123845535
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2015536385
Short name T1617
Test name
Test status
Simulation time 194548396 ps
CPU time 0.84 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:06 PM PDT 24
Peak memory 206104 kb
Host smart-fbf50555-8528-4af8-8af3-21e1f6b14bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20155
36385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2015536385
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1774605046
Short name T976
Test name
Test status
Simulation time 23364654368 ps
CPU time 30.13 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:32 PM PDT 24
Peak memory 206196 kb
Host smart-a48b9f1b-cc1c-4d90-95fd-32427c5ea699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17746
05046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1774605046
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3978804652
Short name T1892
Test name
Test status
Simulation time 3291126124 ps
CPU time 3.77 seconds
Started Jul 03 04:53:07 PM PDT 24
Finished Jul 03 04:53:11 PM PDT 24
Peak memory 206144 kb
Host smart-364aa99c-3dea-4563-aedd-511276add18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39788
04652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3978804652
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.4222766757
Short name T2469
Test name
Test status
Simulation time 9539196001 ps
CPU time 87.03 seconds
Started Jul 03 04:53:12 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206444 kb
Host smart-64534613-ee8c-485d-985d-0cc1e24a03cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42227
66757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.4222766757
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2137741070
Short name T788
Test name
Test status
Simulation time 3055939676 ps
CPU time 22.03 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206408 kb
Host smart-d3b42b5e-51c9-4359-ab0b-0703fce883e9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2137741070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2137741070
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.520494959
Short name T794
Test name
Test status
Simulation time 260600976 ps
CPU time 0.9 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:07 PM PDT 24
Peak memory 206132 kb
Host smart-500b6d92-5fb3-43fa-ac6d-8a6252a1fe34
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=520494959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.520494959
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.439550247
Short name T890
Test name
Test status
Simulation time 196932761 ps
CPU time 0.84 seconds
Started Jul 03 04:53:02 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 205980 kb
Host smart-c2b54a42-df38-4ed0-a283-fe141fcb28e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43955
0247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.439550247
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1714010652
Short name T2115
Test name
Test status
Simulation time 6289316648 ps
CPU time 163.55 seconds
Started Jul 03 04:53:06 PM PDT 24
Finished Jul 03 04:55:50 PM PDT 24
Peak memory 206236 kb
Host smart-7e0b15ee-1f90-4d6e-81b0-d48fd9fa030a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17140
10652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1714010652
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.942883468
Short name T669
Test name
Test status
Simulation time 5468274961 ps
CPU time 51.96 seconds
Started Jul 03 04:53:08 PM PDT 24
Finished Jul 03 04:54:01 PM PDT 24
Peak memory 206264 kb
Host smart-56e58242-8466-4fd9-9ae0-711f1caf2f34
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=942883468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.942883468
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.435161237
Short name T1401
Test name
Test status
Simulation time 176028540 ps
CPU time 0.85 seconds
Started Jul 03 04:53:03 PM PDT 24
Finished Jul 03 04:53:05 PM PDT 24
Peak memory 206092 kb
Host smart-74cea9bc-f698-43b0-8288-da655311d75d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=435161237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.435161237
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3987707815
Short name T1163
Test name
Test status
Simulation time 148995027 ps
CPU time 0.77 seconds
Started Jul 03 04:53:09 PM PDT 24
Finished Jul 03 04:53:10 PM PDT 24
Peak memory 206096 kb
Host smart-f318d396-2da1-4167-993e-b8bd52730167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39877
07815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3987707815
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.487279716
Short name T705
Test name
Test status
Simulation time 163445632 ps
CPU time 0.82 seconds
Started Jul 03 04:53:03 PM PDT 24
Finished Jul 03 04:53:05 PM PDT 24
Peak memory 206076 kb
Host smart-45ec8cfe-2f50-4c06-b8e4-87de83c4f1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48727
9716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.487279716
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3555913478
Short name T1431
Test name
Test status
Simulation time 170717704 ps
CPU time 0.87 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:53:19 PM PDT 24
Peak memory 206132 kb
Host smart-bbb30694-8f2a-49f4-aa76-40aceb5ec9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35559
13478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3555913478
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.905077247
Short name T2691
Test name
Test status
Simulation time 169389440 ps
CPU time 0.79 seconds
Started Jul 03 04:53:16 PM PDT 24
Finished Jul 03 04:53:17 PM PDT 24
Peak memory 206128 kb
Host smart-5c0c1516-ad11-451d-9b3b-07cd0b50f235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90507
7247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.905077247
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.593820740
Short name T1399
Test name
Test status
Simulation time 150892839 ps
CPU time 0.76 seconds
Started Jul 03 04:53:15 PM PDT 24
Finished Jul 03 04:53:16 PM PDT 24
Peak memory 206104 kb
Host smart-1bbf1e73-9241-49c1-9e8e-a5fb005292e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59382
0740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.593820740
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.490379658
Short name T2272
Test name
Test status
Simulation time 248467038 ps
CPU time 0.95 seconds
Started Jul 03 04:53:16 PM PDT 24
Finished Jul 03 04:53:17 PM PDT 24
Peak memory 206132 kb
Host smart-4edc520a-fbbd-4d1b-9a24-346590952900
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=490379658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.490379658
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2805067741
Short name T24
Test name
Test status
Simulation time 46449791 ps
CPU time 0.66 seconds
Started Jul 03 04:53:03 PM PDT 24
Finished Jul 03 04:53:04 PM PDT 24
Peak memory 206128 kb
Host smart-625487ab-a308-4875-97bc-106e666b9de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28050
67741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2805067741
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1181161644
Short name T270
Test name
Test status
Simulation time 12752307091 ps
CPU time 26.26 seconds
Started Jul 03 04:53:12 PM PDT 24
Finished Jul 03 04:53:39 PM PDT 24
Peak memory 206400 kb
Host smart-40740af7-99cd-4d46-a080-7c1c69bd0168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11811
61644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1181161644
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1664660400
Short name T907
Test name
Test status
Simulation time 201869800 ps
CPU time 0.88 seconds
Started Jul 03 04:53:20 PM PDT 24
Finished Jul 03 04:53:21 PM PDT 24
Peak memory 206136 kb
Host smart-08d7d340-8f03-477d-8064-71fa370c7a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16646
60400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1664660400
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1665495507
Short name T1373
Test name
Test status
Simulation time 244442238 ps
CPU time 0.92 seconds
Started Jul 03 04:53:16 PM PDT 24
Finished Jul 03 04:53:18 PM PDT 24
Peak memory 206128 kb
Host smart-527c7873-986d-40ac-9ab8-1db24c473e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16654
95507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1665495507
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.318688764
Short name T1488
Test name
Test status
Simulation time 208090738 ps
CPU time 0.82 seconds
Started Jul 03 04:53:02 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 205976 kb
Host smart-584eae6f-0868-4821-a8e9-df19eb87759b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31868
8764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.318688764
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.2130072557
Short name T2376
Test name
Test status
Simulation time 197581155 ps
CPU time 0.83 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:06 PM PDT 24
Peak memory 206104 kb
Host smart-a482a40b-3046-40cf-b44b-6fdde40bb0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21300
72557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.2130072557
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1507806202
Short name T1043
Test name
Test status
Simulation time 158222083 ps
CPU time 0.77 seconds
Started Jul 03 04:53:02 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 206116 kb
Host smart-2f3ec6d2-2ca7-4468-a835-5071cff9b688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15078
06202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1507806202
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3649364338
Short name T1711
Test name
Test status
Simulation time 153185924 ps
CPU time 0.75 seconds
Started Jul 03 04:53:12 PM PDT 24
Finished Jul 03 04:53:14 PM PDT 24
Peak memory 206124 kb
Host smart-c2addade-9b61-4e20-9222-e9bfd47c44fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36493
64338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3649364338
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3849649391
Short name T2192
Test name
Test status
Simulation time 148176833 ps
CPU time 0.76 seconds
Started Jul 03 04:53:06 PM PDT 24
Finished Jul 03 04:53:07 PM PDT 24
Peak memory 206004 kb
Host smart-a44bddf6-f70e-41d2-bf55-dceb234458e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38496
49391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3849649391
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2986713092
Short name T2274
Test name
Test status
Simulation time 240634785 ps
CPU time 1.02 seconds
Started Jul 03 04:53:02 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 206040 kb
Host smart-cce8204c-3794-4f6e-9f55-34b67daa2c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29867
13092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2986713092
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2249791866
Short name T2523
Test name
Test status
Simulation time 5776119527 ps
CPU time 162.52 seconds
Started Jul 03 04:53:16 PM PDT 24
Finished Jul 03 04:55:59 PM PDT 24
Peak memory 206480 kb
Host smart-3b8c7cd3-ee27-4638-a920-b329a7c51e71
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2249791866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2249791866
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1589299061
Short name T1424
Test name
Test status
Simulation time 180093040 ps
CPU time 0.82 seconds
Started Jul 03 04:53:21 PM PDT 24
Finished Jul 03 04:53:23 PM PDT 24
Peak memory 206136 kb
Host smart-6b8e1038-245d-4977-af0d-04b982adf19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15892
99061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1589299061
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1926200589
Short name T2193
Test name
Test status
Simulation time 223973354 ps
CPU time 0.87 seconds
Started Jul 03 04:53:16 PM PDT 24
Finished Jul 03 04:53:18 PM PDT 24
Peak memory 206124 kb
Host smart-08904619-e842-4e7c-83fb-4276fcb32a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19262
00589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1926200589
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.306833402
Short name T2175
Test name
Test status
Simulation time 1238423678 ps
CPU time 2.57 seconds
Started Jul 03 04:53:06 PM PDT 24
Finished Jul 03 04:53:09 PM PDT 24
Peak memory 206240 kb
Host smart-620c6009-3b74-41f4-9b13-4a31ff449e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30683
3402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.306833402
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3272671659
Short name T1201
Test name
Test status
Simulation time 3832106630 ps
CPU time 28.28 seconds
Started Jul 03 04:53:07 PM PDT 24
Finished Jul 03 04:53:35 PM PDT 24
Peak memory 206388 kb
Host smart-0ba6bfdd-e78d-444f-be3a-45663477ee92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32726
71659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3272671659
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.4251161553
Short name T1343
Test name
Test status
Simulation time 34033486 ps
CPU time 0.68 seconds
Started Jul 03 04:53:19 PM PDT 24
Finished Jul 03 04:53:20 PM PDT 24
Peak memory 206196 kb
Host smart-6d50af9f-5f29-4ffe-9206-1a55b929d085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4251161553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.4251161553
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3928673532
Short name T839
Test name
Test status
Simulation time 3999216872 ps
CPU time 4.91 seconds
Started Jul 03 04:53:05 PM PDT 24
Finished Jul 03 04:53:10 PM PDT 24
Peak memory 206428 kb
Host smart-4b8c6e08-4547-4cec-87ac-7d1dc9583039
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3928673532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.3928673532
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3324210943
Short name T520
Test name
Test status
Simulation time 13385668679 ps
CPU time 14.71 seconds
Started Jul 03 04:53:20 PM PDT 24
Finished Jul 03 04:53:35 PM PDT 24
Peak memory 206176 kb
Host smart-b67e092d-e075-4f73-8b64-6fa2ace88207
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3324210943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3324210943
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.64877172
Short name T1090
Test name
Test status
Simulation time 23413042412 ps
CPU time 24.97 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:53:43 PM PDT 24
Peak memory 206432 kb
Host smart-a4426cf1-3871-4026-935e-61adcd1dfe94
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=64877172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.64877172
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2058228817
Short name T1261
Test name
Test status
Simulation time 166728826 ps
CPU time 0.89 seconds
Started Jul 03 04:53:15 PM PDT 24
Finished Jul 03 04:53:16 PM PDT 24
Peak memory 206088 kb
Host smart-4fe831fd-3275-459b-8011-2fdfe71628e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20582
28817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2058228817
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.1009019639
Short name T2668
Test name
Test status
Simulation time 142859673 ps
CPU time 0.81 seconds
Started Jul 03 04:53:06 PM PDT 24
Finished Jul 03 04:53:07 PM PDT 24
Peak memory 206128 kb
Host smart-5051eab1-2f62-4b27-b514-9e001e6addc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10090
19639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1009019639
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3442233629
Short name T2415
Test name
Test status
Simulation time 526326933 ps
CPU time 1.8 seconds
Started Jul 03 04:53:10 PM PDT 24
Finished Jul 03 04:53:13 PM PDT 24
Peak memory 206332 kb
Host smart-8608ac36-9315-4d75-9476-75f1b76ee8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34422
33629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3442233629
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_device_address.1193263640
Short name T1619
Test name
Test status
Simulation time 9813776207 ps
CPU time 18.01 seconds
Started Jul 03 04:53:10 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206368 kb
Host smart-f0b68c7c-033b-4e58-bb1b-474ad495ac9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11932
63640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1193263640
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1492197843
Short name T864
Test name
Test status
Simulation time 535396582 ps
CPU time 1.4 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:53:19 PM PDT 24
Peak memory 205984 kb
Host smart-eee7e822-28ad-4e31-b3c2-a6bf7bc0c9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14921
97843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1492197843
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2021373996
Short name T2495
Test name
Test status
Simulation time 139127614 ps
CPU time 0.73 seconds
Started Jul 03 04:53:13 PM PDT 24
Finished Jul 03 04:53:14 PM PDT 24
Peak memory 206104 kb
Host smart-eb6e6bbc-9638-4618-99ac-cda34d2a62dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20213
73996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2021373996
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.3676573980
Short name T2165
Test name
Test status
Simulation time 38161339 ps
CPU time 0.66 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:53:18 PM PDT 24
Peak memory 206108 kb
Host smart-9f1a1d43-e5f3-452f-9c9d-fca87bd711e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36765
73980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3676573980
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.1179005079
Short name T2239
Test name
Test status
Simulation time 866922646 ps
CPU time 2.2 seconds
Started Jul 03 04:53:21 PM PDT 24
Finished Jul 03 04:53:24 PM PDT 24
Peak memory 206344 kb
Host smart-f0d35153-1603-4fe7-9474-9fbb5c9d210a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11790
05079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.1179005079
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3241217571
Short name T986
Test name
Test status
Simulation time 184505877 ps
CPU time 1.2 seconds
Started Jul 03 04:53:19 PM PDT 24
Finished Jul 03 04:53:21 PM PDT 24
Peak memory 206388 kb
Host smart-fe0cff76-8f54-4585-ac9e-8b8b54f611fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32412
17571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3241217571
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3249549867
Short name T1964
Test name
Test status
Simulation time 215064004 ps
CPU time 0.82 seconds
Started Jul 03 04:53:24 PM PDT 24
Finished Jul 03 04:53:26 PM PDT 24
Peak memory 206072 kb
Host smart-e81f3737-ade4-4763-aebb-597712d8af7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32495
49867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3249549867
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1470538386
Short name T2485
Test name
Test status
Simulation time 140720584 ps
CPU time 0.74 seconds
Started Jul 03 04:53:14 PM PDT 24
Finished Jul 03 04:53:16 PM PDT 24
Peak memory 206068 kb
Host smart-d09dee71-5325-4c54-b1b2-96f7b2c59550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14705
38386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1470538386
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.400043467
Short name T413
Test name
Test status
Simulation time 166626162 ps
CPU time 0.85 seconds
Started Jul 03 04:53:20 PM PDT 24
Finished Jul 03 04:53:21 PM PDT 24
Peak memory 206104 kb
Host smart-8cd0c766-d8bf-4486-8de1-b8184df4e72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40004
3467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.400043467
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1687174526
Short name T1172
Test name
Test status
Simulation time 235017678 ps
CPU time 0.97 seconds
Started Jul 03 04:53:20 PM PDT 24
Finished Jul 03 04:53:21 PM PDT 24
Peak memory 206108 kb
Host smart-57ff4b73-1c9e-498b-8a1c-d9de919a71eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16871
74526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1687174526
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3226678350
Short name T2425
Test name
Test status
Simulation time 23297863991 ps
CPU time 26.04 seconds
Started Jul 03 04:53:16 PM PDT 24
Finished Jul 03 04:53:43 PM PDT 24
Peak memory 206196 kb
Host smart-157de6fa-f0aa-4fa6-afbc-f67e1a5d88f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32266
78350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3226678350
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2795848741
Short name T2669
Test name
Test status
Simulation time 3299443481 ps
CPU time 4.07 seconds
Started Jul 03 04:53:14 PM PDT 24
Finished Jul 03 04:53:18 PM PDT 24
Peak memory 206140 kb
Host smart-22cf6e77-8fa6-4643-aab3-87207dfd67b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27958
48741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2795848741
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.1545332225
Short name T1270
Test name
Test status
Simulation time 9206013155 ps
CPU time 256.21 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:57:33 PM PDT 24
Peak memory 206420 kb
Host smart-1bc6b866-cf0b-4431-91a4-844fb8fcd94f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15453
32225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.1545332225
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1866789637
Short name T158
Test name
Test status
Simulation time 4371403654 ps
CPU time 120.9 seconds
Started Jul 03 04:53:22 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206352 kb
Host smart-9d4740e1-66a9-46b8-a266-b30084c3edc8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1866789637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1866789637
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1339862107
Short name T2226
Test name
Test status
Simulation time 255190333 ps
CPU time 0.93 seconds
Started Jul 03 04:53:24 PM PDT 24
Finished Jul 03 04:53:26 PM PDT 24
Peak memory 206128 kb
Host smart-0b015b25-5816-4a7f-8c2c-3522f071712e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1339862107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1339862107
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.209787173
Short name T1398
Test name
Test status
Simulation time 191446203 ps
CPU time 0.86 seconds
Started Jul 03 04:53:20 PM PDT 24
Finished Jul 03 04:53:22 PM PDT 24
Peak memory 206072 kb
Host smart-d337fd01-190c-4b8c-81d3-2506f6930a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20978
7173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.209787173
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2215122467
Short name T862
Test name
Test status
Simulation time 5816321029 ps
CPU time 51.28 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:54:09 PM PDT 24
Peak memory 206328 kb
Host smart-6ffd553c-b4e4-458f-832f-626f732e7ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22151
22467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2215122467
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.4116806723
Short name T1345
Test name
Test status
Simulation time 4661734660 ps
CPU time 33.24 seconds
Started Jul 03 04:53:21 PM PDT 24
Finished Jul 03 04:53:55 PM PDT 24
Peak memory 206360 kb
Host smart-28fae207-d183-4ff0-9040-5f83e1c2b127
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4116806723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.4116806723
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.1619776620
Short name T1653
Test name
Test status
Simulation time 182780822 ps
CPU time 0.82 seconds
Started Jul 03 04:53:19 PM PDT 24
Finished Jul 03 04:53:21 PM PDT 24
Peak memory 206136 kb
Host smart-e15dc124-df60-4e0f-82f6-eb5c3327bad6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1619776620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.1619776620
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3001257757
Short name T2231
Test name
Test status
Simulation time 159485544 ps
CPU time 0.76 seconds
Started Jul 03 04:53:13 PM PDT 24
Finished Jul 03 04:53:14 PM PDT 24
Peak memory 205980 kb
Host smart-154d7f12-8b08-4304-8183-e98de3bd8484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30012
57757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3001257757
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1713105169
Short name T147
Test name
Test status
Simulation time 223826998 ps
CPU time 0.91 seconds
Started Jul 03 04:53:20 PM PDT 24
Finished Jul 03 04:53:22 PM PDT 24
Peak memory 206080 kb
Host smart-e6ab5034-b3bd-4213-b9d2-2fbbdd85280e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
05169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1713105169
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1038062721
Short name T1403
Test name
Test status
Simulation time 210087722 ps
CPU time 0.89 seconds
Started Jul 03 04:53:21 PM PDT 24
Finished Jul 03 04:53:22 PM PDT 24
Peak memory 206132 kb
Host smart-9f5ff473-97e4-48a7-87aa-f936a5c4512e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10380
62721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1038062721
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.4088310382
Short name T113
Test name
Test status
Simulation time 218272874 ps
CPU time 0.9 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:53:19 PM PDT 24
Peak memory 206080 kb
Host smart-7019d132-de13-436d-8695-99a43393dfa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40883
10382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.4088310382
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3401501812
Short name T96
Test name
Test status
Simulation time 184254525 ps
CPU time 0.87 seconds
Started Jul 03 04:53:24 PM PDT 24
Finished Jul 03 04:53:26 PM PDT 24
Peak memory 206092 kb
Host smart-90b262bc-4e0a-4b1d-8067-74ee375fe163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34015
01812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3401501812
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1392964031
Short name T171
Test name
Test status
Simulation time 150712238 ps
CPU time 0.74 seconds
Started Jul 03 04:53:26 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206076 kb
Host smart-46070897-44b4-4f5c-a770-b1853d555a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13929
64031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1392964031
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2759826323
Short name T2466
Test name
Test status
Simulation time 240471105 ps
CPU time 1.02 seconds
Started Jul 03 04:53:18 PM PDT 24
Finished Jul 03 04:53:20 PM PDT 24
Peak memory 206140 kb
Host smart-4e1371b0-e257-4b6d-8662-bfa45c3fb7c5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2759826323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2759826323
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3819641691
Short name T1993
Test name
Test status
Simulation time 149502504 ps
CPU time 0.84 seconds
Started Jul 03 04:53:15 PM PDT 24
Finished Jul 03 04:53:17 PM PDT 24
Peak memory 206092 kb
Host smart-fddc7ba4-712b-4269-8bdc-d440ec209f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38196
41691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3819641691
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1995048392
Short name T1340
Test name
Test status
Simulation time 48303630 ps
CPU time 0.68 seconds
Started Jul 03 04:53:12 PM PDT 24
Finished Jul 03 04:53:13 PM PDT 24
Peak memory 206032 kb
Host smart-c8514cdd-ed0b-4271-b555-c84621c62086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19950
48392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1995048392
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1479829349
Short name T274
Test name
Test status
Simulation time 13401370820 ps
CPU time 30.82 seconds
Started Jul 03 04:53:16 PM PDT 24
Finished Jul 03 04:53:47 PM PDT 24
Peak memory 206392 kb
Host smart-849ddf81-5584-41f9-ba91-6485de2bfdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14798
29349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1479829349
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2733074202
Short name T1267
Test name
Test status
Simulation time 209007332 ps
CPU time 0.9 seconds
Started Jul 03 04:53:21 PM PDT 24
Finished Jul 03 04:53:23 PM PDT 24
Peak memory 206096 kb
Host smart-525d0c53-655a-4b18-9bf5-3c729918c8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27330
74202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2733074202
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2131308351
Short name T2622
Test name
Test status
Simulation time 215829055 ps
CPU time 0.88 seconds
Started Jul 03 04:53:25 PM PDT 24
Finished Jul 03 04:53:27 PM PDT 24
Peak memory 206084 kb
Host smart-e43b6595-7b27-45aa-9aca-d2765ea5f59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21313
08351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2131308351
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2975229091
Short name T1433
Test name
Test status
Simulation time 228938119 ps
CPU time 0.87 seconds
Started Jul 03 04:53:18 PM PDT 24
Finished Jul 03 04:53:19 PM PDT 24
Peak memory 206092 kb
Host smart-ec2748e3-a455-42f9-962b-79bbe43bc7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29752
29091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2975229091
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3430222496
Short name T532
Test name
Test status
Simulation time 162381907 ps
CPU time 0.87 seconds
Started Jul 03 04:53:25 PM PDT 24
Finished Jul 03 04:53:31 PM PDT 24
Peak memory 206108 kb
Host smart-04114fa4-948d-4751-83f6-280169cadd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34302
22496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3430222496
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3859905471
Short name T753
Test name
Test status
Simulation time 172923002 ps
CPU time 0.83 seconds
Started Jul 03 04:53:20 PM PDT 24
Finished Jul 03 04:53:21 PM PDT 24
Peak memory 206124 kb
Host smart-a2c1cd5e-005a-47d6-9a6b-0dd859d0f4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38599
05471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3859905471
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2270648512
Short name T1260
Test name
Test status
Simulation time 144988292 ps
CPU time 0.84 seconds
Started Jul 03 04:53:20 PM PDT 24
Finished Jul 03 04:53:21 PM PDT 24
Peak memory 206136 kb
Host smart-e138b44f-cd30-475c-a966-2b9314869dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22706
48512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2270648512
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1907472203
Short name T1893
Test name
Test status
Simulation time 183854346 ps
CPU time 0.82 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:53:19 PM PDT 24
Peak memory 206112 kb
Host smart-ef523b39-2bf4-4e4f-9a2f-f2c325363bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19074
72203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1907472203
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3043734823
Short name T1860
Test name
Test status
Simulation time 207080942 ps
CPU time 1 seconds
Started Jul 03 04:53:25 PM PDT 24
Finished Jul 03 04:53:27 PM PDT 24
Peak memory 206040 kb
Host smart-0fcdd697-b4a5-4b66-97b0-5c8cc55e2183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30437
34823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3043734823
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.322790965
Short name T2476
Test name
Test status
Simulation time 4373529094 ps
CPU time 122.83 seconds
Started Jul 03 04:53:19 PM PDT 24
Finished Jul 03 04:55:22 PM PDT 24
Peak memory 206428 kb
Host smart-6098d42f-4c25-4fc3-8f0c-2c922607eaad
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=322790965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.322790965
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1736738090
Short name T1413
Test name
Test status
Simulation time 198697172 ps
CPU time 0.84 seconds
Started Jul 03 04:53:24 PM PDT 24
Finished Jul 03 04:53:26 PM PDT 24
Peak memory 206100 kb
Host smart-6b2a7c11-9c1a-428a-94d3-9ab54d37d798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17367
38090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1736738090
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2343437269
Short name T2408
Test name
Test status
Simulation time 150685782 ps
CPU time 0.76 seconds
Started Jul 03 04:53:19 PM PDT 24
Finished Jul 03 04:53:20 PM PDT 24
Peak memory 206132 kb
Host smart-d5278993-8d4d-4091-a199-d47423129ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23434
37269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2343437269
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.3375144284
Short name T2683
Test name
Test status
Simulation time 1077264209 ps
CPU time 2.71 seconds
Started Jul 03 04:53:23 PM PDT 24
Finished Jul 03 04:53:26 PM PDT 24
Peak memory 206376 kb
Host smart-ccee2e92-9eb6-48f6-a7cd-86db675b101c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33751
44284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.3375144284
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.679668621
Short name T1418
Test name
Test status
Simulation time 4543708531 ps
CPU time 123.87 seconds
Started Jul 03 04:53:23 PM PDT 24
Finished Jul 03 04:55:28 PM PDT 24
Peak memory 206436 kb
Host smart-771a26dc-5d8a-49d5-9fe1-3dcaf780cb19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67966
8621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.679668621
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.711841523
Short name T1943
Test name
Test status
Simulation time 33832564 ps
CPU time 0.67 seconds
Started Jul 03 04:53:28 PM PDT 24
Finished Jul 03 04:53:29 PM PDT 24
Peak memory 206172 kb
Host smart-55c7a52a-6768-4913-b135-3519d8ed043d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=711841523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.711841523
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2213367166
Short name T460
Test name
Test status
Simulation time 4004572871 ps
CPU time 5.12 seconds
Started Jul 03 04:53:19 PM PDT 24
Finished Jul 03 04:53:24 PM PDT 24
Peak memory 206444 kb
Host smart-901cac94-2569-4378-bdd5-225b91d3a73f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2213367166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.2213367166
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3852944620
Short name T761
Test name
Test status
Simulation time 13359549055 ps
CPU time 11.85 seconds
Started Jul 03 04:53:18 PM PDT 24
Finished Jul 03 04:53:31 PM PDT 24
Peak memory 206328 kb
Host smart-a8073209-a14b-4fd5-9e63-f294729ed942
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3852944620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3852944620
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2139628380
Short name T1660
Test name
Test status
Simulation time 23430508485 ps
CPU time 22.91 seconds
Started Jul 03 04:53:18 PM PDT 24
Finished Jul 03 04:53:41 PM PDT 24
Peak memory 206196 kb
Host smart-b00a2233-7d3f-4bcf-b870-cd3efb6ab00e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2139628380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.2139628380
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.864414097
Short name T340
Test name
Test status
Simulation time 192782783 ps
CPU time 0.84 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:53:19 PM PDT 24
Peak memory 206128 kb
Host smart-ac6a21ac-8c81-4081-bc25-e319bd2f3614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86441
4097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.864414097
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2312716049
Short name T2061
Test name
Test status
Simulation time 145420616 ps
CPU time 0.78 seconds
Started Jul 03 04:53:28 PM PDT 24
Finished Jul 03 04:53:29 PM PDT 24
Peak memory 206096 kb
Host smart-ee9d3cdc-f7d0-413f-9cf8-ca1919e92e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23127
16049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2312716049
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.1855494291
Short name T1210
Test name
Test status
Simulation time 372536835 ps
CPU time 1.16 seconds
Started Jul 03 04:53:25 PM PDT 24
Finished Jul 03 04:53:27 PM PDT 24
Peak memory 206092 kb
Host smart-e02084f7-0116-46b6-b4d2-01abed58f4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18554
94291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.1855494291
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3960531007
Short name T1437
Test name
Test status
Simulation time 477828876 ps
CPU time 1.27 seconds
Started Jul 03 04:53:16 PM PDT 24
Finished Jul 03 04:53:18 PM PDT 24
Peak memory 206132 kb
Host smart-235a491b-8e82-4dca-90a5-7b38448dfce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39605
31007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3960531007
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.2062718101
Short name T1448
Test name
Test status
Simulation time 13763827362 ps
CPU time 28.59 seconds
Started Jul 03 04:53:24 PM PDT 24
Finished Jul 03 04:53:54 PM PDT 24
Peak memory 206444 kb
Host smart-2011ad86-eb27-4027-af56-642cb794e970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20627
18101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.2062718101
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.804271091
Short name T1895
Test name
Test status
Simulation time 438757740 ps
CPU time 1.32 seconds
Started Jul 03 04:53:21 PM PDT 24
Finished Jul 03 04:53:23 PM PDT 24
Peak memory 206088 kb
Host smart-e8d3c2aa-5ebc-4559-ae4a-0dff8ae4ac1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80427
1091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.804271091
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.484211316
Short name T1231
Test name
Test status
Simulation time 171592216 ps
CPU time 0.79 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:53:19 PM PDT 24
Peak memory 206144 kb
Host smart-dffe9c9c-a730-4c44-a4cf-45d3f9086549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48421
1316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.484211316
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2618883301
Short name T1428
Test name
Test status
Simulation time 62750520 ps
CPU time 0.66 seconds
Started Jul 03 04:53:24 PM PDT 24
Finished Jul 03 04:53:25 PM PDT 24
Peak memory 206092 kb
Host smart-fc00ef33-6fa8-4bec-a3e9-f59c7dc4236f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26188
83301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2618883301
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.918231731
Short name T1846
Test name
Test status
Simulation time 829211597 ps
CPU time 2.19 seconds
Started Jul 03 04:53:22 PM PDT 24
Finished Jul 03 04:53:25 PM PDT 24
Peak memory 206412 kb
Host smart-74d641a0-6bed-4429-b40f-a7be518439be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91823
1731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.918231731
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1589327260
Short name T2359
Test name
Test status
Simulation time 172994597 ps
CPU time 1.73 seconds
Started Jul 03 04:53:24 PM PDT 24
Finished Jul 03 04:53:27 PM PDT 24
Peak memory 206272 kb
Host smart-fb360352-3727-49c1-96eb-bbeab7c7e386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15893
27260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1589327260
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2983994657
Short name T744
Test name
Test status
Simulation time 230060672 ps
CPU time 0.87 seconds
Started Jul 03 04:53:21 PM PDT 24
Finished Jul 03 04:53:22 PM PDT 24
Peak memory 206112 kb
Host smart-af418d00-1af7-48c9-af4c-d34f17b5feb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29839
94657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2983994657
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2768030531
Short name T2567
Test name
Test status
Simulation time 148093840 ps
CPU time 0.79 seconds
Started Jul 03 04:53:23 PM PDT 24
Finished Jul 03 04:53:24 PM PDT 24
Peak memory 206048 kb
Host smart-1e2ba0b7-ee6e-4611-b858-d589847ca2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27680
30531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2768030531
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2876181874
Short name T2209
Test name
Test status
Simulation time 223573125 ps
CPU time 0.95 seconds
Started Jul 03 04:53:24 PM PDT 24
Finished Jul 03 04:53:26 PM PDT 24
Peak memory 206132 kb
Host smart-e2de2d24-69a9-48d3-a09d-f43a7356c909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28761
81874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2876181874
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.516622301
Short name T2038
Test name
Test status
Simulation time 9356298353 ps
CPU time 69.4 seconds
Started Jul 03 04:53:27 PM PDT 24
Finished Jul 03 04:54:37 PM PDT 24
Peak memory 206420 kb
Host smart-3bc40d39-724b-45b1-bef1-ad1f3427e349
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=516622301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.516622301
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.2607673568
Short name T1781
Test name
Test status
Simulation time 227864782 ps
CPU time 0.97 seconds
Started Jul 03 04:53:23 PM PDT 24
Finished Jul 03 04:53:25 PM PDT 24
Peak memory 206104 kb
Host smart-9769a179-0b4d-4853-b9b8-381b7dbca212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26076
73568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.2607673568
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.1166824189
Short name T1497
Test name
Test status
Simulation time 23306309308 ps
CPU time 26.11 seconds
Started Jul 03 04:53:21 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 206180 kb
Host smart-c425fd5e-701f-457b-97f9-af95a1c9cade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11668
24189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.1166824189
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1341067866
Short name T1258
Test name
Test status
Simulation time 3337255714 ps
CPU time 3.85 seconds
Started Jul 03 04:53:23 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206112 kb
Host smart-e1fc29ed-aaee-411a-83e3-8b879bbba7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13410
67866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1341067866
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3664956747
Short name T2083
Test name
Test status
Simulation time 11406668978 ps
CPU time 100.62 seconds
Started Jul 03 04:53:17 PM PDT 24
Finished Jul 03 04:54:59 PM PDT 24
Peak memory 206260 kb
Host smart-7adb5e56-731b-4df2-b8a3-5f778244dc76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36649
56747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3664956747
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1970082457
Short name T790
Test name
Test status
Simulation time 3245854417 ps
CPU time 31.23 seconds
Started Jul 03 04:53:21 PM PDT 24
Finished Jul 03 04:53:53 PM PDT 24
Peak memory 206412 kb
Host smart-6bfe7300-21a4-42cd-a55c-2800519aba3a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1970082457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1970082457
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3781256897
Short name T1564
Test name
Test status
Simulation time 272640707 ps
CPU time 0.94 seconds
Started Jul 03 04:53:22 PM PDT 24
Finished Jul 03 04:53:24 PM PDT 24
Peak memory 206092 kb
Host smart-442b4447-e71d-418a-ac54-6c1d11b6c335
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3781256897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3781256897
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.268721343
Short name T538
Test name
Test status
Simulation time 194070305 ps
CPU time 0.83 seconds
Started Jul 03 04:53:22 PM PDT 24
Finished Jul 03 04:53:23 PM PDT 24
Peak memory 206052 kb
Host smart-6197fc62-0cac-40c2-b1e2-5ec7029c47db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26872
1343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.268721343
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.265482799
Short name T1968
Test name
Test status
Simulation time 6539194954 ps
CPU time 181.06 seconds
Started Jul 03 04:53:31 PM PDT 24
Finished Jul 03 04:56:32 PM PDT 24
Peak memory 206320 kb
Host smart-16c98c39-5e18-4ddc-88e1-ebd2a885f488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26548
2799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.265482799
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2134067061
Short name T2108
Test name
Test status
Simulation time 5447709885 ps
CPU time 150.44 seconds
Started Jul 03 04:53:28 PM PDT 24
Finished Jul 03 04:55:59 PM PDT 24
Peak memory 206380 kb
Host smart-2fa32d34-a4ae-466c-ac6a-9df735c5102d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2134067061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2134067061
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3285055315
Short name T1695
Test name
Test status
Simulation time 155892963 ps
CPU time 0.84 seconds
Started Jul 03 04:53:19 PM PDT 24
Finished Jul 03 04:53:20 PM PDT 24
Peak memory 206132 kb
Host smart-0f2d6edf-ceff-4b9c-9443-a34f75b35ec8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3285055315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3285055315
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1435273460
Short name T2538
Test name
Test status
Simulation time 162255734 ps
CPU time 0.78 seconds
Started Jul 03 04:53:24 PM PDT 24
Finished Jul 03 04:53:25 PM PDT 24
Peak memory 206108 kb
Host smart-cc7a2b5b-9dc0-4e40-a48e-a7fd495a7b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14352
73460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1435273460
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2463697963
Short name T129
Test name
Test status
Simulation time 211070671 ps
CPU time 0.86 seconds
Started Jul 03 04:53:26 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206104 kb
Host smart-60af4d32-8daa-4b56-9060-97fddc5a443c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24636
97963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2463697963
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3590502209
Short name T1727
Test name
Test status
Simulation time 195768209 ps
CPU time 0.91 seconds
Started Jul 03 04:53:24 PM PDT 24
Finished Jul 03 04:53:26 PM PDT 24
Peak memory 206080 kb
Host smart-2bf262c9-48d0-4971-ae78-513dfd53c125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35905
02209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3590502209
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3269434486
Short name T2613
Test name
Test status
Simulation time 159435885 ps
CPU time 0.82 seconds
Started Jul 03 04:53:26 PM PDT 24
Finished Jul 03 04:53:27 PM PDT 24
Peak memory 206124 kb
Host smart-9988d3ae-e369-4073-bf4a-8b05d5da67e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32694
34486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3269434486
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1547973269
Short name T949
Test name
Test status
Simulation time 195347854 ps
CPU time 0.89 seconds
Started Jul 03 04:53:29 PM PDT 24
Finished Jul 03 04:53:30 PM PDT 24
Peak memory 206132 kb
Host smart-a43fc4fc-feb7-437b-b02a-45ce032de8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15479
73269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1547973269
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1931424700
Short name T2143
Test name
Test status
Simulation time 205463641 ps
CPU time 0.88 seconds
Started Jul 03 04:53:27 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206044 kb
Host smart-fafc5454-f425-486e-b457-7b10d826952c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19314
24700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1931424700
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.94190185
Short name T374
Test name
Test status
Simulation time 255694442 ps
CPU time 0.94 seconds
Started Jul 03 04:53:29 PM PDT 24
Finished Jul 03 04:53:30 PM PDT 24
Peak memory 206132 kb
Host smart-e4cc4d4e-4637-4825-92e2-1beb982a3a56
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=94190185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.94190185
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.4076945674
Short name T1973
Test name
Test status
Simulation time 208401136 ps
CPU time 0.78 seconds
Started Jul 03 04:53:29 PM PDT 24
Finished Jul 03 04:53:30 PM PDT 24
Peak memory 206108 kb
Host smart-ccb28bdf-9159-40bc-b407-ea44051d21c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40769
45674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.4076945674
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1202370519
Short name T1024
Test name
Test status
Simulation time 36950787 ps
CPU time 0.68 seconds
Started Jul 03 04:53:26 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206136 kb
Host smart-a9a7b233-25fd-46fd-9384-c3af4a91523c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12023
70519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1202370519
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.33320197
Short name T1873
Test name
Test status
Simulation time 11605290493 ps
CPU time 25.05 seconds
Started Jul 03 04:53:31 PM PDT 24
Finished Jul 03 04:53:57 PM PDT 24
Peak memory 206468 kb
Host smart-f6682c4d-b596-4ccd-9596-983a3281b7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33320
197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.33320197
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2758355522
Short name T491
Test name
Test status
Simulation time 191157387 ps
CPU time 0.89 seconds
Started Jul 03 04:53:28 PM PDT 24
Finished Jul 03 04:53:30 PM PDT 24
Peak memory 206108 kb
Host smart-2ddea807-cf41-4b42-9c08-34b39de9b0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27583
55522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2758355522
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.653543071
Short name T1514
Test name
Test status
Simulation time 190915570 ps
CPU time 0.94 seconds
Started Jul 03 04:53:28 PM PDT 24
Finished Jul 03 04:53:29 PM PDT 24
Peak memory 206052 kb
Host smart-1fb005c5-d423-46f5-a790-796c9923321b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65354
3071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.653543071
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.1036733481
Short name T1000
Test name
Test status
Simulation time 158901653 ps
CPU time 0.83 seconds
Started Jul 03 04:53:25 PM PDT 24
Finished Jul 03 04:53:27 PM PDT 24
Peak memory 206124 kb
Host smart-2260e614-0fab-4bb3-8014-f0ce79773469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10367
33481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.1036733481
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.4019882876
Short name T800
Test name
Test status
Simulation time 209370228 ps
CPU time 0.85 seconds
Started Jul 03 04:53:23 PM PDT 24
Finished Jul 03 04:53:24 PM PDT 24
Peak memory 206132 kb
Host smart-9d99212f-c63f-4b5b-9a71-f32e80309caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40198
82876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.4019882876
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3932541890
Short name T1502
Test name
Test status
Simulation time 182911560 ps
CPU time 0.98 seconds
Started Jul 03 04:53:30 PM PDT 24
Finished Jul 03 04:53:32 PM PDT 24
Peak memory 206144 kb
Host smart-a8937ca7-d728-46ff-88a7-3939ffad82af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39325
41890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3932541890
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.95170426
Short name T992
Test name
Test status
Simulation time 161174408 ps
CPU time 0.76 seconds
Started Jul 03 04:53:30 PM PDT 24
Finished Jul 03 04:53:31 PM PDT 24
Peak memory 206112 kb
Host smart-64e165d7-ffb4-4952-bc9f-7b39ae7b418e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95170
426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.95170426
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.938103682
Short name T2331
Test name
Test status
Simulation time 166814273 ps
CPU time 0.83 seconds
Started Jul 03 04:53:31 PM PDT 24
Finished Jul 03 04:53:33 PM PDT 24
Peak memory 206120 kb
Host smart-0cf2e668-2f0e-4a88-9f4f-21b634836cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93810
3682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.938103682
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2546297773
Short name T377
Test name
Test status
Simulation time 239524796 ps
CPU time 0.97 seconds
Started Jul 03 04:53:34 PM PDT 24
Finished Jul 03 04:53:35 PM PDT 24
Peak memory 206132 kb
Host smart-bfef983d-5339-4173-9741-c91388f718d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25462
97773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2546297773
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2042039807
Short name T2371
Test name
Test status
Simulation time 5705237983 ps
CPU time 53.66 seconds
Started Jul 03 04:53:25 PM PDT 24
Finished Jul 03 04:54:19 PM PDT 24
Peak memory 206384 kb
Host smart-3a504ecb-cd67-4337-b202-57fd2d3e315c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2042039807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2042039807
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.351298756
Short name T2394
Test name
Test status
Simulation time 176033224 ps
CPU time 0.8 seconds
Started Jul 03 04:53:26 PM PDT 24
Finished Jul 03 04:53:27 PM PDT 24
Peak memory 206128 kb
Host smart-799dfdc7-5c90-415f-ab96-5b40669214e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35129
8756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.351298756
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1527878901
Short name T2102
Test name
Test status
Simulation time 166748822 ps
CPU time 0.84 seconds
Started Jul 03 04:53:25 PM PDT 24
Finished Jul 03 04:53:27 PM PDT 24
Peak memory 206128 kb
Host smart-82c33ccd-db02-4995-a9d8-bce8858faa93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15278
78901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1527878901
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2207518323
Short name T1077
Test name
Test status
Simulation time 1149705390 ps
CPU time 2.33 seconds
Started Jul 03 04:53:29 PM PDT 24
Finished Jul 03 04:53:31 PM PDT 24
Peak memory 206304 kb
Host smart-9c08938d-dfaf-4583-a7e3-83218470a7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22075
18323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2207518323
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3612192422
Short name T2703
Test name
Test status
Simulation time 4805526032 ps
CPU time 45.28 seconds
Started Jul 03 04:53:26 PM PDT 24
Finished Jul 03 04:54:12 PM PDT 24
Peak memory 206340 kb
Host smart-5a34682f-0d11-454a-ba81-f97681a88e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36121
92422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3612192422
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.4189899663
Short name T210
Test name
Test status
Simulation time 54708441 ps
CPU time 0.71 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 206148 kb
Host smart-4d50a88c-7334-433f-a5c6-06957ae1b50a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4189899663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.4189899663
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2039779737
Short name T1326
Test name
Test status
Simulation time 3986888189 ps
CPU time 5.83 seconds
Started Jul 03 04:53:29 PM PDT 24
Finished Jul 03 04:53:35 PM PDT 24
Peak memory 206440 kb
Host smart-b9a954f0-ec9f-4505-9a3b-8136c8f6f0da
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2039779737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2039779737
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1430439145
Short name T2103
Test name
Test status
Simulation time 13325280219 ps
CPU time 12.2 seconds
Started Jul 03 04:53:28 PM PDT 24
Finished Jul 03 04:53:41 PM PDT 24
Peak memory 206176 kb
Host smart-4c42f6f5-96d6-454e-a6ff-1d8421a3668f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1430439145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1430439145
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.560730622
Short name T978
Test name
Test status
Simulation time 23381642569 ps
CPU time 23.95 seconds
Started Jul 03 04:53:26 PM PDT 24
Finished Jul 03 04:53:51 PM PDT 24
Peak memory 206172 kb
Host smart-5125d45f-3618-417c-a756-2ee03437f910
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=560730622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.560730622
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2466465204
Short name T1825
Test name
Test status
Simulation time 147278565 ps
CPU time 0.77 seconds
Started Jul 03 04:53:33 PM PDT 24
Finished Jul 03 04:53:34 PM PDT 24
Peak memory 206052 kb
Host smart-11dfe2ff-695d-4967-8119-96b4a358bb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24664
65204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2466465204
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.125902971
Short name T2088
Test name
Test status
Simulation time 178262742 ps
CPU time 0.79 seconds
Started Jul 03 04:53:27 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206096 kb
Host smart-dec62a74-ac45-4d6c-af89-c2185c4d2cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12590
2971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.125902971
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.4046734347
Short name T176
Test name
Test status
Simulation time 405198845 ps
CPU time 1.27 seconds
Started Jul 03 04:53:41 PM PDT 24
Finished Jul 03 04:53:42 PM PDT 24
Peak memory 206076 kb
Host smart-395e09bf-ac95-493e-85bd-f155da857261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40467
34347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.4046734347
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1249647601
Short name T1342
Test name
Test status
Simulation time 486618353 ps
CPU time 1.44 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206136 kb
Host smart-6bfe1e8a-7b60-405a-86d4-8410bb28e9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12496
47601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1249647601
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.138188081
Short name T1794
Test name
Test status
Simulation time 13001895706 ps
CPU time 27.49 seconds
Started Jul 03 04:53:28 PM PDT 24
Finished Jul 03 04:53:56 PM PDT 24
Peak memory 206424 kb
Host smart-f2d98d24-81da-437f-91c3-2590528946ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13818
8081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.138188081
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3572790245
Short name T1092
Test name
Test status
Simulation time 440407572 ps
CPU time 1.33 seconds
Started Jul 03 04:53:36 PM PDT 24
Finished Jul 03 04:53:37 PM PDT 24
Peak memory 206108 kb
Host smart-89141316-1151-4770-ab20-cfa592e887af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35727
90245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3572790245
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.251719350
Short name T2565
Test name
Test status
Simulation time 155523144 ps
CPU time 0.76 seconds
Started Jul 03 04:53:40 PM PDT 24
Finished Jul 03 04:53:41 PM PDT 24
Peak memory 206128 kb
Host smart-4c6a2b50-618c-4b19-b9b9-4395416a3d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25171
9350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.251719350
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1733521825
Short name T1903
Test name
Test status
Simulation time 37127683 ps
CPU time 0.64 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:47 PM PDT 24
Peak memory 206108 kb
Host smart-8f8eaeb3-41c0-4852-8d37-f53e63ac2058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17335
21825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1733521825
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.492220794
Short name T1266
Test name
Test status
Simulation time 413032129 ps
CPU time 2.25 seconds
Started Jul 03 04:53:41 PM PDT 24
Finished Jul 03 04:53:44 PM PDT 24
Peak memory 206336 kb
Host smart-6c45c2a0-2f89-419f-b487-d4218bcdcbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49222
0794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.492220794
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.4138507215
Short name T572
Test name
Test status
Simulation time 149950728 ps
CPU time 0.79 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:53:46 PM PDT 24
Peak memory 206088 kb
Host smart-fb986980-803f-48b8-9797-72edf684e6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41385
07215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.4138507215
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.146495529
Short name T1782
Test name
Test status
Simulation time 235938407 ps
CPU time 0.95 seconds
Started Jul 03 04:53:31 PM PDT 24
Finished Jul 03 04:53:32 PM PDT 24
Peak memory 206144 kb
Host smart-65123129-e96f-4c47-aebc-81331ccd6584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14649
5529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.146495529
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3984024859
Short name T786
Test name
Test status
Simulation time 7087349776 ps
CPU time 48.61 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:54:38 PM PDT 24
Peak memory 206348 kb
Host smart-20e9cd84-61cb-49ee-abe6-29a9f9729b6d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3984024859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3984024859
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1488213030
Short name T1566
Test name
Test status
Simulation time 226754574 ps
CPU time 0.84 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:47 PM PDT 24
Peak memory 206132 kb
Host smart-38f4e7e2-022d-4a71-b7fe-e95a0736b091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14882
13030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1488213030
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3316453382
Short name T2216
Test name
Test status
Simulation time 23349463783 ps
CPU time 25.36 seconds
Started Jul 03 04:53:34 PM PDT 24
Finished Jul 03 04:54:00 PM PDT 24
Peak memory 206160 kb
Host smart-bee5781e-b1e1-49cb-9d1b-58b704fd6261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33164
53382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3316453382
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.1438152524
Short name T1806
Test name
Test status
Simulation time 3329273148 ps
CPU time 3.75 seconds
Started Jul 03 04:53:34 PM PDT 24
Finished Jul 03 04:53:38 PM PDT 24
Peak memory 206192 kb
Host smart-73651080-994d-45a5-bd54-25c7a4085a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14381
52524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1438152524
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.1175916501
Short name T252
Test name
Test status
Simulation time 10093758776 ps
CPU time 68.48 seconds
Started Jul 03 04:53:38 PM PDT 24
Finished Jul 03 04:54:46 PM PDT 24
Peak memory 206448 kb
Host smart-d2e44804-234f-45cb-9b94-f5acd9bac4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11759
16501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1175916501
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3972592907
Short name T911
Test name
Test status
Simulation time 6161194342 ps
CPU time 170.96 seconds
Started Jul 03 04:53:48 PM PDT 24
Finished Jul 03 04:56:41 PM PDT 24
Peak memory 206244 kb
Host smart-53f00d92-74f4-457d-aa31-c26e141a86a2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3972592907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3972592907
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2188703500
Short name T1441
Test name
Test status
Simulation time 251982104 ps
CPU time 0.89 seconds
Started Jul 03 04:53:31 PM PDT 24
Finished Jul 03 04:53:32 PM PDT 24
Peak memory 206128 kb
Host smart-4002be60-b65a-46ba-b35c-82fadc73ab6c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2188703500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2188703500
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.287730098
Short name T1633
Test name
Test status
Simulation time 197632156 ps
CPU time 0.86 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:46 PM PDT 24
Peak memory 206092 kb
Host smart-912f84e4-8564-4a7f-8a04-dbb950606e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28773
0098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.287730098
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.3930992333
Short name T2281
Test name
Test status
Simulation time 5743578479 ps
CPU time 153.06 seconds
Started Jul 03 04:53:33 PM PDT 24
Finished Jul 03 04:56:06 PM PDT 24
Peak memory 206360 kb
Host smart-6c6c1724-87a9-4619-accc-77050913972c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39309
92333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.3930992333
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3275543618
Short name T1122
Test name
Test status
Simulation time 4282813347 ps
CPU time 29.55 seconds
Started Jul 03 04:53:33 PM PDT 24
Finished Jul 03 04:54:03 PM PDT 24
Peak memory 206380 kb
Host smart-d302b72e-9e75-42fe-88ef-cba9a8f1e40e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3275543618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3275543618
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3088335204
Short name T1086
Test name
Test status
Simulation time 160914970 ps
CPU time 0.81 seconds
Started Jul 03 04:53:37 PM PDT 24
Finished Jul 03 04:53:38 PM PDT 24
Peak memory 206100 kb
Host smart-fc9d58b5-e2b7-47d6-a54b-2861abd927d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3088335204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3088335204
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.236524035
Short name T1796
Test name
Test status
Simulation time 153834907 ps
CPU time 0.76 seconds
Started Jul 03 04:53:28 PM PDT 24
Finished Jul 03 04:53:30 PM PDT 24
Peak memory 206096 kb
Host smart-d99a6567-63e5-45d5-ad47-9dac9c68caee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23652
4035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.236524035
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2922274572
Short name T1346
Test name
Test status
Simulation time 205561097 ps
CPU time 0.89 seconds
Started Jul 03 04:53:33 PM PDT 24
Finished Jul 03 04:53:34 PM PDT 24
Peak memory 206052 kb
Host smart-762cf666-f9b4-47a0-80f2-fed374617576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29222
74572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2922274572
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1337499574
Short name T1272
Test name
Test status
Simulation time 207520853 ps
CPU time 0.82 seconds
Started Jul 03 04:53:26 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 205940 kb
Host smart-68ef2408-64d3-4eb5-a834-fd20a0900c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13374
99574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1337499574
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3923447329
Short name T1384
Test name
Test status
Simulation time 190459895 ps
CPU time 0.88 seconds
Started Jul 03 04:53:36 PM PDT 24
Finished Jul 03 04:53:37 PM PDT 24
Peak memory 206132 kb
Host smart-ba703440-24c4-40e7-b159-30781cebe276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39234
47329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3923447329
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.807314341
Short name T2446
Test name
Test status
Simulation time 153670812 ps
CPU time 0.79 seconds
Started Jul 03 04:53:30 PM PDT 24
Finished Jul 03 04:53:31 PM PDT 24
Peak memory 206092 kb
Host smart-1cfe2408-ca2d-4b8f-9027-9fba3fcea045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80731
4341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.807314341
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1707933596
Short name T2379
Test name
Test status
Simulation time 211921726 ps
CPU time 0.87 seconds
Started Jul 03 04:53:41 PM PDT 24
Finished Jul 03 04:53:43 PM PDT 24
Peak memory 206076 kb
Host smart-35876fae-acf5-4660-8cbb-59a2699054ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17079
33596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1707933596
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1029924742
Short name T774
Test name
Test status
Simulation time 211740149 ps
CPU time 0.93 seconds
Started Jul 03 04:53:32 PM PDT 24
Finished Jul 03 04:53:33 PM PDT 24
Peak memory 206120 kb
Host smart-626cccef-ff6f-4552-83a5-5456b0f8fd57
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1029924742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1029924742
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1368442994
Short name T349
Test name
Test status
Simulation time 162733927 ps
CPU time 0.8 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:53:46 PM PDT 24
Peak memory 206100 kb
Host smart-7ef4f523-52aa-40e6-9e73-186b172479d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13684
42994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1368442994
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.137270471
Short name T1707
Test name
Test status
Simulation time 38446861 ps
CPU time 0.64 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:47 PM PDT 24
Peak memory 206100 kb
Host smart-aacf5589-97f6-4acc-8f79-092fd31fe253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13727
0471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.137270471
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.326865602
Short name T2675
Test name
Test status
Simulation time 8014723376 ps
CPU time 17.42 seconds
Started Jul 03 04:53:37 PM PDT 24
Finished Jul 03 04:53:54 PM PDT 24
Peak memory 206420 kb
Host smart-c4d65def-42db-4c1f-b6f7-1d34d61d164f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32686
5602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.326865602
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.872290249
Short name T381
Test name
Test status
Simulation time 149323519 ps
CPU time 0.79 seconds
Started Jul 03 04:53:42 PM PDT 24
Finished Jul 03 04:53:43 PM PDT 24
Peak memory 206084 kb
Host smart-22b25e2b-6967-4055-8f7a-f69210b4f136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87229
0249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.872290249
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.828153671
Short name T1461
Test name
Test status
Simulation time 202732147 ps
CPU time 0.83 seconds
Started Jul 03 04:53:41 PM PDT 24
Finished Jul 03 04:53:43 PM PDT 24
Peak memory 206092 kb
Host smart-4361aabc-03f7-4140-8611-65ee3edfec3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82815
3671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.828153671
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.4074812280
Short name T1139
Test name
Test status
Simulation time 212291965 ps
CPU time 0.88 seconds
Started Jul 03 04:53:30 PM PDT 24
Finished Jul 03 04:53:31 PM PDT 24
Peak memory 206004 kb
Host smart-a6608974-8fd1-4030-96c6-4acd5c1a5271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40748
12280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.4074812280
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.180689361
Short name T1817
Test name
Test status
Simulation time 165197582 ps
CPU time 0.83 seconds
Started Jul 03 04:53:30 PM PDT 24
Finished Jul 03 04:53:31 PM PDT 24
Peak memory 206068 kb
Host smart-b219a348-a4d1-43d7-94f4-33cea6aa040f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18068
9361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.180689361
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2779564759
Short name T1179
Test name
Test status
Simulation time 157991558 ps
CPU time 0.83 seconds
Started Jul 03 04:53:42 PM PDT 24
Finished Jul 03 04:53:43 PM PDT 24
Peak memory 206112 kb
Host smart-caa7143f-7649-4185-a372-93e98e66e6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27795
64759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2779564759
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2382052182
Short name T1501
Test name
Test status
Simulation time 178983744 ps
CPU time 0.8 seconds
Started Jul 03 04:53:31 PM PDT 24
Finished Jul 03 04:53:33 PM PDT 24
Peak memory 206112 kb
Host smart-0fc7f67c-10c8-4417-a0d5-835665c98d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23820
52182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2382052182
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.693444571
Short name T241
Test name
Test status
Simulation time 161869048 ps
CPU time 0.79 seconds
Started Jul 03 04:53:40 PM PDT 24
Finished Jul 03 04:53:42 PM PDT 24
Peak memory 206104 kb
Host smart-7a29c185-0ad8-4e97-89ac-9b736c12e392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69344
4571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.693444571
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.188988140
Short name T1131
Test name
Test status
Simulation time 248492025 ps
CPU time 1 seconds
Started Jul 03 04:53:33 PM PDT 24
Finished Jul 03 04:53:35 PM PDT 24
Peak memory 206128 kb
Host smart-8e9c2c9a-2965-4ebf-8715-6dbd2029470a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18898
8140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.188988140
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.3213343676
Short name T15
Test name
Test status
Simulation time 6279271812 ps
CPU time 42.63 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:54:29 PM PDT 24
Peak memory 206428 kb
Host smart-cdffde69-4192-4a18-bad8-4fb6766dddb9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3213343676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.3213343676
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1402717924
Short name T2407
Test name
Test status
Simulation time 196217791 ps
CPU time 0.83 seconds
Started Jul 03 04:53:42 PM PDT 24
Finished Jul 03 04:53:43 PM PDT 24
Peak memory 206072 kb
Host smart-77d7af40-0f69-4009-889a-061a1604ec8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14027
17924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1402717924
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.354851945
Short name T1776
Test name
Test status
Simulation time 147358153 ps
CPU time 0.78 seconds
Started Jul 03 04:53:29 PM PDT 24
Finished Jul 03 04:53:31 PM PDT 24
Peak memory 206132 kb
Host smart-dc4f7f00-3f40-41a9-9e3c-7ebc58139a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35485
1945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.354851945
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.511774284
Short name T2411
Test name
Test status
Simulation time 918546530 ps
CPU time 1.98 seconds
Started Jul 03 04:53:31 PM PDT 24
Finished Jul 03 04:53:34 PM PDT 24
Peak memory 206256 kb
Host smart-fc30b61f-c0af-4264-a59e-6704283767ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51177
4284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.511774284
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.998118351
Short name T469
Test name
Test status
Simulation time 4482193883 ps
CPU time 42.57 seconds
Started Jul 03 04:53:33 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206340 kb
Host smart-03f3dbcd-11db-4bf3-8122-8162a2ba4a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99811
8351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.998118351
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2030419640
Short name T1302
Test name
Test status
Simulation time 37432136 ps
CPU time 0.66 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:53:46 PM PDT 24
Peak memory 206188 kb
Host smart-367826ee-8fb0-4cfb-97de-42480b047e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2030419640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2030419640
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.4041768875
Short name T1931
Test name
Test status
Simulation time 3535002603 ps
CPU time 4.75 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:53 PM PDT 24
Peak memory 206168 kb
Host smart-f292cfc6-7d77-4566-a2f2-0a765fca69fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4041768875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.4041768875
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3596817568
Short name T934
Test name
Test status
Simulation time 13313556403 ps
CPU time 13.92 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:54:01 PM PDT 24
Peak memory 206176 kb
Host smart-2e8b7264-5e80-4f9b-8493-f169e3e0b4ff
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3596817568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3596817568
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.388819900
Short name T5
Test name
Test status
Simulation time 23408990556 ps
CPU time 29.48 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206128 kb
Host smart-09e23267-6a69-4df5-95d4-a2ffcb05976c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=388819900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.388819900
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2603927316
Short name T348
Test name
Test status
Simulation time 152804441 ps
CPU time 0.81 seconds
Started Jul 03 04:53:37 PM PDT 24
Finished Jul 03 04:53:39 PM PDT 24
Peak memory 206052 kb
Host smart-cd97e9eb-cd00-452a-b0f3-856d6d2dd56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26039
27316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2603927316
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.332783098
Short name T713
Test name
Test status
Simulation time 142502959 ps
CPU time 0.77 seconds
Started Jul 03 04:53:41 PM PDT 24
Finished Jul 03 04:53:43 PM PDT 24
Peak memory 206128 kb
Host smart-9b079c3e-7b7b-4d26-90be-0e5d2e4559db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33278
3098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.332783098
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.154043117
Short name T1590
Test name
Test status
Simulation time 204437631 ps
CPU time 0.92 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 206096 kb
Host smart-77ec7a93-b087-4144-89ca-c064dd8e8abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
3117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.154043117
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.2295816847
Short name T1900
Test name
Test status
Simulation time 1442940057 ps
CPU time 3.11 seconds
Started Jul 03 04:53:40 PM PDT 24
Finished Jul 03 04:53:44 PM PDT 24
Peak memory 206272 kb
Host smart-4b51b6b3-c493-4640-a110-f8738eab7f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22958
16847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.2295816847
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3378980657
Short name T2467
Test name
Test status
Simulation time 554833985 ps
CPU time 1.5 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 205240 kb
Host smart-fb3ce21d-e1cf-4740-8d83-e0457df8b23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33789
80657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3378980657
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2238139257
Short name T709
Test name
Test status
Simulation time 147259808 ps
CPU time 0.76 seconds
Started Jul 03 04:53:33 PM PDT 24
Finished Jul 03 04:53:35 PM PDT 24
Peak memory 206144 kb
Host smart-cfaf59fa-78d0-4993-ba39-a975f1bf0c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22381
39257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2238139257
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.875510567
Short name T380
Test name
Test status
Simulation time 109239949 ps
CPU time 0.72 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 206080 kb
Host smart-af44b95c-6d7c-489c-9f47-ec294d5ec1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87551
0567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.875510567
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2572840346
Short name T2354
Test name
Test status
Simulation time 949706356 ps
CPU time 2.19 seconds
Started Jul 03 04:53:38 PM PDT 24
Finished Jul 03 04:53:40 PM PDT 24
Peak memory 206288 kb
Host smart-3f859023-2a3f-4b53-bb56-859e80afc56e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25728
40346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2572840346
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2102983861
Short name T1925
Test name
Test status
Simulation time 174213126 ps
CPU time 1.22 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206208 kb
Host smart-71ecef02-259d-4e48-8e06-1bb6f03ada52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21029
83861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2102983861
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3680104985
Short name T2188
Test name
Test status
Simulation time 254929924 ps
CPU time 0.91 seconds
Started Jul 03 04:53:51 PM PDT 24
Finished Jul 03 04:53:52 PM PDT 24
Peak memory 206088 kb
Host smart-5bc63e6f-0fb5-46df-8740-5d07ef117a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36801
04985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3680104985
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3535077509
Short name T1955
Test name
Test status
Simulation time 172571465 ps
CPU time 0.84 seconds
Started Jul 03 04:53:38 PM PDT 24
Finished Jul 03 04:53:39 PM PDT 24
Peak memory 206124 kb
Host smart-c5d4cb88-6aab-4967-9965-78a5b2cac832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35350
77509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3535077509
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2751025701
Short name T1064
Test name
Test status
Simulation time 218910371 ps
CPU time 0.96 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:47 PM PDT 24
Peak memory 205604 kb
Host smart-e8665ede-baf8-450a-8e41-809bdce357c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27510
25701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2751025701
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.599034836
Short name T634
Test name
Test status
Simulation time 7678734551 ps
CPU time 204.42 seconds
Started Jul 03 04:53:35 PM PDT 24
Finished Jul 03 04:57:00 PM PDT 24
Peak memory 206484 kb
Host smart-43312048-1e55-4506-b5e7-e59668ed68d8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=599034836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.599034836
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2217443372
Short name T1483
Test name
Test status
Simulation time 225936427 ps
CPU time 0.9 seconds
Started Jul 03 04:53:39 PM PDT 24
Finished Jul 03 04:53:41 PM PDT 24
Peak memory 206124 kb
Host smart-3f8f702b-54c4-467b-819c-4744c1be89ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22174
43372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2217443372
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.2350751252
Short name T2607
Test name
Test status
Simulation time 23282787243 ps
CPU time 22.81 seconds
Started Jul 03 04:53:37 PM PDT 24
Finished Jul 03 04:54:00 PM PDT 24
Peak memory 206156 kb
Host smart-b75ee64f-5c46-466c-ba3e-b994193476b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23507
51252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.2350751252
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.3066023641
Short name T1200
Test name
Test status
Simulation time 3292874471 ps
CPU time 3.75 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206156 kb
Host smart-4affbf13-97b5-46c2-8d6b-d0486984d013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30660
23641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3066023641
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.2380783586
Short name T485
Test name
Test status
Simulation time 13100914080 ps
CPU time 91.01 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:55:16 PM PDT 24
Peak memory 206472 kb
Host smart-c68983a3-da4c-4b96-ab6f-c756742be5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23807
83586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2380783586
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.731741481
Short name T2667
Test name
Test status
Simulation time 4810177526 ps
CPU time 45.29 seconds
Started Jul 03 04:53:43 PM PDT 24
Finished Jul 03 04:54:29 PM PDT 24
Peak memory 206356 kb
Host smart-efca5fe0-73f0-409d-a97c-fcce5ee902ec
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=731741481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.731741481
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.2253793045
Short name T2256
Test name
Test status
Simulation time 249334629 ps
CPU time 0.88 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206112 kb
Host smart-6dae20a6-2a1e-4e45-8108-2a44cdba88ce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2253793045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.2253793045
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1471518625
Short name T787
Test name
Test status
Simulation time 178634092 ps
CPU time 0.88 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206096 kb
Host smart-3ce38fa6-6ec7-4c78-a6ec-8b3a8b4aa359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14715
18625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1471518625
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.373125104
Short name T1178
Test name
Test status
Simulation time 4604995581 ps
CPU time 42.7 seconds
Started Jul 03 04:53:35 PM PDT 24
Finished Jul 03 04:54:18 PM PDT 24
Peak memory 206444 kb
Host smart-017d97c6-3c52-48c3-be28-43914b795410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37312
5104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.373125104
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.313849781
Short name T1778
Test name
Test status
Simulation time 3928837464 ps
CPU time 28.11 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206356 kb
Host smart-3245f356-5e0f-40d9-84e8-3b3fbf7bd22b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=313849781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.313849781
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3212793465
Short name T410
Test name
Test status
Simulation time 159880453 ps
CPU time 0.77 seconds
Started Jul 03 04:53:35 PM PDT 24
Finished Jul 03 04:53:36 PM PDT 24
Peak memory 206112 kb
Host smart-732a2308-734b-4d3c-a7b2-6f0d5b675332
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3212793465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3212793465
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.956099555
Short name T1482
Test name
Test status
Simulation time 186553984 ps
CPU time 0.82 seconds
Started Jul 03 04:53:33 PM PDT 24
Finished Jul 03 04:53:35 PM PDT 24
Peak memory 206064 kb
Host smart-48d0defa-4c4e-4872-acd5-338d1a160d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95609
9555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.956099555
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3274191278
Short name T1101
Test name
Test status
Simulation time 194436047 ps
CPU time 0.93 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206076 kb
Host smart-60021c4e-c7f4-4912-8746-14627d440c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32741
91278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3274191278
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2165311219
Short name T456
Test name
Test status
Simulation time 213640737 ps
CPU time 0.89 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:53:45 PM PDT 24
Peak memory 206128 kb
Host smart-349ef237-fbed-4958-9cbe-3d97bddc2ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21653
11219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2165311219
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1954886711
Short name T1164
Test name
Test status
Simulation time 151519854 ps
CPU time 0.75 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:53:46 PM PDT 24
Peak memory 206096 kb
Host smart-e1de12f8-0f73-4e0d-bf09-e22c598ab3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548
86711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1954886711
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2940607181
Short name T1757
Test name
Test status
Simulation time 189448535 ps
CPU time 0.85 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 206120 kb
Host smart-262f84d3-5180-480b-8bf1-66f50342a83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29406
07181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2940607181
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.955173224
Short name T199
Test name
Test status
Simulation time 176589108 ps
CPU time 0.89 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 205912 kb
Host smart-dcf9afe5-30ab-4889-a95e-a685796e9019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95517
3224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.955173224
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.1287192290
Short name T539
Test name
Test status
Simulation time 219030364 ps
CPU time 0.93 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:53:45 PM PDT 24
Peak memory 206088 kb
Host smart-c0062fc5-0001-4007-99ae-117ab7572b20
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1287192290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.1287192290
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.563978908
Short name T2509
Test name
Test status
Simulation time 170265436 ps
CPU time 0.84 seconds
Started Jul 03 04:53:35 PM PDT 24
Finished Jul 03 04:53:36 PM PDT 24
Peak memory 205980 kb
Host smart-e1b68a8e-bfad-40b2-95c3-40c3c932cee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56397
8908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.563978908
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1327001581
Short name T2080
Test name
Test status
Simulation time 39843012 ps
CPU time 0.68 seconds
Started Jul 03 04:53:48 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206124 kb
Host smart-baf2f526-b403-4eaf-aa4a-e398bb6169b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13270
01581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1327001581
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2810695691
Short name T94
Test name
Test status
Simulation time 13664135167 ps
CPU time 31.55 seconds
Started Jul 03 04:53:48 PM PDT 24
Finished Jul 03 04:54:21 PM PDT 24
Peak memory 206380 kb
Host smart-a5500c45-e5ee-48b2-a90c-46af1a24c2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28106
95691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2810695691
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2420031800
Short name T2240
Test name
Test status
Simulation time 157154825 ps
CPU time 0.8 seconds
Started Jul 03 04:53:40 PM PDT 24
Finished Jul 03 04:53:42 PM PDT 24
Peak memory 206032 kb
Host smart-eb79e1da-df24-4c9b-b6e5-c647a806b7f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24200
31800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2420031800
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.423208778
Short name T1102
Test name
Test status
Simulation time 227003014 ps
CPU time 0.87 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:47 PM PDT 24
Peak memory 206100 kb
Host smart-44e9dc66-5c61-4f83-9775-d60016a15411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42320
8778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.423208778
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1260430056
Short name T1824
Test name
Test status
Simulation time 253032194 ps
CPU time 0.93 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 206100 kb
Host smart-dec857fc-7a13-4e65-bea8-d74cd05f6f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12604
30056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1260430056
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.31009300
Short name T1396
Test name
Test status
Simulation time 178023684 ps
CPU time 0.88 seconds
Started Jul 03 04:53:37 PM PDT 24
Finished Jul 03 04:53:38 PM PDT 24
Peak memory 206140 kb
Host smart-d30f5636-87e7-4ced-ad40-f89ebbe27a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31009
300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.31009300
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.4045868609
Short name T2396
Test name
Test status
Simulation time 139777492 ps
CPU time 0.8 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206104 kb
Host smart-4cfad68b-1f37-41c3-84a6-a33c15937180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40458
68609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.4045868609
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2953024937
Short name T2716
Test name
Test status
Simulation time 151200272 ps
CPU time 0.82 seconds
Started Jul 03 04:53:49 PM PDT 24
Finished Jul 03 04:53:51 PM PDT 24
Peak memory 206144 kb
Host smart-e7c695ab-7324-4b09-a3ee-fb32d55f2a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29530
24937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2953024937
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.4155036880
Short name T2545
Test name
Test status
Simulation time 148003977 ps
CPU time 0.79 seconds
Started Jul 03 04:53:39 PM PDT 24
Finished Jul 03 04:53:40 PM PDT 24
Peak memory 206000 kb
Host smart-accf815c-805b-453b-8ad9-acccb18b517d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41550
36880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.4155036880
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1528867930
Short name T1154
Test name
Test status
Simulation time 188052033 ps
CPU time 0.9 seconds
Started Jul 03 04:53:43 PM PDT 24
Finished Jul 03 04:53:44 PM PDT 24
Peak memory 206000 kb
Host smart-d0690cbb-501b-4f06-8d6d-24276ee16335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15288
67930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1528867930
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.4289840299
Short name T610
Test name
Test status
Simulation time 5981554909 ps
CPU time 58.75 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:54:44 PM PDT 24
Peak memory 206372 kb
Host smart-4cb4d47b-05b7-4625-9017-fc38eff6b02f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4289840299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.4289840299
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2309167682
Short name T2548
Test name
Test status
Simulation time 255007635 ps
CPU time 0.96 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:52 PM PDT 24
Peak memory 206112 kb
Host smart-8656accb-2201-46b2-8f96-ef1c4cd79d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23091
67682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2309167682
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3697502138
Short name T984
Test name
Test status
Simulation time 202835625 ps
CPU time 0.85 seconds
Started Jul 03 04:53:39 PM PDT 24
Finished Jul 03 04:53:40 PM PDT 24
Peak memory 206096 kb
Host smart-14feb18e-0271-48ce-9883-43034bb5117b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36975
02138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3697502138
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.170761843
Short name T2424
Test name
Test status
Simulation time 1364332419 ps
CPU time 2.65 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206636 kb
Host smart-d87ffc00-1664-4e18-9dad-22777d375d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17076
1843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.170761843
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2458181516
Short name T1013
Test name
Test status
Simulation time 5001587851 ps
CPU time 51.54 seconds
Started Jul 03 04:53:38 PM PDT 24
Finished Jul 03 04:54:30 PM PDT 24
Peak memory 206424 kb
Host smart-3b735fa0-ce35-42b1-94df-aee14d58a0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24581
81516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2458181516
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.394687383
Short name T1938
Test name
Test status
Simulation time 90379476 ps
CPU time 0.83 seconds
Started Jul 03 04:53:43 PM PDT 24
Finished Jul 03 04:53:45 PM PDT 24
Peak memory 206192 kb
Host smart-5df730b2-5cbe-4792-945f-ee707347510d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=394687383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.394687383
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3025088490
Short name T404
Test name
Test status
Simulation time 3835936749 ps
CPU time 5.12 seconds
Started Jul 03 04:53:41 PM PDT 24
Finished Jul 03 04:53:47 PM PDT 24
Peak memory 206168 kb
Host smart-1cddfe62-3715-4591-8c9d-f585da9bca2d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3025088490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.3025088490
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2300278594
Short name T6
Test name
Test status
Simulation time 13323184653 ps
CPU time 12.93 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:59 PM PDT 24
Peak memory 206472 kb
Host smart-1aa39086-2b50-4fa3-8d5f-96c263371062
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2300278594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2300278594
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3819934174
Short name T1224
Test name
Test status
Simulation time 23290582176 ps
CPU time 24.29 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:54:13 PM PDT 24
Peak memory 206388 kb
Host smart-6be7b6b0-f87e-4dc8-ada6-5797af61dbb5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3819934174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.3819934174
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2478951132
Short name T93
Test name
Test status
Simulation time 192885995 ps
CPU time 0.86 seconds
Started Jul 03 04:53:49 PM PDT 24
Finished Jul 03 04:53:51 PM PDT 24
Peak memory 206144 kb
Host smart-3b88aafc-7871-4006-87ce-25b01fa39eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24789
51132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2478951132
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2693123029
Short name T1747
Test name
Test status
Simulation time 159540969 ps
CPU time 0.83 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:53:46 PM PDT 24
Peak memory 206100 kb
Host smart-7e6ac4fa-bf81-412b-a6db-ec7a4abb6709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26931
23029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2693123029
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.530927395
Short name T1599
Test name
Test status
Simulation time 519407568 ps
CPU time 1.51 seconds
Started Jul 03 04:53:42 PM PDT 24
Finished Jul 03 04:53:44 PM PDT 24
Peak memory 206288 kb
Host smart-5043a416-ba18-4c57-8b28-364bde842391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53092
7395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.530927395
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2897494122
Short name T2077
Test name
Test status
Simulation time 335746313 ps
CPU time 1.03 seconds
Started Jul 03 04:53:48 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206136 kb
Host smart-b5b8d1bb-79fd-42dc-9ffc-9104fd4e0996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28974
94122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2897494122
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.224662131
Short name T1453
Test name
Test status
Simulation time 20206650888 ps
CPU time 38.5 seconds
Started Jul 03 04:53:49 PM PDT 24
Finished Jul 03 04:54:28 PM PDT 24
Peak memory 206252 kb
Host smart-6a34e2da-da21-4440-80f9-c876c2f5e852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22466
2131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.224662131
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.3618656622
Short name T1896
Test name
Test status
Simulation time 356270255 ps
CPU time 1.25 seconds
Started Jul 03 04:53:42 PM PDT 24
Finished Jul 03 04:53:44 PM PDT 24
Peak memory 206104 kb
Host smart-b5696692-a8d2-4a91-84f1-1e623c5e5ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36186
56622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.3618656622
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1580611014
Short name T1490
Test name
Test status
Simulation time 138419967 ps
CPU time 0.79 seconds
Started Jul 03 04:53:42 PM PDT 24
Finished Jul 03 04:53:43 PM PDT 24
Peak memory 206108 kb
Host smart-c22f577b-1d0c-4803-ac3e-42a8564f4c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
11014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1580611014
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.4135680192
Short name T1185
Test name
Test status
Simulation time 55370743 ps
CPU time 0.68 seconds
Started Jul 03 04:53:41 PM PDT 24
Finished Jul 03 04:53:42 PM PDT 24
Peak memory 206080 kb
Host smart-320bcf84-9ff9-406f-b11d-c8b8eb82254a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41356
80192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.4135680192
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.920476558
Short name T1542
Test name
Test status
Simulation time 791713286 ps
CPU time 1.84 seconds
Started Jul 03 04:53:36 PM PDT 24
Finished Jul 03 04:53:39 PM PDT 24
Peak memory 206320 kb
Host smart-eaf57286-ddca-442f-8756-39c6cbf44ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92047
6558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.920476558
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1159760080
Short name T1285
Test name
Test status
Simulation time 181659478 ps
CPU time 2.23 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:53:46 PM PDT 24
Peak memory 206376 kb
Host smart-79bd6d06-1c78-40ee-9b57-c9344e335466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11597
60080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1159760080
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2470731417
Short name T710
Test name
Test status
Simulation time 209172600 ps
CPU time 0.9 seconds
Started Jul 03 04:53:48 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206116 kb
Host smart-b266062f-e48e-489a-9e9b-d35c313176ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24707
31417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2470731417
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1420405440
Short name T1003
Test name
Test status
Simulation time 166463876 ps
CPU time 0.8 seconds
Started Jul 03 04:53:48 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206040 kb
Host smart-753ca7cc-6be2-4e97-a425-58a211e6967b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14204
05440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1420405440
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1785346462
Short name T2383
Test name
Test status
Simulation time 245833890 ps
CPU time 0.97 seconds
Started Jul 03 04:53:49 PM PDT 24
Finished Jul 03 04:53:51 PM PDT 24
Peak memory 205920 kb
Host smart-ec6e4d97-d138-48c1-a180-3aac81832dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17853
46462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1785346462
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.388669405
Short name T1577
Test name
Test status
Simulation time 6050506170 ps
CPU time 167.37 seconds
Started Jul 03 04:53:41 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206440 kb
Host smart-a640a038-80cc-479c-8573-b98e1af0c8ba
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=388669405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.388669405
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.1319980195
Short name T830
Test name
Test status
Simulation time 217101479 ps
CPU time 0.9 seconds
Started Jul 03 04:53:49 PM PDT 24
Finished Jul 03 04:53:51 PM PDT 24
Peak memory 206132 kb
Host smart-7d31e06a-97ba-45bd-b5f5-cb56777f5460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13199
80195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1319980195
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.1282834477
Short name T2237
Test name
Test status
Simulation time 23277576311 ps
CPU time 25.44 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206192 kb
Host smart-79871c8d-ba14-42e5-8f4f-4d66e8046c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12828
34477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.1282834477
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.833306885
Short name T1587
Test name
Test status
Simulation time 3288639869 ps
CPU time 3.87 seconds
Started Jul 03 04:53:49 PM PDT 24
Finished Jul 03 04:53:54 PM PDT 24
Peak memory 206208 kb
Host smart-f319f480-324c-4634-b68b-1c39dfed67b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83330
6885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.833306885
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3959337606
Short name T752
Test name
Test status
Simulation time 9004080671 ps
CPU time 238.46 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:57:47 PM PDT 24
Peak memory 206468 kb
Host smart-ab06ae04-b908-4077-ac6f-6ed409703883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39593
37606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3959337606
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.617340116
Short name T2377
Test name
Test status
Simulation time 4235927493 ps
CPU time 115.54 seconds
Started Jul 03 04:53:40 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206384 kb
Host smart-a9059476-34a7-496b-b6d1-004473a4310c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=617340116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.617340116
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2470816708
Short name T464
Test name
Test status
Simulation time 262664822 ps
CPU time 1.01 seconds
Started Jul 03 04:53:39 PM PDT 24
Finished Jul 03 04:53:40 PM PDT 24
Peak memory 206128 kb
Host smart-7104a8d7-74c1-4389-8fdd-65493ad07ca1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2470816708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2470816708
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3455900106
Short name T444
Test name
Test status
Simulation time 192470318 ps
CPU time 0.8 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 206388 kb
Host smart-736bd3e9-4e38-4774-853e-a81ca225eed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34559
00106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3455900106
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.727658389
Short name T1839
Test name
Test status
Simulation time 6115354064 ps
CPU time 57.04 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 206640 kb
Host smart-8ba01278-9585-477f-9173-5ae562d0ebfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72765
8389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.727658389
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1550781880
Short name T2260
Test name
Test status
Simulation time 5338414628 ps
CPU time 147.87 seconds
Started Jul 03 04:53:49 PM PDT 24
Finished Jul 03 04:56:18 PM PDT 24
Peak memory 206396 kb
Host smart-6693235d-030b-480e-8395-5c38a751defc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1550781880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1550781880
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3236928703
Short name T1551
Test name
Test status
Simulation time 187952152 ps
CPU time 0.84 seconds
Started Jul 03 04:53:37 PM PDT 24
Finished Jul 03 04:53:38 PM PDT 24
Peak memory 206132 kb
Host smart-7bfcc237-2f19-4b8c-9967-8737f9f72605
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3236928703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3236928703
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.517045689
Short name T689
Test name
Test status
Simulation time 164665475 ps
CPU time 0.81 seconds
Started Jul 03 04:53:38 PM PDT 24
Finished Jul 03 04:53:40 PM PDT 24
Peak memory 206084 kb
Host smart-0ce935ab-e33f-4482-90e8-367d11b2b71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51704
5689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.517045689
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1664029544
Short name T373
Test name
Test status
Simulation time 174674122 ps
CPU time 0.85 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206132 kb
Host smart-23fc17d8-8964-4294-b807-3a04ab082f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16640
29544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1664029544
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2561291940
Short name T2717
Test name
Test status
Simulation time 204905056 ps
CPU time 0.84 seconds
Started Jul 03 04:53:48 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206112 kb
Host smart-8895ca11-f2df-4534-9bb8-afec163b2c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25612
91940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2561291940
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1092902979
Short name T1934
Test name
Test status
Simulation time 185653492 ps
CPU time 0.89 seconds
Started Jul 03 04:53:43 PM PDT 24
Finished Jul 03 04:53:44 PM PDT 24
Peak memory 206124 kb
Host smart-cddcf621-c15c-4d12-bc04-16b05ca1f441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10929
02979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1092902979
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3065668111
Short name T2421
Test name
Test status
Simulation time 180822250 ps
CPU time 0.83 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:53:45 PM PDT 24
Peak memory 206072 kb
Host smart-07fba186-74e9-4927-b9c1-f7e200e1b53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30656
68111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3065668111
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.116580832
Short name T525
Test name
Test status
Simulation time 215365462 ps
CPU time 0.9 seconds
Started Jul 03 04:53:43 PM PDT 24
Finished Jul 03 04:53:44 PM PDT 24
Peak memory 206000 kb
Host smart-72f7a6a3-c243-400a-8b9e-7b1dc4eb2db7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=116580832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.116580832
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.542432751
Short name T475
Test name
Test status
Simulation time 153227250 ps
CPU time 0.76 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206092 kb
Host smart-f89da04f-8eb4-4c0c-abf0-58ee28f9761b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54243
2751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.542432751
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3775646931
Short name T899
Test name
Test status
Simulation time 49395532 ps
CPU time 0.73 seconds
Started Jul 03 04:53:40 PM PDT 24
Finished Jul 03 04:53:41 PM PDT 24
Peak memory 205996 kb
Host smart-7958cac9-12eb-4ede-b7ec-b106b98edfaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37756
46931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3775646931
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3747340517
Short name T996
Test name
Test status
Simulation time 16333591850 ps
CPU time 39.56 seconds
Started Jul 03 04:53:48 PM PDT 24
Finished Jul 03 04:54:29 PM PDT 24
Peak memory 206408 kb
Host smart-69b3c195-e30f-48e3-9a2c-de4a6f049ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37473
40517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3747340517
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1672993952
Short name T803
Test name
Test status
Simulation time 261844698 ps
CPU time 0.9 seconds
Started Jul 03 04:53:43 PM PDT 24
Finished Jul 03 04:53:45 PM PDT 24
Peak memory 206112 kb
Host smart-68499824-cd05-4ac3-bf4f-2f999f19e2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16729
93952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1672993952
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1588310406
Short name T375
Test name
Test status
Simulation time 172943534 ps
CPU time 0.86 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206088 kb
Host smart-b433eee8-840e-47b2-b540-56f96e027712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15883
10406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1588310406
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1985858667
Short name T732
Test name
Test status
Simulation time 213443987 ps
CPU time 0.83 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206128 kb
Host smart-9eb1790a-500e-40f0-83c9-2c8d16612ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19858
58667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1985858667
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1355473372
Short name T1158
Test name
Test status
Simulation time 262375953 ps
CPU time 0.97 seconds
Started Jul 03 04:53:43 PM PDT 24
Finished Jul 03 04:53:45 PM PDT 24
Peak memory 206052 kb
Host smart-830ecdcb-1657-4aa9-9751-7a9315a16463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13554
73372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1355473372
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1942050632
Short name T1088
Test name
Test status
Simulation time 171303843 ps
CPU time 0.81 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206128 kb
Host smart-be726a99-4323-4c15-805e-6b2f339bc5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19420
50632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1942050632
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3005868130
Short name T1193
Test name
Test status
Simulation time 148264663 ps
CPU time 0.76 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206128 kb
Host smart-9159255c-42f0-427e-b20f-e552214976cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30058
68130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3005868130
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.216274528
Short name T1843
Test name
Test status
Simulation time 152293971 ps
CPU time 0.76 seconds
Started Jul 03 04:53:44 PM PDT 24
Finished Jul 03 04:53:45 PM PDT 24
Peak memory 206108 kb
Host smart-4773abac-98d7-4521-a9a0-dceea43d4036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21627
4528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.216274528
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1996185756
Short name T344
Test name
Test status
Simulation time 233160500 ps
CPU time 0.99 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206084 kb
Host smart-b15cafbe-f59a-4664-9625-5506efe911fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19961
85756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1996185756
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.3877297335
Short name T1883
Test name
Test status
Simulation time 5380219619 ps
CPU time 148.25 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:56:17 PM PDT 24
Peak memory 206440 kb
Host smart-4a69a482-d72b-4ddc-ba00-126c51d5a1ca
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3877297335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.3877297335
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.264666286
Short name T758
Test name
Test status
Simulation time 181969761 ps
CPU time 0.8 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206100 kb
Host smart-ee68ee19-250e-4f27-a9e2-08125e43401c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26466
6286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.264666286
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2068849852
Short name T1371
Test name
Test status
Simulation time 183047110 ps
CPU time 0.81 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:48 PM PDT 24
Peak memory 206108 kb
Host smart-e3fbe713-c727-4ebe-a483-486e42523f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20688
49852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2068849852
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.3831445679
Short name T2313
Test name
Test status
Simulation time 396486735 ps
CPU time 1.12 seconds
Started Jul 03 04:53:41 PM PDT 24
Finished Jul 03 04:53:42 PM PDT 24
Peak memory 206088 kb
Host smart-86c2fccd-44ef-4f5c-b499-3ce2ba18d8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38314
45679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3831445679
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.3824920282
Short name T904
Test name
Test status
Simulation time 4707978693 ps
CPU time 31.86 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206256 kb
Host smart-99f73c52-0572-47d1-982d-f4a032af3b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38249
20282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3824920282
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.4078598553
Short name T1607
Test name
Test status
Simulation time 44730113 ps
CPU time 0.69 seconds
Started Jul 03 04:53:58 PM PDT 24
Finished Jul 03 04:54:00 PM PDT 24
Peak memory 206180 kb
Host smart-c9542336-305f-464d-92f2-1fe134104ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4078598553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.4078598553
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.963779022
Short name T1591
Test name
Test status
Simulation time 3519075386 ps
CPU time 4.07 seconds
Started Jul 03 04:53:48 PM PDT 24
Finished Jul 03 04:53:53 PM PDT 24
Peak memory 206452 kb
Host smart-9779b8ad-2bc1-4804-8929-f8bc3a349bd6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=963779022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.963779022
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.261683529
Short name T1814
Test name
Test status
Simulation time 13357735397 ps
CPU time 14.63 seconds
Started Jul 03 04:53:45 PM PDT 24
Finished Jul 03 04:54:01 PM PDT 24
Peak memory 206200 kb
Host smart-e3251d73-001c-4115-b30a-88ac274e8eb8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=261683529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.261683529
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1828453264
Short name T654
Test name
Test status
Simulation time 23398233000 ps
CPU time 22.63 seconds
Started Jul 03 04:53:51 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 206452 kb
Host smart-5f8720f5-21ad-4386-90d1-68e38c356000
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1828453264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.1828453264
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3168537495
Short name T2349
Test name
Test status
Simulation time 207942775 ps
CPU time 0.87 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206132 kb
Host smart-51dddc8c-2189-42c3-9b52-a200eb51aa21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31685
37495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3168537495
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1150517627
Short name T1255
Test name
Test status
Simulation time 163365071 ps
CPU time 0.83 seconds
Started Jul 03 04:54:00 PM PDT 24
Finished Jul 03 04:54:02 PM PDT 24
Peak memory 206132 kb
Host smart-e4a48130-e1dc-4cf9-8e3a-e4043b967abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11505
17627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1150517627
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.465248126
Short name T2223
Test name
Test status
Simulation time 1530568783 ps
CPU time 3.16 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:52 PM PDT 24
Peak memory 206380 kb
Host smart-c4b66a48-7556-415c-9f30-6518e4688487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46524
8126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.465248126
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.609802870
Short name T1805
Test name
Test status
Simulation time 13682850143 ps
CPU time 26.5 seconds
Started Jul 03 04:53:46 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 206392 kb
Host smart-7a885ec3-82c1-46f1-8ca4-2de9cbccae26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60980
2870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.609802870
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3126107722
Short name T1095
Test name
Test status
Simulation time 410836527 ps
CPU time 1.41 seconds
Started Jul 03 04:53:53 PM PDT 24
Finished Jul 03 04:53:55 PM PDT 24
Peak memory 206084 kb
Host smart-6193a566-fcc9-48b9-beb9-423b1e027bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31261
07722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3126107722
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1785676227
Short name T2049
Test name
Test status
Simulation time 154013482 ps
CPU time 0.81 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:49 PM PDT 24
Peak memory 206080 kb
Host smart-1078cfca-0951-4772-aaf8-4614f14275e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17856
76227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1785676227
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1372413325
Short name T1323
Test name
Test status
Simulation time 30940095 ps
CPU time 0.64 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206108 kb
Host smart-5a015e2c-4564-4000-8b1f-875485e84b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13724
13325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1372413325
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2882855670
Short name T843
Test name
Test status
Simulation time 763907610 ps
CPU time 1.92 seconds
Started Jul 03 04:54:17 PM PDT 24
Finished Jul 03 04:54:19 PM PDT 24
Peak memory 206340 kb
Host smart-e2addeb4-6561-448d-900f-34a69a735bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28828
55670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2882855670
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.4237904193
Short name T2491
Test name
Test status
Simulation time 272951506 ps
CPU time 1.89 seconds
Started Jul 03 04:53:48 PM PDT 24
Finished Jul 03 04:53:51 PM PDT 24
Peak memory 206308 kb
Host smart-2dd70c0a-80fa-4832-a8b0-1974d5302b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42379
04193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.4237904193
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3901304057
Short name T1390
Test name
Test status
Simulation time 243356003 ps
CPU time 0.96 seconds
Started Jul 03 04:53:54 PM PDT 24
Finished Jul 03 04:53:55 PM PDT 24
Peak memory 206084 kb
Host smart-8fbf9e88-2d57-482f-9963-c81b7c5405dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39013
04057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3901304057
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3730568859
Short name T2347
Test name
Test status
Simulation time 170545502 ps
CPU time 0.76 seconds
Started Jul 03 04:53:50 PM PDT 24
Finished Jul 03 04:53:52 PM PDT 24
Peak memory 206088 kb
Host smart-6bc3c100-6912-4f87-ab4d-07663622f259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37305
68859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3730568859
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3614995485
Short name T1237
Test name
Test status
Simulation time 191015662 ps
CPU time 0.86 seconds
Started Jul 03 04:53:50 PM PDT 24
Finished Jul 03 04:53:52 PM PDT 24
Peak memory 206100 kb
Host smart-925b236e-9e13-4769-9eb1-93a91aaeffad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36149
95485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3614995485
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.4102782651
Short name T2517
Test name
Test status
Simulation time 231783567 ps
CPU time 0.83 seconds
Started Jul 03 04:53:52 PM PDT 24
Finished Jul 03 04:53:53 PM PDT 24
Peak memory 206132 kb
Host smart-d18d7084-e0fe-4bbf-860e-61d4256ecced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41027
82651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.4102782651
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1793759099
Short name T854
Test name
Test status
Simulation time 23333438187 ps
CPU time 22.1 seconds
Started Jul 03 04:53:47 PM PDT 24
Finished Jul 03 04:54:11 PM PDT 24
Peak memory 206176 kb
Host smart-e5bf16ae-971a-4781-87b2-4bcc668d08f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17937
59099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1793759099
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1250653523
Short name T2478
Test name
Test status
Simulation time 3330488169 ps
CPU time 4.21 seconds
Started Jul 03 04:53:58 PM PDT 24
Finished Jul 03 04:54:03 PM PDT 24
Peak memory 206064 kb
Host smart-d756e070-379c-443f-9e81-a1f13f94fde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506
53523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1250653523
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.2446367143
Short name T2163
Test name
Test status
Simulation time 9695003911 ps
CPU time 74.15 seconds
Started Jul 03 04:54:02 PM PDT 24
Finished Jul 03 04:55:17 PM PDT 24
Peak memory 206412 kb
Host smart-d090eee6-4a7a-4e97-8cb8-2956b489ae09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24463
67143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.2446367143
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.2058403689
Short name T337
Test name
Test status
Simulation time 3968646776 ps
CPU time 113.04 seconds
Started Jul 03 04:53:53 PM PDT 24
Finished Jul 03 04:55:46 PM PDT 24
Peak memory 206332 kb
Host smart-5e453c0d-9d49-426e-97df-3f4f4008c335
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2058403689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.2058403689
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2801971505
Short name T2480
Test name
Test status
Simulation time 244580425 ps
CPU time 0.87 seconds
Started Jul 03 04:53:56 PM PDT 24
Finished Jul 03 04:53:57 PM PDT 24
Peak memory 206112 kb
Host smart-c528eea9-7f40-4882-ad5d-18c944781c46
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2801971505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2801971505
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3597236975
Short name T2310
Test name
Test status
Simulation time 203241664 ps
CPU time 0.92 seconds
Started Jul 03 04:53:52 PM PDT 24
Finished Jul 03 04:53:53 PM PDT 24
Peak memory 206064 kb
Host smart-7824c11c-c1ef-40ed-bfb3-c4f5bbb27cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35972
36975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3597236975
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3627942717
Short name T1862
Test name
Test status
Simulation time 6564459580 ps
CPU time 61.82 seconds
Started Jul 03 04:53:58 PM PDT 24
Finished Jul 03 04:55:00 PM PDT 24
Peak memory 206304 kb
Host smart-d6e6fc23-1f65-4141-86c8-4c9cc5cb6810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36279
42717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3627942717
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.251133448
Short name T1450
Test name
Test status
Simulation time 4340824758 ps
CPU time 113.38 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:56:09 PM PDT 24
Peak memory 206352 kb
Host smart-6f5780c0-1f6f-4972-b3e7-ad76c0057986
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=251133448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.251133448
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3283339380
Short name T21
Test name
Test status
Simulation time 168222406 ps
CPU time 0.86 seconds
Started Jul 03 04:54:02 PM PDT 24
Finished Jul 03 04:54:03 PM PDT 24
Peak memory 206128 kb
Host smart-13519559-f599-474a-9282-7b15b8c68d79
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3283339380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3283339380
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1991399947
Short name T269
Test name
Test status
Simulation time 151169746 ps
CPU time 0.76 seconds
Started Jul 03 04:53:50 PM PDT 24
Finished Jul 03 04:53:52 PM PDT 24
Peak memory 206112 kb
Host smart-0246d279-7149-4010-a722-02a2f693520b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19913
99947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1991399947
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.919710974
Short name T1269
Test name
Test status
Simulation time 157515752 ps
CPU time 0.85 seconds
Started Jul 03 04:53:54 PM PDT 24
Finished Jul 03 04:53:55 PM PDT 24
Peak memory 206128 kb
Host smart-d3f6d5ec-791b-429d-b0bd-cd6246513d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91971
0974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.919710974
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3293374931
Short name T2719
Test name
Test status
Simulation time 198489635 ps
CPU time 0.89 seconds
Started Jul 03 04:54:14 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206076 kb
Host smart-81631e7d-5dc6-48ea-9b57-da708d861519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32933
74931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3293374931
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2392703905
Short name T2322
Test name
Test status
Simulation time 191896933 ps
CPU time 0.9 seconds
Started Jul 03 04:54:12 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 206092 kb
Host smart-4d088f2b-bad9-4fdc-b588-0704b8315c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23927
03905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2392703905
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.446768204
Short name T809
Test name
Test status
Simulation time 203022851 ps
CPU time 0.81 seconds
Started Jul 03 04:53:53 PM PDT 24
Finished Jul 03 04:53:54 PM PDT 24
Peak memory 206108 kb
Host smart-6dc1e656-ccce-4db7-b2c3-eb4d6bcca813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44676
8204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.446768204
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.4089649301
Short name T1026
Test name
Test status
Simulation time 245141935 ps
CPU time 0.96 seconds
Started Jul 03 04:53:50 PM PDT 24
Finished Jul 03 04:53:52 PM PDT 24
Peak memory 206136 kb
Host smart-a58e1bb6-a134-44d0-9564-0034627ade3c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4089649301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.4089649301
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3712777456
Short name T106
Test name
Test status
Simulation time 205979937 ps
CPU time 0.85 seconds
Started Jul 03 04:53:56 PM PDT 24
Finished Jul 03 04:53:58 PM PDT 24
Peak memory 206084 kb
Host smart-0b44e598-11ed-4968-8926-0cf6631832b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37127
77456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3712777456
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3751332515
Short name T1168
Test name
Test status
Simulation time 68453834 ps
CPU time 0.68 seconds
Started Jul 03 04:54:12 PM PDT 24
Finished Jul 03 04:54:13 PM PDT 24
Peak memory 205992 kb
Host smart-3da91a4d-c38d-4d2b-870c-e217ba4849eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37513
32515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3751332515
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3289790744
Short name T969
Test name
Test status
Simulation time 14923951181 ps
CPU time 30.75 seconds
Started Jul 03 04:54:06 PM PDT 24
Finished Jul 03 04:54:37 PM PDT 24
Peak memory 206404 kb
Host smart-3c676f0a-cea4-4950-a6d8-8cf5c4fa44df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32897
90744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3289790744
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1526274377
Short name T1100
Test name
Test status
Simulation time 208035995 ps
CPU time 0.84 seconds
Started Jul 03 04:54:10 PM PDT 24
Finished Jul 03 04:54:11 PM PDT 24
Peak memory 206132 kb
Host smart-a1e55721-58b5-4ff8-a99b-65e430dc8288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15262
74377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1526274377
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2327765807
Short name T2174
Test name
Test status
Simulation time 164734312 ps
CPU time 0.78 seconds
Started Jul 03 04:54:17 PM PDT 24
Finished Jul 03 04:54:18 PM PDT 24
Peak memory 206144 kb
Host smart-77a5805f-1ae8-4ae4-a656-53224f313132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23277
65807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2327765807
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3711594203
Short name T2621
Test name
Test status
Simulation time 193070871 ps
CPU time 0.81 seconds
Started Jul 03 04:53:50 PM PDT 24
Finished Jul 03 04:53:51 PM PDT 24
Peak memory 206132 kb
Host smart-1588dc38-0072-47f2-8b49-f16ebb974389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37115
94203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3711594203
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2317645603
Short name T1017
Test name
Test status
Simulation time 162090135 ps
CPU time 0.84 seconds
Started Jul 03 04:53:55 PM PDT 24
Finished Jul 03 04:53:56 PM PDT 24
Peak memory 206072 kb
Host smart-71496dc3-f7d2-4120-af42-7bfe615346d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23176
45603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2317645603
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.4133233302
Short name T83
Test name
Test status
Simulation time 144782575 ps
CPU time 0.82 seconds
Started Jul 03 04:54:07 PM PDT 24
Finished Jul 03 04:54:08 PM PDT 24
Peak memory 206088 kb
Host smart-5ad6405c-bce0-4798-bd07-c2a6bf5605b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41332
33302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.4133233302
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.826303328
Short name T2681
Test name
Test status
Simulation time 145092491 ps
CPU time 0.75 seconds
Started Jul 03 04:53:55 PM PDT 24
Finished Jul 03 04:53:56 PM PDT 24
Peak memory 206068 kb
Host smart-480bab72-3bf3-43ed-baf4-8e7dec8c877c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82630
3328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.826303328
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.169525611
Short name T1612
Test name
Test status
Simulation time 155900620 ps
CPU time 0.75 seconds
Started Jul 03 04:54:00 PM PDT 24
Finished Jul 03 04:54:02 PM PDT 24
Peak memory 206092 kb
Host smart-41116f4d-9498-4275-802c-6436676c5e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16952
5611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.169525611
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.238417207
Short name T1317
Test name
Test status
Simulation time 243457496 ps
CPU time 0.92 seconds
Started Jul 03 04:54:07 PM PDT 24
Finished Jul 03 04:54:09 PM PDT 24
Peak memory 206060 kb
Host smart-293ce4de-e696-45b6-a477-60e0c1ed1262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23841
7207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.238417207
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.701135039
Short name T1009
Test name
Test status
Simulation time 5420779187 ps
CPU time 39.82 seconds
Started Jul 03 04:53:55 PM PDT 24
Finished Jul 03 04:54:35 PM PDT 24
Peak memory 206372 kb
Host smart-36c3b4bc-a255-46eb-9163-aa6c8a80675e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=701135039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.701135039
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1628095033
Short name T342
Test name
Test status
Simulation time 222891179 ps
CPU time 0.81 seconds
Started Jul 03 04:53:55 PM PDT 24
Finished Jul 03 04:53:56 PM PDT 24
Peak memory 206132 kb
Host smart-4d18a631-a9b9-483a-998c-a1c829528b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16280
95033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1628095033
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2278167843
Short name T1734
Test name
Test status
Simulation time 153286093 ps
CPU time 0.8 seconds
Started Jul 03 04:54:00 PM PDT 24
Finished Jul 03 04:54:02 PM PDT 24
Peak memory 206132 kb
Host smart-0f08fe4f-73a8-464b-8a06-e2d69dc0915b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22781
67843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2278167843
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3703098294
Short name T1232
Test name
Test status
Simulation time 350458211 ps
CPU time 1.06 seconds
Started Jul 03 04:53:57 PM PDT 24
Finished Jul 03 04:53:59 PM PDT 24
Peak memory 206140 kb
Host smart-4e326271-8a51-4541-85ed-9b75ddee353b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37030
98294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3703098294
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.3727432781
Short name T2141
Test name
Test status
Simulation time 4876336709 ps
CPU time 34.33 seconds
Started Jul 03 04:53:55 PM PDT 24
Finished Jul 03 04:54:30 PM PDT 24
Peak memory 206328 kb
Host smart-bd895b93-ae4c-4b96-a52f-c51bf2b24ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37274
32781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3727432781
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.4086138400
Short name T1570
Test name
Test status
Simulation time 44187317 ps
CPU time 0.72 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:09 PM PDT 24
Peak memory 206112 kb
Host smart-5580b786-f629-4a84-a112-ed85f1436e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4086138400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.4086138400
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1969974065
Short name T2149
Test name
Test status
Simulation time 3806804545 ps
CPU time 4.96 seconds
Started Jul 03 04:53:59 PM PDT 24
Finished Jul 03 04:54:05 PM PDT 24
Peak memory 206396 kb
Host smart-798ef204-114a-43bb-b195-d3017e993769
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1969974065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1969974065
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.4116102497
Short name T578
Test name
Test status
Simulation time 13389464226 ps
CPU time 11.84 seconds
Started Jul 03 04:53:59 PM PDT 24
Finished Jul 03 04:54:11 PM PDT 24
Peak memory 206452 kb
Host smart-c7384454-5cdb-4fd7-9496-c00473a8fe80
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4116102497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.4116102497
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1391707540
Short name T1452
Test name
Test status
Simulation time 23349887154 ps
CPU time 22.92 seconds
Started Jul 03 04:53:57 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206176 kb
Host smart-1e152a5e-7e7e-4c1a-bed8-f827173ec84a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1391707540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1391707540
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1846281703
Short name T562
Test name
Test status
Simulation time 152691875 ps
CPU time 0.81 seconds
Started Jul 03 04:53:55 PM PDT 24
Finished Jul 03 04:53:56 PM PDT 24
Peak memory 206112 kb
Host smart-33cfba8d-e5b8-4fae-bd60-f57244c0d7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18462
81703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1846281703
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.45194230
Short name T2678
Test name
Test status
Simulation time 142353794 ps
CPU time 0.8 seconds
Started Jul 03 04:53:59 PM PDT 24
Finished Jul 03 04:54:01 PM PDT 24
Peak memory 206080 kb
Host smart-76e92b48-7081-4165-8cd8-098fea9a3169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45194
230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.45194230
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.3473504796
Short name T1174
Test name
Test status
Simulation time 217753323 ps
CPU time 0.97 seconds
Started Jul 03 04:53:57 PM PDT 24
Finished Jul 03 04:53:59 PM PDT 24
Peak memory 206104 kb
Host smart-80788148-a3c4-4d67-b91d-e7d5b3d8419a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34735
04796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3473504796
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1821695938
Short name T1183
Test name
Test status
Simulation time 1167487766 ps
CPU time 2.46 seconds
Started Jul 03 04:54:14 PM PDT 24
Finished Jul 03 04:54:17 PM PDT 24
Peak memory 206380 kb
Host smart-dab815b7-bc08-4b9e-9553-7f34e16c60f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18216
95938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1821695938
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1548148273
Short name T201
Test name
Test status
Simulation time 13787429792 ps
CPU time 25.98 seconds
Started Jul 03 04:53:57 PM PDT 24
Finished Jul 03 04:54:24 PM PDT 24
Peak memory 206404 kb
Host smart-967e45f2-0c19-4e3d-a4ea-0dbe53569c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481
48273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1548148273
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3338219669
Short name T663
Test name
Test status
Simulation time 475238442 ps
CPU time 1.34 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:09 PM PDT 24
Peak memory 206128 kb
Host smart-355900f6-d5c3-4cc8-9f76-8a5d0fff9393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33382
19669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3338219669
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3143134636
Short name T2321
Test name
Test status
Simulation time 139377323 ps
CPU time 0.81 seconds
Started Jul 03 04:53:57 PM PDT 24
Finished Jul 03 04:53:58 PM PDT 24
Peak memory 206108 kb
Host smart-0946b043-e153-4725-b19c-c1363fa4f0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31431
34636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3143134636
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.1608500678
Short name T1667
Test name
Test status
Simulation time 125872451 ps
CPU time 0.75 seconds
Started Jul 03 04:54:13 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 206112 kb
Host smart-dd588724-967b-4e5e-9209-6d3430d49ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16085
00678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1608500678
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.65127888
Short name T1983
Test name
Test status
Simulation time 823727816 ps
CPU time 2.15 seconds
Started Jul 03 04:53:54 PM PDT 24
Finished Jul 03 04:53:57 PM PDT 24
Peak memory 206348 kb
Host smart-8e90a1d6-bea0-473e-8889-6256f7c4f0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65127
888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.65127888
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.3404846322
Short name T489
Test name
Test status
Simulation time 174584496 ps
CPU time 1.32 seconds
Started Jul 03 04:53:58 PM PDT 24
Finished Jul 03 04:54:00 PM PDT 24
Peak memory 206388 kb
Host smart-ed7e6d36-ff20-4dba-aa75-e61195a52f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34048
46322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.3404846322
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.886369124
Short name T2611
Test name
Test status
Simulation time 172002250 ps
CPU time 0.84 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:21 PM PDT 24
Peak memory 206084 kb
Host smart-b04fe9c7-76de-467e-a6e8-adad924c0575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88636
9124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.886369124
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1997600692
Short name T1263
Test name
Test status
Simulation time 178899324 ps
CPU time 0.81 seconds
Started Jul 03 04:53:58 PM PDT 24
Finished Jul 03 04:53:59 PM PDT 24
Peak memory 206140 kb
Host smart-df89cc0e-1cbe-4dc8-b4d2-12e444c002a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19976
00692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1997600692
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3374967386
Short name T1978
Test name
Test status
Simulation time 212379458 ps
CPU time 0.95 seconds
Started Jul 03 04:53:58 PM PDT 24
Finished Jul 03 04:53:59 PM PDT 24
Peak memory 206124 kb
Host smart-2215426b-8a5c-438f-956d-3786f3ca4408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33749
67386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3374967386
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.1172815720
Short name T2039
Test name
Test status
Simulation time 5681998811 ps
CPU time 52.86 seconds
Started Jul 03 04:54:09 PM PDT 24
Finished Jul 03 04:55:03 PM PDT 24
Peak memory 206444 kb
Host smart-64412b2a-3b38-4a00-9004-5369afe4f982
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1172815720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.1172815720
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2384917392
Short name T1236
Test name
Test status
Simulation time 157987277 ps
CPU time 0.78 seconds
Started Jul 03 04:54:12 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 205968 kb
Host smart-fb068b61-513a-47c2-8576-e35930b5388b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23849
17392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2384917392
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.1057223984
Short name T882
Test name
Test status
Simulation time 23310345675 ps
CPU time 27.16 seconds
Started Jul 03 04:54:10 PM PDT 24
Finished Jul 03 04:54:38 PM PDT 24
Peak memory 206152 kb
Host smart-3a69b390-232a-4961-b10a-6c9d7c7b5902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10572
23984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.1057223984
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2958745251
Short name T1152
Test name
Test status
Simulation time 3299770235 ps
CPU time 4.18 seconds
Started Jul 03 04:53:56 PM PDT 24
Finished Jul 03 04:54:01 PM PDT 24
Peak memory 206164 kb
Host smart-bfdd693d-6188-4234-a17b-905c4f3ae16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29587
45251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2958745251
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1785452806
Short name T2154
Test name
Test status
Simulation time 10529200134 ps
CPU time 284.07 seconds
Started Jul 03 04:53:57 PM PDT 24
Finished Jul 03 04:58:42 PM PDT 24
Peak memory 206424 kb
Host smart-ad81b415-651b-4882-a644-856eff82a3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17854
52806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1785452806
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1473973249
Short name T1341
Test name
Test status
Simulation time 5391054088 ps
CPU time 143.66 seconds
Started Jul 03 04:54:09 PM PDT 24
Finished Jul 03 04:56:34 PM PDT 24
Peak memory 206384 kb
Host smart-43cc5539-ac43-453e-bee4-6ec0293ecc1d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1473973249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1473973249
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3546301077
Short name T1691
Test name
Test status
Simulation time 233686884 ps
CPU time 0.95 seconds
Started Jul 03 04:53:58 PM PDT 24
Finished Jul 03 04:54:00 PM PDT 24
Peak memory 206120 kb
Host smart-b32e42cf-7b48-4a7d-b1d2-0b3bcea9dc7b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3546301077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3546301077
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1494252272
Short name T1247
Test name
Test status
Simulation time 228743802 ps
CPU time 0.93 seconds
Started Jul 03 04:54:03 PM PDT 24
Finished Jul 03 04:54:04 PM PDT 24
Peak memory 206128 kb
Host smart-d08bc4f8-0f3d-4d3b-be62-e44646c7178b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14942
52272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1494252272
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1263721555
Short name T2413
Test name
Test status
Simulation time 5888466883 ps
CPU time 156.74 seconds
Started Jul 03 04:54:11 PM PDT 24
Finished Jul 03 04:56:48 PM PDT 24
Peak memory 206428 kb
Host smart-b42f01c5-f4f9-4861-a3dd-d19ca1dc971f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12637
21555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1263721555
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1051541747
Short name T2630
Test name
Test status
Simulation time 5889699142 ps
CPU time 52.93 seconds
Started Jul 03 04:54:01 PM PDT 24
Finished Jul 03 04:54:54 PM PDT 24
Peak memory 206392 kb
Host smart-5dd9e788-a2b8-4f2b-90aa-8b2dd293bea6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1051541747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1051541747
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.2682964256
Short name T817
Test name
Test status
Simulation time 193703606 ps
CPU time 0.85 seconds
Started Jul 03 04:54:10 PM PDT 24
Finished Jul 03 04:54:12 PM PDT 24
Peak memory 206128 kb
Host smart-e29eeaca-413c-4975-9078-698324143761
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2682964256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.2682964256
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1106351646
Short name T335
Test name
Test status
Simulation time 164699479 ps
CPU time 0.83 seconds
Started Jul 03 04:54:07 PM PDT 24
Finished Jul 03 04:54:08 PM PDT 24
Peak memory 206112 kb
Host smart-d171000f-3092-4cb4-9e37-80fe062d04e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11063
51646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1106351646
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2772565710
Short name T142
Test name
Test status
Simulation time 181976012 ps
CPU time 0.94 seconds
Started Jul 03 04:53:59 PM PDT 24
Finished Jul 03 04:54:00 PM PDT 24
Peak memory 206144 kb
Host smart-d4aa2127-43a8-4a9f-a6eb-42018cd4d4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27725
65710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2772565710
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1449203937
Short name T91
Test name
Test status
Simulation time 162704759 ps
CPU time 0.86 seconds
Started Jul 03 04:54:12 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 206112 kb
Host smart-783fbb4b-f703-476b-b834-18d98f654e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14492
03937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1449203937
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1147278785
Short name T2184
Test name
Test status
Simulation time 203774654 ps
CPU time 0.87 seconds
Started Jul 03 04:54:05 PM PDT 24
Finished Jul 03 04:54:06 PM PDT 24
Peak memory 206084 kb
Host smart-ae87fb83-e64b-4561-a54a-39f759240198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11472
78785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1147278785
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.641555031
Short name T2344
Test name
Test status
Simulation time 191779109 ps
CPU time 0.93 seconds
Started Jul 03 04:53:59 PM PDT 24
Finished Jul 03 04:54:01 PM PDT 24
Peak memory 206136 kb
Host smart-6d6ac630-8a40-4e2e-a3b6-190b01f84d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64155
5031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.641555031
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.397340558
Short name T205
Test name
Test status
Simulation time 156154229 ps
CPU time 0.91 seconds
Started Jul 03 04:54:02 PM PDT 24
Finished Jul 03 04:54:03 PM PDT 24
Peak memory 206120 kb
Host smart-5bc2915e-61c2-4be4-b4bf-b20c9990c684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39734
0558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.397340558
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.782357316
Short name T620
Test name
Test status
Simulation time 185871076 ps
CPU time 0.91 seconds
Started Jul 03 04:54:07 PM PDT 24
Finished Jul 03 04:54:08 PM PDT 24
Peak memory 206132 kb
Host smart-9279b72e-e338-4007-935c-df69c7b1651b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=782357316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.782357316
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.99608602
Short name T2557
Test name
Test status
Simulation time 201366492 ps
CPU time 0.85 seconds
Started Jul 03 04:54:05 PM PDT 24
Finished Jul 03 04:54:06 PM PDT 24
Peak memory 206128 kb
Host smart-032db909-91ef-45f5-8fab-9fc687d509f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99608
602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.99608602
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3749012381
Short name T1833
Test name
Test status
Simulation time 47710093 ps
CPU time 0.7 seconds
Started Jul 03 04:53:59 PM PDT 24
Finished Jul 03 04:54:00 PM PDT 24
Peak memory 206116 kb
Host smart-b009fcaf-36ee-484d-b899-cffd81441f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37490
12381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3749012381
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3603043554
Short name T2244
Test name
Test status
Simulation time 16026220553 ps
CPU time 34.58 seconds
Started Jul 03 04:54:07 PM PDT 24
Finished Jul 03 04:54:42 PM PDT 24
Peak memory 206436 kb
Host smart-faeb8a2a-0525-4f3a-8dd5-c96fc0147870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36030
43554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3603043554
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3277378452
Short name T1119
Test name
Test status
Simulation time 161153401 ps
CPU time 0.85 seconds
Started Jul 03 04:54:00 PM PDT 24
Finished Jul 03 04:54:02 PM PDT 24
Peak memory 206112 kb
Host smart-37931f8a-b186-494c-82f1-2bb8fdff2c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32773
78452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3277378452
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1045658508
Short name T2518
Test name
Test status
Simulation time 251173894 ps
CPU time 0.92 seconds
Started Jul 03 04:54:16 PM PDT 24
Finished Jul 03 04:54:18 PM PDT 24
Peak memory 206132 kb
Host smart-3b3f73a4-4c55-49b2-ad88-76435a2a1d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10456
58508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1045658508
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2420686806
Short name T1648
Test name
Test status
Simulation time 177076343 ps
CPU time 0.94 seconds
Started Jul 03 04:54:07 PM PDT 24
Finished Jul 03 04:54:08 PM PDT 24
Peak memory 206132 kb
Host smart-570756e1-1c30-46bd-925a-d2af675106bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24206
86806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2420686806
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.3227099984
Short name T901
Test name
Test status
Simulation time 184269126 ps
CPU time 0.81 seconds
Started Jul 03 04:54:00 PM PDT 24
Finished Jul 03 04:54:02 PM PDT 24
Peak memory 206104 kb
Host smart-7b35140d-8707-4414-bc10-690876fe5ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32270
99984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.3227099984
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.541920681
Short name T1370
Test name
Test status
Simulation time 159686039 ps
CPU time 0.76 seconds
Started Jul 03 04:54:00 PM PDT 24
Finished Jul 03 04:54:01 PM PDT 24
Peak memory 206132 kb
Host smart-3fcdf839-4a13-4a5b-b43b-d1035c78df29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54192
0681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.541920681
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1825354186
Short name T390
Test name
Test status
Simulation time 193458905 ps
CPU time 0.82 seconds
Started Jul 03 04:53:58 PM PDT 24
Finished Jul 03 04:53:59 PM PDT 24
Peak memory 206108 kb
Host smart-c90abbfa-0ae1-496a-a338-1443395ac5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18253
54186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1825354186
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2721865248
Short name T2308
Test name
Test status
Simulation time 157973654 ps
CPU time 0.87 seconds
Started Jul 03 04:54:07 PM PDT 24
Finished Jul 03 04:54:08 PM PDT 24
Peak memory 206128 kb
Host smart-6d53ef13-0a6f-4ed5-850b-ef2ff060040b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27218
65248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2721865248
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.715963113
Short name T2238
Test name
Test status
Simulation time 173035878 ps
CPU time 0.82 seconds
Started Jul 03 04:54:03 PM PDT 24
Finished Jul 03 04:54:04 PM PDT 24
Peak memory 206044 kb
Host smart-264c91d9-474b-4b86-af31-ec5e3bf05540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71596
3113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.715963113
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.510918563
Short name T1339
Test name
Test status
Simulation time 5679520556 ps
CPU time 154.82 seconds
Started Jul 03 04:54:00 PM PDT 24
Finished Jul 03 04:56:36 PM PDT 24
Peak memory 206448 kb
Host smart-8a4270da-2488-4ce5-aba8-4101a0169ba5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=510918563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.510918563
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2424382442
Short name T2176
Test name
Test status
Simulation time 181509799 ps
CPU time 0.86 seconds
Started Jul 03 04:54:00 PM PDT 24
Finished Jul 03 04:54:02 PM PDT 24
Peak memory 206084 kb
Host smart-5f60d177-3c4d-46d4-80a4-6722a73158d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
82442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2424382442
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1837406678
Short name T1234
Test name
Test status
Simulation time 160170124 ps
CPU time 0.79 seconds
Started Jul 03 04:54:06 PM PDT 24
Finished Jul 03 04:54:07 PM PDT 24
Peak memory 206092 kb
Host smart-5fa24de2-2bf9-424a-b514-c03c0afcd4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18374
06678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1837406678
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.3291592147
Short name T2694
Test name
Test status
Simulation time 913973922 ps
CPU time 2.26 seconds
Started Jul 03 04:54:04 PM PDT 24
Finished Jul 03 04:54:06 PM PDT 24
Peak memory 206308 kb
Host smart-26e8f6dc-2c60-4163-8ae3-745dde1e5337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32915
92147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.3291592147
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1868807432
Short name T1578
Test name
Test status
Simulation time 3334176021 ps
CPU time 92.3 seconds
Started Jul 03 04:54:16 PM PDT 24
Finished Jul 03 04:55:49 PM PDT 24
Peak memory 206440 kb
Host smart-b5291d96-72de-4bc1-8135-08802516304e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18688
07432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1868807432
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3284398590
Short name T1855
Test name
Test status
Simulation time 72386488 ps
CPU time 0.72 seconds
Started Jul 03 04:51:58 PM PDT 24
Finished Jul 03 04:51:59 PM PDT 24
Peak memory 206176 kb
Host smart-6c296688-da24-4eb0-9986-e2e1cac79da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3284398590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3284398590
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3831422978
Short name T1974
Test name
Test status
Simulation time 3645619340 ps
CPU time 5.08 seconds
Started Jul 03 04:51:43 PM PDT 24
Finished Jul 03 04:51:49 PM PDT 24
Peak memory 206440 kb
Host smart-abb5d75f-b25f-4f13-96b0-819006ce6ac2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3831422978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.3831422978
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2662096123
Short name T1558
Test name
Test status
Simulation time 13386980566 ps
CPU time 11.79 seconds
Started Jul 03 04:51:41 PM PDT 24
Finished Jul 03 04:51:53 PM PDT 24
Peak memory 206448 kb
Host smart-75fc8041-969e-4ba7-8366-29a99509a011
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2662096123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2662096123
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.3621925308
Short name T1913
Test name
Test status
Simulation time 23319423535 ps
CPU time 22.95 seconds
Started Jul 03 04:51:37 PM PDT 24
Finished Jul 03 04:52:01 PM PDT 24
Peak memory 206132 kb
Host smart-88928164-68c1-490a-bcf8-711dc9e55c43
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3621925308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.3621925308
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3182119855
Short name T1205
Test name
Test status
Simulation time 155333412 ps
CPU time 0.77 seconds
Started Jul 03 04:51:39 PM PDT 24
Finished Jul 03 04:51:41 PM PDT 24
Peak memory 206112 kb
Host smart-c6120be9-1a08-48df-884f-6060fd2f9900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31821
19855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3182119855
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2620817628
Short name T71
Test name
Test status
Simulation time 161171328 ps
CPU time 0.79 seconds
Started Jul 03 04:51:37 PM PDT 24
Finished Jul 03 04:51:39 PM PDT 24
Peak memory 206092 kb
Host smart-02f6d20a-38ea-4c4b-8ced-9d4d851e04f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26208
17628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2620817628
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2760086226
Short name T77
Test name
Test status
Simulation time 154566017 ps
CPU time 0.82 seconds
Started Jul 03 04:51:33 PM PDT 24
Finished Jul 03 04:51:35 PM PDT 24
Peak memory 206116 kb
Host smart-90b607f1-8def-47ab-aef0-d752ef68077f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27600
86226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2760086226
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3214002684
Short name T714
Test name
Test status
Simulation time 138439204 ps
CPU time 0.78 seconds
Started Jul 03 04:51:38 PM PDT 24
Finished Jul 03 04:51:39 PM PDT 24
Peak memory 206124 kb
Host smart-8d6d5b8f-5fc9-4fd6-a5dd-7be225780858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32140
02684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3214002684
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.962936011
Short name T196
Test name
Test status
Simulation time 460469108 ps
CPU time 1.31 seconds
Started Jul 03 04:51:38 PM PDT 24
Finished Jul 03 04:51:40 PM PDT 24
Peak memory 206108 kb
Host smart-c3760e6c-5b12-42e3-8f95-909286fdf41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96293
6011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.962936011
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2359655290
Short name T529
Test name
Test status
Simulation time 498686377 ps
CPU time 1.51 seconds
Started Jul 03 04:51:38 PM PDT 24
Finished Jul 03 04:51:41 PM PDT 24
Peak memory 206128 kb
Host smart-9e5ed24f-f58b-44be-9a50-bd4a6b62b5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23596
55290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2359655290
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.2304645002
Short name T1985
Test name
Test status
Simulation time 7798881778 ps
CPU time 14.64 seconds
Started Jul 03 04:51:41 PM PDT 24
Finished Jul 03 04:51:56 PM PDT 24
Peak memory 206388 kb
Host smart-1ab3b437-bb9a-4994-bee1-2975eeb5301a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23046
45002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.2304645002
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.800822480
Short name T1187
Test name
Test status
Simulation time 397178610 ps
CPU time 1.37 seconds
Started Jul 03 04:51:56 PM PDT 24
Finished Jul 03 04:51:58 PM PDT 24
Peak memory 206100 kb
Host smart-b4660ece-8429-481a-aae7-b6da4d2d76a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80082
2480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.800822480
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2911617786
Short name T2390
Test name
Test status
Simulation time 170969924 ps
CPU time 0.8 seconds
Started Jul 03 04:51:38 PM PDT 24
Finished Jul 03 04:51:40 PM PDT 24
Peak memory 206128 kb
Host smart-f8a81468-553e-4631-8c5e-c8e9346417dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29116
17786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2911617786
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1983195098
Short name T730
Test name
Test status
Simulation time 31921836 ps
CPU time 0.64 seconds
Started Jul 03 04:51:52 PM PDT 24
Finished Jul 03 04:51:53 PM PDT 24
Peak memory 206092 kb
Host smart-a0d16f50-88fb-4bf7-9de7-62fcead5f407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19831
95098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1983195098
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1119719791
Short name T513
Test name
Test status
Simulation time 904744673 ps
CPU time 2.16 seconds
Started Jul 03 04:51:43 PM PDT 24
Finished Jul 03 04:51:45 PM PDT 24
Peak memory 206336 kb
Host smart-04f0f4c2-82ed-497c-9861-22cb104b5bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11197
19791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1119719791
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.310088285
Short name T2044
Test name
Test status
Simulation time 166719832 ps
CPU time 1.67 seconds
Started Jul 03 04:51:39 PM PDT 24
Finished Jul 03 04:51:46 PM PDT 24
Peak memory 206316 kb
Host smart-226db1d5-aa37-4f85-bc16-2d062360388c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31008
8285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.310088285
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1399556673
Short name T406
Test name
Test status
Simulation time 114236846506 ps
CPU time 161.34 seconds
Started Jul 03 04:51:40 PM PDT 24
Finished Jul 03 04:54:22 PM PDT 24
Peak memory 206344 kb
Host smart-5e25f198-fe98-4915-8cdc-c551979b91e7
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1399556673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1399556673
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.3205575226
Short name T1540
Test name
Test status
Simulation time 95229348944 ps
CPU time 147.76 seconds
Started Jul 03 04:51:42 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206388 kb
Host smart-7dc974b2-2c3e-4e65-abb2-2637f24f7632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205575226 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.3205575226
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.1297646629
Short name T1910
Test name
Test status
Simulation time 113109104791 ps
CPU time 159.81 seconds
Started Jul 03 04:51:53 PM PDT 24
Finished Jul 03 04:54:33 PM PDT 24
Peak memory 206360 kb
Host smart-4beb1af5-5a77-4f11-89ab-20b2de0a1391
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1297646629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1297646629
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.883616724
Short name T1524
Test name
Test status
Simulation time 120931054673 ps
CPU time 175.69 seconds
Started Jul 03 04:51:38 PM PDT 24
Finished Jul 03 04:54:35 PM PDT 24
Peak memory 206308 kb
Host smart-19ce4db4-f316-4a12-985d-627dbe477b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883616724 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.883616724
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.1061070625
Short name T1126
Test name
Test status
Simulation time 101148020611 ps
CPU time 139 seconds
Started Jul 03 04:51:36 PM PDT 24
Finished Jul 03 04:53:56 PM PDT 24
Peak memory 206376 kb
Host smart-355c95fe-a175-4a3a-a5f0-f8742bc5c053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10610
70625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.1061070625
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2914045977
Short name T1295
Test name
Test status
Simulation time 171927043 ps
CPU time 0.92 seconds
Started Jul 03 04:51:40 PM PDT 24
Finished Jul 03 04:51:42 PM PDT 24
Peak memory 206116 kb
Host smart-b28c4ac1-f3bc-413b-8123-62fc98c516f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29140
45977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2914045977
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2179814398
Short name T2501
Test name
Test status
Simulation time 151996679 ps
CPU time 0.78 seconds
Started Jul 03 04:51:50 PM PDT 24
Finished Jul 03 04:51:51 PM PDT 24
Peak memory 206120 kb
Host smart-16c5c57b-9b0c-47b1-b38a-77a78363d17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21798
14398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2179814398
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3384574284
Short name T2609
Test name
Test status
Simulation time 162396719 ps
CPU time 0.82 seconds
Started Jul 03 04:51:48 PM PDT 24
Finished Jul 03 04:51:49 PM PDT 24
Peak memory 206132 kb
Host smart-76d819ee-61de-48de-83a1-f78cf7005321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33845
74284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3384574284
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.213590975
Short name T2702
Test name
Test status
Simulation time 7099571144 ps
CPU time 52.37 seconds
Started Jul 03 04:51:53 PM PDT 24
Finished Jul 03 04:52:46 PM PDT 24
Peak memory 206372 kb
Host smart-b70eb7d6-6d59-4fbb-8e83-6c6bc478fc69
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=213590975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.213590975
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1029836333
Short name T983
Test name
Test status
Simulation time 228635876 ps
CPU time 0.9 seconds
Started Jul 03 04:51:48 PM PDT 24
Finished Jul 03 04:51:49 PM PDT 24
Peak memory 206136 kb
Host smart-e40d2adc-44f3-4375-a5ab-80adc81f6a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10298
36333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1029836333
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.224469828
Short name T2534
Test name
Test status
Simulation time 23353868359 ps
CPU time 23.9 seconds
Started Jul 03 04:51:44 PM PDT 24
Finished Jul 03 04:52:09 PM PDT 24
Peak memory 206176 kb
Host smart-115b51ca-b014-4896-8b41-24734a1e6210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22446
9828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.224469828
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3848737143
Short name T492
Test name
Test status
Simulation time 3275215780 ps
CPU time 3.99 seconds
Started Jul 03 04:51:45 PM PDT 24
Finished Jul 03 04:51:50 PM PDT 24
Peak memory 206144 kb
Host smart-ad39f562-3699-4d5d-91bc-2c1bfea89a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38487
37143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3848737143
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2378491954
Short name T49
Test name
Test status
Simulation time 7437951219 ps
CPU time 193.76 seconds
Started Jul 03 04:51:51 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206424 kb
Host smart-efdfb7af-7d0c-47f4-b0a2-59e0cfb0173f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23784
91954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2378491954
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1064896039
Short name T2098
Test name
Test status
Simulation time 3878136514 ps
CPU time 26.35 seconds
Started Jul 03 04:51:41 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206436 kb
Host smart-16bed6ae-dfc3-4bf6-95a6-f90d9a93af9e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1064896039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1064896039
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1128271980
Short name T1321
Test name
Test status
Simulation time 237526057 ps
CPU time 0.91 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:52:01 PM PDT 24
Peak memory 206116 kb
Host smart-edd38f4d-c9d9-4c99-9331-5fc97b2b0249
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1128271980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1128271980
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1957813560
Short name T968
Test name
Test status
Simulation time 240062207 ps
CPU time 0.9 seconds
Started Jul 03 04:51:56 PM PDT 24
Finished Jul 03 04:51:58 PM PDT 24
Peak memory 206080 kb
Host smart-0aae1d57-c724-4428-98bd-55d12dec93ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19578
13560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1957813560
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.3864037536
Short name T524
Test name
Test status
Simulation time 5298397273 ps
CPU time 142.76 seconds
Started Jul 03 04:51:58 PM PDT 24
Finished Jul 03 04:54:21 PM PDT 24
Peak memory 206388 kb
Host smart-f897aa26-2ef2-474f-b8b4-521f729c171f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38640
37536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.3864037536
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1173825564
Short name T2665
Test name
Test status
Simulation time 4208346087 ps
CPU time 111.09 seconds
Started Jul 03 04:51:50 PM PDT 24
Finished Jul 03 04:53:42 PM PDT 24
Peak memory 206332 kb
Host smart-3a46f711-28b6-4e4f-b0a2-0b1411ceddf5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1173825564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1173825564
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1694917746
Short name T1235
Test name
Test status
Simulation time 153230027 ps
CPU time 0.82 seconds
Started Jul 03 04:51:58 PM PDT 24
Finished Jul 03 04:52:00 PM PDT 24
Peak memory 206132 kb
Host smart-49b5d697-9e57-4636-8cd5-5a6964ea2ba1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1694917746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1694917746
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2566869977
Short name T1434
Test name
Test status
Simulation time 177194409 ps
CPU time 0.88 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206052 kb
Host smart-b9048bba-7698-4a20-9ac0-3f46c8163023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25668
69977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2566869977
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1161658310
Short name T1854
Test name
Test status
Simulation time 175731789 ps
CPU time 0.87 seconds
Started Jul 03 04:51:50 PM PDT 24
Finished Jul 03 04:51:51 PM PDT 24
Peak memory 206072 kb
Host smart-e96f2d57-0cbb-4bfd-9ad2-bc4d1ae3f8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11616
58310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1161658310
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2318106006
Short name T2378
Test name
Test status
Simulation time 196654027 ps
CPU time 0.91 seconds
Started Jul 03 04:51:51 PM PDT 24
Finished Jul 03 04:51:52 PM PDT 24
Peak memory 206080 kb
Host smart-ceea8815-4c03-4342-8f0a-047de9c007de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23181
06006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2318106006
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3612868547
Short name T1460
Test name
Test status
Simulation time 238159111 ps
CPU time 0.92 seconds
Started Jul 03 04:51:52 PM PDT 24
Finished Jul 03 04:51:54 PM PDT 24
Peak memory 206096 kb
Host smart-19f0a2af-3aa9-4853-ba41-0e6a3fc749a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36128
68547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3612868547
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2469457182
Short name T945
Test name
Test status
Simulation time 152026716 ps
CPU time 0.75 seconds
Started Jul 03 04:51:50 PM PDT 24
Finished Jul 03 04:51:51 PM PDT 24
Peak memory 206020 kb
Host smart-c8982c49-7c26-4cf9-b334-015e7f973d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24694
57182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2469457182
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.548074269
Short name T2353
Test name
Test status
Simulation time 225350861 ps
CPU time 1.02 seconds
Started Jul 03 04:51:50 PM PDT 24
Finished Jul 03 04:51:52 PM PDT 24
Peak memory 206060 kb
Host smart-b54fad21-d2c0-41db-a2f6-29367742a519
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=548074269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.548074269
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.2185401348
Short name T237
Test name
Test status
Simulation time 177972526 ps
CPU time 0.82 seconds
Started Jul 03 04:51:52 PM PDT 24
Finished Jul 03 04:51:53 PM PDT 24
Peak memory 206116 kb
Host smart-195925e5-2397-4b76-a7c4-5adab395ef4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21854
01348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.2185401348
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3234912664
Short name T2672
Test name
Test status
Simulation time 169701285 ps
CPU time 0.77 seconds
Started Jul 03 04:51:55 PM PDT 24
Finished Jul 03 04:51:56 PM PDT 24
Peak memory 206108 kb
Host smart-11d9805f-0528-4827-bb39-ffef62f54a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32349
12664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3234912664
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.751268321
Short name T2197
Test name
Test status
Simulation time 46171775 ps
CPU time 0.73 seconds
Started Jul 03 04:52:01 PM PDT 24
Finished Jul 03 04:52:02 PM PDT 24
Peak memory 206116 kb
Host smart-b3582ff0-8db9-4924-af6a-3f00e686485c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75126
8321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.751268321
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.420768353
Short name T102
Test name
Test status
Simulation time 24767885385 ps
CPU time 62.8 seconds
Started Jul 03 04:51:50 PM PDT 24
Finished Jul 03 04:52:53 PM PDT 24
Peak memory 206456 kb
Host smart-cf1693a2-8f5b-459a-afdd-6e1961aca5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42076
8353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.420768353
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2703381646
Short name T1109
Test name
Test status
Simulation time 163415698 ps
CPU time 0.83 seconds
Started Jul 03 04:51:58 PM PDT 24
Finished Jul 03 04:52:00 PM PDT 24
Peak memory 206108 kb
Host smart-ad2c7b44-141e-4b06-b7a2-44387bae1343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27033
81646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2703381646
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3966588446
Short name T2558
Test name
Test status
Simulation time 176484199 ps
CPU time 0.83 seconds
Started Jul 03 04:51:49 PM PDT 24
Finished Jul 03 04:51:51 PM PDT 24
Peak memory 206132 kb
Host smart-d2c544d8-c8d3-4be7-8323-5dd0fbffd9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39665
88446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3966588446
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3297338100
Short name T470
Test name
Test status
Simulation time 5313085992 ps
CPU time 127.59 seconds
Started Jul 03 04:52:01 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206440 kb
Host smart-e4eb2a95-0626-4753-b94b-0972dca33e01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3297338100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3297338100
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1361189831
Short name T716
Test name
Test status
Simulation time 9378457183 ps
CPU time 142.98 seconds
Started Jul 03 04:52:05 PM PDT 24
Finished Jul 03 04:54:29 PM PDT 24
Peak memory 206432 kb
Host smart-6c179734-3224-4430-8ad4-ec2f4ae9693e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1361189831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1361189831
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3507114665
Short name T1765
Test name
Test status
Simulation time 19917992834 ps
CPU time 461.21 seconds
Started Jul 03 04:51:47 PM PDT 24
Finished Jul 03 04:59:29 PM PDT 24
Peak memory 206480 kb
Host smart-a56393d3-3e44-4b0a-954c-6fa089cf77aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3507114665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3507114665
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1661443482
Short name T2081
Test name
Test status
Simulation time 169469525 ps
CPU time 0.83 seconds
Started Jul 03 04:51:55 PM PDT 24
Finished Jul 03 04:51:56 PM PDT 24
Peak memory 206088 kb
Host smart-ebe19100-4e88-47ec-b52a-296b93c4e4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16614
43482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1661443482
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1044568588
Short name T2242
Test name
Test status
Simulation time 160660826 ps
CPU time 0.81 seconds
Started Jul 03 04:52:01 PM PDT 24
Finished Jul 03 04:52:02 PM PDT 24
Peak memory 206128 kb
Host smart-1f942492-7a83-4e9b-8bf7-815587225bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10445
68588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1044568588
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1379626793
Short name T57
Test name
Test status
Simulation time 185447756 ps
CPU time 0.84 seconds
Started Jul 03 04:51:54 PM PDT 24
Finished Jul 03 04:51:56 PM PDT 24
Peak memory 206064 kb
Host smart-7baf352a-d477-487a-a91c-fdfd14003d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13796
26793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1379626793
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.2882558552
Short name T2623
Test name
Test status
Simulation time 151481783 ps
CPU time 0.79 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206128 kb
Host smart-cc6d0eaf-86fb-4c2d-b34c-43e77f2f724d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28825
58552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2882558552
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.4259609447
Short name T216
Test name
Test status
Simulation time 357620028 ps
CPU time 1.22 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:52:02 PM PDT 24
Peak memory 224028 kb
Host smart-b00bd1a7-aa23-4c7e-a7ae-f89972a1f222
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4259609447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.4259609447
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1686017292
Short name T67
Test name
Test status
Simulation time 410908751 ps
CPU time 1.25 seconds
Started Jul 03 04:51:51 PM PDT 24
Finished Jul 03 04:51:52 PM PDT 24
Peak memory 206132 kb
Host smart-400168c3-7789-475e-b64f-c13c343c17b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16860
17292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1686017292
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2318608092
Short name T189
Test name
Test status
Simulation time 171139720 ps
CPU time 0.89 seconds
Started Jul 03 04:51:49 PM PDT 24
Finished Jul 03 04:51:50 PM PDT 24
Peak memory 206092 kb
Host smart-8218c585-b60d-4724-aba5-fc0c7f5b6eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23186
08092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2318608092
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.724668820
Short name T1438
Test name
Test status
Simulation time 152796380 ps
CPU time 0.78 seconds
Started Jul 03 04:51:50 PM PDT 24
Finished Jul 03 04:51:51 PM PDT 24
Peak memory 206124 kb
Host smart-17071975-626b-4f41-b26d-0f793d12eac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72466
8820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.724668820
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.4048675575
Short name T556
Test name
Test status
Simulation time 144569964 ps
CPU time 0.78 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206100 kb
Host smart-8cf969ef-16c3-4fa7-b926-ff405ef6dd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40486
75575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.4048675575
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2175524707
Short name T1792
Test name
Test status
Simulation time 217966126 ps
CPU time 0.97 seconds
Started Jul 03 04:51:49 PM PDT 24
Finished Jul 03 04:51:50 PM PDT 24
Peak memory 206100 kb
Host smart-ec0faad1-181c-46b1-a153-d9a8340aebf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21755
24707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2175524707
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3581173557
Short name T98
Test name
Test status
Simulation time 4376701204 ps
CPU time 122.02 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:54:02 PM PDT 24
Peak memory 206404 kb
Host smart-af097032-f2f5-415e-bd72-cfa4bfa58881
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3581173557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3581173557
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2195480255
Short name T2596
Test name
Test status
Simulation time 185359176 ps
CPU time 0.85 seconds
Started Jul 03 04:51:53 PM PDT 24
Finished Jul 03 04:51:54 PM PDT 24
Peak memory 206132 kb
Host smart-9f4f82a1-ce94-41f4-ab28-1c46d7a51989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21954
80255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2195480255
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3841493363
Short name T912
Test name
Test status
Simulation time 161351111 ps
CPU time 0.83 seconds
Started Jul 03 04:51:56 PM PDT 24
Finished Jul 03 04:51:57 PM PDT 24
Peak memory 206116 kb
Host smart-5fb414d8-8f5b-4323-bcc4-073ca818bf3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38414
93363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3841493363
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.1225720038
Short name T433
Test name
Test status
Simulation time 224768763 ps
CPU time 0.86 seconds
Started Jul 03 04:51:46 PM PDT 24
Finished Jul 03 04:51:48 PM PDT 24
Peak memory 206040 kb
Host smart-5d35c810-90d0-4231-8ebb-2471b85161ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12257
20038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1225720038
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2650533238
Short name T434
Test name
Test status
Simulation time 5088807581 ps
CPU time 35.01 seconds
Started Jul 03 04:51:55 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206312 kb
Host smart-e48b4d27-7800-4713-acb1-517c3087ce28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26505
33238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2650533238
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3652316132
Short name T1588
Test name
Test status
Simulation time 39339649 ps
CPU time 0.7 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:21 PM PDT 24
Peak memory 206192 kb
Host smart-01de51a9-d117-4889-a29e-ff93fa5724cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3652316132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3652316132
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.659940489
Short name T1383
Test name
Test status
Simulation time 13332816541 ps
CPU time 12.5 seconds
Started Jul 03 04:54:14 PM PDT 24
Finished Jul 03 04:54:27 PM PDT 24
Peak memory 206140 kb
Host smart-fa4ba835-2fc5-4ae0-8407-3ad27112a196
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=659940489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.659940489
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3974162285
Short name T2463
Test name
Test status
Simulation time 23392050646 ps
CPU time 29.94 seconds
Started Jul 03 04:54:12 PM PDT 24
Finished Jul 03 04:54:43 PM PDT 24
Peak memory 206016 kb
Host smart-9d7a95ec-7c5e-4ae3-ba8a-da701332b6e6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3974162285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.3974162285
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.623407341
Short name T1393
Test name
Test status
Simulation time 179174501 ps
CPU time 0.8 seconds
Started Jul 03 04:54:06 PM PDT 24
Finished Jul 03 04:54:07 PM PDT 24
Peak memory 206140 kb
Host smart-7d47391e-de3f-44e7-a8dc-5453c14d5eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62340
7341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.623407341
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1000588893
Short name T2589
Test name
Test status
Simulation time 144087734 ps
CPU time 0.83 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:09 PM PDT 24
Peak memory 206108 kb
Host smart-9ded7c22-7f22-4c0b-8945-609693bc254c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10005
88893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1000588893
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2063297229
Short name T1838
Test name
Test status
Simulation time 417100158 ps
CPU time 1.27 seconds
Started Jul 03 04:54:14 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206124 kb
Host smart-e817201d-38c8-48b7-b8b3-99deceb684c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20632
97229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2063297229
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.841812890
Short name T2084
Test name
Test status
Simulation time 976507841 ps
CPU time 2.53 seconds
Started Jul 03 04:54:11 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 206284 kb
Host smart-f8a8392a-7666-4541-b52c-c9c36355182e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84181
2890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.841812890
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3347198156
Short name T457
Test name
Test status
Simulation time 14625010104 ps
CPU time 28.01 seconds
Started Jul 03 04:54:09 PM PDT 24
Finished Jul 03 04:54:37 PM PDT 24
Peak memory 206420 kb
Host smart-23e8b20a-47e4-4745-8586-390d4a53b067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33471
98156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3347198156
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3127740948
Short name T343
Test name
Test status
Simulation time 420070167 ps
CPU time 1.25 seconds
Started Jul 03 04:54:13 PM PDT 24
Finished Jul 03 04:54:15 PM PDT 24
Peak memory 206072 kb
Host smart-9cc74c8e-9f31-4d38-9a34-ae7e55488a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31277
40948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3127740948
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.4031391167
Short name T1149
Test name
Test status
Simulation time 183596271 ps
CPU time 0.86 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206092 kb
Host smart-cf2b97ba-b219-4976-a291-cefeb64f67d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40313
91167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.4031391167
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.306551713
Short name T2062
Test name
Test status
Simulation time 32903592 ps
CPU time 0.68 seconds
Started Jul 03 04:54:10 PM PDT 24
Finished Jul 03 04:54:12 PM PDT 24
Peak memory 206124 kb
Host smart-1be64e5e-f752-4242-a3bf-9717f879b8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30655
1713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.306551713
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3129278452
Short name T1921
Test name
Test status
Simulation time 907437184 ps
CPU time 2.17 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206376 kb
Host smart-20646eb0-33ae-4464-807d-3a1fe7144a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31292
78452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3129278452
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.4206118971
Short name T1462
Test name
Test status
Simulation time 178012148 ps
CPU time 1.82 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:21 PM PDT 24
Peak memory 206324 kb
Host smart-0a139fde-0b7a-4fce-86bf-78070a9c65f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42061
18971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.4206118971
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1739401420
Short name T1335
Test name
Test status
Simulation time 193288165 ps
CPU time 0.85 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206116 kb
Host smart-f6b0f671-745f-4183-9303-5857667f7a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17394
01420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1739401420
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1826372777
Short name T2414
Test name
Test status
Simulation time 138752107 ps
CPU time 0.74 seconds
Started Jul 03 04:54:13 PM PDT 24
Finished Jul 03 04:54:15 PM PDT 24
Peak memory 206100 kb
Host smart-76b26613-0b6e-420f-a74a-e07d3875fb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
72777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1826372777
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1228151294
Short name T1400
Test name
Test status
Simulation time 159390582 ps
CPU time 0.82 seconds
Started Jul 03 04:54:02 PM PDT 24
Finished Jul 03 04:54:03 PM PDT 24
Peak memory 206124 kb
Host smart-e091577b-d71c-4645-b926-26ffdc8de529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12281
51294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1228151294
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.3248384170
Short name T244
Test name
Test status
Simulation time 5083196600 ps
CPU time 33.91 seconds
Started Jul 03 04:54:13 PM PDT 24
Finished Jul 03 04:54:47 PM PDT 24
Peak memory 206408 kb
Host smart-746ccd53-cc6e-4c6a-92a8-6a192f51412f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3248384170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.3248384170
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.966337246
Short name T2095
Test name
Test status
Simulation time 195976247 ps
CPU time 0.83 seconds
Started Jul 03 04:54:18 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206132 kb
Host smart-9741ba2f-e860-4249-a9c6-56ce432c31b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96633
7246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.966337246
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.153976477
Short name T2241
Test name
Test status
Simulation time 23365369859 ps
CPU time 27.53 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:35 PM PDT 24
Peak memory 206148 kb
Host smart-c1eb2dbf-bb14-47ba-a1f0-31107cab721a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15397
6477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.153976477
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.286569798
Short name T2373
Test name
Test status
Simulation time 3346866326 ps
CPU time 4.08 seconds
Started Jul 03 04:54:06 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206188 kb
Host smart-5c79593a-cba6-4c39-9b74-95cb135fc9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28656
9798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.286569798
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.976509378
Short name T1829
Test name
Test status
Simulation time 7668049965 ps
CPU time 216.9 seconds
Started Jul 03 04:54:09 PM PDT 24
Finished Jul 03 04:57:46 PM PDT 24
Peak memory 206404 kb
Host smart-827ffc1b-859c-4e3d-a9fe-01aefe697fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97650
9378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.976509378
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.218812191
Short name T2264
Test name
Test status
Simulation time 2785331312 ps
CPU time 20.6 seconds
Started Jul 03 04:54:04 PM PDT 24
Finished Jul 03 04:54:25 PM PDT 24
Peak memory 206348 kb
Host smart-52c24887-c122-4033-b8f7-7a3347812956
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=218812191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.218812191
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.3369126820
Short name T1159
Test name
Test status
Simulation time 279267271 ps
CPU time 0.99 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:17 PM PDT 24
Peak memory 206032 kb
Host smart-91a172b9-716b-4909-9e92-239f910b57d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3369126820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3369126820
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.69893256
Short name T378
Test name
Test status
Simulation time 187491574 ps
CPU time 0.85 seconds
Started Jul 03 04:54:05 PM PDT 24
Finished Jul 03 04:54:06 PM PDT 24
Peak memory 206072 kb
Host smart-d0d9ad4c-380a-41d8-be40-c4680169d507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69893
256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.69893256
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3297415633
Short name T1089
Test name
Test status
Simulation time 3319346878 ps
CPU time 91.49 seconds
Started Jul 03 04:54:10 PM PDT 24
Finished Jul 03 04:55:43 PM PDT 24
Peak memory 206348 kb
Host smart-6cafec81-c826-4778-9659-fc6f9a142762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32974
15633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3297415633
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.661869934
Short name T462
Test name
Test status
Simulation time 5420278947 ps
CPU time 145.94 seconds
Started Jul 03 04:54:12 PM PDT 24
Finished Jul 03 04:56:39 PM PDT 24
Peak memory 206408 kb
Host smart-50c8fa36-3b51-40f0-b13c-b3c3f177c1c3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=661869934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.661869934
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.3311082492
Short name T1016
Test name
Test status
Simulation time 151719295 ps
CPU time 0.8 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:17 PM PDT 24
Peak memory 206128 kb
Host smart-5ec25522-2f31-4671-8be4-5242d517828c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3311082492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.3311082492
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3434500176
Short name T2470
Test name
Test status
Simulation time 242263395 ps
CPU time 0.85 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:09 PM PDT 24
Peak memory 206036 kb
Host smart-e314d3db-88e7-40bf-9616-1285d5944533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34345
00176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3434500176
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3274138863
Short name T125
Test name
Test status
Simulation time 190462007 ps
CPU time 0.87 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:09 PM PDT 24
Peak memory 206080 kb
Host smart-b624d982-23c8-4620-b6b8-2e631dd136f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32741
38863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3274138863
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3489543112
Short name T362
Test name
Test status
Simulation time 174263008 ps
CPU time 0.82 seconds
Started Jul 03 04:54:11 PM PDT 24
Finished Jul 03 04:54:12 PM PDT 24
Peak memory 206088 kb
Host smart-8b65d2b2-df27-4f9a-aaa0-e54937b70c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34895
43112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3489543112
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1816294345
Short name T2283
Test name
Test status
Simulation time 228941786 ps
CPU time 0.88 seconds
Started Jul 03 04:54:10 PM PDT 24
Finished Jul 03 04:54:11 PM PDT 24
Peak memory 206120 kb
Host smart-4c7ae90b-6f20-4d73-8c0b-ab531078c776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18162
94345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1816294345
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2162627221
Short name T683
Test name
Test status
Simulation time 172295291 ps
CPU time 0.79 seconds
Started Jul 03 04:54:16 PM PDT 24
Finished Jul 03 04:54:17 PM PDT 24
Peak memory 206108 kb
Host smart-63530a14-4895-41b8-a523-cccfad0194ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21626
27221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2162627221
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3983653050
Short name T453
Test name
Test status
Simulation time 151609708 ps
CPU time 0.77 seconds
Started Jul 03 04:54:12 PM PDT 24
Finished Jul 03 04:54:13 PM PDT 24
Peak memory 206024 kb
Host smart-d064e391-4a7a-43ac-b1b4-0e2cfeea7c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39836
53050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3983653050
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2622845806
Short name T2686
Test name
Test status
Simulation time 251283951 ps
CPU time 0.99 seconds
Started Jul 03 04:54:04 PM PDT 24
Finished Jul 03 04:54:05 PM PDT 24
Peak memory 206080 kb
Host smart-8f9d841f-a422-41dd-ba87-ab603ce4d8ba
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2622845806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2622845806
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1950862808
Short name T844
Test name
Test status
Simulation time 143701827 ps
CPU time 0.82 seconds
Started Jul 03 04:54:11 PM PDT 24
Finished Jul 03 04:54:12 PM PDT 24
Peak memory 206072 kb
Host smart-3d74fec0-af26-4f44-ab3b-91cb8f57cb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19508
62808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1950862808
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2958287404
Short name T2405
Test name
Test status
Simulation time 72152518 ps
CPU time 0.7 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206020 kb
Host smart-c08a8a78-4ab7-4b02-a51e-c948b128f52e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29582
87404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2958287404
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3999506289
Short name T1134
Test name
Test status
Simulation time 8509915849 ps
CPU time 20.46 seconds
Started Jul 03 04:54:33 PM PDT 24
Finished Jul 03 04:54:54 PM PDT 24
Peak memory 206488 kb
Host smart-b2387bc1-740d-47a5-9e85-04bad6278a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39995
06289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3999506289
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.568888614
Short name T2116
Test name
Test status
Simulation time 175767982 ps
CPU time 0.89 seconds
Started Jul 03 04:54:10 PM PDT 24
Finished Jul 03 04:54:11 PM PDT 24
Peak memory 206112 kb
Host smart-2c18e7e9-0be2-40b0-a903-54f885d4f3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56888
8614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.568888614
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1231666299
Short name T1808
Test name
Test status
Simulation time 163173968 ps
CPU time 0.85 seconds
Started Jul 03 04:54:09 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206144 kb
Host smart-91382dd4-69d0-42f5-a493-a306d7c85f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12316
66299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1231666299
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.1471384266
Short name T2461
Test name
Test status
Simulation time 172958782 ps
CPU time 0.81 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206136 kb
Host smart-67080845-d11e-41d2-baf1-c86eeb1125cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14713
84266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.1471384266
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.2539052310
Short name T918
Test name
Test status
Simulation time 156585108 ps
CPU time 0.81 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206096 kb
Host smart-d6ab01e0-f0f8-4383-abf6-cee080db1cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25390
52310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.2539052310
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3360874983
Short name T2340
Test name
Test status
Simulation time 237521467 ps
CPU time 0.87 seconds
Started Jul 03 04:54:11 PM PDT 24
Finished Jul 03 04:54:12 PM PDT 24
Peak memory 206116 kb
Host smart-a1f773a8-2e96-4c0e-a1c0-250e2ab209f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33608
74983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3360874983
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1478825371
Short name T2533
Test name
Test status
Simulation time 224700770 ps
CPU time 0.85 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206096 kb
Host smart-a40211c8-94a7-4054-9627-fc5301aa00dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14788
25371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1478825371
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2797542525
Short name T422
Test name
Test status
Simulation time 206593120 ps
CPU time 0.8 seconds
Started Jul 03 04:54:18 PM PDT 24
Finished Jul 03 04:54:19 PM PDT 24
Peak memory 206124 kb
Host smart-9719d767-7f38-4f6a-a02c-365aa5f51bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27975
42525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2797542525
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.320479136
Short name T397
Test name
Test status
Simulation time 303009264 ps
CPU time 0.99 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206096 kb
Host smart-2271bc6c-b66d-45cd-ac4a-d5dccaa181c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
9136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.320479136
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.3577515059
Short name T1198
Test name
Test status
Simulation time 4404419098 ps
CPU time 29.95 seconds
Started Jul 03 04:54:20 PM PDT 24
Finished Jul 03 04:54:50 PM PDT 24
Peak memory 206312 kb
Host smart-270d5548-d75d-44ec-a9bb-d47333965d51
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3577515059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.3577515059
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2597300100
Short name T479
Test name
Test status
Simulation time 173021776 ps
CPU time 0.84 seconds
Started Jul 03 04:54:11 PM PDT 24
Finished Jul 03 04:54:13 PM PDT 24
Peak memory 206116 kb
Host smart-aa66782b-6e07-4d8d-a56d-bd7c4478d583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25973
00100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2597300100
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.216752141
Short name T515
Test name
Test status
Simulation time 146337922 ps
CPU time 0.79 seconds
Started Jul 03 04:54:18 PM PDT 24
Finished Jul 03 04:54:19 PM PDT 24
Peak memory 206124 kb
Host smart-3494d1ee-36a0-4481-8b54-79dafa90bba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21675
2141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.216752141
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.1212422855
Short name T1980
Test name
Test status
Simulation time 389380861 ps
CPU time 1.21 seconds
Started Jul 03 04:54:20 PM PDT 24
Finished Jul 03 04:54:22 PM PDT 24
Peak memory 206128 kb
Host smart-a88670d6-36a4-421c-b3ab-5ceaf3c04bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12124
22855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.1212422855
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.232224600
Short name T585
Test name
Test status
Simulation time 3085050313 ps
CPU time 28.93 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206440 kb
Host smart-11b7331d-1792-4bdf-8d73-168cd3c4a072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23222
4600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.232224600
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.774833761
Short name T926
Test name
Test status
Simulation time 125672697 ps
CPU time 0.76 seconds
Started Jul 03 04:54:20 PM PDT 24
Finished Jul 03 04:54:21 PM PDT 24
Peak memory 206076 kb
Host smart-1cb80308-01db-41a0-a92e-9b85fc2917c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=774833761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.774833761
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2358500405
Short name T2492
Test name
Test status
Simulation time 3867989101 ps
CPU time 4.77 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:24 PM PDT 24
Peak memory 206348 kb
Host smart-875fa13b-8e82-4fd4-92a5-0cf722bd5d3b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2358500405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2358500405
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3539953878
Short name T546
Test name
Test status
Simulation time 13355632967 ps
CPU time 13.27 seconds
Started Jul 03 04:54:16 PM PDT 24
Finished Jul 03 04:54:30 PM PDT 24
Peak memory 206200 kb
Host smart-1225709b-e39c-4056-bd79-ad1ebe68adff
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3539953878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3539953878
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.279359391
Short name T2666
Test name
Test status
Simulation time 23313793627 ps
CPU time 26.93 seconds
Started Jul 03 04:54:18 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206164 kb
Host smart-6d1441dc-50c1-4a04-ad76-7715087fc324
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=279359391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.279359391
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.4294421414
Short name T383
Test name
Test status
Simulation time 163712789 ps
CPU time 0.83 seconds
Started Jul 03 04:54:09 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206104 kb
Host smart-6ad55d70-a3c1-4e1c-940c-cdfa799a3bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42944
21414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.4294421414
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3907074073
Short name T74
Test name
Test status
Simulation time 140927892 ps
CPU time 0.75 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206000 kb
Host smart-f4487977-dc1d-4117-8b71-8d2b46b3ae5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39070
74073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3907074073
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1407399740
Short name T165
Test name
Test status
Simulation time 495611635 ps
CPU time 1.57 seconds
Started Jul 03 04:54:17 PM PDT 24
Finished Jul 03 04:54:19 PM PDT 24
Peak memory 206272 kb
Host smart-89e41a7f-3d71-4757-b4e7-fe3bd42954e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073
99740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1407399740
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2897984121
Short name T2554
Test name
Test status
Simulation time 1443326304 ps
CPU time 3.12 seconds
Started Jul 03 04:54:10 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 206264 kb
Host smart-cb877b7c-bc81-4548-9476-63bbd9f674cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28979
84121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2897984121
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3537003260
Short name T1376
Test name
Test status
Simulation time 19335393654 ps
CPU time 33.08 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:49 PM PDT 24
Peak memory 206388 kb
Host smart-b7088d0e-f427-48ef-b2ab-53ba98c0f488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35370
03260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3537003260
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.2704192563
Short name T1559
Test name
Test status
Simulation time 500965201 ps
CPU time 1.5 seconds
Started Jul 03 04:54:08 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206056 kb
Host smart-faae0a7a-b1bc-41a7-ba49-a0eb6a770511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27041
92563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2704192563
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3246304159
Short name T1700
Test name
Test status
Simulation time 142799707 ps
CPU time 0.78 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206132 kb
Host smart-98ac1541-f807-4172-a4e5-c7a36549f064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32463
04159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3246304159
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1630698451
Short name T2502
Test name
Test status
Simulation time 37409276 ps
CPU time 0.67 seconds
Started Jul 03 04:54:09 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 205980 kb
Host smart-b0d5b0eb-e712-44cf-95a3-b7734b347452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16306
98451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1630698451
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.767992865
Short name T508
Test name
Test status
Simulation time 804327446 ps
CPU time 1.85 seconds
Started Jul 03 04:54:11 PM PDT 24
Finished Jul 03 04:54:13 PM PDT 24
Peak memory 206320 kb
Host smart-ad89a6fe-62e5-466f-8390-68bcce7bbaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76799
2865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.767992865
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3067719499
Short name T2646
Test name
Test status
Simulation time 230679282 ps
CPU time 1.93 seconds
Started Jul 03 04:54:09 PM PDT 24
Finished Jul 03 04:54:12 PM PDT 24
Peak memory 206348 kb
Host smart-71fa97b5-2c87-4c9b-bc85-be3c01a76f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30677
19499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3067719499
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2684937338
Short name T120
Test name
Test status
Simulation time 243367611 ps
CPU time 0.97 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206044 kb
Host smart-3c2f843d-0be1-4b2b-a1d3-ca5279301df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26849
37338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2684937338
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3407609071
Short name T1057
Test name
Test status
Simulation time 144406843 ps
CPU time 0.76 seconds
Started Jul 03 04:54:11 PM PDT 24
Finished Jul 03 04:54:12 PM PDT 24
Peak memory 206048 kb
Host smart-c1f13a75-7a9d-4c52-9e1f-b7c3909522ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34076
09071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3407609071
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.4122867802
Short name T1891
Test name
Test status
Simulation time 234081610 ps
CPU time 0.89 seconds
Started Jul 03 04:54:14 PM PDT 24
Finished Jul 03 04:54:15 PM PDT 24
Peak memory 206120 kb
Host smart-bfb3b38d-2bbb-416e-96d3-0717696bff28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41228
67802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.4122867802
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.382894999
Short name T2096
Test name
Test status
Simulation time 5362664105 ps
CPU time 37.37 seconds
Started Jul 03 04:54:10 PM PDT 24
Finished Jul 03 04:54:48 PM PDT 24
Peak memory 206372 kb
Host smart-bd35de2c-81df-4de7-8e3a-a1eadd6a5dc2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=382894999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.382894999
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3068610357
Short name T751
Test name
Test status
Simulation time 233953031 ps
CPU time 0.96 seconds
Started Jul 03 04:54:11 PM PDT 24
Finished Jul 03 04:54:13 PM PDT 24
Peak memory 206132 kb
Host smart-2193e150-3481-44c1-8313-0f0948a75c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30686
10357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3068610357
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.4028491874
Short name T1759
Test name
Test status
Simulation time 23298905971 ps
CPU time 26.42 seconds
Started Jul 03 04:54:14 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 206152 kb
Host smart-4f422c8e-2407-48de-94d4-3053ecaa16a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40284
91874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.4028491874
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3237146592
Short name T1881
Test name
Test status
Simulation time 3280059459 ps
CPU time 3.97 seconds
Started Jul 03 04:54:16 PM PDT 24
Finished Jul 03 04:54:26 PM PDT 24
Peak memory 206108 kb
Host smart-177b74a2-f2bb-429e-9865-fb299443dd7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32371
46592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3237146592
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.375663658
Short name T1170
Test name
Test status
Simulation time 11345560921 ps
CPU time 101.12 seconds
Started Jul 03 04:54:18 PM PDT 24
Finished Jul 03 04:56:00 PM PDT 24
Peak memory 206416 kb
Host smart-f2ac741a-46e8-4de4-b48d-2fa5707570eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37566
3658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.375663658
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.4237758707
Short name T641
Test name
Test status
Simulation time 5490482997 ps
CPU time 156.11 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206392 kb
Host smart-c33ce1cb-402e-4380-a0ab-627134e90b4f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4237758707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.4237758707
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3954087605
Short name T1397
Test name
Test status
Simulation time 235322228 ps
CPU time 0.9 seconds
Started Jul 03 04:54:14 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206112 kb
Host smart-7a05f684-63b7-46b3-853e-52b679b02122
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3954087605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3954087605
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1169880665
Short name T1865
Test name
Test status
Simulation time 198995492 ps
CPU time 0.87 seconds
Started Jul 03 04:54:12 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 206056 kb
Host smart-08f351dc-087a-4311-ab3b-86e666df92f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11698
80665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1169880665
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.481636469
Short name T1548
Test name
Test status
Simulation time 4744350167 ps
CPU time 130.65 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:56:47 PM PDT 24
Peak memory 206364 kb
Host smart-5c564df0-beb6-4094-b7ff-7db601d9105b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48163
6469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.481636469
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2177189453
Short name T921
Test name
Test status
Simulation time 4170880594 ps
CPU time 108.81 seconds
Started Jul 03 04:54:14 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206380 kb
Host smart-2ce2a836-7ecb-40d5-b133-6f5b68ad57cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2177189453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2177189453
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1084603218
Short name T1928
Test name
Test status
Simulation time 156401296 ps
CPU time 0.77 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:17 PM PDT 24
Peak memory 206112 kb
Host smart-039afcda-6e4e-4352-b2e5-beff873ab115
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1084603218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1084603218
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.603085299
Short name T876
Test name
Test status
Simulation time 189125851 ps
CPU time 0.86 seconds
Started Jul 03 04:54:12 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 206076 kb
Host smart-81e03bf0-23e4-47cc-8353-12bea9890ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60308
5299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.603085299
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.1910300152
Short name T560
Test name
Test status
Simulation time 164534052 ps
CPU time 0.81 seconds
Started Jul 03 04:54:32 PM PDT 24
Finished Jul 03 04:54:33 PM PDT 24
Peak memory 206088 kb
Host smart-3ef8b558-397a-416b-abf8-43b3b1178828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19103
00152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1910300152
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2090531544
Short name T2498
Test name
Test status
Simulation time 155019032 ps
CPU time 0.8 seconds
Started Jul 03 04:54:13 PM PDT 24
Finished Jul 03 04:54:15 PM PDT 24
Peak memory 206080 kb
Host smart-e09f56da-f81c-4049-8e2b-898cda69b503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20905
31544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2090531544
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2520953305
Short name T1864
Test name
Test status
Simulation time 198668090 ps
CPU time 0.85 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206084 kb
Host smart-2c490b1d-bb78-49be-986e-3c918ff204d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25209
53305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2520953305
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3114881822
Short name T1738
Test name
Test status
Simulation time 154922815 ps
CPU time 0.8 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206124 kb
Host smart-28a92afc-446b-413e-9aff-23263657865c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31148
81822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3114881822
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.68505124
Short name T510
Test name
Test status
Simulation time 218134695 ps
CPU time 0.9 seconds
Started Jul 03 04:54:12 PM PDT 24
Finished Jul 03 04:54:13 PM PDT 24
Peak memory 206092 kb
Host smart-e9ea688a-76d4-4ce9-8001-2ff98040517a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=68505124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.68505124
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.264776277
Short name T1737
Test name
Test status
Simulation time 156868503 ps
CPU time 0.8 seconds
Started Jul 03 04:54:15 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206124 kb
Host smart-714578eb-e450-417a-a5d0-82f3110cb980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26477
6277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.264776277
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3587002077
Short name T2225
Test name
Test status
Simulation time 60851721 ps
CPU time 0.66 seconds
Started Jul 03 04:54:13 PM PDT 24
Finished Jul 03 04:54:14 PM PDT 24
Peak memory 205992 kb
Host smart-b6ac8af8-4c5e-4914-8bff-2afd0e9a6091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35870
02077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3587002077
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.1975714195
Short name T2328
Test name
Test status
Simulation time 7781959382 ps
CPU time 17.61 seconds
Started Jul 03 04:54:20 PM PDT 24
Finished Jul 03 04:54:38 PM PDT 24
Peak memory 206476 kb
Host smart-e28ea566-a3bb-4057-95ae-e70b6f9aaa56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19757
14195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.1975714195
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2118950933
Short name T828
Test name
Test status
Simulation time 192059728 ps
CPU time 0.81 seconds
Started Jul 03 04:54:18 PM PDT 24
Finished Jul 03 04:54:19 PM PDT 24
Peak memory 206132 kb
Host smart-f681b67e-ef85-43bd-8c2f-21d0f89ab2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21189
50933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2118950933
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.88290449
Short name T242
Test name
Test status
Simulation time 208868641 ps
CPU time 0.9 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:54:36 PM PDT 24
Peak memory 206116 kb
Host smart-a972e491-4a5d-4f01-b43a-ea0d3b926cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88290
449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.88290449
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1312766987
Short name T32
Test name
Test status
Simulation time 233332106 ps
CPU time 0.9 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206136 kb
Host smart-42cf26ef-2899-4ab4-a489-1aeb93376209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13127
66987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1312766987
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3051876774
Short name T1585
Test name
Test status
Simulation time 157821776 ps
CPU time 0.82 seconds
Started Jul 03 04:54:27 PM PDT 24
Finished Jul 03 04:54:28 PM PDT 24
Peak memory 206128 kb
Host smart-615fcfca-7dc3-4289-8877-93092cecd0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30518
76774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3051876774
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.178479380
Short name T754
Test name
Test status
Simulation time 138899684 ps
CPU time 0.77 seconds
Started Jul 03 04:54:20 PM PDT 24
Finished Jul 03 04:54:21 PM PDT 24
Peak memory 206124 kb
Host smart-ddd1ecaf-5db8-449d-b5ff-4ee5b6bbed42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17847
9380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.178479380
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2188046399
Short name T1593
Test name
Test status
Simulation time 163850082 ps
CPU time 0.79 seconds
Started Jul 03 04:54:28 PM PDT 24
Finished Jul 03 04:54:29 PM PDT 24
Peak memory 206112 kb
Host smart-9bdcdbd4-99dd-4bd5-a482-72305c1c6ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21880
46399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2188046399
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1429646263
Short name T2519
Test name
Test status
Simulation time 167811471 ps
CPU time 0.83 seconds
Started Jul 03 04:54:28 PM PDT 24
Finished Jul 03 04:54:29 PM PDT 24
Peak memory 206132 kb
Host smart-dc13fdad-62ed-4406-b184-a242ea154957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14296
46263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1429646263
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2617583504
Short name T2670
Test name
Test status
Simulation time 255129707 ps
CPU time 1.02 seconds
Started Jul 03 04:54:22 PM PDT 24
Finished Jul 03 04:54:23 PM PDT 24
Peak memory 206052 kb
Host smart-92a51769-5d55-4b05-8230-38b9f294645e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26175
83504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2617583504
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3563664627
Short name T2537
Test name
Test status
Simulation time 4614918077 ps
CPU time 41.7 seconds
Started Jul 03 04:54:40 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206452 kb
Host smart-5e7db8dc-1c7f-4441-910d-e441d520fb3a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3563664627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3563664627
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.670755324
Short name T820
Test name
Test status
Simulation time 193540193 ps
CPU time 0.79 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:54:35 PM PDT 24
Peak memory 206128 kb
Host smart-d1b08290-4bf3-4a5d-9c8c-f88b1dd87a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67075
5324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.670755324
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.695443531
Short name T1790
Test name
Test status
Simulation time 168667551 ps
CPU time 0.85 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206132 kb
Host smart-ed03c2cc-7151-47de-90d9-658ec79687fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69544
3531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.695443531
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.2944844599
Short name T861
Test name
Test status
Simulation time 753824841 ps
CPU time 1.81 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:21 PM PDT 24
Peak memory 206380 kb
Host smart-227f9c61-4ef4-4f84-9542-7d7c1e4eecc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29448
44599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.2944844599
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2102976480
Short name T345
Test name
Test status
Simulation time 6609835864 ps
CPU time 60.4 seconds
Started Jul 03 04:54:20 PM PDT 24
Finished Jul 03 04:55:21 PM PDT 24
Peak memory 206388 kb
Host smart-c0ceac46-e167-46df-ad79-c56e1cf86532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21029
76480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2102976480
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.3449228162
Short name T17
Test name
Test status
Simulation time 43640363 ps
CPU time 0.65 seconds
Started Jul 03 04:54:25 PM PDT 24
Finished Jul 03 04:54:26 PM PDT 24
Peak memory 206108 kb
Host smart-d3f5ae3f-46a7-4428-a461-c4baf744f4d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3449228162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.3449228162
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3405612235
Short name T618
Test name
Test status
Simulation time 4045772894 ps
CPU time 4.82 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 206412 kb
Host smart-d38cd43c-091a-4fe6-b048-6b57683ff2a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3405612235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.3405612235
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.59884102
Short name T212
Test name
Test status
Simulation time 13438845608 ps
CPU time 13.98 seconds
Started Jul 03 04:54:42 PM PDT 24
Finished Jul 03 04:54:58 PM PDT 24
Peak memory 206164 kb
Host smart-5a0b1d41-e989-4490-afbc-c81fc82275d0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=59884102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.59884102
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1537356662
Short name T2599
Test name
Test status
Simulation time 23286078133 ps
CPU time 25.46 seconds
Started Jul 03 04:54:18 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206444 kb
Host smart-19dbc85d-b535-4816-b2f0-d16724e84a2a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1537356662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1537356662
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3983780903
Short name T2071
Test name
Test status
Simulation time 180551183 ps
CPU time 0.85 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206000 kb
Host smart-c3b1dd49-a1fa-4c4d-8ab0-359a9ed4d4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39837
80903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3983780903
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3456137032
Short name T866
Test name
Test status
Simulation time 240176741 ps
CPU time 0.92 seconds
Started Jul 03 04:54:30 PM PDT 24
Finished Jul 03 04:54:31 PM PDT 24
Peak memory 206112 kb
Host smart-fe50b31a-f4ed-4710-9d89-02e328ad1538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34561
37032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3456137032
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3430438600
Short name T1683
Test name
Test status
Simulation time 286141582 ps
CPU time 0.98 seconds
Started Jul 03 04:54:23 PM PDT 24
Finished Jul 03 04:54:24 PM PDT 24
Peak memory 206132 kb
Host smart-536e61df-aac3-4bf7-a70d-edda38435fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34304
38600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3430438600
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2341318759
Short name T2614
Test name
Test status
Simulation time 923727234 ps
CPU time 2.14 seconds
Started Jul 03 04:54:22 PM PDT 24
Finished Jul 03 04:54:25 PM PDT 24
Peak memory 206360 kb
Host smart-f25747b3-3b5e-4964-b26e-fdd0c2369fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23413
18759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2341318759
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.3638859756
Short name T1616
Test name
Test status
Simulation time 13366525067 ps
CPU time 26.78 seconds
Started Jul 03 04:54:20 PM PDT 24
Finished Jul 03 04:54:47 PM PDT 24
Peak memory 206460 kb
Host smart-3b5675da-ac18-4c13-a36b-6c5c3b3742a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36388
59756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3638859756
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.4069099823
Short name T1664
Test name
Test status
Simulation time 532175636 ps
CPU time 1.41 seconds
Started Jul 03 04:54:18 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206112 kb
Host smart-7c11ba2f-6328-4350-9ec1-556c7ca71a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40690
99823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.4069099823
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2224645805
Short name T1923
Test name
Test status
Simulation time 141137263 ps
CPU time 0.76 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:38 PM PDT 24
Peak memory 206100 kb
Host smart-7973209c-c315-4f7c-99f9-0737b4204369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22246
45805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2224645805
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2689947214
Short name T1350
Test name
Test status
Simulation time 34379509 ps
CPU time 0.66 seconds
Started Jul 03 04:54:19 PM PDT 24
Finished Jul 03 04:54:20 PM PDT 24
Peak memory 206112 kb
Host smart-2f9ba2db-9d40-4c6a-80af-46ef7a9c028d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26899
47214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2689947214
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1130772682
Short name T1145
Test name
Test status
Simulation time 828170577 ps
CPU time 1.96 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:54:36 PM PDT 24
Peak memory 206328 kb
Host smart-8a0c7441-513c-443d-8ac1-315ae665897d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11307
72682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1130772682
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1023991783
Short name T2587
Test name
Test status
Simulation time 269178323 ps
CPU time 1.75 seconds
Started Jul 03 04:54:22 PM PDT 24
Finished Jul 03 04:54:25 PM PDT 24
Peak memory 206372 kb
Host smart-2c1e2978-d95e-4b49-bfe5-41e068a17b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10239
91783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1023991783
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2720056874
Short name T2671
Test name
Test status
Simulation time 176564024 ps
CPU time 0.8 seconds
Started Jul 03 04:54:31 PM PDT 24
Finished Jul 03 04:54:32 PM PDT 24
Peak memory 206116 kb
Host smart-f944cd23-441e-481c-a973-9d435b49e509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27200
56874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2720056874
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3251338581
Short name T1876
Test name
Test status
Simulation time 164122096 ps
CPU time 0.83 seconds
Started Jul 03 04:54:22 PM PDT 24
Finished Jul 03 04:54:23 PM PDT 24
Peak memory 205996 kb
Host smart-3f886c6c-1ee0-4022-b56e-d184c9a2e4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32513
38581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3251338581
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.918476286
Short name T33
Test name
Test status
Simulation time 166674328 ps
CPU time 0.84 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:54:37 PM PDT 24
Peak memory 206132 kb
Host smart-ffa281b6-d80c-4cd6-bd14-cc7960088a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91847
6286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.918476286
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.3062890531
Short name T924
Test name
Test status
Simulation time 9183356930 ps
CPU time 267.79 seconds
Started Jul 03 04:54:23 PM PDT 24
Finished Jul 03 04:58:52 PM PDT 24
Peak memory 206432 kb
Host smart-449c6a8a-a355-4e28-89c8-9b367e102178
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3062890531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.3062890531
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.1185976100
Short name T1981
Test name
Test status
Simulation time 189168008 ps
CPU time 0.8 seconds
Started Jul 03 04:54:45 PM PDT 24
Finished Jul 03 04:54:47 PM PDT 24
Peak memory 206096 kb
Host smart-f50487f6-d4b4-45a1-9fe7-8eb4de41fce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11859
76100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.1185976100
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.584069543
Short name T2343
Test name
Test status
Simulation time 23347728937 ps
CPU time 27.61 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:55:08 PM PDT 24
Peak memory 206200 kb
Host smart-08a5c426-6065-45b8-a520-ebbf5ef49200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58406
9543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.584069543
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2233212385
Short name T1165
Test name
Test status
Simulation time 3263595027 ps
CPU time 3.97 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206180 kb
Host smart-47e4bbda-c9ad-4d30-ad75-1a4cfecacbf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332
12385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2233212385
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.3040643065
Short name T1412
Test name
Test status
Simulation time 7680708730 ps
CPU time 213.58 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:58:08 PM PDT 24
Peak memory 206444 kb
Host smart-976dbdab-4c88-4521-b27b-2a622abc426d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30406
43065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.3040643065
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.2531473941
Short name T1970
Test name
Test status
Simulation time 5344580608 ps
CPU time 144.7 seconds
Started Jul 03 04:54:22 PM PDT 24
Finished Jul 03 04:56:47 PM PDT 24
Peak memory 206356 kb
Host smart-06eea70e-f9a0-4d9f-a4fd-20e90e0f4ab4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2531473941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.2531473941
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.2454559430
Short name T1487
Test name
Test status
Simulation time 234830444 ps
CPU time 0.93 seconds
Started Jul 03 04:54:35 PM PDT 24
Finished Jul 03 04:54:36 PM PDT 24
Peak memory 206072 kb
Host smart-23b05e1c-28ad-43c2-a771-4803896e3cc3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2454559430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.2454559430
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2055429209
Short name T521
Test name
Test status
Simulation time 204237907 ps
CPU time 0.9 seconds
Started Jul 03 04:54:21 PM PDT 24
Finished Jul 03 04:54:23 PM PDT 24
Peak memory 206080 kb
Host smart-c7da5b64-7de0-4a74-9617-ff72abe6715c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20554
29209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2055429209
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3402233906
Short name T1141
Test name
Test status
Simulation time 4623991083 ps
CPU time 40.93 seconds
Started Jul 03 04:54:23 PM PDT 24
Finished Jul 03 04:55:04 PM PDT 24
Peak memory 206316 kb
Host smart-a96690f8-7df0-4d15-a5a2-8137aa14ab5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34022
33906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3402233906
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.570783780
Short name T599
Test name
Test status
Simulation time 6779249715 ps
CPU time 63.59 seconds
Started Jul 03 04:54:22 PM PDT 24
Finished Jul 03 04:55:26 PM PDT 24
Peak memory 206380 kb
Host smart-b461e320-536b-46ef-8acb-c20130c8c859
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=570783780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.570783780
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1403396658
Short name T1256
Test name
Test status
Simulation time 155648459 ps
CPU time 0.9 seconds
Started Jul 03 04:54:29 PM PDT 24
Finished Jul 03 04:54:30 PM PDT 24
Peak memory 206120 kb
Host smart-dcbd78f7-883a-48a2-9e72-25f0c5ce10e1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1403396658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1403396658
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.1216353579
Short name T2050
Test name
Test status
Simulation time 154049956 ps
CPU time 0.76 seconds
Started Jul 03 04:54:26 PM PDT 24
Finished Jul 03 04:54:27 PM PDT 24
Peak memory 206112 kb
Host smart-5b007b9a-3f78-4ca7-8126-d79fbc516f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12163
53579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.1216353579
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.33897643
Short name T133
Test name
Test status
Simulation time 175469923 ps
CPU time 0.79 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:43 PM PDT 24
Peak memory 206076 kb
Host smart-389349c1-312e-4cea-a9b6-ad5e20cd9d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33897
643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.33897643
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1595236655
Short name T1681
Test name
Test status
Simulation time 162245214 ps
CPU time 0.85 seconds
Started Jul 03 04:54:30 PM PDT 24
Finished Jul 03 04:54:32 PM PDT 24
Peak memory 206128 kb
Host smart-812eb164-3bbf-4181-9127-2627689132d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15952
36655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1595236655
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1037116692
Short name T1520
Test name
Test status
Simulation time 167928184 ps
CPU time 0.79 seconds
Started Jul 03 04:54:26 PM PDT 24
Finished Jul 03 04:54:27 PM PDT 24
Peak memory 206112 kb
Host smart-cb3619b7-4adc-4116-b97f-c330d5953c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10371
16692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1037116692
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2148629102
Short name T799
Test name
Test status
Simulation time 174208168 ps
CPU time 0.85 seconds
Started Jul 03 04:54:26 PM PDT 24
Finished Jul 03 04:54:27 PM PDT 24
Peak memory 206116 kb
Host smart-f7afb02f-388f-4db5-81fc-0c556a522ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21486
29102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2148629102
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1524650410
Short name T1382
Test name
Test status
Simulation time 165958788 ps
CPU time 0.78 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 206084 kb
Host smart-7af38feb-3f36-4921-9339-9b57cb176259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15246
50410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1524650410
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.2697336641
Short name T1253
Test name
Test status
Simulation time 271234606 ps
CPU time 0.96 seconds
Started Jul 03 04:54:25 PM PDT 24
Finished Jul 03 04:54:27 PM PDT 24
Peak memory 206152 kb
Host smart-89a7e36d-c6a2-4d9e-b1fd-71322cb49d1f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2697336641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.2697336641
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1537987807
Short name T1414
Test name
Test status
Simulation time 143244756 ps
CPU time 0.79 seconds
Started Jul 03 04:54:21 PM PDT 24
Finished Jul 03 04:54:22 PM PDT 24
Peak memory 205984 kb
Host smart-368a0ac4-c681-4818-9c09-63ca1e6b49a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15379
87807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1537987807
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1634905779
Short name T2348
Test name
Test status
Simulation time 32563689 ps
CPU time 0.63 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:54:35 PM PDT 24
Peak memory 206064 kb
Host smart-b1332425-6961-4333-be48-8d7b758a5b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16349
05779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1634905779
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2474326271
Short name T1124
Test name
Test status
Simulation time 19546869951 ps
CPU time 42.59 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206452 kb
Host smart-f948fe7c-bbe8-4fa3-b9d6-2fdd03e873ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24743
26271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2474326271
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2176837388
Short name T1581
Test name
Test status
Simulation time 193608694 ps
CPU time 0.85 seconds
Started Jul 03 04:54:40 PM PDT 24
Finished Jul 03 04:54:42 PM PDT 24
Peak memory 206092 kb
Host smart-14740f1f-7598-47ef-a518-40fa6beaea76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21768
37388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2176837388
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2436168100
Short name T2205
Test name
Test status
Simulation time 208647427 ps
CPU time 0.88 seconds
Started Jul 03 04:54:21 PM PDT 24
Finished Jul 03 04:54:23 PM PDT 24
Peak memory 206124 kb
Host smart-81fab78b-a59b-43e5-903d-46ec165dbc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24361
68100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2436168100
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1675969839
Short name T2712
Test name
Test status
Simulation time 209008092 ps
CPU time 0.85 seconds
Started Jul 03 04:54:35 PM PDT 24
Finished Jul 03 04:54:36 PM PDT 24
Peak memory 206132 kb
Host smart-4d385224-2e13-455b-9c31-085946abcee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16759
69839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1675969839
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.2705420298
Short name T782
Test name
Test status
Simulation time 189196198 ps
CPU time 0.81 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 205908 kb
Host smart-ff8a5ee7-0fe9-400c-8b33-b4caa7ae3621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27054
20298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.2705420298
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.4033498544
Short name T2459
Test name
Test status
Simulation time 159213274 ps
CPU time 0.79 seconds
Started Jul 03 04:54:23 PM PDT 24
Finished Jul 03 04:54:24 PM PDT 24
Peak memory 206096 kb
Host smart-36803f9d-4b33-4af8-8ea1-ac2329dc1fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40334
98544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.4033498544
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2027997099
Short name T393
Test name
Test status
Simulation time 148244110 ps
CPU time 0.75 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206092 kb
Host smart-7417cb19-18ca-4c1c-bfef-06ebc00eb444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20279
97099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2027997099
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2810541582
Short name T18
Test name
Test status
Simulation time 192147681 ps
CPU time 0.83 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:54:38 PM PDT 24
Peak memory 206096 kb
Host smart-46cfe51a-06c8-4852-a4c8-a95b51d41a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28105
41582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2810541582
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3980606389
Short name T431
Test name
Test status
Simulation time 220787012 ps
CPU time 0.99 seconds
Started Jul 03 04:54:24 PM PDT 24
Finished Jul 03 04:54:25 PM PDT 24
Peak memory 206112 kb
Host smart-0c451a4a-6397-4d4f-a283-f827aaf0469b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39806
06389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3980606389
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.675785978
Short name T161
Test name
Test status
Simulation time 5329325154 ps
CPU time 150.21 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:57:11 PM PDT 24
Peak memory 206420 kb
Host smart-71bb7ba8-c8a5-464e-b671-04ceffb93bfe
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=675785978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.675785978
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.342986593
Short name T1809
Test name
Test status
Simulation time 181001594 ps
CPU time 0.81 seconds
Started Jul 03 04:54:35 PM PDT 24
Finished Jul 03 04:54:37 PM PDT 24
Peak memory 206128 kb
Host smart-acff6827-45cf-44e1-86e3-5bb52cd7b902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34298
6593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.342986593
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2157966082
Short name T575
Test name
Test status
Simulation time 159268738 ps
CPU time 0.79 seconds
Started Jul 03 04:54:26 PM PDT 24
Finished Jul 03 04:54:28 PM PDT 24
Peak memory 206132 kb
Host smart-fc71fa4e-c096-4cdb-9a7c-4c3e76d2f3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21579
66082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2157966082
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.2707918294
Short name T615
Test name
Test status
Simulation time 1140534214 ps
CPU time 2.45 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206340 kb
Host smart-f8bd705f-1472-4e87-b531-e13ae89fbdb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27079
18294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.2707918294
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2128450661
Short name T2487
Test name
Test status
Simulation time 7295643783 ps
CPU time 75.96 seconds
Started Jul 03 04:54:27 PM PDT 24
Finished Jul 03 04:55:44 PM PDT 24
Peak memory 206436 kb
Host smart-3ae8830a-c156-456a-8a99-204b9116dbfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21284
50661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2128450661
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.1066360263
Short name T1885
Test name
Test status
Simulation time 37985439 ps
CPU time 0.71 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206084 kb
Host smart-f6ca41d5-a151-4912-b401-6625b61cf72d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1066360263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1066360263
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2482492289
Short name T757
Test name
Test status
Simulation time 4358408564 ps
CPU time 5.33 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:44 PM PDT 24
Peak memory 206192 kb
Host smart-0578ff3e-5468-4a51-989a-8d6286de9167
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2482492289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.2482492289
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3751508099
Short name T659
Test name
Test status
Simulation time 13356593160 ps
CPU time 12.56 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:55 PM PDT 24
Peak memory 206160 kb
Host smart-08b474ff-2222-42c4-99e2-57bc626700a1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3751508099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3751508099
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3212744465
Short name T2690
Test name
Test status
Simulation time 23310840992 ps
CPU time 24.95 seconds
Started Jul 03 04:54:28 PM PDT 24
Finished Jul 03 04:54:54 PM PDT 24
Peak memory 206048 kb
Host smart-a737e519-f843-4ee1-94d3-ee4cf680f20c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3212744465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.3212744465
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3778363835
Short name T2372
Test name
Test status
Simulation time 226935122 ps
CPU time 0.89 seconds
Started Jul 03 04:54:24 PM PDT 24
Finished Jul 03 04:54:25 PM PDT 24
Peak memory 206112 kb
Host smart-94d50f45-ae20-4545-81f9-45bc7db7f1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37783
63835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3778363835
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2791437232
Short name T2426
Test name
Test status
Simulation time 235194985 ps
CPU time 0.89 seconds
Started Jul 03 04:54:24 PM PDT 24
Finished Jul 03 04:54:25 PM PDT 24
Peak memory 206092 kb
Host smart-610514e2-5173-47e4-b570-844842a02537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27914
37232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2791437232
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1264174317
Short name T878
Test name
Test status
Simulation time 485007719 ps
CPU time 1.37 seconds
Started Jul 03 04:54:25 PM PDT 24
Finished Jul 03 04:54:27 PM PDT 24
Peak memory 206368 kb
Host smart-e1cb3a82-a506-4a74-8982-99c0a511f3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12641
74317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1264174317
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.737139826
Short name T1239
Test name
Test status
Simulation time 1263914953 ps
CPU time 2.63 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206348 kb
Host smart-ac7fe70d-988d-4228-85b5-92da9d1a54c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73713
9826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.737139826
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.917275098
Short name T1675
Test name
Test status
Simulation time 11151811171 ps
CPU time 20.83 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:55:03 PM PDT 24
Peak memory 206396 kb
Host smart-77ca2169-bb76-41ec-a8eb-48b5cd6ed3a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91727
5098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.917275098
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2353667425
Short name T1407
Test name
Test status
Simulation time 522216995 ps
CPU time 1.54 seconds
Started Jul 03 04:54:29 PM PDT 24
Finished Jul 03 04:54:31 PM PDT 24
Peak memory 205972 kb
Host smart-9046bcfd-2859-49a3-89de-1f540fa6fe3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23536
67425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2353667425
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.268220703
Short name T2447
Test name
Test status
Simulation time 145205535 ps
CPU time 0.77 seconds
Started Jul 03 04:54:25 PM PDT 24
Finished Jul 03 04:54:27 PM PDT 24
Peak memory 206092 kb
Host smart-b82cb7f9-58c9-4e9c-9ed8-b2fa603f0bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26822
0703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.268220703
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2029442363
Short name T1715
Test name
Test status
Simulation time 73128974 ps
CPU time 0.69 seconds
Started Jul 03 04:54:26 PM PDT 24
Finished Jul 03 04:54:27 PM PDT 24
Peak memory 206120 kb
Host smart-b047251c-92cc-4228-9652-954aa74840c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20294
42363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2029442363
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.725446145
Short name T1750
Test name
Test status
Simulation time 666138145 ps
CPU time 1.99 seconds
Started Jul 03 04:54:24 PM PDT 24
Finished Jul 03 04:54:26 PM PDT 24
Peak memory 206380 kb
Host smart-077b568f-ca13-4f05-a93d-40563d61d7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72544
6145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.725446145
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2898728921
Short name T1301
Test name
Test status
Simulation time 158400051 ps
CPU time 1.35 seconds
Started Jul 03 04:54:25 PM PDT 24
Finished Jul 03 04:54:27 PM PDT 24
Peak memory 206388 kb
Host smart-99d3e944-6edb-4240-a6e6-383ebb1b8888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28987
28921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2898728921
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2859994405
Short name T694
Test name
Test status
Simulation time 215556426 ps
CPU time 0.86 seconds
Started Jul 03 04:54:31 PM PDT 24
Finished Jul 03 04:54:32 PM PDT 24
Peak memory 205984 kb
Host smart-d768d91c-33a2-468a-ade9-770f6d7ebcb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28599
94405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2859994405
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.494908462
Short name T647
Test name
Test status
Simulation time 154362609 ps
CPU time 0.73 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206128 kb
Host smart-96b312f7-5f9f-4415-b91a-630992a917b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49490
8462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.494908462
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3434643428
Short name T2155
Test name
Test status
Simulation time 204019675 ps
CPU time 0.87 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:54:35 PM PDT 24
Peak memory 206040 kb
Host smart-73fa61e4-529d-4342-96e1-706cd538b32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34346
43428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3434643428
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.274340099
Short name T1702
Test name
Test status
Simulation time 4959371850 ps
CPU time 47.46 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:55:25 PM PDT 24
Peak memory 206396 kb
Host smart-0d6f4a61-5c8f-463d-b46f-b97f6a85a964
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=274340099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.274340099
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.577960475
Short name T1751
Test name
Test status
Simulation time 198482495 ps
CPU time 0.89 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:54:37 PM PDT 24
Peak memory 206064 kb
Host smart-ac45c31b-91eb-400e-924d-bc190ee663ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57796
0475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.577960475
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.388387144
Short name T1526
Test name
Test status
Simulation time 23357567615 ps
CPU time 30.24 seconds
Started Jul 03 04:54:29 PM PDT 24
Finished Jul 03 04:54:59 PM PDT 24
Peak memory 206188 kb
Host smart-25e91de0-e34d-44c9-93e0-4bb7b4970f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38838
7144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.388387144
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3095753360
Short name T2714
Test name
Test status
Simulation time 3285478571 ps
CPU time 3.62 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 206160 kb
Host smart-2ee218fa-55b9-4353-8b19-b52ebaa1b963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30957
53360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3095753360
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3631198653
Short name T501
Test name
Test status
Simulation time 8525989372 ps
CPU time 64.41 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:55:38 PM PDT 24
Peak memory 206416 kb
Host smart-f9ae1e39-13f8-459f-98c3-7fa3308b8ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36311
98653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3631198653
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2633557347
Short name T30
Test name
Test status
Simulation time 4914164665 ps
CPU time 47.97 seconds
Started Jul 03 04:54:25 PM PDT 24
Finished Jul 03 04:55:13 PM PDT 24
Peak memory 206344 kb
Host smart-1d3a5b09-85f2-46cf-8da9-cf9cfda4eb6e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2633557347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2633557347
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2808657847
Short name T1036
Test name
Test status
Simulation time 236011690 ps
CPU time 0.95 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:44 PM PDT 24
Peak memory 206116 kb
Host smart-7e9cd047-228a-4854-b77d-7da11e755787
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2808657847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2808657847
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3317981002
Short name T473
Test name
Test status
Simulation time 188635210 ps
CPU time 0.86 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:43 PM PDT 24
Peak memory 206020 kb
Host smart-3f191d25-8f94-45f3-b3af-a73bc333983c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33179
81002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3317981002
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2236905679
Short name T847
Test name
Test status
Simulation time 3822325828 ps
CPU time 32.33 seconds
Started Jul 03 04:54:40 PM PDT 24
Finished Jul 03 04:55:14 PM PDT 24
Peak memory 206348 kb
Host smart-c7791682-7eb8-4cdc-88f3-4edc16ed5bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22369
05679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2236905679
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2102893779
Short name T2700
Test name
Test status
Simulation time 3137389735 ps
CPU time 82.62 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:56:00 PM PDT 24
Peak memory 206416 kb
Host smart-1931e076-3942-413c-81bc-9c63696bcd05
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2102893779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2102893779
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2339495429
Short name T656
Test name
Test status
Simulation time 178644448 ps
CPU time 0.81 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 206092 kb
Host smart-d8388989-28f3-4e71-89ea-3e7704adb888
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2339495429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2339495429
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.4080124859
Short name T804
Test name
Test status
Simulation time 160802169 ps
CPU time 0.76 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:47 PM PDT 24
Peak memory 206020 kb
Host smart-bfbba6c9-4dd1-4225-b281-e32d5905be75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40801
24859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.4080124859
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1829689192
Short name T1945
Test name
Test status
Simulation time 187614920 ps
CPU time 0.81 seconds
Started Jul 03 04:54:26 PM PDT 24
Finished Jul 03 04:54:28 PM PDT 24
Peak memory 206128 kb
Host smart-5d24a376-7d33-4eee-973f-8a4e2b8df0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18296
89192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1829689192
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3254566241
Short name T535
Test name
Test status
Simulation time 227611643 ps
CPU time 0.87 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:54:44 PM PDT 24
Peak memory 206128 kb
Host smart-2acb0946-38f7-40d1-b18f-03c54b506521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32545
66241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3254566241
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.610790855
Short name T637
Test name
Test status
Simulation time 152653580 ps
CPU time 0.77 seconds
Started Jul 03 04:54:33 PM PDT 24
Finished Jul 03 04:54:34 PM PDT 24
Peak memory 206116 kb
Host smart-a2f97d0c-28c9-49f4-8e3a-841d8af7c8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61079
0855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.610790855
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3156611385
Short name T617
Test name
Test status
Simulation time 209414695 ps
CPU time 0.82 seconds
Started Jul 03 04:54:26 PM PDT 24
Finished Jul 03 04:54:28 PM PDT 24
Peak memory 206132 kb
Host smart-8bb82015-af15-4a8d-ac2a-491cf2720a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31566
11385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3156611385
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1693275378
Short name T725
Test name
Test status
Simulation time 146164081 ps
CPU time 0.77 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:54:37 PM PDT 24
Peak memory 206084 kb
Host smart-b11c768b-8b4d-49ef-8041-a6fb8d9f77fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16932
75378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1693275378
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1043282137
Short name T1334
Test name
Test status
Simulation time 282891700 ps
CPU time 0.97 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206092 kb
Host smart-1141d2ca-b1ed-4515-ab75-b175e9c7a984
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1043282137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1043282137
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3333850578
Short name T2689
Test name
Test status
Simulation time 142058139 ps
CPU time 0.84 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:43 PM PDT 24
Peak memory 206116 kb
Host smart-26b0c242-d698-48db-a26b-97e5b8b9537c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33338
50578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3333850578
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.79387398
Short name T38
Test name
Test status
Simulation time 37202784 ps
CPU time 0.68 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:43 PM PDT 24
Peak memory 206028 kb
Host smart-05aa986d-4d77-4538-ab0a-45298b5d3c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79387
398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.79387398
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1405724255
Short name T1966
Test name
Test status
Simulation time 15208587362 ps
CPU time 31.67 seconds
Started Jul 03 04:54:40 PM PDT 24
Finished Jul 03 04:55:13 PM PDT 24
Peak memory 206380 kb
Host smart-6bf7c3bc-10ce-406b-b93f-1d8e58c425b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14057
24255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1405724255
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.115816095
Short name T2027
Test name
Test status
Simulation time 209213114 ps
CPU time 0.84 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 205896 kb
Host smart-51e324ed-1de6-4d84-a914-0c99c51994ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11581
6095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.115816095
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1770634590
Short name T1775
Test name
Test status
Simulation time 246139326 ps
CPU time 0.96 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:44 PM PDT 24
Peak memory 206084 kb
Host smart-33b65ec1-fcd9-4155-86a8-c87742a8edd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17706
34590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1770634590
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.4122871625
Short name T2606
Test name
Test status
Simulation time 212416334 ps
CPU time 0.84 seconds
Started Jul 03 04:54:25 PM PDT 24
Finished Jul 03 04:54:26 PM PDT 24
Peak memory 206116 kb
Host smart-b0425984-bea3-4015-893c-fbfb77b26217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41228
71625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.4122871625
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3515343016
Short name T2559
Test name
Test status
Simulation time 194381219 ps
CPU time 0.84 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206104 kb
Host smart-ee6c8ac2-22f7-4b87-8aeb-6ab42b610b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35153
43016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3515343016
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.1773943192
Short name T394
Test name
Test status
Simulation time 185977038 ps
CPU time 0.92 seconds
Started Jul 03 04:54:26 PM PDT 24
Finished Jul 03 04:54:28 PM PDT 24
Peak memory 206112 kb
Host smart-3f7dad43-2e60-4c3b-8a84-e12019d4feac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17739
43192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1773943192
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.4043562567
Short name T1169
Test name
Test status
Simulation time 185709332 ps
CPU time 0.81 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206128 kb
Host smart-884df769-719c-40b0-9619-5d72e7a6f7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40435
62567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.4043562567
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.10115289
Short name T1404
Test name
Test status
Simulation time 167310424 ps
CPU time 0.86 seconds
Started Jul 03 04:54:40 PM PDT 24
Finished Jul 03 04:54:42 PM PDT 24
Peak memory 206100 kb
Host smart-89f5ea73-e553-461e-8aa1-6f17bef61a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10115
289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.10115289
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2846095435
Short name T849
Test name
Test status
Simulation time 204692472 ps
CPU time 0.89 seconds
Started Jul 03 04:54:26 PM PDT 24
Finished Jul 03 04:54:27 PM PDT 24
Peak memory 206100 kb
Host smart-38dcf801-1ee8-40ad-be59-782a8dfcf354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28460
95435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2846095435
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.4209875839
Short name T1286
Test name
Test status
Simulation time 7038517411 ps
CPU time 64.35 seconds
Started Jul 03 04:54:35 PM PDT 24
Finished Jul 03 04:55:40 PM PDT 24
Peak memory 206428 kb
Host smart-14b38252-ae05-46f2-9e99-43ab36d0e4f9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4209875839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.4209875839
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2120286302
Short name T2312
Test name
Test status
Simulation time 180118401 ps
CPU time 0.84 seconds
Started Jul 03 04:54:29 PM PDT 24
Finished Jul 03 04:54:30 PM PDT 24
Peak memory 206124 kb
Host smart-d05ba077-3b8e-4526-acd6-1843c79ddeae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21202
86302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2120286302
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2290718035
Short name T1639
Test name
Test status
Simulation time 203414296 ps
CPU time 0.81 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:43 PM PDT 24
Peak memory 206088 kb
Host smart-22f2b97e-9563-4fd4-b6bd-e776a23fd7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22907
18035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2290718035
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.4117035389
Short name T696
Test name
Test status
Simulation time 503012622 ps
CPU time 1.42 seconds
Started Jul 03 04:54:27 PM PDT 24
Finished Jul 03 04:54:29 PM PDT 24
Peak memory 206052 kb
Host smart-8d862741-c35b-466b-8fc1-3ce1afcb0be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41170
35389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.4117035389
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.24787386
Short name T2137
Test name
Test status
Simulation time 3427701280 ps
CPU time 31.64 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:55:14 PM PDT 24
Peak memory 206296 kb
Host smart-2a077e73-65fe-4a84-bf62-91386e444f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24787
386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.24787386
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.943424545
Short name T1103
Test name
Test status
Simulation time 117149962 ps
CPU time 0.74 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206172 kb
Host smart-6584c55e-32be-48d6-991a-9a09cdbae9e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=943424545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.943424545
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3834017598
Short name T722
Test name
Test status
Simulation time 4393927777 ps
CPU time 5.26 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:44 PM PDT 24
Peak memory 206148 kb
Host smart-7a5142b9-4cb1-4e26-9c69-1c670324dbe0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3834017598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3834017598
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2761354212
Short name T1466
Test name
Test status
Simulation time 13381896571 ps
CPU time 12.38 seconds
Started Jul 03 04:54:27 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206192 kb
Host smart-542d4c2b-1ef8-4a14-87a0-84173f41bbdc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2761354212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2761354212
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.4001602858
Short name T1673
Test name
Test status
Simulation time 23331097205 ps
CPU time 23 seconds
Started Jul 03 04:54:45 PM PDT 24
Finished Jul 03 04:55:08 PM PDT 24
Peak memory 206148 kb
Host smart-44d0baf7-e66b-43c3-8e9d-586b96c28d11
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4001602858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.4001602858
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2548077967
Short name T644
Test name
Test status
Simulation time 185438761 ps
CPU time 0.88 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206036 kb
Host smart-94bc7e6c-d9e9-4c09-a34e-a0f5d4c9e6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25480
77967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2548077967
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.1371619934
Short name T1657
Test name
Test status
Simulation time 173945968 ps
CPU time 0.77 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 206128 kb
Host smart-356e962d-cb40-4adb-a2a6-db0030249480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13716
19934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.1371619934
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.3734832955
Short name T2648
Test name
Test status
Simulation time 200888467 ps
CPU time 0.89 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 205776 kb
Host smart-d06f9841-5c02-409d-a5ee-e4e5c0fe50d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37348
32955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.3734832955
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1231541835
Short name T1464
Test name
Test status
Simulation time 852801956 ps
CPU time 2.07 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 205904 kb
Host smart-1feec826-d783-4c55-95b7-59fc6ba10405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12315
41835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1231541835
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2354996360
Short name T195
Test name
Test status
Simulation time 11862192567 ps
CPU time 24.95 seconds
Started Jul 03 04:54:33 PM PDT 24
Finished Jul 03 04:54:59 PM PDT 24
Peak memory 206416 kb
Host smart-f0dbcd58-a015-42dd-bf6a-eabcc8c790d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23549
96360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2354996360
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.112991145
Short name T1076
Test name
Test status
Simulation time 361312793 ps
CPU time 1.24 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206108 kb
Host smart-ca3d55a4-4b60-4bfa-a075-ee8054081742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11299
1145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.112991145
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_enable.1217407011
Short name T2452
Test name
Test status
Simulation time 31526792 ps
CPU time 0.65 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206104 kb
Host smart-2d3d7afb-7f5c-4d2b-8508-42e2bf4fd323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12174
07011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1217407011
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2633010205
Short name T1215
Test name
Test status
Simulation time 844860182 ps
CPU time 2.1 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:54:38 PM PDT 24
Peak memory 206300 kb
Host smart-cde9f76b-6eea-464f-af0d-b35f268763c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26330
10205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2633010205
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2129778007
Short name T207
Test name
Test status
Simulation time 164055573 ps
CPU time 1.55 seconds
Started Jul 03 04:54:35 PM PDT 24
Finished Jul 03 04:54:37 PM PDT 24
Peak memory 206272 kb
Host smart-4e49bfb3-8d57-4ac8-91d8-043d0392966c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21297
78007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2129778007
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2907331961
Short name T1957
Test name
Test status
Simulation time 215834563 ps
CPU time 0.89 seconds
Started Jul 03 04:54:29 PM PDT 24
Finished Jul 03 04:54:30 PM PDT 24
Peak memory 206096 kb
Host smart-69f43298-ded1-4f77-bcc1-a6258d61a9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29073
31961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2907331961
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.989510325
Short name T1445
Test name
Test status
Simulation time 162799570 ps
CPU time 0.81 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206088 kb
Host smart-d2d1a289-3b3d-484a-8a5e-ccf9a3a8ed4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98951
0325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.989510325
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.194622551
Short name T2677
Test name
Test status
Simulation time 264135071 ps
CPU time 0.94 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:54:35 PM PDT 24
Peak memory 206096 kb
Host smart-50a40e28-ab25-4754-bda0-ffaa0130ed69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19462
2551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.194622551
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3686035772
Short name T2012
Test name
Test status
Simulation time 205756113 ps
CPU time 0.88 seconds
Started Jul 03 04:54:35 PM PDT 24
Finished Jul 03 04:54:36 PM PDT 24
Peak memory 206096 kb
Host smart-8a333054-9115-4b56-b3d3-5a5e8724151f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36860
35772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3686035772
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1009651201
Short name T1008
Test name
Test status
Simulation time 23391647621 ps
CPU time 24.23 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:55:08 PM PDT 24
Peak memory 206176 kb
Host smart-80b0e2f3-924b-4573-9036-1d957f13511c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10096
51201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1009651201
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1334251115
Short name T1228
Test name
Test status
Simulation time 3274849074 ps
CPU time 3.93 seconds
Started Jul 03 04:54:42 PM PDT 24
Finished Jul 03 04:54:47 PM PDT 24
Peak memory 206196 kb
Host smart-a39ebc81-9733-467d-8f46-5c79eca86b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13342
51115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1334251115
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.1663311747
Short name T1191
Test name
Test status
Simulation time 10154267973 ps
CPU time 78.44 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:55:53 PM PDT 24
Peak memory 206440 kb
Host smart-5319c3c9-2141-45b6-8b89-6bb922433416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16633
11747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1663311747
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.2389183818
Short name T2465
Test name
Test status
Simulation time 3967064623 ps
CPU time 107.77 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:56:25 PM PDT 24
Peak memory 206380 kb
Host smart-f791db78-2594-4f5c-baae-c0b92cf9836b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2389183818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.2389183818
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.371269842
Short name T1696
Test name
Test status
Simulation time 244565740 ps
CPU time 0.93 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206092 kb
Host smart-19f5fdd1-32eb-47f1-a242-a0c5ab33cbf9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=371269842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.371269842
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2703988881
Short name T502
Test name
Test status
Simulation time 196831925 ps
CPU time 0.88 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206096 kb
Host smart-932ae5ad-4a7c-4502-8e7d-fe8e6da1a805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27039
88881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2703988881
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.195495995
Short name T1596
Test name
Test status
Simulation time 5137255050 ps
CPU time 47.93 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:55:30 PM PDT 24
Peak memory 206376 kb
Host smart-fb864819-b830-4eee-8918-d8f3061b6efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19549
5995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.195495995
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3668321449
Short name T1740
Test name
Test status
Simulation time 6111014452 ps
CPU time 40.22 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:55:16 PM PDT 24
Peak memory 206396 kb
Host smart-3ff55362-4de1-4e2e-9e6d-2568edf5f54b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3668321449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3668321449
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3491906584
Short name T1157
Test name
Test status
Simulation time 156386960 ps
CPU time 0.78 seconds
Started Jul 03 04:54:42 PM PDT 24
Finished Jul 03 04:54:44 PM PDT 24
Peak memory 206128 kb
Host smart-7a1338fc-bb50-4b55-8276-65c45212e17e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3491906584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3491906584
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1414084679
Short name T512
Test name
Test status
Simulation time 159532622 ps
CPU time 0.8 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206128 kb
Host smart-5ff6c749-133b-4658-84e1-0cfb7bb1972c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14140
84679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1414084679
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.264697530
Short name T1246
Test name
Test status
Simulation time 178773245 ps
CPU time 0.89 seconds
Started Jul 03 04:54:33 PM PDT 24
Finished Jul 03 04:54:34 PM PDT 24
Peak memory 206072 kb
Host smart-b3ea760c-9702-4080-b1c0-1111506ea177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26469
7530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.264697530
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2323905100
Short name T2004
Test name
Test status
Simulation time 199230904 ps
CPU time 0.81 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206128 kb
Host smart-54fe3177-3209-4ea4-88cd-094ba3bdb184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23239
05100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2323905100
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3974005638
Short name T376
Test name
Test status
Simulation time 159662970 ps
CPU time 0.81 seconds
Started Jul 03 04:54:42 PM PDT 24
Finished Jul 03 04:54:44 PM PDT 24
Peak memory 206112 kb
Host smart-13a8ade5-adb6-44b8-a726-c8b90918ba17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39740
05638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3974005638
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.251393076
Short name T386
Test name
Test status
Simulation time 153777638 ps
CPU time 0.8 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206124 kb
Host smart-18bd4450-71e5-4f4a-8443-80248c08b7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25139
3076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.251393076
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.757286816
Short name T2430
Test name
Test status
Simulation time 230554261 ps
CPU time 0.93 seconds
Started Jul 03 04:54:42 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206112 kb
Host smart-b9179ef6-f21b-4502-b99c-5dc20d94e59d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=757286816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.757286816
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.371920371
Short name T1356
Test name
Test status
Simulation time 157822455 ps
CPU time 0.77 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206068 kb
Host smart-4be53d1f-8eaf-4046-8692-6d5bb9dd3226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37192
0371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.371920371
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.4187632229
Short name T1125
Test name
Test status
Simulation time 75922448 ps
CPU time 0.71 seconds
Started Jul 03 04:54:34 PM PDT 24
Finished Jul 03 04:54:35 PM PDT 24
Peak memory 206076 kb
Host smart-5967d6b1-7629-4a3e-a312-c80fb1b88759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41876
32229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.4187632229
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3596672256
Short name T1722
Test name
Test status
Simulation time 16772891150 ps
CPU time 38.69 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:55:21 PM PDT 24
Peak memory 206400 kb
Host smart-dc6728ef-64cb-4563-ac72-5c7df78f735a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35966
72256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3596672256
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3950496957
Short name T2616
Test name
Test status
Simulation time 188253983 ps
CPU time 0.81 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:54:38 PM PDT 24
Peak memory 206128 kb
Host smart-967c0af1-680b-4b73-b774-64e5358f5d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39504
96957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3950496957
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2867963586
Short name T2423
Test name
Test status
Simulation time 160014982 ps
CPU time 0.74 seconds
Started Jul 03 04:54:36 PM PDT 24
Finished Jul 03 04:54:37 PM PDT 24
Peak memory 206144 kb
Host smart-4cf7992d-5578-45a5-bced-a4b1649b503f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28679
63586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2867963586
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.605139020
Short name T835
Test name
Test status
Simulation time 190453370 ps
CPU time 0.89 seconds
Started Jul 03 04:54:55 PM PDT 24
Finished Jul 03 04:54:56 PM PDT 24
Peak memory 206120 kb
Host smart-7a74fc40-e455-4510-8065-df483c7deb13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60513
9020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.605139020
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3871400133
Short name T2386
Test name
Test status
Simulation time 212427833 ps
CPU time 0.82 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:43 PM PDT 24
Peak memory 206116 kb
Host smart-b0fa7740-b223-403b-adec-ce607fad76aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38714
00133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3871400133
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.80879798
Short name T2028
Test name
Test status
Simulation time 185263586 ps
CPU time 0.83 seconds
Started Jul 03 04:54:40 PM PDT 24
Finished Jul 03 04:54:42 PM PDT 24
Peak memory 206128 kb
Host smart-d632d61a-8f0d-4323-b967-02e96167aa26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80879
798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.80879798
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1539516835
Short name T769
Test name
Test status
Simulation time 174527092 ps
CPU time 0.81 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 206104 kb
Host smart-0fdd1215-3d90-4a7f-9692-94793d3bfb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15395
16835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1539516835
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1866492099
Short name T822
Test name
Test status
Simulation time 159236632 ps
CPU time 0.76 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:39 PM PDT 24
Peak memory 206128 kb
Host smart-75a073ed-fd1a-4c5e-959e-25f77b854ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18664
92099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1866492099
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3806739627
Short name T2284
Test name
Test status
Simulation time 202480897 ps
CPU time 0.9 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:54:41 PM PDT 24
Peak memory 206084 kb
Host smart-df37050c-8d89-43c6-a723-0459e0112812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38067
39627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3806739627
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.4227592836
Short name T1002
Test name
Test status
Simulation time 6411031389 ps
CPU time 45.88 seconds
Started Jul 03 04:54:39 PM PDT 24
Finished Jul 03 04:55:26 PM PDT 24
Peak memory 206376 kb
Host smart-42eeaef5-407a-4d3b-9aab-148e639ac3c9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4227592836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.4227592836
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1474863312
Short name T2041
Test name
Test status
Simulation time 162129816 ps
CPU time 0.78 seconds
Started Jul 03 04:54:32 PM PDT 24
Finished Jul 03 04:54:33 PM PDT 24
Peak memory 206132 kb
Host smart-a2697706-59b0-4d54-ba45-2741113abd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14748
63312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1474863312
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.4083638079
Short name T2508
Test name
Test status
Simulation time 182638882 ps
CPU time 0.81 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:43 PM PDT 24
Peak memory 206132 kb
Host smart-a6e78b03-30fa-413d-a54f-7b4b87f70852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40836
38079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.4083638079
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.3573949692
Short name T2296
Test name
Test status
Simulation time 1152248157 ps
CPU time 2.35 seconds
Started Jul 03 04:54:42 PM PDT 24
Finished Jul 03 04:54:46 PM PDT 24
Peak memory 206312 kb
Host smart-ba0fc94a-1972-4c1e-8849-1301236cd8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35739
49692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.3573949692
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.587061663
Short name T1631
Test name
Test status
Simulation time 3979302672 ps
CPU time 28.14 seconds
Started Jul 03 04:54:48 PM PDT 24
Finished Jul 03 04:55:17 PM PDT 24
Peak memory 206392 kb
Host smart-d16c72ec-dc41-48d3-b679-7ccce345d66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58706
1663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.587061663
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.3471159239
Short name T1368
Test name
Test status
Simulation time 49467742 ps
CPU time 0.71 seconds
Started Jul 03 04:55:02 PM PDT 24
Finished Jul 03 04:55:03 PM PDT 24
Peak memory 206168 kb
Host smart-fe2c1877-dbac-4d2f-a15f-c56648e42b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3471159239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.3471159239
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1609423098
Short name T12
Test name
Test status
Simulation time 3462130611 ps
CPU time 4.78 seconds
Started Jul 03 04:54:44 PM PDT 24
Finished Jul 03 04:54:50 PM PDT 24
Peak memory 206212 kb
Host smart-55862c13-fe14-4ffd-974d-d294a0e868cd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1609423098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.1609423098
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3203793815
Short name T1716
Test name
Test status
Simulation time 13350231382 ps
CPU time 13.06 seconds
Started Jul 03 04:54:51 PM PDT 24
Finished Jul 03 04:55:04 PM PDT 24
Peak memory 206200 kb
Host smart-3228104a-2cd6-47aa-a617-1cc234b6ebfe
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3203793815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3203793815
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1393590604
Short name T1148
Test name
Test status
Simulation time 23302222300 ps
CPU time 27.66 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:55:10 PM PDT 24
Peak memory 206460 kb
Host smart-875c02f7-4832-430e-9c5f-eca3f9bbbf54
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1393590604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.1393590604
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2521244121
Short name T1268
Test name
Test status
Simulation time 195561540 ps
CPU time 0.92 seconds
Started Jul 03 04:54:40 PM PDT 24
Finished Jul 03 04:54:42 PM PDT 24
Peak memory 206144 kb
Host smart-e747cb2d-768a-4c2e-a7a4-1d936eccbf72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25212
44121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2521244121
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2652762188
Short name T1430
Test name
Test status
Simulation time 140846875 ps
CPU time 0.8 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 205964 kb
Host smart-05edcc7d-f9fd-425f-ae08-75f882dfe848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26527
62188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2652762188
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.936388446
Short name T1213
Test name
Test status
Simulation time 473659031 ps
CPU time 1.51 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:54:46 PM PDT 24
Peak memory 206284 kb
Host smart-8ee1c4f9-1c94-4003-a286-8d81837bcc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93638
8446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.936388446
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_device_address.1323960880
Short name T1821
Test name
Test status
Simulation time 6608153177 ps
CPU time 13.41 seconds
Started Jul 03 04:54:57 PM PDT 24
Finished Jul 03 04:55:11 PM PDT 24
Peak memory 206364 kb
Host smart-c00167f1-3583-4a56-bc42-6be5c7b9f819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13239
60880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.1323960880
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.742683564
Short name T1426
Test name
Test status
Simulation time 427237658 ps
CPU time 1.36 seconds
Started Jul 03 04:54:45 PM PDT 24
Finished Jul 03 04:54:47 PM PDT 24
Peak memory 206108 kb
Host smart-1c975edd-8413-44fb-82d0-b4be6ba47c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74268
3564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.742683564
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.4248359324
Short name T971
Test name
Test status
Simulation time 141944193 ps
CPU time 0.76 seconds
Started Jul 03 04:54:49 PM PDT 24
Finished Jul 03 04:54:50 PM PDT 24
Peak memory 206136 kb
Host smart-bbd8cd21-4574-49b5-9a92-d441e0a79ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42483
59324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.4248359324
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3472694352
Short name T970
Test name
Test status
Simulation time 44377640 ps
CPU time 0.68 seconds
Started Jul 03 04:54:45 PM PDT 24
Finished Jul 03 04:54:46 PM PDT 24
Peak memory 206116 kb
Host smart-85cb6362-25b4-4c38-9236-0a92baac4167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34726
94352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3472694352
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1215041781
Short name T1739
Test name
Test status
Simulation time 856195586 ps
CPU time 2.04 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206300 kb
Host smart-81e9319e-1ea2-4dbc-993a-330938d20bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12150
41781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1215041781
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2871964972
Short name T1942
Test name
Test status
Simulation time 263115435 ps
CPU time 1.47 seconds
Started Jul 03 04:54:38 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206340 kb
Host smart-3073c717-70a7-430f-bee1-cf22cb9cbff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28719
64972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2871964972
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3781352600
Short name T121
Test name
Test status
Simulation time 180233830 ps
CPU time 0.81 seconds
Started Jul 03 04:54:44 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206116 kb
Host smart-3fc25627-6e0b-415a-a093-ae1c1ed752dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37813
52600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3781352600
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.4095137458
Short name T1731
Test name
Test status
Simulation time 143531148 ps
CPU time 0.76 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:43 PM PDT 24
Peak memory 206128 kb
Host smart-d7abe743-81db-4d1b-bc50-1ff54d42b14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40951
37458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4095137458
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1354446423
Short name T1565
Test name
Test status
Simulation time 235798565 ps
CPU time 0.94 seconds
Started Jul 03 04:54:52 PM PDT 24
Finished Jul 03 04:54:54 PM PDT 24
Peak memory 206132 kb
Host smart-37c64e92-29c7-4ea6-ae70-3a9fb8a20511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13544
46423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1354446423
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.249664876
Short name T1863
Test name
Test status
Simulation time 5805368448 ps
CPU time 152.98 seconds
Started Jul 03 04:54:54 PM PDT 24
Finished Jul 03 04:57:27 PM PDT 24
Peak memory 206388 kb
Host smart-2cfe3c65-2287-4cc3-be4c-ecfb756fd457
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=249664876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.249664876
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1644874394
Short name T1176
Test name
Test status
Simulation time 174385381 ps
CPU time 0.8 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206096 kb
Host smart-9647086d-e0fc-4bc0-88a2-c488623f6fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16448
74394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1644874394
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.613563550
Short name T2455
Test name
Test status
Simulation time 23355684744 ps
CPU time 29.59 seconds
Started Jul 03 04:54:40 PM PDT 24
Finished Jul 03 04:55:11 PM PDT 24
Peak memory 206160 kb
Host smart-3bd94e75-c564-4dfa-83f1-6d768f3876fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61356
3550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.613563550
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2740913218
Short name T2180
Test name
Test status
Simulation time 3307784751 ps
CPU time 3.99 seconds
Started Jul 03 04:54:37 PM PDT 24
Finished Jul 03 04:54:42 PM PDT 24
Peak memory 206160 kb
Host smart-40f73aae-5265-4cb0-ad3e-0186dde083b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27409
13218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2740913218
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3520386606
Short name T909
Test name
Test status
Simulation time 9651768725 ps
CPU time 72.98 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:55:57 PM PDT 24
Peak memory 206432 kb
Host smart-3103eee9-c76b-4cee-a83d-29e60c674cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35203
86606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3520386606
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.55902379
Short name T154
Test name
Test status
Simulation time 5301163894 ps
CPU time 36.5 seconds
Started Jul 03 04:54:44 PM PDT 24
Finished Jul 03 04:55:22 PM PDT 24
Peak memory 206392 kb
Host smart-632d2dc8-2cac-4e7b-8d42-814dc12c129b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=55902379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.55902379
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1719804356
Short name T2127
Test name
Test status
Simulation time 235471800 ps
CPU time 0.91 seconds
Started Jul 03 04:54:40 PM PDT 24
Finished Jul 03 04:54:42 PM PDT 24
Peak memory 206084 kb
Host smart-aeadba62-2099-435e-beb2-2765a4c1fee5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1719804356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1719804356
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2913671292
Short name T2409
Test name
Test status
Simulation time 184703858 ps
CPU time 0.81 seconds
Started Jul 03 04:54:44 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206096 kb
Host smart-629e46c8-6279-4511-96df-f6aae897fce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29136
71292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2913671292
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2491272480
Short name T509
Test name
Test status
Simulation time 5884716259 ps
CPU time 157.08 seconds
Started Jul 03 04:54:46 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206368 kb
Host smart-cf8de3a7-c48d-45c4-97c6-12951b03b86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24912
72480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2491272480
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1935816724
Short name T832
Test name
Test status
Simulation time 4069332388 ps
CPU time 28.89 seconds
Started Jul 03 04:54:48 PM PDT 24
Finished Jul 03 04:55:17 PM PDT 24
Peak memory 206356 kb
Host smart-66499662-6e38-44f6-bad9-789684d34760
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1935816724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1935816724
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.580197763
Short name T2091
Test name
Test status
Simulation time 164877262 ps
CPU time 0.84 seconds
Started Jul 03 04:54:51 PM PDT 24
Finished Jul 03 04:54:52 PM PDT 24
Peak memory 206116 kb
Host smart-9b7e1dcc-5780-40c1-a4f5-86e2fd0b88ff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=580197763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.580197763
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.376042097
Short name T2042
Test name
Test status
Simulation time 146035655 ps
CPU time 0.76 seconds
Started Jul 03 04:54:45 PM PDT 24
Finished Jul 03 04:54:46 PM PDT 24
Peak memory 206028 kb
Host smart-7901a3f0-5cd6-41b5-8f73-46eb0f7aafa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37604
2097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.376042097
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1472317083
Short name T141
Test name
Test status
Simulation time 208480766 ps
CPU time 0.86 seconds
Started Jul 03 04:54:41 PM PDT 24
Finished Jul 03 04:54:44 PM PDT 24
Peak memory 206112 kb
Host smart-921b376c-4eea-4e06-94d4-f00c280d16f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14723
17083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1472317083
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.2079270793
Short name T2173
Test name
Test status
Simulation time 156233181 ps
CPU time 0.83 seconds
Started Jul 03 04:54:49 PM PDT 24
Finished Jul 03 04:54:50 PM PDT 24
Peak memory 206088 kb
Host smart-33fed17f-9228-40aa-9ec8-4886def266bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20792
70793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2079270793
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3377768233
Short name T1504
Test name
Test status
Simulation time 189637992 ps
CPU time 0.82 seconds
Started Jul 03 04:54:47 PM PDT 24
Finished Jul 03 04:54:48 PM PDT 24
Peak memory 205960 kb
Host smart-cc7beb7c-e469-4d25-8fdf-306e78f6575c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33777
68233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3377768233
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1830308422
Short name T1196
Test name
Test status
Simulation time 182114611 ps
CPU time 0.79 seconds
Started Jul 03 04:55:12 PM PDT 24
Finished Jul 03 04:55:13 PM PDT 24
Peak memory 206096 kb
Host smart-f528a18d-45f5-4db7-a1cd-e64467331407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18303
08422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1830308422
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3319406083
Short name T829
Test name
Test status
Simulation time 165569310 ps
CPU time 0.81 seconds
Started Jul 03 04:54:59 PM PDT 24
Finished Jul 03 04:55:00 PM PDT 24
Peak memory 206112 kb
Host smart-d682839b-459b-47f4-abd9-ef596f299cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33194
06083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3319406083
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.579468650
Short name T1447
Test name
Test status
Simulation time 242115066 ps
CPU time 0.93 seconds
Started Jul 03 04:54:47 PM PDT 24
Finished Jul 03 04:54:49 PM PDT 24
Peak memory 206136 kb
Host smart-f7c13f4b-52b8-451b-bda9-2974bdbb21b6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=579468650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.579468650
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3644123816
Short name T842
Test name
Test status
Simulation time 151835003 ps
CPU time 0.82 seconds
Started Jul 03 04:54:52 PM PDT 24
Finished Jul 03 04:54:53 PM PDT 24
Peak memory 205980 kb
Host smart-683445d1-f8b0-401f-907e-5c94cb22f527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36441
23816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3644123816
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2968106363
Short name T482
Test name
Test status
Simulation time 54373802 ps
CPU time 0.68 seconds
Started Jul 03 04:54:47 PM PDT 24
Finished Jul 03 04:54:48 PM PDT 24
Peak memory 205952 kb
Host smart-0bcd625c-8556-475d-97ab-addb6fce7311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29681
06363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2968106363
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1486668019
Short name T240
Test name
Test status
Simulation time 20345735784 ps
CPU time 45.33 seconds
Started Jul 03 04:54:45 PM PDT 24
Finished Jul 03 04:55:31 PM PDT 24
Peak memory 214596 kb
Host smart-15df49d2-a1ce-401e-991e-3ef0fc75627c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14866
68019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1486668019
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1734431556
Short name T1932
Test name
Test status
Simulation time 189217943 ps
CPU time 0.84 seconds
Started Jul 03 04:55:03 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206108 kb
Host smart-d66df6b5-e809-40b4-8bb6-bf43b5787c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17344
31556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1734431556
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2264621967
Short name T973
Test name
Test status
Simulation time 198053810 ps
CPU time 0.85 seconds
Started Jul 03 04:54:48 PM PDT 24
Finished Jul 03 04:54:50 PM PDT 24
Peak memory 206108 kb
Host smart-6752fe47-f8ca-4345-b984-238a241ad756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22646
21967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2264621967
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2284658583
Short name T1532
Test name
Test status
Simulation time 217943860 ps
CPU time 0.91 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206076 kb
Host smart-e67c82d7-2a27-4a7d-a8d5-4bbfc643f7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22846
58583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2284658583
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3551867118
Short name T1958
Test name
Test status
Simulation time 181124327 ps
CPU time 0.89 seconds
Started Jul 03 04:54:43 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206140 kb
Host smart-753f9f07-ba2f-4dfa-b914-1fcdffc0d8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35518
67118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3551867118
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.4003965845
Short name T2067
Test name
Test status
Simulation time 175813570 ps
CPU time 0.81 seconds
Started Jul 03 04:54:52 PM PDT 24
Finished Jul 03 04:54:54 PM PDT 24
Peak memory 206112 kb
Host smart-96bff4e0-01c6-4a7a-aaef-bc9a4efa292e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40039
65845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.4003965845
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3999448233
Short name T2562
Test name
Test status
Simulation time 187246306 ps
CPU time 0.8 seconds
Started Jul 03 04:55:11 PM PDT 24
Finished Jul 03 04:55:12 PM PDT 24
Peak memory 206140 kb
Host smart-5e65a9c0-ac4a-45b2-8d7d-6c91174a7a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39994
48233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3999448233
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1706602832
Short name T2515
Test name
Test status
Simulation time 182895007 ps
CPU time 0.84 seconds
Started Jul 03 04:54:49 PM PDT 24
Finished Jul 03 04:54:51 PM PDT 24
Peak memory 206088 kb
Host smart-96dc103f-4a4e-4678-9526-9c1d52e1f704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17066
02832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1706602832
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2138241877
Short name T1207
Test name
Test status
Simulation time 245307697 ps
CPU time 1.01 seconds
Started Jul 03 04:54:51 PM PDT 24
Finished Jul 03 04:54:53 PM PDT 24
Peak memory 206080 kb
Host smart-9fdc9930-c100-404d-88a0-e514c81067fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21382
41877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2138241877
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.1379560390
Short name T2580
Test name
Test status
Simulation time 7168954550 ps
CPU time 63.01 seconds
Started Jul 03 04:55:13 PM PDT 24
Finished Jul 03 04:56:17 PM PDT 24
Peak memory 206396 kb
Host smart-6b6ee200-bec9-4155-8b52-70c9e6cd71ea
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1379560390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.1379560390
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3808649034
Short name T1475
Test name
Test status
Simulation time 181545739 ps
CPU time 0.84 seconds
Started Jul 03 04:54:47 PM PDT 24
Finished Jul 03 04:54:49 PM PDT 24
Peak memory 206076 kb
Host smart-b5fbabd1-9794-4813-888d-8f57267a54fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38086
49034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3808649034
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.523050260
Short name T2493
Test name
Test status
Simulation time 167314243 ps
CPU time 0.81 seconds
Started Jul 03 04:55:05 PM PDT 24
Finished Jul 03 04:55:06 PM PDT 24
Peak memory 206132 kb
Host smart-2b2a1912-5bcb-4610-b4f0-e1c4cd5736cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52305
0260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.523050260
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.2024972985
Short name T1004
Test name
Test status
Simulation time 1011677787 ps
CPU time 2.17 seconds
Started Jul 03 04:55:03 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206344 kb
Host smart-6d16d147-d84e-4d81-b564-d67c58c709c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20249
72985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.2024972985
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3542419199
Short name T1240
Test name
Test status
Simulation time 4179993715 ps
CPU time 115.43 seconds
Started Jul 03 04:55:10 PM PDT 24
Finished Jul 03 04:57:06 PM PDT 24
Peak memory 206396 kb
Host smart-391ee61b-dfb7-4fd7-b7b4-6a44bbdb4cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35424
19199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3542419199
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.806981340
Short name T2259
Test name
Test status
Simulation time 33972865 ps
CPU time 0.67 seconds
Started Jul 03 04:54:54 PM PDT 24
Finished Jul 03 04:54:55 PM PDT 24
Peak memory 206156 kb
Host smart-d9aaad92-d0ca-442e-9749-9b20b1b882f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=806981340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.806981340
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3801873292
Short name T947
Test name
Test status
Simulation time 4132202316 ps
CPU time 4.74 seconds
Started Jul 03 04:55:06 PM PDT 24
Finished Jul 03 04:55:11 PM PDT 24
Peak memory 206192 kb
Host smart-fdadd404-3a69-423f-a7a8-a553387791ea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3801873292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.3801873292
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.4098539389
Short name T1668
Test name
Test status
Simulation time 13334722119 ps
CPU time 12.59 seconds
Started Jul 03 04:54:50 PM PDT 24
Finished Jul 03 04:55:04 PM PDT 24
Peak memory 206136 kb
Host smart-8af40591-9cbf-4ddd-8991-e11e36d8928f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4098539389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.4098539389
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.906215014
Short name T573
Test name
Test status
Simulation time 23354936471 ps
CPU time 24.09 seconds
Started Jul 03 04:55:05 PM PDT 24
Finished Jul 03 04:55:30 PM PDT 24
Peak memory 206196 kb
Host smart-86b3b9db-5553-41a7-b21c-d9fd889b693f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=906215014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.906215014
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1764990499
Short name T727
Test name
Test status
Simulation time 164926239 ps
CPU time 0.86 seconds
Started Jul 03 04:54:52 PM PDT 24
Finished Jul 03 04:54:53 PM PDT 24
Peak memory 206080 kb
Host smart-a096d6de-dd69-4522-a59c-46fe1bfc7e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17649
90499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1764990499
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2718403265
Short name T2682
Test name
Test status
Simulation time 146494253 ps
CPU time 0.78 seconds
Started Jul 03 04:55:14 PM PDT 24
Finished Jul 03 04:55:15 PM PDT 24
Peak memory 206108 kb
Host smart-4d61795b-4aae-46e3-a310-2006afefedbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27184
03265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2718403265
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2138934155
Short name T2561
Test name
Test status
Simulation time 424211195 ps
CPU time 1.41 seconds
Started Jul 03 04:55:13 PM PDT 24
Finished Jul 03 04:55:15 PM PDT 24
Peak memory 206040 kb
Host smart-d194f224-0760-4131-ae39-b55686e58c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21389
34155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2138934155
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1778021118
Short name T2403
Test name
Test status
Simulation time 1019726769 ps
CPU time 2.3 seconds
Started Jul 03 04:54:59 PM PDT 24
Finished Jul 03 04:55:02 PM PDT 24
Peak memory 206396 kb
Host smart-63a3411d-f0ea-4ad3-8ac5-7cc0ea3df36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17780
21118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1778021118
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1132893171
Short name T1815
Test name
Test status
Simulation time 11382757929 ps
CPU time 20.84 seconds
Started Jul 03 04:55:03 PM PDT 24
Finished Jul 03 04:55:24 PM PDT 24
Peak memory 206388 kb
Host smart-047efb73-3e33-4c28-8edc-a7a18e78c9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11328
93171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1132893171
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1169278187
Short name T2005
Test name
Test status
Simulation time 467666948 ps
CPU time 1.4 seconds
Started Jul 03 04:54:50 PM PDT 24
Finished Jul 03 04:54:52 PM PDT 24
Peak memory 206056 kb
Host smart-2e421921-7a73-46e2-af74-51515ce1e308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11692
78187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1169278187
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2071178934
Short name T427
Test name
Test status
Simulation time 138733398 ps
CPU time 0.83 seconds
Started Jul 03 04:55:00 PM PDT 24
Finished Jul 03 04:55:01 PM PDT 24
Peak memory 206096 kb
Host smart-9815de5d-3206-4743-8843-1487d199c274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20711
78934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2071178934
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.696109148
Short name T966
Test name
Test status
Simulation time 33060101 ps
CPU time 0.64 seconds
Started Jul 03 04:54:56 PM PDT 24
Finished Jul 03 04:54:57 PM PDT 24
Peak memory 206124 kb
Host smart-bdc992fa-f339-43a8-88e9-a8f881d9cab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69610
9148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.696109148
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3136318997
Short name T2097
Test name
Test status
Simulation time 978423839 ps
CPU time 2.31 seconds
Started Jul 03 04:54:59 PM PDT 24
Finished Jul 03 04:55:02 PM PDT 24
Peak memory 206344 kb
Host smart-8cd2dc7f-583e-4ffe-86ef-d30c5ce9de50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31363
18997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3136318997
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3466253924
Short name T1871
Test name
Test status
Simulation time 186135199 ps
CPU time 1.51 seconds
Started Jul 03 04:55:00 PM PDT 24
Finished Jul 03 04:55:02 PM PDT 24
Peak memory 206320 kb
Host smart-603109d6-30ba-4e37-9357-b4d48ca28c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34662
53924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3466253924
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2638746457
Short name T1093
Test name
Test status
Simulation time 248639715 ps
CPU time 1.03 seconds
Started Jul 03 04:55:02 PM PDT 24
Finished Jul 03 04:55:04 PM PDT 24
Peak memory 206088 kb
Host smart-475edc92-f5ef-481e-b6cc-74bcb6301e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26387
46457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2638746457
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.195339881
Short name T1419
Test name
Test status
Simulation time 200439222 ps
CPU time 0.77 seconds
Started Jul 03 04:54:44 PM PDT 24
Finished Jul 03 04:54:46 PM PDT 24
Peak memory 206120 kb
Host smart-b9ed33e1-97f5-4c32-b623-ec2b08771a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19533
9881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.195339881
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3119507193
Short name T856
Test name
Test status
Simulation time 185864010 ps
CPU time 0.79 seconds
Started Jul 03 04:55:04 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206128 kb
Host smart-de28765a-a0d8-4895-8fce-bd91b4d09b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31195
07193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3119507193
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3962726
Short name T566
Test name
Test status
Simulation time 209180386 ps
CPU time 0.86 seconds
Started Jul 03 04:54:59 PM PDT 24
Finished Jul 03 04:55:00 PM PDT 24
Peak memory 206088 kb
Host smart-c1f75bb0-137f-4d8b-82bf-3fa79b4758c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39627
26 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3962726
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.618173198
Short name T1580
Test name
Test status
Simulation time 23279086689 ps
CPU time 27.43 seconds
Started Jul 03 04:55:02 PM PDT 24
Finished Jul 03 04:55:30 PM PDT 24
Peak memory 206140 kb
Host smart-b95b12f4-11da-4faa-8fc2-41daf49e581d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61817
3198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.618173198
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2115401059
Short name T363
Test name
Test status
Simulation time 3364229293 ps
CPU time 3.8 seconds
Started Jul 03 04:55:08 PM PDT 24
Finished Jul 03 04:55:12 PM PDT 24
Peak memory 206196 kb
Host smart-b5669481-4cb7-48e2-b241-17c3327a3773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21154
01059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2115401059
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.272186780
Short name T494
Test name
Test status
Simulation time 7570646435 ps
CPU time 56.31 seconds
Started Jul 03 04:54:49 PM PDT 24
Finished Jul 03 04:55:46 PM PDT 24
Peak memory 206416 kb
Host smart-e1b26c64-7d80-4fa6-afe2-e8826830131c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27218
6780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.272186780
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2257150847
Short name T1521
Test name
Test status
Simulation time 4751904466 ps
CPU time 131.43 seconds
Started Jul 03 04:55:11 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206324 kb
Host smart-1c0fba68-2b2f-48b9-bac1-81e4d99c2dd5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2257150847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2257150847
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.561327546
Short name T2381
Test name
Test status
Simulation time 264091910 ps
CPU time 0.91 seconds
Started Jul 03 04:54:56 PM PDT 24
Finished Jul 03 04:54:57 PM PDT 24
Peak memory 206128 kb
Host smart-a4d4cc36-9b09-47bc-a5d7-e0439e3bfbc4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=561327546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.561327546
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2082677117
Short name T454
Test name
Test status
Simulation time 186853279 ps
CPU time 0.85 seconds
Started Jul 03 04:54:49 PM PDT 24
Finished Jul 03 04:54:51 PM PDT 24
Peak memory 206076 kb
Host smart-f003fa7d-aee4-4f53-8dfb-cdda18074ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20826
77117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2082677117
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.1083435625
Short name T411
Test name
Test status
Simulation time 6034458539 ps
CPU time 168.48 seconds
Started Jul 03 04:54:56 PM PDT 24
Finished Jul 03 04:57:44 PM PDT 24
Peak memory 206340 kb
Host smart-18786e5a-050f-4b2a-b78c-8e70baa5a281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10834
35625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.1083435625
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1373044680
Short name T2578
Test name
Test status
Simulation time 5458282526 ps
CPU time 36.74 seconds
Started Jul 03 04:55:02 PM PDT 24
Finished Jul 03 04:55:39 PM PDT 24
Peak memory 206288 kb
Host smart-4d21d52c-06d8-4ff6-bb7a-eab053a1921d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1373044680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1373044680
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.575066687
Short name T1493
Test name
Test status
Simulation time 152164650 ps
CPU time 0.83 seconds
Started Jul 03 04:54:57 PM PDT 24
Finished Jul 03 04:54:58 PM PDT 24
Peak memory 206116 kb
Host smart-0e06e10c-675e-4462-b20e-5bfeb4006012
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=575066687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.575066687
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1460972018
Short name T875
Test name
Test status
Simulation time 145261964 ps
CPU time 0.76 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:18 PM PDT 24
Peak memory 206020 kb
Host smart-54b05b25-bed9-4041-beb5-8ad9a37a0819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14609
72018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1460972018
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3645976917
Short name T1262
Test name
Test status
Simulation time 190261511 ps
CPU time 0.82 seconds
Started Jul 03 04:55:01 PM PDT 24
Finished Jul 03 04:55:02 PM PDT 24
Peak memory 206036 kb
Host smart-94baf7e7-9e15-4b61-9379-e2bd506630e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
76917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3645976917
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1228670937
Short name T1649
Test name
Test status
Simulation time 167918288 ps
CPU time 0.81 seconds
Started Jul 03 04:55:01 PM PDT 24
Finished Jul 03 04:55:02 PM PDT 24
Peak memory 206088 kb
Host smart-19f24791-d928-4f9b-ab72-f95529a4f984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12286
70937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1228670937
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.920860781
Short name T749
Test name
Test status
Simulation time 152372158 ps
CPU time 0.77 seconds
Started Jul 03 04:54:53 PM PDT 24
Finished Jul 03 04:54:54 PM PDT 24
Peak memory 206052 kb
Host smart-4f6a0e09-704c-4985-916e-90dd465dd628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92086
0781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.920860781
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3312081538
Short name T2387
Test name
Test status
Simulation time 195206848 ps
CPU time 0.8 seconds
Started Jul 03 04:55:01 PM PDT 24
Finished Jul 03 04:55:02 PM PDT 24
Peak memory 206132 kb
Host smart-11f130b8-a733-449a-9f02-41bee0d323e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33120
81538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3312081538
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.661307356
Short name T1647
Test name
Test status
Simulation time 142729304 ps
CPU time 0.75 seconds
Started Jul 03 04:55:03 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206052 kb
Host smart-1bd0c7ba-af56-47a7-841d-3a2e40d213c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66130
7356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.661307356
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.227082520
Short name T1155
Test name
Test status
Simulation time 260071414 ps
CPU time 0.94 seconds
Started Jul 03 04:54:50 PM PDT 24
Finished Jul 03 04:54:52 PM PDT 24
Peak memory 206144 kb
Host smart-1f5cacb4-c996-43f8-a37e-4e19e13eaa99
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=227082520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.227082520
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.570163763
Short name T445
Test name
Test status
Simulation time 145999356 ps
CPU time 0.76 seconds
Started Jul 03 04:54:54 PM PDT 24
Finished Jul 03 04:54:55 PM PDT 24
Peak memory 206080 kb
Host smart-0e46df29-33d3-4b93-b2fa-f3a75c9c177c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57016
3763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.570163763
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2626702305
Short name T505
Test name
Test status
Simulation time 36079328 ps
CPU time 0.64 seconds
Started Jul 03 04:55:02 PM PDT 24
Finished Jul 03 04:55:03 PM PDT 24
Peak memory 206032 kb
Host smart-19ad8514-2162-4684-bb6a-73bb813b60f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26267
02305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2626702305
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1419440020
Short name T1469
Test name
Test status
Simulation time 202954302 ps
CPU time 0.83 seconds
Started Jul 03 04:54:52 PM PDT 24
Finished Jul 03 04:54:54 PM PDT 24
Peak memory 206080 kb
Host smart-cac2b75a-cbbc-47f6-8efe-1a5412f104d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14194
40020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1419440020
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2764375362
Short name T1225
Test name
Test status
Simulation time 245105300 ps
CPU time 0.94 seconds
Started Jul 03 04:55:06 PM PDT 24
Finished Jul 03 04:55:07 PM PDT 24
Peak memory 206096 kb
Host smart-1f087d75-7a98-440c-ba5e-0749452c9ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27643
75362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2764375362
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.4013638709
Short name T1594
Test name
Test status
Simulation time 168177338 ps
CPU time 0.79 seconds
Started Jul 03 04:55:03 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206072 kb
Host smart-cb05a668-d356-46e6-bb32-89c428d510ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40136
38709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.4013638709
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.270459283
Short name T474
Test name
Test status
Simulation time 144810768 ps
CPU time 0.78 seconds
Started Jul 03 04:54:53 PM PDT 24
Finished Jul 03 04:54:54 PM PDT 24
Peak memory 206052 kb
Host smart-fb5882a7-4b5d-40ff-8da6-d6e5f5b1ad65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27045
9283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.270459283
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1149466073
Short name T2355
Test name
Test status
Simulation time 214200683 ps
CPU time 0.87 seconds
Started Jul 03 04:55:03 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206100 kb
Host smart-bb3e8174-486a-495f-a84e-81e8b89427e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11494
66073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1149466073
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.4241932263
Short name T2572
Test name
Test status
Simulation time 153224007 ps
CPU time 0.78 seconds
Started Jul 03 04:55:18 PM PDT 24
Finished Jul 03 04:55:19 PM PDT 24
Peak memory 206112 kb
Host smart-69aece16-3a4b-4297-8a5b-14adedc4ee3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42419
32263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.4241932263
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2904625760
Short name T555
Test name
Test status
Simulation time 156721929 ps
CPU time 0.81 seconds
Started Jul 03 04:55:11 PM PDT 24
Finished Jul 03 04:55:12 PM PDT 24
Peak memory 206136 kb
Host smart-791622f0-ad26-4ad9-9ea8-2512c475e9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29046
25760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2904625760
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.59070384
Short name T2697
Test name
Test status
Simulation time 189855310 ps
CPU time 0.91 seconds
Started Jul 03 04:54:53 PM PDT 24
Finished Jul 03 04:54:55 PM PDT 24
Peak memory 206052 kb
Host smart-fb2a6a15-faa1-496e-bfbb-f2b5e97c3a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59070
384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.59070384
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1143368950
Short name T927
Test name
Test status
Simulation time 5711370059 ps
CPU time 53.84 seconds
Started Jul 03 04:55:02 PM PDT 24
Finished Jul 03 04:55:56 PM PDT 24
Peak memory 206384 kb
Host smart-9eaf22a5-5520-4016-b3cc-1fb77b0c0150
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1143368950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1143368950
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.4208132406
Short name T2002
Test name
Test status
Simulation time 189443294 ps
CPU time 0.82 seconds
Started Jul 03 04:54:51 PM PDT 24
Finished Jul 03 04:54:52 PM PDT 24
Peak memory 206100 kb
Host smart-ae646a6a-abd6-4ed2-aa29-01ab3c1f24aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42081
32406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.4208132406
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2622507127
Short name T2011
Test name
Test status
Simulation time 191431220 ps
CPU time 0.89 seconds
Started Jul 03 04:54:49 PM PDT 24
Finished Jul 03 04:54:51 PM PDT 24
Peak memory 206132 kb
Host smart-f68fc47a-b455-46df-93a5-46d160570335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
07127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2622507127
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.2883635703
Short name T1880
Test name
Test status
Simulation time 812893559 ps
CPU time 1.8 seconds
Started Jul 03 04:55:07 PM PDT 24
Finished Jul 03 04:55:10 PM PDT 24
Peak memory 206312 kb
Host smart-8bf1b766-378f-4a06-b1e7-7b335fdc71b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28836
35703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.2883635703
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1645536995
Short name T1192
Test name
Test status
Simulation time 4154473486 ps
CPU time 29.25 seconds
Started Jul 03 04:54:58 PM PDT 24
Finished Jul 03 04:55:28 PM PDT 24
Peak memory 206448 kb
Host smart-b886eed5-5761-4260-a2c3-98692a39960d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16455
36995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1645536995
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.2356190104
Short name T209
Test name
Test status
Simulation time 51229841 ps
CPU time 0.71 seconds
Started Jul 03 04:54:58 PM PDT 24
Finished Jul 03 04:54:59 PM PDT 24
Peak memory 206112 kb
Host smart-01e00c59-758a-406d-a3a5-59c00e86de97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2356190104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2356190104
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.4274741038
Short name T9
Test name
Test status
Simulation time 3805480429 ps
CPU time 4.65 seconds
Started Jul 03 04:55:18 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206180 kb
Host smart-2f93e9b5-8c5f-4667-a1ec-bf3e541ce196
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4274741038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.4274741038
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2570393363
Short name T2659
Test name
Test status
Simulation time 13336804274 ps
CPU time 12.84 seconds
Started Jul 03 04:54:55 PM PDT 24
Finished Jul 03 04:55:08 PM PDT 24
Peak memory 206064 kb
Host smart-3de4e51b-2e93-472d-996f-2e0d8514ca90
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2570393363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2570393363
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3096595651
Short name T1107
Test name
Test status
Simulation time 23421584031 ps
CPU time 28.52 seconds
Started Jul 03 04:55:02 PM PDT 24
Finished Jul 03 04:55:31 PM PDT 24
Peak memory 206384 kb
Host smart-982ac145-2e32-4788-a24e-094af930bb5b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3096595651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.3096595651
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.214959024
Short name T451
Test name
Test status
Simulation time 170321803 ps
CPU time 0.83 seconds
Started Jul 03 04:55:05 PM PDT 24
Finished Jul 03 04:55:06 PM PDT 24
Peak memory 206128 kb
Host smart-e3ba7d8c-7400-45eb-a14f-c093e14258aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21495
9024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.214959024
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2325499575
Short name T661
Test name
Test status
Simulation time 174799834 ps
CPU time 0.79 seconds
Started Jul 03 04:54:59 PM PDT 24
Finished Jul 03 04:55:00 PM PDT 24
Peak memory 206140 kb
Host smart-738f773d-a034-49c7-a48f-16024ad99850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23254
99575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2325499575
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.963576616
Short name T1546
Test name
Test status
Simulation time 234552975 ps
CPU time 0.89 seconds
Started Jul 03 04:55:06 PM PDT 24
Finished Jul 03 04:55:07 PM PDT 24
Peak memory 206024 kb
Host smart-f81aaeb9-e7cb-4766-a926-4401e2c19d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96357
6616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.963576616
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2632521749
Short name T1375
Test name
Test status
Simulation time 900839035 ps
CPU time 2.23 seconds
Started Jul 03 04:55:10 PM PDT 24
Finished Jul 03 04:55:12 PM PDT 24
Peak memory 206320 kb
Host smart-4cf1ab1c-3281-452c-b506-7d50dabbc6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26325
21749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2632521749
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.736979510
Short name T181
Test name
Test status
Simulation time 5895855711 ps
CPU time 10.97 seconds
Started Jul 03 04:55:10 PM PDT 24
Finished Jul 03 04:55:21 PM PDT 24
Peak memory 206684 kb
Host smart-1b25e720-cafa-465a-8075-fae0beca3a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73697
9510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.736979510
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1453491125
Short name T357
Test name
Test status
Simulation time 394160631 ps
CPU time 1.3 seconds
Started Jul 03 04:54:56 PM PDT 24
Finished Jul 03 04:54:57 PM PDT 24
Peak memory 206092 kb
Host smart-496c5463-35f8-44c2-b3d0-8a11c7f503e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14534
91125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1453491125
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1923244391
Short name T2556
Test name
Test status
Simulation time 224074557 ps
CPU time 0.89 seconds
Started Jul 03 04:55:07 PM PDT 24
Finished Jul 03 04:55:09 PM PDT 24
Peak memory 206136 kb
Host smart-a33d4dab-5b9f-412d-8e73-85b55fe2476c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19232
44391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1923244391
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.556419014
Short name T1568
Test name
Test status
Simulation time 58705318 ps
CPU time 0.7 seconds
Started Jul 03 04:54:53 PM PDT 24
Finished Jul 03 04:54:54 PM PDT 24
Peak memory 206136 kb
Host smart-dfc4a1a1-5648-4fef-9295-bf858e119f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55641
9014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.556419014
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3634816926
Short name T545
Test name
Test status
Simulation time 889692117 ps
CPU time 2.21 seconds
Started Jul 03 04:55:00 PM PDT 24
Finished Jul 03 04:55:02 PM PDT 24
Peak memory 206576 kb
Host smart-591e50e1-fc2e-4337-af9f-fee977ed1e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36348
16926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3634816926
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2270187592
Short name T2688
Test name
Test status
Simulation time 184986905 ps
CPU time 1.9 seconds
Started Jul 03 04:54:58 PM PDT 24
Finished Jul 03 04:55:00 PM PDT 24
Peak memory 206312 kb
Host smart-4e3c18c1-dd8c-48ff-b2d6-62c50f260a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22701
87592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2270187592
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1388416884
Short name T2277
Test name
Test status
Simulation time 156129581 ps
CPU time 0.8 seconds
Started Jul 03 04:54:53 PM PDT 24
Finished Jul 03 04:54:55 PM PDT 24
Peak memory 206084 kb
Host smart-9fd70166-a0af-4044-981e-83b353d7f36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13884
16884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1388416884
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3831071307
Short name T2437
Test name
Test status
Simulation time 158044929 ps
CPU time 0.76 seconds
Started Jul 03 04:54:53 PM PDT 24
Finished Jul 03 04:54:55 PM PDT 24
Peak memory 206088 kb
Host smart-4b156282-aa06-452e-813d-36dd76147a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38310
71307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3831071307
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.372535750
Short name T938
Test name
Test status
Simulation time 242320389 ps
CPU time 0.9 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206092 kb
Host smart-9879933e-8f5a-475d-b5f0-67d4f65a477a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37253
5750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.372535750
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.1171013163
Short name T685
Test name
Test status
Simulation time 223565086 ps
CPU time 1.16 seconds
Started Jul 03 04:54:51 PM PDT 24
Finished Jul 03 04:54:52 PM PDT 24
Peak memory 206124 kb
Host smart-0dee0292-84db-401b-b121-1a6fa78fdc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11710
13163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1171013163
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2259323545
Short name T868
Test name
Test status
Simulation time 23278039237 ps
CPU time 21.65 seconds
Started Jul 03 04:55:07 PM PDT 24
Finished Jul 03 04:55:29 PM PDT 24
Peak memory 206444 kb
Host smart-060b7760-3811-41f0-95ef-650138cb0d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
23545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2259323545
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.3992444974
Short name T1303
Test name
Test status
Simulation time 3343036980 ps
CPU time 3.87 seconds
Started Jul 03 04:55:08 PM PDT 24
Finished Jul 03 04:55:12 PM PDT 24
Peak memory 206068 kb
Host smart-5f48acba-f8f1-4319-ada7-7c8c14845d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39924
44974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.3992444974
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.414648107
Short name T448
Test name
Test status
Simulation time 11849242129 ps
CPU time 110.04 seconds
Started Jul 03 04:55:10 PM PDT 24
Finished Jul 03 04:57:01 PM PDT 24
Peak memory 206424 kb
Host smart-f1c65534-6345-4e55-9552-0e63c571f411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41464
8107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.414648107
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.285198075
Short name T2585
Test name
Test status
Simulation time 4485045151 ps
CPU time 117.26 seconds
Started Jul 03 04:55:10 PM PDT 24
Finished Jul 03 04:57:08 PM PDT 24
Peak memory 206340 kb
Host smart-0c5a1df8-963c-4b51-97b2-6cf1b12983cb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=285198075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.285198075
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2516377665
Short name T880
Test name
Test status
Simulation time 271090023 ps
CPU time 0.96 seconds
Started Jul 03 04:54:54 PM PDT 24
Finished Jul 03 04:54:55 PM PDT 24
Peak memory 206000 kb
Host smart-23820dda-79bc-4dd8-8f66-b9f8d7fee7ec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2516377665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2516377665
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1742841053
Short name T2327
Test name
Test status
Simulation time 192926204 ps
CPU time 0.87 seconds
Started Jul 03 04:55:00 PM PDT 24
Finished Jul 03 04:55:01 PM PDT 24
Peak memory 206044 kb
Host smart-5c1bc164-43aa-4150-bce0-eea5da3ff683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17428
41053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1742841053
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.3618181657
Short name T1451
Test name
Test status
Simulation time 3579204720 ps
CPU time 98.64 seconds
Started Jul 03 04:54:52 PM PDT 24
Finished Jul 03 04:56:31 PM PDT 24
Peak memory 206424 kb
Host smart-8b945ab2-c739-47f0-b4c3-fb292ebe484d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36181
81657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.3618181657
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.4232301869
Short name T2388
Test name
Test status
Simulation time 4648233152 ps
CPU time 30.18 seconds
Started Jul 03 04:55:15 PM PDT 24
Finished Jul 03 04:55:45 PM PDT 24
Peak memory 206340 kb
Host smart-aa2c2210-1ae1-445a-8eeb-26b37aab86a8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4232301869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.4232301869
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3343125550
Short name T1922
Test name
Test status
Simulation time 157907377 ps
CPU time 0.77 seconds
Started Jul 03 04:54:52 PM PDT 24
Finished Jul 03 04:54:53 PM PDT 24
Peak memory 206112 kb
Host smart-eb83499f-a119-4a9c-86e2-dd3ab91841d4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3343125550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3343125550
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2725645455
Short name T95
Test name
Test status
Simulation time 193426261 ps
CPU time 0.8 seconds
Started Jul 03 04:54:53 PM PDT 24
Finished Jul 03 04:54:55 PM PDT 24
Peak memory 206076 kb
Host smart-7bbffaeb-d247-47bd-b773-3e60e4775bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27256
45455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2725645455
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2743766999
Short name T153
Test name
Test status
Simulation time 193840853 ps
CPU time 0.89 seconds
Started Jul 03 04:54:58 PM PDT 24
Finished Jul 03 04:54:59 PM PDT 24
Peak memory 206128 kb
Host smart-c288930c-21b1-456c-9d28-fd76a86980df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27437
66999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2743766999
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.245876127
Short name T858
Test name
Test status
Simulation time 160150791 ps
CPU time 0.81 seconds
Started Jul 03 04:55:02 PM PDT 24
Finished Jul 03 04:55:04 PM PDT 24
Peak memory 206072 kb
Host smart-0f0547a5-143b-4f28-bbdb-7bee2caacaf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24587
6127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.245876127
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2089698977
Short name T48
Test name
Test status
Simulation time 152300310 ps
CPU time 0.75 seconds
Started Jul 03 04:55:12 PM PDT 24
Finished Jul 03 04:55:13 PM PDT 24
Peak memory 206088 kb
Host smart-8f930275-78a8-4500-b9f7-9c47d2dc47a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20896
98977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2089698977
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3094266343
Short name T2400
Test name
Test status
Simulation time 186328454 ps
CPU time 0.76 seconds
Started Jul 03 04:55:10 PM PDT 24
Finished Jul 03 04:55:10 PM PDT 24
Peak memory 206388 kb
Host smart-d5d30f7c-1d26-46f9-a3a1-6daa9583a68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30942
66343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3094266343
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2338815388
Short name T2030
Test name
Test status
Simulation time 146500821 ps
CPU time 0.77 seconds
Started Jul 03 04:55:14 PM PDT 24
Finished Jul 03 04:55:15 PM PDT 24
Peak memory 206068 kb
Host smart-5f3c5a32-40f3-4262-9a2d-7ccc62cf2ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23388
15388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2338815388
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3735603319
Short name T601
Test name
Test status
Simulation time 272462150 ps
CPU time 1.13 seconds
Started Jul 03 04:55:01 PM PDT 24
Finished Jul 03 04:55:03 PM PDT 24
Peak memory 206088 kb
Host smart-88d210d3-1253-4a6f-afa0-84d6ce879a17
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3735603319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3735603319
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1300083057
Short name T2435
Test name
Test status
Simulation time 141779961 ps
CPU time 0.74 seconds
Started Jul 03 04:55:14 PM PDT 24
Finished Jul 03 04:55:16 PM PDT 24
Peak memory 205984 kb
Host smart-f450af4d-f97e-4d01-aea1-b5516f607a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13000
83057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1300083057
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3863999464
Short name T1741
Test name
Test status
Simulation time 43303558 ps
CPU time 0.65 seconds
Started Jul 03 04:54:58 PM PDT 24
Finished Jul 03 04:54:59 PM PDT 24
Peak memory 206076 kb
Host smart-bd582066-ce21-4fb6-b719-a95ff0e09271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38639
99464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3863999464
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3347192731
Short name T1666
Test name
Test status
Simulation time 21264336992 ps
CPU time 48.42 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:56:05 PM PDT 24
Peak memory 206456 kb
Host smart-f7f69fbd-6361-4ffa-829b-9db287bcae5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33471
92731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3347192731
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3283046784
Short name T1217
Test name
Test status
Simulation time 166825223 ps
CPU time 0.84 seconds
Started Jul 03 04:54:59 PM PDT 24
Finished Jul 03 04:55:00 PM PDT 24
Peak memory 206144 kb
Host smart-0cdfa485-34fd-4d12-93ae-4e94eb76d0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32830
46784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3283046784
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2055148739
Short name T1933
Test name
Test status
Simulation time 239938259 ps
CPU time 0.92 seconds
Started Jul 03 04:54:56 PM PDT 24
Finished Jul 03 04:54:57 PM PDT 24
Peak memory 206112 kb
Host smart-8a4ade6d-e7d2-4249-acdf-1cfe43ed2c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20551
48739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2055148739
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2332599337
Short name T608
Test name
Test status
Simulation time 186611448 ps
CPU time 0.8 seconds
Started Jul 03 04:55:08 PM PDT 24
Finished Jul 03 04:55:10 PM PDT 24
Peak memory 206076 kb
Host smart-0cb3866e-4e4a-4b5c-83f4-2acb391641ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23325
99337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2332599337
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.172455697
Short name T1834
Test name
Test status
Simulation time 157547537 ps
CPU time 0.84 seconds
Started Jul 03 04:55:20 PM PDT 24
Finished Jul 03 04:55:21 PM PDT 24
Peak memory 206112 kb
Host smart-eddfdbd5-606b-45a1-8f2b-a7ddb5b1c942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
5697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.172455697
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1264083385
Short name T2620
Test name
Test status
Simulation time 148731957 ps
CPU time 0.8 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:18 PM PDT 24
Peak memory 206132 kb
Host smart-d33cd123-275a-4cc7-9124-914d0715fce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12640
83385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1264083385
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.604102645
Short name T1020
Test name
Test status
Simulation time 145457311 ps
CPU time 0.77 seconds
Started Jul 03 04:55:00 PM PDT 24
Finished Jul 03 04:55:01 PM PDT 24
Peak memory 206128 kb
Host smart-3d7e0af5-7c58-4d22-85ca-74059015fc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60410
2645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.604102645
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.318838578
Short name T776
Test name
Test status
Simulation time 146753306 ps
CPU time 0.76 seconds
Started Jul 03 04:55:01 PM PDT 24
Finished Jul 03 04:55:02 PM PDT 24
Peak memory 206128 kb
Host smart-b741715c-c137-4624-8138-1a95ba565c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31883
8578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.318838578
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3225276429
Short name T2270
Test name
Test status
Simulation time 206137097 ps
CPU time 0.91 seconds
Started Jul 03 04:55:08 PM PDT 24
Finished Jul 03 04:55:09 PM PDT 24
Peak memory 206128 kb
Host smart-479fbf81-7c81-4ee9-8eba-88e382f38ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32252
76429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3225276429
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2193384903
Short name T857
Test name
Test status
Simulation time 4676375172 ps
CPU time 42.17 seconds
Started Jul 03 04:54:59 PM PDT 24
Finished Jul 03 04:55:42 PM PDT 24
Peak memory 206424 kb
Host smart-5361494a-0439-4665-97f9-cb82b5250479
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2193384903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2193384903
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3601072915
Short name T372
Test name
Test status
Simulation time 188737538 ps
CPU time 0.87 seconds
Started Jul 03 04:55:14 PM PDT 24
Finished Jul 03 04:55:15 PM PDT 24
Peak memory 206108 kb
Host smart-2822eec4-56d4-43ad-ac57-835dac92d2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36010
72915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3601072915
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.4081364078
Short name T974
Test name
Test status
Simulation time 197639797 ps
CPU time 0.85 seconds
Started Jul 03 04:54:58 PM PDT 24
Finished Jul 03 04:55:00 PM PDT 24
Peak memory 206136 kb
Host smart-b9960056-5a2b-4a58-bf77-3272ac77720e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40813
64078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.4081364078
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.2379405620
Short name T1084
Test name
Test status
Simulation time 376161393 ps
CPU time 1.12 seconds
Started Jul 03 04:55:13 PM PDT 24
Finished Jul 03 04:55:14 PM PDT 24
Peak memory 206132 kb
Host smart-c0340090-202f-4808-b458-bfd5e9c5d417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23794
05620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.2379405620
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.2917048022
Short name T351
Test name
Test status
Simulation time 4596130774 ps
CPU time 121.09 seconds
Started Jul 03 04:55:02 PM PDT 24
Finished Jul 03 04:57:04 PM PDT 24
Peak memory 206404 kb
Host smart-6d3b8bc7-225f-4667-a834-17d9144febb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29170
48022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.2917048022
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.4074862398
Short name T836
Test name
Test status
Simulation time 43015327 ps
CPU time 0.68 seconds
Started Jul 03 04:55:04 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206188 kb
Host smart-09b917f2-950e-4736-9980-23c9410410b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4074862398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.4074862398
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.288322288
Short name T906
Test name
Test status
Simulation time 4131974859 ps
CPU time 4.85 seconds
Started Jul 03 04:55:12 PM PDT 24
Finished Jul 03 04:55:18 PM PDT 24
Peak memory 206172 kb
Host smart-c0f647d7-f2ff-4e17-a843-a6a301cb18b3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=288322288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.288322288
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.208466683
Short name T2253
Test name
Test status
Simulation time 13368112539 ps
CPU time 11.83 seconds
Started Jul 03 04:55:07 PM PDT 24
Finished Jul 03 04:55:19 PM PDT 24
Peak memory 206352 kb
Host smart-ec2bb3f1-e0be-446e-ac6f-7f6f45054311
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=208466683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.208466683
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3410476490
Short name T1293
Test name
Test status
Simulation time 23473721353 ps
CPU time 24.51 seconds
Started Jul 03 04:55:17 PM PDT 24
Finished Jul 03 04:55:43 PM PDT 24
Peak memory 206196 kb
Host smart-349e7b3a-4d9a-41f0-a5f6-7675cd28a506
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3410476490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3410476490
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3182684057
Short name T1081
Test name
Test status
Simulation time 221784379 ps
CPU time 0.97 seconds
Started Jul 03 04:54:58 PM PDT 24
Finished Jul 03 04:54:59 PM PDT 24
Peak memory 206112 kb
Host smart-59325ae9-941b-41f6-9dab-8256232d908f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31826
84057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3182684057
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3653766234
Short name T2497
Test name
Test status
Simulation time 163205489 ps
CPU time 0.79 seconds
Started Jul 03 04:55:18 PM PDT 24
Finished Jul 03 04:55:20 PM PDT 24
Peak memory 206128 kb
Host smart-8f1fdba5-13f7-408c-8389-ac76b42c3869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36537
66234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3653766234
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2259555418
Short name T1318
Test name
Test status
Simulation time 272892841 ps
CPU time 1.1 seconds
Started Jul 03 04:54:59 PM PDT 24
Finished Jul 03 04:55:01 PM PDT 24
Peak memory 206148 kb
Host smart-1c421998-497c-4bac-8e9a-2ff7fa8e027f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22595
55418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2259555418
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3129260361
Short name T1950
Test name
Test status
Simulation time 1065319927 ps
CPU time 2.59 seconds
Started Jul 03 04:54:55 PM PDT 24
Finished Jul 03 04:54:58 PM PDT 24
Peak memory 206328 kb
Host smart-e948d2fb-4589-4f65-8be0-b8e7ca7d9d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31292
60361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3129260361
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3218712167
Short name T1034
Test name
Test status
Simulation time 8536539205 ps
CPU time 15.69 seconds
Started Jul 03 04:55:12 PM PDT 24
Finished Jul 03 04:55:28 PM PDT 24
Peak memory 206448 kb
Host smart-1dc31218-621c-4354-af4c-e23ef014f025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32187
12167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3218712167
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.4218034396
Short name T902
Test name
Test status
Simulation time 422122098 ps
CPU time 1.26 seconds
Started Jul 03 04:55:26 PM PDT 24
Finished Jul 03 04:55:27 PM PDT 24
Peak memory 206116 kb
Host smart-9fed1cf4-0575-43cb-a150-be58a4e8a4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42180
34396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.4218034396
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3091067032
Short name T526
Test name
Test status
Simulation time 194938197 ps
CPU time 0.82 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:31 PM PDT 24
Peak memory 206096 kb
Host smart-2fda322a-bf3e-4fed-864d-f5b13d0b9faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30910
67032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3091067032
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.4082555689
Short name T1444
Test name
Test status
Simulation time 44083501 ps
CPU time 0.65 seconds
Started Jul 03 04:54:58 PM PDT 24
Finished Jul 03 04:54:59 PM PDT 24
Peak memory 206048 kb
Host smart-0252b9f0-27cd-43c0-8b79-4b0aeeac43fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40825
55689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.4082555689
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2927892025
Short name T2100
Test name
Test status
Simulation time 804746574 ps
CPU time 2.03 seconds
Started Jul 03 04:55:08 PM PDT 24
Finished Jul 03 04:55:10 PM PDT 24
Peak memory 206384 kb
Host smart-aec031fd-219a-4f84-91c5-148e6173b145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29278
92025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2927892025
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.613027013
Short name T1299
Test name
Test status
Simulation time 271501610 ps
CPU time 1.86 seconds
Started Jul 03 04:54:58 PM PDT 24
Finished Jul 03 04:55:00 PM PDT 24
Peak memory 206376 kb
Host smart-edd819ab-5243-4b83-be62-fe20466f345c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61302
7013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.613027013
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1454747644
Short name T2136
Test name
Test status
Simulation time 190321059 ps
CPU time 0.85 seconds
Started Jul 03 04:55:20 PM PDT 24
Finished Jul 03 04:55:21 PM PDT 24
Peak memory 206076 kb
Host smart-48a3d640-c37e-48b2-acc0-27c7c4d7781c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14547
47644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1454747644
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3704019770
Short name T2130
Test name
Test status
Simulation time 152558360 ps
CPU time 0.76 seconds
Started Jul 03 04:55:04 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206128 kb
Host smart-a61eddf3-09eb-4ac5-974b-b58c887240c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37040
19770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3704019770
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3006620362
Short name T1902
Test name
Test status
Simulation time 232367405 ps
CPU time 0.92 seconds
Started Jul 03 04:55:02 PM PDT 24
Finished Jul 03 04:55:03 PM PDT 24
Peak memory 206128 kb
Host smart-3ba92475-2b2c-4774-91d5-ae281775d696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30066
20362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3006620362
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3621152450
Short name T1835
Test name
Test status
Simulation time 6239242774 ps
CPU time 57.92 seconds
Started Jul 03 04:55:24 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206428 kb
Host smart-ca27c6db-bb76-46ae-8c85-b4fbba30a9e1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3621152450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3621152450
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.4257135827
Short name T1611
Test name
Test status
Simulation time 237109024 ps
CPU time 0.88 seconds
Started Jul 03 04:55:23 PM PDT 24
Finished Jul 03 04:55:24 PM PDT 24
Peak memory 206136 kb
Host smart-bb2d5019-4b0c-4c38-9973-e16703a1f880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42571
35827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.4257135827
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.31298038
Short name T533
Test name
Test status
Simulation time 23277665214 ps
CPU time 27.71 seconds
Started Jul 03 04:55:21 PM PDT 24
Finished Jul 03 04:55:50 PM PDT 24
Peak memory 206124 kb
Host smart-cf6dcd0c-0d4b-4498-af7b-3e1016a1a0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31298
038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.31298038
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3300981415
Short name T2652
Test name
Test status
Simulation time 3330072974 ps
CPU time 4.32 seconds
Started Jul 03 04:55:05 PM PDT 24
Finished Jul 03 04:55:09 PM PDT 24
Peak memory 206044 kb
Host smart-4aa4759e-efaa-4318-9172-d11e2080814e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33009
81415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3300981415
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.4135854582
Short name T2626
Test name
Test status
Simulation time 6932098502 ps
CPU time 195.05 seconds
Started Jul 03 04:55:06 PM PDT 24
Finished Jul 03 04:58:21 PM PDT 24
Peak memory 206396 kb
Host smart-732482df-92aa-4c5b-ae8a-d283f1db3d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41358
54582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.4135854582
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.4005876595
Short name T1243
Test name
Test status
Simulation time 4982428866 ps
CPU time 126.74 seconds
Started Jul 03 04:55:18 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206376 kb
Host smart-11abbc78-2c10-4665-aa89-17a8bf1db104
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4005876595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.4005876595
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.341713264
Short name T1689
Test name
Test status
Simulation time 250082981 ps
CPU time 1.02 seconds
Started Jul 03 04:55:11 PM PDT 24
Finished Jul 03 04:55:12 PM PDT 24
Peak memory 206132 kb
Host smart-7a140e40-a091-45db-a8b7-28b8bd3a8d52
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=341713264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.341713264
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.562306060
Short name T1485
Test name
Test status
Simulation time 195865619 ps
CPU time 0.94 seconds
Started Jul 03 04:55:05 PM PDT 24
Finished Jul 03 04:55:06 PM PDT 24
Peak memory 206072 kb
Host smart-615c9add-934d-4f81-a77c-db9738210769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56230
6060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.562306060
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.1736393410
Short name T796
Test name
Test status
Simulation time 4398064054 ps
CPU time 29.26 seconds
Started Jul 03 04:55:20 PM PDT 24
Finished Jul 03 04:55:50 PM PDT 24
Peak memory 206392 kb
Host smart-19804492-afae-4b77-8e95-483a544ed6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17363
93410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.1736393410
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.2823831948
Short name T2150
Test name
Test status
Simulation time 4214964934 ps
CPU time 107.84 seconds
Started Jul 03 04:55:17 PM PDT 24
Finished Jul 03 04:57:06 PM PDT 24
Peak memory 206384 kb
Host smart-0656fcb3-a8ae-4563-a68e-0aca13c7a01a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2823831948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.2823831948
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2300318856
Short name T2521
Test name
Test status
Simulation time 164671866 ps
CPU time 0.76 seconds
Started Jul 03 04:55:13 PM PDT 24
Finished Jul 03 04:55:14 PM PDT 24
Peak memory 206144 kb
Host smart-8f61c4fe-5b40-453a-820f-d2b3ec8a0926
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2300318856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2300318856
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.909281955
Short name T1348
Test name
Test status
Simulation time 157771370 ps
CPU time 0.74 seconds
Started Jul 03 04:55:24 PM PDT 24
Finished Jul 03 04:55:25 PM PDT 24
Peak memory 206136 kb
Host smart-d37be9bc-3c15-4949-9167-c33b380706e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90928
1955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.909281955
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2718833031
Short name T1525
Test name
Test status
Simulation time 223222522 ps
CPU time 0.89 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:31 PM PDT 24
Peak memory 206084 kb
Host smart-ae3f04c4-be3b-4cfa-9301-d5c466c31af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27188
33031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2718833031
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1443969419
Short name T568
Test name
Test status
Simulation time 184728816 ps
CPU time 0.85 seconds
Started Jul 03 04:55:04 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206140 kb
Host smart-6bb99731-5067-4beb-8057-ee9a06c0c4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14439
69419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1443969419
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3281626866
Short name T948
Test name
Test status
Simulation time 200568221 ps
CPU time 0.78 seconds
Started Jul 03 04:55:25 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206144 kb
Host smart-03e09115-5a27-4f47-8380-0a33cf289ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32816
26866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3281626866
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2945817963
Short name T1622
Test name
Test status
Simulation time 171412133 ps
CPU time 0.85 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:31 PM PDT 24
Peak memory 206004 kb
Host smart-2439b51d-c3ec-4cb0-be3f-4f289ed8c6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29458
17963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2945817963
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2888357826
Short name T1832
Test name
Test status
Simulation time 154059626 ps
CPU time 0.76 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:30 PM PDT 24
Peak memory 206112 kb
Host smart-014ea597-1f24-435d-9908-1c5a56f20cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28883
57826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2888357826
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.2378034342
Short name T954
Test name
Test status
Simulation time 270899896 ps
CPU time 0.99 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:30 PM PDT 24
Peak memory 206088 kb
Host smart-af88e209-9fa7-44c5-9802-b694f89dbc6f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2378034342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.2378034342
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1709506667
Short name T2398
Test name
Test status
Simulation time 145418649 ps
CPU time 0.8 seconds
Started Jul 03 04:55:06 PM PDT 24
Finished Jul 03 04:55:07 PM PDT 24
Peak memory 206072 kb
Host smart-6e6a1ae7-7686-41d7-9f32-a236d67e3d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17095
06667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1709506667
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.710486862
Short name T596
Test name
Test status
Simulation time 45957483 ps
CPU time 0.64 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:55:34 PM PDT 24
Peak memory 206120 kb
Host smart-62b4c5d3-048f-409a-9bdf-733a1b0e42b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71048
6862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.710486862
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2399876165
Short name T2018
Test name
Test status
Simulation time 15504001598 ps
CPU time 35.64 seconds
Started Jul 03 04:55:03 PM PDT 24
Finished Jul 03 04:55:39 PM PDT 24
Peak memory 206480 kb
Host smart-04fa7a17-a9a6-449e-af28-eb62a0290bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23998
76165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2399876165
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3273982221
Short name T1717
Test name
Test status
Simulation time 159878553 ps
CPU time 0.85 seconds
Started Jul 03 04:55:06 PM PDT 24
Finished Jul 03 04:55:07 PM PDT 24
Peak memory 206088 kb
Host smart-044c71a7-c27d-4d6b-be3d-75be14709842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32739
82221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3273982221
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.348974931
Short name T703
Test name
Test status
Simulation time 281278615 ps
CPU time 0.96 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206132 kb
Host smart-0d385144-9e08-431f-adb8-769cd58c7959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34897
4931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.348974931
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.732394633
Short name T779
Test name
Test status
Simulation time 189726397 ps
CPU time 0.87 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206128 kb
Host smart-a62a70b1-6874-4c57-b20e-7cc5d19c16b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73239
4633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.732394633
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3175833030
Short name T1605
Test name
Test status
Simulation time 167076085 ps
CPU time 0.85 seconds
Started Jul 03 04:55:05 PM PDT 24
Finished Jul 03 04:55:06 PM PDT 24
Peak memory 205984 kb
Host smart-7f580714-75fe-4d3c-9919-16fce5973787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31758
33030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3175833030
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2124702401
Short name T2516
Test name
Test status
Simulation time 130930231 ps
CPU time 0.82 seconds
Started Jul 03 04:55:25 PM PDT 24
Finished Jul 03 04:55:27 PM PDT 24
Peak memory 206072 kb
Host smart-768c7066-34b5-4608-95e9-fb97b2d174ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21247
02401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2124702401
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1059536417
Short name T2551
Test name
Test status
Simulation time 238810925 ps
CPU time 0.89 seconds
Started Jul 03 04:55:03 PM PDT 24
Finished Jul 03 04:55:05 PM PDT 24
Peak memory 206120 kb
Host smart-aaf7adbf-751e-4c29-80db-3c2370b72e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10595
36417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1059536417
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3227484573
Short name T2289
Test name
Test status
Simulation time 151847768 ps
CPU time 0.83 seconds
Started Jul 03 04:55:17 PM PDT 24
Finished Jul 03 04:55:19 PM PDT 24
Peak memory 206128 kb
Host smart-25d7dafc-d8f1-44b8-bc12-3094f277f1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32274
84573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3227484573
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3781695244
Short name T2229
Test name
Test status
Simulation time 211346823 ps
CPU time 0.9 seconds
Started Jul 03 04:55:27 PM PDT 24
Finished Jul 03 04:55:28 PM PDT 24
Peak memory 206104 kb
Host smart-8fcf186d-ab24-4548-93b0-352329920513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37816
95244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3781695244
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.108844489
Short name T2460
Test name
Test status
Simulation time 6572247994 ps
CPU time 64.53 seconds
Started Jul 03 04:55:03 PM PDT 24
Finished Jul 03 04:56:08 PM PDT 24
Peak memory 206312 kb
Host smart-1baeda42-c90b-4df8-867e-ccbc7aa3c8c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=108844489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.108844489
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3976155733
Short name T1894
Test name
Test status
Simulation time 172368116 ps
CPU time 0.81 seconds
Started Jul 03 04:55:06 PM PDT 24
Finished Jul 03 04:55:07 PM PDT 24
Peak memory 206132 kb
Host smart-e8889700-f8f0-4ca0-86ad-5c8b82c7fc9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39761
55733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3976155733
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1776779496
Short name T2362
Test name
Test status
Simulation time 156130670 ps
CPU time 0.82 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:29 PM PDT 24
Peak memory 206088 kb
Host smart-cfac66ef-6eff-4f39-9943-252e6b15bc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17767
79496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1776779496
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.1139735501
Short name T2535
Test name
Test status
Simulation time 456889153 ps
CPU time 1.43 seconds
Started Jul 03 04:55:25 PM PDT 24
Finished Jul 03 04:55:27 PM PDT 24
Peak memory 206128 kb
Host smart-0f6ae9ec-2e9e-4778-9e51-03213ed4ed30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11397
35501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.1139735501
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2112242231
Short name T679
Test name
Test status
Simulation time 4194805859 ps
CPU time 28.23 seconds
Started Jul 03 04:55:14 PM PDT 24
Finished Jul 03 04:55:43 PM PDT 24
Peak memory 206408 kb
Host smart-5ab0ac1d-e746-4103-9fce-3fe126fc8386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21122
42231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2112242231
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.223272528
Short name T47
Test name
Test status
Simulation time 70215573 ps
CPU time 0.68 seconds
Started Jul 03 04:55:15 PM PDT 24
Finished Jul 03 04:55:16 PM PDT 24
Peak memory 206060 kb
Host smart-ae579e31-b21e-479e-8745-c751c34bde8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=223272528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.223272528
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.4111616856
Short name T738
Test name
Test status
Simulation time 3870421380 ps
CPU time 4.36 seconds
Started Jul 03 04:55:18 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206364 kb
Host smart-0fcf2ec1-1668-4fb5-854d-857a2a3df938
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4111616856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.4111616856
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3368700778
Short name T484
Test name
Test status
Simulation time 13503499289 ps
CPU time 17.2 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:47 PM PDT 24
Peak memory 206368 kb
Host smart-38f27d55-a462-4e67-8981-57cab304e761
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3368700778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3368700778
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.375217935
Short name T991
Test name
Test status
Simulation time 23384705581 ps
CPU time 22.78 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:52 PM PDT 24
Peak memory 206156 kb
Host smart-effc2679-72e9-4bf1-8862-f334006032e1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=375217935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.375217935
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.591832992
Short name T1986
Test name
Test status
Simulation time 156942580 ps
CPU time 0.76 seconds
Started Jul 03 04:55:07 PM PDT 24
Finished Jul 03 04:55:08 PM PDT 24
Peak memory 206080 kb
Host smart-a017cb29-88b9-47f0-a85f-bc423b43f1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59183
2992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.591832992
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1874226722
Short name T2315
Test name
Test status
Simulation time 142217151 ps
CPU time 0.77 seconds
Started Jul 03 04:55:07 PM PDT 24
Finished Jul 03 04:55:08 PM PDT 24
Peak memory 206128 kb
Host smart-6e5efef5-0b88-4602-b614-1cc0a5d8908f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18742
26722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1874226722
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3118768489
Short name T1278
Test name
Test status
Simulation time 191033026 ps
CPU time 0.84 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:30 PM PDT 24
Peak memory 206124 kb
Host smart-7b18ffa2-547b-4cfe-a9f9-2fa4bd29ed7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31187
68489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3118768489
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.68707938
Short name T2126
Test name
Test status
Simulation time 746113973 ps
CPU time 1.79 seconds
Started Jul 03 04:55:07 PM PDT 24
Finished Jul 03 04:55:09 PM PDT 24
Peak memory 206328 kb
Host smart-00f8362c-d48c-4d9c-a520-bf4efbc170cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68707
938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.68707938
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.146470622
Short name T174
Test name
Test status
Simulation time 19233442493 ps
CPU time 39.9 seconds
Started Jul 03 04:55:19 PM PDT 24
Finished Jul 03 04:55:59 PM PDT 24
Peak memory 206364 kb
Host smart-cde665be-9d81-4a62-845d-f282e42fdae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14647
0622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.146470622
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1486712928
Short name T1912
Test name
Test status
Simulation time 412790399 ps
CPU time 1.22 seconds
Started Jul 03 04:55:08 PM PDT 24
Finished Jul 03 04:55:10 PM PDT 24
Peak memory 206052 kb
Host smart-7b7c57dd-fc1a-4a6b-b2b6-8ddd1e084e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14867
12928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1486712928
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1877332742
Short name T739
Test name
Test status
Simulation time 159655317 ps
CPU time 0.82 seconds
Started Jul 03 04:55:24 PM PDT 24
Finished Jul 03 04:55:25 PM PDT 24
Peak memory 206092 kb
Host smart-6fbf1b0c-f164-443a-9df6-08e60871b40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18773
32742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1877332742
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.366557919
Short name T588
Test name
Test status
Simulation time 60393345 ps
CPU time 0.66 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:29 PM PDT 24
Peak memory 206124 kb
Host smart-7c8424d4-5bed-4569-bf1d-7c18dc1451e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36655
7919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.366557919
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1529561608
Short name T2054
Test name
Test status
Simulation time 845124395 ps
CPU time 1.93 seconds
Started Jul 03 04:55:12 PM PDT 24
Finished Jul 03 04:55:14 PM PDT 24
Peak memory 206328 kb
Host smart-bd5a0f90-8dd8-4a67-b633-6059cb156000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15295
61608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1529561608
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1100134325
Short name T1799
Test name
Test status
Simulation time 162944598 ps
CPU time 1.4 seconds
Started Jul 03 04:55:26 PM PDT 24
Finished Jul 03 04:55:28 PM PDT 24
Peak memory 206320 kb
Host smart-319edb47-697a-4c5e-b1cc-8636e351a84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11001
34325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1100134325
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.127357713
Short name T2631
Test name
Test status
Simulation time 268091643 ps
CPU time 0.91 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:17 PM PDT 24
Peak memory 206040 kb
Host smart-3d9d76c0-f816-4e51-8ab6-8981c11cba51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12735
7713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.127357713
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3541023804
Short name T2019
Test name
Test status
Simulation time 148513191 ps
CPU time 0.82 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:18 PM PDT 24
Peak memory 205992 kb
Host smart-17979c10-f8c0-432b-b312-73dc32ad1ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35410
23804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3541023804
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.572237770
Short name T2595
Test name
Test status
Simulation time 278215332 ps
CPU time 1.02 seconds
Started Jul 03 04:55:13 PM PDT 24
Finished Jul 03 04:55:15 PM PDT 24
Peak memory 206144 kb
Host smart-ffca5742-6a5f-4704-a255-2980621d0562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57223
7770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.572237770
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.263762900
Short name T2129
Test name
Test status
Simulation time 214519447 ps
CPU time 0.91 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206092 kb
Host smart-f6709818-599e-41c5-8f2e-e343a5ac257e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26376
2900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.263762900
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3159134377
Short name T619
Test name
Test status
Simulation time 23330656399 ps
CPU time 20.87 seconds
Started Jul 03 04:55:24 PM PDT 24
Finished Jul 03 04:55:45 PM PDT 24
Peak memory 206196 kb
Host smart-970e7b28-65b9-483e-9869-36c68ac2c07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31591
34377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3159134377
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.2490073963
Short name T1153
Test name
Test status
Simulation time 3313440430 ps
CPU time 4.53 seconds
Started Jul 03 04:55:11 PM PDT 24
Finished Jul 03 04:55:16 PM PDT 24
Peak memory 206160 kb
Host smart-fd856f46-3b30-4795-8165-f1ed8af6dde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24900
73963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.2490073963
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2544787145
Short name T478
Test name
Test status
Simulation time 5336041273 ps
CPU time 145.91 seconds
Started Jul 03 04:55:13 PM PDT 24
Finished Jul 03 04:57:40 PM PDT 24
Peak memory 206424 kb
Host smart-ae46ce1d-be03-46c1-be76-89d601397be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25447
87145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2544787145
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.1789596267
Short name T1082
Test name
Test status
Simulation time 4923921339 ps
CPU time 137.36 seconds
Started Jul 03 04:55:12 PM PDT 24
Finished Jul 03 04:57:30 PM PDT 24
Peak memory 206428 kb
Host smart-ed62cfc6-012e-44a4-bcc5-cdf8b198af3d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1789596267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.1789596267
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3705651796
Short name T2546
Test name
Test status
Simulation time 253984287 ps
CPU time 0.94 seconds
Started Jul 03 04:55:12 PM PDT 24
Finished Jul 03 04:55:13 PM PDT 24
Peak memory 206128 kb
Host smart-ebd736c9-9078-49fe-9632-b0f5de09d85c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3705651796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3705651796
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3242002689
Short name T514
Test name
Test status
Simulation time 202545974 ps
CPU time 0.88 seconds
Started Jul 03 04:55:25 PM PDT 24
Finished Jul 03 04:55:26 PM PDT 24
Peak memory 206044 kb
Host smart-b8af6a9d-6b88-429a-8557-626e026e953e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32420
02689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3242002689
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.169845383
Short name T162
Test name
Test status
Simulation time 6974035791 ps
CPU time 193.97 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:58:47 PM PDT 24
Peak memory 206368 kb
Host smart-577dc01e-f994-4511-a567-52611c525c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16984
5383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.169845383
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.343021610
Short name T1023
Test name
Test status
Simulation time 4362669659 ps
CPU time 121.84 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:57:31 PM PDT 24
Peak memory 206464 kb
Host smart-dd38679b-f285-4fdb-a519-52d12a6e40ac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=343021610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.343021610
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1700077700
Short name T1535
Test name
Test status
Simulation time 146296682 ps
CPU time 0.79 seconds
Started Jul 03 04:55:13 PM PDT 24
Finished Jul 03 04:55:14 PM PDT 24
Peak memory 206144 kb
Host smart-3184c7b5-6502-4dce-9fa6-93d360cf6490
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1700077700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1700077700
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1233380571
Short name T1467
Test name
Test status
Simulation time 152505445 ps
CPU time 0.76 seconds
Started Jul 03 04:55:13 PM PDT 24
Finished Jul 03 04:55:14 PM PDT 24
Peak memory 206092 kb
Host smart-b7292728-9812-4dfa-98ed-2281783f9c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12333
80571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1233380571
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1572450154
Short name T143
Test name
Test status
Simulation time 242752765 ps
CPU time 0.91 seconds
Started Jul 03 04:55:10 PM PDT 24
Finished Jul 03 04:55:12 PM PDT 24
Peak memory 206144 kb
Host smart-30064e30-7f59-48aa-8ccd-b669e47ea393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15724
50154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1572450154
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3313098704
Short name T2297
Test name
Test status
Simulation time 166970380 ps
CPU time 0.88 seconds
Started Jul 03 04:55:10 PM PDT 24
Finished Jul 03 04:55:11 PM PDT 24
Peak memory 206132 kb
Host smart-12c012bd-ee50-42a9-ba78-20c74a924258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33130
98704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3313098704
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.822635866
Short name T1728
Test name
Test status
Simulation time 194174020 ps
CPU time 0.89 seconds
Started Jul 03 04:55:17 PM PDT 24
Finished Jul 03 04:55:18 PM PDT 24
Peak memory 206080 kb
Host smart-fc5cd63a-0b0f-4707-b322-7c740687e137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82263
5866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.822635866
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1065528606
Short name T700
Test name
Test status
Simulation time 152767959 ps
CPU time 0.87 seconds
Started Jul 03 04:55:11 PM PDT 24
Finished Jul 03 04:55:13 PM PDT 24
Peak memory 206000 kb
Host smart-d8bf8628-5901-4066-a8b2-395b06271b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10655
28606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1065528606
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1413990850
Short name T194
Test name
Test status
Simulation time 174869093 ps
CPU time 0.83 seconds
Started Jul 03 04:55:25 PM PDT 24
Finished Jul 03 04:55:27 PM PDT 24
Peak memory 206112 kb
Host smart-7d3b0d7b-0bf6-4c06-9174-28298466c78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14139
90850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1413990850
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2585268219
Short name T1435
Test name
Test status
Simulation time 202966368 ps
CPU time 0.92 seconds
Started Jul 03 04:55:10 PM PDT 24
Finished Jul 03 04:55:12 PM PDT 24
Peak memory 206104 kb
Host smart-b8562f71-2e5e-41eb-a1bf-2de5bab7bf22
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2585268219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2585268219
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.762011489
Short name T1693
Test name
Test status
Simulation time 165007024 ps
CPU time 0.86 seconds
Started Jul 03 04:55:12 PM PDT 24
Finished Jul 03 04:55:13 PM PDT 24
Peak memory 206096 kb
Host smart-a2ada46b-d712-49f0-861f-7e8eada41e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76201
1489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.762011489
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1778035024
Short name T41
Test name
Test status
Simulation time 102321299 ps
CPU time 0.72 seconds
Started Jul 03 04:55:21 PM PDT 24
Finished Jul 03 04:55:22 PM PDT 24
Peak memory 206104 kb
Host smart-5e658f31-743a-43a7-90e2-a7e650eb6be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17780
35024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1778035024
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1073753395
Short name T2025
Test name
Test status
Simulation time 23032593462 ps
CPU time 54.49 seconds
Started Jul 03 04:55:13 PM PDT 24
Finished Jul 03 04:56:08 PM PDT 24
Peak memory 214596 kb
Host smart-ee9f4774-fde7-4763-8486-d6162ed07a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10737
53395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1073753395
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.843615488
Short name T1783
Test name
Test status
Simulation time 185186139 ps
CPU time 0.85 seconds
Started Jul 03 04:55:13 PM PDT 24
Finished Jul 03 04:55:15 PM PDT 24
Peak memory 206112 kb
Host smart-9594d143-6eef-4b09-94ca-e49049f30fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84361
5488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.843615488
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1054867219
Short name T2632
Test name
Test status
Simulation time 177024403 ps
CPU time 0.82 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:34 PM PDT 24
Peak memory 206072 kb
Host smart-f1302ed3-c8c6-43dd-8068-44241f021960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10548
67219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1054867219
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.3466891594
Short name T1097
Test name
Test status
Simulation time 213409861 ps
CPU time 0.87 seconds
Started Jul 03 04:55:15 PM PDT 24
Finished Jul 03 04:55:16 PM PDT 24
Peak memory 206096 kb
Host smart-17dd202a-4780-4273-a174-1e1503139a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34668
91594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.3466891594
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.838522891
Short name T417
Test name
Test status
Simulation time 173018849 ps
CPU time 0.9 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:33 PM PDT 24
Peak memory 206044 kb
Host smart-ac8db16a-2063-4ff9-a620-ce7d98eefc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83852
2891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.838522891
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1922397376
Short name T2450
Test name
Test status
Simulation time 144860162 ps
CPU time 0.75 seconds
Started Jul 03 04:55:17 PM PDT 24
Finished Jul 03 04:55:18 PM PDT 24
Peak memory 206108 kb
Host smart-551a5784-c28f-47e9-b572-9a28643aa27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19223
97376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1922397376
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3975974931
Short name T1677
Test name
Test status
Simulation time 217366287 ps
CPU time 0.84 seconds
Started Jul 03 04:55:24 PM PDT 24
Finished Jul 03 04:55:26 PM PDT 24
Peak memory 206108 kb
Host smart-9dd7c412-b590-43f4-9393-a1e41f93bd8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39759
74931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3975974931
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2087860869
Short name T2571
Test name
Test status
Simulation time 226337890 ps
CPU time 0.84 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:33 PM PDT 24
Peak memory 206132 kb
Host smart-886064ae-41df-40e0-9bd9-d55dea876c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20878
60869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2087860869
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.581792455
Short name T481
Test name
Test status
Simulation time 236056996 ps
CPU time 0.95 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:18 PM PDT 24
Peak memory 206104 kb
Host smart-ee559dce-2310-4e59-9cee-b25f58218171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58179
2455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.581792455
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2513310047
Short name T1567
Test name
Test status
Simulation time 4930108914 ps
CPU time 42.63 seconds
Started Jul 03 04:56:46 PM PDT 24
Finished Jul 03 04:57:29 PM PDT 24
Peak memory 206016 kb
Host smart-b2ec97a0-539e-4bd1-af9f-f8e4f3bf13d1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2513310047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2513310047
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.556390847
Short name T905
Test name
Test status
Simulation time 197893248 ps
CPU time 0.83 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:02 PM PDT 24
Peak memory 206144 kb
Host smart-27d9ab94-587a-4f3b-b1e2-cb422349b911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55639
0847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.556390847
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2508792530
Short name T1480
Test name
Test status
Simulation time 193519273 ps
CPU time 0.85 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206096 kb
Host smart-0e1ec274-08ce-4a59-8a9c-b8bcb515997c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25087
92530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2508792530
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.634959472
Short name T369
Test name
Test status
Simulation time 1339664736 ps
CPU time 3.05 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:20 PM PDT 24
Peak memory 206328 kb
Host smart-0dd887e9-99db-460f-83b9-05ef6760f7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63495
9472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.634959472
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1820487466
Short name T2320
Test name
Test status
Simulation time 2893274399 ps
CPU time 77.75 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:56:51 PM PDT 24
Peak memory 206440 kb
Host smart-c6257ec2-d974-49f3-a4e8-fca2b98f1528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18204
87466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1820487466
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.275583953
Short name T1549
Test name
Test status
Simulation time 45502570 ps
CPU time 0.69 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:52:11 PM PDT 24
Peak memory 206120 kb
Host smart-b02df4b1-36cc-49a3-9fde-8ca5e146418e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=275583953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.275583953
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1652897851
Short name T1507
Test name
Test status
Simulation time 3577342980 ps
CPU time 4.48 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206392 kb
Host smart-36eab53c-e94d-4ea3-a9f9-ceb581f76e34
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1652897851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.1652897851
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2499011542
Short name T1851
Test name
Test status
Simulation time 13365639141 ps
CPU time 11.81 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:52:12 PM PDT 24
Peak memory 206420 kb
Host smart-3cda5e71-4d03-4850-812e-a6a36671dab7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2499011542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2499011542
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.2040624002
Short name T2602
Test name
Test status
Simulation time 23440524877 ps
CPU time 23.47 seconds
Started Jul 03 04:51:55 PM PDT 24
Finished Jul 03 04:52:19 PM PDT 24
Peak memory 206440 kb
Host smart-1b2f4081-63eb-4240-a43f-b17b76e5cbfd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2040624002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.2040624002
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1911894430
Short name T483
Test name
Test status
Simulation time 181472034 ps
CPU time 0.86 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:52:00 PM PDT 24
Peak memory 206088 kb
Host smart-5659a0db-3211-4dbc-a856-1db21c7992ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19118
94430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1911894430
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1962756477
Short name T65
Test name
Test status
Simulation time 165714609 ps
CPU time 0.82 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206100 kb
Host smart-aa8eca6c-a479-40ef-9651-82cf04be7816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19627
56477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1962756477
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.1610736810
Short name T100
Test name
Test status
Simulation time 146804533 ps
CPU time 0.78 seconds
Started Jul 03 04:51:58 PM PDT 24
Finished Jul 03 04:51:59 PM PDT 24
Peak memory 206128 kb
Host smart-b93332c3-221f-47ba-82c0-d3723337c7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16107
36810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.1610736810
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3101808125
Short name T2000
Test name
Test status
Simulation time 144748459 ps
CPU time 0.75 seconds
Started Jul 03 04:52:05 PM PDT 24
Finished Jul 03 04:52:06 PM PDT 24
Peak memory 206132 kb
Host smart-be9f8db7-9e02-42f7-8db1-44be4f9540f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31018
08125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3101808125
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.2830435573
Short name T1641
Test name
Test status
Simulation time 325166451 ps
CPU time 1.2 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:06 PM PDT 24
Peak memory 206056 kb
Host smart-973dfc22-fdf2-4091-9055-41502ee7d6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28304
35573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.2830435573
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1483325797
Short name T2020
Test name
Test status
Simulation time 1565126167 ps
CPU time 3.31 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:52:04 PM PDT 24
Peak memory 206352 kb
Host smart-27d6b52f-0105-482a-b2ea-45accce74392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14833
25797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1483325797
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.120117175
Short name T2568
Test name
Test status
Simulation time 20488531306 ps
CPU time 40.74 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:52:43 PM PDT 24
Peak memory 206404 kb
Host smart-1e907814-77bb-40c0-bcf7-b086625523aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12011
7175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.120117175
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3543634891
Short name T923
Test name
Test status
Simulation time 356689841 ps
CPU time 1.17 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206112 kb
Host smart-4060f688-31b6-4353-a723-69e0d835b3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35436
34891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3543634891
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2324626177
Short name T2438
Test name
Test status
Simulation time 136337750 ps
CPU time 0.82 seconds
Started Jul 03 04:51:54 PM PDT 24
Finished Jul 03 04:51:55 PM PDT 24
Peak memory 206132 kb
Host smart-11b7762b-684b-4780-a7c3-96880228a210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23246
26177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2324626177
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.4213280087
Short name T2306
Test name
Test status
Simulation time 35202146 ps
CPU time 0.66 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:52:06 PM PDT 24
Peak memory 206108 kb
Host smart-9d52d0c0-a542-4cef-97c0-be2fbf2d7ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42132
80087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.4213280087
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.1216619317
Short name T472
Test name
Test status
Simulation time 757708003 ps
CPU time 1.85 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:52:02 PM PDT 24
Peak memory 206292 kb
Host smart-a31fd231-b1dc-4d96-857d-a8c2f0910413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12166
19317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1216619317
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.4015673658
Short name T1211
Test name
Test status
Simulation time 215310653 ps
CPU time 1.26 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206272 kb
Host smart-2724c6b5-ebdb-46e5-b7e7-66a1672e9ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40156
73658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.4015673658
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3429453903
Short name T2695
Test name
Test status
Simulation time 90184205497 ps
CPU time 119.96 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:54:04 PM PDT 24
Peak memory 206372 kb
Host smart-1e93ff32-773b-45ec-9218-4a7585a7e6d9
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3429453903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3429453903
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.4169894181
Short name T622
Test name
Test status
Simulation time 104115762896 ps
CPU time 139.72 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:54:24 PM PDT 24
Peak memory 206396 kb
Host smart-f29b1ba8-aa58-426a-9940-d18b243af82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169894181 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.4169894181
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.2613912294
Short name T541
Test name
Test status
Simulation time 103102144228 ps
CPU time 140.28 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:54:25 PM PDT 24
Peak memory 206328 kb
Host smart-84ee1e1d-035f-4655-ac27-5a1a04506cdf
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2613912294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.2613912294
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.2327662341
Short name T1858
Test name
Test status
Simulation time 102928522389 ps
CPU time 142.51 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:54:22 PM PDT 24
Peak memory 206372 kb
Host smart-f5eda2f3-4914-4da6-be5d-3bfa4fa1a91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327662341 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.2327662341
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.1055476151
Short name T1212
Test name
Test status
Simulation time 113136160784 ps
CPU time 161.62 seconds
Started Jul 03 04:51:53 PM PDT 24
Finished Jul 03 04:54:34 PM PDT 24
Peak memory 206392 kb
Host smart-5d4bddf9-6a5c-4c70-bbaa-145e87d85a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10554
76151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.1055476151
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2437326192
Short name T1248
Test name
Test status
Simulation time 168269464 ps
CPU time 0.83 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:52:01 PM PDT 24
Peak memory 206080 kb
Host smart-aa9d9818-8fd7-4b31-8a42-6b7f404827c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24373
26192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2437326192
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2669710382
Short name T2146
Test name
Test status
Simulation time 147397549 ps
CPU time 0.8 seconds
Started Jul 03 04:51:52 PM PDT 24
Finished Jul 03 04:51:53 PM PDT 24
Peak memory 206128 kb
Host smart-2a7fb323-bbfe-4819-8d2e-affad2c0a8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26697
10382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2669710382
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2711574190
Short name T1543
Test name
Test status
Simulation time 198091002 ps
CPU time 0.96 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:52:03 PM PDT 24
Peak memory 206080 kb
Host smart-732a9f26-2f26-4cb7-8ca1-a80711ca2e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27115
74190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2711574190
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.2802925484
Short name T1249
Test name
Test status
Simulation time 7952172755 ps
CPU time 74.04 seconds
Started Jul 03 04:52:00 PM PDT 24
Finished Jul 03 04:53:15 PM PDT 24
Peak memory 206460 kb
Host smart-f59e47c7-a6db-460c-8934-2ec5b6bb029b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2802925484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.2802925484
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3142414861
Short name T365
Test name
Test status
Simulation time 226423851 ps
CPU time 0.94 seconds
Started Jul 03 04:52:00 PM PDT 24
Finished Jul 03 04:52:02 PM PDT 24
Peak memory 206104 kb
Host smart-07f32cde-6a80-49f8-8e2c-b1a89784477e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31424
14861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3142414861
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1592547953
Short name T2046
Test name
Test status
Simulation time 23309600045 ps
CPU time 24.42 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 206040 kb
Host smart-09351598-cb35-4777-af25-4500dd466a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15925
47953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1592547953
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2129843992
Short name T1005
Test name
Test status
Simulation time 3322769355 ps
CPU time 4.26 seconds
Started Jul 03 04:52:00 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206156 kb
Host smart-3e93ca34-76c5-44b2-8529-a5d909eefe8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21298
43992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2129843992
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.3145789879
Short name T707
Test name
Test status
Simulation time 12391900524 ps
CPU time 122.92 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:54:07 PM PDT 24
Peak memory 206444 kb
Host smart-902e79b8-20be-4d09-8437-7f0ac372ba53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31457
89879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.3145789879
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1607958740
Short name T698
Test name
Test status
Simulation time 4676790813 ps
CPU time 125.35 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:54:10 PM PDT 24
Peak memory 206324 kb
Host smart-7b04f01e-9400-400c-9ced-36c8b47eadd3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1607958740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1607958740
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.4096444709
Short name T2346
Test name
Test status
Simulation time 238111696 ps
CPU time 0.96 seconds
Started Jul 03 04:52:00 PM PDT 24
Finished Jul 03 04:52:02 PM PDT 24
Peak memory 206092 kb
Host smart-d5eb4e26-9b66-4b3d-a6e9-d3a9aa989539
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4096444709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.4096444709
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2981931876
Short name T2358
Test name
Test status
Simulation time 192878520 ps
CPU time 0.86 seconds
Started Jul 03 04:52:11 PM PDT 24
Finished Jul 03 04:52:12 PM PDT 24
Peak memory 206032 kb
Host smart-42d21243-8718-498c-a974-0648d0ac78e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29819
31876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2981931876
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.975123023
Short name T437
Test name
Test status
Simulation time 5512666969 ps
CPU time 158.53 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:54:47 PM PDT 24
Peak memory 206260 kb
Host smart-ce7c579e-6941-440f-8c8b-f44d445683d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97512
3023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.975123023
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3263770637
Short name T1646
Test name
Test status
Simulation time 5502591050 ps
CPU time 46.92 seconds
Started Jul 03 04:52:01 PM PDT 24
Finished Jul 03 04:52:49 PM PDT 24
Peak memory 206304 kb
Host smart-7acd5231-3372-4b14-940b-fa8f925b1680
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3263770637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3263770637
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2428941221
Short name T762
Test name
Test status
Simulation time 144844765 ps
CPU time 0.78 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:52:03 PM PDT 24
Peak memory 206120 kb
Host smart-dde0ff7e-bf95-4ef7-8bd2-a0284a2a139d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2428941221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2428941221
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.4281388300
Short name T530
Test name
Test status
Simulation time 188555893 ps
CPU time 0.81 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:52:04 PM PDT 24
Peak memory 206128 kb
Host smart-38280c9c-a4ac-4793-b2bc-9d04c2546b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42813
88300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.4281388300
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.441292974
Short name T127
Test name
Test status
Simulation time 206013109 ps
CPU time 0.81 seconds
Started Jul 03 04:51:56 PM PDT 24
Finished Jul 03 04:51:58 PM PDT 24
Peak memory 206124 kb
Host smart-932d4cac-bd1d-4381-8872-a66d6cd22e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44129
2974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.441292974
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.1085304729
Short name T2074
Test name
Test status
Simulation time 195874959 ps
CPU time 0.9 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206088 kb
Host smart-6e1a4cd3-cfc1-4dfa-abae-0b50c36c07bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10853
04729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.1085304729
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3647660003
Short name T1277
Test name
Test status
Simulation time 190513400 ps
CPU time 0.89 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:52:06 PM PDT 24
Peak memory 206108 kb
Host smart-046e62bc-e727-41a5-8f65-f44df9916889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36476
60003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3647660003
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.540750110
Short name T873
Test name
Test status
Simulation time 180722981 ps
CPU time 0.85 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:52:06 PM PDT 24
Peak memory 206072 kb
Host smart-f4cc5194-2d25-43a6-92e7-1116dc061a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54075
0110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.540750110
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.299324298
Short name T1120
Test name
Test status
Simulation time 200134501 ps
CPU time 0.86 seconds
Started Jul 03 04:51:59 PM PDT 24
Finished Jul 03 04:52:01 PM PDT 24
Peak memory 206092 kb
Host smart-90900853-5910-42f8-8bd4-525aeda13db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29932
4298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.299324298
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3204311530
Short name T2323
Test name
Test status
Simulation time 196536964 ps
CPU time 0.88 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206084 kb
Host smart-d31befc2-b732-4787-bedc-c6e63cc5e78e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3204311530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3204311530
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1437221722
Short name T225
Test name
Test status
Simulation time 271978558 ps
CPU time 0.93 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206132 kb
Host smart-7c1ab5de-b1ee-421d-98f0-87fdd1f274b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14372
21722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1437221722
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.760846068
Short name T44
Test name
Test status
Simulation time 151808185 ps
CPU time 0.8 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206052 kb
Host smart-5395671f-4f10-4393-b3ef-c87ef4ebca25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76084
6068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.760846068
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1802555609
Short name T2540
Test name
Test status
Simulation time 80737064 ps
CPU time 0.76 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206120 kb
Host smart-4f4e5cb5-dac2-4fee-b4ef-55d649d6c7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025
55609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1802555609
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1429416082
Short name T1583
Test name
Test status
Simulation time 13726142162 ps
CPU time 32.5 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:42 PM PDT 24
Peak memory 206476 kb
Host smart-905fe8d5-b6f4-4cf1-8a70-2d5974c8fefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14294
16082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1429416082
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.4204560282
Short name T2569
Test name
Test status
Simulation time 177358480 ps
CPU time 0.83 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206128 kb
Host smart-62323944-75f9-43a1-a8c6-2f4cf48a5481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42045
60282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.4204560282
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.4044651594
Short name T893
Test name
Test status
Simulation time 268251896 ps
CPU time 0.96 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:52:06 PM PDT 24
Peak memory 206072 kb
Host smart-912878e8-0af4-49b4-af3e-59f22e994472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40446
51594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.4044651594
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.2750221113
Short name T2418
Test name
Test status
Simulation time 8840871187 ps
CPU time 58.01 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206480 kb
Host smart-6537fbe0-8907-4d76-b601-ed5683bf8261
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2750221113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2750221113
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.1057377778
Short name T2232
Test name
Test status
Simulation time 22157035663 ps
CPU time 133.27 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206164 kb
Host smart-86ea9359-dde2-4729-8430-9d20a2e7f811
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1057377778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.1057377778
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2753543771
Short name T2588
Test name
Test status
Simulation time 199000174 ps
CPU time 0.86 seconds
Started Jul 03 04:52:00 PM PDT 24
Finished Jul 03 04:52:02 PM PDT 24
Peak memory 206128 kb
Host smart-59005c28-1c47-43f0-bd09-b0725ab2fff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27535
43771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2753543771
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.656136683
Short name T1316
Test name
Test status
Simulation time 187939589 ps
CPU time 0.81 seconds
Started Jul 03 04:52:05 PM PDT 24
Finished Jul 03 04:52:07 PM PDT 24
Peak memory 206092 kb
Host smart-1feb10c5-6e6c-401a-97b6-4f25ed8291e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65613
6683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.656136683
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3806612552
Short name T1099
Test name
Test status
Simulation time 161518599 ps
CPU time 0.84 seconds
Started Jul 03 04:52:00 PM PDT 24
Finished Jul 03 04:52:01 PM PDT 24
Peak memory 206076 kb
Host smart-c7d2ab8a-6e08-44f1-9eea-cb5bbfad00c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38066
12552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3806612552
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.575112209
Short name T86
Test name
Test status
Simulation time 177517287 ps
CPU time 0.81 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:52:03 PM PDT 24
Peak memory 206124 kb
Host smart-3d3c7c76-74d2-45ba-8a06-37a8c48f4a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57511
2209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.575112209
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.9526773
Short name T234
Test name
Test status
Simulation time 438806938 ps
CPU time 1.35 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:52:04 PM PDT 24
Peak memory 225052 kb
Host smart-c933effb-70e8-4843-ad2e-6767d96b4d4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=9526773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.9526773
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1277276909
Short name T66
Test name
Test status
Simulation time 433005355 ps
CPU time 1.29 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206144 kb
Host smart-3485a0aa-250c-477c-a8e9-92509943a787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12772
76909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1277276909
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.1547163587
Short name T2288
Test name
Test status
Simulation time 194960175 ps
CPU time 0.86 seconds
Started Jul 03 04:52:12 PM PDT 24
Finished Jul 03 04:52:13 PM PDT 24
Peak memory 206088 kb
Host smart-edd7f1c3-51a8-4fc3-9fc0-e0c797a562d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471
63587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.1547163587
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3468790967
Short name T1962
Test name
Test status
Simulation time 171277089 ps
CPU time 0.8 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:09 PM PDT 24
Peak memory 206128 kb
Host smart-63348c58-d360-403c-8180-1ad36fca7ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34687
90967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3468790967
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3769094434
Short name T1478
Test name
Test status
Simulation time 143145100 ps
CPU time 0.81 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206140 kb
Host smart-0766e87d-b05e-4ce1-8491-1d46f9466354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37690
94434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3769094434
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1611532249
Short name T1642
Test name
Test status
Simulation time 206228973 ps
CPU time 0.88 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206140 kb
Host smart-28dbc554-0347-4c64-8156-888050c56e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16115
32249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1611532249
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.282392626
Short name T726
Test name
Test status
Simulation time 4850254205 ps
CPU time 46.7 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206372 kb
Host smart-9f7100e3-532a-4e1c-9852-062ee097d420
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=282392626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.282392626
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3916517384
Short name T1849
Test name
Test status
Simulation time 158660362 ps
CPU time 0.85 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:52:04 PM PDT 24
Peak memory 205856 kb
Host smart-cfc1b539-06b1-4cd8-8f70-d8575ceab487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39165
17384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3916517384
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1560545165
Short name T2033
Test name
Test status
Simulation time 163789915 ps
CPU time 0.82 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:52:11 PM PDT 24
Peak memory 206096 kb
Host smart-a828f2d2-4f96-48cc-9feb-8f73cddf2411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15605
45165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1560545165
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.1491626849
Short name T2269
Test name
Test status
Simulation time 406013899 ps
CPU time 1.18 seconds
Started Jul 03 04:52:09 PM PDT 24
Finished Jul 03 04:52:11 PM PDT 24
Peak memory 206024 kb
Host smart-a16a5cf3-b2da-46a7-8f36-5cf9a892329a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14916
26849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1491626849
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.4017959006
Short name T2255
Test name
Test status
Simulation time 4371620261 ps
CPU time 29.84 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:39 PM PDT 24
Peak memory 206312 kb
Host smart-d0b8e473-31b0-4868-ac27-82cafb2b00dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40179
59006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.4017959006
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.66838793
Short name T1040
Test name
Test status
Simulation time 66088228 ps
CPU time 0.71 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:29 PM PDT 24
Peak memory 206160 kb
Host smart-976dda8b-4a0d-4e98-b94e-b30695a21bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=66838793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.66838793
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.79838631
Short name T2542
Test name
Test status
Simulation time 4122884854 ps
CPU time 4.52 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:22 PM PDT 24
Peak memory 206188 kb
Host smart-b017f296-0862-4d2b-bd9a-1b628c08c27e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=79838631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.79838631
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2202328291
Short name T630
Test name
Test status
Simulation time 13456517664 ps
CPU time 16.09 seconds
Started Jul 03 04:55:15 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206340 kb
Host smart-7059ffa9-9203-4c6e-925f-06135644e50e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2202328291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2202328291
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1217911567
Short name T860
Test name
Test status
Simulation time 23302872755 ps
CPU time 23.06 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:40 PM PDT 24
Peak memory 206168 kb
Host smart-d8d2b3f2-7bb8-45fb-b6ab-e171971f37d7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1217911567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1217911567
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1748842130
Short name T717
Test name
Test status
Simulation time 153090053 ps
CPU time 0.79 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206128 kb
Host smart-d7ff0e99-862e-42cd-a62c-ea566f9c4b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17488
42130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1748842130
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.3285010470
Short name T1362
Test name
Test status
Simulation time 164844521 ps
CPU time 0.79 seconds
Started Jul 03 04:55:17 PM PDT 24
Finished Jul 03 04:55:18 PM PDT 24
Peak memory 206120 kb
Host smart-ba36bf71-7308-457b-962c-29fd5cb78952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32850
10470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3285010470
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3856739191
Short name T187
Test name
Test status
Simulation time 478133637 ps
CPU time 1.44 seconds
Started Jul 03 04:55:37 PM PDT 24
Finished Jul 03 04:55:38 PM PDT 24
Peak memory 206184 kb
Host smart-093a811c-8f88-46d9-bcb2-6bfd2faed411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567
39191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3856739191
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3568878173
Short name T1743
Test name
Test status
Simulation time 1270657387 ps
CPU time 2.69 seconds
Started Jul 03 04:55:25 PM PDT 24
Finished Jul 03 04:55:29 PM PDT 24
Peak memory 206248 kb
Host smart-b7529caa-f77c-4cb4-9d74-aaa5026a7613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35688
78173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3568878173
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.17694887
Short name T105
Test name
Test status
Simulation time 12052438626 ps
CPU time 23.36 seconds
Started Jul 03 04:56:52 PM PDT 24
Finished Jul 03 04:57:16 PM PDT 24
Peak memory 206180 kb
Host smart-0322002c-5442-429b-b3e9-7e7390ec413b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17694
887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.17694887
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.2853587174
Short name T2008
Test name
Test status
Simulation time 453047778 ps
CPU time 1.3 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:33 PM PDT 24
Peak memory 206072 kb
Host smart-7057bb01-32ab-48ec-925c-f0a87ad7715e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28535
87174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.2853587174
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1273499165
Short name T2594
Test name
Test status
Simulation time 171572577 ps
CPU time 0.84 seconds
Started Jul 03 04:55:20 PM PDT 24
Finished Jul 03 04:55:21 PM PDT 24
Peak memory 206124 kb
Host smart-2053e11b-b378-4f39-aeda-5434f1d30795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12734
99165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1273499165
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.951843213
Short name T1203
Test name
Test status
Simulation time 49133659 ps
CPU time 0.65 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206084 kb
Host smart-752c8b6a-4f28-423d-899c-97a77ec8b7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95184
3213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.951843213
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3375532987
Short name T2350
Test name
Test status
Simulation time 748615415 ps
CPU time 1.8 seconds
Started Jul 03 04:55:19 PM PDT 24
Finished Jul 03 04:55:22 PM PDT 24
Peak memory 206368 kb
Host smart-0b706b7a-b902-4d94-a367-78474fdf4239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33755
32987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3375532987
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1850728633
Short name T2685
Test name
Test status
Simulation time 278933101 ps
CPU time 1.66 seconds
Started Jul 03 04:55:17 PM PDT 24
Finished Jul 03 04:55:19 PM PDT 24
Peak memory 206352 kb
Host smart-cfe6894e-af00-4508-ab97-cf129c044264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18507
28633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1850728633
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1434717865
Short name T119
Test name
Test status
Simulation time 212003889 ps
CPU time 0.84 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:18 PM PDT 24
Peak memory 206032 kb
Host smart-d410f825-8066-4c90-abc2-44cd33df9c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14347
17865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1434717865
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1328095858
Short name T336
Test name
Test status
Simulation time 154404409 ps
CPU time 0.75 seconds
Started Jul 03 04:55:19 PM PDT 24
Finished Jul 03 04:55:20 PM PDT 24
Peak memory 206112 kb
Host smart-9171b070-fbc8-41c9-bef5-cd897e50f782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13280
95858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1328095858
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.4085822126
Short name T818
Test name
Test status
Simulation time 235255382 ps
CPU time 0.95 seconds
Started Jul 03 04:55:35 PM PDT 24
Finished Jul 03 04:55:37 PM PDT 24
Peak memory 206088 kb
Host smart-1243a4a6-880b-4b62-9e41-ff65d9f2e8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40858
22126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.4085822126
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2244344963
Short name T112
Test name
Test status
Simulation time 6135604558 ps
CPU time 169.57 seconds
Started Jul 03 04:55:17 PM PDT 24
Finished Jul 03 04:58:07 PM PDT 24
Peak memory 206396 kb
Host smart-230e2720-358c-444d-ac60-61d6a0face5b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2244344963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2244344963
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3058753490
Short name T2249
Test name
Test status
Simulation time 254174304 ps
CPU time 0.89 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:31 PM PDT 24
Peak memory 206088 kb
Host smart-ec6dc5bd-670b-4642-9579-457b0d825eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30587
53490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3058753490
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.2958966830
Short name T1536
Test name
Test status
Simulation time 23391193580 ps
CPU time 30.39 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:56:04 PM PDT 24
Peak memory 206156 kb
Host smart-96ed3c05-ffee-44e8-853f-1ac412d3428c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29589
66830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2958966830
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3644520089
Short name T353
Test name
Test status
Simulation time 3298366741 ps
CPU time 3.58 seconds
Started Jul 03 04:55:18 PM PDT 24
Finished Jul 03 04:55:22 PM PDT 24
Peak memory 206184 kb
Host smart-460ec15c-6d12-4c79-8cc8-b4eb6644607b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36445
20089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3644520089
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1031644231
Short name T416
Test name
Test status
Simulation time 13002469768 ps
CPU time 312.67 seconds
Started Jul 03 04:56:51 PM PDT 24
Finished Jul 03 05:02:05 PM PDT 24
Peak memory 206296 kb
Host smart-4bb080fe-717a-4035-ac40-ed03639ae80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10316
44231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1031644231
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.2012443430
Short name T504
Test name
Test status
Simulation time 4239276082 ps
CPU time 110.67 seconds
Started Jul 03 04:56:43 PM PDT 24
Finished Jul 03 04:58:34 PM PDT 24
Peak memory 206136 kb
Host smart-c0106ccc-bbbf-4b13-be3b-b1d09b150064
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2012443430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.2012443430
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.1788967652
Short name T1070
Test name
Test status
Simulation time 240071212 ps
CPU time 0.88 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:29 PM PDT 24
Peak memory 206144 kb
Host smart-7d5d146f-9b8b-4ba4-ac0f-b24697916a4c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1788967652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.1788967652
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3810412489
Short name T1908
Test name
Test status
Simulation time 194186576 ps
CPU time 0.89 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:18 PM PDT 24
Peak memory 205976 kb
Host smart-7f837d2f-d57c-4db4-9b8d-1cffc3829f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38104
12489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3810412489
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.3583236265
Short name T687
Test name
Test status
Simulation time 2801697003 ps
CPU time 19.25 seconds
Started Jul 03 04:55:19 PM PDT 24
Finished Jul 03 04:55:39 PM PDT 24
Peak memory 206372 kb
Host smart-a9e5f2ee-32e8-4f2e-8dcc-ec1673937229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35832
36265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.3583236265
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3105781146
Short name T1678
Test name
Test status
Simulation time 3239304260 ps
CPU time 85.6 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:56:59 PM PDT 24
Peak memory 206336 kb
Host smart-04c7d00b-c4eb-41a7-acc6-8eaca98f7529
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3105781146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3105781146
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.420134268
Short name T567
Test name
Test status
Simulation time 159734377 ps
CPU time 0.82 seconds
Started Jul 03 04:55:17 PM PDT 24
Finished Jul 03 04:55:19 PM PDT 24
Peak memory 206096 kb
Host smart-da199798-e154-45d9-979c-43d0ddb2d60d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=420134268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.420134268
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2727424853
Short name T1768
Test name
Test status
Simulation time 153837601 ps
CPU time 0.82 seconds
Started Jul 03 04:56:24 PM PDT 24
Finished Jul 03 04:56:27 PM PDT 24
Peak memory 204860 kb
Host smart-ce6ee36b-0570-4478-a7b9-2dc55785d424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27274
24853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2727424853
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1228662218
Short name T1651
Test name
Test status
Simulation time 234100760 ps
CPU time 0.81 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:33 PM PDT 24
Peak memory 206088 kb
Host smart-961fa5ac-4eeb-457b-ab9e-8417600819c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12286
62218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1228662218
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3635636404
Short name T1721
Test name
Test status
Simulation time 167721403 ps
CPU time 0.77 seconds
Started Jul 03 04:56:42 PM PDT 24
Finished Jul 03 04:56:43 PM PDT 24
Peak memory 205620 kb
Host smart-c2387015-8c00-4397-b21f-82569287f023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36356
36404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3635636404
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1660079858
Short name T1882
Test name
Test status
Simulation time 153657758 ps
CPU time 0.76 seconds
Started Jul 03 04:56:39 PM PDT 24
Finished Jul 03 04:56:40 PM PDT 24
Peak memory 205872 kb
Host smart-a2bf2282-69af-471a-904d-11522a40de5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16600
79858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1660079858
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3508533766
Short name T27
Test name
Test status
Simulation time 164349388 ps
CPU time 0.77 seconds
Started Jul 03 04:55:16 PM PDT 24
Finished Jul 03 04:55:17 PM PDT 24
Peak memory 206032 kb
Host smart-795542b8-4a0d-428a-9e5d-6ff52cf5e92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35085
33766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3508533766
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1819982450
Short name T827
Test name
Test status
Simulation time 297267277 ps
CPU time 0.94 seconds
Started Jul 03 04:55:36 PM PDT 24
Finished Jul 03 04:55:37 PM PDT 24
Peak memory 206092 kb
Host smart-264fbc98-f86f-485a-9157-828aced08e79
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1819982450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1819982450
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1126249443
Short name T2263
Test name
Test status
Simulation time 150036752 ps
CPU time 0.73 seconds
Started Jul 03 04:56:47 PM PDT 24
Finished Jul 03 04:56:48 PM PDT 24
Peak memory 205692 kb
Host smart-f05f9f29-1e7f-497e-a26c-34d030a944c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11262
49443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1126249443
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1547662641
Short name T540
Test name
Test status
Simulation time 41399005 ps
CPU time 0.71 seconds
Started Jul 03 04:56:24 PM PDT 24
Finished Jul 03 04:56:26 PM PDT 24
Peak memory 204800 kb
Host smart-db1479f8-b1bb-4a28-bae9-1f6238f67cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15476
62641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1547662641
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3188219637
Short name T1206
Test name
Test status
Simulation time 11376105967 ps
CPU time 21.74 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:50 PM PDT 24
Peak memory 205492 kb
Host smart-9298a20e-65b2-41b3-947b-9e42563c8a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31882
19637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3188219637
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3195739811
Short name T1554
Test name
Test status
Simulation time 176977154 ps
CPU time 0.91 seconds
Started Jul 03 04:55:18 PM PDT 24
Finished Jul 03 04:55:19 PM PDT 24
Peak memory 206092 kb
Host smart-10feb20a-1439-4125-a52f-fb6086910313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31957
39811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3195739811
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4221814576
Short name T629
Test name
Test status
Simulation time 233284731 ps
CPU time 0.89 seconds
Started Jul 03 04:55:19 PM PDT 24
Finished Jul 03 04:55:21 PM PDT 24
Peak memory 206128 kb
Host smart-9740e265-1549-4ada-884a-4e6d294357fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42218
14576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4221814576
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.167253516
Short name T1995
Test name
Test status
Simulation time 225186207 ps
CPU time 0.83 seconds
Started Jul 03 04:56:42 PM PDT 24
Finished Jul 03 04:56:43 PM PDT 24
Peak memory 205644 kb
Host smart-eca1f39f-35bf-4149-828e-2c15cf470330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16725
3516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.167253516
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.3199356397
Short name T1956
Test name
Test status
Simulation time 153005910 ps
CPU time 0.75 seconds
Started Jul 03 04:56:48 PM PDT 24
Finished Jul 03 04:56:49 PM PDT 24
Peak memory 205872 kb
Host smart-6c2cd7a5-553f-4f96-aec6-31d1b50b9731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31993
56397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.3199356397
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2544709462
Short name T2706
Test name
Test status
Simulation time 161542463 ps
CPU time 0.76 seconds
Started Jul 03 04:56:43 PM PDT 24
Finished Jul 03 04:56:44 PM PDT 24
Peak memory 205868 kb
Host smart-eebdfa46-1a8c-40eb-80a2-46fa72674641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25447
09462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2544709462
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2855656120
Short name T1988
Test name
Test status
Simulation time 145992366 ps
CPU time 0.75 seconds
Started Jul 03 04:56:48 PM PDT 24
Finished Jul 03 04:56:49 PM PDT 24
Peak memory 205868 kb
Host smart-cd4245de-d605-4d33-b75a-f25a1df49fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28556
56120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2855656120
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2747881548
Short name T1636
Test name
Test status
Simulation time 201469932 ps
CPU time 0.79 seconds
Started Jul 03 04:56:42 PM PDT 24
Finished Jul 03 04:56:43 PM PDT 24
Peak memory 205864 kb
Host smart-0cb35dfa-8f0b-4f52-b50c-5d2240c8bcc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27478
81548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2747881548
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.671790411
Short name T2218
Test name
Test status
Simulation time 195977826 ps
CPU time 0.88 seconds
Started Jul 03 04:55:21 PM PDT 24
Finished Jul 03 04:55:22 PM PDT 24
Peak memory 206128 kb
Host smart-1bcda5d5-911f-4812-ae5d-854487a83525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67179
0411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.671790411
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.1616258713
Short name T2299
Test name
Test status
Simulation time 3995108596 ps
CPU time 35.88 seconds
Started Jul 03 04:55:21 PM PDT 24
Finished Jul 03 04:55:57 PM PDT 24
Peak memory 206428 kb
Host smart-47d2e1f6-ac76-4c3e-858d-cd8989f9b008
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1616258713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.1616258713
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1763173051
Short name T1046
Test name
Test status
Simulation time 177538233 ps
CPU time 0.88 seconds
Started Jul 03 04:55:50 PM PDT 24
Finished Jul 03 04:55:52 PM PDT 24
Peak memory 206092 kb
Host smart-c8901795-c94c-4721-8e4d-3a3db9bccbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17631
73051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1763173051
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.260432915
Short name T2457
Test name
Test status
Simulation time 171937152 ps
CPU time 0.77 seconds
Started Jul 03 04:55:37 PM PDT 24
Finished Jul 03 04:55:38 PM PDT 24
Peak memory 206096 kb
Host smart-d4dea38f-66a2-466a-baba-f47e0086db1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26043
2915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.260432915
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.2295042228
Short name T1503
Test name
Test status
Simulation time 1061620081 ps
CPU time 2.23 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:33 PM PDT 24
Peak memory 206300 kb
Host smart-c6d1a7b8-0621-4c1e-868f-80c8c88ce948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22950
42228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.2295042228
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.4268671689
Short name T2608
Test name
Test status
Simulation time 5837455357 ps
CPU time 54.45 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:56:26 PM PDT 24
Peak memory 206364 kb
Host smart-b11b37fc-3eb7-4f1f-8719-110cfebdc1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42686
71689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.4268671689
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.3761230866
Short name T1534
Test name
Test status
Simulation time 35403419 ps
CPU time 0.63 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:30 PM PDT 24
Peak memory 206108 kb
Host smart-039cb1ce-793a-4ae1-aef9-0f913861031a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3761230866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.3761230866
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1030624164
Short name T2078
Test name
Test status
Simulation time 3620840613 ps
CPU time 5.35 seconds
Started Jul 03 04:55:26 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206436 kb
Host smart-3d795e11-cebf-42b8-b583-816f40078278
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1030624164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.1030624164
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2249985926
Short name T1916
Test name
Test status
Simulation time 13385564009 ps
CPU time 12.14 seconds
Started Jul 03 04:55:27 PM PDT 24
Finished Jul 03 04:55:39 PM PDT 24
Peak memory 206192 kb
Host smart-d4c2d795-4ec5-4aab-b40e-ec28dbdd720b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2249985926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2249985926
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2428730605
Short name T1749
Test name
Test status
Simulation time 23303300810 ps
CPU time 23.25 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:54 PM PDT 24
Peak memory 206192 kb
Host smart-05176bb0-7d50-4745-89e3-030ff8078cb6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2428730605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.2428730605
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2205692987
Short name T465
Test name
Test status
Simulation time 156629069 ps
CPU time 0.81 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:30 PM PDT 24
Peak memory 206088 kb
Host smart-18932e39-3a29-4ca8-b0df-e92e4bcac2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22056
92987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2205692987
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3612242252
Short name T75
Test name
Test status
Simulation time 139750090 ps
CPU time 0.78 seconds
Started Jul 03 04:55:22 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206128 kb
Host smart-b4f3e293-7946-4c8d-baf5-de5c8c52b7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36122
42252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3612242252
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.2733173987
Short name T1194
Test name
Test status
Simulation time 401999015 ps
CPU time 1.41 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206088 kb
Host smart-9c0d2684-1922-4a27-9586-a582eb1caada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27331
73987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2733173987
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.38918605
Short name T2001
Test name
Test status
Simulation time 608929778 ps
CPU time 1.58 seconds
Started Jul 03 04:55:22 PM PDT 24
Finished Jul 03 04:55:24 PM PDT 24
Peak memory 206056 kb
Host smart-fee9365e-4dc9-43f2-842d-f76ea90d2db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38918
605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.38918605
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.1568470101
Short name T1494
Test name
Test status
Simulation time 13978348429 ps
CPU time 25.09 seconds
Started Jul 03 04:55:37 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206404 kb
Host smart-fe8c907b-49a3-42ee-94e0-6e2edf206a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15684
70101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1568470101
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3269275667
Short name T1385
Test name
Test status
Simulation time 479251450 ps
CPU time 1.29 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206112 kb
Host smart-2ccce58d-2bb2-49a7-b11f-8d2c883e4620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32692
75667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3269275667
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1302397703
Short name T1764
Test name
Test status
Simulation time 140578182 ps
CPU time 0.81 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:33 PM PDT 24
Peak memory 206132 kb
Host smart-563e8f2c-fb07-4e57-90b6-d565153a1a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13023
97703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1302397703
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2894456339
Short name T593
Test name
Test status
Simulation time 44755278 ps
CPU time 0.66 seconds
Started Jul 03 04:55:35 PM PDT 24
Finished Jul 03 04:55:36 PM PDT 24
Peak memory 206112 kb
Host smart-98d31c4a-a53d-4c82-aed8-d0b03a530af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28944
56339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2894456339
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3679899664
Short name T959
Test name
Test status
Simulation time 918739496 ps
CPU time 1.99 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:33 PM PDT 24
Peak memory 206360 kb
Host smart-2b08e2ad-4c85-4e88-9cad-d6adc4fc1b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36798
99664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3679899664
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1341668155
Short name T950
Test name
Test status
Simulation time 232866027 ps
CPU time 1.25 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206372 kb
Host smart-204e7d44-36f7-4e7b-b2b2-e36b8c42382b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13416
68155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1341668155
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3796162311
Short name T1899
Test name
Test status
Simulation time 255415865 ps
CPU time 0.95 seconds
Started Jul 03 04:55:22 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206076 kb
Host smart-8a879702-b995-4578-85e7-0e791a9cb519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37961
62311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3796162311
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1922697620
Short name T2104
Test name
Test status
Simulation time 143580163 ps
CPU time 0.76 seconds
Started Jul 03 04:55:21 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206092 kb
Host smart-9eb1b584-3fb2-45a9-bcda-d0a94c425083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19226
97620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1922697620
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3807412246
Short name T2431
Test name
Test status
Simulation time 199036546 ps
CPU time 0.87 seconds
Started Jul 03 04:55:25 PM PDT 24
Finished Jul 03 04:55:27 PM PDT 24
Peak memory 206128 kb
Host smart-fecb5fb2-530c-4db5-971f-724a063a2ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38074
12246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3807412246
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.1359022084
Short name T2157
Test name
Test status
Simulation time 9601999327 ps
CPU time 258.61 seconds
Started Jul 03 04:55:27 PM PDT 24
Finished Jul 03 04:59:46 PM PDT 24
Peak memory 206436 kb
Host smart-023db8ca-0aad-480e-bba6-f280b7ea85d0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1359022084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.1359022084
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3191471652
Short name T734
Test name
Test status
Simulation time 173331302 ps
CPU time 0.86 seconds
Started Jul 03 04:55:23 PM PDT 24
Finished Jul 03 04:55:24 PM PDT 24
Peak memory 206048 kb
Host smart-167bbdec-adda-45e8-ae0a-dd8a8bb13d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31914
71652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3191471652
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3468470967
Short name T1771
Test name
Test status
Simulation time 23283891180 ps
CPU time 23.43 seconds
Started Jul 03 04:55:37 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206196 kb
Host smart-39f3df4e-829c-450f-ab70-ad6ff2a98093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34684
70967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3468470967
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1524235131
Short name T429
Test name
Test status
Simulation time 3294853993 ps
CPU time 3.98 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:37 PM PDT 24
Peak memory 206196 kb
Host smart-1df7e8b9-1ba2-4052-8cd0-52a1a3431c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15242
35131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1524235131
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.4240404613
Short name T1818
Test name
Test status
Simulation time 11025482499 ps
CPU time 75.02 seconds
Started Jul 03 04:55:42 PM PDT 24
Finished Jul 03 04:56:57 PM PDT 24
Peak memory 206448 kb
Host smart-1a0ba020-7548-4fb6-a7c6-d045b7f377f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42404
04613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.4240404613
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.665775954
Short name T1644
Test name
Test status
Simulation time 7715092126 ps
CPU time 53.94 seconds
Started Jul 03 04:55:50 PM PDT 24
Finished Jul 03 04:56:45 PM PDT 24
Peak memory 206376 kb
Host smart-bbce770e-7293-4947-96b8-e8256e644158
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=665775954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.665775954
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2104375654
Short name T1766
Test name
Test status
Simulation time 242133214 ps
CPU time 0.88 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206132 kb
Host smart-4c2f6700-f1b9-456d-94a4-67caa64b8eb3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2104375654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2104375654
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3958969725
Short name T792
Test name
Test status
Simulation time 227957668 ps
CPU time 0.95 seconds
Started Jul 03 04:55:24 PM PDT 24
Finished Jul 03 04:55:25 PM PDT 24
Peak memory 206096 kb
Host smart-3e7d2f1a-ee23-4be1-a61e-2a71f7f509d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39589
69725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3958969725
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.794408802
Short name T364
Test name
Test status
Simulation time 6466621801 ps
CPU time 60.82 seconds
Started Jul 03 04:55:24 PM PDT 24
Finished Jul 03 04:56:25 PM PDT 24
Peak memory 206364 kb
Host smart-ce42587c-6c16-4c24-ac4e-08bac741e9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79440
8802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.794408802
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.1976829279
Short name T1643
Test name
Test status
Simulation time 5365434760 ps
CPU time 46.88 seconds
Started Jul 03 04:55:34 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206428 kb
Host smart-2fef7a37-cc88-4cb7-a68a-b9f7f225104e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1976829279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.1976829279
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.493497899
Short name T1652
Test name
Test status
Simulation time 155953910 ps
CPU time 0.79 seconds
Started Jul 03 04:55:22 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 205964 kb
Host smart-94efb19b-2ec3-4e48-a07c-e16ed34d4a6e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=493497899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.493497899
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2425419058
Short name T915
Test name
Test status
Simulation time 152425765 ps
CPU time 0.79 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:55:34 PM PDT 24
Peak memory 206072 kb
Host smart-8c6eab7e-ac84-455a-8298-acc97992d5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24254
19058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2425419058
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.903460521
Short name T151
Test name
Test status
Simulation time 219383457 ps
CPU time 0.87 seconds
Started Jul 03 04:55:21 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206144 kb
Host smart-88e3bbff-c52c-40ad-a72f-e16cf48288d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90346
0521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.903460521
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2295675165
Short name T987
Test name
Test status
Simulation time 208596992 ps
CPU time 0.86 seconds
Started Jul 03 04:55:34 PM PDT 24
Finished Jul 03 04:55:36 PM PDT 24
Peak memory 206124 kb
Host smart-e7277706-582b-41bd-a726-a49c92fbc16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956
75165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2295675165
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4047182440
Short name T1582
Test name
Test status
Simulation time 158939545 ps
CPU time 0.79 seconds
Started Jul 03 04:55:22 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206128 kb
Host smart-bdacd53e-8989-4b9b-be01-af3112f82864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40471
82440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4047182440
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2813672722
Short name T1324
Test name
Test status
Simulation time 197584861 ps
CPU time 0.81 seconds
Started Jul 03 04:55:25 PM PDT 24
Finished Jul 03 04:55:26 PM PDT 24
Peak memory 206132 kb
Host smart-8f4d1d43-e67e-4015-8c95-bb1da740a558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28136
72722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2813672722
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1514727878
Short name T2294
Test name
Test status
Simulation time 177682565 ps
CPU time 0.79 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:33 PM PDT 24
Peak memory 206072 kb
Host smart-3fbe4537-9959-4683-92de-9e930f2c1b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15147
27878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1514727878
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3536535331
Short name T1204
Test name
Test status
Simulation time 252618102 ps
CPU time 0.96 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:36 PM PDT 24
Peak memory 206088 kb
Host smart-f976a0ce-d6fb-450d-930d-183cf90aad78
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3536535331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3536535331
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2579851865
Short name T1015
Test name
Test status
Simulation time 149148370 ps
CPU time 0.75 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:31 PM PDT 24
Peak memory 206112 kb
Host smart-29d98dd0-4ae6-47c9-a367-349d3f72195e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25798
51865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2579851865
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1303162813
Short name T40
Test name
Test status
Simulation time 85531862 ps
CPU time 0.7 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206032 kb
Host smart-55af3313-57bd-4d1b-a773-97ec3e436829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13031
62813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1303162813
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2492559294
Short name T2265
Test name
Test status
Simulation time 17594742618 ps
CPU time 38.66 seconds
Started Jul 03 04:55:27 PM PDT 24
Finished Jul 03 04:56:07 PM PDT 24
Peak memory 206396 kb
Host smart-78cfbdac-e0a4-4878-b6b7-ecd44f8c3206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24925
59294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2492559294
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3778339740
Short name T2051
Test name
Test status
Simulation time 212760262 ps
CPU time 0.86 seconds
Started Jul 03 04:55:50 PM PDT 24
Finished Jul 03 04:55:51 PM PDT 24
Peak memory 206100 kb
Host smart-8eeb0ebe-103f-4490-9efa-ad5321352ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37783
39740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3778339740
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.4113434630
Short name T2555
Test name
Test status
Simulation time 195122699 ps
CPU time 0.83 seconds
Started Jul 03 04:55:26 PM PDT 24
Finished Jul 03 04:55:28 PM PDT 24
Peak memory 206116 kb
Host smart-1cbba706-1939-4423-9e51-c88509d00f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
34630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.4113434630
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2566360492
Short name T2159
Test name
Test status
Simulation time 229344155 ps
CPU time 0.92 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206092 kb
Host smart-c2f28ba4-72e2-491a-9821-3e538131df3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25663
60492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2566360492
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.1782201342
Short name T1613
Test name
Test status
Simulation time 192877950 ps
CPU time 0.84 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206092 kb
Host smart-663a9297-8883-49b3-8bfc-a8075dff459c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17822
01342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1782201342
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.277856932
Short name T1229
Test name
Test status
Simulation time 182319995 ps
CPU time 0.92 seconds
Started Jul 03 04:55:44 PM PDT 24
Finished Jul 03 04:55:45 PM PDT 24
Peak memory 206132 kb
Host smart-66e10af2-cf69-4509-b787-3d5fad467132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27785
6932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.277856932
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1578789266
Short name T1199
Test name
Test status
Simulation time 192085675 ps
CPU time 0.81 seconds
Started Jul 03 04:55:25 PM PDT 24
Finished Jul 03 04:55:26 PM PDT 24
Peak memory 206104 kb
Host smart-f809ac3c-f73d-4729-82aa-588a656e7d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15787
89266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1578789266
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2791901551
Short name T1241
Test name
Test status
Simulation time 224790194 ps
CPU time 0.92 seconds
Started Jul 03 04:55:26 PM PDT 24
Finished Jul 03 04:55:28 PM PDT 24
Peak memory 206140 kb
Host smart-ae056a09-0930-4031-8255-2bc5804e80ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27919
01551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2791901551
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1984600544
Short name T1915
Test name
Test status
Simulation time 235529863 ps
CPU time 0.94 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:30 PM PDT 24
Peak memory 206112 kb
Host smart-522c36a7-96ba-4703-a6d7-3b56216f4af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19846
00544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1984600544
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1388438101
Short name T1930
Test name
Test status
Simulation time 4709000785 ps
CPU time 133.63 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:57:42 PM PDT 24
Peak memory 206424 kb
Host smart-803a88df-0a10-44ac-a902-aa410105de4d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1388438101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1388438101
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1350986852
Short name T1746
Test name
Test status
Simulation time 196463068 ps
CPU time 0.86 seconds
Started Jul 03 04:55:27 PM PDT 24
Finished Jul 03 04:55:29 PM PDT 24
Peak memory 206120 kb
Host smart-12a8a1a5-033e-4de5-ac2e-ab715d298a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13509
86852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1350986852
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.407639288
Short name T928
Test name
Test status
Simulation time 170443356 ps
CPU time 0.81 seconds
Started Jul 03 04:55:25 PM PDT 24
Finished Jul 03 04:55:26 PM PDT 24
Peak memory 206048 kb
Host smart-1b9a7f22-eec7-4d15-a7b7-fecea7a31fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40763
9288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.407639288
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2147916976
Short name T2500
Test name
Test status
Simulation time 839597620 ps
CPU time 1.9 seconds
Started Jul 03 04:55:21 PM PDT 24
Finished Jul 03 04:55:23 PM PDT 24
Peak memory 206628 kb
Host smart-eb257d0b-a258-4b35-aa18-c1f19df288e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21479
16976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2147916976
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3436408072
Short name T2006
Test name
Test status
Simulation time 6887447480 ps
CPU time 47.19 seconds
Started Jul 03 04:55:22 PM PDT 24
Finished Jul 03 04:56:10 PM PDT 24
Peak memory 206328 kb
Host smart-1944ab36-3d7e-4b79-a014-27d34937b8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34364
08072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3436408072
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.2823359182
Short name T1367
Test name
Test status
Simulation time 64761772 ps
CPU time 0.69 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206152 kb
Host smart-204a22f8-5b0e-4cda-891d-05ae657e0a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2823359182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.2823359182
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.718558673
Short name T1709
Test name
Test status
Simulation time 3969918672 ps
CPU time 4.55 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:34 PM PDT 24
Peak memory 206424 kb
Host smart-9f96f976-9992-40e5-aa47-b6ba17600668
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=718558673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.718558673
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.1561914108
Short name T1972
Test name
Test status
Simulation time 13311501565 ps
CPU time 12.3 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:44 PM PDT 24
Peak memory 206172 kb
Host smart-af16ee89-3c01-458a-9961-51e320378eca
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1561914108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.1561914108
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.323300165
Short name T884
Test name
Test status
Simulation time 23371861371 ps
CPU time 22 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:53 PM PDT 24
Peak memory 206368 kb
Host smart-d068088e-a502-4e4a-b200-a58e17b16e85
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=323300165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.323300165
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.226589956
Short name T1866
Test name
Test status
Simulation time 174533943 ps
CPU time 0.81 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206072 kb
Host smart-cc5ee1e7-0bab-4f7d-959f-6bd0ea51990e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22658
9956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.226589956
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.4191041264
Short name T767
Test name
Test status
Simulation time 161767568 ps
CPU time 0.84 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:55:49 PM PDT 24
Peak memory 206108 kb
Host smart-58395cd3-a954-4dfc-b58e-678d0c57742d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41910
41264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.4191041264
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1332034924
Short name T1745
Test name
Test status
Simulation time 165716917 ps
CPU time 0.76 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:55:49 PM PDT 24
Peak memory 206128 kb
Host smart-d6005d87-da4b-4028-83fd-3d02337157f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13320
34924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1332034924
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1585614400
Short name T197
Test name
Test status
Simulation time 1428788831 ps
CPU time 2.83 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206308 kb
Host smart-1feb4fd5-99a7-4872-89ed-48f8f782d640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15856
14400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1585614400
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.4269540464
Short name T2250
Test name
Test status
Simulation time 8123053259 ps
CPU time 14.93 seconds
Started Jul 03 04:55:38 PM PDT 24
Finished Jul 03 04:55:54 PM PDT 24
Peak memory 206428 kb
Host smart-dae8d94d-6d8d-45cb-af3b-012b5e63390f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42695
40464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.4269540464
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.4150678603
Short name T1812
Test name
Test status
Simulation time 415465327 ps
CPU time 1.19 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:34 PM PDT 24
Peak memory 206128 kb
Host smart-ccf27931-8882-4205-bc55-821271e41aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41506
78603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.4150678603
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.2519413459
Short name T54
Test name
Test status
Simulation time 191938183 ps
CPU time 0.78 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206084 kb
Host smart-e07ea557-ac6b-4302-bc74-dec4c5cfb4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25194
13459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2519413459
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.1564080064
Short name T1830
Test name
Test status
Simulation time 36943856 ps
CPU time 0.67 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206088 kb
Host smart-2bfacc11-4078-4e6d-a092-f83e50507091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640
80064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1564080064
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.17190660
Short name T777
Test name
Test status
Simulation time 774597551 ps
CPU time 1.84 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:33 PM PDT 24
Peak memory 206360 kb
Host smart-03fdd8b1-da81-4c15-8339-a8f4f39dc5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17190
660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.17190660
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2984329734
Short name T2113
Test name
Test status
Simulation time 450048525 ps
CPU time 2.91 seconds
Started Jul 03 04:55:46 PM PDT 24
Finished Jul 03 04:55:49 PM PDT 24
Peak memory 206336 kb
Host smart-805aa3eb-c835-4163-abbd-e6f350d6c047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29843
29734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2984329734
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2376396564
Short name T493
Test name
Test status
Simulation time 170039865 ps
CPU time 0.85 seconds
Started Jul 03 04:55:41 PM PDT 24
Finished Jul 03 04:55:42 PM PDT 24
Peak memory 206096 kb
Host smart-5111af18-85a6-4ee1-b911-5aa2db6eb226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23763
96564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2376396564
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3702064132
Short name T1735
Test name
Test status
Simulation time 218927054 ps
CPU time 0.82 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:55:33 PM PDT 24
Peak memory 206124 kb
Host smart-cc50d6ac-b720-4b34-8a07-f937bcbc02a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37020
64132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3702064132
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2243586872
Short name T1918
Test name
Test status
Simulation time 240041201 ps
CPU time 0.91 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:55:55 PM PDT 24
Peak memory 205576 kb
Host smart-3decad70-0325-4061-a5f3-6e24fbcb1f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22435
86872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2243586872
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2692634478
Short name T1473
Test name
Test status
Simulation time 237730155 ps
CPU time 0.93 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206084 kb
Host smart-6fd37453-c2a1-4672-a5b5-12c41098ca3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26926
34478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2692634478
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.1606237632
Short name T430
Test name
Test status
Simulation time 23338614377 ps
CPU time 23.83 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:53 PM PDT 24
Peak memory 206028 kb
Host smart-cc5e5cba-75f8-4215-b546-659cdde88146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16062
37632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.1606237632
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2424743574
Short name T347
Test name
Test status
Simulation time 3335575453 ps
CPU time 3.57 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:36 PM PDT 24
Peak memory 206152 kb
Host smart-570469c9-1a15-4098-8c5c-1912699bdc7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24247
43574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2424743574
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.323856353
Short name T2661
Test name
Test status
Simulation time 9546358710 ps
CPU time 68.84 seconds
Started Jul 03 04:55:30 PM PDT 24
Finished Jul 03 04:56:41 PM PDT 24
Peak memory 206464 kb
Host smart-71104d83-74ee-4da3-9ccd-26a21be9379b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32385
6353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.323856353
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.1368584369
Short name T650
Test name
Test status
Simulation time 5173579007 ps
CPU time 50.44 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:56:38 PM PDT 24
Peak memory 206432 kb
Host smart-6ba6c02f-1d79-4789-85cf-7ee14eeead81
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1368584369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1368584369
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.4244938906
Short name T402
Test name
Test status
Simulation time 237632292 ps
CPU time 0.95 seconds
Started Jul 03 04:55:45 PM PDT 24
Finished Jul 03 04:55:46 PM PDT 24
Peak memory 206100 kb
Host smart-b31113cc-2ca6-4003-b898-57e93b282b72
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4244938906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.4244938906
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3672876990
Short name T1378
Test name
Test status
Simulation time 194768424 ps
CPU time 0.86 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:55:34 PM PDT 24
Peak memory 206088 kb
Host smart-eee1aea3-64c3-429c-8f98-72ccb5e3bd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36728
76990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3672876990
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1269888626
Short name T2486
Test name
Test status
Simulation time 6112690657 ps
CPU time 58.76 seconds
Started Jul 03 04:55:38 PM PDT 24
Finished Jul 03 04:56:37 PM PDT 24
Peak memory 206436 kb
Host smart-6c538232-638f-4ff0-a0bd-cd8525ac5c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12698
88626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1269888626
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.524942596
Short name T155
Test name
Test status
Simulation time 5826496948 ps
CPU time 162.41 seconds
Started Jul 03 04:55:46 PM PDT 24
Finished Jul 03 04:58:29 PM PDT 24
Peak memory 206380 kb
Host smart-5597b893-66f2-464b-b1eb-b16df11c4e31
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=524942596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.524942596
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.144422916
Short name T1515
Test name
Test status
Simulation time 169560142 ps
CPU time 0.86 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:30 PM PDT 24
Peak memory 206132 kb
Host smart-5e304d7c-9b7f-4330-8688-963cc917abc2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=144422916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.144422916
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3867066586
Short name T1365
Test name
Test status
Simulation time 157824601 ps
CPU time 0.8 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206128 kb
Host smart-953b0df0-d80e-46ac-9c26-ca195120664a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38670
66586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3867066586
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.364404169
Short name T2693
Test name
Test status
Simulation time 204125380 ps
CPU time 0.86 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:31 PM PDT 24
Peak memory 205960 kb
Host smart-529d3152-acb5-41f5-b0c7-faf7c17e2eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
4169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.364404169
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1302261349
Short name T1091
Test name
Test status
Simulation time 187154758 ps
CPU time 0.85 seconds
Started Jul 03 04:55:28 PM PDT 24
Finished Jul 03 04:55:29 PM PDT 24
Peak memory 206132 kb
Host smart-c23b0bd7-a1e9-4465-b88f-ee752a5866cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13022
61349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1302261349
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.135447386
Short name T1914
Test name
Test status
Simulation time 190340165 ps
CPU time 0.82 seconds
Started Jul 03 04:55:40 PM PDT 24
Finished Jul 03 04:55:41 PM PDT 24
Peak memory 206128 kb
Host smart-bbf92315-5fbb-4ac5-ac4a-f89e80931c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13544
7386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.135447386
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2989403896
Short name T1283
Test name
Test status
Simulation time 195554054 ps
CPU time 0.84 seconds
Started Jul 03 04:55:39 PM PDT 24
Finished Jul 03 04:55:40 PM PDT 24
Peak memory 206080 kb
Host smart-8a123fc7-7446-4883-ad2a-9219feef9c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29894
03896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2989403896
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.179402137
Short name T379
Test name
Test status
Simulation time 231761765 ps
CPU time 1.01 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206076 kb
Host smart-738e8894-c6b9-43e6-9694-1850c57232ec
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=179402137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.179402137
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3806317669
Short name T764
Test name
Test status
Simulation time 147100505 ps
CPU time 0.74 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:34 PM PDT 24
Peak memory 206124 kb
Host smart-ab46426a-ec40-4780-8b73-b5d16de4f7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38063
17669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3806317669
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.4167950352
Short name T1470
Test name
Test status
Simulation time 39934776 ps
CPU time 0.67 seconds
Started Jul 03 04:55:46 PM PDT 24
Finished Jul 03 04:55:48 PM PDT 24
Peak memory 206084 kb
Host smart-3858afba-cf36-4c80-a75c-670971a0a028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41679
50352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.4167950352
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1349421366
Short name T297
Test name
Test status
Simulation time 13268355262 ps
CPU time 29.27 seconds
Started Jul 03 04:55:27 PM PDT 24
Finished Jul 03 04:55:57 PM PDT 24
Peak memory 206296 kb
Host smart-2972a547-4009-4cee-8078-8f7b96208d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13494
21366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1349421366
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1907508848
Short name T2713
Test name
Test status
Simulation time 170411525 ps
CPU time 0.78 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:34 PM PDT 24
Peak memory 206136 kb
Host smart-e5e28bec-4b30-4900-a934-a437bc8eb4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19075
08848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1907508848
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3882024271
Short name T985
Test name
Test status
Simulation time 195847793 ps
CPU time 0.9 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:31 PM PDT 24
Peak memory 206108 kb
Host smart-212c415c-ab2e-4485-b9e6-e4e4b4fc0ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38820
24271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3882024271
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2010797300
Short name T1484
Test name
Test status
Simulation time 205745440 ps
CPU time 0.9 seconds
Started Jul 03 04:55:43 PM PDT 24
Finished Jul 03 04:55:44 PM PDT 24
Peak memory 206088 kb
Host smart-ab9b675a-22b1-4ed3-9f07-745eaa9efdb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20107
97300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2010797300
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.445386781
Short name T834
Test name
Test status
Simulation time 184042881 ps
CPU time 0.8 seconds
Started Jul 03 04:55:29 PM PDT 24
Finished Jul 03 04:55:32 PM PDT 24
Peak memory 206072 kb
Host smart-19b48a27-ef40-41ed-8a5c-cd5ac47ffde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44538
6781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.445386781
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2903155913
Short name T1937
Test name
Test status
Simulation time 139382662 ps
CPU time 0.77 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206140 kb
Host smart-570fff13-df25-4600-bdf2-345bd4f072b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29031
55913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2903155913
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1647919253
Short name T972
Test name
Test status
Simulation time 152726712 ps
CPU time 0.78 seconds
Started Jul 03 04:55:32 PM PDT 24
Finished Jul 03 04:55:34 PM PDT 24
Peak memory 206092 kb
Host smart-6cd12735-cd60-423e-8e3e-74e428d63e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16479
19253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1647919253
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3651911306
Short name T680
Test name
Test status
Simulation time 162475722 ps
CPU time 0.8 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206040 kb
Host smart-5ecb155b-36a3-4232-b004-74fe02bfefd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36519
11306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3651911306
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3000575768
Short name T1300
Test name
Test status
Simulation time 240915901 ps
CPU time 0.91 seconds
Started Jul 03 04:55:51 PM PDT 24
Finished Jul 03 04:55:52 PM PDT 24
Peak memory 206128 kb
Host smart-af613daa-a2ab-45d6-85ff-31b285f58cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30005
75768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3000575768
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.1009380900
Short name T1242
Test name
Test status
Simulation time 5473883522 ps
CPU time 38.25 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:56:12 PM PDT 24
Peak memory 206344 kb
Host smart-9d7a7ba6-be34-4cc7-9da7-3fde0021101d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1009380900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1009380900
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3724742102
Short name T2635
Test name
Test status
Simulation time 191537824 ps
CPU time 0.86 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206092 kb
Host smart-a18eabf4-9b2e-4383-8a71-f2a34caa6db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37247
42102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3724742102
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2562772103
Short name T1052
Test name
Test status
Simulation time 198077642 ps
CPU time 0.85 seconds
Started Jul 03 04:55:50 PM PDT 24
Finished Jul 03 04:55:52 PM PDT 24
Peak memory 206132 kb
Host smart-6904013a-4d7b-4b03-a204-f2d49bbd69c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25627
72103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2562772103
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.649812488
Short name T1443
Test name
Test status
Simulation time 1012921198 ps
CPU time 2.07 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:37 PM PDT 24
Peak memory 206280 kb
Host smart-01fd6d5d-edfa-4f25-8d4d-93ff6a29d1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64981
2488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.649812488
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2949987069
Short name T1733
Test name
Test status
Simulation time 6276171733 ps
CPU time 57.46 seconds
Started Jul 03 04:56:05 PM PDT 24
Finished Jul 03 04:57:03 PM PDT 24
Peak memory 206360 kb
Host smart-d6164560-5425-4b5b-b5ad-7ef8bf43d74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29499
87069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2949987069
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.34563332
Short name T845
Test name
Test status
Simulation time 71087379 ps
CPU time 0.72 seconds
Started Jul 03 04:55:48 PM PDT 24
Finished Jul 03 04:55:50 PM PDT 24
Peak memory 205500 kb
Host smart-d927a9a5-03e7-47a7-ad99-82bafd65904b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=34563332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.34563332
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2804670557
Short name T1929
Test name
Test status
Simulation time 3698676223 ps
CPU time 4.48 seconds
Started Jul 03 04:55:52 PM PDT 24
Finished Jul 03 04:55:57 PM PDT 24
Peak memory 206360 kb
Host smart-f2e7bcf4-cdc7-4566-bf6b-f39161c33d05
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2804670557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.2804670557
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3797008262
Short name T995
Test name
Test status
Simulation time 13323938215 ps
CPU time 12.4 seconds
Started Jul 03 04:55:31 PM PDT 24
Finished Jul 03 04:55:46 PM PDT 24
Peak memory 206192 kb
Host smart-fbbb13c7-dca3-414a-a62e-7bdd23014042
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3797008262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3797008262
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.4259048458
Short name T850
Test name
Test status
Simulation time 23390600744 ps
CPU time 21.84 seconds
Started Jul 03 04:55:43 PM PDT 24
Finished Jul 03 04:56:05 PM PDT 24
Peak memory 206240 kb
Host smart-16da98de-cd8d-470b-9454-81c76adeb0f6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4259048458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.4259048458
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2311960631
Short name T2138
Test name
Test status
Simulation time 169606964 ps
CPU time 0.86 seconds
Started Jul 03 04:55:33 PM PDT 24
Finished Jul 03 04:55:35 PM PDT 24
Peak memory 206100 kb
Host smart-4c7ed287-0b02-4ed9-8943-6bfb1b2ccaf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23119
60631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2311960631
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3515174901
Short name T2298
Test name
Test status
Simulation time 172756837 ps
CPU time 0.78 seconds
Started Jul 03 04:55:51 PM PDT 24
Finished Jul 03 04:55:52 PM PDT 24
Peak memory 206132 kb
Host smart-137b2b6d-db30-4f8f-8213-8b9e40a27200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35151
74901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3515174901
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.1816421758
Short name T118
Test name
Test status
Simulation time 216558751 ps
CPU time 0.96 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:55:55 PM PDT 24
Peak memory 205612 kb
Host smart-a054c886-c262-464e-b3ef-3233cbd66b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18164
21758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.1816421758
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1108284816
Short name T1166
Test name
Test status
Simulation time 406252410 ps
CPU time 1.17 seconds
Started Jul 03 04:55:38 PM PDT 24
Finished Jul 03 04:55:40 PM PDT 24
Peak memory 206088 kb
Host smart-5bfdf237-2fc2-41c1-bad4-25db27446a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11082
84816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1108284816
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.505144329
Short name T721
Test name
Test status
Simulation time 23398308934 ps
CPU time 49.31 seconds
Started Jul 03 04:55:36 PM PDT 24
Finished Jul 03 04:56:25 PM PDT 24
Peak memory 206448 kb
Host smart-6b2c7fe8-4f26-411e-9955-5edcf5d7d0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50514
4329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.505144329
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3755707750
Short name T2679
Test name
Test status
Simulation time 406988142 ps
CPU time 1.23 seconds
Started Jul 03 04:55:44 PM PDT 24
Finished Jul 03 04:55:45 PM PDT 24
Peak memory 206116 kb
Host smart-f5878090-fad7-4e8e-8095-e62b9fcc0f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37557
07750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3755707750
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2499563248
Short name T2639
Test name
Test status
Simulation time 213956832 ps
CPU time 0.84 seconds
Started Jul 03 04:55:57 PM PDT 24
Finished Jul 03 04:55:59 PM PDT 24
Peak memory 206004 kb
Host smart-59f8b88b-cff8-4561-815a-44ba8009da19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24995
63248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2499563248
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.647775160
Short name T889
Test name
Test status
Simulation time 32611022 ps
CPU time 0.65 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:55:55 PM PDT 24
Peak memory 206124 kb
Host smart-1babfa1b-4570-4e57-a008-f8f74e132700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64777
5160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.647775160
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2044443882
Short name T846
Test name
Test status
Simulation time 957111222 ps
CPU time 2.28 seconds
Started Jul 03 04:56:03 PM PDT 24
Finished Jul 03 04:56:06 PM PDT 24
Peak memory 206336 kb
Host smart-d367839a-6209-4d8d-8edf-0f94b9fe040f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20444
43882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2044443882
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3886968623
Short name T1394
Test name
Test status
Simulation time 157723535 ps
CPU time 1.32 seconds
Started Jul 03 04:56:04 PM PDT 24
Finished Jul 03 04:56:06 PM PDT 24
Peak memory 206276 kb
Host smart-9000cd68-a81a-4b82-92c5-449347e3ef16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38869
68623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3886968623
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2724226895
Short name T2168
Test name
Test status
Simulation time 160795652 ps
CPU time 0.79 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206084 kb
Host smart-a7983bb7-965b-49c1-bed4-03ce55a0a291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27242
26895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2724226895
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1216799362
Short name T2363
Test name
Test status
Simulation time 149222505 ps
CPU time 0.78 seconds
Started Jul 03 04:55:59 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206124 kb
Host smart-2fbf8f28-de7e-437b-96fc-535e23864bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12167
99362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1216799362
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3884055610
Short name T399
Test name
Test status
Simulation time 164677623 ps
CPU time 0.79 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:55:58 PM PDT 24
Peak memory 206128 kb
Host smart-5eaebc1f-8b03-4f40-bb49-04c044dcc902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38840
55610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3884055610
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.373134646
Short name T686
Test name
Test status
Simulation time 167602484 ps
CPU time 0.84 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:02 PM PDT 24
Peak memory 206136 kb
Host smart-92876f73-acd4-4bd7-9567-4bc9e632108a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37313
4646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.373134646
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.793546131
Short name T748
Test name
Test status
Simulation time 23327943286 ps
CPU time 24.35 seconds
Started Jul 03 04:55:39 PM PDT 24
Finished Jul 03 04:56:04 PM PDT 24
Peak memory 206172 kb
Host smart-6183b9dc-1f4c-47f6-8840-b7c861a318c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79354
6131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.793546131
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3889221728
Short name T1621
Test name
Test status
Simulation time 3355420029 ps
CPU time 4.36 seconds
Started Jul 03 04:55:38 PM PDT 24
Finished Jul 03 04:55:42 PM PDT 24
Peak memory 206176 kb
Host smart-1407c947-d74f-449c-b7b8-ef78d4adacee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38892
21728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3889221728
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.4150511657
Short name T2112
Test name
Test status
Simulation time 9827708673 ps
CPU time 70.13 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:57:04 PM PDT 24
Peak memory 206408 kb
Host smart-c4f8d034-08d6-4e10-9cf2-0709e227187a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41505
11657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.4150511657
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.2764758487
Short name T2279
Test name
Test status
Simulation time 4837493903 ps
CPU time 43.22 seconds
Started Jul 03 04:55:54 PM PDT 24
Finished Jul 03 04:56:43 PM PDT 24
Peak memory 206376 kb
Host smart-d1784638-c8c4-455a-948a-6592f86c0a24
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2764758487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2764758487
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1293178278
Short name T1672
Test name
Test status
Simulation time 247776568 ps
CPU time 0.89 seconds
Started Jul 03 04:55:59 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206088 kb
Host smart-b2e27306-2a32-4f9c-9ad2-33ca744e1bf8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1293178278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1293178278
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2086544681
Short name T720
Test name
Test status
Simulation time 201520741 ps
CPU time 0.85 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:55:58 PM PDT 24
Peak memory 206116 kb
Host smart-d9e27245-baf7-4ff2-8230-e5dda91cb75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20865
44681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2086544681
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.61659944
Short name T2345
Test name
Test status
Simulation time 6745355694 ps
CPU time 64.43 seconds
Started Jul 03 04:55:40 PM PDT 24
Finished Jul 03 04:56:44 PM PDT 24
Peak memory 206372 kb
Host smart-6afd67df-fc1f-4457-872e-40b5141bfe88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61659
944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.61659944
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2766453889
Short name T2699
Test name
Test status
Simulation time 5860897602 ps
CPU time 43.97 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:56:38 PM PDT 24
Peak memory 206352 kb
Host smart-c3317bf0-ca2e-4675-b860-f5d067663725
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2766453889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2766453889
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.4197458327
Short name T594
Test name
Test status
Simulation time 161833678 ps
CPU time 0.77 seconds
Started Jul 03 04:55:52 PM PDT 24
Finished Jul 03 04:55:53 PM PDT 24
Peak memory 206128 kb
Host smart-776746d4-c135-42a8-b992-77067ced9055
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4197458327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.4197458327
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2229280067
Short name T463
Test name
Test status
Simulation time 149600980 ps
CPU time 0.86 seconds
Started Jul 03 04:55:38 PM PDT 24
Finished Jul 03 04:55:40 PM PDT 24
Peak memory 205916 kb
Host smart-c793287c-de12-49a0-96cc-c78d1c5a8b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292
80067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2229280067
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3166606417
Short name T2182
Test name
Test status
Simulation time 183830778 ps
CPU time 0.82 seconds
Started Jul 03 04:56:04 PM PDT 24
Finished Jul 03 04:56:06 PM PDT 24
Peak memory 206128 kb
Host smart-2237d414-ff40-4ddf-8ec3-66f0f4e4e0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31666
06417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3166606417
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.273740377
Short name T1879
Test name
Test status
Simulation time 176163255 ps
CPU time 0.83 seconds
Started Jul 03 04:55:35 PM PDT 24
Finished Jul 03 04:55:36 PM PDT 24
Peak memory 206132 kb
Host smart-844e8145-9258-4ae6-93db-305df9f53faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27374
0377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.273740377
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.877946414
Short name T1600
Test name
Test status
Simulation time 172890279 ps
CPU time 0.78 seconds
Started Jul 03 04:55:52 PM PDT 24
Finished Jul 03 04:55:53 PM PDT 24
Peak memory 206084 kb
Host smart-682da3a6-bf07-4982-97f0-7af0fde11b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87794
6414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.877946414
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1752687522
Short name T31
Test name
Test status
Simulation time 193781268 ps
CPU time 0.85 seconds
Started Jul 03 04:55:55 PM PDT 24
Finished Jul 03 04:55:56 PM PDT 24
Peak memory 206132 kb
Host smart-a3a3e3bb-540e-41eb-8847-0c773f9d2370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17526
87522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1752687522
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.598015534
Short name T1777
Test name
Test status
Simulation time 155593119 ps
CPU time 0.82 seconds
Started Jul 03 04:55:55 PM PDT 24
Finished Jul 03 04:55:56 PM PDT 24
Peak memory 206108 kb
Host smart-64fe572f-39d7-448d-aa62-b1b61c8a0209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59801
5534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.598015534
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3856370411
Short name T2079
Test name
Test status
Simulation time 219064039 ps
CPU time 0.92 seconds
Started Jul 03 04:55:34 PM PDT 24
Finished Jul 03 04:55:36 PM PDT 24
Peak memory 206104 kb
Host smart-9408f874-97f8-4e08-8ad5-3a9e853aa54b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3856370411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3856370411
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3170615197
Short name T2584
Test name
Test status
Simulation time 180383695 ps
CPU time 0.79 seconds
Started Jul 03 04:55:39 PM PDT 24
Finished Jul 03 04:55:40 PM PDT 24
Peak memory 206084 kb
Host smart-c046d69f-96b9-4c04-a78e-9b6fd0b5e936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31706
15197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3170615197
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2856166634
Short name T37
Test name
Test status
Simulation time 37781031 ps
CPU time 0.74 seconds
Started Jul 03 04:55:38 PM PDT 24
Finished Jul 03 04:55:39 PM PDT 24
Peak memory 205948 kb
Host smart-530cce8c-f1ed-4f25-a726-49ac3419880a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28561
66634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2856166634
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1916614541
Short name T2316
Test name
Test status
Simulation time 9420040913 ps
CPU time 19.89 seconds
Started Jul 03 04:56:02 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206424 kb
Host smart-6d86be92-bf41-4391-b58b-d0a364350872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19166
14541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1916614541
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.4245210379
Short name T547
Test name
Test status
Simulation time 148843357 ps
CPU time 0.79 seconds
Started Jul 03 04:55:44 PM PDT 24
Finished Jul 03 04:55:45 PM PDT 24
Peak memory 206132 kb
Host smart-6d53ce23-cd0a-4c96-bdcf-be60108e1d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42452
10379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.4245210379
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1716675031
Short name T621
Test name
Test status
Simulation time 209847452 ps
CPU time 0.9 seconds
Started Jul 03 04:55:52 PM PDT 24
Finished Jul 03 04:55:53 PM PDT 24
Peak memory 206040 kb
Host smart-f08df32e-13c7-4d50-a557-3a00c0510e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17166
75031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1716675031
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.542082577
Short name T1904
Test name
Test status
Simulation time 198069634 ps
CPU time 0.86 seconds
Started Jul 03 04:55:48 PM PDT 24
Finished Jul 03 04:55:50 PM PDT 24
Peak memory 205444 kb
Host smart-20f966d1-dfc0-4246-a2fe-7206a949d651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54208
2577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.542082577
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.1149990945
Short name T338
Test name
Test status
Simulation time 172454977 ps
CPU time 0.86 seconds
Started Jul 03 04:55:50 PM PDT 24
Finished Jul 03 04:55:51 PM PDT 24
Peak memory 206124 kb
Host smart-aabc3113-3162-4030-b22e-53e1821e9e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11499
90945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.1149990945
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.850994967
Short name T1523
Test name
Test status
Simulation time 203252098 ps
CPU time 0.85 seconds
Started Jul 03 04:55:55 PM PDT 24
Finished Jul 03 04:55:56 PM PDT 24
Peak memory 206128 kb
Host smart-591d360d-0d9a-4eb4-940d-3f8c31d8267c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85099
4967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.850994967
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.4183892003
Short name T333
Test name
Test status
Simulation time 147048162 ps
CPU time 0.78 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:55:48 PM PDT 24
Peak memory 206108 kb
Host smart-d2a5bd88-e79f-42f3-9807-8872653c805b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41838
92003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.4183892003
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3549924919
Short name T1289
Test name
Test status
Simulation time 149434304 ps
CPU time 0.78 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:55:58 PM PDT 24
Peak memory 206132 kb
Host smart-78e33c02-16bf-460a-9ef1-f923ef92dcca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35499
24919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3549924919
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1508578318
Short name T1143
Test name
Test status
Simulation time 206784718 ps
CPU time 0.91 seconds
Started Jul 03 04:55:48 PM PDT 24
Finished Jul 03 04:55:49 PM PDT 24
Peak memory 206112 kb
Host smart-57d3876b-53af-45d5-9619-eb53a5ca65a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15085
78318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1508578318
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1736077926
Short name T723
Test name
Test status
Simulation time 5790883041 ps
CPU time 163.16 seconds
Started Jul 03 04:56:05 PM PDT 24
Finished Jul 03 04:58:48 PM PDT 24
Peak memory 206436 kb
Host smart-90e453f3-df95-4999-8144-b8e2187f4181
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1736077926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1736077926
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1840238760
Short name T2336
Test name
Test status
Simulation time 196494219 ps
CPU time 0.87 seconds
Started Jul 03 04:55:44 PM PDT 24
Finished Jul 03 04:55:45 PM PDT 24
Peak memory 206148 kb
Host smart-f7418bc0-2495-4e18-9770-f0fd3fea609f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18402
38760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1840238760
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.385538567
Short name T1953
Test name
Test status
Simulation time 156269646 ps
CPU time 0.79 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206132 kb
Host smart-cc9cabde-c289-4295-b216-37fb83766116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38553
8567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.385538567
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.2386031515
Short name T964
Test name
Test status
Simulation time 915011533 ps
CPU time 1.86 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206308 kb
Host smart-c6ef8a88-18a8-4e38-9dc3-3b6ddb692f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23860
31515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.2386031515
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.4014976651
Short name T931
Test name
Test status
Simulation time 4043428258 ps
CPU time 29.49 seconds
Started Jul 03 04:55:46 PM PDT 24
Finished Jul 03 04:56:17 PM PDT 24
Peak memory 206348 kb
Host smart-6d3ee960-657f-44cc-99d5-91f6a86ad250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40149
76651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.4014976651
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.2656423105
Short name T598
Test name
Test status
Simulation time 66889087 ps
CPU time 0.72 seconds
Started Jul 03 04:55:54 PM PDT 24
Finished Jul 03 04:55:55 PM PDT 24
Peak memory 206056 kb
Host smart-559110b1-e03a-4810-8a28-dedc5dad1f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2656423105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.2656423105
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3677453218
Short name T1780
Test name
Test status
Simulation time 4255089095 ps
CPU time 5.04 seconds
Started Jul 03 04:55:51 PM PDT 24
Finished Jul 03 04:55:57 PM PDT 24
Peak memory 206196 kb
Host smart-d85f1a71-a3a3-4cc3-9490-aca8d10fc962
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3677453218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.3677453218
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3517610506
Short name T2610
Test name
Test status
Simulation time 13354890643 ps
CPU time 13.14 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:56:10 PM PDT 24
Peak memory 206152 kb
Host smart-fa2d62fd-8178-4ce4-9f14-e97732e8d1bd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3517610506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3517610506
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1069527006
Short name T768
Test name
Test status
Simulation time 23301229152 ps
CPU time 22.1 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:56:10 PM PDT 24
Peak memory 206392 kb
Host smart-85f6b6f4-7116-4878-8bf8-5d5f733fa61a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1069527006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.1069527006
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2761194669
Short name T384
Test name
Test status
Simulation time 156924249 ps
CPU time 0.79 seconds
Started Jul 03 04:55:45 PM PDT 24
Finished Jul 03 04:55:47 PM PDT 24
Peak memory 206080 kb
Host smart-5327f940-c0f6-4dc3-83ac-6bc7cde6acf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27611
94669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2761194669
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.4001224098
Short name T1906
Test name
Test status
Simulation time 192346295 ps
CPU time 0.84 seconds
Started Jul 03 04:55:44 PM PDT 24
Finished Jul 03 04:55:46 PM PDT 24
Peak memory 206144 kb
Host smart-df55d334-5336-4402-af6d-f559fd0b652d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40012
24098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.4001224098
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3447675645
Short name T1319
Test name
Test status
Simulation time 348340968 ps
CPU time 1.41 seconds
Started Jul 03 04:55:45 PM PDT 24
Finished Jul 03 04:55:47 PM PDT 24
Peak memory 206144 kb
Host smart-a09d960f-51fb-4657-b83d-3cbf3728123d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34476
75645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3447675645
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.574470050
Short name T117
Test name
Test status
Simulation time 869931278 ps
CPU time 2 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:56:00 PM PDT 24
Peak memory 206296 kb
Host smart-ae27c22b-28c7-4308-a2ea-8f0fbce9ac50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57447
0050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.574470050
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.300569307
Short name T1027
Test name
Test status
Simulation time 9508174497 ps
CPU time 16.43 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:18 PM PDT 24
Peak memory 206364 kb
Host smart-6a04a9a5-4af7-42c3-b916-80d5a1d87955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30056
9307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.300569307
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.3046692779
Short name T2053
Test name
Test status
Simulation time 456306838 ps
CPU time 1.58 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:55:49 PM PDT 24
Peak memory 206092 kb
Host smart-4cd4ba80-9e5d-4897-9e04-728a2b6be09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30466
92779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.3046692779
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1755187789
Short name T2024
Test name
Test status
Simulation time 168343088 ps
CPU time 0.76 seconds
Started Jul 03 04:56:11 PM PDT 24
Finished Jul 03 04:56:12 PM PDT 24
Peak memory 206104 kb
Host smart-d230ea46-5f39-42f2-a8e1-6d24b7b00dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17551
87789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1755187789
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2413843001
Short name T1252
Test name
Test status
Simulation time 28277108 ps
CPU time 0.64 seconds
Started Jul 03 04:56:03 PM PDT 24
Finished Jul 03 04:56:04 PM PDT 24
Peak memory 206080 kb
Host smart-59fa6219-dd53-4dda-87ea-981af77a6d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24138
43001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2413843001
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2427209203
Short name T2009
Test name
Test status
Simulation time 868794322 ps
CPU time 2.14 seconds
Started Jul 03 04:56:03 PM PDT 24
Finished Jul 03 04:56:05 PM PDT 24
Peak memory 206288 kb
Host smart-a96a9318-2731-46b1-95d3-a152f4211889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24272
09203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2427209203
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.300383819
Short name T688
Test name
Test status
Simulation time 390698355 ps
CPU time 2.3 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:55:50 PM PDT 24
Peak memory 206360 kb
Host smart-d341b247-2d57-42cd-a713-741f7d69572a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30038
3819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.300383819
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.172125234
Short name T1075
Test name
Test status
Simulation time 222989155 ps
CPU time 0.94 seconds
Started Jul 03 04:55:46 PM PDT 24
Finished Jul 03 04:55:47 PM PDT 24
Peak memory 206128 kb
Host smart-b5c8b17a-34b6-4319-b141-07e13487f96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17212
5234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.172125234
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1686190574
Short name T1282
Test name
Test status
Simulation time 199343893 ps
CPU time 0.8 seconds
Started Jul 03 04:55:52 PM PDT 24
Finished Jul 03 04:55:53 PM PDT 24
Peak memory 206104 kb
Host smart-4c551d89-51b1-4d27-b018-4f05ccecc93c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16861
90574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1686190574
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1850464033
Short name T409
Test name
Test status
Simulation time 269460202 ps
CPU time 0.92 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:55:58 PM PDT 24
Peak memory 206092 kb
Host smart-60ca0f9b-c19e-407f-92bb-e6fe6420c0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18504
64033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1850464033
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3588252370
Short name T549
Test name
Test status
Simulation time 219894317 ps
CPU time 0.89 seconds
Started Jul 03 04:55:55 PM PDT 24
Finished Jul 03 04:55:56 PM PDT 24
Peak memory 206096 kb
Host smart-5c59387f-33d1-4253-89cf-adf76c034d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35882
52370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3588252370
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1893848974
Short name T611
Test name
Test status
Simulation time 23307206966 ps
CPU time 24.57 seconds
Started Jul 03 04:56:05 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206164 kb
Host smart-e8a1354e-3216-4609-a4bb-64c3c6bc0825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18938
48974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1893848974
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.828086459
Short name T563
Test name
Test status
Simulation time 3304752799 ps
CPU time 3.72 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:04 PM PDT 24
Peak memory 206156 kb
Host smart-af892e9f-7d7d-4094-a419-b37f863d0229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82808
6459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.828086459
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3965385319
Short name T1474
Test name
Test status
Simulation time 9177291631 ps
CPU time 87.02 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:57:21 PM PDT 24
Peak memory 206424 kb
Host smart-4ef1eaee-4719-464f-b5ee-ab3fe17381bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39653
85319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3965385319
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.872361086
Short name T1623
Test name
Test status
Simulation time 5872776168 ps
CPU time 155.72 seconds
Started Jul 03 04:55:46 PM PDT 24
Finished Jul 03 04:58:23 PM PDT 24
Peak memory 206388 kb
Host smart-71a72510-af7b-4105-8f8d-84b198b22bb0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=872361086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.872361086
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1912242804
Short name T2212
Test name
Test status
Simulation time 260939334 ps
CPU time 0.92 seconds
Started Jul 03 04:56:07 PM PDT 24
Finished Jul 03 04:56:08 PM PDT 24
Peak memory 206096 kb
Host smart-11e4fa63-50e0-455d-ad17-1d836c2701af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1912242804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1912242804
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.425161505
Short name T1374
Test name
Test status
Simulation time 226879103 ps
CPU time 0.85 seconds
Started Jul 03 04:55:57 PM PDT 24
Finished Jul 03 04:55:59 PM PDT 24
Peak memory 206104 kb
Host smart-4ee86261-4435-4d53-ae18-2d9a569b4953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42516
1505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.425161505
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.4054917253
Short name T1680
Test name
Test status
Simulation time 6407785674 ps
CPU time 181.76 seconds
Started Jul 03 04:55:46 PM PDT 24
Finished Jul 03 04:58:49 PM PDT 24
Peak memory 206404 kb
Host smart-851a274a-1a1c-4919-91b9-f1fb4286318b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40549
17253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.4054917253
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.1583031862
Short name T414
Test name
Test status
Simulation time 4117711885 ps
CPU time 116.4 seconds
Started Jul 03 04:55:45 PM PDT 24
Finished Jul 03 04:57:42 PM PDT 24
Peak memory 206360 kb
Host smart-4ce9c064-b2a6-4e4b-8c2d-f7ab10a28006
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1583031862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.1583031862
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2801609815
Short name T358
Test name
Test status
Simulation time 163918335 ps
CPU time 0.8 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:55:58 PM PDT 24
Peak memory 206092 kb
Host smart-99c31431-5d14-4d10-96d4-884ef189fe30
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2801609815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2801609815
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2960188397
Short name T1061
Test name
Test status
Simulation time 155327933 ps
CPU time 0.81 seconds
Started Jul 03 04:55:46 PM PDT 24
Finished Jul 03 04:55:48 PM PDT 24
Peak memory 206112 kb
Host smart-b09ccb76-432c-4b1f-a644-93674d08d078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29601
88397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2960188397
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1234730058
Short name T1454
Test name
Test status
Simulation time 182260873 ps
CPU time 0.82 seconds
Started Jul 03 04:56:06 PM PDT 24
Finished Jul 03 04:56:07 PM PDT 24
Peak memory 206104 kb
Host smart-d0dcf789-668e-40f3-9e85-d0f80af9b65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12347
30058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1234730058
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.150714027
Short name T2161
Test name
Test status
Simulation time 166598657 ps
CPU time 0.88 seconds
Started Jul 03 04:55:46 PM PDT 24
Finished Jul 03 04:55:48 PM PDT 24
Peak memory 206124 kb
Host smart-61bab664-e69c-4a71-a750-4cb90d4cb56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15071
4027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.150714027
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.4157280039
Short name T2304
Test name
Test status
Simulation time 174435159 ps
CPU time 0.83 seconds
Started Jul 03 04:55:49 PM PDT 24
Finished Jul 03 04:55:50 PM PDT 24
Peak memory 206128 kb
Host smart-656045c4-0c14-4a6b-9802-e897c0d5b83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41572
80039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.4157280039
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1029796089
Short name T2047
Test name
Test status
Simulation time 174795883 ps
CPU time 0.8 seconds
Started Jul 03 04:55:49 PM PDT 24
Finished Jul 03 04:55:50 PM PDT 24
Peak memory 206132 kb
Host smart-e4b52388-3492-4537-8c9c-4ab355bdc7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10297
96089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1029796089
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.4225935425
Short name T2287
Test name
Test status
Simulation time 158560624 ps
CPU time 0.87 seconds
Started Jul 03 04:56:04 PM PDT 24
Finished Jul 03 04:56:05 PM PDT 24
Peak memory 206080 kb
Host smart-9da1f13b-064e-4ffa-a2ee-4ba20a99c668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42259
35425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.4225935425
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2723223141
Short name T1840
Test name
Test status
Simulation time 210361976 ps
CPU time 0.87 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:55:54 PM PDT 24
Peak memory 206412 kb
Host smart-230c5755-f69e-4abf-bf89-6309c0891676
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2723223141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2723223141
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2166604501
Short name T2064
Test name
Test status
Simulation time 181499975 ps
CPU time 0.83 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:55:48 PM PDT 24
Peak memory 206108 kb
Host smart-42341335-c63b-4b2b-86e1-84655574000d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21666
04501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2166604501
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1231131698
Short name T1685
Test name
Test status
Simulation time 93697708 ps
CPU time 0.75 seconds
Started Jul 03 04:55:51 PM PDT 24
Finished Jul 03 04:55:52 PM PDT 24
Peak memory 206140 kb
Host smart-6edbbc63-8ae3-47c2-b8cd-13915f4ddd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12311
31698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1231131698
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.29819127
Short name T299
Test name
Test status
Simulation time 18871414703 ps
CPU time 40.51 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 214680 kb
Host smart-c61bd9ed-722a-49ed-bdd9-d037d44f22b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29819
127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.29819127
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.345792119
Short name T2048
Test name
Test status
Simulation time 187972684 ps
CPU time 0.86 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:55:49 PM PDT 24
Peak memory 206132 kb
Host smart-fd26af70-73e9-4206-b55f-f5e62fa520ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34579
2119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.345792119
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2160466904
Short name T2234
Test name
Test status
Simulation time 279589003 ps
CPU time 0.97 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:56:00 PM PDT 24
Peak memory 206096 kb
Host smart-89bf3e74-241c-406b-9c3f-756750fc8f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21604
66904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2160466904
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1513303660
Short name T1997
Test name
Test status
Simulation time 206397914 ps
CPU time 0.87 seconds
Started Jul 03 04:55:50 PM PDT 24
Finished Jul 03 04:55:51 PM PDT 24
Peak memory 206092 kb
Host smart-f8adae00-bf4a-4caf-a1e0-94036cb9dfb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15133
03660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1513303660
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.3381092479
Short name T1752
Test name
Test status
Simulation time 260030010 ps
CPU time 0.92 seconds
Started Jul 03 04:56:14 PM PDT 24
Finished Jul 03 04:56:16 PM PDT 24
Peak memory 206136 kb
Host smart-13aed0de-0fa4-4888-9797-755cb34048db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33810
92479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.3381092479
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.2570733999
Short name T2169
Test name
Test status
Simulation time 181118008 ps
CPU time 0.85 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:23 PM PDT 24
Peak memory 206088 kb
Host smart-02209cbe-8332-47a5-a435-22e1aac56757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25707
33999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.2570733999
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1674899163
Short name T606
Test name
Test status
Simulation time 152934643 ps
CPU time 0.79 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206072 kb
Host smart-ea528475-904e-42a8-b96e-c1246440bdcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16748
99163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1674899163
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3124567082
Short name T701
Test name
Test status
Simulation time 206744075 ps
CPU time 0.82 seconds
Started Jul 03 04:55:47 PM PDT 24
Finished Jul 03 04:55:49 PM PDT 24
Peak memory 206044 kb
Host smart-68b09b0a-7650-4171-9cb1-ad7fab49a07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31245
67082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3124567082
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1864706406
Short name T965
Test name
Test status
Simulation time 251170219 ps
CPU time 0.94 seconds
Started Jul 03 04:55:49 PM PDT 24
Finished Jul 03 04:55:50 PM PDT 24
Peak memory 206128 kb
Host smart-f4772308-500c-44d0-abd8-c56e72877bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18647
06406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1864706406
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.4036450762
Short name T2330
Test name
Test status
Simulation time 4302788997 ps
CPU time 117.81 seconds
Started Jul 03 04:56:03 PM PDT 24
Finished Jul 03 04:58:02 PM PDT 24
Peak memory 206420 kb
Host smart-ebf9af03-fe9c-41fe-9c07-796839c60416
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4036450762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.4036450762
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2319935644
Short name T1322
Test name
Test status
Simulation time 189147230 ps
CPU time 0.81 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:55:58 PM PDT 24
Peak memory 206044 kb
Host smart-d8e268c2-094a-48f3-825a-eaa72d1e2626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23199
35644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2319935644
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.21578636
Short name T1387
Test name
Test status
Simulation time 181686092 ps
CPU time 0.82 seconds
Started Jul 03 04:55:48 PM PDT 24
Finished Jul 03 04:55:50 PM PDT 24
Peak memory 206088 kb
Host smart-2523dcf9-421c-4873-92de-d2adbddc8f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21578
636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.21578636
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.3192637390
Short name T346
Test name
Test status
Simulation time 578015840 ps
CPU time 1.58 seconds
Started Jul 03 04:55:51 PM PDT 24
Finished Jul 03 04:55:53 PM PDT 24
Peak memory 206144 kb
Host smart-e317ea64-6e4c-4078-8896-100db9f34962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31926
37390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.3192637390
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.77174885
Short name T1907
Test name
Test status
Simulation time 4508302501 ps
CPU time 38.39 seconds
Started Jul 03 04:55:49 PM PDT 24
Finished Jul 03 04:56:28 PM PDT 24
Peak memory 206388 kb
Host smart-7669961e-9828-4da8-b6fe-5359d9bbe8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77174
885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.77174885
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2513043360
Short name T396
Test name
Test status
Simulation time 45487889 ps
CPU time 0.73 seconds
Started Jul 03 04:55:59 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206172 kb
Host smart-c65f93ab-3df1-4905-b3c3-2f7ba47e8395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2513043360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2513043360
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.4184859727
Short name T684
Test name
Test status
Simulation time 3840605619 ps
CPU time 4.67 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206160 kb
Host smart-c2336e0b-b511-4cc8-9ec4-3e920b946829
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4184859727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.4184859727
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1934319250
Short name T2190
Test name
Test status
Simulation time 13449137544 ps
CPU time 16.38 seconds
Started Jul 03 04:55:54 PM PDT 24
Finished Jul 03 04:56:11 PM PDT 24
Peak memory 206136 kb
Host smart-4354c381-42ea-41a7-858b-9e15a601b16b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1934319250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1934319250
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.2920695264
Short name T977
Test name
Test status
Simulation time 23409788847 ps
CPU time 28.41 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:56:26 PM PDT 24
Peak memory 206440 kb
Host smart-cc759bee-c4a0-430b-91dd-e51c13f34d99
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2920695264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.2920695264
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3958797034
Short name T2183
Test name
Test status
Simulation time 160682965 ps
CPU time 0.78 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206100 kb
Host smart-d9130c90-d716-4f6a-9595-7808ef7e7b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39587
97034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3958797034
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2118982390
Short name T668
Test name
Test status
Simulation time 155333533 ps
CPU time 0.78 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:55:59 PM PDT 24
Peak memory 206128 kb
Host smart-70bf9c28-2c01-4cc4-aa7b-4fa13e85b83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21189
82390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2118982390
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2617919643
Short name T940
Test name
Test status
Simulation time 241450706 ps
CPU time 0.97 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:55:55 PM PDT 24
Peak memory 206076 kb
Host smart-c2426f57-8394-4640-aeb9-7a1d53c49d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179
19643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2617919643
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.475150118
Short name T2186
Test name
Test status
Simulation time 631999771 ps
CPU time 1.63 seconds
Started Jul 03 04:56:14 PM PDT 24
Finished Jul 03 04:56:16 PM PDT 24
Peak memory 206108 kb
Host smart-68498f1b-0d93-484d-89a8-5049ad51e31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47515
0118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.475150118
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.1941229536
Short name T2647
Test name
Test status
Simulation time 14555232425 ps
CPU time 27.32 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:56:21 PM PDT 24
Peak memory 206316 kb
Host smart-4d28e82a-191b-4235-8162-f48fb0d15b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19412
29536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.1941229536
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1940531320
Short name T1869
Test name
Test status
Simulation time 479640281 ps
CPU time 1.45 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:55:55 PM PDT 24
Peak memory 205980 kb
Host smart-d98951a4-4174-4eb7-bdb7-3fccf37dfefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19405
31320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1940531320
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1756549071
Short name T1963
Test name
Test status
Simulation time 153338321 ps
CPU time 0.77 seconds
Started Jul 03 04:56:09 PM PDT 24
Finished Jul 03 04:56:10 PM PDT 24
Peak memory 206100 kb
Host smart-70052b22-06b3-4c22-8821-14bf3a2a8f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17565
49071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1756549071
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.642421904
Short name T2360
Test name
Test status
Simulation time 34699605 ps
CPU time 0.67 seconds
Started Jul 03 04:55:54 PM PDT 24
Finished Jul 03 04:55:56 PM PDT 24
Peak memory 206068 kb
Host smart-1330ed81-fdee-42d7-9e1e-d65704028263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64242
1904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.642421904
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.107205978
Short name T156
Test name
Test status
Simulation time 1058092696 ps
CPU time 2.56 seconds
Started Jul 03 04:55:54 PM PDT 24
Finished Jul 03 04:55:57 PM PDT 24
Peak memory 206320 kb
Host smart-5ad22f0f-01ec-45a0-9b8e-42b70ddc64a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10720
5978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.107205978
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.321341246
Short name T2536
Test name
Test status
Simulation time 190442486 ps
CPU time 2.13 seconds
Started Jul 03 04:55:54 PM PDT 24
Finished Jul 03 04:55:57 PM PDT 24
Peak memory 206360 kb
Host smart-84628b97-3589-4c7e-81e4-6b1a4512f9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32134
1246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.321341246
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3099434299
Short name T1982
Test name
Test status
Simulation time 216657509 ps
CPU time 0.85 seconds
Started Jul 03 04:55:59 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206036 kb
Host smart-8b43a086-2df3-46be-9edd-6acee1ba7fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30994
34299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3099434299
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2432721533
Short name T1067
Test name
Test status
Simulation time 136020649 ps
CPU time 0.77 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:24 PM PDT 24
Peak memory 206088 kb
Host smart-6deb90b0-24f9-4a58-84d7-8a8553d3a071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24327
21533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2432721533
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2944338491
Short name T1762
Test name
Test status
Simulation time 207383580 ps
CPU time 0.91 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206120 kb
Host smart-b758c163-b5f2-4a5a-95b2-b156f23599c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29443
38491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2944338491
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1900326672
Short name T503
Test name
Test status
Simulation time 171004518 ps
CPU time 0.8 seconds
Started Jul 03 04:55:54 PM PDT 24
Finished Jul 03 04:55:55 PM PDT 24
Peak memory 206004 kb
Host smart-d556a062-141a-47db-afb9-cb792b28ac7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19003
26672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1900326672
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.257009673
Short name T1307
Test name
Test status
Simulation time 23333385723 ps
CPU time 23.77 seconds
Started Jul 03 04:55:57 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206172 kb
Host smart-339dc108-6141-46e1-a750-6f6e72665da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25700
9673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.257009673
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.3924929689
Short name T838
Test name
Test status
Simulation time 3340432470 ps
CPU time 4.25 seconds
Started Jul 03 04:55:54 PM PDT 24
Finished Jul 03 04:55:59 PM PDT 24
Peak memory 206196 kb
Host smart-f6d3dc02-35d9-4672-bf4e-bb9e9661d0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39249
29689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3924929689
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1371958608
Short name T2417
Test name
Test status
Simulation time 12109375256 ps
CPU time 338.8 seconds
Started Jul 03 04:56:20 PM PDT 24
Finished Jul 03 05:02:00 PM PDT 24
Peak memory 206360 kb
Host smart-6a46ab05-66ba-4bb6-b542-e17a824d39ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13719
58608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1371958608
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.1575762758
Short name T715
Test name
Test status
Simulation time 4420630443 ps
CPU time 33.26 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206396 kb
Host smart-7e87b3da-2def-46e7-aa26-c667b9b35ddc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1575762758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.1575762758
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1374970104
Short name T2043
Test name
Test status
Simulation time 263210171 ps
CPU time 0.96 seconds
Started Jul 03 04:56:20 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206108 kb
Host smart-11c21e38-2e21-47c9-aa27-aeae43f298ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1374970104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1374970104
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2496190041
Short name T2586
Test name
Test status
Simulation time 188699033 ps
CPU time 0.86 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:02 PM PDT 24
Peak memory 206072 kb
Host smart-a2ee6f59-c39a-4c56-9f5b-342fbba12804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24961
90041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2496190041
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.956299543
Short name T2058
Test name
Test status
Simulation time 3018671867 ps
CPU time 78.12 seconds
Started Jul 03 04:55:57 PM PDT 24
Finished Jul 03 04:57:17 PM PDT 24
Peak memory 206412 kb
Host smart-fe46810f-e610-4f6c-967c-1f0ce03ad77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95629
9543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.956299543
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2857802466
Short name T1598
Test name
Test status
Simulation time 4684596039 ps
CPU time 120.01 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:58:02 PM PDT 24
Peak memory 206412 kb
Host smart-c477072a-c605-490e-8ada-cc771a5c7be4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2857802466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2857802466
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2193831160
Short name T1432
Test name
Test status
Simulation time 189207057 ps
CPU time 0.83 seconds
Started Jul 03 04:55:53 PM PDT 24
Finished Jul 03 04:55:54 PM PDT 24
Peak memory 206096 kb
Host smart-f3140314-c856-4c5f-800a-e4300901be3f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2193831160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2193831160
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.4172494760
Short name T1784
Test name
Test status
Simulation time 154523213 ps
CPU time 0.79 seconds
Started Jul 03 04:55:57 PM PDT 24
Finished Jul 03 04:55:59 PM PDT 24
Peak memory 206072 kb
Host smart-2913b153-2b7f-4901-bfd2-19fead1eb9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41724
94760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.4172494760
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3610370624
Short name T2416
Test name
Test status
Simulation time 234513040 ps
CPU time 0.94 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:56:00 PM PDT 24
Peak memory 206132 kb
Host smart-c652e2a3-205f-4c64-904b-a648e6c76307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36103
70624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3610370624
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.471181933
Short name T1924
Test name
Test status
Simulation time 193484942 ps
CPU time 0.83 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:02 PM PDT 24
Peak memory 206048 kb
Host smart-578700a0-1f12-4ce5-994b-c453690c7273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47118
1933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.471181933
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3205761504
Short name T1042
Test name
Test status
Simulation time 182552645 ps
CPU time 0.87 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:56:00 PM PDT 24
Peak memory 206080 kb
Host smart-e5850b75-d9ca-4428-a3cb-1b9d81e065af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32057
61504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3205761504
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1102191675
Short name T1492
Test name
Test status
Simulation time 208881690 ps
CPU time 0.89 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206120 kb
Host smart-e68e3e25-14f8-4006-878f-c7ab1ad0b0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11021
91675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1102191675
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.47086263
Short name T1861
Test name
Test status
Simulation time 206700383 ps
CPU time 0.86 seconds
Started Jul 03 04:56:21 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206124 kb
Host smart-8f5cf225-5519-4784-a1dd-3f420dc3199e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47086
263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.47086263
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.3569323984
Short name T826
Test name
Test status
Simulation time 241859345 ps
CPU time 0.94 seconds
Started Jul 03 04:55:59 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206056 kb
Host smart-e7448dc2-b44b-4be7-8a63-718fce5c44b6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3569323984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.3569323984
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3454737071
Short name T704
Test name
Test status
Simulation time 178575107 ps
CPU time 0.76 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:02 PM PDT 24
Peak memory 206036 kb
Host smart-4822d461-3707-46a0-9a44-20d5ad2538b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34547
37071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3454737071
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.260426951
Short name T933
Test name
Test status
Simulation time 36004674 ps
CPU time 0.66 seconds
Started Jul 03 04:56:07 PM PDT 24
Finished Jul 03 04:56:08 PM PDT 24
Peak memory 205992 kb
Host smart-e3fddfc8-48db-4538-8a54-febec0855f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26042
6951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.260426951
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.243870908
Short name T1087
Test name
Test status
Simulation time 17699144967 ps
CPU time 40.11 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:56:37 PM PDT 24
Peak memory 206448 kb
Host smart-f5c522d6-a893-4656-aece-984a0756a584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24387
0908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.243870908
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.671309539
Short name T2458
Test name
Test status
Simulation time 162977798 ps
CPU time 0.82 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:55:58 PM PDT 24
Peak memory 206092 kb
Host smart-251e0ce7-e460-447b-a830-0ebb40b3e1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67130
9539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.671309539
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2398951695
Short name T1984
Test name
Test status
Simulation time 184982037 ps
CPU time 0.84 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:56:00 PM PDT 24
Peak memory 206120 kb
Host smart-63b5e472-0da8-4007-9504-8217c1cf2949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23989
51695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2398951695
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1546341670
Short name T1989
Test name
Test status
Simulation time 220661532 ps
CPU time 0.86 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:55:58 PM PDT 24
Peak memory 206092 kb
Host smart-5591bdf3-faa3-40b5-98f8-cec2c208dac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15463
41670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1546341670
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3661920621
Short name T2286
Test name
Test status
Simulation time 160541383 ps
CPU time 0.82 seconds
Started Jul 03 04:56:08 PM PDT 24
Finished Jul 03 04:56:09 PM PDT 24
Peak memory 206136 kb
Host smart-17695538-d49f-4970-9d29-4803f88608bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36619
20621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3661920621
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2995760675
Short name T1529
Test name
Test status
Simulation time 152128531 ps
CPU time 0.8 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206132 kb
Host smart-f09772a9-ce5a-4742-b9b8-f32d8cba59e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29957
60675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2995760675
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1143503998
Short name T1197
Test name
Test status
Simulation time 167204992 ps
CPU time 0.79 seconds
Started Jul 03 04:56:19 PM PDT 24
Finished Jul 03 04:56:20 PM PDT 24
Peak memory 206092 kb
Host smart-4f288bf6-0705-4c8c-a213-3d55eeae4c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11435
03998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1143503998
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1688745772
Short name T957
Test name
Test status
Simulation time 156094463 ps
CPU time 0.84 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:24 PM PDT 24
Peak memory 206132 kb
Host smart-dffc3c32-6f0b-4adb-bb11-af079ea3862a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16887
45772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1688745772
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.971614605
Short name T356
Test name
Test status
Simulation time 226736894 ps
CPU time 0.91 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206104 kb
Host smart-f9fc5e9c-d2b5-44d2-81c6-40b7eb5fb1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97161
4605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.971614605
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.498874384
Short name T1789
Test name
Test status
Simulation time 5913036851 ps
CPU time 56.37 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:57:20 PM PDT 24
Peak memory 206380 kb
Host smart-24efdea6-8d10-4b4c-8da5-763acc7ccdde
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=498874384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.498874384
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3582972246
Short name T2365
Test name
Test status
Simulation time 246295822 ps
CPU time 0.9 seconds
Started Jul 03 04:56:02 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206096 kb
Host smart-0f90587a-bd07-4a00-b39f-88462659f72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35829
72246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3582972246
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.983123823
Short name T763
Test name
Test status
Simulation time 194863706 ps
CPU time 0.86 seconds
Started Jul 03 04:55:56 PM PDT 24
Finished Jul 03 04:55:58 PM PDT 24
Peak memory 206148 kb
Host smart-a1e46bc1-0027-43d8-b099-56375407755e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98312
3823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.983123823
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.2365357315
Short name T740
Test name
Test status
Simulation time 921470310 ps
CPU time 2.07 seconds
Started Jul 03 04:56:12 PM PDT 24
Finished Jul 03 04:56:15 PM PDT 24
Peak memory 206312 kb
Host smart-55a8056a-5586-4db5-8e13-7827db2791d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23653
57315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.2365357315
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1430309545
Short name T2576
Test name
Test status
Simulation time 7349301071 ps
CPU time 213.78 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:59:33 PM PDT 24
Peak memory 206424 kb
Host smart-fca525a2-33bb-4af1-a3ca-a92b3874b750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14303
09545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1430309545
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.2725480618
Short name T914
Test name
Test status
Simulation time 37344847 ps
CPU time 0.65 seconds
Started Jul 03 04:56:19 PM PDT 24
Finished Jul 03 04:56:20 PM PDT 24
Peak memory 206468 kb
Host smart-eea55735-d1bb-4778-b9fb-5e47f8eff813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2725480618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2725480618
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2708584200
Short name T11
Test name
Test status
Simulation time 3637894977 ps
CPU time 4.57 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:07 PM PDT 24
Peak memory 206148 kb
Host smart-8d0e6271-c69b-4f44-b569-a129064f0a19
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2708584200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2708584200
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3039220341
Short name T1123
Test name
Test status
Simulation time 13346463437 ps
CPU time 14.23 seconds
Started Jul 03 04:56:09 PM PDT 24
Finished Jul 03 04:56:23 PM PDT 24
Peak memory 206260 kb
Host smart-53f3dda9-8f91-4f44-9498-cdf042b72f91
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3039220341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3039220341
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.399579723
Short name T1140
Test name
Test status
Simulation time 23366529090 ps
CPU time 21.81 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:24 PM PDT 24
Peak memory 206312 kb
Host smart-5e79b4bb-3739-4303-808b-008cda2f89f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=399579723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.399579723
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2524537699
Short name T1115
Test name
Test status
Simulation time 166036250 ps
CPU time 0.79 seconds
Started Jul 03 04:55:57 PM PDT 24
Finished Jul 03 04:55:59 PM PDT 24
Peak memory 206092 kb
Host smart-07327c58-a1c0-430f-9798-78a586ff373b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245
37699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2524537699
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3679851912
Short name T625
Test name
Test status
Simulation time 171672015 ps
CPU time 0.8 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206132 kb
Host smart-5dbe7a1c-9278-44a4-b465-311b48196b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36798
51912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3679851912
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.1970703290
Short name T2441
Test name
Test status
Simulation time 471855714 ps
CPU time 1.4 seconds
Started Jul 03 04:55:59 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206076 kb
Host smart-566060a1-76a5-4f3c-8a66-fb538c96fdf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
03290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.1970703290
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3864272914
Short name T186
Test name
Test status
Simulation time 1365965772 ps
CPU time 3.09 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:04 PM PDT 24
Peak memory 206332 kb
Host smart-af46a09a-5754-473c-9f1f-9a1d8774dd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38642
72914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3864272914
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1866424114
Short name T1571
Test name
Test status
Simulation time 13112656652 ps
CPU time 28.43 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:56:27 PM PDT 24
Peak memory 206368 kb
Host smart-09184181-fa41-433d-979c-bf15e945082a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18664
24114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1866424114
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.558726375
Short name T1290
Test name
Test status
Simulation time 334530592 ps
CPU time 1.11 seconds
Started Jul 03 04:56:20 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206084 kb
Host smart-b78ea2f8-0944-4042-bd00-65bbd3a372ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55872
6375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.558726375
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.208889607
Short name T1500
Test name
Test status
Simulation time 149008825 ps
CPU time 0.81 seconds
Started Jul 03 04:56:19 PM PDT 24
Finished Jul 03 04:56:20 PM PDT 24
Peak memory 206104 kb
Host smart-4ccb753e-aa25-48ce-aa3d-c02f1652cf9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20888
9607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.208889607
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.210115311
Short name T962
Test name
Test status
Simulation time 64031267 ps
CPU time 0.68 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:02 PM PDT 24
Peak memory 206072 kb
Host smart-88c134c4-9adc-4ce3-8148-9f0095900c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21011
5311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.210115311
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.151176335
Short name T1597
Test name
Test status
Simulation time 898139037 ps
CPU time 2.15 seconds
Started Jul 03 04:56:15 PM PDT 24
Finished Jul 03 04:56:17 PM PDT 24
Peak memory 206340 kb
Host smart-6fb4c54a-d67a-409e-99d9-2d548a4e8ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15117
6335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.151176335
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1687683171
Short name T2060
Test name
Test status
Simulation time 191142716 ps
CPU time 2.25 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:56:01 PM PDT 24
Peak memory 206296 kb
Host smart-13a9cee7-a3a5-4583-bdb5-bec6587a0749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16876
83171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1687683171
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3167154605
Short name T2684
Test name
Test status
Simulation time 190847853 ps
CPU time 0.83 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206108 kb
Host smart-2adf8b07-1add-45fa-b50e-c885d1b2b155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31671
54605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3167154605
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.932424562
Short name T603
Test name
Test status
Simulation time 147160750 ps
CPU time 0.78 seconds
Started Jul 03 04:56:09 PM PDT 24
Finished Jul 03 04:56:10 PM PDT 24
Peak memory 206088 kb
Host smart-ff0e27de-ac99-4a84-91d2-f87e86c70e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93242
4562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.932424562
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2853748811
Short name T1214
Test name
Test status
Simulation time 248698336 ps
CPU time 0.98 seconds
Started Jul 03 04:56:12 PM PDT 24
Finished Jul 03 04:56:13 PM PDT 24
Peak memory 206060 kb
Host smart-f720262e-cafc-4eec-a74e-6a4f4227b1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28537
48811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2853748811
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.1392471529
Short name T2219
Test name
Test status
Simulation time 5740269050 ps
CPU time 55.47 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:57 PM PDT 24
Peak memory 206400 kb
Host smart-35e1c057-0ba4-4cab-83e3-2ab67aba235c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1392471529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.1392471529
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.247046908
Short name T2593
Test name
Test status
Simulation time 167179049 ps
CPU time 0.81 seconds
Started Jul 03 04:56:17 PM PDT 24
Finished Jul 03 04:56:18 PM PDT 24
Peak memory 206092 kb
Host smart-4d62ae1b-a2e8-4386-9094-e9dff98deceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24704
6908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.247046908
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.358118672
Short name T936
Test name
Test status
Simulation time 23343381233 ps
CPU time 20.9 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:23 PM PDT 24
Peak memory 206148 kb
Host smart-23d99ff5-1fe5-45fe-95ad-c0590b244482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35811
8672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.358118672
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.123272394
Short name T1018
Test name
Test status
Simulation time 3378851821 ps
CPU time 4.2 seconds
Started Jul 03 04:55:59 PM PDT 24
Finished Jul 03 04:56:05 PM PDT 24
Peak memory 206144 kb
Host smart-40d7af20-d195-41f3-b401-a2fed79b1cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12327
2394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.123272394
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.241956565
Short name T1620
Test name
Test status
Simulation time 11309149851 ps
CPU time 79.92 seconds
Started Jul 03 04:55:58 PM PDT 24
Finished Jul 03 04:57:19 PM PDT 24
Peak memory 206404 kb
Host smart-eb0cf85a-90a3-4666-9c07-acb224999998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24195
6565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.241956565
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.4239869648
Short name T737
Test name
Test status
Simulation time 4424101468 ps
CPU time 40.82 seconds
Started Jul 03 04:56:16 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206392 kb
Host smart-8ea322a0-440f-4347-a75a-a6f1d616ef0e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4239869648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.4239869648
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2624327902
Short name T1704
Test name
Test status
Simulation time 243640933 ps
CPU time 0.95 seconds
Started Jul 03 04:56:00 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206052 kb
Host smart-0d2a082e-84de-4a8b-bdb8-66a159bd8199
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2624327902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2624327902
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3446099109
Short name T1420
Test name
Test status
Simulation time 207312833 ps
CPU time 0.82 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:27 PM PDT 24
Peak memory 206108 kb
Host smart-9b21c302-2fab-47ba-96f9-0b3f3e340ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34460
99109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3446099109
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.3664836235
Short name T2258
Test name
Test status
Simulation time 5893757551 ps
CPU time 55.8 seconds
Started Jul 03 04:56:08 PM PDT 24
Finished Jul 03 04:57:04 PM PDT 24
Peak memory 206360 kb
Host smart-92ae7c01-f984-46eb-9265-1e939bc48fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36648
36235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.3664836235
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.996464690
Short name T666
Test name
Test status
Simulation time 4599194732 ps
CPU time 126.2 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:58:08 PM PDT 24
Peak memory 206384 kb
Host smart-b5941bf6-be68-4797-8992-07df04c57a0e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=996464690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.996464690
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.820674607
Short name T819
Test name
Test status
Simulation time 168521936 ps
CPU time 0.84 seconds
Started Jul 03 04:56:03 PM PDT 24
Finished Jul 03 04:56:04 PM PDT 24
Peak memory 206116 kb
Host smart-6e4c960f-b4e3-4558-921f-862ec318657b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=820674607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.820674607
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3943196062
Short name T2181
Test name
Test status
Simulation time 164362612 ps
CPU time 0.8 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206112 kb
Host smart-fcb6c926-8a43-4eb5-900f-f78586127f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39431
96062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3943196062
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.426096960
Short name T131
Test name
Test status
Simulation time 257011103 ps
CPU time 0.94 seconds
Started Jul 03 04:55:59 PM PDT 24
Finished Jul 03 04:56:02 PM PDT 24
Peak memory 206108 kb
Host smart-9fdf1b0a-68a2-49ae-b401-96aa90c030a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42609
6960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.426096960
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.450929128
Short name T1359
Test name
Test status
Simulation time 174458344 ps
CPU time 1.02 seconds
Started Jul 03 04:56:02 PM PDT 24
Finished Jul 03 04:56:04 PM PDT 24
Peak memory 206140 kb
Host smart-252eb492-786d-4af3-ae09-9930dd18f928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45092
9128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.450929128
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1939639286
Short name T1606
Test name
Test status
Simulation time 155610791 ps
CPU time 0.78 seconds
Started Jul 03 04:56:20 PM PDT 24
Finished Jul 03 04:56:21 PM PDT 24
Peak memory 206036 kb
Host smart-93235060-61d7-4e7a-9ad7-ac5d57f93baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19396
39286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1939639286
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1732538586
Short name T97
Test name
Test status
Simulation time 232652837 ps
CPU time 0.86 seconds
Started Jul 03 04:56:19 PM PDT 24
Finished Jul 03 04:56:20 PM PDT 24
Peak memory 206088 kb
Host smart-235d533a-a4e9-421a-92e3-350495cf0a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17325
38586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1732538586
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3356866409
Short name T897
Test name
Test status
Simulation time 153564224 ps
CPU time 0.79 seconds
Started Jul 03 04:56:20 PM PDT 24
Finished Jul 03 04:56:21 PM PDT 24
Peak memory 206068 kb
Host smart-faf5f118-dcec-40d5-9ada-7e0d39359239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33568
66409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3356866409
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.4244211017
Short name T1886
Test name
Test status
Simulation time 185922117 ps
CPU time 0.88 seconds
Started Jul 03 04:56:10 PM PDT 24
Finished Jul 03 04:56:11 PM PDT 24
Peak memory 206132 kb
Host smart-09fdbb58-7eb1-4e79-b53a-1183b27a72b0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4244211017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.4244211017
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2556297631
Short name T742
Test name
Test status
Simulation time 144952129 ps
CPU time 0.74 seconds
Started Jul 03 04:56:21 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206092 kb
Host smart-8740ee70-ee0e-4af7-aba8-ea319cfbf826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25562
97631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2556297631
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.209528814
Short name T773
Test name
Test status
Simulation time 45847565 ps
CPU time 0.66 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:26 PM PDT 24
Peak memory 206120 kb
Host smart-0762ddcd-45a1-422c-bb8e-552d5223dbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20952
8814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.209528814
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.4170767777
Short name T2200
Test name
Test status
Simulation time 21211220891 ps
CPU time 45.3 seconds
Started Jul 03 04:56:11 PM PDT 24
Finished Jul 03 04:56:57 PM PDT 24
Peak memory 206368 kb
Host smart-55e1d478-1e2d-453f-83d9-ccae5bff3458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41707
67777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.4170767777
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.531055900
Short name T56
Test name
Test status
Simulation time 161894570 ps
CPU time 0.79 seconds
Started Jul 03 04:56:08 PM PDT 24
Finished Jul 03 04:56:09 PM PDT 24
Peak memory 206104 kb
Host smart-56d901ec-f2b5-4a5a-b3e7-0da2eface970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53105
5900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.531055900
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.4277560404
Short name T2638
Test name
Test status
Simulation time 237466792 ps
CPU time 0.85 seconds
Started Jul 03 04:56:08 PM PDT 24
Finished Jul 03 04:56:09 PM PDT 24
Peak memory 206084 kb
Host smart-6541c8a7-49cb-4c16-bb92-d81af9738772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42775
60404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.4277560404
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.3164559157
Short name T387
Test name
Test status
Simulation time 217624675 ps
CPU time 0.85 seconds
Started Jul 03 04:56:04 PM PDT 24
Finished Jul 03 04:56:05 PM PDT 24
Peak memory 206116 kb
Host smart-e94f75e4-4ca0-4233-9509-053810afb448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645
59157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.3164559157
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2390508826
Short name T1725
Test name
Test status
Simulation time 180304566 ps
CPU time 0.84 seconds
Started Jul 03 04:56:16 PM PDT 24
Finished Jul 03 04:56:17 PM PDT 24
Peak memory 206096 kb
Host smart-19ff2dc8-f973-41e7-9e62-f94c45c9e298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23905
08826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2390508826
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.1450113570
Short name T1280
Test name
Test status
Simulation time 151026081 ps
CPU time 0.82 seconds
Started Jul 03 04:56:02 PM PDT 24
Finished Jul 03 04:56:04 PM PDT 24
Peak memory 206084 kb
Host smart-bb22dadc-65e6-4431-8823-7c3758811284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14501
13570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.1450113570
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.725319258
Short name T423
Test name
Test status
Simulation time 158997102 ps
CPU time 0.86 seconds
Started Jul 03 04:56:01 PM PDT 24
Finished Jul 03 04:56:03 PM PDT 24
Peak memory 206128 kb
Host smart-37cac8c1-417f-4ba1-9372-b4805b5442ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72531
9258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.725319258
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.771317801
Short name T1844
Test name
Test status
Simulation time 209941620 ps
CPU time 0.83 seconds
Started Jul 03 04:56:03 PM PDT 24
Finished Jul 03 04:56:04 PM PDT 24
Peak memory 206120 kb
Host smart-e70f1840-8d0f-4956-8165-6f19e349c4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77131
7801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.771317801
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1144674215
Short name T1388
Test name
Test status
Simulation time 275046960 ps
CPU time 0.94 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:56:25 PM PDT 24
Peak memory 206104 kb
Host smart-717720f4-89bb-415d-87c9-190fed47009b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11446
74215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1144674215
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.462370655
Short name T1694
Test name
Test status
Simulation time 6612539507 ps
CPU time 63.28 seconds
Started Jul 03 04:56:07 PM PDT 24
Finished Jul 03 04:57:11 PM PDT 24
Peak memory 206428 kb
Host smart-43f08f42-4888-4ed0-b076-0b5accee0e46
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=462370655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.462370655
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.4156946862
Short name T1909
Test name
Test status
Simulation time 161383752 ps
CPU time 0.85 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:24 PM PDT 24
Peak memory 206136 kb
Host smart-6759c42f-97f4-4fff-bb23-2be3d7dc1f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41569
46862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.4156946862
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1786949962
Short name T2440
Test name
Test status
Simulation time 145237382 ps
CPU time 0.82 seconds
Started Jul 03 04:56:06 PM PDT 24
Finished Jul 03 04:56:07 PM PDT 24
Peak memory 205960 kb
Host smart-96d0a4fb-8c2f-4158-b555-f0d31532a827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17869
49962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1786949962
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.3038973426
Short name T1071
Test name
Test status
Simulation time 612779703 ps
CPU time 1.53 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206132 kb
Host smart-cecbd3be-9ff3-40fb-8534-a7d9837860d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30389
73426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.3038973426
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1366133026
Short name T1991
Test name
Test status
Simulation time 4465997836 ps
CPU time 42.47 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:57:06 PM PDT 24
Peak memory 206436 kb
Host smart-71512863-1f05-4165-99e8-0e26d43c7a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13661
33026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1366133026
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.422039787
Short name T1890
Test name
Test status
Simulation time 57355890 ps
CPU time 0.72 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206136 kb
Host smart-d7cbdbf7-a754-4d15-b150-8f072c7a6db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=422039787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.422039787
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.275810407
Short name T693
Test name
Test status
Simulation time 4134920717 ps
CPU time 5.49 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:33 PM PDT 24
Peak memory 206304 kb
Host smart-28c0f8ba-4348-48d0-a9a7-f190d57bfc95
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=275810407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.275810407
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3886737655
Short name T1506
Test name
Test status
Simulation time 13323638814 ps
CPU time 11.51 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:34 PM PDT 24
Peak memory 206392 kb
Host smart-d02b63d2-44d4-4391-bc4d-f5d5026c6fe5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3886737655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3886737655
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3646082651
Short name T1949
Test name
Test status
Simulation time 23393717771 ps
CPU time 22.74 seconds
Started Jul 03 04:56:08 PM PDT 24
Finished Jul 03 04:56:31 PM PDT 24
Peak memory 206412 kb
Host smart-ed1a377c-ab59-45f0-b2cf-2a955892d415
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3646082651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3646082651
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2971567848
Short name T660
Test name
Test status
Simulation time 175116948 ps
CPU time 0.83 seconds
Started Jul 03 04:56:06 PM PDT 24
Finished Jul 03 04:56:07 PM PDT 24
Peak memory 206080 kb
Host smart-3fe127aa-31aa-4c01-b8b8-a98d558be743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29715
67848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2971567848
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.2730451528
Short name T1233
Test name
Test status
Simulation time 139440970 ps
CPU time 0.75 seconds
Started Jul 03 04:56:09 PM PDT 24
Finished Jul 03 04:56:10 PM PDT 24
Peak memory 206076 kb
Host smart-14a5794a-39a7-45d9-878b-06b73d78dc53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27304
51528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.2730451528
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.1314920949
Short name T172
Test name
Test status
Simulation time 260075432 ps
CPU time 1.06 seconds
Started Jul 03 04:56:12 PM PDT 24
Finished Jul 03 04:56:14 PM PDT 24
Peak memory 206136 kb
Host smart-08bbfdca-1411-4f13-bb97-437f91e1eaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13149
20949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.1314920949
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.956475361
Short name T1216
Test name
Test status
Simulation time 381998894 ps
CPU time 1.1 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:56:25 PM PDT 24
Peak memory 206108 kb
Host smart-d6aac16e-bcbc-409e-84e9-a0e4db13f449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95647
5361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.956475361
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.3008187034
Short name T2
Test name
Test status
Simulation time 483026066 ps
CPU time 1.42 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:28 PM PDT 24
Peak memory 206112 kb
Host smart-1b59ef7d-9886-450d-9040-312ccf6a3804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30081
87034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3008187034
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.732171926
Short name T2513
Test name
Test status
Simulation time 137942440 ps
CPU time 0.73 seconds
Started Jul 03 04:56:24 PM PDT 24
Finished Jul 03 04:56:26 PM PDT 24
Peak memory 206144 kb
Host smart-a59e847d-af33-46c4-8a3f-3f3e4e73440d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73217
1926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.732171926
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1303736566
Short name T614
Test name
Test status
Simulation time 59502723 ps
CPU time 0.67 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:24 PM PDT 24
Peak memory 206108 kb
Host smart-1910c468-3a94-4a88-b2a8-13906afae096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13037
36566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1303736566
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.1649075812
Short name T2489
Test name
Test status
Simulation time 1132639598 ps
CPU time 2.5 seconds
Started Jul 03 04:56:05 PM PDT 24
Finished Jul 03 04:56:08 PM PDT 24
Peak memory 206364 kb
Host smart-2c409a10-b841-4208-8ff7-d02373debc09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16490
75812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1649075812
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2749700555
Short name T2201
Test name
Test status
Simulation time 189008441 ps
CPU time 1.49 seconds
Started Jul 03 04:56:09 PM PDT 24
Finished Jul 03 04:56:11 PM PDT 24
Peak memory 206364 kb
Host smart-4dc5f9a0-08e4-4814-b75f-1b696ce8ede0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27497
00555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2749700555
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3869931461
Short name T2035
Test name
Test status
Simulation time 177423823 ps
CPU time 0.87 seconds
Started Jul 03 04:56:06 PM PDT 24
Finished Jul 03 04:56:07 PM PDT 24
Peak memory 206084 kb
Host smart-51fdbc57-afc5-403a-9306-399660a1823b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38699
31461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3869931461
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3412959423
Short name T2709
Test name
Test status
Simulation time 137008575 ps
CPU time 0.76 seconds
Started Jul 03 04:56:04 PM PDT 24
Finished Jul 03 04:56:06 PM PDT 24
Peak memory 206124 kb
Host smart-2d304db4-e5ad-4372-a71e-7d9141b4616a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34129
59423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3412959423
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1849579536
Short name T1650
Test name
Test status
Simulation time 240539431 ps
CPU time 0.88 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:23 PM PDT 24
Peak memory 206144 kb
Host smart-dce188ea-c699-4d6a-921d-920168aa56b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18495
79536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1849579536
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.736807698
Short name T1180
Test name
Test status
Simulation time 7648827438 ps
CPU time 71.13 seconds
Started Jul 03 04:56:04 PM PDT 24
Finished Jul 03 04:57:16 PM PDT 24
Peak memory 206452 kb
Host smart-23a55c29-7ff4-409f-ad05-169cb2a228bd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=736807698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.736807698
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1191567267
Short name T1971
Test name
Test status
Simulation time 182953760 ps
CPU time 0.85 seconds
Started Jul 03 04:56:07 PM PDT 24
Finished Jul 03 04:56:08 PM PDT 24
Peak memory 206092 kb
Host smart-a42cfcf1-6e33-4e69-800e-433768746d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11915
67267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1191567267
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.536205075
Short name T1665
Test name
Test status
Simulation time 23329662029 ps
CPU time 24.31 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:50 PM PDT 24
Peak memory 206164 kb
Host smart-1bd875c1-ef60-4b0d-abf5-2a07ac52fa68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53620
5075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.536205075
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2244972327
Short name T544
Test name
Test status
Simulation time 3316931787 ps
CPU time 3.91 seconds
Started Jul 03 04:56:04 PM PDT 24
Finished Jul 03 04:56:09 PM PDT 24
Peak memory 206196 kb
Host smart-cd830391-e856-4b33-9f4c-dba3ce7e1fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22449
72327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2244972327
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.557602611
Short name T1723
Test name
Test status
Simulation time 9428563121 ps
CPU time 254.41 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 05:00:38 PM PDT 24
Peak memory 206448 kb
Host smart-fc9637db-843e-4ee0-99a3-6c14e0a9a2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55760
2611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.557602611
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.1391530160
Short name T1511
Test name
Test status
Simulation time 5083094300 ps
CPU time 46.36 seconds
Started Jul 03 04:56:07 PM PDT 24
Finished Jul 03 04:56:54 PM PDT 24
Peak memory 206424 kb
Host smart-c33921c1-4d64-454b-9af4-3090747ff3c4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1391530160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.1391530160
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.2638871193
Short name T1901
Test name
Test status
Simulation time 260436237 ps
CPU time 0.9 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:56:24 PM PDT 24
Peak memory 206128 kb
Host smart-2e00653e-4475-48c9-a8a4-ad3577121108
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2638871193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.2638871193
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1153284287
Short name T2082
Test name
Test status
Simulation time 197393384 ps
CPU time 0.88 seconds
Started Jul 03 04:56:11 PM PDT 24
Finished Jul 03 04:56:12 PM PDT 24
Peak memory 206076 kb
Host smart-86c8c196-4570-4bf3-8280-aae4666e3229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11532
84287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1153284287
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1361014357
Short name T3
Test name
Test status
Simulation time 6398353064 ps
CPU time 169.19 seconds
Started Jul 03 04:56:13 PM PDT 24
Finished Jul 03 04:59:02 PM PDT 24
Peak memory 206328 kb
Host smart-c53daeed-41ac-456f-9f51-4ec7be4a24ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13610
14357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1361014357
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1463595372
Short name T2026
Test name
Test status
Simulation time 6184959918 ps
CPU time 168.89 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:59:17 PM PDT 24
Peak memory 206336 kb
Host smart-7e5afd17-3377-4ce9-9072-25c49a1adf32
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1463595372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1463595372
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.892817191
Short name T2314
Test name
Test status
Simulation time 165239591 ps
CPU time 0.78 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:27 PM PDT 24
Peak memory 206128 kb
Host smart-f7d50189-a8cf-49b0-bca3-efd2843c5d12
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=892817191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.892817191
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.676201086
Short name T605
Test name
Test status
Simulation time 234988289 ps
CPU time 0.84 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:27 PM PDT 24
Peak memory 206088 kb
Host smart-72c26eb3-39a9-460d-b3e5-d0f3ab1eb382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67620
1086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.676201086
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.200053858
Short name T2220
Test name
Test status
Simulation time 191764692 ps
CPU time 0.84 seconds
Started Jul 03 04:56:20 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206088 kb
Host smart-41726a61-bfc9-4b76-ba6a-8ee4b6e28d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20005
3858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.200053858
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.330202519
Short name T879
Test name
Test status
Simulation time 183331808 ps
CPU time 0.89 seconds
Started Jul 03 04:56:10 PM PDT 24
Finished Jul 03 04:56:11 PM PDT 24
Peak memory 206080 kb
Host smart-18419d65-3569-4d50-bfdd-f0dcaa4fe3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33020
2519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.330202519
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3426414906
Short name T624
Test name
Test status
Simulation time 172122176 ps
CPU time 0.85 seconds
Started Jul 03 04:56:11 PM PDT 24
Finished Jul 03 04:56:12 PM PDT 24
Peak memory 206128 kb
Host smart-e002e142-93b8-47ef-aefd-7281357c99da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34264
14906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3426414906
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1145762104
Short name T865
Test name
Test status
Simulation time 174225763 ps
CPU time 0.86 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:56:25 PM PDT 24
Peak memory 206116 kb
Host smart-1a687a45-845e-401f-9f0d-25142da82c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11457
62104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1145762104
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2379130543
Short name T180
Test name
Test status
Simulation time 166439706 ps
CPU time 0.8 seconds
Started Jul 03 04:56:06 PM PDT 24
Finished Jul 03 04:56:07 PM PDT 24
Peak memory 206112 kb
Host smart-186cf37c-2310-42a6-8ddf-6cfd597c2d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23791
30543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2379130543
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.491286513
Short name T665
Test name
Test status
Simulation time 241307774 ps
CPU time 1.03 seconds
Started Jul 03 04:56:21 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206132 kb
Host smart-90d70bcb-04e9-4196-918b-97d1f1764489
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=491286513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.491286513
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2500815998
Short name T824
Test name
Test status
Simulation time 161498593 ps
CPU time 0.8 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:27 PM PDT 24
Peak memory 206116 kb
Host smart-b1b29bc9-c430-4445-ae7d-c80d5e6288a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25008
15998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2500815998
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.4187003794
Short name T2573
Test name
Test status
Simulation time 41209120 ps
CPU time 0.65 seconds
Started Jul 03 04:56:32 PM PDT 24
Finished Jul 03 04:56:33 PM PDT 24
Peak memory 206032 kb
Host smart-b9632cc0-9c4d-435d-a6a6-99da3669c907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41870
03794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.4187003794
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3791824244
Short name T733
Test name
Test status
Simulation time 8229550503 ps
CPU time 18.73 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:47 PM PDT 24
Peak memory 206332 kb
Host smart-862d19a7-17a5-4f39-b767-30f6ddb713bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37918
24244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3791824244
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1587178587
Short name T1705
Test name
Test status
Simulation time 152457704 ps
CPU time 0.75 seconds
Started Jul 03 04:56:10 PM PDT 24
Finished Jul 03 04:56:12 PM PDT 24
Peak memory 206128 kb
Host smart-638c2265-7eff-40c8-b9bd-2342141eea8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15871
78587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1587178587
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1847299947
Short name T840
Test name
Test status
Simulation time 255684302 ps
CPU time 0.92 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:56:24 PM PDT 24
Peak memory 206132 kb
Host smart-d4449a6d-3b95-4dd1-a106-79136ecc1cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18472
99947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1847299947
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.949870143
Short name T382
Test name
Test status
Simulation time 247737365 ps
CPU time 0.97 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:56:25 PM PDT 24
Peak memory 206132 kb
Host smart-b3c1ae40-e237-4d18-ab70-ecbac1947175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94987
0143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.949870143
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.1138053213
Short name T2549
Test name
Test status
Simulation time 148398629 ps
CPU time 0.75 seconds
Started Jul 03 04:56:14 PM PDT 24
Finished Jul 03 04:56:15 PM PDT 24
Peak memory 206108 kb
Host smart-98cc85a5-6b85-4d8f-86be-6d1bdc599892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11380
53213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.1138053213
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3586029495
Short name T806
Test name
Test status
Simulation time 143664624 ps
CPU time 0.83 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206116 kb
Host smart-d39cfb7f-863a-473b-8ba0-e88129af3a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35860
29495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3586029495
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2564828300
Short name T164
Test name
Test status
Simulation time 161756138 ps
CPU time 0.77 seconds
Started Jul 03 04:56:08 PM PDT 24
Finished Jul 03 04:56:09 PM PDT 24
Peak memory 206128 kb
Host smart-f153a0a1-0d96-44f4-8053-66b0e24c1b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25648
28300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2564828300
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2436009441
Short name T570
Test name
Test status
Simulation time 155633653 ps
CPU time 0.81 seconds
Started Jul 03 04:56:14 PM PDT 24
Finished Jul 03 04:56:15 PM PDT 24
Peak memory 206136 kb
Host smart-bce6a438-f170-4771-a21c-9f9738fec338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24360
09441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2436009441
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.358737318
Short name T554
Test name
Test status
Simulation time 197398517 ps
CPU time 0.9 seconds
Started Jul 03 04:56:10 PM PDT 24
Finished Jul 03 04:56:11 PM PDT 24
Peak memory 206144 kb
Host smart-5cd6a779-da24-4ee1-9031-9436b6ab4661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35873
7318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.358737318
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.3620719536
Short name T2653
Test name
Test status
Simulation time 5445366059 ps
CPU time 37.92 seconds
Started Jul 03 04:56:15 PM PDT 24
Finished Jul 03 04:56:53 PM PDT 24
Peak memory 206424 kb
Host smart-52d09fe5-abcb-4976-918a-814793cba175
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3620719536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.3620719536
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.781539953
Short name T1569
Test name
Test status
Simulation time 170374086 ps
CPU time 0.83 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:56:24 PM PDT 24
Peak memory 206088 kb
Host smart-a870a71a-9b8a-4bb9-8d17-663c05e29ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78153
9953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.781539953
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.940011971
Short name T584
Test name
Test status
Simulation time 151459108 ps
CPU time 0.76 seconds
Started Jul 03 04:56:09 PM PDT 24
Finished Jul 03 04:56:11 PM PDT 24
Peak memory 206108 kb
Host smart-09866252-db81-4186-8cba-737dad4c9ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94001
1971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.940011971
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.1855826239
Short name T1629
Test name
Test status
Simulation time 423191779 ps
CPU time 1.29 seconds
Started Jul 03 04:56:13 PM PDT 24
Finished Jul 03 04:56:15 PM PDT 24
Peak memory 206052 kb
Host smart-dd977d5f-be34-45f9-ac9b-30f3ae1c1b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18558
26239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.1855826239
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2084845899
Short name T597
Test name
Test status
Simulation time 7268646502 ps
CPU time 49.94 seconds
Started Jul 03 04:56:12 PM PDT 24
Finished Jul 03 04:57:02 PM PDT 24
Peak memory 206304 kb
Host smart-7135fcb2-35dc-431b-9e9a-59e271d5dc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20848
45899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2084845899
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1842487369
Short name T1409
Test name
Test status
Simulation time 50122933 ps
CPU time 0.67 seconds
Started Jul 03 04:56:12 PM PDT 24
Finished Jul 03 04:56:13 PM PDT 24
Peak memory 206152 kb
Host smart-68c4336c-24fe-4510-9544-378bc21c4459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1842487369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1842487369
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.75293692
Short name T2132
Test name
Test status
Simulation time 3700712901 ps
CPU time 5.06 seconds
Started Jul 03 04:56:09 PM PDT 24
Finished Jul 03 04:56:15 PM PDT 24
Peak memory 206416 kb
Host smart-d71fe49d-03e1-41fa-a1a7-32deb64840cc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=75293692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.75293692
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.3207776950
Short name T2454
Test name
Test status
Simulation time 13434786684 ps
CPU time 12.77 seconds
Started Jul 03 04:56:29 PM PDT 24
Finished Jul 03 04:56:43 PM PDT 24
Peak memory 206356 kb
Host smart-35f9a0ef-1992-42d3-b7a2-40215a7791ae
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3207776950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.3207776950
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3596908343
Short name T10
Test name
Test status
Simulation time 23425370964 ps
CPU time 22.47 seconds
Started Jul 03 04:56:12 PM PDT 24
Finished Jul 03 04:56:35 PM PDT 24
Peak memory 206404 kb
Host smart-210f125c-e6b1-4b07-b297-5ed4133fb196
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3596908343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.3596908343
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2879401208
Short name T2295
Test name
Test status
Simulation time 150083086 ps
CPU time 0.82 seconds
Started Jul 03 04:56:12 PM PDT 24
Finished Jul 03 04:56:13 PM PDT 24
Peak memory 206108 kb
Host smart-8b49c0a1-b3ec-4739-a9a4-5556af9e2e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28794
01208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2879401208
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.3965809847
Short name T2122
Test name
Test status
Simulation time 138895289 ps
CPU time 0.76 seconds
Started Jul 03 04:56:12 PM PDT 24
Finished Jul 03 04:56:13 PM PDT 24
Peak memory 206072 kb
Host smart-946c350f-f83f-4892-a515-121113b1e7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
09847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.3965809847
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2308160555
Short name T531
Test name
Test status
Simulation time 366304255 ps
CPU time 1.21 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206036 kb
Host smart-056bfa3a-bfa7-480c-a857-105be50474a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23081
60555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2308160555
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3466050750
Short name T2278
Test name
Test status
Simulation time 624291628 ps
CPU time 1.62 seconds
Started Jul 03 04:56:10 PM PDT 24
Finished Jul 03 04:56:12 PM PDT 24
Peak memory 206092 kb
Host smart-14d1643f-afa0-41dc-9025-ea94b8aba2e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34660
50750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3466050750
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3163088976
Short name T2123
Test name
Test status
Simulation time 21556223216 ps
CPU time 47.76 seconds
Started Jul 03 04:56:09 PM PDT 24
Finished Jul 03 04:56:57 PM PDT 24
Peak memory 206428 kb
Host smart-d719032e-b4ee-4f93-b754-38c1b3937baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31630
88976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3163088976
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.3583232699
Short name T2059
Test name
Test status
Simulation time 462825320 ps
CPU time 1.36 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:27 PM PDT 24
Peak memory 206096 kb
Host smart-fbd8d05d-9aab-46f7-94f3-6b3099dd8e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35832
32699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.3583232699
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.920175038
Short name T712
Test name
Test status
Simulation time 152619344 ps
CPU time 0.82 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206028 kb
Host smart-377747df-c8ea-40f5-915b-ff64fcfb3271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92017
5038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.920175038
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3289573546
Short name T1822
Test name
Test status
Simulation time 33020984 ps
CPU time 0.65 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:23 PM PDT 24
Peak memory 206124 kb
Host smart-f76bea3c-19b4-44b4-bd32-f1bd23f3fba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32895
73546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3289573546
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.517162370
Short name T595
Test name
Test status
Simulation time 872359297 ps
CPU time 2.18 seconds
Started Jul 03 04:56:15 PM PDT 24
Finished Jul 03 04:56:17 PM PDT 24
Peak memory 206324 kb
Host smart-dab2e2c9-45ab-47a1-b3a0-f86349513c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51716
2370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.517162370
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.106326318
Short name T649
Test name
Test status
Simulation time 296385270 ps
CPU time 2.05 seconds
Started Jul 03 04:56:08 PM PDT 24
Finished Jul 03 04:56:10 PM PDT 24
Peak memory 206152 kb
Host smart-3e925918-bcc9-4196-8b04-1f92c557a726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10632
6318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.106326318
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2978043812
Short name T745
Test name
Test status
Simulation time 173251092 ps
CPU time 0.82 seconds
Started Jul 03 04:56:11 PM PDT 24
Finished Jul 03 04:56:13 PM PDT 24
Peak memory 206124 kb
Host smart-b9df174e-6860-4bd4-806a-29079f434bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29780
43812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2978043812
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.537933554
Short name T122
Test name
Test status
Simulation time 144146541 ps
CPU time 0.73 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:23 PM PDT 24
Peak memory 206380 kb
Host smart-15e6064c-e2d4-4b7f-b306-5695c471222b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53793
3554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.537933554
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.770566387
Short name T395
Test name
Test status
Simulation time 221238858 ps
CPU time 0.89 seconds
Started Jul 03 04:56:42 PM PDT 24
Finished Jul 03 04:56:43 PM PDT 24
Peak memory 206108 kb
Host smart-b98ae207-5d36-42cc-9911-5734c90b6285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77056
6387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.770566387
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.4009781912
Short name T1162
Test name
Test status
Simulation time 6650120015 ps
CPU time 177.25 seconds
Started Jul 03 04:56:17 PM PDT 24
Finished Jul 03 04:59:15 PM PDT 24
Peak memory 206464 kb
Host smart-ecaeb572-ffa9-4a1a-8465-4bef2e0d49f0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4009781912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.4009781912
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.2495693302
Short name T2187
Test name
Test status
Simulation time 276526554 ps
CPU time 0.96 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:26 PM PDT 24
Peak memory 206148 kb
Host smart-6da9b537-52ae-4c38-b1ab-b6be73bda3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24956
93302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.2495693302
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1292597484
Short name T1574
Test name
Test status
Simulation time 23348230698 ps
CPU time 22.91 seconds
Started Jul 03 04:56:12 PM PDT 24
Finished Jul 03 04:56:35 PM PDT 24
Peak memory 206108 kb
Host smart-3d2f7b24-5c41-4c78-93de-4fad22897148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12925
97484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1292597484
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2055903370
Short name T341
Test name
Test status
Simulation time 3308267275 ps
CPU time 4.13 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206128 kb
Host smart-1d038f3c-7d85-421f-9fc6-13453256a98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20559
03370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2055903370
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1486030464
Short name T2070
Test name
Test status
Simulation time 7710341645 ps
CPU time 53.26 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:57:17 PM PDT 24
Peak memory 206448 kb
Host smart-4a9ebbdc-2053-490b-998f-e166e8a4f807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14860
30464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1486030464
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3345698898
Short name T559
Test name
Test status
Simulation time 5855837019 ps
CPU time 49.89 seconds
Started Jul 03 04:56:24 PM PDT 24
Finished Jul 03 04:57:15 PM PDT 24
Peak memory 206248 kb
Host smart-58669c98-aace-4c77-a682-5ffbb61eebac
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3345698898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3345698898
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1677801792
Short name T2422
Test name
Test status
Simulation time 249190032 ps
CPU time 0.97 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:23 PM PDT 24
Peak memory 206000 kb
Host smart-40955f04-a378-4b4f-b5a3-d634b0626c60
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1677801792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1677801792
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.819215104
Short name T1275
Test name
Test status
Simulation time 230933820 ps
CPU time 0.89 seconds
Started Jul 03 04:56:13 PM PDT 24
Finished Jul 03 04:56:14 PM PDT 24
Peak memory 206128 kb
Host smart-240ef48e-682e-4c65-9da1-a87d1f1425dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81921
5104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.819215104
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3167643586
Short name T967
Test name
Test status
Simulation time 2936906948 ps
CPU time 22.95 seconds
Started Jul 03 04:56:13 PM PDT 24
Finished Jul 03 04:56:37 PM PDT 24
Peak memory 206372 kb
Host smart-47e5f03c-fc57-4dab-9e32-dfc532361a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31676
43586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3167643586
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1896083801
Short name T1530
Test name
Test status
Simulation time 4742017757 ps
CPU time 128.21 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:58:30 PM PDT 24
Peak memory 206340 kb
Host smart-70cfff3e-e26c-483b-ab2b-859bff0e64ca
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1896083801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1896083801
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1109482357
Short name T1584
Test name
Test status
Simulation time 172898190 ps
CPU time 0.83 seconds
Started Jul 03 04:56:20 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206088 kb
Host smart-f321e337-e9a0-4651-b7ce-2fcc302cfdc5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1109482357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1109482357
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2945364574
Short name T2013
Test name
Test status
Simulation time 144815950 ps
CPU time 0.77 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:56:23 PM PDT 24
Peak memory 206388 kb
Host smart-34c5bc97-7ccf-4b3b-ac32-95982a7eecd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29453
64574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2945364574
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.807684243
Short name T1671
Test name
Test status
Simulation time 225888834 ps
CPU time 0.85 seconds
Started Jul 03 04:56:19 PM PDT 24
Finished Jul 03 04:56:20 PM PDT 24
Peak memory 206088 kb
Host smart-fc39c0f0-114e-49d6-a65c-fe43f656b34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80768
4243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.807684243
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3395118441
Short name T500
Test name
Test status
Simulation time 154178932 ps
CPU time 0.75 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:56:25 PM PDT 24
Peak memory 206124 kb
Host smart-d3364f7b-6041-4e58-ac2d-05af0bcbde58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33951
18441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3395118441
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1590522449
Short name T2601
Test name
Test status
Simulation time 163827418 ps
CPU time 0.79 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:28 PM PDT 24
Peak memory 206128 kb
Host smart-752a025d-9968-4660-af0b-11e98b6daf51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15905
22449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1590522449
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2473837031
Short name T2444
Test name
Test status
Simulation time 209319065 ps
CPU time 0.83 seconds
Started Jul 03 04:56:14 PM PDT 24
Finished Jul 03 04:56:15 PM PDT 24
Peak memory 206048 kb
Host smart-23063e2c-24a6-4cce-a608-9866686615ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24738
37031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2473837031
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2055644246
Short name T2090
Test name
Test status
Simulation time 161286139 ps
CPU time 0.84 seconds
Started Jul 03 04:56:17 PM PDT 24
Finished Jul 03 04:56:19 PM PDT 24
Peak memory 206028 kb
Host smart-1b638683-181c-4ea7-b870-cc7f91a99376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20556
44246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2055644246
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3430472369
Short name T903
Test name
Test status
Simulation time 244347865 ps
CPU time 1 seconds
Started Jul 03 04:56:15 PM PDT 24
Finished Jul 03 04:56:16 PM PDT 24
Peak memory 206136 kb
Host smart-8aba0bbf-aedd-4943-86a8-3c4774892681
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3430472369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3430472369
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2694257
Short name T2439
Test name
Test status
Simulation time 152516383 ps
CPU time 0.83 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206088 kb
Host smart-d6933d24-e0f6-4002-9a7f-6175bccd0fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26942
57 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2694257
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.410341746
Short name T1031
Test name
Test status
Simulation time 96164629 ps
CPU time 0.69 seconds
Started Jul 03 04:56:17 PM PDT 24
Finished Jul 03 04:56:18 PM PDT 24
Peak memory 206104 kb
Host smart-7c6550fb-468d-4caf-971a-5b1d44b8b54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41034
1746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.410341746
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.214243500
Short name T296
Test name
Test status
Simulation time 7708954946 ps
CPU time 17.36 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:43 PM PDT 24
Peak memory 206476 kb
Host smart-70e01ac8-b787-4d3d-9e4d-d1194821cb3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21424
3500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.214243500
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.240902083
Short name T2251
Test name
Test status
Simulation time 172545241 ps
CPU time 0.84 seconds
Started Jul 03 04:56:13 PM PDT 24
Finished Jul 03 04:56:14 PM PDT 24
Peak memory 206108 kb
Host smart-1850d277-efc7-4cf4-a797-13dbae2428d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24090
2083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.240902083
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2158385650
Short name T487
Test name
Test status
Simulation time 280798020 ps
CPU time 0.98 seconds
Started Jul 03 04:56:15 PM PDT 24
Finished Jul 03 04:56:17 PM PDT 24
Peak memory 206128 kb
Host smart-0ff2a03f-db27-4ae4-9d15-c8acc34bdf31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21583
85650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2158385650
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.920842396
Short name T1219
Test name
Test status
Simulation time 202761167 ps
CPU time 0.87 seconds
Started Jul 03 04:56:17 PM PDT 24
Finished Jul 03 04:56:18 PM PDT 24
Peak memory 206116 kb
Host smart-7968df7d-9379-41ab-8788-086b26bf67cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92084
2396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.920842396
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.638988249
Short name T2395
Test name
Test status
Simulation time 156966304 ps
CPU time 0.79 seconds
Started Jul 03 04:56:15 PM PDT 24
Finished Jul 03 04:56:16 PM PDT 24
Peak memory 206124 kb
Host smart-923cae8a-1337-429e-99ad-7c43a523e033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63898
8249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.638988249
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.2338622715
Short name T2532
Test name
Test status
Simulation time 156026962 ps
CPU time 0.75 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:28 PM PDT 24
Peak memory 206132 kb
Host smart-56c3fe33-8b98-47b7-9c90-c090be6cbc45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23386
22715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.2338622715
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2914457463
Short name T775
Test name
Test status
Simulation time 156074434 ps
CPU time 0.8 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:56:25 PM PDT 24
Peak memory 206116 kb
Host smart-314917a1-3ded-4603-a280-23f0aee2461b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29144
57463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2914457463
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1403401024
Short name T236
Test name
Test status
Simulation time 229902067 ps
CPU time 0.82 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:56:55 PM PDT 24
Peak memory 206092 kb
Host smart-9efe963a-7288-4f77-aac2-b0c05e2ee97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14034
01024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1403401024
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1314119722
Short name T1736
Test name
Test status
Simulation time 219927859 ps
CPU time 0.93 seconds
Started Jul 03 04:56:24 PM PDT 24
Finished Jul 03 04:56:26 PM PDT 24
Peak memory 206108 kb
Host smart-92e03f1b-793a-45a0-bc30-afbb09f25c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13141
19722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1314119722
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.2122226310
Short name T1786
Test name
Test status
Simulation time 4958617710 ps
CPU time 136.66 seconds
Started Jul 03 04:56:22 PM PDT 24
Finished Jul 03 04:58:39 PM PDT 24
Peak memory 206372 kb
Host smart-eedac354-944c-4e31-aaa1-2e0bba334748
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2122226310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.2122226310
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3953105728
Short name T2045
Test name
Test status
Simulation time 196492616 ps
CPU time 0.88 seconds
Started Jul 03 04:56:17 PM PDT 24
Finished Jul 03 04:56:19 PM PDT 24
Peak memory 206120 kb
Host smart-e899c13a-2280-4b79-b83c-b3e272ffefd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39531
05728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3953105728
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1458038517
Short name T2055
Test name
Test status
Simulation time 154031636 ps
CPU time 0.79 seconds
Started Jul 03 04:56:21 PM PDT 24
Finished Jul 03 04:56:22 PM PDT 24
Peak memory 206092 kb
Host smart-e97e9056-15a3-48ad-ba0b-61aee80a0435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14580
38517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1458038517
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.3489939757
Short name T655
Test name
Test status
Simulation time 768197942 ps
CPU time 1.73 seconds
Started Jul 03 04:56:18 PM PDT 24
Finished Jul 03 04:56:20 PM PDT 24
Peak memory 206308 kb
Host smart-eda399d4-df64-4b00-8d36-ee4d897a33d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34899
39757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.3489939757
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.1459992951
Short name T536
Test name
Test status
Simulation time 7770518184 ps
CPU time 208 seconds
Started Jul 03 04:56:32 PM PDT 24
Finished Jul 03 05:00:00 PM PDT 24
Peak memory 206400 kb
Host smart-3e1c40fd-0237-4ca9-aa0e-54d435bb0291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14599
92951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.1459992951
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.2136261118
Short name T1007
Test name
Test status
Simulation time 47749958 ps
CPU time 0.66 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:28 PM PDT 24
Peak memory 206192 kb
Host smart-099173e3-3f19-4a8e-b732-7dc9e3caf365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2136261118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.2136261118
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.974752738
Short name T2590
Test name
Test status
Simulation time 4319977127 ps
CPU time 5.54 seconds
Started Jul 03 04:56:16 PM PDT 24
Finished Jul 03 04:56:23 PM PDT 24
Peak memory 206432 kb
Host smart-4dcc01cd-d081-47cb-a84e-a821afd9dc45
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=974752738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.974752738
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1776843022
Short name T523
Test name
Test status
Simulation time 13344117003 ps
CPU time 14.42 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:41 PM PDT 24
Peak memory 206172 kb
Host smart-17d5272d-f48e-45a1-9ab7-5a879084588b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1776843022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1776843022
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.387689992
Short name T1990
Test name
Test status
Simulation time 23401531917 ps
CPU time 25.35 seconds
Started Jul 03 04:56:24 PM PDT 24
Finished Jul 03 04:56:50 PM PDT 24
Peak memory 206400 kb
Host smart-8539e041-28b9-463d-82c8-4e50970ba0ef
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=387689992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.387689992
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1980234475
Short name T1132
Test name
Test status
Simulation time 173617667 ps
CPU time 0.88 seconds
Started Jul 03 04:56:16 PM PDT 24
Finished Jul 03 04:56:17 PM PDT 24
Peak memory 206128 kb
Host smart-8d4802bd-cdf9-4770-a285-058316bd8f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19802
34475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1980234475
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3577124338
Short name T2643
Test name
Test status
Simulation time 154824623 ps
CPU time 0.79 seconds
Started Jul 03 04:56:23 PM PDT 24
Finished Jul 03 04:56:25 PM PDT 24
Peak memory 206124 kb
Host smart-3bce7bd9-2cd0-40ca-b915-0272e65f392b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35771
24338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3577124338
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.714558914
Short name T2641
Test name
Test status
Simulation time 424649013 ps
CPU time 1.47 seconds
Started Jul 03 04:56:33 PM PDT 24
Finished Jul 03 04:56:35 PM PDT 24
Peak memory 206052 kb
Host smart-9301be60-92ec-468e-a2a4-de821771da73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71455
8914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.714558914
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.379346569
Short name T1994
Test name
Test status
Simulation time 444819915 ps
CPU time 1.31 seconds
Started Jul 03 04:56:28 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206128 kb
Host smart-0779295e-a08c-4c06-8087-358edb8473d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37934
6569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.379346569
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.1854845103
Short name T755
Test name
Test status
Simulation time 13778731530 ps
CPU time 27.51 seconds
Started Jul 03 04:56:24 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206388 kb
Host smart-1edbc3c8-fd13-40d4-a7c5-3ffc9cf834e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18548
45103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.1854845103
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.3437983308
Short name T2474
Test name
Test status
Simulation time 327514598 ps
CPU time 1.18 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206080 kb
Host smart-7b61ed69-b3c2-49dc-abc7-f2a3881f18b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34379
83308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.3437983308
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.21350594
Short name T2339
Test name
Test status
Simulation time 166972540 ps
CPU time 0.74 seconds
Started Jul 03 04:56:30 PM PDT 24
Finished Jul 03 04:56:31 PM PDT 24
Peak memory 206096 kb
Host smart-aadd9d12-69fa-47e0-8a9b-d45df0af1f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21350
594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.21350594
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3294303947
Short name T798
Test name
Test status
Simulation time 54846604 ps
CPU time 0.66 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:26 PM PDT 24
Peak memory 206064 kb
Host smart-066fa32c-5221-47ea-9ccf-c4d72dd0a1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32943
03947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3294303947
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1206447721
Short name T2117
Test name
Test status
Simulation time 808279406 ps
CPU time 2.03 seconds
Started Jul 03 04:56:16 PM PDT 24
Finished Jul 03 04:56:19 PM PDT 24
Peak memory 206364 kb
Host smart-404ee822-97bd-4fd4-9ccd-0e6a9386f1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12064
47721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1206447721
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.4100754356
Short name T1845
Test name
Test status
Simulation time 245052339 ps
CPU time 1.58 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:27 PM PDT 24
Peak memory 206340 kb
Host smart-003fc9d9-4bdb-49e4-af78-4faeb663db35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41007
54356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.4100754356
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.865337437
Short name T1245
Test name
Test status
Simulation time 235145937 ps
CPU time 1 seconds
Started Jul 03 04:56:29 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206140 kb
Host smart-3c5ce881-cd4f-4465-9fdd-793d725e052c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86533
7437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.865337437
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3131441627
Short name T628
Test name
Test status
Simulation time 147367452 ps
CPU time 0.78 seconds
Started Jul 03 04:56:29 PM PDT 24
Finished Jul 03 04:56:31 PM PDT 24
Peak memory 205996 kb
Host smart-4bf76e50-1996-448e-a905-fb5081c00d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31314
41627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3131441627
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.472303214
Short name T1801
Test name
Test status
Simulation time 217234178 ps
CPU time 0.84 seconds
Started Jul 03 04:56:30 PM PDT 24
Finished Jul 03 04:56:32 PM PDT 24
Peak memory 206112 kb
Host smart-de75a16b-a383-4b03-9733-9fc80893aec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47230
3214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.472303214
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.834953349
Short name T1297
Test name
Test status
Simulation time 213304790 ps
CPU time 0.9 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206120 kb
Host smart-846d09a7-4a0d-4b1c-8c6a-16df871d1872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83495
3349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.834953349
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.2282212307
Short name T1423
Test name
Test status
Simulation time 23281933417 ps
CPU time 23.9 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:50 PM PDT 24
Peak memory 206164 kb
Host smart-80aa66be-6dba-4662-96d7-4af9daeacc21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22822
12307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.2282212307
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1277795440
Short name T2657
Test name
Test status
Simulation time 3262142320 ps
CPU time 4.43 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:32 PM PDT 24
Peak memory 206160 kb
Host smart-603ac60f-3312-4305-90b3-a9ff9f6fadea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12777
95440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1277795440
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.897030552
Short name T1533
Test name
Test status
Simulation time 9426176163 ps
CPU time 92.82 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:58:01 PM PDT 24
Peak memory 206392 kb
Host smart-7955d60d-9cf8-4000-860a-7aa65ffbb112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89703
0552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.897030552
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.181575532
Short name T163
Test name
Test status
Simulation time 4354316428 ps
CPU time 42.55 seconds
Started Jul 03 04:56:48 PM PDT 24
Finished Jul 03 04:57:31 PM PDT 24
Peak memory 206384 kb
Host smart-26e6f642-e2d9-483a-8c24-f92cc20b0d20
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=181575532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.181575532
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.4230498188
Short name T2099
Test name
Test status
Simulation time 253368786 ps
CPU time 0.89 seconds
Started Jul 03 04:56:19 PM PDT 24
Finished Jul 03 04:56:20 PM PDT 24
Peak memory 206388 kb
Host smart-424c0598-baf1-4aeb-b481-d3935bbfbfc6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4230498188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.4230498188
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.853951378
Short name T2619
Test name
Test status
Simulation time 190776132 ps
CPU time 0.86 seconds
Started Jul 03 04:56:28 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206072 kb
Host smart-164e2913-ae55-4f65-b2e2-cd22dec0d3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85395
1378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.853951378
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.3243301987
Short name T616
Test name
Test status
Simulation time 4393608653 ps
CPU time 30.99 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206364 kb
Host smart-b2763f63-83b8-40e2-879b-5f36c8bcf671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32433
01987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.3243301987
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1337279522
Short name T1114
Test name
Test status
Simulation time 5850227244 ps
CPU time 41.36 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:57:08 PM PDT 24
Peak memory 206292 kb
Host smart-b8831e5d-68db-46db-a725-d4d6142de422
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1337279522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1337279522
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.236776281
Short name T1177
Test name
Test status
Simulation time 158784761 ps
CPU time 0.81 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206128 kb
Host smart-2fe82201-8452-427a-9e11-df8cfba25116
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=236776281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.236776281
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3252869375
Short name T2352
Test name
Test status
Simulation time 143395624 ps
CPU time 0.75 seconds
Started Jul 03 04:56:29 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206052 kb
Host smart-9e019ea0-27e9-46d7-a778-d56b5f7fc563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32528
69375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3252869375
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3811466456
Short name T2325
Test name
Test status
Simulation time 168751771 ps
CPU time 0.81 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:28 PM PDT 24
Peak memory 206084 kb
Host smart-39895bc3-7437-465f-b856-688c3f514814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38114
66456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3811466456
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1709508580
Short name T1427
Test name
Test status
Simulation time 158119445 ps
CPU time 0.82 seconds
Started Jul 03 04:56:32 PM PDT 24
Finished Jul 03 04:56:33 PM PDT 24
Peak memory 206088 kb
Host smart-b0c8467e-d870-4f7d-ae67-ceef3b61ec65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17095
08580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1709508580
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3836429925
Short name T651
Test name
Test status
Simulation time 152552015 ps
CPU time 0.82 seconds
Started Jul 03 04:56:28 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206092 kb
Host smart-334ff14a-2183-4891-9b4c-79c1ac416701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38364
29925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3836429925
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3804354209
Short name T760
Test name
Test status
Simulation time 176574590 ps
CPU time 0.8 seconds
Started Jul 03 04:56:57 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206044 kb
Host smart-31c0e8c6-a70a-4133-9685-68272f271966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38043
54209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3804354209
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1987529716
Short name T2135
Test name
Test status
Simulation time 164541199 ps
CPU time 0.79 seconds
Started Jul 03 04:56:31 PM PDT 24
Finished Jul 03 04:56:32 PM PDT 24
Peak memory 205980 kb
Host smart-31466e11-7326-4d4d-a05d-878bd553865c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19875
29716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1987529716
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.1787365570
Short name T1108
Test name
Test status
Simulation time 223520251 ps
CPU time 0.96 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:28 PM PDT 24
Peak memory 206100 kb
Host smart-f06ca871-6ca8-4b8c-9630-ad56209e247e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1787365570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.1787365570
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.6893702
Short name T1936
Test name
Test status
Simulation time 162653028 ps
CPU time 0.79 seconds
Started Jul 03 04:56:28 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206088 kb
Host smart-7b6e3ec8-a1b4-48de-a016-aa1af0ea22d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68937
02 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.6893702
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.380682393
Short name T1628
Test name
Test status
Simulation time 40578649 ps
CPU time 0.64 seconds
Started Jul 03 04:56:47 PM PDT 24
Finished Jul 03 04:56:48 PM PDT 24
Peak memory 206116 kb
Host smart-40d70c61-396a-469f-a117-c4d54c6c5e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38068
2393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.380682393
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2449164657
Short name T2524
Test name
Test status
Simulation time 12265085882 ps
CPU time 29.45 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:57:05 PM PDT 24
Peak memory 206480 kb
Host smart-76564078-0d02-455d-a581-f854ca4011c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24491
64657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2449164657
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.4235084317
Short name T1496
Test name
Test status
Simulation time 215925894 ps
CPU time 0.89 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:28 PM PDT 24
Peak memory 206100 kb
Host smart-a0673e38-93e2-4474-b896-773647754905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42350
84317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.4235084317
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1605643015
Short name T2660
Test name
Test status
Simulation time 209916954 ps
CPU time 0.91 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:28 PM PDT 24
Peak memory 206100 kb
Host smart-76e283ce-0cee-4812-a95b-e52eca918d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16056
43015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1605643015
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.190009084
Short name T2544
Test name
Test status
Simulation time 195973537 ps
CPU time 0.83 seconds
Started Jul 03 04:56:28 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206084 kb
Host smart-302b9cf0-a265-4755-a299-e1784671d687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19000
9084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.190009084
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.3799240305
Short name T2428
Test name
Test status
Simulation time 177289732 ps
CPU time 0.83 seconds
Started Jul 03 04:56:40 PM PDT 24
Finished Jul 03 04:56:41 PM PDT 24
Peak memory 206076 kb
Host smart-ef08d186-a528-4844-84b3-1fd624f118d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37992
40305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3799240305
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2197474143
Short name T2311
Test name
Test status
Simulation time 159544840 ps
CPU time 0.78 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206096 kb
Host smart-fbcbad43-8dd6-43dc-8dc2-a07546caa966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21974
74143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2197474143
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1451594486
Short name T586
Test name
Test status
Simulation time 158758501 ps
CPU time 0.79 seconds
Started Jul 03 04:56:29 PM PDT 24
Finished Jul 03 04:56:31 PM PDT 24
Peak memory 206128 kb
Host smart-82fbb1d9-0032-4e69-92f6-f88e0a0f1cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14515
94486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1451594486
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.4213261064
Short name T1841
Test name
Test status
Simulation time 158000929 ps
CPU time 0.77 seconds
Started Jul 03 04:57:08 PM PDT 24
Finished Jul 03 04:57:09 PM PDT 24
Peak memory 206132 kb
Host smart-8232f3e8-972a-4ddf-af74-01fe17b7f4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42132
61064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.4213261064
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3136748691
Short name T2369
Test name
Test status
Simulation time 230670823 ps
CPU time 0.98 seconds
Started Jul 03 04:56:30 PM PDT 24
Finished Jul 03 04:56:32 PM PDT 24
Peak memory 206116 kb
Host smart-738c3153-fbdd-4862-8630-4ee6236b38dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31367
48691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3136748691
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.2269139500
Short name T895
Test name
Test status
Simulation time 6392496504 ps
CPU time 55.98 seconds
Started Jul 03 04:56:34 PM PDT 24
Finished Jul 03 04:57:30 PM PDT 24
Peak memory 206384 kb
Host smart-91d1606e-a2e8-4508-a295-861fe1ae9037
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2269139500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.2269139500
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2158936327
Short name T1710
Test name
Test status
Simulation time 199934825 ps
CPU time 0.84 seconds
Started Jul 03 04:56:26 PM PDT 24
Finished Jul 03 04:56:28 PM PDT 24
Peak memory 206136 kb
Host smart-39332748-05f0-421a-b6ba-10a66301f150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21589
36327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2158936327
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.4051003601
Short name T2015
Test name
Test status
Simulation time 198683663 ps
CPU time 0.85 seconds
Started Jul 03 04:56:29 PM PDT 24
Finished Jul 03 04:56:30 PM PDT 24
Peak memory 206116 kb
Host smart-a51b15da-d64a-40e7-b4d9-0619b3a15001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40510
03601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.4051003601
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3913114355
Short name T2479
Test name
Test status
Simulation time 709874711 ps
CPU time 1.82 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:29 PM PDT 24
Peak memory 206328 kb
Host smart-c0c992a9-2872-49b0-8b34-46b87c09e82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39131
14355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3913114355
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2447487786
Short name T1550
Test name
Test status
Simulation time 7700006412 ps
CPU time 73.91 seconds
Started Jul 03 04:56:45 PM PDT 24
Finished Jul 03 04:57:59 PM PDT 24
Peak memory 206440 kb
Host smart-4bf27763-edff-4678-8fdf-6aed1baaddc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24474
87786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2447487786
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.14295090
Short name T553
Test name
Test status
Simulation time 41923533 ps
CPU time 0.68 seconds
Started Jul 03 04:52:29 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206168 kb
Host smart-0da929bc-17d5-4117-87c8-df53158b4a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=14295090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.14295090
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2943734897
Short name T2385
Test name
Test status
Simulation time 4083476364 ps
CPU time 4.38 seconds
Started Jul 03 04:52:09 PM PDT 24
Finished Jul 03 04:52:14 PM PDT 24
Peak memory 206404 kb
Host smart-adce5455-8e02-4217-ab6f-fe73682e198b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2943734897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.2943734897
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.736179033
Short name T963
Test name
Test status
Simulation time 13391280025 ps
CPU time 12.56 seconds
Started Jul 03 04:52:05 PM PDT 24
Finished Jul 03 04:52:18 PM PDT 24
Peak memory 206384 kb
Host smart-a961c131-c38a-490c-927d-c4a08b964c55
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=736179033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.736179033
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1197759143
Short name T1992
Test name
Test status
Simulation time 23439438741 ps
CPU time 26.49 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:52:37 PM PDT 24
Peak memory 206192 kb
Host smart-8e71998d-4d99-4651-a3b0-d126a5039fb5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1197759143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.1197759143
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.519181749
Short name T1803
Test name
Test status
Simulation time 179431722 ps
CPU time 0.84 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:52:09 PM PDT 24
Peak memory 206132 kb
Host smart-1a8211b0-d5ef-4a26-98ed-46518df9509e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51918
1749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.519181749
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.938308110
Short name T63
Test name
Test status
Simulation time 199397625 ps
CPU time 0.89 seconds
Started Jul 03 04:52:13 PM PDT 24
Finished Jul 03 04:52:14 PM PDT 24
Peak memory 206080 kb
Host smart-a46b9597-e30e-42c0-a282-8c6c22880fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93830
8110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.938308110
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2401408617
Short name T99
Test name
Test status
Simulation time 140425399 ps
CPU time 0.76 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:52:11 PM PDT 24
Peak memory 206124 kb
Host smart-943edf77-60c9-49c1-8a97-06935439418c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24014
08617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2401408617
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.419422263
Short name T1742
Test name
Test status
Simulation time 167145144 ps
CPU time 0.8 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206100 kb
Host smart-1692d37d-f834-4411-88fd-304090f2db9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41942
2263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.419422263
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.873961382
Short name T802
Test name
Test status
Simulation time 259748816 ps
CPU time 1.03 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:52:09 PM PDT 24
Peak memory 206112 kb
Host smart-4c3fdc46-f99e-43cc-931d-ea450c1ac4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87396
1382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.873961382
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.307564160
Short name T200
Test name
Test status
Simulation time 1348753524 ps
CPU time 2.96 seconds
Started Jul 03 04:52:21 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 206308 kb
Host smart-8b4d9f76-7e74-43eb-b253-00c9d0e60014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30756
4160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.307564160
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3086385133
Short name T179
Test name
Test status
Simulation time 6400141233 ps
CPU time 12.09 seconds
Started Jul 03 04:52:16 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 206352 kb
Host smart-15e4f989-2bf1-4537-84c1-fc482005eee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30863
85133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3086385133
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.748339423
Short name T743
Test name
Test status
Simulation time 318552792 ps
CPU time 1.15 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:52:04 PM PDT 24
Peak memory 206132 kb
Host smart-6823b490-3510-4956-934b-78e2349e11e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74833
9423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.748339423
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3848293154
Short name T1595
Test name
Test status
Simulation time 136731457 ps
CPU time 0.77 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206128 kb
Host smart-050c71b1-5550-466e-a001-c1e16ca44251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38482
93154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3848293154
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.346111162
Short name T1389
Test name
Test status
Simulation time 38851601 ps
CPU time 0.68 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206052 kb
Host smart-03246222-b6b4-4fcb-8cd8-9e34a424871d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34611
1162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.346111162
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.504433920
Short name T990
Test name
Test status
Simulation time 942372207 ps
CPU time 2.29 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:06 PM PDT 24
Peak memory 206360 kb
Host smart-0303863b-7528-4c09-a2d1-88082c2af30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50443
3920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.504433920
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3368532920
Short name T920
Test name
Test status
Simulation time 227747773 ps
CPU time 1.51 seconds
Started Jul 03 04:52:02 PM PDT 24
Finished Jul 03 04:52:04 PM PDT 24
Peak memory 206312 kb
Host smart-0f70387b-735d-4884-8a76-31877e784c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33685
32920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3368532920
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.3174064107
Short name T1947
Test name
Test status
Simulation time 101193667737 ps
CPU time 167.25 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:54:56 PM PDT 24
Peak memory 206388 kb
Host smart-99bcbde6-b601-49d4-bad8-c504a3f598e9
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3174064107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.3174064107
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.1452362574
Short name T2172
Test name
Test status
Simulation time 85226239753 ps
CPU time 113.3 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:53:58 PM PDT 24
Peak memory 206352 kb
Host smart-6ed6894a-3d46-4cb9-938d-aa69d3aaa3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452362574 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.1452362574
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1349773882
Short name T682
Test name
Test status
Simulation time 111113896776 ps
CPU time 135.8 seconds
Started Jul 03 04:52:05 PM PDT 24
Finished Jul 03 04:54:21 PM PDT 24
Peak memory 206332 kb
Host smart-8386fc73-585a-4575-b702-98fb12d8309d
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1349773882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1349773882
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1006229698
Short name T1074
Test name
Test status
Simulation time 93018374286 ps
CPU time 148.62 seconds
Started Jul 03 04:52:05 PM PDT 24
Finished Jul 03 04:54:34 PM PDT 24
Peak memory 206384 kb
Host smart-e10a6548-3bbb-41fe-8e3d-b189c730a192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006229698 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1006229698
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.1771084555
Short name T2073
Test name
Test status
Simulation time 108102541856 ps
CPU time 152.28 seconds
Started Jul 03 04:52:12 PM PDT 24
Finished Jul 03 04:54:45 PM PDT 24
Peak memory 206372 kb
Host smart-b8a063bf-0958-48b6-9f06-10b09400cdb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17710
84555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.1771084555
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.2924103737
Short name T2207
Test name
Test status
Simulation time 173237762 ps
CPU time 0.79 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206092 kb
Host smart-3eeef016-8118-4a4c-a610-255042f5565d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29241
03737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.2924103737
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3385625085
Short name T389
Test name
Test status
Simulation time 197289530 ps
CPU time 0.79 seconds
Started Jul 03 04:52:16 PM PDT 24
Finished Jul 03 04:52:18 PM PDT 24
Peak memory 206108 kb
Host smart-3c0edfe4-eb7c-4e3c-b0a3-46377418caa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33856
25085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3385625085
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3238727384
Short name T2206
Test name
Test status
Simulation time 265379959 ps
CPU time 0.92 seconds
Started Jul 03 04:52:05 PM PDT 24
Finished Jul 03 04:52:07 PM PDT 24
Peak memory 206072 kb
Host smart-f726cb2a-681b-4c23-a59c-5c6ac0c0c844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32387
27384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3238727384
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.3309795827
Short name T2305
Test name
Test status
Simulation time 7141845584 ps
CPU time 49.25 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206352 kb
Host smart-2dd84849-fb09-446d-aa78-a1b69f49ea40
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3309795827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3309795827
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.4045138808
Short name T2655
Test name
Test status
Simulation time 214636450 ps
CPU time 0.77 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:52:09 PM PDT 24
Peak memory 205944 kb
Host smart-631e9032-9860-4d56-be65-50b55e45887f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40451
38808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.4045138808
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.4135384328
Short name T239
Test name
Test status
Simulation time 23318655542 ps
CPU time 21.61 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:28 PM PDT 24
Peak memory 206192 kb
Host smart-b5569fe0-47d1-4a0d-97bf-48dba3a863bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41353
84328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.4135384328
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.4217324359
Short name T42
Test name
Test status
Simulation time 3341899706 ps
CPU time 3.99 seconds
Started Jul 03 04:52:05 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206148 kb
Host smart-07cb916d-c01e-4c29-b066-adec5355b170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42173
24359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.4217324359
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3531875681
Short name T2317
Test name
Test status
Simulation time 8805587858 ps
CPU time 79.53 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206460 kb
Host smart-0c2dbc99-2ca5-41ff-b080-1d2e234da097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35318
75681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3531875681
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.547439365
Short name T1697
Test name
Test status
Simulation time 4947543257 ps
CPU time 32.51 seconds
Started Jul 03 04:52:11 PM PDT 24
Finished Jul 03 04:52:44 PM PDT 24
Peak memory 206376 kb
Host smart-97719a72-604a-4e94-8796-a93d45c590d2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=547439365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.547439365
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3569050699
Short name T2066
Test name
Test status
Simulation time 304578198 ps
CPU time 0.94 seconds
Started Jul 03 04:52:09 PM PDT 24
Finished Jul 03 04:52:11 PM PDT 24
Peak memory 206116 kb
Host smart-f6de027a-a8bd-4a0b-a467-676cd7ee8d04
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3569050699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3569050699
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.4281578396
Short name T1898
Test name
Test status
Simulation time 221212595 ps
CPU time 0.86 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:52:12 PM PDT 24
Peak memory 206100 kb
Host smart-d4e201ee-0641-40bd-8df7-3e88f4a3213f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42815
78396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.4281578396
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3419815454
Short name T1996
Test name
Test status
Simulation time 6111627185 ps
CPU time 51.5 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:53:02 PM PDT 24
Peak memory 206440 kb
Host smart-6eaf7161-2cf2-4600-b73d-17b6463536d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34198
15454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3419815454
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2484458179
Short name T1471
Test name
Test status
Simulation time 3584383480 ps
CPU time 98.67 seconds
Started Jul 03 04:52:11 PM PDT 24
Finished Jul 03 04:53:50 PM PDT 24
Peak memory 206300 kb
Host smart-f0580d06-895f-4017-9182-bc421263e6c2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2484458179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2484458179
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.3227886484
Short name T2087
Test name
Test status
Simulation time 183052803 ps
CPU time 0.8 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:52:12 PM PDT 24
Peak memory 206116 kb
Host smart-872c888d-765a-4745-b16a-c8260362980d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3227886484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.3227886484
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2211306622
Short name T2673
Test name
Test status
Simulation time 180145965 ps
CPU time 0.82 seconds
Started Jul 03 04:52:03 PM PDT 24
Finished Jul 03 04:52:05 PM PDT 24
Peak memory 206108 kb
Host smart-2e51b96a-1989-44a9-b34d-7504adb6ca33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22113
06622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2211306622
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2059062542
Short name T135
Test name
Test status
Simulation time 208043133 ps
CPU time 0.84 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:07 PM PDT 24
Peak memory 206060 kb
Host smart-21decc31-bf00-4701-812c-737ae2b5ec33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20590
62542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2059062542
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.49327509
Short name T2490
Test name
Test status
Simulation time 147664438 ps
CPU time 0.76 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:07 PM PDT 24
Peak memory 206084 kb
Host smart-bc0fb34e-91e1-4438-837b-507c43bc57c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49327
509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.49327509
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2824585615
Short name T942
Test name
Test status
Simulation time 159546417 ps
CPU time 0.85 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206132 kb
Host smart-971b9c1b-5dc3-425d-974d-9b403329b6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28245
85615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2824585615
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.951891627
Short name T366
Test name
Test status
Simulation time 178851979 ps
CPU time 0.83 seconds
Started Jul 03 04:52:17 PM PDT 24
Finished Jul 03 04:52:18 PM PDT 24
Peak memory 206076 kb
Host smart-ad94fc63-84ea-4e77-b430-c5ae9e074537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95189
1627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.951891627
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3145154779
Short name T2217
Test name
Test status
Simulation time 148315109 ps
CPU time 0.78 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:52:06 PM PDT 24
Peak memory 206108 kb
Host smart-48e2cbfe-eb25-4121-b0b2-5112158332f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31451
54779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3145154779
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.790759150
Short name T499
Test name
Test status
Simulation time 225367958 ps
CPU time 0.94 seconds
Started Jul 03 04:52:09 PM PDT 24
Finished Jul 03 04:52:11 PM PDT 24
Peak memory 206096 kb
Host smart-59afe7ac-d2ed-4dc4-87c9-cbd4aaefdd77
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=790759150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.790759150
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.1996569442
Short name T1019
Test name
Test status
Simulation time 215086393 ps
CPU time 0.88 seconds
Started Jul 03 04:52:22 PM PDT 24
Finished Jul 03 04:52:23 PM PDT 24
Peak memory 206068 kb
Host smart-94f62104-d34a-43a2-a12f-40d84968d7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19965
69442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.1996569442
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.920919628
Short name T863
Test name
Test status
Simulation time 144220795 ps
CPU time 0.77 seconds
Started Jul 03 04:52:17 PM PDT 24
Finished Jul 03 04:52:19 PM PDT 24
Peak memory 206116 kb
Host smart-d68d38dd-df21-41c6-8cb2-2f9e4a7b2351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92091
9628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.920919628
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3805032447
Short name T426
Test name
Test status
Simulation time 63573646 ps
CPU time 0.68 seconds
Started Jul 03 04:52:13 PM PDT 24
Finished Jul 03 04:52:14 PM PDT 24
Peak memory 206136 kb
Host smart-b9cd370a-7d94-41e3-8c2c-c58490030a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38050
32447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3805032447
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2027565526
Short name T2449
Test name
Test status
Simulation time 18622529397 ps
CPU time 42.23 seconds
Started Jul 03 04:52:12 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 206416 kb
Host smart-69c66916-407e-4f0c-89b7-6d4400df89b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275
65526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2027565526
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3297515099
Short name T2401
Test name
Test status
Simulation time 208471768 ps
CPU time 0.81 seconds
Started Jul 03 04:52:05 PM PDT 24
Finished Jul 03 04:52:07 PM PDT 24
Peak memory 206124 kb
Host smart-23dee812-9f19-4e21-bc5e-f3922fd0fb09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32975
15099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3297515099
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3186888371
Short name T812
Test name
Test status
Simulation time 164742151 ps
CPU time 0.85 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:07 PM PDT 24
Peak memory 206116 kb
Host smart-11be93ed-4d24-4e15-8a0e-5941b48148ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31868
88371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3186888371
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.4117785575
Short name T883
Test name
Test status
Simulation time 7537041216 ps
CPU time 28.61 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:52:33 PM PDT 24
Peak memory 206448 kb
Host smart-182304e3-6b81-4150-bc83-992025a8b162
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4117785575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.4117785575
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1061689216
Short name T664
Test name
Test status
Simulation time 8518024186 ps
CPU time 128.14 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:54:16 PM PDT 24
Peak memory 206480 kb
Host smart-7eac4903-6181-44c8-96ab-fb2d7825679d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1061689216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1061689216
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.3601826021
Short name T587
Test name
Test status
Simulation time 246174190 ps
CPU time 0.98 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:07 PM PDT 24
Peak memory 206000 kb
Host smart-0ccb43a4-3216-4d5c-b498-1a4de1d7d30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36018
26021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.3601826021
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.44633276
Short name T1190
Test name
Test status
Simulation time 179707115 ps
CPU time 0.84 seconds
Started Jul 03 04:52:19 PM PDT 24
Finished Jul 03 04:52:20 PM PDT 24
Peak memory 206084 kb
Host smart-2bb46a58-af5b-4c05-93c5-579613baea94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44633
276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.44633276
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2806866539
Short name T1354
Test name
Test status
Simulation time 198054077 ps
CPU time 0.78 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206112 kb
Host smart-0e24b052-7327-400e-8cf1-8ef7523707fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28068
66539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2806866539
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2464506395
Short name T87
Test name
Test status
Simulation time 192927948 ps
CPU time 0.85 seconds
Started Jul 03 04:52:04 PM PDT 24
Finished Jul 03 04:52:06 PM PDT 24
Peak memory 206132 kb
Host smart-c41c4bab-9b7d-4eb2-acc9-f52d016d1476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24645
06395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2464506395
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3324796336
Short name T233
Test name
Test status
Simulation time 795906059 ps
CPU time 1.88 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:52:12 PM PDT 24
Peak memory 224016 kb
Host smart-42dda6bc-a071-455b-b890-81efb2489045
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3324796336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3324796336
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.1214270328
Short name T2627
Test name
Test status
Simulation time 374392367 ps
CPU time 1.28 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:52:09 PM PDT 24
Peak memory 206112 kb
Host smart-cbb5018f-b4e2-449b-ba4b-85e2479af7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12142
70328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.1214270328
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3086893212
Short name T1626
Test name
Test status
Simulation time 323080247 ps
CPU time 1.05 seconds
Started Jul 03 04:52:06 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206064 kb
Host smart-5b41e13e-af1d-47bc-bcd1-f65d44594e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30868
93212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3086893212
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3739703462
Short name T993
Test name
Test status
Simulation time 150938947 ps
CPU time 0.78 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206092 kb
Host smart-b1adda68-1bfe-4bb2-80fa-dedf91887cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37397
03462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3739703462
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3982428669
Short name T60
Test name
Test status
Simulation time 202577615 ps
CPU time 0.82 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:52:08 PM PDT 24
Peak memory 206092 kb
Host smart-9d7a50bc-2864-4fd1-8fa4-6ce580f1e122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39824
28669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3982428669
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2239668755
Short name T495
Test name
Test status
Simulation time 228155249 ps
CPU time 0.96 seconds
Started Jul 03 04:52:05 PM PDT 24
Finished Jul 03 04:52:07 PM PDT 24
Peak memory 206092 kb
Host smart-c6e42996-e210-4557-bb8e-667d3983a9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22396
68755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2239668755
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.2830472971
Short name T2324
Test name
Test status
Simulation time 3574258777 ps
CPU time 95.54 seconds
Started Jul 03 04:52:17 PM PDT 24
Finished Jul 03 04:53:53 PM PDT 24
Peak memory 206428 kb
Host smart-87212359-8eaf-4bcd-ab04-d2eda6a3ad87
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2830472971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.2830472971
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.17488403
Short name T1422
Test name
Test status
Simulation time 181563571 ps
CPU time 0.81 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206128 kb
Host smart-cb4779d1-87db-4a55-9c73-6e28c84c89dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17488
403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.17488403
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3535776087
Short name T728
Test name
Test status
Simulation time 244088251 ps
CPU time 0.88 seconds
Started Jul 03 04:52:21 PM PDT 24
Finished Jul 03 04:52:23 PM PDT 24
Peak memory 206132 kb
Host smart-14a54154-dd26-4b3b-8e35-b5d65f34f529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35357
76087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3535776087
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2123039512
Short name T1457
Test name
Test status
Simulation time 1070231949 ps
CPU time 2.55 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:12 PM PDT 24
Peak memory 206348 kb
Host smart-e394cc8d-8e09-4a58-b72b-d0b11c5cd734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21230
39512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2123039512
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.761786865
Short name T408
Test name
Test status
Simulation time 3400900758 ps
CPU time 91.2 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:53:40 PM PDT 24
Peak memory 206456 kb
Host smart-8e40bcbc-c0f4-4a21-82b5-9c6824dc1d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76178
6865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.761786865
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.796333335
Short name T2040
Test name
Test status
Simulation time 85854060 ps
CPU time 0.72 seconds
Started Jul 03 04:56:47 PM PDT 24
Finished Jul 03 04:56:48 PM PDT 24
Peak memory 206140 kb
Host smart-99cda1b5-8e3e-4907-ab36-b87f5df56589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=796333335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.796333335
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1133124139
Short name T919
Test name
Test status
Simulation time 3920681064 ps
CPU time 4.75 seconds
Started Jul 03 04:56:29 PM PDT 24
Finished Jul 03 04:56:35 PM PDT 24
Peak memory 206176 kb
Host smart-a8dd86de-bb3e-403e-8548-b422878e4584
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1133124139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1133124139
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3589690454
Short name T1774
Test name
Test status
Simulation time 23362637072 ps
CPU time 24.12 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:56:59 PM PDT 24
Peak memory 206188 kb
Host smart-3b95fafb-080c-46be-bcdb-74ad059221fb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3589690454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3589690454
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.4191676045
Short name T1604
Test name
Test status
Simulation time 204943099 ps
CPU time 0.8 seconds
Started Jul 03 04:56:40 PM PDT 24
Finished Jul 03 04:56:41 PM PDT 24
Peak memory 206128 kb
Host smart-1dbae1bb-425e-4b08-8a76-2ceb576f1fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41916
76045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.4191676045
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.365076153
Short name T2106
Test name
Test status
Simulation time 214642282 ps
CPU time 0.83 seconds
Started Jul 03 04:56:39 PM PDT 24
Finished Jul 03 04:56:40 PM PDT 24
Peak memory 206132 kb
Host smart-dca9af6a-e134-4623-9d14-88b7397fdd27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36507
6153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.365076153
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3415081199
Short name T35
Test name
Test status
Simulation time 670355419 ps
CPU time 1.74 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:56:56 PM PDT 24
Peak memory 206308 kb
Host smart-6ce50b93-0588-45e1-82cb-5cbdd26333ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34150
81199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3415081199
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.989783504
Short name T2506
Test name
Test status
Simulation time 330201896 ps
CPU time 1 seconds
Started Jul 03 04:56:25 PM PDT 24
Finished Jul 03 04:56:27 PM PDT 24
Peak memory 206100 kb
Host smart-e645b012-6c79-4f5e-b658-01f0058936c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98978
3504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.989783504
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.954747930
Short name T2319
Test name
Test status
Simulation time 9831634707 ps
CPU time 19.63 seconds
Started Jul 03 04:56:27 PM PDT 24
Finished Jul 03 04:56:48 PM PDT 24
Peak memory 206256 kb
Host smart-6109c6ad-d893-4032-b310-c6a2a56d9795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95474
7930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.954747930
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.904975118
Short name T2235
Test name
Test status
Simulation time 470430039 ps
CPU time 1.38 seconds
Started Jul 03 04:56:37 PM PDT 24
Finished Jul 03 04:56:39 PM PDT 24
Peak memory 206124 kb
Host smart-568f0fb9-65cf-4499-b6f7-35b8d68448df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90497
5118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.904975118
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.4255121818
Short name T1624
Test name
Test status
Simulation time 151847652 ps
CPU time 0.84 seconds
Started Jul 03 04:56:30 PM PDT 24
Finished Jul 03 04:56:32 PM PDT 24
Peak memory 206144 kb
Host smart-eccd437e-61f6-4a8b-a67b-6998bf0d7b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42551
21818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.4255121818
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2871848178
Short name T1351
Test name
Test status
Simulation time 51195521 ps
CPU time 0.68 seconds
Started Jul 03 04:56:45 PM PDT 24
Finished Jul 03 04:56:46 PM PDT 24
Peak memory 206052 kb
Host smart-ac012c83-a952-4e4e-86b3-a2a516f72037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28718
48178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2871848178
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2506855557
Short name T642
Test name
Test status
Simulation time 944669526 ps
CPU time 2.18 seconds
Started Jul 03 04:56:45 PM PDT 24
Finished Jul 03 04:56:48 PM PDT 24
Peak memory 206332 kb
Host smart-159b5ba3-cb95-4295-9d72-93552a985f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25068
55557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2506855557
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1016905008
Short name T735
Test name
Test status
Simulation time 328413921 ps
CPU time 2.18 seconds
Started Jul 03 04:56:30 PM PDT 24
Finished Jul 03 04:56:32 PM PDT 24
Peak memory 206352 kb
Host smart-b0752b90-5158-43cc-a8f1-c8a3b163db70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10169
05008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1016905008
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1604566052
Short name T1058
Test name
Test status
Simulation time 262320219 ps
CPU time 0.97 seconds
Started Jul 03 04:56:32 PM PDT 24
Finished Jul 03 04:56:34 PM PDT 24
Peak memory 206088 kb
Host smart-51087cb2-7d1b-43c9-a550-3f1f30703cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16045
66052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1604566052
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3587281387
Short name T1732
Test name
Test status
Simulation time 143773222 ps
CPU time 0.77 seconds
Started Jul 03 04:56:34 PM PDT 24
Finished Jul 03 04:56:35 PM PDT 24
Peak memory 206076 kb
Host smart-9c9cf738-0ded-4de3-aa9c-e35b3d02dc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35872
81387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3587281387
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2747079567
Short name T2120
Test name
Test status
Simulation time 214196621 ps
CPU time 0.84 seconds
Started Jul 03 04:56:30 PM PDT 24
Finished Jul 03 04:56:31 PM PDT 24
Peak memory 206144 kb
Host smart-f1f01f93-c5f4-4320-8558-94750f1f67e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27470
79567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2747079567
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.825198379
Short name T84
Test name
Test status
Simulation time 8070023219 ps
CPU time 71.81 seconds
Started Jul 03 04:56:47 PM PDT 24
Finished Jul 03 04:57:59 PM PDT 24
Peak memory 206344 kb
Host smart-90a23602-7b4c-4533-b48a-a839d62ec1ad
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=825198379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.825198379
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2915230480
Short name T73
Test name
Test status
Simulation time 224694032 ps
CPU time 0.97 seconds
Started Jul 03 04:56:29 PM PDT 24
Finished Jul 03 04:56:31 PM PDT 24
Peak memory 206148 kb
Host smart-5aaf5751-5934-41d5-9d2a-72249bec7363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29152
30480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2915230480
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1146498334
Short name T631
Test name
Test status
Simulation time 23372873808 ps
CPU time 25.36 seconds
Started Jul 03 04:56:29 PM PDT 24
Finished Jul 03 04:56:55 PM PDT 24
Peak memory 206196 kb
Host smart-b0112777-b603-4708-a500-453b9146fd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11464
98334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1146498334
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.533938207
Short name T1744
Test name
Test status
Simulation time 3270883629 ps
CPU time 3.57 seconds
Started Jul 03 04:56:34 PM PDT 24
Finished Jul 03 04:56:38 PM PDT 24
Peak memory 206132 kb
Host smart-770e23f7-dded-449e-9cc9-bf4af9295b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53393
8207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.533938207
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.357503082
Short name T251
Test name
Test status
Simulation time 13813110033 ps
CPU time 125.06 seconds
Started Jul 03 04:56:34 PM PDT 24
Finished Jul 03 04:58:40 PM PDT 24
Peak memory 206400 kb
Host smart-a24411ae-9578-4d48-bd7e-6d11ec526ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35750
3082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.357503082
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.247317758
Short name T1130
Test name
Test status
Simulation time 6756945085 ps
CPU time 49.74 seconds
Started Jul 03 04:56:33 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206336 kb
Host smart-cccf0d25-e59f-44a9-894d-3574b43785eb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=247317758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.247317758
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.492231564
Short name T1035
Test name
Test status
Simulation time 249148694 ps
CPU time 0.92 seconds
Started Jul 03 04:56:33 PM PDT 24
Finished Jul 03 04:56:34 PM PDT 24
Peak memory 206132 kb
Host smart-e2ee5cc6-0750-4e9e-a2a2-f4cc82504389
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=492231564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.492231564
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2080439049
Short name T428
Test name
Test status
Simulation time 204338152 ps
CPU time 0.93 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:56:36 PM PDT 24
Peak memory 206116 kb
Host smart-2e06511c-9eb9-4592-bb94-dc089b262e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20804
39049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2080439049
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1821713915
Short name T1661
Test name
Test status
Simulation time 5641871322 ps
CPU time 54.4 seconds
Started Jul 03 04:56:33 PM PDT 24
Finished Jul 03 04:57:28 PM PDT 24
Peak memory 206388 kb
Host smart-ca669361-59a9-4954-b0ec-424ea4f847d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18217
13915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1821713915
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.141289938
Short name T2429
Test name
Test status
Simulation time 7561719117 ps
CPU time 72.59 seconds
Started Jul 03 04:56:33 PM PDT 24
Finished Jul 03 04:57:46 PM PDT 24
Peak memory 206396 kb
Host smart-601b30f6-40e9-4608-b465-2e6a7e589dff
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=141289938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.141289938
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2158444507
Short name T1110
Test name
Test status
Simulation time 158206993 ps
CPU time 0.8 seconds
Started Jul 03 04:56:34 PM PDT 24
Finished Jul 03 04:56:35 PM PDT 24
Peak memory 206044 kb
Host smart-1737c9f7-7da6-46b1-9d2e-7f889e44da3b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2158444507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2158444507
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2518595653
Short name T2356
Test name
Test status
Simulation time 160087175 ps
CPU time 0.84 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:56:56 PM PDT 24
Peak memory 206040 kb
Host smart-1a825bb4-5c9b-4e98-902d-d878d5f748da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25185
95653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2518595653
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1130456252
Short name T1218
Test name
Test status
Simulation time 174733381 ps
CPU time 0.84 seconds
Started Jul 03 04:56:33 PM PDT 24
Finished Jul 03 04:56:34 PM PDT 24
Peak memory 206140 kb
Host smart-b19cb927-aa21-49e6-a1b5-9ee4dbe33518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11304
56252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1130456252
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2889544385
Short name T1402
Test name
Test status
Simulation time 152749270 ps
CPU time 0.77 seconds
Started Jul 03 04:56:32 PM PDT 24
Finished Jul 03 04:56:34 PM PDT 24
Peak memory 206140 kb
Host smart-59e256d4-d7cb-46de-93b7-425f0ffbb26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28895
44385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2889544385
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3348100109
Short name T442
Test name
Test status
Simulation time 180318401 ps
CPU time 0.8 seconds
Started Jul 03 04:56:30 PM PDT 24
Finished Jul 03 04:56:32 PM PDT 24
Peak memory 206136 kb
Host smart-deac32ee-9fb1-42f3-98f5-7d690556af81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33481
00109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3348100109
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3383223343
Short name T190
Test name
Test status
Simulation time 155947885 ps
CPU time 0.78 seconds
Started Jul 03 04:56:34 PM PDT 24
Finished Jul 03 04:56:36 PM PDT 24
Peak memory 206092 kb
Host smart-3cb3140e-778d-4d3c-988f-1cc262cd06bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33832
23343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3383223343
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.986442260
Short name T2482
Test name
Test status
Simulation time 259645431 ps
CPU time 0.98 seconds
Started Jul 03 04:56:34 PM PDT 24
Finished Jul 03 04:56:35 PM PDT 24
Peak memory 206076 kb
Host smart-43cabb4d-00ce-4ee7-9406-19f3e8436aa7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=986442260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.986442260
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2563425332
Short name T1772
Test name
Test status
Simulation time 186769700 ps
CPU time 0.94 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:56:37 PM PDT 24
Peak memory 206092 kb
Host smart-6d440d6c-2a1a-40a5-b5e9-880b0a679956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25634
25332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2563425332
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2939768407
Short name T23
Test name
Test status
Simulation time 44062462 ps
CPU time 0.71 seconds
Started Jul 03 04:56:34 PM PDT 24
Finished Jul 03 04:56:35 PM PDT 24
Peak memory 206124 kb
Host smart-8416f3f6-17a0-4460-aee0-c5d5196c83db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29397
68407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2939768407
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.705586201
Short name T1519
Test name
Test status
Simulation time 14400371262 ps
CPU time 35.51 seconds
Started Jul 03 04:56:41 PM PDT 24
Finished Jul 03 04:57:17 PM PDT 24
Peak memory 206428 kb
Host smart-875e94a8-c6a3-4fd3-bad7-ca7b2ce6638a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70558
6201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.705586201
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.827508096
Short name T1292
Test name
Test status
Simulation time 163060524 ps
CPU time 0.81 seconds
Started Jul 03 04:56:33 PM PDT 24
Finished Jul 03 04:56:34 PM PDT 24
Peak memory 206088 kb
Host smart-b3f6edbc-dada-40cf-8754-7e02572f7af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82750
8096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.827508096
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2649278535
Short name T1630
Test name
Test status
Simulation time 152977176 ps
CPU time 0.79 seconds
Started Jul 03 04:56:43 PM PDT 24
Finished Jul 03 04:56:44 PM PDT 24
Peak memory 206092 kb
Host smart-ea3620bc-a575-4694-b4d0-c5960aeb9a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26492
78535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2649278535
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.508966174
Short name T2105
Test name
Test status
Simulation time 212993001 ps
CPU time 0.89 seconds
Started Jul 03 04:56:43 PM PDT 24
Finished Jul 03 04:56:45 PM PDT 24
Peak memory 206040 kb
Host smart-839651e9-b13e-4634-8887-061f997f62b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50896
6174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.508966174
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1950259071
Short name T334
Test name
Test status
Simulation time 175257716 ps
CPU time 0.86 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:56:37 PM PDT 24
Peak memory 206112 kb
Host smart-5992968c-f277-4b63-9005-7c12497cc1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19502
59071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1950259071
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3202635970
Short name T1279
Test name
Test status
Simulation time 140867284 ps
CPU time 0.79 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:56:36 PM PDT 24
Peak memory 206072 kb
Host smart-c0398c4f-c9b2-400b-8d42-ec99e8fd5b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32026
35970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3202635970
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.3623660316
Short name T447
Test name
Test status
Simulation time 145733694 ps
CPU time 0.78 seconds
Started Jul 03 04:56:42 PM PDT 24
Finished Jul 03 04:56:43 PM PDT 24
Peak memory 206120 kb
Host smart-e93f30a3-1304-4055-9908-8e50f7100666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36236
60316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.3623660316
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.109933236
Short name T2107
Test name
Test status
Simulation time 161193270 ps
CPU time 0.81 seconds
Started Jul 03 04:56:45 PM PDT 24
Finished Jul 03 04:56:46 PM PDT 24
Peak memory 206116 kb
Host smart-a02aeac6-a69e-4f1d-8426-3db08b7b0897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10993
3236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.109933236
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1543103615
Short name T1054
Test name
Test status
Simulation time 213603126 ps
CPU time 0.89 seconds
Started Jul 03 04:56:55 PM PDT 24
Finished Jul 03 04:56:56 PM PDT 24
Peak memory 206128 kb
Host smart-2a4a450f-8825-468b-ab12-8621d2cd3217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15431
03615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1543103615
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2784084812
Short name T646
Test name
Test status
Simulation time 6472703817 ps
CPU time 172.26 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:59:43 PM PDT 24
Peak memory 206436 kb
Host smart-0b353dd1-edee-48fc-9291-d0bf02141070
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2784084812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2784084812
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1646602417
Short name T1411
Test name
Test status
Simulation time 208206205 ps
CPU time 0.82 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206088 kb
Host smart-4dc12a1b-f044-402d-826c-35ca29262c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16466
02417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1646602417
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.921935978
Short name T2342
Test name
Test status
Simulation time 227202019 ps
CPU time 0.93 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:56:37 PM PDT 24
Peak memory 205780 kb
Host smart-61f71463-6b94-45da-bd0d-bb91d9573c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92193
5978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.921935978
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.1186739062
Short name T2114
Test name
Test status
Simulation time 341031123 ps
CPU time 1.07 seconds
Started Jul 03 04:56:51 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206128 kb
Host smart-e2d3d6da-2712-4e29-91d1-2582713e2b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11867
39062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.1186739062
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1081111820
Short name T1926
Test name
Test status
Simulation time 5157525411 ps
CPU time 36.2 seconds
Started Jul 03 04:57:05 PM PDT 24
Finished Jul 03 04:57:41 PM PDT 24
Peak memory 206408 kb
Host smart-c3b51ea1-5896-461d-a454-c770a5fc0358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811
11820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1081111820
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.706402499
Short name T211
Test name
Test status
Simulation time 71024238 ps
CPU time 0.78 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206176 kb
Host smart-8f396fa8-3a1c-49c0-88b1-d8d8fd0f07ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=706402499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.706402499
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2192612475
Short name T2204
Test name
Test status
Simulation time 3803652839 ps
CPU time 4.4 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:56:40 PM PDT 24
Peak memory 206100 kb
Host smart-dbb3ee8c-ba6f-4936-a283-49702e3ede5b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2192612475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.2192612475
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1769184868
Short name T1848
Test name
Test status
Simulation time 13362375909 ps
CPU time 14.88 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:57:05 PM PDT 24
Peak memory 206400 kb
Host smart-35125ad9-9a20-451d-9089-5f2901478c97
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1769184868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1769184868
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.286275491
Short name T699
Test name
Test status
Simulation time 23333322982 ps
CPU time 24.22 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:57:00 PM PDT 24
Peak memory 205728 kb
Host smart-4afafd90-0ea6-487e-b76a-b2c2fb7d2787
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=286275491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.286275491
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2266589121
Short name T2504
Test name
Test status
Simulation time 153274135 ps
CPU time 0.88 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:56:36 PM PDT 24
Peak memory 206000 kb
Host smart-cddabc9d-d984-4484-87fd-84b6c4479c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22665
89121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2266589121
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1636463162
Short name T1857
Test name
Test status
Simulation time 152758361 ps
CPU time 0.77 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:56:36 PM PDT 24
Peak memory 206068 kb
Host smart-e33c2d6b-1853-4a04-b87f-ef656d6705d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16364
63162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1636463162
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2991388540
Short name T1221
Test name
Test status
Simulation time 322241974 ps
CPU time 1.17 seconds
Started Jul 03 04:56:44 PM PDT 24
Finished Jul 03 04:56:45 PM PDT 24
Peak memory 206116 kb
Host smart-656aa648-6dc9-44d0-8ea2-238444494260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29913
88540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2991388540
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1452833594
Short name T177
Test name
Test status
Simulation time 1306787300 ps
CPU time 2.91 seconds
Started Jul 03 04:56:35 PM PDT 24
Finished Jul 03 04:56:38 PM PDT 24
Peak memory 206308 kb
Host smart-becab154-54d6-40d8-88f1-b1395a46d074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14528
33594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1452833594
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.3120024448
Short name T1509
Test name
Test status
Simulation time 9011434147 ps
CPU time 18.2 seconds
Started Jul 03 04:56:45 PM PDT 24
Finished Jul 03 04:57:04 PM PDT 24
Peak memory 206444 kb
Host smart-5e88ce2f-7419-4b52-9210-a428c2e07b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31200
24448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.3120024448
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.3706722685
Short name T2531
Test name
Test status
Simulation time 440992490 ps
CPU time 1.29 seconds
Started Jul 03 04:56:34 PM PDT 24
Finished Jul 03 04:56:36 PM PDT 24
Peak memory 206108 kb
Host smart-05a428a4-e5c5-41d5-967f-0fa869f4b738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37067
22685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3706722685
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.382033204
Short name T450
Test name
Test status
Simulation time 201437607 ps
CPU time 0.8 seconds
Started Jul 03 04:56:58 PM PDT 24
Finished Jul 03 04:56:59 PM PDT 24
Peak memory 206100 kb
Host smart-fbd147c2-871d-40a3-b9d1-d9b6297b59a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38203
3204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.382033204
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3165575880
Short name T398
Test name
Test status
Simulation time 37145875 ps
CPU time 0.71 seconds
Started Jul 03 04:56:32 PM PDT 24
Finished Jul 03 04:56:33 PM PDT 24
Peak memory 205936 kb
Host smart-c1a40e40-3684-470f-95d2-a2be42abcbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31655
75880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3165575880
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3924404509
Short name T440
Test name
Test status
Simulation time 1001563087 ps
CPU time 2.59 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:57:06 PM PDT 24
Peak memory 206364 kb
Host smart-35b12da1-9496-49bc-a970-57e48a3b7cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39244
04509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3924404509
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3594891806
Short name T1053
Test name
Test status
Simulation time 239514640 ps
CPU time 1.43 seconds
Started Jul 03 04:56:32 PM PDT 24
Finished Jul 03 04:56:34 PM PDT 24
Peak memory 206336 kb
Host smart-c797a446-df61-4abd-93b1-96113dddd97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35948
91806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3594891806
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3402969132
Short name T2152
Test name
Test status
Simulation time 257874654 ps
CPU time 0.94 seconds
Started Jul 03 04:56:39 PM PDT 24
Finished Jul 03 04:56:41 PM PDT 24
Peak memory 206112 kb
Host smart-4a2985db-b199-415e-b8f3-8e7546cf3b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34029
69132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3402969132
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3256713819
Short name T1748
Test name
Test status
Simulation time 135548850 ps
CPU time 0.76 seconds
Started Jul 03 04:56:40 PM PDT 24
Finished Jul 03 04:56:41 PM PDT 24
Peak memory 206084 kb
Host smart-789025a1-a704-4b59-9cb8-d372799fab95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32567
13819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3256713819
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.751312352
Short name T1813
Test name
Test status
Simulation time 270391258 ps
CPU time 0.97 seconds
Started Jul 03 04:56:43 PM PDT 24
Finished Jul 03 04:56:44 PM PDT 24
Peak memory 206072 kb
Host smart-dc89e2a6-7a54-41cf-9184-6e6c5812f051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75131
2352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.751312352
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.4289933862
Short name T674
Test name
Test status
Simulation time 271278370 ps
CPU time 0.97 seconds
Started Jul 03 04:56:41 PM PDT 24
Finished Jul 03 04:56:43 PM PDT 24
Peak memory 206120 kb
Host smart-6fd17c72-9cf0-433e-b4eb-8b6f2e731573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42899
33862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.4289933862
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.2100994654
Short name T1029
Test name
Test status
Simulation time 23296661557 ps
CPU time 21.39 seconds
Started Jul 03 04:56:41 PM PDT 24
Finished Jul 03 04:57:03 PM PDT 24
Peak memory 206156 kb
Host smart-8bec6084-69e6-42af-9f0f-198732bbb7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21009
94654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.2100994654
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1184822396
Short name T1797
Test name
Test status
Simulation time 3279441196 ps
CPU time 3.63 seconds
Started Jul 03 04:57:01 PM PDT 24
Finished Jul 03 04:57:05 PM PDT 24
Peak memory 206148 kb
Host smart-e458771c-3ec7-4880-a91e-54f431e0f2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11848
22396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1184822396
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1604609643
Short name T2477
Test name
Test status
Simulation time 9469780742 ps
CPU time 265.39 seconds
Started Jul 03 04:56:47 PM PDT 24
Finished Jul 03 05:01:13 PM PDT 24
Peak memory 206452 kb
Host smart-df4a52c0-ece3-488f-a642-fd73c8036b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16046
09643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1604609643
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1667716635
Short name T1226
Test name
Test status
Simulation time 5897148946 ps
CPU time 167.13 seconds
Started Jul 03 04:56:42 PM PDT 24
Finished Jul 03 04:59:29 PM PDT 24
Peak memory 206384 kb
Host smart-bcce5d5d-f511-4602-94ff-97d05698f737
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1667716635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1667716635
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.4034777557
Short name T781
Test name
Test status
Simulation time 234046325 ps
CPU time 0.91 seconds
Started Jul 03 04:56:49 PM PDT 24
Finished Jul 03 04:56:50 PM PDT 24
Peak memory 206112 kb
Host smart-7415cdc7-9e4b-42af-a9fa-0978cbc90b56
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4034777557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.4034777557
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3406434191
Short name T90
Test name
Test status
Simulation time 194899363 ps
CPU time 0.87 seconds
Started Jul 03 04:56:40 PM PDT 24
Finished Jul 03 04:56:41 PM PDT 24
Peak memory 206064 kb
Host smart-1b8f441e-9c6a-483c-9ebc-7ec6fe548b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34064
34191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3406434191
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.1527865931
Short name T403
Test name
Test status
Simulation time 5568780350 ps
CPU time 146.05 seconds
Started Jul 03 04:56:56 PM PDT 24
Finished Jul 03 04:59:22 PM PDT 24
Peak memory 206368 kb
Host smart-1ba88c4e-938b-49bb-9072-4cc4ff4fe0bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15278
65931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.1527865931
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.4188459198
Short name T1381
Test name
Test status
Simulation time 4740611526 ps
CPU time 135.03 seconds
Started Jul 03 04:56:51 PM PDT 24
Finished Jul 03 04:59:07 PM PDT 24
Peak memory 206376 kb
Host smart-2768ce1a-6420-40f8-8f1c-e76c48158897
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4188459198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.4188459198
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2584068361
Short name T1060
Test name
Test status
Simulation time 156780168 ps
CPU time 0.79 seconds
Started Jul 03 04:56:40 PM PDT 24
Finished Jul 03 04:56:41 PM PDT 24
Peak memory 206096 kb
Host smart-e4cedece-b974-4d7d-989e-a94092b706d2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2584068361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2584068361
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.435391565
Short name T2233
Test name
Test status
Simulation time 144475650 ps
CPU time 0.77 seconds
Started Jul 03 04:56:47 PM PDT 24
Finished Jul 03 04:56:48 PM PDT 24
Peak memory 206120 kb
Host smart-5859e41c-d6be-44fe-b81c-bad999433cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43539
1565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.435391565
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1501436497
Short name T139
Test name
Test status
Simulation time 187798334 ps
CPU time 0.87 seconds
Started Jul 03 04:56:56 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206108 kb
Host smart-ffd8c59d-aa9b-473d-98a4-3a4dd204b629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15014
36497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1501436497
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.816017933
Short name T2507
Test name
Test status
Simulation time 143615375 ps
CPU time 0.77 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:56:51 PM PDT 24
Peak memory 206124 kb
Host smart-15e892e9-095f-44e2-b7d7-0eb35a2dfe57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81601
7933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.816017933
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1074227906
Short name T1522
Test name
Test status
Simulation time 163639019 ps
CPU time 0.8 seconds
Started Jul 03 04:56:48 PM PDT 24
Finished Jul 03 04:56:49 PM PDT 24
Peak memory 206072 kb
Host smart-d8d2cecf-32cf-4c05-b11d-7152aa2d69b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10742
27906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1074227906
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.340331933
Short name T1332
Test name
Test status
Simulation time 221296341 ps
CPU time 0.88 seconds
Started Jul 03 04:56:58 PM PDT 24
Finished Jul 03 04:57:00 PM PDT 24
Peak memory 206040 kb
Host smart-048094ec-517e-44d0-88ce-2b253ed183a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34033
1933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.340331933
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3643576245
Short name T204
Test name
Test status
Simulation time 161414797 ps
CPU time 0.82 seconds
Started Jul 03 04:56:52 PM PDT 24
Finished Jul 03 04:56:53 PM PDT 24
Peak memory 205936 kb
Host smart-638bc08e-7738-48ee-af7b-f5231c6b174a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36435
76245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3643576245
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.568572762
Short name T747
Test name
Test status
Simulation time 269830564 ps
CPU time 1.01 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:57:03 PM PDT 24
Peak memory 206128 kb
Host smart-5b7260dd-99d2-44ab-b4d2-b6791e8b844c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=568572762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.568572762
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2050466115
Short name T1355
Test name
Test status
Simulation time 193813671 ps
CPU time 0.8 seconds
Started Jul 03 04:57:01 PM PDT 24
Finished Jul 03 04:57:03 PM PDT 24
Peak memory 206020 kb
Host smart-0a44eb45-cea8-45e5-b22a-ca8b9f132613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20504
66115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2050466115
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3246796041
Short name T1455
Test name
Test status
Simulation time 65848284 ps
CPU time 0.68 seconds
Started Jul 03 04:56:52 PM PDT 24
Finished Jul 03 04:56:53 PM PDT 24
Peak memory 205968 kb
Host smart-ad58ef58-088e-4f5a-bc1a-4ef4d1810761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32467
96041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3246796041
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1082722708
Short name T2267
Test name
Test status
Simulation time 14864102206 ps
CPU time 35.15 seconds
Started Jul 03 04:56:42 PM PDT 24
Finished Jul 03 04:57:18 PM PDT 24
Peak memory 206392 kb
Host smart-47d93227-8b13-48ee-99bb-1143dc50ba15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10827
22708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1082722708
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.334123849
Short name T1073
Test name
Test status
Simulation time 178074677 ps
CPU time 0.82 seconds
Started Jul 03 04:56:57 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206128 kb
Host smart-3ef32f04-f98b-434c-bd9e-d7a3bc9906cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33412
3849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.334123849
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.398065936
Short name T1325
Test name
Test status
Simulation time 172040699 ps
CPU time 0.81 seconds
Started Jul 03 04:57:00 PM PDT 24
Finished Jul 03 04:57:01 PM PDT 24
Peak memory 206040 kb
Host smart-99c9b3f3-5acb-49bc-abc5-f58460fc8279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39806
5936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.398065936
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.2383639367
Short name T2075
Test name
Test status
Simulation time 187945762 ps
CPU time 0.87 seconds
Started Jul 03 04:56:42 PM PDT 24
Finished Jul 03 04:56:44 PM PDT 24
Peak memory 206108 kb
Host smart-f844e1dc-4ba5-405a-b8c9-32330c1bd1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23836
39367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.2383639367
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3163077171
Short name T823
Test name
Test status
Simulation time 169978590 ps
CPU time 0.8 seconds
Started Jul 03 04:56:49 PM PDT 24
Finished Jul 03 04:56:50 PM PDT 24
Peak memory 206132 kb
Host smart-077de609-b154-4f06-abfc-174e8336f0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31630
77171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3163077171
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.3153793892
Short name T1917
Test name
Test status
Simulation time 146692556 ps
CPU time 0.76 seconds
Started Jul 03 04:56:41 PM PDT 24
Finished Jul 03 04:56:42 PM PDT 24
Peak memory 206132 kb
Host smart-2985dfe9-8c4a-42f6-90b4-b9813d07fa19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31537
93892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.3153793892
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.250165817
Short name T2530
Test name
Test status
Simulation time 148661370 ps
CPU time 0.77 seconds
Started Jul 03 04:56:38 PM PDT 24
Finished Jul 03 04:56:39 PM PDT 24
Peak memory 205972 kb
Host smart-4aae018e-99f1-4210-a06c-6045ef856faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25016
5817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.250165817
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.334805565
Short name T711
Test name
Test status
Simulation time 160561197 ps
CPU time 0.85 seconds
Started Jul 03 04:56:53 PM PDT 24
Finished Jul 03 04:56:54 PM PDT 24
Peak memory 206108 kb
Host smart-2a3e714a-f455-494b-a924-44648f56ee88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33480
5565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.334805565
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2146882206
Short name T670
Test name
Test status
Simulation time 215050653 ps
CPU time 0.98 seconds
Started Jul 03 04:56:51 PM PDT 24
Finished Jul 03 04:56:53 PM PDT 24
Peak memory 206124 kb
Host smart-8b0578f5-9b2d-4486-9a0d-05bf1102bac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21468
82206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2146882206
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.75938813
Short name T1066
Test name
Test status
Simulation time 4712617487 ps
CPU time 45.5 seconds
Started Jul 03 04:56:51 PM PDT 24
Finished Jul 03 04:57:38 PM PDT 24
Peak memory 206352 kb
Host smart-ec39cb96-bafc-4e1c-84af-db7e9770d534
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=75938813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.75938813
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1647682886
Short name T2367
Test name
Test status
Simulation time 195904170 ps
CPU time 0.88 seconds
Started Jul 03 04:56:43 PM PDT 24
Finished Jul 03 04:56:44 PM PDT 24
Peak memory 205976 kb
Host smart-3cb3189b-ac27-480c-baa0-8e4e6fb57e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16476
82886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1647682886
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3390663686
Short name T813
Test name
Test status
Simulation time 196352280 ps
CPU time 0.86 seconds
Started Jul 03 04:56:45 PM PDT 24
Finished Jul 03 04:56:46 PM PDT 24
Peak memory 205976 kb
Host smart-d266122a-9bee-41fe-8f3e-74dc8dfae44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33906
63686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3390663686
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.615477383
Short name T1022
Test name
Test status
Simulation time 930316207 ps
CPU time 1.94 seconds
Started Jul 03 04:56:55 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206376 kb
Host smart-002b40a3-9ba7-4184-950d-4f5703e0da44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61547
7383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.615477383
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2967623886
Short name T671
Test name
Test status
Simulation time 4785784818 ps
CPU time 130.44 seconds
Started Jul 03 04:56:49 PM PDT 24
Finished Jul 03 04:59:00 PM PDT 24
Peak memory 206400 kb
Host smart-e61ed9f3-6299-4ca1-b8e9-b8200c1e9761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29676
23886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2967623886
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2563972420
Short name T2604
Test name
Test status
Simulation time 102080682 ps
CPU time 0.73 seconds
Started Jul 03 04:56:52 PM PDT 24
Finished Jul 03 04:56:53 PM PDT 24
Peak memory 206164 kb
Host smart-9b4cc406-8799-4dcf-9a59-5cdefe1e6d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2563972420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2563972420
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.680906838
Short name T1314
Test name
Test status
Simulation time 3596855787 ps
CPU time 4.45 seconds
Started Jul 03 04:56:53 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206352 kb
Host smart-218ff1e2-37ef-481b-8a95-7001605ba1c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=680906838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.680906838
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3510236359
Short name T1627
Test name
Test status
Simulation time 13404450635 ps
CPU time 12.21 seconds
Started Jul 03 04:56:49 PM PDT 24
Finished Jul 03 04:57:02 PM PDT 24
Peak memory 206136 kb
Host smart-c18784b7-3133-4d9c-811d-54a04a01bc28
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3510236359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3510236359
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3685976888
Short name T2582
Test name
Test status
Simulation time 23481192828 ps
CPU time 26.05 seconds
Started Jul 03 04:56:38 PM PDT 24
Finished Jul 03 04:57:04 PM PDT 24
Peak memory 206320 kb
Host smart-7cfe2ac3-d6c4-4a03-a192-453d1a025c3c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3685976888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.3685976888
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1325253777
Short name T729
Test name
Test status
Simulation time 177383829 ps
CPU time 0.78 seconds
Started Jul 03 04:56:51 PM PDT 24
Finished Jul 03 04:56:53 PM PDT 24
Peak memory 206120 kb
Host smart-961813da-b189-4e65-b6bf-4fe6c7b63585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13252
53777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1325253777
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.58100334
Short name T643
Test name
Test status
Simulation time 151297143 ps
CPU time 0.86 seconds
Started Jul 03 04:56:43 PM PDT 24
Finished Jul 03 04:56:44 PM PDT 24
Peak memory 205976 kb
Host smart-e405c8c4-4a34-4961-869e-fae5f3148438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58100
334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.58100334
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.2842041718
Short name T2510
Test name
Test status
Simulation time 317745826 ps
CPU time 1.11 seconds
Started Jul 03 04:56:47 PM PDT 24
Finished Jul 03 04:56:48 PM PDT 24
Peak memory 206132 kb
Host smart-98113987-3c75-4afa-b13d-e371c0ae197d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28420
41718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.2842041718
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.2126949151
Short name T203
Test name
Test status
Simulation time 628972111 ps
CPU time 1.76 seconds
Started Jul 03 04:56:43 PM PDT 24
Finished Jul 03 04:56:45 PM PDT 24
Peak memory 206152 kb
Host smart-dd72b0ef-2358-4943-ad18-3b1dc2daa70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21269
49151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.2126949151
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.3030074533
Short name T1699
Test name
Test status
Simulation time 11482861521 ps
CPU time 22.59 seconds
Started Jul 03 04:56:43 PM PDT 24
Finished Jul 03 04:57:06 PM PDT 24
Peak memory 206444 kb
Host smart-a5508c0b-d36b-4786-9051-2da37e91acbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30300
74533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.3030074533
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.2194262821
Short name T1458
Test name
Test status
Simulation time 400333536 ps
CPU time 1.31 seconds
Started Jul 03 04:56:52 PM PDT 24
Finished Jul 03 04:56:54 PM PDT 24
Peak memory 206100 kb
Host smart-57fc34ee-18e8-4a69-aac5-8a83e9e0829c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21942
62821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.2194262821
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2609161207
Short name T810
Test name
Test status
Simulation time 138370303 ps
CPU time 0.75 seconds
Started Jul 03 04:56:47 PM PDT 24
Finished Jul 03 04:56:48 PM PDT 24
Peak memory 206096 kb
Host smart-7b5082e3-dee1-4ff6-bb84-7ff5b2f9089c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26091
61207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2609161207
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.849061056
Short name T1079
Test name
Test status
Simulation time 33801819 ps
CPU time 0.69 seconds
Started Jul 03 04:57:08 PM PDT 24
Finished Jul 03 04:57:09 PM PDT 24
Peak memory 206120 kb
Host smart-279c7ae2-fb7a-418c-9f12-7cf81c3a0e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84906
1056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.849061056
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.1263213098
Short name T1615
Test name
Test status
Simulation time 833846305 ps
CPU time 2.28 seconds
Started Jul 03 04:56:52 PM PDT 24
Finished Jul 03 04:56:55 PM PDT 24
Peak memory 206328 kb
Host smart-4b544e3f-a1e7-4da4-b2ed-e2dc9cabccea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12632
13098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.1263213098
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2302446691
Short name T2374
Test name
Test status
Simulation time 212147583 ps
CPU time 2.15 seconds
Started Jul 03 04:56:39 PM PDT 24
Finished Jul 03 04:56:41 PM PDT 24
Peak memory 206268 kb
Host smart-b951d6db-5ab5-480d-a134-a9ac3aad7f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23024
46691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2302446691
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3227010482
Short name T1056
Test name
Test status
Simulation time 246986055 ps
CPU time 0.91 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:56:51 PM PDT 24
Peak memory 206116 kb
Host smart-33628bb4-34c0-4196-ad79-dbc6ba787082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32270
10482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3227010482
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3657688662
Short name T1030
Test name
Test status
Simulation time 152366377 ps
CPU time 0.9 seconds
Started Jul 03 04:56:48 PM PDT 24
Finished Jul 03 04:56:49 PM PDT 24
Peak memory 206088 kb
Host smart-d58fd6e3-7a0a-4fea-aedd-0344492a5dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36576
88662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3657688662
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1819050538
Short name T2101
Test name
Test status
Simulation time 171864415 ps
CPU time 0.91 seconds
Started Jul 03 04:56:46 PM PDT 24
Finished Jul 03 04:56:47 PM PDT 24
Peak memory 206144 kb
Host smart-53539bb4-cc51-45f1-81c7-390f7dbda214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18190
50538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1819050538
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1097808770
Short name T859
Test name
Test status
Simulation time 7151423036 ps
CPU time 49.64 seconds
Started Jul 03 04:56:57 PM PDT 24
Finished Jul 03 04:57:48 PM PDT 24
Peak memory 206376 kb
Host smart-b5b5f951-1c77-4660-ac60-d795f37a4181
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1097808770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1097808770
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2957537862
Short name T1856
Test name
Test status
Simulation time 192559104 ps
CPU time 0.89 seconds
Started Jul 03 04:56:58 PM PDT 24
Finished Jul 03 04:57:00 PM PDT 24
Peak memory 206132 kb
Host smart-77a2c591-29e0-4127-bcc9-e225d56745c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29575
37862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2957537862
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.2155363365
Short name T1006
Test name
Test status
Simulation time 23335492600 ps
CPU time 23.06 seconds
Started Jul 03 04:57:01 PM PDT 24
Finished Jul 03 04:57:24 PM PDT 24
Peak memory 206196 kb
Host smart-8cf72bce-1d08-4e70-96df-e40b34be2bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21553
63365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2155363365
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1815365249
Short name T613
Test name
Test status
Simulation time 3344231509 ps
CPU time 4.91 seconds
Started Jul 03 04:56:47 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206168 kb
Host smart-c2531391-7386-4686-932b-227ce8a33204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18153
65249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1815365249
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.1181773803
Short name T869
Test name
Test status
Simulation time 11645008701 ps
CPU time 85.19 seconds
Started Jul 03 04:56:48 PM PDT 24
Finished Jul 03 04:58:14 PM PDT 24
Peak memory 206452 kb
Host smart-7b92e7ec-04ca-40c2-8380-bf9692b6e569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11817
73803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.1181773803
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.1231989148
Short name T652
Test name
Test status
Simulation time 5236595850 ps
CPU time 51.04 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:57:45 PM PDT 24
Peak memory 206348 kb
Host smart-0b02a27f-0c60-49a1-95d4-79b8f0b5479d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1231989148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1231989148
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.300412607
Short name T982
Test name
Test status
Simulation time 241481575 ps
CPU time 0.96 seconds
Started Jul 03 04:56:38 PM PDT 24
Finished Jul 03 04:56:39 PM PDT 24
Peak memory 206056 kb
Host smart-804394b0-fd67-4460-bc5f-32837907aad6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=300412607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.300412607
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3731322657
Short name T1250
Test name
Test status
Simulation time 193393937 ps
CPU time 0.96 seconds
Started Jul 03 04:56:39 PM PDT 24
Finished Jul 03 04:56:40 PM PDT 24
Peak memory 206076 kb
Host smart-f48ac3c8-bd32-4c9a-ac5b-f97291df866c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37313
22657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3731322657
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.658892387
Short name T571
Test name
Test status
Simulation time 3677845050 ps
CPU time 95.33 seconds
Started Jul 03 04:57:03 PM PDT 24
Finished Jul 03 04:58:39 PM PDT 24
Peak memory 206392 kb
Host smart-c4566bed-0dd1-4dac-8d6f-d9bc7d99ee43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65889
2387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.658892387
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3175910198
Short name T2698
Test name
Test status
Simulation time 3201192034 ps
CPU time 87.03 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:58:30 PM PDT 24
Peak memory 206384 kb
Host smart-b5ee0d03-e710-4bc3-a73a-c2e0e1a9ca96
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3175910198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3175910198
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3468388255
Short name T1795
Test name
Test status
Simulation time 158498697 ps
CPU time 0.79 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:56:56 PM PDT 24
Peak memory 206128 kb
Host smart-c91ce0a0-c0a1-40dd-a2e1-e6faa2115f20
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3468388255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3468388255
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.4267705699
Short name T1133
Test name
Test status
Simulation time 216335688 ps
CPU time 0.81 seconds
Started Jul 03 04:56:58 PM PDT 24
Finished Jul 03 04:56:59 PM PDT 24
Peak memory 206108 kb
Host smart-d2df9b93-2a77-4734-86f3-d211db9d28dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42677
05699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.4267705699
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1298749123
Short name T126
Test name
Test status
Simulation time 216925473 ps
CPU time 0.85 seconds
Started Jul 03 04:56:49 PM PDT 24
Finished Jul 03 04:56:50 PM PDT 24
Peak memory 206072 kb
Host smart-8a7cd022-324a-4ee5-a766-3d2be39dec4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12987
49123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1298749123
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.838640486
Short name T2162
Test name
Test status
Simulation time 194775839 ps
CPU time 0.93 seconds
Started Jul 03 04:56:45 PM PDT 24
Finished Jul 03 04:56:46 PM PDT 24
Peak memory 206116 kb
Host smart-b38d7ec5-e765-4e1b-b3be-0d1c7d198b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83864
0486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.838640486
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.794832862
Short name T2069
Test name
Test status
Simulation time 205935689 ps
CPU time 0.85 seconds
Started Jul 03 04:56:53 PM PDT 24
Finished Jul 03 04:56:54 PM PDT 24
Peak memory 206052 kb
Host smart-0dc68916-5362-4e9a-bdf4-670c4415b0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79483
2862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.794832862
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1229435097
Short name T2034
Test name
Test status
Simulation time 250558034 ps
CPU time 0.92 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:57:03 PM PDT 24
Peak memory 206132 kb
Host smart-582e8732-c992-4622-9547-b4e57fa085a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12294
35097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1229435097
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3290097843
Short name T1353
Test name
Test status
Simulation time 176316716 ps
CPU time 0.83 seconds
Started Jul 03 04:56:56 PM PDT 24
Finished Jul 03 04:56:57 PM PDT 24
Peak memory 206116 kb
Host smart-b123ae58-75bb-4621-9fb7-b577b5e376c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32900
97843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3290097843
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.2219726123
Short name T2021
Test name
Test status
Simulation time 231819176 ps
CPU time 1.01 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:57:03 PM PDT 24
Peak memory 206132 kb
Host smart-ca14aff7-ec8c-4cf4-a2c8-8518bec2c72a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2219726123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.2219726123
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3272878352
Short name T1181
Test name
Test status
Simulation time 137992100 ps
CPU time 0.75 seconds
Started Jul 03 04:56:57 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206112 kb
Host smart-7da33f7a-e577-479a-be19-09ef79deed80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32728
78352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3272878352
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.953256614
Short name T1429
Test name
Test status
Simulation time 56764179 ps
CPU time 0.66 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:56:51 PM PDT 24
Peak memory 206100 kb
Host smart-85628080-be9a-4d8b-aaa7-62483a32e965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95325
6614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.953256614
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.828987815
Short name T298
Test name
Test status
Simulation time 16482000652 ps
CPU time 38.75 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:58 PM PDT 24
Peak memory 206368 kb
Host smart-23d0b43e-39ad-4b0d-b359-4ea3b0c0b98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82898
7815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.828987815
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.487819194
Short name T315
Test name
Test status
Simulation time 162294169 ps
CPU time 0.79 seconds
Started Jul 03 04:56:57 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206128 kb
Host smart-11d90340-4495-4376-9779-4dc4b8942676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48781
9194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.487819194
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2807966730
Short name T1608
Test name
Test status
Simulation time 290042263 ps
CPU time 0.99 seconds
Started Jul 03 04:56:49 PM PDT 24
Finished Jul 03 04:56:50 PM PDT 24
Peak memory 206092 kb
Host smart-5ba363f7-fd98-4149-b713-70db8f43db60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28079
66730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2807966730
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.4053910755
Short name T848
Test name
Test status
Simulation time 237813342 ps
CPU time 0.9 seconds
Started Jul 03 04:56:57 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206120 kb
Host smart-6af91942-2559-424a-958e-e7f74e2306ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40539
10755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.4053910755
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.745299591
Short name T2089
Test name
Test status
Simulation time 213281550 ps
CPU time 0.91 seconds
Started Jul 03 04:57:09 PM PDT 24
Finished Jul 03 04:57:10 PM PDT 24
Peak memory 206128 kb
Host smart-b1dbf830-5a29-4f4b-87df-a2dd486db3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74529
9591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.745299591
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1213797441
Short name T2550
Test name
Test status
Simulation time 182544910 ps
CPU time 0.83 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:14 PM PDT 24
Peak memory 206092 kb
Host smart-2860ba8f-19b0-46ab-a9d7-9f01d8425cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12137
97441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1213797441
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.712760523
Short name T1360
Test name
Test status
Simulation time 156551599 ps
CPU time 0.81 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:14 PM PDT 24
Peak memory 206088 kb
Host smart-59100603-379c-4aea-9f74-edbdf451d1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71276
0523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.712760523
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2185621111
Short name T385
Test name
Test status
Simulation time 150578721 ps
CPU time 0.81 seconds
Started Jul 03 04:56:42 PM PDT 24
Finished Jul 03 04:56:43 PM PDT 24
Peak memory 206112 kb
Host smart-1a378203-fe2c-42eb-9475-5873417c36fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21856
21111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2185621111
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.440452030
Short name T1690
Test name
Test status
Simulation time 218006281 ps
CPU time 0.93 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:56:55 PM PDT 24
Peak memory 206132 kb
Host smart-81262d05-7769-46ad-b344-bac23c566b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44045
2030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.440452030
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.639295992
Short name T561
Test name
Test status
Simulation time 5590674838 ps
CPU time 53.57 seconds
Started Jul 03 04:57:04 PM PDT 24
Finished Jul 03 04:57:58 PM PDT 24
Peak memory 206368 kb
Host smart-c2e6a2ab-c412-4b1c-af09-2f61c0836c8e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=639295992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.639295992
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1434003760
Short name T1635
Test name
Test status
Simulation time 188457642 ps
CPU time 0.81 seconds
Started Jul 03 04:57:04 PM PDT 24
Finished Jul 03 04:57:05 PM PDT 24
Peak memory 206004 kb
Host smart-bd276373-0041-4712-842f-3dbf6fd77497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14340
03760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1434003760
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.649312192
Short name T1998
Test name
Test status
Simulation time 179155021 ps
CPU time 0.83 seconds
Started Jul 03 04:56:44 PM PDT 24
Finished Jul 03 04:56:45 PM PDT 24
Peak memory 206096 kb
Host smart-db5e3093-967c-46ad-91d8-4e171cfc275e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64931
2192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.649312192
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.185458566
Short name T609
Test name
Test status
Simulation time 878183932 ps
CPU time 2.11 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:56:56 PM PDT 24
Peak memory 206376 kb
Host smart-d599668a-9507-4be5-90b9-ebca2bd69873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18545
8566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.185458566
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.266892189
Short name T2649
Test name
Test status
Simulation time 3677835697 ps
CPU time 25.68 seconds
Started Jul 03 04:56:49 PM PDT 24
Finished Jul 03 04:57:15 PM PDT 24
Peak memory 206428 kb
Host smart-6381386e-61a0-4161-b806-b6ba55878a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26689
2189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.266892189
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.2920010813
Short name T1614
Test name
Test status
Simulation time 42368401 ps
CPU time 0.68 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:14 PM PDT 24
Peak memory 206160 kb
Host smart-923bb275-68c9-400d-a1d7-0748dfcba350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2920010813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.2920010813
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.448762207
Short name T480
Test name
Test status
Simulation time 3406394092 ps
CPU time 4.83 seconds
Started Jul 03 04:56:43 PM PDT 24
Finished Jul 03 04:56:49 PM PDT 24
Peak memory 206192 kb
Host smart-0caa350b-daf1-4926-9d8c-4d3304244be8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=448762207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.448762207
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.562252306
Short name T1039
Test name
Test status
Simulation time 13444245915 ps
CPU time 12.92 seconds
Started Jul 03 04:56:49 PM PDT 24
Finished Jul 03 04:57:02 PM PDT 24
Peak memory 206452 kb
Host smart-71f513ea-ad20-473e-93f3-068ce457c7ed
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=562252306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.562252306
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1302414531
Short name T2663
Test name
Test status
Simulation time 23348462792 ps
CPU time 22.62 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:57:38 PM PDT 24
Peak memory 206192 kb
Host smart-66fb4b1c-124c-479a-bd18-f30ad1f0f307
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1302414531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.1302414531
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.514547974
Short name T657
Test name
Test status
Simulation time 154485809 ps
CPU time 0.84 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:57:03 PM PDT 24
Peak memory 206040 kb
Host smart-65a461a6-4701-4737-8964-5dfc5e74ef6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51454
7974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.514547974
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1598379936
Short name T2642
Test name
Test status
Simulation time 153964011 ps
CPU time 0.8 seconds
Started Jul 03 04:56:56 PM PDT 24
Finished Jul 03 04:56:57 PM PDT 24
Peak memory 206096 kb
Host smart-a4bb756b-0111-42da-b5f0-898ce2555278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15983
79936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1598379936
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2410845134
Short name T939
Test name
Test status
Simulation time 201262593 ps
CPU time 0.87 seconds
Started Jul 03 04:57:03 PM PDT 24
Finished Jul 03 04:57:04 PM PDT 24
Peak memory 206092 kb
Host smart-bb88677c-9c98-4160-b8c1-e605c2233d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24108
45134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2410845134
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.4177004152
Short name T1788
Test name
Test status
Simulation time 899383616 ps
CPU time 1.96 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:57:17 PM PDT 24
Peak memory 206340 kb
Host smart-295c6251-018b-4497-8383-19c89c41972a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41770
04152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.4177004152
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3906496172
Short name T1826
Test name
Test status
Simulation time 11307788143 ps
CPU time 21.96 seconds
Started Jul 03 04:56:57 PM PDT 24
Finished Jul 03 04:57:19 PM PDT 24
Peak memory 206352 kb
Host smart-be0fb40e-8aec-4893-85e7-e746de853f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39064
96172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3906496172
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.4216773625
Short name T2072
Test name
Test status
Simulation time 493504454 ps
CPU time 1.67 seconds
Started Jul 03 04:57:03 PM PDT 24
Finished Jul 03 04:57:05 PM PDT 24
Peak memory 206112 kb
Host smart-d36d6541-c586-4a78-8267-f149d35c11ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42167
73625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.4216773625
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1328117650
Short name T53
Test name
Test status
Simulation time 140317141 ps
CPU time 0.76 seconds
Started Jul 03 04:56:58 PM PDT 24
Finished Jul 03 04:56:59 PM PDT 24
Peak memory 206132 kb
Host smart-3f0870ad-301b-4697-9a83-981bcb92a23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13281
17650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1328117650
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3030269442
Short name T370
Test name
Test status
Simulation time 36140528 ps
CPU time 0.65 seconds
Started Jul 03 04:56:53 PM PDT 24
Finished Jul 03 04:56:54 PM PDT 24
Peak memory 206056 kb
Host smart-9e4d04f1-e228-45f2-8f9a-07370645fd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
69442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3030269442
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.731763513
Short name T1572
Test name
Test status
Simulation time 881490167 ps
CPU time 2.18 seconds
Started Jul 03 04:56:49 PM PDT 24
Finished Jul 03 04:56:51 PM PDT 24
Peak memory 206332 kb
Host smart-ac915853-d14b-457b-8219-d585015fc368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73176
3513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.731763513
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2986148556
Short name T452
Test name
Test status
Simulation time 189060361 ps
CPU time 1.33 seconds
Started Jul 03 04:56:52 PM PDT 24
Finished Jul 03 04:56:54 PM PDT 24
Peak memory 206224 kb
Host smart-d070d593-9ec8-4e8e-bdee-1a8d9c336ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29861
48556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2986148556
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3434493778
Short name T2633
Test name
Test status
Simulation time 187152794 ps
CPU time 0.88 seconds
Started Jul 03 04:56:47 PM PDT 24
Finished Jul 03 04:56:49 PM PDT 24
Peak memory 206112 kb
Host smart-6feab51b-ca8c-447a-8e44-ca7da30f6cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34344
93778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3434493778
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3166932491
Short name T2391
Test name
Test status
Simulation time 136155964 ps
CPU time 0.73 seconds
Started Jul 03 04:57:06 PM PDT 24
Finished Jul 03 04:57:07 PM PDT 24
Peak memory 206140 kb
Host smart-f5c85b34-6f70-47bc-9283-7ff141aaf75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31669
32491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3166932491
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3967017510
Short name T458
Test name
Test status
Simulation time 262941189 ps
CPU time 0.96 seconds
Started Jul 03 04:56:51 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206080 kb
Host smart-e9599e39-93ae-4f0d-b1c7-0dd9869dfaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39670
17510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3967017510
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.3454665265
Short name T111
Test name
Test status
Simulation time 5641938824 ps
CPU time 37.83 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:57:32 PM PDT 24
Peak memory 206320 kb
Host smart-b4bd8bcb-d29e-4fc6-953e-f93e9e5b21c4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3454665265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.3454665265
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.546696863
Short name T1547
Test name
Test status
Simulation time 233873501 ps
CPU time 0.91 seconds
Started Jul 03 04:56:58 PM PDT 24
Finished Jul 03 04:57:00 PM PDT 24
Peak memory 206136 kb
Host smart-d0229640-8441-49e7-afa3-768443f395a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54669
6863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.546696863
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1915822534
Short name T1045
Test name
Test status
Simulation time 23291290890 ps
CPU time 23.49 seconds
Started Jul 03 04:57:01 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206196 kb
Host smart-9f0484a1-3daa-4208-bd38-0b692d9d91b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19158
22534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1915822534
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1177520406
Short name T2093
Test name
Test status
Simulation time 3351255688 ps
CPU time 3.75 seconds
Started Jul 03 04:56:58 PM PDT 24
Finished Jul 03 04:57:02 PM PDT 24
Peak memory 206168 kb
Host smart-5bd4a3a3-8a02-4ecd-af84-41b7836dbf86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11775
20406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1177520406
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3623728290
Short name T1380
Test name
Test status
Simulation time 9671314408 ps
CPU time 67.98 seconds
Started Jul 03 04:57:08 PM PDT 24
Finished Jul 03 04:58:16 PM PDT 24
Peak memory 206408 kb
Host smart-25804bd3-22fb-4020-b509-13fa3be64923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237
28290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3623728290
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.849934383
Short name T2560
Test name
Test status
Simulation time 4741416522 ps
CPU time 131.77 seconds
Started Jul 03 04:56:48 PM PDT 24
Finished Jul 03 04:59:00 PM PDT 24
Peak memory 206384 kb
Host smart-be983698-757c-45ab-a5d1-eac2c97bd180
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=849934383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.849934383
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.367658941
Short name T702
Test name
Test status
Simulation time 271839708 ps
CPU time 0.95 seconds
Started Jul 03 04:56:56 PM PDT 24
Finished Jul 03 04:56:57 PM PDT 24
Peak memory 206084 kb
Host smart-56557e84-9b4a-4230-853c-f7e699ed14c0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=367658941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.367658941
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2026853438
Short name T1127
Test name
Test status
Simulation time 189883819 ps
CPU time 0.88 seconds
Started Jul 03 04:57:04 PM PDT 24
Finished Jul 03 04:57:05 PM PDT 24
Peak memory 206072 kb
Host smart-47eabaf4-818c-47f5-80d5-17bf6e3cb4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20268
53438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2026853438
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.3697970581
Short name T1941
Test name
Test status
Simulation time 5654406212 ps
CPU time 156.23 seconds
Started Jul 03 04:57:10 PM PDT 24
Finished Jul 03 04:59:46 PM PDT 24
Peak memory 206392 kb
Host smart-6a3f14b4-b24d-49eb-8bb2-a28352780dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36979
70581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.3697970581
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.1893380819
Short name T2654
Test name
Test status
Simulation time 4645337285 ps
CPU time 130.29 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:59:13 PM PDT 24
Peak memory 206408 kb
Host smart-fbb60f1f-5a78-4904-9939-5c09ad8b42d6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1893380819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.1893380819
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.3711699073
Short name T2211
Test name
Test status
Simulation time 191059297 ps
CPU time 0.86 seconds
Started Jul 03 04:57:15 PM PDT 24
Finished Jul 03 04:57:17 PM PDT 24
Peak memory 206132 kb
Host smart-9ef8ec4e-519b-4ada-96e8-c5dc003013ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3711699073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.3711699073
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.415340612
Short name T2711
Test name
Test status
Simulation time 146033087 ps
CPU time 0.81 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206032 kb
Host smart-5558a63e-9867-4d2d-8d0a-43d03da9a5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41534
0612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.415340612
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.4246783177
Short name T149
Test name
Test status
Simulation time 248892968 ps
CPU time 0.89 seconds
Started Jul 03 04:57:10 PM PDT 24
Finished Jul 03 04:57:11 PM PDT 24
Peak memory 206088 kb
Host smart-24475306-0413-492b-86b5-ec1bcc476fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42467
83177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.4246783177
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2043283507
Short name T1602
Test name
Test status
Simulation time 170881107 ps
CPU time 0.81 seconds
Started Jul 03 04:56:51 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206080 kb
Host smart-66210be9-f180-4655-b6da-567c458e3d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20432
83507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2043283507
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.254461248
Short name T2052
Test name
Test status
Simulation time 242681328 ps
CPU time 0.84 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:56:56 PM PDT 24
Peak memory 206100 kb
Host smart-be3a1cea-902c-4fd0-9b09-e9db415124be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25446
1248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.254461248
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3077376335
Short name T2302
Test name
Test status
Simulation time 212286129 ps
CPU time 0.82 seconds
Started Jul 03 04:57:19 PM PDT 24
Finished Jul 03 04:57:21 PM PDT 24
Peak memory 206076 kb
Host smart-857e3ad1-b73b-40f2-9f9e-9f1b59dd96a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30773
76335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3077376335
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2930776016
Short name T2512
Test name
Test status
Simulation time 166423996 ps
CPU time 0.83 seconds
Started Jul 03 04:56:56 PM PDT 24
Finished Jul 03 04:56:57 PM PDT 24
Peak memory 206044 kb
Host smart-7ff5ab7d-0922-4237-88e2-5dd557ae0ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29307
76016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2930776016
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.4197816212
Short name T2420
Test name
Test status
Simulation time 272074338 ps
CPU time 0.95 seconds
Started Jul 03 04:57:33 PM PDT 24
Finished Jul 03 04:57:34 PM PDT 24
Peak memory 206004 kb
Host smart-0b236931-5f29-43bd-a016-8e50852314ad
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4197816212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.4197816212
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1188207568
Short name T853
Test name
Test status
Simulation time 149729078 ps
CPU time 0.76 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:14 PM PDT 24
Peak memory 206092 kb
Host smart-2faf3e70-0fcd-45c0-82de-55c80d6a5272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11882
07568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1188207568
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2901315693
Short name T2472
Test name
Test status
Simulation time 77480700 ps
CPU time 0.7 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:20 PM PDT 24
Peak memory 206068 kb
Host smart-e8af0110-d8c3-4836-957c-a311ffa88a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29013
15693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2901315693
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1693103804
Short name T271
Test name
Test status
Simulation time 17316205664 ps
CPU time 36.95 seconds
Started Jul 03 04:57:03 PM PDT 24
Finished Jul 03 04:57:40 PM PDT 24
Peak memory 206420 kb
Host smart-ca7a2224-3b42-4299-9fb6-54216c30d2f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16931
03804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1693103804
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2768582420
Short name T1905
Test name
Test status
Simulation time 163728074 ps
CPU time 0.79 seconds
Started Jul 03 04:57:12 PM PDT 24
Finished Jul 03 04:57:13 PM PDT 24
Peak memory 206088 kb
Host smart-5e9ba273-97ca-4dc4-a656-39e83bbd0b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27685
82420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2768582420
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2423650773
Short name T1395
Test name
Test status
Simulation time 212123545 ps
CPU time 0.93 seconds
Started Jul 03 04:56:52 PM PDT 24
Finished Jul 03 04:56:53 PM PDT 24
Peak memory 206144 kb
Host smart-af46729d-828d-45a8-8fa1-8d08d367ad72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24236
50773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2423650773
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.4090909519
Short name T1670
Test name
Test status
Simulation time 176360825 ps
CPU time 0.84 seconds
Started Jul 03 04:57:19 PM PDT 24
Finished Jul 03 04:57:21 PM PDT 24
Peak memory 206132 kb
Host smart-924da10e-38d4-43b1-9e4c-0d4b5b056854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40909
09519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.4090909519
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.1839089816
Short name T789
Test name
Test status
Simulation time 156317561 ps
CPU time 0.82 seconds
Started Jul 03 04:56:53 PM PDT 24
Finished Jul 03 04:56:55 PM PDT 24
Peak memory 206088 kb
Host smart-b3f2c02b-b488-48f2-a336-8a878f27c24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18390
89816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.1839089816
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1399704677
Short name T808
Test name
Test status
Simulation time 197056545 ps
CPU time 0.82 seconds
Started Jul 03 04:56:51 PM PDT 24
Finished Jul 03 04:56:53 PM PDT 24
Peak memory 206128 kb
Host smart-36cafe18-cc9e-4a1d-82c7-71caec07da60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13997
04677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1399704677
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.199623208
Short name T1831
Test name
Test status
Simulation time 156884728 ps
CPU time 0.73 seconds
Started Jul 03 04:56:51 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206112 kb
Host smart-c4a4b0c1-3151-4760-89c6-a3cf1e1d19bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19962
3208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.199623208
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1050095966
Short name T1449
Test name
Test status
Simulation time 144838769 ps
CPU time 0.77 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:14 PM PDT 24
Peak memory 206088 kb
Host smart-6e9e9981-8542-4933-9793-0c139e8d822e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10500
95966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1050095966
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1314346001
Short name T2361
Test name
Test status
Simulation time 217459337 ps
CPU time 0.88 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:56:55 PM PDT 24
Peak memory 206072 kb
Host smart-332a1682-791e-4705-8656-a2c4f1ce4b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13143
46001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1314346001
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.42097496
Short name T1012
Test name
Test status
Simulation time 6240735012 ps
CPU time 44.84 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:57:36 PM PDT 24
Peak memory 206276 kb
Host smart-e9819606-ca32-468c-bdff-105c75e8da64
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=42097496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.42097496
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3739044216
Short name T1712
Test name
Test status
Simulation time 200846802 ps
CPU time 0.84 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:56:55 PM PDT 24
Peak memory 206096 kb
Host smart-9f1776d3-d2d4-4e9a-ba6c-4f589689451c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37390
44216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3739044216
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3861336752
Short name T1859
Test name
Test status
Simulation time 167462733 ps
CPU time 0.83 seconds
Started Jul 03 04:56:50 PM PDT 24
Finished Jul 03 04:56:52 PM PDT 24
Peak memory 206100 kb
Host smart-58c63aa3-6d9b-4295-b4fd-233eba5e25c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38613
36752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3861336752
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1526755295
Short name T1767
Test name
Test status
Simulation time 1158297581 ps
CPU time 2.59 seconds
Started Jul 03 04:57:09 PM PDT 24
Finished Jul 03 04:57:11 PM PDT 24
Peak memory 206240 kb
Host smart-ad8239b5-827e-469e-88a2-670c8d1d8d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15267
55295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1526755295
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1471775321
Short name T1562
Test name
Test status
Simulation time 5223728470 ps
CPU time 36.5 seconds
Started Jul 03 04:56:54 PM PDT 24
Finished Jul 03 04:57:31 PM PDT 24
Peak memory 206360 kb
Host smart-dc7d4628-f12a-4997-b81c-13c9e84f4b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14717
75321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1471775321
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.2257041262
Short name T1556
Test name
Test status
Simulation time 54732500 ps
CPU time 0.69 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:18 PM PDT 24
Peak memory 206164 kb
Host smart-41fd8bfa-86ec-491c-84f5-0bd433e65c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2257041262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2257041262
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2928679636
Short name T1512
Test name
Test status
Simulation time 3468283981 ps
CPU time 3.98 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:17 PM PDT 24
Peak memory 206432 kb
Host smart-445fa708-4a65-4104-b3df-52229a37a15c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2928679636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2928679636
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.711134847
Short name T946
Test name
Test status
Simulation time 13434697956 ps
CPU time 12.43 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:31 PM PDT 24
Peak memory 206160 kb
Host smart-69fc6495-3ec1-44f8-bf2a-ee44e0093919
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=711134847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.711134847
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3331690723
Short name T2503
Test name
Test status
Simulation time 23364226119 ps
CPU time 25.59 seconds
Started Jul 03 04:56:57 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206396 kb
Host smart-c29bfea9-2b11-43e0-ac30-0717ffc53cfc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3331690723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.3331690723
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1469936282
Short name T2445
Test name
Test status
Simulation time 186583785 ps
CPU time 0.78 seconds
Started Jul 03 04:57:22 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206132 kb
Host smart-93d20d67-212e-4e74-8926-ea5efb90bbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14699
36282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1469936282
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2578667248
Short name T1333
Test name
Test status
Simulation time 188594543 ps
CPU time 0.81 seconds
Started Jul 03 04:56:56 PM PDT 24
Finished Jul 03 04:56:57 PM PDT 24
Peak memory 206044 kb
Host smart-6a82c160-c34e-49a2-8709-51df5058b5b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25786
67248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2578667248
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.1444015410
Short name T975
Test name
Test status
Simulation time 283081858 ps
CPU time 1.03 seconds
Started Jul 03 04:57:07 PM PDT 24
Finished Jul 03 04:57:09 PM PDT 24
Peak memory 206132 kb
Host smart-816ecd87-8ef0-40cd-a043-f347245f2820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14440
15410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1444015410
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_device_address.4227882590
Short name T392
Test name
Test status
Simulation time 14699993581 ps
CPU time 27.95 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:47 PM PDT 24
Peak memory 206276 kb
Host smart-a9137db4-117a-4f51-9ad8-f5a94a17bf14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42278
82590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.4227882590
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2370213614
Short name T925
Test name
Test status
Simulation time 315271464 ps
CPU time 1.11 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:57:16 PM PDT 24
Peak memory 206116 kb
Host smart-47e5dc2a-c321-4a60-9c63-c3dd5338bf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23702
13614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2370213614
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.531677027
Short name T576
Test name
Test status
Simulation time 183719772 ps
CPU time 0.79 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:57:15 PM PDT 24
Peak memory 206132 kb
Host smart-6dea0f3d-2e4f-4ae7-b48b-337ae60f08ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53167
7027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.531677027
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.4031414134
Short name T719
Test name
Test status
Simulation time 32089365 ps
CPU time 0.63 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:57:16 PM PDT 24
Peak memory 206104 kb
Host smart-8ec3fd0a-0b1c-482d-97b7-fa3e79b54dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40314
14134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.4031414134
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.121872401
Short name T2366
Test name
Test status
Simulation time 843133648 ps
CPU time 2.03 seconds
Started Jul 03 04:57:09 PM PDT 24
Finished Jul 03 04:57:12 PM PDT 24
Peak memory 206304 kb
Host smart-97e0395b-6d3a-494d-aad4-bb1d610da5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12187
2401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.121872401
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1981147334
Short name T506
Test name
Test status
Simulation time 215051752 ps
CPU time 1.46 seconds
Started Jul 03 04:57:03 PM PDT 24
Finished Jul 03 04:57:05 PM PDT 24
Peak memory 206328 kb
Host smart-f4baefd6-fa5a-4019-81cb-00e7ac7156ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19811
47334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1981147334
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1724877014
Short name T1117
Test name
Test status
Simulation time 202343955 ps
CPU time 0.88 seconds
Started Jul 03 04:57:01 PM PDT 24
Finished Jul 03 04:57:02 PM PDT 24
Peak memory 206064 kb
Host smart-a07dbb09-4df4-4378-9420-7b9dc644255a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
77014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1724877014
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1695953061
Short name T16
Test name
Test status
Simulation time 140386862 ps
CPU time 0.86 seconds
Started Jul 03 04:56:56 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206140 kb
Host smart-3c42caa1-fb73-4901-9dc6-1c455514b923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16959
53061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1695953061
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2625949757
Short name T476
Test name
Test status
Simulation time 224853908 ps
CPU time 0.88 seconds
Started Jul 03 04:56:53 PM PDT 24
Finished Jul 03 04:56:54 PM PDT 24
Peak memory 206112 kb
Host smart-59fdfeca-96a0-4a5d-bdfa-ce0579a7efd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26259
49757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2625949757
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1583562834
Short name T1816
Test name
Test status
Simulation time 4974267720 ps
CPU time 46.22 seconds
Started Jul 03 04:57:16 PM PDT 24
Finished Jul 03 04:58:02 PM PDT 24
Peak memory 206380 kb
Host smart-12c7246e-99da-43eb-987c-838b2e320cce
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1583562834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1583562834
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1987005230
Short name T886
Test name
Test status
Simulation time 250689509 ps
CPU time 0.98 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:14 PM PDT 24
Peak memory 206132 kb
Host smart-34af0044-1b04-473a-880b-cf57aa1245cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19870
05230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1987005230
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3070693561
Short name T2634
Test name
Test status
Simulation time 23419377800 ps
CPU time 26.36 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:44 PM PDT 24
Peak memory 206160 kb
Host smart-dbaa1f2a-c107-4162-bd2b-cdd20ab91439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30706
93561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3070693561
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1318494309
Short name T1510
Test name
Test status
Simulation time 3294840856 ps
CPU time 3.7 seconds
Started Jul 03 04:57:01 PM PDT 24
Finished Jul 03 04:57:05 PM PDT 24
Peak memory 206160 kb
Host smart-578bce9c-9938-4888-805d-9c5aa848d5ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13184
94309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1318494309
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.2920261788
Short name T2171
Test name
Test status
Simulation time 11310733136 ps
CPU time 100.54 seconds
Started Jul 03 04:57:16 PM PDT 24
Finished Jul 03 04:58:57 PM PDT 24
Peak memory 206456 kb
Host smart-44b4c9d1-e504-46ce-8109-5b4477ec1e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29202
61788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2920261788
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.2219012474
Short name T956
Test name
Test status
Simulation time 7815237269 ps
CPU time 57.51 seconds
Started Jul 03 04:56:58 PM PDT 24
Finished Jul 03 04:57:56 PM PDT 24
Peak memory 206436 kb
Host smart-bfb7e2f8-f7be-4720-be00-4a7f048a87d5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2219012474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.2219012474
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.35061233
Short name T1726
Test name
Test status
Simulation time 244789302 ps
CPU time 0.92 seconds
Started Jul 03 04:57:07 PM PDT 24
Finished Jul 03 04:57:08 PM PDT 24
Peak memory 206132 kb
Host smart-0424b77f-c7af-44dd-b630-483eea212b39
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=35061233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.35061233
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1743487076
Short name T2481
Test name
Test status
Simulation time 195389642 ps
CPU time 0.87 seconds
Started Jul 03 04:57:07 PM PDT 24
Finished Jul 03 04:57:08 PM PDT 24
Peak memory 206076 kb
Host smart-dfc0c4a6-8001-40e4-9ff1-acda1d72a5c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17434
87076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1743487076
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3683870333
Short name T765
Test name
Test status
Simulation time 6068975864 ps
CPU time 57.72 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:58:00 PM PDT 24
Peak memory 206356 kb
Host smart-56fa818e-e816-4342-abdf-f5da52661935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36838
70333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3683870333
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.707541408
Short name T2273
Test name
Test status
Simulation time 4001280105 ps
CPU time 36.29 seconds
Started Jul 03 04:57:09 PM PDT 24
Finished Jul 03 04:57:46 PM PDT 24
Peak memory 206348 kb
Host smart-69b23b77-f3cd-4878-9a99-c0039e6b8474
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=707541408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.707541408
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2308935956
Short name T1952
Test name
Test status
Simulation time 150079821 ps
CPU time 0.77 seconds
Started Jul 03 04:56:55 PM PDT 24
Finished Jul 03 04:56:56 PM PDT 24
Peak memory 206140 kb
Host smart-b823fbea-360c-44a2-9524-5999e6213709
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2308935956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2308935956
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.724583556
Short name T1150
Test name
Test status
Simulation time 165700838 ps
CPU time 0.76 seconds
Started Jul 03 04:56:57 PM PDT 24
Finished Jul 03 04:56:59 PM PDT 24
Peak memory 206052 kb
Host smart-2966591c-d727-4bd7-bb96-d0cda5d83ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72458
3556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.724583556
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1706880308
Short name T134
Test name
Test status
Simulation time 212293074 ps
CPU time 0.89 seconds
Started Jul 03 04:56:59 PM PDT 24
Finished Jul 03 04:57:00 PM PDT 24
Peak memory 206132 kb
Host smart-09c0f9f9-1913-4073-88bf-5d7cf77ee073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17068
80308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1706880308
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.1480111634
Short name T467
Test name
Test status
Simulation time 181557146 ps
CPU time 0.83 seconds
Started Jul 03 04:57:16 PM PDT 24
Finished Jul 03 04:57:18 PM PDT 24
Peak memory 206088 kb
Host smart-d6c564ad-27e8-434b-810e-5431098e8a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14801
11634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.1480111634
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.4045742101
Short name T697
Test name
Test status
Simulation time 146090939 ps
CPU time 0.79 seconds
Started Jul 03 04:57:03 PM PDT 24
Finished Jul 03 04:57:04 PM PDT 24
Peak memory 206108 kb
Host smart-f652c1e1-70f3-40ea-bcfa-55febf3d8348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40457
42101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.4045742101
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1806322487
Short name T2285
Test name
Test status
Simulation time 239561156 ps
CPU time 0.86 seconds
Started Jul 03 04:57:00 PM PDT 24
Finished Jul 03 04:57:01 PM PDT 24
Peak memory 206084 kb
Host smart-c23fa16b-a5d3-413a-9e25-02a86e9974ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18063
22487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1806322487
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1345254862
Short name T198
Test name
Test status
Simulation time 151624277 ps
CPU time 0.78 seconds
Started Jul 03 04:57:16 PM PDT 24
Finished Jul 03 04:57:18 PM PDT 24
Peak memory 206068 kb
Host smart-7c6ba566-e2cc-4ab6-ba1e-65eb1979e70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13452
54862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1345254862
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1312343102
Short name T1386
Test name
Test status
Simulation time 264439561 ps
CPU time 0.98 seconds
Started Jul 03 04:56:59 PM PDT 24
Finished Jul 03 04:57:00 PM PDT 24
Peak memory 206100 kb
Host smart-11216a13-5c89-421b-b4ab-68222d272760
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1312343102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1312343102
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.2609845838
Short name T1142
Test name
Test status
Simulation time 141594922 ps
CPU time 0.76 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:15 PM PDT 24
Peak memory 206116 kb
Host smart-debd49c4-e3af-4a9f-8d3e-f186ed1befc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26098
45838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2609845838
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.965315004
Short name T1186
Test name
Test status
Simulation time 50655454 ps
CPU time 0.66 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:57:15 PM PDT 24
Peak memory 206092 kb
Host smart-d0799446-172c-4adb-8504-c5806f6a2f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96531
5004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.965315004
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1419992049
Short name T1366
Test name
Test status
Simulation time 16314090518 ps
CPU time 35.54 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:57:50 PM PDT 24
Peak memory 206400 kb
Host smart-3ce52465-f637-4ee7-b07f-a8e39d88b123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14199
92049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1419992049
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.4190459065
Short name T1202
Test name
Test status
Simulation time 185813091 ps
CPU time 0.89 seconds
Started Jul 03 04:57:00 PM PDT 24
Finished Jul 03 04:57:01 PM PDT 24
Peak memory 206004 kb
Host smart-77af8e12-737b-45a6-b57c-136b467213f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41904
59065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.4190459065
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3515048882
Short name T2261
Test name
Test status
Simulation time 228862338 ps
CPU time 0.88 seconds
Started Jul 03 04:56:59 PM PDT 24
Finished Jul 03 04:57:00 PM PDT 24
Peak memory 206088 kb
Host smart-ddcee67b-1857-491a-91ac-8dfe0821b3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35150
48882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3515048882
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1543301559
Short name T1069
Test name
Test status
Simulation time 204393563 ps
CPU time 0.87 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:19 PM PDT 24
Peak memory 206104 kb
Host smart-f21b22da-ebfb-4383-b81d-a8fd0661147b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15433
01559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1543301559
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.2310681535
Short name T2410
Test name
Test status
Simulation time 202314651 ps
CPU time 0.86 seconds
Started Jul 03 04:57:11 PM PDT 24
Finished Jul 03 04:57:12 PM PDT 24
Peak memory 206104 kb
Host smart-72074fcd-54e5-4699-94d8-8f50e811b3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23106
81535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.2310681535
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3994337968
Short name T104
Test name
Test status
Simulation time 144509793 ps
CPU time 0.79 seconds
Started Jul 03 04:57:06 PM PDT 24
Finished Jul 03 04:57:08 PM PDT 24
Peak memory 206128 kb
Host smart-c083acec-9448-45aa-83da-0c001070a922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39943
37968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3994337968
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1466961866
Short name T477
Test name
Test status
Simulation time 235362526 ps
CPU time 0.83 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:57:16 PM PDT 24
Peak memory 206088 kb
Host smart-6db3d775-d6a0-465d-bf23-2fa4551d27a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14669
61866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1466961866
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.501994233
Short name T807
Test name
Test status
Simulation time 158963353 ps
CPU time 0.77 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:15 PM PDT 24
Peak memory 206088 kb
Host smart-5322adbe-e015-49cd-9766-a47ca68c2359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50199
4233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.501994233
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3226091050
Short name T1763
Test name
Test status
Simulation time 234996701 ps
CPU time 0.92 seconds
Started Jul 03 04:57:15 PM PDT 24
Finished Jul 03 04:57:17 PM PDT 24
Peak memory 206104 kb
Host smart-a210d380-c53b-42df-b220-405c5f3f600f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32260
91050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3226091050
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1892515005
Short name T1188
Test name
Test status
Simulation time 5378119484 ps
CPU time 149.43 seconds
Started Jul 03 04:57:03 PM PDT 24
Finished Jul 03 04:59:33 PM PDT 24
Peak memory 206428 kb
Host smart-7e5f292a-0995-4f00-840d-e65651e629e2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1892515005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1892515005
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3832006711
Short name T852
Test name
Test status
Simulation time 173450335 ps
CPU time 0.81 seconds
Started Jul 03 04:57:09 PM PDT 24
Finished Jul 03 04:57:11 PM PDT 24
Peak memory 206092 kb
Host smart-a9e9c273-4618-4da2-a775-1c1046fbfa5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38320
06711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3832006711
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1557894723
Short name T1254
Test name
Test status
Simulation time 176477948 ps
CPU time 0.8 seconds
Started Jul 03 04:57:06 PM PDT 24
Finished Jul 03 04:57:07 PM PDT 24
Peak memory 206056 kb
Host smart-9a22bcf2-d13e-4ee2-bb50-a9ef27a5a438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15578
94723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1557894723
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2217321092
Short name T612
Test name
Test status
Simulation time 572625461 ps
CPU time 1.5 seconds
Started Jul 03 04:57:11 PM PDT 24
Finished Jul 03 04:57:13 PM PDT 24
Peak memory 205976 kb
Host smart-b0ac2608-1bcb-46a3-805b-b3e149034243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22173
21092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2217321092
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2723816690
Short name T1111
Test name
Test status
Simulation time 4822107360 ps
CPU time 46.48 seconds
Started Jul 03 04:57:03 PM PDT 24
Finished Jul 03 04:57:50 PM PDT 24
Peak memory 206284 kb
Host smart-1eee0bea-0553-4978-a21a-52c0b3beb6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27238
16690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2723816690
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3121414129
Short name T488
Test name
Test status
Simulation time 33910330 ps
CPU time 0.68 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:19 PM PDT 24
Peak memory 206192 kb
Host smart-d0645857-98cb-48e6-954a-9e3b298a3854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3121414129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3121414129
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1005150050
Short name T496
Test name
Test status
Simulation time 4090760545 ps
CPU time 5.92 seconds
Started Jul 03 04:57:01 PM PDT 24
Finished Jul 03 04:57:07 PM PDT 24
Peak memory 206392 kb
Host smart-91024933-4fd7-459d-ace9-764f03d8d4f1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1005150050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.1005150050
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1984011649
Short name T2451
Test name
Test status
Simulation time 13376616830 ps
CPU time 13.66 seconds
Started Jul 03 04:57:16 PM PDT 24
Finished Jul 03 04:57:30 PM PDT 24
Peak memory 206172 kb
Host smart-92fe2234-d435-47a7-8dce-a7d6669e7acf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1984011649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1984011649
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1463738291
Short name T534
Test name
Test status
Simulation time 23395788058 ps
CPU time 21.63 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:40 PM PDT 24
Peak memory 206344 kb
Host smart-03387916-fcc5-439e-b589-ee7f97eda5bd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1463738291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.1463738291
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.669397681
Short name T1313
Test name
Test status
Simulation time 143318916 ps
CPU time 0.78 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:57:03 PM PDT 24
Peak memory 205968 kb
Host smart-b4112144-cac4-4c81-8a39-075c7e4fc7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66939
7681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.669397681
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2821127488
Short name T2280
Test name
Test status
Simulation time 198135442 ps
CPU time 0.86 seconds
Started Jul 03 04:57:09 PM PDT 24
Finished Jul 03 04:57:11 PM PDT 24
Peak memory 206052 kb
Host smart-e732f224-28a2-4837-a162-70ff89d79efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28211
27488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2821127488
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2732515696
Short name T1676
Test name
Test status
Simulation time 533672575 ps
CPU time 1.48 seconds
Started Jul 03 04:57:30 PM PDT 24
Finished Jul 03 04:57:32 PM PDT 24
Peak memory 206108 kb
Host smart-a40ba4d0-396c-4cc2-80da-b1d1445da8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27325
15696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2732515696
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1529322013
Short name T183
Test name
Test status
Simulation time 1361641844 ps
CPU time 2.82 seconds
Started Jul 03 04:56:59 PM PDT 24
Finished Jul 03 04:57:02 PM PDT 24
Peak memory 206336 kb
Host smart-1b5e3fe3-7c68-4f03-a4a9-dcb93d2b3ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15293
22013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1529322013
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.1654783626
Short name T175
Test name
Test status
Simulation time 22741648275 ps
CPU time 46.02 seconds
Started Jul 03 04:57:40 PM PDT 24
Finished Jul 03 04:58:26 PM PDT 24
Peak memory 206420 kb
Host smart-3efe5613-c4bf-4cc4-9a7d-33952a7caa00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16547
83626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1654783626
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.1509815155
Short name T2380
Test name
Test status
Simulation time 458419050 ps
CPU time 1.32 seconds
Started Jul 03 04:57:21 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206084 kb
Host smart-a752e434-f468-474c-9100-5e74c0903539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15098
15155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.1509815155
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.700590134
Short name T1440
Test name
Test status
Simulation time 157859115 ps
CPU time 0.74 seconds
Started Jul 03 04:57:15 PM PDT 24
Finished Jul 03 04:57:16 PM PDT 24
Peak memory 206088 kb
Host smart-d3221ac6-7525-42b0-9858-496741aebc21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70059
0134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.700590134
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.852464994
Short name T2705
Test name
Test status
Simulation time 74294417 ps
CPU time 0.69 seconds
Started Jul 03 04:57:08 PM PDT 24
Finished Jul 03 04:57:09 PM PDT 24
Peak memory 206108 kb
Host smart-495dc6d3-958f-4014-9833-042eb899425d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85246
4994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.852464994
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.4050838108
Short name T815
Test name
Test status
Simulation time 1156612557 ps
CPU time 2.59 seconds
Started Jul 03 04:57:03 PM PDT 24
Finished Jul 03 04:57:06 PM PDT 24
Peak memory 206340 kb
Host smart-b3e59946-d5ca-4a65-a231-85be12714443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40508
38108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.4050838108
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3759773938
Short name T1291
Test name
Test status
Simulation time 161868593 ps
CPU time 1.31 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:57:04 PM PDT 24
Peak memory 206308 kb
Host smart-3b9635e4-1dd4-499e-af87-d3ec9c7e2c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37597
73938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3759773938
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.1969843409
Short name T1358
Test name
Test status
Simulation time 196937102 ps
CPU time 0.83 seconds
Started Jul 03 04:57:23 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206108 kb
Host smart-bae9dd89-2a5e-403e-a1c0-fda36b7062c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19698
43409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.1969843409
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2232076902
Short name T1698
Test name
Test status
Simulation time 140414267 ps
CPU time 0.77 seconds
Started Jul 03 04:57:19 PM PDT 24
Finished Jul 03 04:57:21 PM PDT 24
Peak memory 206084 kb
Host smart-f858dc7a-dfd4-4fd7-9a64-9bf1b8c39519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22320
76902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2232076902
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.816554906
Short name T953
Test name
Test status
Simulation time 168841833 ps
CPU time 0.81 seconds
Started Jul 03 04:57:05 PM PDT 24
Finished Jul 03 04:57:06 PM PDT 24
Peak memory 206116 kb
Host smart-7c0ced8d-c3d3-4dec-a1a9-5c9399e913bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81655
4906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.816554906
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.3726235678
Short name T2151
Test name
Test status
Simulation time 6073141064 ps
CPU time 161.92 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:59:57 PM PDT 24
Peak memory 206432 kb
Host smart-266e8cc4-67b8-4d9b-ad96-7cf18d8fd48a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3726235678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.3726235678
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3945594082
Short name T951
Test name
Test status
Simulation time 283495874 ps
CPU time 1.03 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:20 PM PDT 24
Peak memory 206112 kb
Host smart-4f95345e-b8ad-46da-a353-747dbf05ed1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39455
94082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3945594082
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.321979066
Short name T898
Test name
Test status
Simulation time 23303246035 ps
CPU time 25.77 seconds
Started Jul 03 04:57:12 PM PDT 24
Finished Jul 03 04:57:38 PM PDT 24
Peak memory 206196 kb
Host smart-36371f3b-2fb1-4976-8c35-c958c3b6d44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32197
9066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.321979066
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.479192506
Short name T591
Test name
Test status
Simulation time 3321787028 ps
CPU time 5.06 seconds
Started Jul 03 04:57:10 PM PDT 24
Finished Jul 03 04:57:16 PM PDT 24
Peak memory 206180 kb
Host smart-d6081465-ca91-4820-aaeb-75fdb676c5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47919
2506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.479192506
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1584874779
Short name T1038
Test name
Test status
Simulation time 6589261841 ps
CPU time 174.73 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 05:00:14 PM PDT 24
Peak memory 206428 kb
Host smart-23b558fc-4c6b-4f71-969a-d49138528e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15848
74779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1584874779
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.1836415787
Short name T412
Test name
Test status
Simulation time 4608833778 ps
CPU time 126.74 seconds
Started Jul 03 04:57:05 PM PDT 24
Finished Jul 03 04:59:12 PM PDT 24
Peak memory 206332 kb
Host smart-b65c5d77-4bb1-4509-83c8-94ec51c23b6a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1836415787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.1836415787
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3462521617
Short name T2017
Test name
Test status
Simulation time 285046482 ps
CPU time 0.95 seconds
Started Jul 03 04:57:10 PM PDT 24
Finished Jul 03 04:57:11 PM PDT 24
Peak memory 206052 kb
Host smart-88a52f45-1b39-4a57-ae43-d6a3f3c98efa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3462521617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3462521617
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.179376111
Short name T2222
Test name
Test status
Simulation time 195137952 ps
CPU time 0.89 seconds
Started Jul 03 04:57:11 PM PDT 24
Finished Jul 03 04:57:13 PM PDT 24
Peak memory 206096 kb
Host smart-4bfbae9b-77c1-4910-b908-4268422a0126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17937
6111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.179376111
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.2445942132
Short name T446
Test name
Test status
Simulation time 4757183746 ps
CPU time 33.08 seconds
Started Jul 03 04:57:15 PM PDT 24
Finished Jul 03 04:57:49 PM PDT 24
Peak memory 206448 kb
Host smart-b8f99cf4-d832-4a82-bce3-a750d9a8b421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24459
42132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.2445942132
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.1826184535
Short name T690
Test name
Test status
Simulation time 8007456985 ps
CPU time 76.99 seconds
Started Jul 03 04:57:19 PM PDT 24
Finished Jul 03 04:58:38 PM PDT 24
Peak memory 206384 kb
Host smart-567e860d-320b-4994-a445-6067162f6c59
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1826184535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1826184535
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1673804825
Short name T29
Test name
Test status
Simulation time 163010552 ps
CPU time 0.83 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:57:15 PM PDT 24
Peak memory 206128 kb
Host smart-13ea0e0b-9380-4c00-96b4-7b25ac4573a5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1673804825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1673804825
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3864988166
Short name T332
Test name
Test status
Simulation time 152327656 ps
CPU time 0.81 seconds
Started Jul 03 04:57:20 PM PDT 24
Finished Jul 03 04:57:22 PM PDT 24
Peak memory 206108 kb
Host smart-8d7f5f72-b21b-4e04-8e0b-f32677b4813a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38649
88166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3864988166
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3511842887
Short name T1969
Test name
Test status
Simulation time 242449688 ps
CPU time 0.88 seconds
Started Jul 03 04:57:11 PM PDT 24
Finished Jul 03 04:57:12 PM PDT 24
Peak memory 206128 kb
Host smart-680e7910-317b-439d-968a-426fd382ce9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35118
42887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3511842887
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.4278969654
Short name T1417
Test name
Test status
Simulation time 175521723 ps
CPU time 0.81 seconds
Started Jul 03 04:57:25 PM PDT 24
Finished Jul 03 04:57:27 PM PDT 24
Peak memory 206096 kb
Host smart-be67f309-0d3a-4c6a-9dc1-8664cfb0eb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42789
69654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.4278969654
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2039781592
Short name T2397
Test name
Test status
Simulation time 160935690 ps
CPU time 0.76 seconds
Started Jul 03 04:57:48 PM PDT 24
Finished Jul 03 04:57:49 PM PDT 24
Peak memory 206084 kb
Host smart-2bd0c2b8-b94e-4e2d-9ac4-cac671cf24c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20397
81592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2039781592
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3958905168
Short name T590
Test name
Test status
Simulation time 160589068 ps
CPU time 0.83 seconds
Started Jul 03 04:57:03 PM PDT 24
Finished Jul 03 04:57:04 PM PDT 24
Peak memory 206108 kb
Host smart-1acfd92d-4f3e-4d35-b941-531d96b5d684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39589
05168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3958905168
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1708324554
Short name T1729
Test name
Test status
Simulation time 156236480 ps
CPU time 0.81 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:20 PM PDT 24
Peak memory 206108 kb
Host smart-85bb2015-7668-4f8d-a7e1-2a86b2d64a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17083
24554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1708324554
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.335239927
Short name T2227
Test name
Test status
Simulation time 181371850 ps
CPU time 0.85 seconds
Started Jul 03 04:57:09 PM PDT 24
Finished Jul 03 04:57:10 PM PDT 24
Peak memory 206144 kb
Host smart-8b1363fd-3fb0-4eeb-8072-459a94815bc6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=335239927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.335239927
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3030265077
Short name T2505
Test name
Test status
Simulation time 142449418 ps
CPU time 0.75 seconds
Started Jul 03 04:57:10 PM PDT 24
Finished Jul 03 04:57:11 PM PDT 24
Peak memory 206108 kb
Host smart-5b1534b1-1ea5-46d4-b095-28c75b9cc044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
65077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3030265077
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.287934543
Short name T1227
Test name
Test status
Simulation time 77765737 ps
CPU time 0.72 seconds
Started Jul 03 04:57:22 PM PDT 24
Finished Jul 03 04:57:24 PM PDT 24
Peak memory 206120 kb
Host smart-f80a6c8d-e622-457e-bf90-071ebac08611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28793
4543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.287934543
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3404412465
Short name T272
Test name
Test status
Simulation time 14238525677 ps
CPU time 32.49 seconds
Started Jul 03 04:57:16 PM PDT 24
Finished Jul 03 04:57:50 PM PDT 24
Peak memory 206388 kb
Host smart-6265de29-f5e5-4ebc-9c21-51241d448b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34044
12465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3404412465
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2365881158
Short name T851
Test name
Test status
Simulation time 188535627 ps
CPU time 0.85 seconds
Started Jul 03 04:57:06 PM PDT 24
Finished Jul 03 04:57:07 PM PDT 24
Peak memory 206052 kb
Host smart-2df99b36-5d68-4417-b4e8-d45ed47943ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23658
81158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2365881158
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.394884928
Short name T1927
Test name
Test status
Simulation time 175066771 ps
CPU time 0.87 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:21 PM PDT 24
Peak memory 206132 kb
Host smart-80e14126-1b45-45a2-8124-7b8c10efb79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39488
4928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.394884928
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3900136644
Short name T1329
Test name
Test status
Simulation time 239767563 ps
CPU time 0.9 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:18 PM PDT 24
Peak memory 206136 kb
Host smart-360b6600-3831-47b9-87a5-011206d63499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39001
36644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3900136644
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.451671007
Short name T1281
Test name
Test status
Simulation time 167860757 ps
CPU time 0.82 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:18 PM PDT 24
Peak memory 206108 kb
Host smart-02760038-09ff-47e2-a147-bc7cb4563ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45167
1007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.451671007
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.436082252
Short name T871
Test name
Test status
Simulation time 208255755 ps
CPU time 0.86 seconds
Started Jul 03 04:57:20 PM PDT 24
Finished Jul 03 04:57:22 PM PDT 24
Peak memory 206116 kb
Host smart-ce703df0-a344-4d97-98da-a306cb505fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43608
2252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.436082252
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1346795000
Short name T1050
Test name
Test status
Simulation time 210951142 ps
CPU time 0.77 seconds
Started Jul 03 04:57:23 PM PDT 24
Finished Jul 03 04:57:24 PM PDT 24
Peak memory 206088 kb
Host smart-1e1c65c0-c658-416e-9bdf-4deb36bf7200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13467
95000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1346795000
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1053708667
Short name T1171
Test name
Test status
Simulation time 191029095 ps
CPU time 0.8 seconds
Started Jul 03 04:57:15 PM PDT 24
Finished Jul 03 04:57:17 PM PDT 24
Peak memory 206108 kb
Host smart-cb1d34e4-b4f2-45ad-b243-78823525d4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10537
08667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1053708667
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3226460276
Short name T692
Test name
Test status
Simulation time 212959208 ps
CPU time 0.89 seconds
Started Jul 03 04:57:24 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206092 kb
Host smart-5d4b46d8-396a-4409-b4c4-a3eb4b0e2d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32264
60276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3226460276
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.1686637454
Short name T955
Test name
Test status
Simulation time 5756756711 ps
CPU time 53.58 seconds
Started Jul 03 04:57:23 PM PDT 24
Finished Jul 03 04:58:17 PM PDT 24
Peak memory 206396 kb
Host smart-42a068aa-bdb0-4f6e-bba7-51e22e640b80
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1686637454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.1686637454
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3245563535
Short name T2309
Test name
Test status
Simulation time 205390445 ps
CPU time 0.83 seconds
Started Jul 03 04:57:30 PM PDT 24
Finished Jul 03 04:57:31 PM PDT 24
Peak memory 206116 kb
Host smart-7393faf8-ba62-40c7-8611-f24c89ba114c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32455
63535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3245563535
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.464118574
Short name T2271
Test name
Test status
Simulation time 207223965 ps
CPU time 0.82 seconds
Started Jul 03 04:57:22 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206132 kb
Host smart-2d81ae14-17ff-4a3a-883e-495f0a0fd7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46411
8574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.464118574
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.2206263282
Short name T1284
Test name
Test status
Simulation time 397420767 ps
CPU time 1.25 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:20 PM PDT 24
Peak memory 206088 kb
Host smart-5c54ffdb-188f-4b6d-846d-654ca1196a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22062
63282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.2206263282
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.2895817266
Short name T1264
Test name
Test status
Simulation time 4624365569 ps
CPU time 30.72 seconds
Started Jul 03 04:57:11 PM PDT 24
Finished Jul 03 04:57:42 PM PDT 24
Peak memory 206372 kb
Host smart-b94a65e3-d3cf-41aa-ad99-82770048b848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28958
17266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.2895817266
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1766584706
Short name T1714
Test name
Test status
Simulation time 62195334 ps
CPU time 0.67 seconds
Started Jul 03 04:57:22 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206192 kb
Host smart-e93c7220-f358-4f3d-be51-7f47d2eb0110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1766584706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1766584706
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3923062874
Short name T415
Test name
Test status
Simulation time 3883697942 ps
CPU time 5.13 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206152 kb
Host smart-b91548bf-45de-4308-8b5f-cf96490713f0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3923062874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3923062874
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2031784447
Short name T1637
Test name
Test status
Simulation time 13402846494 ps
CPU time 14.48 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:33 PM PDT 24
Peak memory 206156 kb
Host smart-a38b4a81-b051-40b8-a788-f10e9cc30455
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2031784447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2031784447
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.44569733
Short name T1531
Test name
Test status
Simulation time 23437171388 ps
CPU time 27.73 seconds
Started Jul 03 04:57:16 PM PDT 24
Finished Jul 03 04:57:45 PM PDT 24
Peak memory 206352 kb
Host smart-97af7476-66f5-4297-bfdd-be26fb1b8c90
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=44569733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.44569733
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2004052421
Short name T2704
Test name
Test status
Simulation time 195624616 ps
CPU time 0.88 seconds
Started Jul 03 04:57:19 PM PDT 24
Finished Jul 03 04:57:21 PM PDT 24
Peak memory 206120 kb
Host smart-279af1ac-dc06-460a-ac9c-808a86e5f414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20040
52421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2004052421
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1288963245
Short name T831
Test name
Test status
Simulation time 195508884 ps
CPU time 0.85 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:20 PM PDT 24
Peak memory 206132 kb
Host smart-4d04bc7a-8707-4f32-a8d4-c7e19fd4b3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12889
63245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1288963245
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.2430142423
Short name T2488
Test name
Test status
Simulation time 423652119 ps
CPU time 1.36 seconds
Started Jul 03 04:57:31 PM PDT 24
Finished Jul 03 04:57:33 PM PDT 24
Peak memory 206112 kb
Host smart-6a1d48a0-ec38-439b-98e8-56c43b5c4a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24301
42423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.2430142423
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1675646597
Short name T766
Test name
Test status
Simulation time 685778655 ps
CPU time 1.65 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:21 PM PDT 24
Peak memory 206132 kb
Host smart-2f90d45e-9639-4837-a328-aa8faa098144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16756
46597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1675646597
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.857970667
Short name T1288
Test name
Test status
Simulation time 12776026350 ps
CPU time 27.07 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:41 PM PDT 24
Peak memory 206392 kb
Host smart-ff8ab9b5-71ac-4189-85ce-80b2e456ffff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85797
0667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.857970667
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.1848477534
Short name T1096
Test name
Test status
Simulation time 427790360 ps
CPU time 1.4 seconds
Started Jul 03 04:57:02 PM PDT 24
Finished Jul 03 04:57:04 PM PDT 24
Peak memory 206376 kb
Host smart-51e9f7fe-b266-45a9-8615-da2f48e9f024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18484
77534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.1848477534
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1942793666
Short name T471
Test name
Test status
Simulation time 139771306 ps
CPU time 0.78 seconds
Started Jul 03 04:57:15 PM PDT 24
Finished Jul 03 04:57:16 PM PDT 24
Peak memory 206128 kb
Host smart-9c5285da-6996-4a68-952e-70833780257c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19427
93666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1942793666
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.4242992744
Short name T2022
Test name
Test status
Simulation time 40787603 ps
CPU time 0.68 seconds
Started Jul 03 04:57:07 PM PDT 24
Finished Jul 03 04:57:08 PM PDT 24
Peak memory 206076 kb
Host smart-7122c856-e1ee-4d93-8783-b0c5628f8f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42429
92744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.4242992744
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3094136681
Short name T784
Test name
Test status
Simulation time 780866498 ps
CPU time 2 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:57:29 PM PDT 24
Peak memory 206356 kb
Host smart-0e149df9-4791-4c57-8aac-4819ecc9d73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30941
36681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3094136681
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.976078889
Short name T2375
Test name
Test status
Simulation time 170742629 ps
CPU time 1.8 seconds
Started Jul 03 04:57:22 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206288 kb
Host smart-682f24bf-f66c-4268-88ba-04cc53b09ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97607
8889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.976078889
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3835211828
Short name T2109
Test name
Test status
Simulation time 177416808 ps
CPU time 0.89 seconds
Started Jul 03 04:57:24 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206100 kb
Host smart-fec5cf3a-85ee-499f-82b9-cd95b8c3b607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38352
11828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3835211828
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.102201734
Short name T1539
Test name
Test status
Simulation time 152923062 ps
CPU time 0.85 seconds
Started Jul 03 04:57:10 PM PDT 24
Finished Jul 03 04:57:12 PM PDT 24
Peak memory 206120 kb
Host smart-224643d2-a6a3-461a-a96d-ca3a130611e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10220
1734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.102201734
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1512135259
Short name T772
Test name
Test status
Simulation time 192273875 ps
CPU time 0.84 seconds
Started Jul 03 04:57:16 PM PDT 24
Finished Jul 03 04:57:18 PM PDT 24
Peak memory 206132 kb
Host smart-39b638e1-f477-481b-8faf-5a47fd91c428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15121
35259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1512135259
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.3207314446
Short name T1634
Test name
Test status
Simulation time 8342678535 ps
CPU time 59.53 seconds
Started Jul 03 04:57:19 PM PDT 24
Finished Jul 03 04:58:20 PM PDT 24
Peak memory 206448 kb
Host smart-3695dca9-be70-4a4b-b7b6-36c07827bd5c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3207314446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3207314446
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.4038582412
Short name T997
Test name
Test status
Simulation time 161191230 ps
CPU time 0.82 seconds
Started Jul 03 04:57:24 PM PDT 24
Finished Jul 03 04:57:26 PM PDT 24
Peak memory 206124 kb
Host smart-5ccc19ef-66d5-459f-b6ba-797f6c7de731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40385
82412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.4038582412
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.3493127220
Short name T1561
Test name
Test status
Simulation time 23282826645 ps
CPU time 21.34 seconds
Started Jul 03 04:57:09 PM PDT 24
Finished Jul 03 04:57:31 PM PDT 24
Peak memory 206136 kb
Host smart-cf358f9d-0684-4aea-baba-4150f3200e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34931
27220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.3493127220
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.253848902
Short name T432
Test name
Test status
Simulation time 3378469615 ps
CPU time 3.71 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:57:30 PM PDT 24
Peak memory 206184 kb
Host smart-30052b7b-3b2a-458d-9b5b-80ca090185e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25384
8902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.253848902
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.4269287525
Short name T1889
Test name
Test status
Simulation time 7354664120 ps
CPU time 201.96 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 05:00:35 PM PDT 24
Peak memory 206456 kb
Host smart-ac88a0d3-bff5-40dc-b023-5a4c99c1a064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42692
87525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.4269287525
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.1842032573
Short name T1349
Test name
Test status
Simulation time 5697153387 ps
CPU time 55.56 seconds
Started Jul 03 04:57:27 PM PDT 24
Finished Jul 03 04:58:23 PM PDT 24
Peak memory 206424 kb
Host smart-488ff54d-f722-44a3-839b-056c35e63652
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1842032573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.1842032573
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.870417764
Short name T1315
Test name
Test status
Simulation time 241242857 ps
CPU time 0.92 seconds
Started Jul 03 04:57:19 PM PDT 24
Finished Jul 03 04:57:21 PM PDT 24
Peak memory 206104 kb
Host smart-2dbb437a-26fb-4f2c-b4e1-1b914e064bca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=870417764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.870417764
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.4091752966
Short name T910
Test name
Test status
Simulation time 189510494 ps
CPU time 0.9 seconds
Started Jul 03 04:57:21 PM PDT 24
Finished Jul 03 04:57:22 PM PDT 24
Peak memory 206108 kb
Host smart-b40c374f-75ed-4ed2-b0f5-33770a7f9fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40917
52966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.4091752966
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2511589435
Short name T552
Test name
Test status
Simulation time 4379890766 ps
CPU time 116.59 seconds
Started Jul 03 04:57:24 PM PDT 24
Finished Jul 03 04:59:21 PM PDT 24
Peak memory 206380 kb
Host smart-d074c4f5-33af-4aeb-b268-7626a95a6cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25115
89435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2511589435
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2771074689
Short name T1033
Test name
Test status
Simulation time 7511707120 ps
CPU time 208.9 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 05:00:43 PM PDT 24
Peak memory 206380 kb
Host smart-3a6c09eb-750c-4464-abcb-63a00c1b3981
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2771074689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2771074689
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1949966335
Short name T2257
Test name
Test status
Simulation time 163515593 ps
CPU time 0.85 seconds
Started Jul 03 04:57:13 PM PDT 24
Finished Jul 03 04:57:14 PM PDT 24
Peak memory 206128 kb
Host smart-8877c5c2-37eb-4fb5-8cd7-7ca25ac34f22
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1949966335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1949966335
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2261998853
Short name T589
Test name
Test status
Simulation time 144520036 ps
CPU time 0.78 seconds
Started Jul 03 04:57:34 PM PDT 24
Finished Jul 03 04:57:36 PM PDT 24
Peak memory 206076 kb
Host smart-9a1fe0f8-453c-48de-bd6f-2b84653b97f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22619
98853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2261998853
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3831152578
Short name T124
Test name
Test status
Simulation time 196064210 ps
CPU time 0.91 seconds
Started Jul 03 04:57:19 PM PDT 24
Finished Jul 03 04:57:22 PM PDT 24
Peak memory 206132 kb
Host smart-3ff3ef30-058b-4a72-bdcd-575984f7ee97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38311
52578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3831152578
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2024051941
Short name T2528
Test name
Test status
Simulation time 208760074 ps
CPU time 0.92 seconds
Started Jul 03 04:57:11 PM PDT 24
Finished Jul 03 04:57:12 PM PDT 24
Peak memory 206132 kb
Host smart-9ba6ab31-083a-4bc2-b119-d63b65ab5da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20240
51941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2024051941
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3652389894
Short name T2676
Test name
Test status
Simulation time 154991342 ps
CPU time 0.82 seconds
Started Jul 03 04:57:21 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206120 kb
Host smart-73ed741e-3652-457f-b5b0-b29afa6b28a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36523
89894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3652389894
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2323818073
Short name T2128
Test name
Test status
Simulation time 206935778 ps
CPU time 0.88 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:19 PM PDT 24
Peak memory 206132 kb
Host smart-f4a9a723-3593-4026-b10a-b7dfdf3065d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23238
18073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2323818073
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1706803871
Short name T1837
Test name
Test status
Simulation time 168195398 ps
CPU time 0.79 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:57:27 PM PDT 24
Peak memory 206104 kb
Host smart-e3717cde-0ac4-4ca5-b087-3bf055384331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17068
03871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1706803871
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1893408659
Short name T1310
Test name
Test status
Simulation time 221498887 ps
CPU time 0.93 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:20 PM PDT 24
Peak memory 206132 kb
Host smart-749d07ce-57c3-4faf-ab58-603b3f64e9a0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1893408659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1893408659
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2362389991
Short name T43
Test name
Test status
Simulation time 149842158 ps
CPU time 0.73 seconds
Started Jul 03 04:57:15 PM PDT 24
Finished Jul 03 04:57:17 PM PDT 24
Peak memory 205980 kb
Host smart-0468284f-db1e-4020-b659-746c241b2c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23623
89991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2362389991
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3278761187
Short name T39
Test name
Test status
Simulation time 41143928 ps
CPU time 0.67 seconds
Started Jul 03 04:57:22 PM PDT 24
Finished Jul 03 04:57:29 PM PDT 24
Peak memory 206084 kb
Host smart-208c38dd-ad02-427b-a1d0-68ad87ddb0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32787
61187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3278761187
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3602069709
Short name T1138
Test name
Test status
Simulation time 7390504550 ps
CPU time 15.92 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:57:43 PM PDT 24
Peak memory 206352 kb
Host smart-c28bdee2-a1c7-404d-a728-33aa470113cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36020
69709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3602069709
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.244459350
Short name T1175
Test name
Test status
Simulation time 180693316 ps
CPU time 0.87 seconds
Started Jul 03 04:57:22 PM PDT 24
Finished Jul 03 04:57:24 PM PDT 24
Peak memory 206108 kb
Host smart-cdc9d54f-1835-4304-8044-f6e6c6b4865d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24445
9350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.244459350
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.336229850
Short name T2718
Test name
Test status
Simulation time 223098126 ps
CPU time 0.84 seconds
Started Jul 03 04:57:22 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206112 kb
Host smart-cc7ebcf4-d20f-4407-970a-67802d43e84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33622
9850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.336229850
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3202591240
Short name T2290
Test name
Test status
Simulation time 174028483 ps
CPU time 0.82 seconds
Started Jul 03 04:57:27 PM PDT 24
Finished Jul 03 04:57:28 PM PDT 24
Peak memory 206112 kb
Host smart-fff35838-c4a4-4285-ab54-2b189c428210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32025
91240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3202591240
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.4177700018
Short name T419
Test name
Test status
Simulation time 188369123 ps
CPU time 0.83 seconds
Started Jul 03 04:57:24 PM PDT 24
Finished Jul 03 04:57:26 PM PDT 24
Peak memory 206116 kb
Host smart-e1470bda-249a-4986-a976-0489406a188d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41777
00018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.4177700018
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1749998884
Short name T82
Test name
Test status
Simulation time 205276713 ps
CPU time 0.83 seconds
Started Jul 03 04:57:21 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206144 kb
Host smart-2ffb9e45-82c1-41ef-b4f1-01458fa689c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17499
98884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1749998884
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.4095103504
Short name T1944
Test name
Test status
Simulation time 172816085 ps
CPU time 0.81 seconds
Started Jul 03 04:57:40 PM PDT 24
Finished Jul 03 04:57:41 PM PDT 24
Peak memory 206096 kb
Host smart-8c642815-9ef9-4386-a486-9f23917be8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40951
03504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.4095103504
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1410953384
Short name T636
Test name
Test status
Simulation time 148631921 ps
CPU time 0.79 seconds
Started Jul 03 04:57:24 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206112 kb
Host smart-d5910c50-8f92-469b-a09b-1ac16aa9f9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14109
53384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1410953384
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3686329762
Short name T1847
Test name
Test status
Simulation time 226926338 ps
CPU time 0.96 seconds
Started Jul 03 04:57:24 PM PDT 24
Finished Jul 03 04:57:26 PM PDT 24
Peak memory 206000 kb
Host smart-e16c3cb4-e420-4216-aedb-2960218138e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36863
29762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3686329762
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.4200382490
Short name T1754
Test name
Test status
Simulation time 3469115712 ps
CPU time 24.36 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:57:51 PM PDT 24
Peak memory 206400 kb
Host smart-8e8fb2a6-6610-40ae-81ec-cd59ec4840ed
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4200382490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.4200382490
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2238865377
Short name T2291
Test name
Test status
Simulation time 178872463 ps
CPU time 0.83 seconds
Started Jul 03 04:57:20 PM PDT 24
Finished Jul 03 04:57:22 PM PDT 24
Peak memory 206148 kb
Host smart-6008c840-72ee-4d9d-8600-3327020980e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22388
65377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2238865377
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3169263347
Short name T1703
Test name
Test status
Simulation time 191581359 ps
CPU time 0.8 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 04:57:47 PM PDT 24
Peak memory 206092 kb
Host smart-f1632b32-7840-48b7-965f-26012dd23fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31692
63347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3169263347
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.3886300076
Short name T1476
Test name
Test status
Simulation time 883995092 ps
CPU time 1.91 seconds
Started Jul 03 04:57:24 PM PDT 24
Finished Jul 03 04:57:27 PM PDT 24
Peak memory 206368 kb
Host smart-f5ef2b08-7112-48ca-8d69-0402ccf1bc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
00076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3886300076
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.162317662
Short name T1779
Test name
Test status
Simulation time 4479027459 ps
CPU time 32.22 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:52 PM PDT 24
Peak memory 206392 kb
Host smart-207d3df1-aa9d-42fc-b95b-28c8af0a7861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16231
7662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.162317662
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.4235094144
Short name T929
Test name
Test status
Simulation time 39424230 ps
CPU time 0.66 seconds
Started Jul 03 04:57:46 PM PDT 24
Finished Jul 03 04:57:48 PM PDT 24
Peak memory 206188 kb
Host smart-23257e7f-c450-4523-b784-8e12506edd42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4235094144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.4235094144
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3398955441
Short name T821
Test name
Test status
Simulation time 4126915874 ps
CPU time 5.41 seconds
Started Jul 03 04:57:18 PM PDT 24
Finished Jul 03 04:57:24 PM PDT 24
Peak memory 206416 kb
Host smart-5a60a344-d3ba-4c4d-95ff-3d3b693dd612
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3398955441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.3398955441
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1264385786
Short name T2370
Test name
Test status
Simulation time 13346446379 ps
CPU time 11.6 seconds
Started Jul 03 04:57:16 PM PDT 24
Finished Jul 03 04:57:28 PM PDT 24
Peak memory 206352 kb
Host smart-de0df5f9-6d51-4546-b535-c48f9ff821cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1264385786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1264385786
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1556174150
Short name T455
Test name
Test status
Simulation time 23373760188 ps
CPU time 22.67 seconds
Started Jul 03 04:57:19 PM PDT 24
Finished Jul 03 04:57:43 PM PDT 24
Peak memory 206160 kb
Host smart-dad1894f-845b-48bb-9f61-efd84c5b587b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1556174150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1556174150
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1997415150
Short name T528
Test name
Test status
Simulation time 181156025 ps
CPU time 0.87 seconds
Started Jul 03 04:57:21 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206096 kb
Host smart-12e4d6c6-23e9-460b-bb11-8be2d8cc855c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19974
15150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1997415150
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.407230939
Short name T2133
Test name
Test status
Simulation time 141774085 ps
CPU time 0.78 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:19 PM PDT 24
Peak memory 206080 kb
Host smart-8533de84-cf18-4673-be7a-07b6614e464b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40723
0939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.407230939
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.3479049140
Short name T2056
Test name
Test status
Simulation time 546520809 ps
CPU time 1.63 seconds
Started Jul 03 04:57:39 PM PDT 24
Finished Jul 03 04:57:41 PM PDT 24
Peak memory 206304 kb
Host smart-37cc8943-bc35-4a34-80b4-90b1ac2a10aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34790
49140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.3479049140
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3656295150
Short name T1151
Test name
Test status
Simulation time 299575863 ps
CPU time 0.99 seconds
Started Jul 03 04:57:20 PM PDT 24
Finished Jul 03 04:57:22 PM PDT 24
Peak memory 206112 kb
Host smart-4ea70e95-baa1-4b9f-b1a0-000532c7c291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36562
95150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3656295150
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.2920164037
Short name T2210
Test name
Test status
Simulation time 14133108589 ps
CPU time 25.67 seconds
Started Jul 03 04:57:29 PM PDT 24
Finished Jul 03 04:57:55 PM PDT 24
Peak memory 206440 kb
Host smart-17dacd97-eb18-4ca1-b09f-2145fa0e0027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29201
64037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.2920164037
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.2910105475
Short name T388
Test name
Test status
Simulation time 466375809 ps
CPU time 1.48 seconds
Started Jul 03 04:57:14 PM PDT 24
Finished Jul 03 04:57:16 PM PDT 24
Peak memory 206068 kb
Host smart-f7a54f62-e496-4406-81fa-1c88389266df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29101
05475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.2910105475
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3266626202
Short name T468
Test name
Test status
Simulation time 151530957 ps
CPU time 0.76 seconds
Started Jul 03 04:57:21 PM PDT 24
Finished Jul 03 04:57:22 PM PDT 24
Peak memory 206004 kb
Host smart-540040ff-8607-4b55-aa4b-6606c7f90721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32666
26202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3266626202
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.997816936
Short name T1118
Test name
Test status
Simulation time 82093481 ps
CPU time 0.72 seconds
Started Jul 03 04:57:24 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206112 kb
Host smart-1dd5d228-ef53-490f-a8f4-484bb0ee16c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99781
6936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.997816936
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1843120156
Short name T633
Test name
Test status
Simulation time 914822247 ps
CPU time 2.08 seconds
Started Jul 03 04:57:20 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206308 kb
Host smart-422f5973-04fe-4fd5-8905-4d56200250eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18431
20156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1843120156
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.4051474744
Short name T1819
Test name
Test status
Simulation time 156935003 ps
CPU time 1.35 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:20 PM PDT 24
Peak memory 206320 kb
Host smart-6996fd3a-8025-4e16-993b-a9d230461fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40514
74744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.4051474744
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1168208681
Short name T518
Test name
Test status
Simulation time 233866542 ps
CPU time 0.88 seconds
Started Jul 03 04:57:32 PM PDT 24
Finished Jul 03 04:57:34 PM PDT 24
Peak memory 206096 kb
Host smart-1a8c5ba8-ec65-4e9a-8015-17bb953ffd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11682
08681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1168208681
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.4176414517
Short name T783
Test name
Test status
Simulation time 156445163 ps
CPU time 0.83 seconds
Started Jul 03 04:57:30 PM PDT 24
Finished Jul 03 04:57:32 PM PDT 24
Peak memory 206088 kb
Host smart-55487aa1-3fc6-4b5b-b28f-5dbb2069c46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41764
14517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.4176414517
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3311563016
Short name T2333
Test name
Test status
Simulation time 167358958 ps
CPU time 0.83 seconds
Started Jul 03 04:57:25 PM PDT 24
Finished Jul 03 04:57:26 PM PDT 24
Peak memory 206100 kb
Host smart-2f657838-2ec7-4cb9-8fc4-c7dc07815165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33115
63016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3311563016
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.524046220
Short name T746
Test name
Test status
Simulation time 166361661 ps
CPU time 0.86 seconds
Started Jul 03 04:57:28 PM PDT 24
Finished Jul 03 04:57:30 PM PDT 24
Peak memory 206108 kb
Host smart-4329b0f8-e4b7-4d35-839e-f558080f2a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52404
6220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.524046220
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1680661099
Short name T1442
Test name
Test status
Simulation time 23283405830 ps
CPU time 24.55 seconds
Started Jul 03 04:57:43 PM PDT 24
Finished Jul 03 04:58:08 PM PDT 24
Peak memory 206172 kb
Host smart-edfa4ec5-af19-4603-8da8-356605e5f81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16806
61099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1680661099
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2985039544
Short name T1189
Test name
Test status
Simulation time 3284831551 ps
CPU time 3.7 seconds
Started Jul 03 04:57:15 PM PDT 24
Finished Jul 03 04:57:19 PM PDT 24
Peak memory 206148 kb
Host smart-79441098-f193-4e74-8b52-dfe53d78641d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29850
39544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2985039544
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.446846313
Short name T1498
Test name
Test status
Simulation time 7120419962 ps
CPU time 189.57 seconds
Started Jul 03 04:57:38 PM PDT 24
Finished Jul 03 05:00:48 PM PDT 24
Peak memory 206432 kb
Host smart-c64c906d-ad2e-448b-9925-29175ebe2fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44684
6313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.446846313
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2263299942
Short name T461
Test name
Test status
Simulation time 3318208421 ps
CPU time 85.88 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:58:52 PM PDT 24
Peak memory 206396 kb
Host smart-139b6574-cc46-4f68-9eda-df8ae90fe9b9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2263299942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2263299942
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.1665431234
Short name T1798
Test name
Test status
Simulation time 250551412 ps
CPU time 0.99 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:19 PM PDT 24
Peak memory 206104 kb
Host smart-dd13d864-971d-41e1-a59e-cfdd91e03280
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1665431234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.1665431234
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3273470218
Short name T1408
Test name
Test status
Simulation time 193823926 ps
CPU time 0.83 seconds
Started Jul 03 04:57:31 PM PDT 24
Finished Jul 03 04:57:32 PM PDT 24
Peak memory 206088 kb
Host smart-1d0d3706-09ca-4031-ba7d-65e6b4c45b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32734
70218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3273470218
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.3790146290
Short name T658
Test name
Test status
Simulation time 5915713020 ps
CPU time 41 seconds
Started Jul 03 04:57:23 PM PDT 24
Finished Jul 03 04:58:04 PM PDT 24
Peak memory 206300 kb
Host smart-151cba2e-9094-4e65-a29a-2f1046b3d43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37901
46290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.3790146290
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3436137196
Short name T1128
Test name
Test status
Simulation time 6028197793 ps
CPU time 40.94 seconds
Started Jul 03 04:57:23 PM PDT 24
Finished Jul 03 04:58:04 PM PDT 24
Peak memory 206212 kb
Host smart-b3146f7d-adc6-4b30-93ac-6155804f2e75
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3436137196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3436137196
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2812710759
Short name T896
Test name
Test status
Simulation time 182050729 ps
CPU time 0.86 seconds
Started Jul 03 04:57:28 PM PDT 24
Finished Jul 03 04:57:29 PM PDT 24
Peak memory 206000 kb
Host smart-b43806ed-5cc1-4a6a-8dcd-fb2b0d17dcfc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2812710759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2812710759
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3654433386
Short name T2246
Test name
Test status
Simulation time 145956192 ps
CPU time 0.83 seconds
Started Jul 03 04:57:21 PM PDT 24
Finished Jul 03 04:57:23 PM PDT 24
Peak memory 206028 kb
Host smart-0e75670b-edb2-4b78-8214-4d9915c85973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36544
33386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3654433386
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2519972094
Short name T132
Test name
Test status
Simulation time 241355209 ps
CPU time 0.91 seconds
Started Jul 03 04:57:21 PM PDT 24
Finished Jul 03 04:57:22 PM PDT 24
Peak memory 206092 kb
Host smart-7c3774c4-d7ef-43be-8e84-ac0f6fb7368b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25199
72094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2519972094
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2604578606
Short name T2300
Test name
Test status
Simulation time 166351996 ps
CPU time 0.85 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:19 PM PDT 24
Peak memory 206040 kb
Host smart-e8dce8c5-2a08-4d48-a9e1-91a6aad10706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26045
78606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2604578606
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1653888453
Short name T1770
Test name
Test status
Simulation time 202607725 ps
CPU time 0.88 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:57:27 PM PDT 24
Peak memory 206108 kb
Host smart-b47e03cf-cb1e-45b3-99f7-577fb661cb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16538
88453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1653888453
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1467308524
Short name T1080
Test name
Test status
Simulation time 181220106 ps
CPU time 0.86 seconds
Started Jul 03 04:57:50 PM PDT 24
Finished Jul 03 04:57:51 PM PDT 24
Peak memory 206108 kb
Host smart-d609fbe4-e40c-4fb8-931e-69c94978df2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14673
08524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1467308524
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.169014949
Short name T1586
Test name
Test status
Simulation time 162383613 ps
CPU time 0.8 seconds
Started Jul 03 04:57:35 PM PDT 24
Finished Jul 03 04:57:36 PM PDT 24
Peak memory 206068 kb
Host smart-821c702b-0f3a-4678-8b74-44a7cf7c6f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16901
4949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.169014949
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2454676639
Short name T2111
Test name
Test status
Simulation time 248134413 ps
CPU time 0.99 seconds
Started Jul 03 04:57:24 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206120 kb
Host smart-96d14221-1f72-4498-b22a-ac61ac97513a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2454676639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2454676639
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1024038070
Short name T2307
Test name
Test status
Simulation time 146532501 ps
CPU time 0.77 seconds
Started Jul 03 04:57:30 PM PDT 24
Finished Jul 03 04:57:32 PM PDT 24
Peak memory 206068 kb
Host smart-cc7ddcd4-644f-4fba-86b9-4c54e8a3dcf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10240
38070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1024038070
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.4102982872
Short name T542
Test name
Test status
Simulation time 43761594 ps
CPU time 0.64 seconds
Started Jul 03 04:57:40 PM PDT 24
Finished Jul 03 04:57:41 PM PDT 24
Peak memory 205908 kb
Host smart-f90c54f9-c1e6-4412-a644-75d7ad1f4b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
82872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.4102982872
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2054523003
Short name T103
Test name
Test status
Simulation time 6375659211 ps
CPU time 16.4 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 04:58:03 PM PDT 24
Peak memory 206368 kb
Host smart-125153a4-20ed-4b78-9aa4-0d057c5a83fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20545
23003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2054523003
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1757632874
Short name T1078
Test name
Test status
Simulation time 171112884 ps
CPU time 0.84 seconds
Started Jul 03 04:57:22 PM PDT 24
Finished Jul 03 04:57:24 PM PDT 24
Peak memory 206112 kb
Host smart-0edc4e4a-f0ec-49ae-b05f-10b4ebf1ff2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17576
32874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1757632874
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2724370800
Short name T2539
Test name
Test status
Simulation time 162175364 ps
CPU time 0.84 seconds
Started Jul 03 04:57:25 PM PDT 24
Finished Jul 03 04:57:27 PM PDT 24
Peak memory 206092 kb
Host smart-4658873d-6f18-4cb3-96d7-546abdae0e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243
70800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2724370800
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1401847903
Short name T2191
Test name
Test status
Simulation time 173356563 ps
CPU time 0.8 seconds
Started Jul 03 04:57:25 PM PDT 24
Finished Jul 03 04:57:27 PM PDT 24
Peak memory 206100 kb
Host smart-213e07ea-847b-493e-87b2-09846a337457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14018
47903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1401847903
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1001583609
Short name T980
Test name
Test status
Simulation time 158325681 ps
CPU time 0.81 seconds
Started Jul 03 04:57:29 PM PDT 24
Finished Jul 03 04:57:30 PM PDT 24
Peak memory 206120 kb
Host smart-3fb3109d-c90d-463f-824a-f081c5d50580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10015
83609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1001583609
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.476779751
Short name T2144
Test name
Test status
Simulation time 167942247 ps
CPU time 0.81 seconds
Started Jul 03 04:57:28 PM PDT 24
Finished Jul 03 04:57:29 PM PDT 24
Peak memory 206000 kb
Host smart-530516c9-b651-4bcb-b429-3212376928cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47677
9751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.476779751
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.978512860
Short name T2208
Test name
Test status
Simulation time 221988196 ps
CPU time 0.81 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:57:28 PM PDT 24
Peak memory 206132 kb
Host smart-de55124c-ad4f-4881-87df-4d68aa6365e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97851
2860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.978512860
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3565890579
Short name T2651
Test name
Test status
Simulation time 173102278 ps
CPU time 0.8 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:57:28 PM PDT 24
Peak memory 206112 kb
Host smart-2b20a9d2-48c0-47e1-b9f2-e285244beadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35658
90579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3565890579
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3724008102
Short name T2404
Test name
Test status
Simulation time 239967797 ps
CPU time 0.92 seconds
Started Jul 03 04:57:27 PM PDT 24
Finished Jul 03 04:57:29 PM PDT 24
Peak memory 206128 kb
Host smart-32e55446-04fd-4171-8f5d-6b09ea219abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37240
08102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3724008102
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2090738020
Short name T435
Test name
Test status
Simulation time 3974818223 ps
CPU time 28.06 seconds
Started Jul 03 04:57:32 PM PDT 24
Finished Jul 03 04:58:01 PM PDT 24
Peak memory 206432 kb
Host smart-7a2aa74e-47e4-42b9-8332-492825d2917b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2090738020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2090738020
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.937734245
Short name T778
Test name
Test status
Simulation time 180543928 ps
CPU time 0.8 seconds
Started Jul 03 04:57:36 PM PDT 24
Finished Jul 03 04:57:37 PM PDT 24
Peak memory 206120 kb
Host smart-da1f8702-9490-420b-a2ad-aef5d8ec443d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93773
4245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.937734245
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.4190667314
Short name T1265
Test name
Test status
Simulation time 161638467 ps
CPU time 0.78 seconds
Started Jul 03 04:58:01 PM PDT 24
Finished Jul 03 04:58:03 PM PDT 24
Peak memory 206132 kb
Host smart-67dd1de5-f234-416e-98ae-dddd1f56df03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41906
67314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.4190667314
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.891744311
Short name T2522
Test name
Test status
Simulation time 605335658 ps
CPU time 1.49 seconds
Started Jul 03 04:57:30 PM PDT 24
Finished Jul 03 04:57:32 PM PDT 24
Peak memory 206128 kb
Host smart-da1fee3a-aa60-4c4d-979e-bd38aad295bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89174
4311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.891744311
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1091963165
Short name T2010
Test name
Test status
Simulation time 5718478531 ps
CPU time 43.53 seconds
Started Jul 03 04:57:25 PM PDT 24
Finished Jul 03 04:58:09 PM PDT 24
Peak memory 206388 kb
Host smart-939f54dc-db24-4f92-94a9-19e2a6d811cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10919
63165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1091963165
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.1443484928
Short name T2570
Test name
Test status
Simulation time 42523936 ps
CPU time 0.68 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 04:57:47 PM PDT 24
Peak memory 206124 kb
Host smart-ed0ab6a4-a42d-4c8d-82e4-cf08b0833626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1443484928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.1443484928
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1438769909
Short name T1330
Test name
Test status
Simulation time 3490581926 ps
CPU time 4.41 seconds
Started Jul 03 04:57:22 PM PDT 24
Finished Jul 03 04:57:28 PM PDT 24
Peak memory 206196 kb
Host smart-4be7adc0-c8dd-4799-812b-c8f2de01802d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1438769909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1438769909
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3187349706
Short name T1684
Test name
Test status
Simulation time 13288565089 ps
CPU time 11.91 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:57:39 PM PDT 24
Peak memory 206376 kb
Host smart-47fe246d-46cd-4806-b10d-9318800553e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3187349706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3187349706
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.230622211
Short name T2145
Test name
Test status
Simulation time 23422600875 ps
CPU time 23.42 seconds
Started Jul 03 04:57:25 PM PDT 24
Finished Jul 03 04:57:49 PM PDT 24
Peak memory 206368 kb
Host smart-1ac32a8e-a21c-49ec-970b-c8450e8e0550
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=230622211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.230622211
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.641263359
Short name T580
Test name
Test status
Simulation time 208400475 ps
CPU time 0.91 seconds
Started Jul 03 04:57:50 PM PDT 24
Finished Jul 03 04:57:57 PM PDT 24
Peak memory 206132 kb
Host smart-351e7f78-c45a-4719-beb6-1e68f8ca48e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64126
3359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.641263359
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2109190941
Short name T36
Test name
Test status
Simulation time 149921324 ps
CPU time 0.75 seconds
Started Jul 03 04:57:27 PM PDT 24
Finished Jul 03 04:57:29 PM PDT 24
Peak memory 206132 kb
Host smart-b889f270-c554-4356-859a-17891b72cf13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21091
90941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2109190941
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1277223685
Short name T361
Test name
Test status
Simulation time 175802734 ps
CPU time 0.81 seconds
Started Jul 03 04:57:27 PM PDT 24
Finished Jul 03 04:57:28 PM PDT 24
Peak memory 206136 kb
Host smart-cf7e3049-e63a-4e8d-b62e-8c4d57b3140f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12772
23685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1277223685
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1360804155
Short name T1674
Test name
Test status
Simulation time 811860048 ps
CPU time 1.87 seconds
Started Jul 03 04:57:34 PM PDT 24
Finished Jul 03 04:57:37 PM PDT 24
Peak memory 206256 kb
Host smart-85d92224-6b30-4e36-b48f-9551e9e8d635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13608
04155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1360804155
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.432165786
Short name T1544
Test name
Test status
Simulation time 15056725016 ps
CPU time 28.92 seconds
Started Jul 03 04:57:19 PM PDT 24
Finished Jul 03 04:57:50 PM PDT 24
Peak memory 206356 kb
Host smart-9186df19-b594-4fd0-a0be-86969480578c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43216
5786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.432165786
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1981776383
Short name T2707
Test name
Test status
Simulation time 437228186 ps
CPU time 1.32 seconds
Started Jul 03 04:57:17 PM PDT 24
Finished Jul 03 04:57:20 PM PDT 24
Peak memory 206112 kb
Host smart-4a4fc54f-1a5f-4007-86c0-4b639d4f9694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19817
76383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1981776383
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.674931518
Short name T1347
Test name
Test status
Simulation time 139711036 ps
CPU time 0.81 seconds
Started Jul 03 04:57:27 PM PDT 24
Finished Jul 03 04:57:29 PM PDT 24
Peak memory 206016 kb
Host smart-05aaf420-7e9c-4184-a70e-86f71339c291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67493
1518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.674931518
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.949904232
Short name T1753
Test name
Test status
Simulation time 52545635 ps
CPU time 0.68 seconds
Started Jul 03 04:57:34 PM PDT 24
Finished Jul 03 04:57:35 PM PDT 24
Peak memory 206100 kb
Host smart-756c065a-28af-43bb-a634-88746f7eaa79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94990
4232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.949904232
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3025121800
Short name T691
Test name
Test status
Simulation time 907116335 ps
CPU time 1.97 seconds
Started Jul 03 04:57:35 PM PDT 24
Finished Jul 03 04:57:37 PM PDT 24
Peak memory 206332 kb
Host smart-6bd7c6cb-94e9-4140-ab49-67406388ad0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30251
21800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3025121800
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1794539187
Short name T1669
Test name
Test status
Simulation time 251225365 ps
CPU time 1.59 seconds
Started Jul 03 04:57:23 PM PDT 24
Finished Jul 03 04:57:25 PM PDT 24
Peak memory 206308 kb
Host smart-73e0029c-86f9-4033-92e6-d20126e6d734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17945
39187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1794539187
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3010044298
Short name T1156
Test name
Test status
Simulation time 297942162 ps
CPU time 0.98 seconds
Started Jul 03 04:57:31 PM PDT 24
Finished Jul 03 04:57:33 PM PDT 24
Peak memory 206104 kb
Host smart-8340c358-ae8c-4149-a061-cce29efc8b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30100
44298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3010044298
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3652406802
Short name T1173
Test name
Test status
Simulation time 141001727 ps
CPU time 0.78 seconds
Started Jul 03 04:57:25 PM PDT 24
Finished Jul 03 04:57:27 PM PDT 24
Peak memory 206128 kb
Host smart-03544b1f-88d4-4bfe-8957-e79142112254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36524
06802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3652406802
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.492395749
Short name T2245
Test name
Test status
Simulation time 209990055 ps
CPU time 0.88 seconds
Started Jul 03 04:57:32 PM PDT 24
Finished Jul 03 04:57:34 PM PDT 24
Peak memory 206112 kb
Host smart-d786ea94-fc61-47d5-9928-72c3e08f6774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49239
5749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.492395749
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.3374601969
Short name T1344
Test name
Test status
Simulation time 7707093873 ps
CPU time 207.8 seconds
Started Jul 03 04:57:36 PM PDT 24
Finished Jul 03 05:01:04 PM PDT 24
Peak memory 206436 kb
Host smart-d2385d3c-1fda-4bed-aef6-ac74b8818fb2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3374601969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.3374601969
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.4067854255
Short name T2164
Test name
Test status
Simulation time 214946429 ps
CPU time 0.86 seconds
Started Jul 03 04:57:33 PM PDT 24
Finished Jul 03 04:57:35 PM PDT 24
Peak memory 206132 kb
Host smart-7650f5d4-dc35-48b4-8f82-ebd6a0eda96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40678
54255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.4067854255
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.855211023
Short name T517
Test name
Test status
Simulation time 23264186241 ps
CPU time 22.33 seconds
Started Jul 03 04:57:33 PM PDT 24
Finished Jul 03 04:57:56 PM PDT 24
Peak memory 206180 kb
Host smart-232813ff-98c0-4542-a69a-9b05912e37ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85521
1023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.855211023
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.4186345214
Short name T1047
Test name
Test status
Simulation time 3386184944 ps
CPU time 3.87 seconds
Started Jul 03 04:57:53 PM PDT 24
Finished Jul 03 04:57:57 PM PDT 24
Peak memory 206164 kb
Host smart-2d05c44a-fe02-4735-af77-d6f1cadb40a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41863
45214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.4186345214
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.3807109000
Short name T1137
Test name
Test status
Simulation time 12731534144 ps
CPU time 91 seconds
Started Jul 03 04:57:43 PM PDT 24
Finished Jul 03 04:59:15 PM PDT 24
Peak memory 206428 kb
Host smart-da6564cb-e790-4d4a-8501-3e6f289bb688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38071
09000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.3807109000
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.1916695659
Short name T1421
Test name
Test status
Simulation time 4135792809 ps
CPU time 30.12 seconds
Started Jul 03 04:57:33 PM PDT 24
Finished Jul 03 04:58:03 PM PDT 24
Peak memory 206348 kb
Host smart-51484538-0976-438e-b35b-e8bc6cb9730a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1916695659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.1916695659
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2681230448
Short name T1336
Test name
Test status
Simulation time 239653617 ps
CPU time 0.94 seconds
Started Jul 03 04:57:40 PM PDT 24
Finished Jul 03 04:57:41 PM PDT 24
Peak memory 206080 kb
Host smart-ac035ccc-781b-47c8-b439-2941f9397f5b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2681230448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2681230448
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3900371484
Short name T677
Test name
Test status
Simulation time 232427421 ps
CPU time 0.93 seconds
Started Jul 03 04:57:48 PM PDT 24
Finished Jul 03 04:57:50 PM PDT 24
Peak memory 206076 kb
Host smart-40497bc2-f9c0-4db9-8fbe-ac710420f160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39003
71484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3900371484
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.1377707832
Short name T2442
Test name
Test status
Simulation time 6946284715 ps
CPU time 49.12 seconds
Started Jul 03 04:57:27 PM PDT 24
Finished Jul 03 04:58:17 PM PDT 24
Peak memory 206368 kb
Host smart-54b204a7-bbeb-442a-a63e-59cf4a4a666c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13777
07832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.1377707832
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.4031622325
Short name T1560
Test name
Test status
Simulation time 5939286914 ps
CPU time 163.69 seconds
Started Jul 03 04:57:38 PM PDT 24
Finished Jul 03 05:00:22 PM PDT 24
Peak memory 206364 kb
Host smart-1ea84eea-8791-4c13-96a4-8bb8dc3e3e75
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4031622325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.4031622325
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.465564721
Short name T2662
Test name
Test status
Simulation time 160939959 ps
CPU time 0.82 seconds
Started Jul 03 04:57:48 PM PDT 24
Finished Jul 03 04:57:49 PM PDT 24
Peak memory 206132 kb
Host smart-53d0ecf3-4dfa-4fe8-9e76-0e97708a15e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=465564721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.465564721
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3781687976
Short name T2384
Test name
Test status
Simulation time 154268456 ps
CPU time 0.77 seconds
Started Jul 03 04:57:42 PM PDT 24
Finished Jul 03 04:57:43 PM PDT 24
Peak memory 206076 kb
Host smart-7bf2298b-3e11-4e2b-8ddf-606012b69043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37816
87976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3781687976
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.330416207
Short name T1062
Test name
Test status
Simulation time 226965973 ps
CPU time 0.87 seconds
Started Jul 03 04:57:41 PM PDT 24
Finished Jul 03 04:57:42 PM PDT 24
Peak memory 206100 kb
Host smart-de23e005-efc5-4005-beea-fb6af79253db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33041
6207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.330416207
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3546129093
Short name T543
Test name
Test status
Simulation time 168510442 ps
CPU time 0.87 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 04:57:47 PM PDT 24
Peak memory 206128 kb
Host smart-dfb3bf9b-680c-41b0-8960-fe3f43795eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35461
29093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3546129093
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2263597004
Short name T2063
Test name
Test status
Simulation time 179950225 ps
CPU time 0.85 seconds
Started Jul 03 04:57:34 PM PDT 24
Finished Jul 03 04:57:35 PM PDT 24
Peak memory 206112 kb
Host smart-0c4b359d-c567-4964-8907-da08d808bc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22635
97004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2263597004
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.922797008
Short name T2153
Test name
Test status
Simulation time 186452963 ps
CPU time 0.83 seconds
Started Jul 03 04:57:51 PM PDT 24
Finished Jul 03 04:57:53 PM PDT 24
Peak memory 206096 kb
Host smart-c3ba525e-af52-4b86-b450-a963cc116dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92279
7008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.922797008
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1208294340
Short name T2715
Test name
Test status
Simulation time 228891321 ps
CPU time 0.89 seconds
Started Jul 03 04:57:43 PM PDT 24
Finished Jul 03 04:57:44 PM PDT 24
Peak memory 206076 kb
Host smart-721ef6a8-c4bf-4be9-9d54-faa7eb3d1cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12082
94340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1208294340
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1793595444
Short name T2057
Test name
Test status
Simulation time 246324010 ps
CPU time 1 seconds
Started Jul 03 04:57:33 PM PDT 24
Finished Jul 03 04:57:35 PM PDT 24
Peak memory 206080 kb
Host smart-92a34623-9e1b-4567-82be-bc6edc3079dc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1793595444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1793595444
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.620050584
Short name T507
Test name
Test status
Simulation time 168279236 ps
CPU time 0.78 seconds
Started Jul 03 04:57:34 PM PDT 24
Finished Jul 03 04:57:36 PM PDT 24
Peak memory 206108 kb
Host smart-3d80dc89-4c97-4102-9486-2e275156a4ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62005
0584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.620050584
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.4269198035
Short name T750
Test name
Test status
Simulation time 41767061 ps
CPU time 0.64 seconds
Started Jul 03 04:57:27 PM PDT 24
Finished Jul 03 04:57:28 PM PDT 24
Peak memory 206120 kb
Host smart-32a1524c-d218-4fd8-aab4-b4a4b00ab31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42691
98035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.4269198035
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3617530852
Short name T101
Test name
Test status
Simulation time 6297162956 ps
CPU time 16.23 seconds
Started Jul 03 04:57:26 PM PDT 24
Finished Jul 03 04:57:43 PM PDT 24
Peak memory 206428 kb
Host smart-aaf43232-8a0b-41ee-aafe-4fcb853d80fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36175
30852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3617530852
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.4144997909
Short name T1049
Test name
Test status
Simulation time 146914661 ps
CPU time 0.77 seconds
Started Jul 03 04:57:46 PM PDT 24
Finished Jul 03 04:57:48 PM PDT 24
Peak memory 206084 kb
Host smart-456de5fd-e5b0-4a60-94c9-e3b00e207c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41449
97909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.4144997909
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.296495337
Short name T2275
Test name
Test status
Simulation time 186436689 ps
CPU time 0.83 seconds
Started Jul 03 04:57:30 PM PDT 24
Finished Jul 03 04:57:31 PM PDT 24
Peak memory 206096 kb
Host smart-e424e288-a4bb-49a1-98ce-6ba54f6eb8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29649
5337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.296495337
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1196937534
Short name T1975
Test name
Test status
Simulation time 203981143 ps
CPU time 0.82 seconds
Started Jul 03 04:57:46 PM PDT 24
Finished Jul 03 04:57:47 PM PDT 24
Peak memory 206140 kb
Host smart-bc0f04a4-d6fe-4e32-ba0f-cf78e8681dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11969
37534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1196937534
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1207668678
Short name T1294
Test name
Test status
Simulation time 174812980 ps
CPU time 0.85 seconds
Started Jul 03 04:57:33 PM PDT 24
Finished Jul 03 04:57:34 PM PDT 24
Peak memory 206092 kb
Host smart-f162d857-d3f1-4b93-b583-f523d2d820da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12076
68678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1207668678
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.353873775
Short name T627
Test name
Test status
Simulation time 213245417 ps
CPU time 0.83 seconds
Started Jul 03 04:57:52 PM PDT 24
Finished Jul 03 04:57:53 PM PDT 24
Peak memory 206132 kb
Host smart-55858945-f188-426d-857e-9015de812100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35387
3775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.353873775
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.564413485
Short name T2592
Test name
Test status
Simulation time 149522121 ps
CPU time 0.79 seconds
Started Jul 03 04:57:47 PM PDT 24
Finished Jul 03 04:57:48 PM PDT 24
Peak memory 206136 kb
Host smart-377a95af-4d1d-4b66-aa47-dfe540422ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56441
3485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.564413485
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2782705614
Short name T2178
Test name
Test status
Simulation time 154516286 ps
CPU time 0.77 seconds
Started Jul 03 04:57:42 PM PDT 24
Finished Jul 03 04:57:43 PM PDT 24
Peak memory 206096 kb
Host smart-a633eb3d-e934-4791-b279-5f57ba418be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27827
05614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2782705614
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.144431101
Short name T604
Test name
Test status
Simulation time 234758934 ps
CPU time 0.9 seconds
Started Jul 03 04:57:47 PM PDT 24
Finished Jul 03 04:57:48 PM PDT 24
Peak memory 206088 kb
Host smart-c9a5c546-26da-43d8-a6c6-60eeee2c2489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14443
1101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.144431101
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2760509771
Short name T944
Test name
Test status
Simulation time 6975945338 ps
CPU time 194.73 seconds
Started Jul 03 04:57:40 PM PDT 24
Finished Jul 03 05:00:55 PM PDT 24
Peak memory 206440 kb
Host smart-3b620d8f-500f-469d-96fc-a9d9062f1132
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2760509771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2760509771
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.842917463
Short name T2326
Test name
Test status
Simulation time 188448718 ps
CPU time 0.79 seconds
Started Jul 03 04:57:32 PM PDT 24
Finished Jul 03 04:57:33 PM PDT 24
Peak memory 206128 kb
Host smart-b9bae556-709a-4739-ad55-bbf3db3f9938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84291
7463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.842917463
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.349170336
Short name T667
Test name
Test status
Simulation time 162319440 ps
CPU time 0.8 seconds
Started Jul 03 04:57:30 PM PDT 24
Finished Jul 03 04:57:32 PM PDT 24
Peak memory 206108 kb
Host smart-da9c1f45-7b1d-4958-8ef8-19375714837c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34917
0336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.349170336
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.3948292948
Short name T1836
Test name
Test status
Simulation time 357655079 ps
CPU time 1.09 seconds
Started Jul 03 04:57:48 PM PDT 24
Finished Jul 03 04:57:49 PM PDT 24
Peak memory 206072 kb
Host smart-ef46de39-fb32-4781-91db-3cba9db914dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39482
92948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.3948292948
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.2168794841
Short name T359
Test name
Test status
Simulation time 3552911595 ps
CPU time 30.97 seconds
Started Jul 03 04:57:50 PM PDT 24
Finished Jul 03 04:58:22 PM PDT 24
Peak memory 206440 kb
Host smart-2b67b7e3-79d1-4500-98e3-25aaa292be2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21687
94841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2168794841
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.3823830093
Short name T885
Test name
Test status
Simulation time 65199603 ps
CPU time 0.68 seconds
Started Jul 03 04:57:50 PM PDT 24
Finished Jul 03 04:57:52 PM PDT 24
Peak memory 206188 kb
Host smart-b1104c77-5ae1-43a7-be3b-0b6744cb9c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3823830093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.3823830093
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.4270229155
Short name T1306
Test name
Test status
Simulation time 3740964191 ps
CPU time 4.47 seconds
Started Jul 03 04:57:33 PM PDT 24
Finished Jul 03 04:57:38 PM PDT 24
Peak memory 206460 kb
Host smart-70482404-295b-41d8-927f-fccad1e8d393
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4270229155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.4270229155
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3525338333
Short name T2364
Test name
Test status
Simulation time 13569567154 ps
CPU time 13.42 seconds
Started Jul 03 04:57:28 PM PDT 24
Finished Jul 03 04:57:42 PM PDT 24
Peak memory 206456 kb
Host smart-d8637279-dc53-467b-b26c-7f21ee651dd4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3525338333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3525338333
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1916276310
Short name T582
Test name
Test status
Simulation time 23401386870 ps
CPU time 22.63 seconds
Started Jul 03 04:57:50 PM PDT 24
Finished Jul 03 04:58:13 PM PDT 24
Peak memory 206324 kb
Host smart-c69f02fa-9088-464a-b78c-ac04c9d76671
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1916276310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1916276310
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.472984618
Short name T1961
Test name
Test status
Simulation time 191403873 ps
CPU time 0.8 seconds
Started Jul 03 04:57:38 PM PDT 24
Finished Jul 03 04:57:39 PM PDT 24
Peak memory 206080 kb
Host smart-3a911923-b0f4-4cd8-b690-5156d3df2245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47298
4618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.472984618
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2810516480
Short name T1463
Test name
Test status
Simulation time 188651738 ps
CPU time 0.88 seconds
Started Jul 03 04:57:51 PM PDT 24
Finished Jul 03 04:57:53 PM PDT 24
Peak memory 206116 kb
Host smart-7ee3f164-aae3-41b7-9949-23d0c9e0b5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28105
16480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2810516480
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2044028109
Short name T1800
Test name
Test status
Simulation time 138067899 ps
CPU time 0.79 seconds
Started Jul 03 04:57:44 PM PDT 24
Finished Jul 03 04:57:45 PM PDT 24
Peak memory 206136 kb
Host smart-1bc175e6-9d87-492a-89bd-0b6cde0c316e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20440
28109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2044028109
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.972098936
Short name T115
Test name
Test status
Simulation time 758953416 ps
CPU time 1.76 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 04:57:48 PM PDT 24
Peak memory 206328 kb
Host smart-0157c83c-54d5-4ddb-8cab-c6a92027efcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97209
8936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.972098936
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.3569765621
Short name T1257
Test name
Test status
Simulation time 20458464021 ps
CPU time 42.77 seconds
Started Jul 03 04:57:31 PM PDT 24
Finished Jul 03 04:58:15 PM PDT 24
Peak memory 206452 kb
Host smart-f6a62ff5-8b21-4b69-9ebe-65cc8bfd192a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35697
65621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.3569765621
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.3073692156
Short name T577
Test name
Test status
Simulation time 318593091 ps
CPU time 1.05 seconds
Started Jul 03 04:57:43 PM PDT 24
Finished Jul 03 04:57:45 PM PDT 24
Peak memory 206112 kb
Host smart-3fc8604f-aaa1-403b-943f-141d9e75184a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30736
92156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.3073692156
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2767895702
Short name T52
Test name
Test status
Simulation time 151897488 ps
CPU time 0.83 seconds
Started Jul 03 04:57:58 PM PDT 24
Finished Jul 03 04:58:00 PM PDT 24
Peak memory 206076 kb
Host smart-6ce4296e-f3b5-493a-bd45-bb9077e71d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27678
95702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2767895702
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.806615595
Short name T1328
Test name
Test status
Simulation time 34519948 ps
CPU time 0.68 seconds
Started Jul 03 04:57:36 PM PDT 24
Finished Jul 03 04:57:37 PM PDT 24
Peak memory 206068 kb
Host smart-88bb43bb-4d58-4672-92bb-448d298b3c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80661
5595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.806615595
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1150689569
Short name T1589
Test name
Test status
Simulation time 930964270 ps
CPU time 2.18 seconds
Started Jul 03 04:57:43 PM PDT 24
Finished Jul 03 04:57:46 PM PDT 24
Peak memory 206384 kb
Host smart-0f26cee5-c128-4ee3-8804-7182cf5f8f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11506
89569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1150689569
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2516683335
Short name T917
Test name
Test status
Simulation time 305827625 ps
CPU time 2.44 seconds
Started Jul 03 04:57:39 PM PDT 24
Finished Jul 03 04:57:42 PM PDT 24
Peak memory 206212 kb
Host smart-268f1bf8-baeb-45f5-86d8-41b0aae057d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25166
83335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2516683335
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2908459142
Short name T1068
Test name
Test status
Simulation time 212372428 ps
CPU time 0.9 seconds
Started Jul 03 04:57:35 PM PDT 24
Finished Jul 03 04:57:36 PM PDT 24
Peak memory 205896 kb
Host smart-5346e9fe-bbea-44d0-aa0c-9a46a6d031ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29084
59142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2908459142
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3975300530
Short name T592
Test name
Test status
Simulation time 146579100 ps
CPU time 0.77 seconds
Started Jul 03 04:57:38 PM PDT 24
Finished Jul 03 04:57:39 PM PDT 24
Peak memory 206128 kb
Host smart-e2d748e0-4079-4008-a99f-fdb7773a508a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39753
00530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3975300530
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3129975788
Short name T2301
Test name
Test status
Simulation time 161446625 ps
CPU time 0.78 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 04:57:46 PM PDT 24
Peak memory 206080 kb
Host smart-34ced6a5-30dd-4a15-8f1b-728b38ce9414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31299
75788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3129975788
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3900292647
Short name T1405
Test name
Test status
Simulation time 206018921 ps
CPU time 0.86 seconds
Started Jul 03 04:57:56 PM PDT 24
Finished Jul 03 04:57:57 PM PDT 24
Peak memory 206132 kb
Host smart-2d02a9f2-5c13-4fb1-b9b2-5dd4a318debb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39002
92647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3900292647
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3687689306
Short name T516
Test name
Test status
Simulation time 23285596079 ps
CPU time 26.2 seconds
Started Jul 03 04:57:52 PM PDT 24
Finished Jul 03 04:58:19 PM PDT 24
Peak memory 206128 kb
Host smart-def48e70-860e-4463-a1fc-cafa4faf1a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36876
89306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3687689306
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3551503247
Short name T350
Test name
Test status
Simulation time 3280441973 ps
CPU time 3.96 seconds
Started Jul 03 04:57:41 PM PDT 24
Finished Jul 03 04:57:45 PM PDT 24
Peak memory 206192 kb
Host smart-c25cbff3-0d13-43d1-b596-1c47e0ed99d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35515
03247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3551503247
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.343736650
Short name T565
Test name
Test status
Simulation time 12469274830 ps
CPU time 326.28 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 05:03:12 PM PDT 24
Peak memory 206428 kb
Host smart-63fc8cb6-eab0-4d74-9c79-3b870ef7c485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34373
6650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.343736650
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.855656747
Short name T1872
Test name
Test status
Simulation time 3963621171 ps
CPU time 28.98 seconds
Started Jul 03 04:57:41 PM PDT 24
Finished Jul 03 04:58:10 PM PDT 24
Peak memory 206392 kb
Host smart-aa9295d0-af34-46b0-b3ee-ec537bf3a54f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=855656747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.855656747
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.103963117
Short name T1758
Test name
Test status
Simulation time 265450924 ps
CPU time 0.9 seconds
Started Jul 03 04:57:36 PM PDT 24
Finished Jul 03 04:57:37 PM PDT 24
Peak memory 206128 kb
Host smart-3adc86ba-7a1a-4dfa-9b4d-4ac44266a98c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=103963117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.103963117
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.127198882
Short name T1603
Test name
Test status
Simulation time 193464668 ps
CPU time 0.87 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 04:57:46 PM PDT 24
Peak memory 206128 kb
Host smart-d446a797-e396-4869-8567-9588d1a83494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12719
8882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.127198882
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1314339467
Short name T1897
Test name
Test status
Simulation time 7141654570 ps
CPU time 185.4 seconds
Started Jul 03 04:57:47 PM PDT 24
Finished Jul 03 05:00:53 PM PDT 24
Peak memory 206364 kb
Host smart-f87c30cb-f4ab-4b51-be42-5634d368669d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13143
39467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1314339467
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.3133558488
Short name T4
Test name
Test status
Simulation time 7263831154 ps
CPU time 49.69 seconds
Started Jul 03 04:57:46 PM PDT 24
Finished Jul 03 04:58:36 PM PDT 24
Peak memory 206348 kb
Host smart-b3cb2aeb-d376-4044-8e52-31b8438b9311
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3133558488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.3133558488
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.2074272851
Short name T2236
Test name
Test status
Simulation time 183852983 ps
CPU time 0.79 seconds
Started Jul 03 04:57:48 PM PDT 24
Finished Jul 03 04:57:49 PM PDT 24
Peak memory 206036 kb
Host smart-9cff6913-7828-483d-ae83-b80220230ca0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2074272851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.2074272851
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.469536314
Short name T1499
Test name
Test status
Simulation time 159430225 ps
CPU time 0.77 seconds
Started Jul 03 04:57:36 PM PDT 24
Finished Jul 03 04:57:37 PM PDT 24
Peak memory 206056 kb
Host smart-b731abcd-c62d-4810-8fca-adfdc1c8cb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46953
6314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.469536314
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1463195622
Short name T123
Test name
Test status
Simulation time 172513597 ps
CPU time 0.9 seconds
Started Jul 03 04:57:43 PM PDT 24
Finished Jul 03 04:57:44 PM PDT 24
Peak memory 206128 kb
Host smart-8a9e7369-14a4-4fa0-9374-cf044f92e739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14631
95622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1463195622
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1982196303
Short name T1575
Test name
Test status
Simulation time 156873607 ps
CPU time 0.8 seconds
Started Jul 03 04:57:35 PM PDT 24
Finished Jul 03 04:57:36 PM PDT 24
Peak memory 206016 kb
Host smart-819b1b64-507c-45d2-912d-c7070da00e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19821
96303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1982196303
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3118384252
Short name T632
Test name
Test status
Simulation time 258507630 ps
CPU time 0.88 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 04:57:47 PM PDT 24
Peak memory 206108 kb
Host smart-aa1edb14-046a-4452-9d86-622ed07c486b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31183
84252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3118384252
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2882193059
Short name T2329
Test name
Test status
Simulation time 169214592 ps
CPU time 0.8 seconds
Started Jul 03 04:57:40 PM PDT 24
Finished Jul 03 04:57:41 PM PDT 24
Peak memory 206108 kb
Host smart-d403aa50-db53-4b46-9689-ea1c1bdcf6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28821
93059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2882193059
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2960509177
Short name T1518
Test name
Test status
Simulation time 152622834 ps
CPU time 0.79 seconds
Started Jul 03 04:57:31 PM PDT 24
Finished Jul 03 04:57:32 PM PDT 24
Peak memory 206092 kb
Host smart-f73761d1-29df-4614-b30d-7a3d48e3d141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29605
09177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2960509177
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1611119289
Short name T61
Test name
Test status
Simulation time 294750059 ps
CPU time 0.97 seconds
Started Jul 03 04:57:51 PM PDT 24
Finished Jul 03 04:57:53 PM PDT 24
Peak memory 206040 kb
Host smart-3f029cb6-5855-458e-95fa-c7730c747dc6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1611119289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1611119289
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2978758999
Short name T2148
Test name
Test status
Simulation time 184333589 ps
CPU time 0.79 seconds
Started Jul 03 04:57:43 PM PDT 24
Finished Jul 03 04:57:44 PM PDT 24
Peak memory 206032 kb
Host smart-88fad8c6-95bc-493c-bee0-0cc14641c1ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29787
58999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2978758999
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3056856536
Short name T814
Test name
Test status
Simulation time 51856830 ps
CPU time 0.67 seconds
Started Jul 03 04:57:33 PM PDT 24
Finished Jul 03 04:57:34 PM PDT 24
Peak memory 206088 kb
Host smart-c56c59b6-2cbb-4e26-a2be-1519b0f9a333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30568
56536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3056856536
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1136367664
Short name T1195
Test name
Test status
Simulation time 9108657140 ps
CPU time 20.06 seconds
Started Jul 03 04:57:36 PM PDT 24
Finished Jul 03 04:57:57 PM PDT 24
Peak memory 206372 kb
Host smart-4388fab8-1999-408c-a7c0-326bd407a336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11363
67664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1136367664
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1567180841
Short name T1259
Test name
Test status
Simulation time 164087455 ps
CPU time 0.8 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 04:57:47 PM PDT 24
Peak memory 206080 kb
Host smart-2e8885b8-f78a-4d42-a3c3-798eb769304c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15671
80841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1567180841
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1047198359
Short name T1820
Test name
Test status
Simulation time 190772787 ps
CPU time 0.86 seconds
Started Jul 03 04:57:33 PM PDT 24
Finished Jul 03 04:57:34 PM PDT 24
Peak memory 206012 kb
Host smart-5789ae1b-6902-42b9-84ac-2ead6c6f9239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10471
98359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1047198359
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3926275226
Short name T2198
Test name
Test status
Simulation time 184869390 ps
CPU time 0.84 seconds
Started Jul 03 04:57:40 PM PDT 24
Finished Jul 03 04:57:41 PM PDT 24
Peak memory 206108 kb
Host smart-40b1ab54-4277-4434-9bcb-7c8d81d218a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39262
75226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3926275226
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.199180123
Short name T438
Test name
Test status
Simulation time 160718084 ps
CPU time 0.84 seconds
Started Jul 03 04:57:57 PM PDT 24
Finished Jul 03 04:57:58 PM PDT 24
Peak memory 206124 kb
Host smart-a3773b28-e7d9-48ed-bb33-cb0d382ec22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19918
0123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.199180123
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2517044259
Short name T2247
Test name
Test status
Simulation time 136697592 ps
CPU time 0.78 seconds
Started Jul 03 04:57:34 PM PDT 24
Finished Jul 03 04:57:36 PM PDT 24
Peak memory 205960 kb
Host smart-6184e86b-65c6-4c1d-9be2-e9a91d35f306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25170
44259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2517044259
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2259397051
Short name T2254
Test name
Test status
Simulation time 154669005 ps
CPU time 0.76 seconds
Started Jul 03 04:57:48 PM PDT 24
Finished Jul 03 04:57:49 PM PDT 24
Peak memory 206036 kb
Host smart-d60e8eb2-4d70-4254-bdfe-ad143bc144fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
97051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2259397051
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1806994059
Short name T2680
Test name
Test status
Simulation time 147186990 ps
CPU time 0.76 seconds
Started Jul 03 04:57:46 PM PDT 24
Finished Jul 03 04:57:47 PM PDT 24
Peak memory 206128 kb
Host smart-ad2e101b-8e60-4ebb-b000-62051a38284c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18069
94059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1806994059
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2168494854
Short name T62
Test name
Test status
Simulation time 238839325 ps
CPU time 0.91 seconds
Started Jul 03 04:57:45 PM PDT 24
Finished Jul 03 04:57:46 PM PDT 24
Peak memory 206124 kb
Host smart-d76dcf9c-5607-4def-bf66-86ca7339b06c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21684
94854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2168494854
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.668512271
Short name T1477
Test name
Test status
Simulation time 5048817822 ps
CPU time 131.57 seconds
Started Jul 03 04:57:35 PM PDT 24
Finished Jul 03 04:59:47 PM PDT 24
Peak memory 206392 kb
Host smart-5770461c-68bb-4619-9d02-2b1bfe4829b4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=668512271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.668512271
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3080913818
Short name T238
Test name
Test status
Simulation time 180369215 ps
CPU time 0.77 seconds
Started Jul 03 04:57:33 PM PDT 24
Finished Jul 03 04:57:35 PM PDT 24
Peak memory 206116 kb
Host smart-8372eca0-d47f-4437-b226-e4d8f0fec969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30809
13818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3080913818
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.2086560145
Short name T2110
Test name
Test status
Simulation time 176011311 ps
CPU time 0.88 seconds
Started Jul 03 04:57:49 PM PDT 24
Finished Jul 03 04:57:50 PM PDT 24
Peak memory 206128 kb
Host smart-c6582fb1-cc48-44cc-be74-961a42264249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20865
60145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.2086560145
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2300011574
Short name T1610
Test name
Test status
Simulation time 579931258 ps
CPU time 1.46 seconds
Started Jul 03 04:57:51 PM PDT 24
Finished Jul 03 04:57:52 PM PDT 24
Peak memory 206036 kb
Host smart-db81652c-a15f-4a4f-96c2-87f09f1296e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23000
11574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2300011574
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.3485639963
Short name T2068
Test name
Test status
Simulation time 6102512398 ps
CPU time 161.6 seconds
Started Jul 03 04:57:47 PM PDT 24
Finished Jul 03 05:00:29 PM PDT 24
Peak memory 206380 kb
Host smart-ed9da0a8-701e-4bb1-94ff-5e0c6831fe1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34856
39963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.3485639963
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.3164878508
Short name T785
Test name
Test status
Simulation time 46145582 ps
CPU time 0.69 seconds
Started Jul 03 04:52:15 PM PDT 24
Finished Jul 03 04:52:16 PM PDT 24
Peak memory 206164 kb
Host smart-96a1949f-be38-456e-a9d2-26e934b741ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3164878508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3164878508
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1367925960
Short name T248
Test name
Test status
Simulation time 3758112293 ps
CPU time 4.82 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:14 PM PDT 24
Peak memory 206360 kb
Host smart-a9163bd8-3fcb-4d98-aef9-0ed2e13b407e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1367925960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1367925960
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.4213605393
Short name T2658
Test name
Test status
Simulation time 13351379731 ps
CPU time 13.49 seconds
Started Jul 03 04:52:30 PM PDT 24
Finished Jul 03 04:52:43 PM PDT 24
Peak memory 206184 kb
Host smart-ea23ac40-2539-4590-b4ff-84cd34c02f3b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4213605393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.4213605393
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3300841423
Short name T1541
Test name
Test status
Simulation time 23361543570 ps
CPU time 24.64 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:34 PM PDT 24
Peak memory 206192 kb
Host smart-18608c51-ff49-4ccf-b5c7-0b1fc3ca99bb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3300841423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.3300841423
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1129848444
Short name T998
Test name
Test status
Simulation time 232284888 ps
CPU time 0.86 seconds
Started Jul 03 04:52:08 PM PDT 24
Finished Jul 03 04:52:10 PM PDT 24
Peak memory 206112 kb
Host smart-5fe95f1f-ebde-4013-879b-ba38b35e061e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11298
48444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1129848444
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.1503338637
Short name T900
Test name
Test status
Simulation time 159042394 ps
CPU time 0.84 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 205460 kb
Host smart-b3f1d43f-a562-4aaf-96fe-421982beaa05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15033
38637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.1503338637
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.1977977358
Short name T1406
Test name
Test status
Simulation time 153290770 ps
CPU time 0.85 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 205480 kb
Host smart-6b67a5cd-1843-441f-9dcd-725ffa60ee5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19779
77358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.1977977358
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1683948896
Short name T1654
Test name
Test status
Simulation time 828108708 ps
CPU time 1.85 seconds
Started Jul 03 04:52:11 PM PDT 24
Finished Jul 03 04:52:13 PM PDT 24
Peak memory 206380 kb
Host smart-e62a22af-5394-4fa7-98d6-5abd027a0aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16839
48896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1683948896
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.2985782290
Short name T1563
Test name
Test status
Simulation time 18609812037 ps
CPU time 32.67 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:53:01 PM PDT 24
Peak memory 206364 kb
Host smart-eb649813-f723-4573-a313-d17f4fc6033c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29857
82290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.2985782290
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.671105137
Short name T1372
Test name
Test status
Simulation time 286051312 ps
CPU time 1.08 seconds
Started Jul 03 04:52:21 PM PDT 24
Finished Jul 03 04:52:23 PM PDT 24
Peak memory 206112 kb
Host smart-5f9cc8e1-23b1-4f33-85eb-4f2beb50e244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67110
5137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.671105137
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.4284593861
Short name T1853
Test name
Test status
Simulation time 135546095 ps
CPU time 0.79 seconds
Started Jul 03 04:52:11 PM PDT 24
Finished Jul 03 04:52:12 PM PDT 24
Peak memory 206124 kb
Host smart-50a9f70b-9a1f-4804-899b-d0cba9f63fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42845
93861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.4284593861
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2002968796
Short name T1465
Test name
Test status
Simulation time 48267577 ps
CPU time 0.65 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:52:11 PM PDT 24
Peak memory 206124 kb
Host smart-be2d5507-7b3a-450b-a141-c7993d69488e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20029
68796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2002968796
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1106244129
Short name T1311
Test name
Test status
Simulation time 934571265 ps
CPU time 2.02 seconds
Started Jul 03 04:52:22 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 206364 kb
Host smart-0d56f270-b8fb-4c86-85a8-7ff41c3b495c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11062
44129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1106244129
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2615909606
Short name T988
Test name
Test status
Simulation time 268277292 ps
CPU time 1.86 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:52:13 PM PDT 24
Peak memory 206284 kb
Host smart-a57e48d7-7e68-440b-adc3-a61218756651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26159
09606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2615909606
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.1359615131
Short name T2453
Test name
Test status
Simulation time 164816341 ps
CPU time 0.83 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:28 PM PDT 24
Peak memory 206076 kb
Host smart-14fb4b6f-0333-43f1-8a40-3758cd1ddbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13596
15131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1359615131
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2527685905
Short name T2214
Test name
Test status
Simulation time 143395880 ps
CPU time 0.76 seconds
Started Jul 03 04:52:15 PM PDT 24
Finished Jul 03 04:52:17 PM PDT 24
Peak memory 206084 kb
Host smart-466d870a-db9d-4e61-9c5a-0d95ce9ff65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25276
85905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2527685905
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.915520189
Short name T1223
Test name
Test status
Simulation time 164604465 ps
CPU time 0.78 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 206116 kb
Host smart-d517a14d-e20b-4ea7-ac04-61df6feb199c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91552
0189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.915520189
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2003660353
Short name T2393
Test name
Test status
Simulation time 234553337 ps
CPU time 0.92 seconds
Started Jul 03 04:52:16 PM PDT 24
Finished Jul 03 04:52:17 PM PDT 24
Peak memory 206108 kb
Host smart-229d2438-7005-4e53-9387-2569506263b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20036
60353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2003660353
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1322228237
Short name T1182
Test name
Test status
Simulation time 23294761049 ps
CPU time 23.82 seconds
Started Jul 03 04:52:12 PM PDT 24
Finished Jul 03 04:52:36 PM PDT 24
Peak memory 206004 kb
Host smart-9a630593-bf3e-4567-ad1a-a309f0ee1678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13222
28237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1322228237
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1734120577
Short name T2708
Test name
Test status
Simulation time 3286115436 ps
CPU time 4.62 seconds
Started Jul 03 04:52:21 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206144 kb
Host smart-5c3220c3-1baf-4cc2-9e70-5d7dd0b8fef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17341
20577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1734120577
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3808427512
Short name T2334
Test name
Test status
Simulation time 9916038713 ps
CPU time 269.68 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:56:58 PM PDT 24
Peak memory 206452 kb
Host smart-5149f1c0-1029-4edd-8f11-0c7af62c4fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38084
27512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3808427512
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.4072255954
Short name T1787
Test name
Test status
Simulation time 3994935750 ps
CPU time 110.24 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:54:19 PM PDT 24
Peak memory 206376 kb
Host smart-4b4f12bb-0f98-4f0f-830a-ec9d1953589e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4072255954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.4072255954
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.3334807150
Short name T2139
Test name
Test status
Simulation time 230576542 ps
CPU time 0.94 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:52:24 PM PDT 24
Peak memory 206112 kb
Host smart-b9799134-5f23-4979-a752-770d2f91b2e4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3334807150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.3334807150
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.58236392
Short name T2494
Test name
Test status
Simulation time 193360291 ps
CPU time 0.89 seconds
Started Jul 03 04:52:15 PM PDT 24
Finished Jul 03 04:52:17 PM PDT 24
Peak memory 206092 kb
Host smart-49d75e49-eb40-489f-834f-fa6ff34dcd72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58236
392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.58236392
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1235473480
Short name T894
Test name
Test status
Simulation time 3924609930 ps
CPU time 26.23 seconds
Started Jul 03 04:52:21 PM PDT 24
Finished Jul 03 04:52:48 PM PDT 24
Peak memory 206392 kb
Host smart-422745d3-0352-4c82-b776-86293d28660f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12354
73480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1235473480
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.779582132
Short name T1357
Test name
Test status
Simulation time 6117504341 ps
CPU time 45.09 seconds
Started Jul 03 04:52:12 PM PDT 24
Finished Jul 03 04:52:57 PM PDT 24
Peak memory 206384 kb
Host smart-4969566d-14f8-4cfe-a05a-71ac284ee8d1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=779582132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.779582132
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.1473666481
Short name T706
Test name
Test status
Simulation time 149954105 ps
CPU time 0.8 seconds
Started Jul 03 04:52:15 PM PDT 24
Finished Jul 03 04:52:16 PM PDT 24
Peak memory 206088 kb
Host smart-872baa8b-a6b9-48a8-9cb3-dda696d5ff67
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1473666481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.1473666481
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1413179297
Short name T2406
Test name
Test status
Simulation time 144369697 ps
CPU time 0.78 seconds
Started Jul 03 04:52:12 PM PDT 24
Finished Jul 03 04:52:14 PM PDT 24
Peak memory 206088 kb
Host smart-1b038b3a-c256-46c2-95f8-62d281df2521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14131
79297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1413179297
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2585737350
Short name T148
Test name
Test status
Simulation time 191826220 ps
CPU time 0.78 seconds
Started Jul 03 04:52:12 PM PDT 24
Finished Jul 03 04:52:13 PM PDT 24
Peak memory 205940 kb
Host smart-443dcbdd-98a0-46fc-9622-dbb055ebc285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25857
37350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2585737350
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3425237828
Short name T1701
Test name
Test status
Simulation time 159309578 ps
CPU time 0.77 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206076 kb
Host smart-3b6b36c7-98cf-4882-b40f-e1871d4e5a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34252
37828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3425237828
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.49547709
Short name T2032
Test name
Test status
Simulation time 214795606 ps
CPU time 0.92 seconds
Started Jul 03 04:52:21 PM PDT 24
Finished Jul 03 04:52:23 PM PDT 24
Peak memory 206144 kb
Host smart-43145a37-53ce-47d9-97f7-03bbcd027c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49547
709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.49547709
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.834320713
Short name T28
Test name
Test status
Simulation time 176593141 ps
CPU time 0.79 seconds
Started Jul 03 04:52:15 PM PDT 24
Finished Jul 03 04:52:16 PM PDT 24
Peak memory 206076 kb
Host smart-8d8ef183-3815-43bc-8fac-c9a400ee3352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83432
0713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.834320713
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2184817920
Short name T2023
Test name
Test status
Simulation time 148200239 ps
CPU time 0.82 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206096 kb
Host smart-46a07e67-fdf2-4919-b4d9-2b70651d5923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21848
17920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2184817920
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2612621437
Short name T1309
Test name
Test status
Simulation time 215818505 ps
CPU time 0.92 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:33 PM PDT 24
Peak memory 206120 kb
Host smart-9005dcb3-4e5f-4a38-a08a-d7719007fbe3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2612621437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2612621437
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1585723876
Short name T1517
Test name
Test status
Simulation time 139617938 ps
CPU time 0.78 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206096 kb
Host smart-5395e8bc-9c29-47ed-bd01-9dcbc89c4750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15857
23876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1585723876
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.125589240
Short name T1113
Test name
Test status
Simulation time 40997241 ps
CPU time 0.67 seconds
Started Jul 03 04:52:17 PM PDT 24
Finished Jul 03 04:52:18 PM PDT 24
Peak memory 206104 kb
Host smart-07334ba2-e347-405f-ac85-dee763e52fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12558
9240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.125589240
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.224239371
Short name T2645
Test name
Test status
Simulation time 16275472963 ps
CPU time 37.65 seconds
Started Jul 03 04:52:09 PM PDT 24
Finished Jul 03 04:52:48 PM PDT 24
Peak memory 206472 kb
Host smart-169bc3e3-1aea-4933-92f1-f831e9e0f4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22423
9371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.224239371
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1865171384
Short name T1271
Test name
Test status
Simulation time 163291673 ps
CPU time 0.8 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:28 PM PDT 24
Peak memory 206080 kb
Host smart-a4877cf6-b500-45d6-9488-989262339dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18651
71384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1865171384
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2826347221
Short name T2248
Test name
Test status
Simulation time 264483965 ps
CPU time 0.9 seconds
Started Jul 03 04:52:10 PM PDT 24
Finished Jul 03 04:52:12 PM PDT 24
Peak memory 206128 kb
Host smart-8cde1f2d-193e-414e-88c8-4d9007fffa75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28263
47221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2826347221
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.3765133790
Short name T558
Test name
Test status
Simulation time 13000226589 ps
CPU time 243.32 seconds
Started Jul 03 04:52:13 PM PDT 24
Finished Jul 03 04:56:17 PM PDT 24
Peak memory 206444 kb
Host smart-38f47aea-6b06-4270-ac19-94827ce0f87d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3765133790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3765133790
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.884003670
Short name T2617
Test name
Test status
Simulation time 9383734258 ps
CPU time 43.76 seconds
Started Jul 03 04:52:14 PM PDT 24
Finished Jul 03 04:52:58 PM PDT 24
Peak memory 206380 kb
Host smart-07387d1e-8b04-42bb-a4bd-65e8d5e895e4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=884003670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.884003670
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2770248612
Short name T935
Test name
Test status
Simulation time 7430177118 ps
CPU time 29.77 seconds
Started Jul 03 04:52:21 PM PDT 24
Finished Jul 03 04:52:51 PM PDT 24
Peak memory 206412 kb
Host smart-4cd95c5d-347d-4411-b0eb-593a4c5d5422
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2770248612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2770248612
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1619317624
Short name T1184
Test name
Test status
Simulation time 236535752 ps
CPU time 0.93 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206116 kb
Host smart-f3889215-8967-41f6-92c0-b95db59defe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16193
17624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1619317624
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2498307957
Short name T1601
Test name
Test status
Simulation time 174425045 ps
CPU time 0.86 seconds
Started Jul 03 04:52:14 PM PDT 24
Finished Jul 03 04:52:15 PM PDT 24
Peak memory 206112 kb
Host smart-a570b2e1-d625-4432-bcc6-a6929f185272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24983
07957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2498307957
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.928350296
Short name T2468
Test name
Test status
Simulation time 160791680 ps
CPU time 0.77 seconds
Started Jul 03 04:52:31 PM PDT 24
Finished Jul 03 04:52:32 PM PDT 24
Peak memory 206088 kb
Host smart-35289ea7-1150-43c5-bf39-39861aca2f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92835
0296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.928350296
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2236536913
Short name T497
Test name
Test status
Simulation time 227099990 ps
CPU time 0.81 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206092 kb
Host smart-2b669d5c-c4c8-4b81-a4fd-ec8d72e5d42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22365
36913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2236536913
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3589377631
Short name T2618
Test name
Test status
Simulation time 157730579 ps
CPU time 0.73 seconds
Started Jul 03 04:52:20 PM PDT 24
Finished Jul 03 04:52:21 PM PDT 24
Peak memory 206092 kb
Host smart-96fadda8-7b15-4fb3-ad58-1212578db534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35893
77631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3589377631
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.4195023498
Short name T354
Test name
Test status
Simulation time 216243459 ps
CPU time 0.98 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206116 kb
Host smart-14bb1cf2-53c3-4473-b8fb-9e172cdda974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41950
23498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.4195023498
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3143859686
Short name T1167
Test name
Test status
Simulation time 7064538170 ps
CPU time 48.2 seconds
Started Jul 03 04:52:07 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206260 kb
Host smart-1c3fc27f-2230-4d21-ab7d-feb38c1ebd99
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3143859686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.3143859686
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3423892731
Short name T2262
Test name
Test status
Simulation time 180650837 ps
CPU time 0.83 seconds
Started Jul 03 04:52:14 PM PDT 24
Finished Jul 03 04:52:15 PM PDT 24
Peak memory 206108 kb
Host smart-2aaf24d8-a0fa-407d-b056-00d31a63be11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34238
92731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3423892731
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3080292003
Short name T645
Test name
Test status
Simulation time 187819504 ps
CPU time 0.85 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206120 kb
Host smart-3a412f92-345b-480d-b16d-f1fb26d4ea03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30802
92003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3080292003
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.363847863
Short name T2125
Test name
Test status
Simulation time 1179907337 ps
CPU time 2.68 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:28 PM PDT 24
Peak memory 206296 kb
Host smart-3da1f87e-a29c-4f65-b1ea-a58ca1ae8cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36384
7863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.363847863
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2442095931
Short name T1662
Test name
Test status
Simulation time 6614123578 ps
CPU time 57.98 seconds
Started Jul 03 04:52:21 PM PDT 24
Finished Jul 03 04:53:19 PM PDT 24
Peak memory 206404 kb
Host smart-46ec9671-41f0-4ecf-9104-794e8999cd8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24420
95931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2442095931
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.2674424596
Short name T1456
Test name
Test status
Simulation time 63423756 ps
CPU time 0.68 seconds
Started Jul 03 04:52:16 PM PDT 24
Finished Jul 03 04:52:17 PM PDT 24
Peak memory 206176 kb
Host smart-796c6dc3-8226-425c-9eac-615e7286cc2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2674424596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.2674424596
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.773066484
Short name T1911
Test name
Test status
Simulation time 3693218432 ps
CPU time 4.17 seconds
Started Jul 03 04:52:16 PM PDT 24
Finished Jul 03 04:52:21 PM PDT 24
Peak memory 206104 kb
Host smart-62944f9e-88e1-4e8d-a27e-a610cbc0104b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=773066484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.773066484
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.4000051805
Short name T2016
Test name
Test status
Simulation time 13377075897 ps
CPU time 12.76 seconds
Started Jul 03 04:52:13 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206160 kb
Host smart-4febf721-c8a3-4de2-b371-614aca70ff98
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4000051805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.4000051805
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2194444638
Short name T1085
Test name
Test status
Simulation time 23426738506 ps
CPU time 24.8 seconds
Started Jul 03 04:52:14 PM PDT 24
Finished Jul 03 04:52:39 PM PDT 24
Peak memory 206444 kb
Host smart-26c0b45a-79c1-4958-9e36-04211fef5041
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2194444638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.2194444638
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3336032201
Short name T2527
Test name
Test status
Simulation time 148357594 ps
CPU time 0.78 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 206072 kb
Host smart-dc7004c1-2da9-4452-a7bb-ab758fba4812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360
32201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3336032201
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2511631064
Short name T360
Test name
Test status
Simulation time 203496984 ps
CPU time 0.83 seconds
Started Jul 03 04:52:12 PM PDT 24
Finished Jul 03 04:52:13 PM PDT 24
Peak memory 206104 kb
Host smart-eda1ee9f-1923-4a9f-9f4d-1527286bceb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25116
31064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2511631064
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.727921829
Short name T1545
Test name
Test status
Simulation time 149484799 ps
CPU time 0.89 seconds
Started Jul 03 04:52:20 PM PDT 24
Finished Jul 03 04:52:21 PM PDT 24
Peak memory 206024 kb
Host smart-792de195-03de-4a4a-afde-ac73b2573bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72792
1829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.727921829
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1992071996
Short name T72
Test name
Test status
Simulation time 381057382 ps
CPU time 1.08 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206096 kb
Host smart-1ae8b18d-8ece-4ed2-adf2-7f483b26af94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19920
71996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1992071996
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2783311323
Short name T937
Test name
Test status
Simulation time 6129031208 ps
CPU time 12.3 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:52:40 PM PDT 24
Peak memory 206360 kb
Host smart-68ae8ebf-5980-4ffb-869c-7b86b9291a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27833
11323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2783311323
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.4049336806
Short name T1954
Test name
Test status
Simulation time 373636434 ps
CPU time 1.17 seconds
Started Jul 03 04:52:16 PM PDT 24
Finished Jul 03 04:52:17 PM PDT 24
Peak memory 206092 kb
Host smart-52fb217b-144d-4137-9690-de82d166d71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40493
36806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.4049336806
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3035377068
Short name T881
Test name
Test status
Simulation time 153921114 ps
CPU time 0.8 seconds
Started Jul 03 04:52:16 PM PDT 24
Finished Jul 03 04:52:17 PM PDT 24
Peak memory 205992 kb
Host smart-b35b6e52-bd63-4149-ad9a-18059d9d44a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30353
77068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3035377068
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.392922659
Short name T1755
Test name
Test status
Simulation time 35581662 ps
CPU time 0.64 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206112 kb
Host smart-634aa37f-3753-4969-91f0-5d94c2557695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39292
2659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.392922659
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3873675691
Short name T1875
Test name
Test status
Simulation time 835114931 ps
CPU time 2.04 seconds
Started Jul 03 04:52:16 PM PDT 24
Finished Jul 03 04:52:18 PM PDT 24
Peak memory 206204 kb
Host smart-12695d70-75b4-404b-b660-c2616f808b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38736
75691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3873675691
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3623630679
Short name T1516
Test name
Test status
Simulation time 261500848 ps
CPU time 1.62 seconds
Started Jul 03 04:52:13 PM PDT 24
Finished Jul 03 04:52:15 PM PDT 24
Peak memory 206340 kb
Host smart-4dd2a805-40ba-4963-9a9d-0726014e0be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36236
30679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3623630679
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2106701985
Short name T537
Test name
Test status
Simulation time 283559264 ps
CPU time 0.97 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 205988 kb
Host smart-1d0d400c-9bba-4453-a521-22f75ad88982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21067
01985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2106701985
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.223351866
Short name T602
Test name
Test status
Simulation time 154628614 ps
CPU time 0.76 seconds
Started Jul 03 04:52:18 PM PDT 24
Finished Jul 03 04:52:19 PM PDT 24
Peak memory 206100 kb
Host smart-a62de7e6-1952-412e-b95d-dbd94f7b4ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22335
1866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.223351866
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.238137283
Short name T2687
Test name
Test status
Simulation time 185797981 ps
CPU time 0.9 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 206096 kb
Host smart-89508d42-559a-4a59-974b-917c32e7c2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23813
7283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.238137283
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.3175402117
Short name T253
Test name
Test status
Simulation time 8872047512 ps
CPU time 249.13 seconds
Started Jul 03 04:52:11 PM PDT 24
Finished Jul 03 04:56:21 PM PDT 24
Peak memory 206476 kb
Host smart-5e37b068-0e2f-43c9-8eb3-58311890830a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3175402117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3175402117
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3097381312
Short name T1887
Test name
Test status
Simulation time 299535216 ps
CPU time 0.97 seconds
Started Jul 03 04:52:35 PM PDT 24
Finished Jul 03 04:52:36 PM PDT 24
Peak memory 206100 kb
Host smart-b0e8635c-a9e4-426f-a7b3-a9f4127d7fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30973
81312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3097381312
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.491139886
Short name T676
Test name
Test status
Simulation time 23297018252 ps
CPU time 26.33 seconds
Started Jul 03 04:52:12 PM PDT 24
Finished Jul 03 04:52:39 PM PDT 24
Peak memory 206180 kb
Host smart-10234459-0119-47ca-a326-5c498ff01c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49113
9886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.491139886
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.2283108581
Short name T2600
Test name
Test status
Simulation time 3302331972 ps
CPU time 3.74 seconds
Started Jul 03 04:52:12 PM PDT 24
Finished Jul 03 04:52:17 PM PDT 24
Peak memory 206156 kb
Host smart-ea3e1d6b-ae62-4b0c-b055-d9829965adbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22831
08581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.2283108581
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.3297192685
Short name T1112
Test name
Test status
Simulation time 8061661115 ps
CPU time 57.47 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:53:25 PM PDT 24
Peak memory 206264 kb
Host smart-00abd60f-d654-4292-9ed3-aae6198e1d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32971
92685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.3297192685
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.1545709895
Short name T2368
Test name
Test status
Simulation time 5773611698 ps
CPU time 52.88 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:53:22 PM PDT 24
Peak memory 206376 kb
Host smart-ce911ae0-71a9-43d9-a85c-f6a62114d5d6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1545709895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.1545709895
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.800330569
Short name T1718
Test name
Test status
Simulation time 249910245 ps
CPU time 0.91 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 206104 kb
Host smart-178a5a81-6757-449e-9dab-feb480653d3c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=800330569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.800330569
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1659909784
Short name T1486
Test name
Test status
Simulation time 185385664 ps
CPU time 0.86 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 206100 kb
Host smart-f20cbd2b-5076-4d68-9d79-b99aeba1adaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16599
09784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1659909784
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.4005684410
Short name T771
Test name
Test status
Simulation time 5641629354 ps
CPU time 40.17 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 206232 kb
Host smart-36dd37ed-86b8-48bd-a2a8-d5bdaf2f1573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40056
84410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.4005684410
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.2164307052
Short name T511
Test name
Test status
Simulation time 6216215549 ps
CPU time 177 seconds
Started Jul 03 04:52:15 PM PDT 24
Finished Jul 03 04:55:13 PM PDT 24
Peak memory 206344 kb
Host smart-187ea0ee-77c0-4c66-9133-2005ae7df1a1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2164307052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.2164307052
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.735818320
Short name T1940
Test name
Test status
Simulation time 172275724 ps
CPU time 0.79 seconds
Started Jul 03 04:52:21 PM PDT 24
Finished Jul 03 04:52:22 PM PDT 24
Peak memory 206104 kb
Host smart-0af89440-89ec-4f8e-b5e6-024323d6bbdc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=735818320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.735818320
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2228981705
Short name T994
Test name
Test status
Simulation time 152242631 ps
CPU time 0.8 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 206108 kb
Host smart-264e49f5-ff7a-40e7-8edb-2a0ad20473b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22289
81705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2228981705
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.930302936
Short name T2199
Test name
Test status
Simulation time 217539597 ps
CPU time 0.86 seconds
Started Jul 03 04:52:22 PM PDT 24
Finished Jul 03 04:52:23 PM PDT 24
Peak memory 206068 kb
Host smart-e4058e2f-f994-4d3b-99b1-7b379c42a3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93030
2936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.930302936
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.406532716
Short name T2432
Test name
Test status
Simulation time 171659755 ps
CPU time 0.86 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:28 PM PDT 24
Peak memory 206108 kb
Host smart-a3b6c86f-98af-4643-aeed-af2814f8e1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40653
2716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.406532716
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2652013785
Short name T1960
Test name
Test status
Simulation time 184735066 ps
CPU time 0.85 seconds
Started Jul 03 04:52:25 PM PDT 24
Finished Jul 03 04:52:27 PM PDT 24
Peak memory 205796 kb
Host smart-ad9b8094-8626-4c97-a0f2-028ce05f1193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26520
13785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2652013785
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2851643878
Short name T1852
Test name
Test status
Simulation time 205410634 ps
CPU time 0.88 seconds
Started Jul 03 04:52:25 PM PDT 24
Finished Jul 03 04:52:27 PM PDT 24
Peak memory 206132 kb
Host smart-54bd6c2d-bc07-427e-81ea-c6d9dd4ca314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28516
43878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2851643878
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.4072250205
Short name T1878
Test name
Test status
Simulation time 159012121 ps
CPU time 0.85 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206088 kb
Host smart-c7fb18b5-e4ab-4b98-a160-bf68bf7926bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40722
50205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.4072250205
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.39789760
Short name T1479
Test name
Test status
Simulation time 283645175 ps
CPU time 1.1 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206072 kb
Host smart-498c41e5-207a-40e7-8c34-af052c5532ec
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=39789760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.39789760
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.276931394
Short name T1802
Test name
Test status
Simulation time 169174220 ps
CPU time 0.78 seconds
Started Jul 03 04:52:19 PM PDT 24
Finished Jul 03 04:52:20 PM PDT 24
Peak memory 206132 kb
Host smart-d72b8a2d-7661-40cc-80a9-dac8956df34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27693
1394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.276931394
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.77555578
Short name T793
Test name
Test status
Simulation time 38771468 ps
CPU time 0.68 seconds
Started Jul 03 04:52:25 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206100 kb
Host smart-439b03cf-55c6-4b3f-9e7f-71725ba5c1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77555
578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.77555578
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2063787135
Short name T1051
Test name
Test status
Simulation time 11084019722 ps
CPU time 24.16 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:52:48 PM PDT 24
Peak memory 206432 kb
Host smart-0f586f15-967e-466a-b014-c0097bc4d698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20637
87135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2063787135
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3824991959
Short name T2140
Test name
Test status
Simulation time 204889183 ps
CPU time 0.89 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 206096 kb
Host smart-f779134f-bab8-408d-bf0f-c27259da19f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38249
91959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3824991959
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3930961437
Short name T173
Test name
Test status
Simulation time 28917520765 ps
CPU time 697.29 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 05:04:02 PM PDT 24
Peak memory 206496 kb
Host smart-6c495ebc-1573-4348-bfe6-6c99d19b80f2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3930961437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3930961437
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2445602664
Short name T168
Test name
Test status
Simulation time 18469726767 ps
CPU time 98.92 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:54:02 PM PDT 24
Peak memory 206348 kb
Host smart-321abd49-29b8-475d-b3ac-1f97836e5a2f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2445602664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2445602664
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.4047209832
Short name T2529
Test name
Test status
Simulation time 12107521445 ps
CPU time 76.72 seconds
Started Jul 03 04:52:29 PM PDT 24
Finished Jul 03 04:53:46 PM PDT 24
Peak memory 206392 kb
Host smart-7fbe3d6a-1dbb-4434-91ea-2357e081b1b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4047209832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.4047209832
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.686879474
Short name T913
Test name
Test status
Simulation time 231892362 ps
CPU time 0.87 seconds
Started Jul 03 04:52:18 PM PDT 24
Finished Jul 03 04:52:19 PM PDT 24
Peak memory 205980 kb
Host smart-536a10e6-fb00-4f65-b9d1-62f0723056ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68687
9474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.686879474
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3095182245
Short name T1655
Test name
Test status
Simulation time 189560027 ps
CPU time 0.85 seconds
Started Jul 03 04:52:25 PM PDT 24
Finished Jul 03 04:52:27 PM PDT 24
Peak memory 206116 kb
Host smart-3e36b62b-ba49-4fa1-b9e7-2b60fc023790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30951
82245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3095182245
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.995149706
Short name T424
Test name
Test status
Simulation time 151588314 ps
CPU time 0.75 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206128 kb
Host smart-2f88fe67-2ad6-4184-964c-721b475102fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99514
9706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.995149706
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1207924974
Short name T235
Test name
Test status
Simulation time 177052226 ps
CPU time 0.81 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206084 kb
Host smart-da112b67-f800-4b94-9a6b-cde42e62ee5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12079
24974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1207924974
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.233841140
Short name T1327
Test name
Test status
Simulation time 193779722 ps
CPU time 0.86 seconds
Started Jul 03 04:52:17 PM PDT 24
Finished Jul 03 04:52:18 PM PDT 24
Peak memory 206064 kb
Host smart-fe43ec9c-291a-4c03-ae5e-58b83cfc5c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23384
1140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.233841140
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.314502174
Short name T1296
Test name
Test status
Simulation time 207706156 ps
CPU time 0.94 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 206092 kb
Host smart-5cfce9a1-adc7-44b6-bb87-5b5cafed1258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31450
2174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.314502174
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1769043758
Short name T2427
Test name
Test status
Simulation time 4360948171 ps
CPU time 38.48 seconds
Started Jul 03 04:52:19 PM PDT 24
Finished Jul 03 04:52:58 PM PDT 24
Peak memory 206440 kb
Host smart-4b26e982-477f-4b05-9fe7-c363fad987b5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1769043758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1769043758
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.79454871
Short name T1724
Test name
Test status
Simulation time 164883973 ps
CPU time 0.81 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 205332 kb
Host smart-3be3e6a9-031a-4d9a-85e6-def5dc075be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79454
871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.79454871
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1381311419
Short name T1363
Test name
Test status
Simulation time 180538609 ps
CPU time 0.84 seconds
Started Jul 03 04:52:17 PM PDT 24
Finished Jul 03 04:52:18 PM PDT 24
Peak memory 205964 kb
Host smart-af8d7218-ec51-4b01-a341-224d016d33a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13813
11419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1381311419
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.4258891489
Short name T2158
Test name
Test status
Simulation time 676744621 ps
CPU time 1.55 seconds
Started Jul 03 04:52:17 PM PDT 24
Finished Jul 03 04:52:19 PM PDT 24
Peak memory 206328 kb
Host smart-cf72a5f1-a383-450a-adc7-09865140e4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42588
91489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.4258891489
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.959818361
Short name T459
Test name
Test status
Simulation time 6388753907 ps
CPU time 59.84 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:53:25 PM PDT 24
Peak memory 205628 kb
Host smart-09fb544b-40e7-42f4-8c39-e111a8b19005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95981
8361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.959818361
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.1385853167
Short name T2357
Test name
Test status
Simulation time 44800431 ps
CPU time 0.68 seconds
Started Jul 03 04:52:35 PM PDT 24
Finished Jul 03 04:52:36 PM PDT 24
Peak memory 206180 kb
Host smart-8992e774-1cb5-4a63-aa70-4dbc04d79a93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1385853167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1385853167
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3552072947
Short name T2566
Test name
Test status
Simulation time 4413480410 ps
CPU time 4.99 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206176 kb
Host smart-7b1a45dc-17cd-46c9-8119-96c0d65ca93b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3552072947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.3552072947
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.491801522
Short name T2402
Test name
Test status
Simulation time 13394733112 ps
CPU time 14.91 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:52:38 PM PDT 24
Peak memory 206400 kb
Host smart-eae52098-a66b-4380-bbae-58710c5fa924
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=491801522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.491801522
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3943829838
Short name T2483
Test name
Test status
Simulation time 23336228655 ps
CPU time 22.22 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:47 PM PDT 24
Peak memory 206372 kb
Host smart-c7679acc-f020-4b01-bb0f-a02e64315ee7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3943829838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.3943829838
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.785208881
Short name T930
Test name
Test status
Simulation time 181231315 ps
CPU time 0.78 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:52:24 PM PDT 24
Peak memory 206000 kb
Host smart-53e29e70-13fa-4819-841a-92fac95d0d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78520
8881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.785208881
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1133910948
Short name T1063
Test name
Test status
Simulation time 169387497 ps
CPU time 0.85 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 206108 kb
Host smart-5fa77a54-edf0-4972-b41b-dfc5887d8a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11339
10948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1133910948
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.975204919
Short name T166
Test name
Test status
Simulation time 339406415 ps
CPU time 1.22 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 206124 kb
Host smart-0f29d8f3-72ce-4035-9f53-4724480bc310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97520
4919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.975204919
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2840175957
Short name T2591
Test name
Test status
Simulation time 850904049 ps
CPU time 1.96 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206348 kb
Host smart-ec6a9e1b-9c41-4e9d-a399-b73f1dfeefe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28401
75957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2840175957
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2165854444
Short name T2541
Test name
Test status
Simulation time 7772193722 ps
CPU time 16.21 seconds
Started Jul 03 04:52:25 PM PDT 24
Finished Jul 03 04:52:42 PM PDT 24
Peak memory 206388 kb
Host smart-f4576fce-5dd3-439e-bf47-0b7d122d7a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21658
54444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2165854444
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.469646876
Short name T2624
Test name
Test status
Simulation time 430261801 ps
CPU time 1.27 seconds
Started Jul 03 04:52:30 PM PDT 24
Finished Jul 03 04:52:31 PM PDT 24
Peak memory 206072 kb
Host smart-c4ba6aa4-2c41-4ca9-8d69-54d33996abe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46964
6876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.469646876
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.4015120118
Short name T439
Test name
Test status
Simulation time 136591506 ps
CPU time 0.77 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:28 PM PDT 24
Peak memory 206096 kb
Host smart-7a8ab723-ee78-42c6-81f7-8c3861925c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40151
20118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.4015120118
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.1276177568
Short name T2276
Test name
Test status
Simulation time 80054369 ps
CPU time 0.75 seconds
Started Jul 03 04:52:31 PM PDT 24
Finished Jul 03 04:52:32 PM PDT 24
Peak memory 206088 kb
Host smart-7880b630-e65f-4d6a-be17-f1ed8cc33857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12761
77568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1276177568
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1683237227
Short name T2605
Test name
Test status
Simulation time 790744618 ps
CPU time 2.18 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206380 kb
Host smart-5ab67c39-3cb6-49fb-8d66-a8e9a5d23d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16832
37227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1683237227
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2091955330
Short name T522
Test name
Test status
Simulation time 399890767 ps
CPU time 2.41 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:52:31 PM PDT 24
Peak memory 206280 kb
Host smart-11648a4c-4f3b-40eb-8d5b-a53c7fa7ec17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20919
55330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2091955330
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.309099326
Short name T2142
Test name
Test status
Simulation time 154157616 ps
CPU time 0.88 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:52:24 PM PDT 24
Peak memory 206128 kb
Host smart-6e62d188-d85d-4b40-b891-8e41a00169c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30909
9326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.309099326
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3215433207
Short name T1682
Test name
Test status
Simulation time 144954600 ps
CPU time 0.79 seconds
Started Jul 03 04:52:25 PM PDT 24
Finished Jul 03 04:52:27 PM PDT 24
Peak memory 205760 kb
Host smart-c82501e5-9f07-469b-8822-50c884ba0157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32154
33207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3215433207
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.235193092
Short name T607
Test name
Test status
Simulation time 190096527 ps
CPU time 0.86 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:28 PM PDT 24
Peak memory 206132 kb
Host smart-e7a9933e-285d-4609-9377-9c669fed17fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23519
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.235193092
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3340753236
Short name T1508
Test name
Test status
Simulation time 240937493 ps
CPU time 0.87 seconds
Started Jul 03 04:52:24 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206004 kb
Host smart-0b424b63-1e9e-48a4-95d6-f2dcc282ad6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33407
53236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3340753236
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2430348142
Short name T2179
Test name
Test status
Simulation time 23262795346 ps
CPU time 21.25 seconds
Started Jul 03 04:52:25 PM PDT 24
Finished Jul 03 04:52:47 PM PDT 24
Peak memory 206180 kb
Host smart-19e05de3-a740-446f-a615-84a6d80ea481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24303
48142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2430348142
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.580238462
Short name T1828
Test name
Test status
Simulation time 3345066265 ps
CPU time 4.49 seconds
Started Jul 03 04:52:22 PM PDT 24
Finished Jul 03 04:52:27 PM PDT 24
Peak memory 206164 kb
Host smart-49949698-dbd3-4f8d-80e7-2b5e3d02394b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58023
8462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.580238462
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.967383535
Short name T421
Test name
Test status
Simulation time 7490586663 ps
CPU time 211.85 seconds
Started Jul 03 04:52:22 PM PDT 24
Finished Jul 03 04:55:55 PM PDT 24
Peak memory 206384 kb
Host smart-b4cd4579-8fdd-4606-884e-06c2290e2c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96738
3535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.967383535
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.4187255215
Short name T1760
Test name
Test status
Simulation time 6095295921 ps
CPU time 57.87 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:53:26 PM PDT 24
Peak memory 206368 kb
Host smart-895b248c-15c0-48c4-aa49-40818c4a6f3e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4187255215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.4187255215
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.4260182825
Short name T2029
Test name
Test status
Simulation time 240957162 ps
CPU time 0.92 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:28 PM PDT 24
Peak memory 206084 kb
Host smart-e04bc4ec-cf64-45bd-9af6-a080060a772b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4260182825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.4260182825
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2626383903
Short name T797
Test name
Test status
Simulation time 201118390 ps
CPU time 0.84 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:27 PM PDT 24
Peak memory 206064 kb
Host smart-2fcbb4f9-7ef6-4295-a0bd-73fdea193476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26263
83903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2626383903
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3742558414
Short name T2577
Test name
Test status
Simulation time 3287332781 ps
CPU time 23.53 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:51 PM PDT 24
Peak memory 206328 kb
Host smart-4d3c0c16-39e0-4947-9a71-aec1b3257ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37425
58414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3742558414
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1199064858
Short name T2574
Test name
Test status
Simulation time 6762236664 ps
CPU time 47.34 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:53:16 PM PDT 24
Peak memory 206392 kb
Host smart-e376ea38-f95e-4a96-9d3b-1fe42bea0b62
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1199064858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1199064858
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1750366955
Short name T638
Test name
Test status
Simulation time 152116062 ps
CPU time 0.81 seconds
Started Jul 03 04:52:32 PM PDT 24
Finished Jul 03 04:52:33 PM PDT 24
Peak memory 206092 kb
Host smart-715cb255-206c-4211-b619-73eb65902bc5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1750366955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1750366955
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3713622884
Short name T1656
Test name
Test status
Simulation time 150589329 ps
CPU time 0.81 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:27 PM PDT 24
Peak memory 206072 kb
Host smart-736f58aa-37e5-4f24-b14d-f274426c5b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37136
22884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3713622884
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2257568609
Short name T146
Test name
Test status
Simulation time 210937464 ps
CPU time 0.85 seconds
Started Jul 03 04:52:25 PM PDT 24
Finished Jul 03 04:52:27 PM PDT 24
Peak memory 206052 kb
Host smart-6581c539-d71a-447b-bb39-e59ffcc3038e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22575
68609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2257568609
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1797900245
Short name T1827
Test name
Test status
Simulation time 209477894 ps
CPU time 0.88 seconds
Started Jul 03 04:52:34 PM PDT 24
Finished Jul 03 04:52:35 PM PDT 24
Peak memory 206072 kb
Host smart-f6db771f-b3dd-4034-9636-e49361f4234f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17979
00245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1797900245
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2507542469
Short name T2131
Test name
Test status
Simulation time 188246196 ps
CPU time 0.85 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 206040 kb
Host smart-505b7ede-b804-435d-b096-5a626a848aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25075
42469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2507542469
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3566006651
Short name T1439
Test name
Test status
Simulation time 159740099 ps
CPU time 0.79 seconds
Started Jul 03 04:52:25 PM PDT 24
Finished Jul 03 04:52:26 PM PDT 24
Peak memory 206108 kb
Host smart-f2e0443f-b627-400f-ac41-fb1809937fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35660
06651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3566006651
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2230979632
Short name T2473
Test name
Test status
Simulation time 164378566 ps
CPU time 0.83 seconds
Started Jul 03 04:52:27 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 206084 kb
Host smart-358f9fc9-4b8e-4144-bd8e-af0cc41bb591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22309
79632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2230979632
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1559296170
Short name T1361
Test name
Test status
Simulation time 190739385 ps
CPU time 0.87 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:28 PM PDT 24
Peak memory 206100 kb
Host smart-f07cedb8-a92b-46bb-9b06-518d67e88f88
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1559296170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1559296170
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.698053981
Short name T2640
Test name
Test status
Simulation time 200229478 ps
CPU time 0.9 seconds
Started Jul 03 04:52:28 PM PDT 24
Finished Jul 03 04:52:29 PM PDT 24
Peak memory 206088 kb
Host smart-c2b955d4-c2b8-4798-be6f-347b753a4b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69805
3981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.698053981
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.221661276
Short name T1276
Test name
Test status
Simulation time 39000742 ps
CPU time 0.65 seconds
Started Jul 03 04:52:23 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 206128 kb
Host smart-874c2d0d-b3a3-4e8e-90cc-ee00495a29a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22166
1276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.221661276
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2309075715
Short name T1811
Test name
Test status
Simulation time 18071499184 ps
CPU time 39.65 seconds
Started Jul 03 04:52:31 PM PDT 24
Finished Jul 03 04:53:11 PM PDT 24
Peak memory 206480 kb
Host smart-4cb77f41-a00e-4631-b334-452d1452a29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23090
75715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2309075715
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.680638225
Short name T1287
Test name
Test status
Simulation time 229432300 ps
CPU time 0.86 seconds
Started Jul 03 04:52:31 PM PDT 24
Finished Jul 03 04:52:32 PM PDT 24
Peak memory 206092 kb
Host smart-950420b1-8495-428b-b075-0a171973979f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68063
8225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.680638225
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.628141676
Short name T1416
Test name
Test status
Simulation time 209046206 ps
CPU time 0.86 seconds
Started Jul 03 04:52:29 PM PDT 24
Finished Jul 03 04:52:30 PM PDT 24
Peak memory 206112 kb
Host smart-276d8572-c2e7-4090-8b9f-ca0e6669d8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62814
1676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.628141676
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.2309479478
Short name T825
Test name
Test status
Simulation time 7793429328 ps
CPU time 129.11 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:54:36 PM PDT 24
Peak memory 206444 kb
Host smart-9b04791b-994f-458b-8a71-c6f095b70e5b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2309479478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.2309479478
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2571249820
Short name T1304
Test name
Test status
Simulation time 10610397943 ps
CPU time 68.91 seconds
Started Jul 03 04:52:37 PM PDT 24
Finished Jul 03 04:53:46 PM PDT 24
Peak memory 206424 kb
Host smart-dec4a109-00d7-42c6-ad50-9a1e756a6eaf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2571249820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2571249820
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.3284068799
Short name T2563
Test name
Test status
Simulation time 7870417356 ps
CPU time 30.92 seconds
Started Jul 03 04:52:36 PM PDT 24
Finished Jul 03 04:53:07 PM PDT 24
Peak memory 206420 kb
Host smart-2dd97dbd-041d-4707-bdf8-df5250ca8314
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3284068799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.3284068799
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.578227200
Short name T741
Test name
Test status
Simulation time 230317951 ps
CPU time 0.9 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:27 PM PDT 24
Peak memory 206128 kb
Host smart-dfaa406d-7064-477f-93b9-0a5fb6f5149c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57822
7200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.578227200
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1230612676
Short name T1706
Test name
Test status
Simulation time 191713063 ps
CPU time 0.86 seconds
Started Jul 03 04:52:26 PM PDT 24
Finished Jul 03 04:52:28 PM PDT 24
Peak memory 206092 kb
Host smart-b1330d5c-4b98-4f9b-bf46-b4ebb444df22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12306
12676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1230612676
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2171172583
Short name T672
Test name
Test status
Simulation time 189606734 ps
CPU time 0.8 seconds
Started Jul 03 04:52:39 PM PDT 24
Finished Jul 03 04:52:41 PM PDT 24
Peak memory 206056 kb
Host smart-9198f1c3-ba06-4cf4-b8e2-6b9484fd268a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21711
72583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2171172583
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.701616789
Short name T2597
Test name
Test status
Simulation time 173118129 ps
CPU time 0.78 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 206124 kb
Host smart-ca92481a-d406-4fef-a39e-49c17fc3db6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70161
6789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.701616789
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.236430325
Short name T2086
Test name
Test status
Simulation time 170116270 ps
CPU time 0.81 seconds
Started Jul 03 04:52:46 PM PDT 24
Finished Jul 03 04:52:47 PM PDT 24
Peak memory 206096 kb
Host smart-aeb32c94-6ba5-42b1-b32f-185ce112fba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23643
0325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.236430325
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2253393001
Short name T2221
Test name
Test status
Simulation time 206300449 ps
CPU time 0.89 seconds
Started Jul 03 04:52:36 PM PDT 24
Finished Jul 03 04:52:37 PM PDT 24
Peak memory 206128 kb
Host smart-bdae8a16-a930-4fef-b439-bf911a7ea23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22533
93001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2253393001
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.1130583954
Short name T673
Test name
Test status
Simulation time 6351814640 ps
CPU time 173.25 seconds
Started Jul 03 04:52:48 PM PDT 24
Finished Jul 03 04:55:42 PM PDT 24
Peak memory 206412 kb
Host smart-36c43f00-c647-462d-b0ad-9d3ca20f48b2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1130583954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.1130583954
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3531995247
Short name T1041
Test name
Test status
Simulation time 172937691 ps
CPU time 0.8 seconds
Started Jul 03 04:52:34 PM PDT 24
Finished Jul 03 04:52:35 PM PDT 24
Peak memory 206040 kb
Host smart-db6e3ebd-285f-4cb9-83a0-3d663f60bc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35319
95247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3531995247
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1299845596
Short name T600
Test name
Test status
Simulation time 160592350 ps
CPU time 0.82 seconds
Started Jul 03 04:52:45 PM PDT 24
Finished Jul 03 04:52:47 PM PDT 24
Peak memory 206084 kb
Host smart-018f76cd-78d9-44f9-bc7f-57e450070feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12998
45596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1299845596
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.1060150102
Short name T2499
Test name
Test status
Simulation time 645081893 ps
CPU time 1.59 seconds
Started Jul 03 04:52:45 PM PDT 24
Finished Jul 03 04:52:47 PM PDT 24
Peak memory 206128 kb
Host smart-b8881361-5a31-4342-b6e7-c07bff276cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10601
50102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.1060150102
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1640156817
Short name T367
Test name
Test status
Simulation time 5128447991 ps
CPU time 34.14 seconds
Started Jul 03 04:52:49 PM PDT 24
Finished Jul 03 04:53:24 PM PDT 24
Peak memory 206400 kb
Host smart-975ba535-f725-4c7e-9b90-08c03d1f4d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16401
56817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1640156817
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.756782826
Short name T1632
Test name
Test status
Simulation time 45778843 ps
CPU time 0.65 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:53:00 PM PDT 24
Peak memory 206176 kb
Host smart-59a4916a-b115-4323-bc0c-bc586740fc90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=756782826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.756782826
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.759949467
Short name T2121
Test name
Test status
Simulation time 3624346352 ps
CPU time 4.25 seconds
Started Jul 03 04:52:48 PM PDT 24
Finished Jul 03 04:52:52 PM PDT 24
Peak memory 206212 kb
Host smart-fd24736d-ffd8-45f3-8670-e0f5c50e83f4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=759949467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.759949467
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.546009904
Short name T1459
Test name
Test status
Simulation time 13326191208 ps
CPU time 12.11 seconds
Started Jul 03 04:52:34 PM PDT 24
Finished Jul 03 04:52:47 PM PDT 24
Peak memory 206196 kb
Host smart-f3f0ab2c-efb0-401b-86ce-de674bb422f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=546009904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.546009904
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.1223747888
Short name T1579
Test name
Test status
Simulation time 23404300308 ps
CPU time 23.13 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:53:15 PM PDT 24
Peak memory 206308 kb
Host smart-c778a0c4-0109-4a9c-a25e-e85936853772
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1223747888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.1223747888
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3135246638
Short name T1377
Test name
Test status
Simulation time 202967015 ps
CPU time 0.86 seconds
Started Jul 03 04:52:33 PM PDT 24
Finished Jul 03 04:52:34 PM PDT 24
Peak memory 206068 kb
Host smart-b1652678-3190-4ced-9d02-5ecdba2124b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31352
46638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3135246638
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2592943755
Short name T2664
Test name
Test status
Simulation time 153316628 ps
CPU time 0.76 seconds
Started Jul 03 04:52:39 PM PDT 24
Finished Jul 03 04:52:40 PM PDT 24
Peak memory 206128 kb
Host smart-77f03f3b-f137-442a-a7e1-eb4725c2bab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25929
43755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2592943755
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2283682872
Short name T2292
Test name
Test status
Simulation time 311700533 ps
CPU time 1.14 seconds
Started Jul 03 04:52:49 PM PDT 24
Finished Jul 03 04:52:51 PM PDT 24
Peak memory 206108 kb
Host smart-cbc2ebf2-b3a7-4210-bfba-dd5805ac58f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22836
82872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2283682872
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.734861693
Short name T178
Test name
Test status
Simulation time 1013549194 ps
CPU time 2.42 seconds
Started Jul 03 04:52:46 PM PDT 24
Finished Jul 03 04:52:49 PM PDT 24
Peak memory 206328 kb
Host smart-f8c972e1-ed2f-4fa6-9fe9-1449d2facd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73486
1693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.734861693
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2576557699
Short name T2419
Test name
Test status
Simulation time 18845966532 ps
CPU time 33.51 seconds
Started Jul 03 04:52:46 PM PDT 24
Finished Jul 03 04:53:20 PM PDT 24
Peak memory 206372 kb
Host smart-2a7ba03b-fde7-4d53-82d8-cec5c02fc2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25765
57699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2576557699
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.3293622971
Short name T989
Test name
Test status
Simulation time 431309976 ps
CPU time 1.26 seconds
Started Jul 03 04:52:35 PM PDT 24
Finished Jul 03 04:52:37 PM PDT 24
Peak memory 206112 kb
Host smart-ca1a0347-1d7a-447c-a15a-d4f46469850d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32936
22971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.3293622971
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2886730748
Short name T1308
Test name
Test status
Simulation time 142145053 ps
CPU time 0.84 seconds
Started Jul 03 04:52:39 PM PDT 24
Finished Jul 03 04:52:40 PM PDT 24
Peak memory 206120 kb
Host smart-7dc1e124-4bea-4b6e-a521-23c98a36313c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28867
30748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2886730748
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2066704834
Short name T2202
Test name
Test status
Simulation time 74493989 ps
CPU time 0.72 seconds
Started Jul 03 04:52:47 PM PDT 24
Finished Jul 03 04:52:48 PM PDT 24
Peak memory 206104 kb
Host smart-32c5430e-ac50-4e1f-9c89-9e482f7f831f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20667
04834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2066704834
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.4086917749
Short name T695
Test name
Test status
Simulation time 911700212 ps
CPU time 2.02 seconds
Started Jul 03 04:52:49 PM PDT 24
Finished Jul 03 04:52:52 PM PDT 24
Peak memory 206360 kb
Host smart-8317b428-36e0-4ee3-80d3-196185744e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40869
17749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.4086917749
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1552450017
Short name T2656
Test name
Test status
Simulation time 379046024 ps
CPU time 2.35 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:57 PM PDT 24
Peak memory 206320 kb
Host smart-634824ce-feec-49e4-8fde-4f1e14b5b40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15524
50017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1552450017
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2815965346
Short name T979
Test name
Test status
Simulation time 197694778 ps
CPU time 0.82 seconds
Started Jul 03 04:52:43 PM PDT 24
Finished Jul 03 04:52:44 PM PDT 24
Peak memory 206128 kb
Host smart-56a3ac15-da1a-4f64-a83a-bca0489b537a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28159
65346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2815965346
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1011848399
Short name T1773
Test name
Test status
Simulation time 175108244 ps
CPU time 0.76 seconds
Started Jul 03 04:52:35 PM PDT 24
Finished Jul 03 04:52:36 PM PDT 24
Peak memory 206084 kb
Host smart-500376a6-3faf-4be7-a902-888615211d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10118
48399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1011848399
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3586578833
Short name T941
Test name
Test status
Simulation time 209840170 ps
CPU time 0.9 seconds
Started Jul 03 04:52:38 PM PDT 24
Finished Jul 03 04:52:39 PM PDT 24
Peak memory 206140 kb
Host smart-3a8cb0e9-95f3-4007-9c97-a896012e96e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35865
78833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3586578833
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.858291647
Short name T639
Test name
Test status
Simulation time 5967452035 ps
CPU time 56.8 seconds
Started Jul 03 04:52:35 PM PDT 24
Finished Jul 03 04:53:32 PM PDT 24
Peak memory 206444 kb
Host smart-7ff3eb25-a98a-438a-8306-4417183bf323
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=858291647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.858291647
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1478470666
Short name T2318
Test name
Test status
Simulation time 210729869 ps
CPU time 0.86 seconds
Started Jul 03 04:52:42 PM PDT 24
Finished Jul 03 04:52:44 PM PDT 24
Peak memory 206056 kb
Host smart-5d8c3f41-e0a6-469b-8f6b-9707404c7114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14784
70666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1478470666
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3388383012
Short name T780
Test name
Test status
Simulation time 23331515429 ps
CPU time 23.69 seconds
Started Jul 03 04:52:35 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206196 kb
Host smart-4c7ced79-6621-4187-8d54-8692ca991da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33883
83012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3388383012
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.882970535
Short name T355
Test name
Test status
Simulation time 3332846879 ps
CPU time 4.65 seconds
Started Jul 03 04:52:34 PM PDT 24
Finished Jul 03 04:52:39 PM PDT 24
Peak memory 206192 kb
Host smart-e5834550-a2fe-49e2-88b8-b5fdfc3c6ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88297
0535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.882970535
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.288699205
Short name T795
Test name
Test status
Simulation time 12761101966 ps
CPU time 346.43 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:58:40 PM PDT 24
Peak memory 206380 kb
Host smart-cd820c5a-2115-4e4d-b20e-49e27a787336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28869
9205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.288699205
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.1784070515
Short name T1877
Test name
Test status
Simulation time 5118058536 ps
CPU time 137.06 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:55:09 PM PDT 24
Peak memory 206300 kb
Host smart-cdcff4b9-caea-4197-a8e5-0f88625e06d6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1784070515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.1784070515
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.108387189
Short name T1121
Test name
Test status
Simulation time 235122413 ps
CPU time 0.9 seconds
Started Jul 03 04:52:49 PM PDT 24
Finished Jul 03 04:52:50 PM PDT 24
Peak memory 206000 kb
Host smart-600ff697-37b4-444a-bc5a-0e07e497b665
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=108387189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.108387189
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2491891482
Short name T1032
Test name
Test status
Simulation time 188381232 ps
CPU time 0.87 seconds
Started Jul 03 04:52:36 PM PDT 24
Finished Jul 03 04:52:37 PM PDT 24
Peak memory 206136 kb
Host smart-21519c2a-9845-4ab4-97ff-17d3cb15a043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24918
91482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2491891482
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.4237463873
Short name T1977
Test name
Test status
Simulation time 4785972933 ps
CPU time 34.31 seconds
Started Jul 03 04:52:41 PM PDT 24
Finished Jul 03 04:53:15 PM PDT 24
Peak memory 206388 kb
Host smart-4bce0840-f29f-4d60-b9a7-2dd5ca2865a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42374
63873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.4237463873
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1721441503
Short name T160
Test name
Test status
Simulation time 4746194064 ps
CPU time 46.64 seconds
Started Jul 03 04:52:38 PM PDT 24
Finished Jul 03 04:53:25 PM PDT 24
Peak memory 206436 kb
Host smart-0f0d5a84-873d-4559-abfc-5d63ca252b4d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1721441503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1721441503
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.965759662
Short name T2282
Test name
Test status
Simulation time 152640089 ps
CPU time 0.79 seconds
Started Jul 03 04:52:54 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206124 kb
Host smart-cf6781bd-c131-4113-a7a1-efd64da3330d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=965759662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.965759662
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3360084302
Short name T1495
Test name
Test status
Simulation time 167553436 ps
CPU time 0.77 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206084 kb
Host smart-956cb944-b8b7-45a3-b59d-8737f36715c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33600
84302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3360084302
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3719049585
Short name T138
Test name
Test status
Simulation time 263541160 ps
CPU time 1 seconds
Started Jul 03 04:52:38 PM PDT 24
Finished Jul 03 04:52:39 PM PDT 24
Peak memory 206112 kb
Host smart-a4682663-968f-420f-9b0d-2d2b6f6ecb9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37190
49585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3719049585
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.4282573937
Short name T110
Test name
Test status
Simulation time 208793769 ps
CPU time 0.86 seconds
Started Jul 03 04:52:39 PM PDT 24
Finished Jul 03 04:52:40 PM PDT 24
Peak memory 206044 kb
Host smart-cdfad279-0022-4898-b727-977d32ab4105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42825
73937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.4282573937
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3152337614
Short name T1999
Test name
Test status
Simulation time 169706080 ps
CPU time 0.78 seconds
Started Jul 03 04:52:48 PM PDT 24
Finished Jul 03 04:52:50 PM PDT 24
Peak memory 206096 kb
Host smart-51a5bcbe-b2ae-4884-973b-07011451991d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31523
37614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3152337614
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2322216301
Short name T872
Test name
Test status
Simulation time 206574957 ps
CPU time 0.82 seconds
Started Jul 03 04:52:36 PM PDT 24
Finished Jul 03 04:52:37 PM PDT 24
Peak memory 205976 kb
Host smart-168c7ac8-7782-463e-8422-0fe914f5beb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23222
16301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2322216301
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1755082832
Short name T1305
Test name
Test status
Simulation time 147042736 ps
CPU time 0.85 seconds
Started Jul 03 04:52:39 PM PDT 24
Finished Jul 03 04:52:40 PM PDT 24
Peak memory 206088 kb
Host smart-77b36a54-407a-4977-8962-7452fc3cbe4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17550
82832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1755082832
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.1058221979
Short name T887
Test name
Test status
Simulation time 238522242 ps
CPU time 0.97 seconds
Started Jul 03 04:52:36 PM PDT 24
Finished Jul 03 04:52:37 PM PDT 24
Peak memory 206040 kb
Host smart-454d68a7-d9a8-4fcd-949c-ad93ae0dbe53
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1058221979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.1058221979
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3101276807
Short name T2520
Test name
Test status
Simulation time 152955444 ps
CPU time 0.81 seconds
Started Jul 03 04:52:42 PM PDT 24
Finished Jul 03 04:52:43 PM PDT 24
Peak memory 206128 kb
Host smart-8bf812e3-25c0-40f8-a63c-b6473c72b931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31012
76807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3101276807
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.589629866
Short name T2118
Test name
Test status
Simulation time 46214112 ps
CPU time 0.68 seconds
Started Jul 03 04:52:38 PM PDT 24
Finished Jul 03 04:52:39 PM PDT 24
Peak memory 206108 kb
Host smart-d6220118-dec7-46ad-9ada-210995e03b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58962
9866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.589629866
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2413677697
Short name T2564
Test name
Test status
Simulation time 15408205018 ps
CPU time 36.52 seconds
Started Jul 03 04:52:54 PM PDT 24
Finished Jul 03 04:53:32 PM PDT 24
Peak memory 206460 kb
Host smart-76521a82-1edb-49ac-b593-bc772c8630cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24136
77697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2413677697
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3483985468
Short name T1274
Test name
Test status
Simulation time 195860845 ps
CPU time 0.87 seconds
Started Jul 03 04:52:41 PM PDT 24
Finished Jul 03 04:52:42 PM PDT 24
Peak memory 206128 kb
Host smart-747955c2-616f-4b4c-a954-c41111d1dfaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34839
85468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3483985468
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1911052564
Short name T1161
Test name
Test status
Simulation time 241452438 ps
CPU time 0.93 seconds
Started Jul 03 04:52:39 PM PDT 24
Finished Jul 03 04:52:40 PM PDT 24
Peak memory 206060 kb
Host smart-6eedcc5d-2051-4d09-9b85-cb037c746fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19110
52564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1911052564
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.2759714359
Short name T564
Test name
Test status
Simulation time 8341201865 ps
CPU time 52.63 seconds
Started Jul 03 04:52:36 PM PDT 24
Finished Jul 03 04:53:29 PM PDT 24
Peak memory 206412 kb
Host smart-3650d41d-14d2-47e7-8648-d44e6e4b230e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2759714359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.2759714359
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1558893157
Short name T2514
Test name
Test status
Simulation time 4535969678 ps
CPU time 32.87 seconds
Started Jul 03 04:52:47 PM PDT 24
Finished Jul 03 04:53:21 PM PDT 24
Peak memory 206388 kb
Host smart-92af7379-9181-4b3d-b4e4-73dffa6cefd2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1558893157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1558893157
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1638969989
Short name T1014
Test name
Test status
Simulation time 12556922153 ps
CPU time 240.45 seconds
Started Jul 03 04:52:44 PM PDT 24
Finished Jul 03 04:56:45 PM PDT 24
Peak memory 206444 kb
Host smart-4c2943ba-bdc1-495c-8b93-86a96da76c72
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1638969989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1638969989
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1218230818
Short name T371
Test name
Test status
Simulation time 202558734 ps
CPU time 0.83 seconds
Started Jul 03 04:52:43 PM PDT 24
Finished Jul 03 04:52:44 PM PDT 24
Peak memory 206124 kb
Host smart-6e75fe95-4829-4d8e-926d-579e8cf638a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12182
30818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1218230818
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.2376885378
Short name T574
Test name
Test status
Simulation time 191646462 ps
CPU time 0.82 seconds
Started Jul 03 04:52:44 PM PDT 24
Finished Jul 03 04:52:45 PM PDT 24
Peak memory 206116 kb
Host smart-814d51a5-3b39-46d2-a62e-cc1a1709de67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23768
85378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2376885378
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3556583581
Short name T2243
Test name
Test status
Simulation time 145697256 ps
CPU time 0.75 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 206112 kb
Host smart-232d2936-1dd1-40de-b58e-b03d82e8390e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35565
83581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3556583581
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1820899691
Short name T2579
Test name
Test status
Simulation time 151259388 ps
CPU time 0.8 seconds
Started Jul 03 04:52:49 PM PDT 24
Finished Jul 03 04:52:51 PM PDT 24
Peak memory 206124 kb
Host smart-b1d4c1f9-ff18-48d5-b00c-05c2b3946a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18208
99691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1820899691
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1515991809
Short name T626
Test name
Test status
Simulation time 155369953 ps
CPU time 0.8 seconds
Started Jul 03 04:52:42 PM PDT 24
Finished Jul 03 04:52:44 PM PDT 24
Peak memory 206088 kb
Host smart-18a7a870-901b-4f2e-a3ed-8934a7363021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15159
91809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1515991809
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1487875563
Short name T1730
Test name
Test status
Simulation time 195017568 ps
CPU time 0.84 seconds
Started Jul 03 04:52:49 PM PDT 24
Finished Jul 03 04:52:50 PM PDT 24
Peak memory 205944 kb
Host smart-28541455-d06d-4dfa-b8c3-ffc8e842acc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14878
75563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1487875563
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.181878355
Short name T1538
Test name
Test status
Simulation time 4631673234 ps
CPU time 123 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:55:03 PM PDT 24
Peak memory 206380 kb
Host smart-9619f242-64ed-41f1-836e-0d5c8c0327d9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=181878355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.181878355
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2560597496
Short name T2650
Test name
Test status
Simulation time 205696569 ps
CPU time 0.99 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:53:00 PM PDT 24
Peak memory 206004 kb
Host smart-4fbe75fd-316a-4c93-9833-39969606616e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25605
97496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2560597496
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1515869084
Short name T1230
Test name
Test status
Simulation time 194410502 ps
CPU time 0.81 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:53:00 PM PDT 24
Peak memory 206004 kb
Host smart-2c98d2ba-5b53-41cf-a7a6-c57467049449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15158
69084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1515869084
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2504648200
Short name T2266
Test name
Test status
Simulation time 847439005 ps
CPU time 1.8 seconds
Started Jul 03 04:52:41 PM PDT 24
Finished Jul 03 04:52:43 PM PDT 24
Peak memory 206308 kb
Host smart-f0bfc52b-3c7a-4118-8302-4223593c7860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25046
48200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2504648200
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3488458900
Short name T1679
Test name
Test status
Simulation time 3091075107 ps
CPU time 83.69 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:54:18 PM PDT 24
Peak memory 206440 kb
Host smart-aa82a473-0ae1-4aef-a0d5-5f5750ffa38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34884
58900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3488458900
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.3039421592
Short name T1576
Test name
Test status
Simulation time 49415783 ps
CPU time 0.67 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:52:57 PM PDT 24
Peak memory 206024 kb
Host smart-6a9e7307-8c98-4d77-9419-865475bbead5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3039421592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.3039421592
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3221555045
Short name T1874
Test name
Test status
Simulation time 4213042788 ps
CPU time 5.21 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:53:05 PM PDT 24
Peak memory 206372 kb
Host smart-6bd1cfb2-5501-4ccc-9412-bdcd0c9f0d96
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3221555045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.3221555045
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3806881874
Short name T1472
Test name
Test status
Simulation time 13339799510 ps
CPU time 12.69 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:53:05 PM PDT 24
Peak memory 206156 kb
Host smart-7d84d413-6da8-45ad-94ac-6e8da6f4119a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3806881874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3806881874
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.657210527
Short name T811
Test name
Test status
Simulation time 23378476251 ps
CPU time 23.71 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:53:15 PM PDT 24
Peak memory 206396 kb
Host smart-644f3384-5ee3-4614-823b-570d7a5c0a50
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=657210527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.657210527
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.486377913
Short name T1037
Test name
Test status
Simulation time 225302471 ps
CPU time 0.9 seconds
Started Jul 03 04:52:48 PM PDT 24
Finished Jul 03 04:52:50 PM PDT 24
Peak memory 206128 kb
Host smart-afc32c5e-65d9-4b2b-9edf-bcf4a1612c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48637
7913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.486377913
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1070203528
Short name T855
Test name
Test status
Simulation time 150170029 ps
CPU time 0.76 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 205960 kb
Host smart-17166fac-138d-43db-8264-ea8937d6ae34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702
03528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1070203528
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2667966334
Short name T874
Test name
Test status
Simulation time 226887882 ps
CPU time 0.94 seconds
Started Jul 03 04:52:43 PM PDT 24
Finished Jul 03 04:52:44 PM PDT 24
Peak memory 206108 kb
Host smart-736d6314-fe0f-4512-98f9-eaadfa3ad6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26679
66334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2667966334
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1683256161
Short name T2525
Test name
Test status
Simulation time 606011627 ps
CPU time 1.52 seconds
Started Jul 03 04:52:45 PM PDT 24
Finished Jul 03 04:52:47 PM PDT 24
Peak memory 206088 kb
Host smart-36836d7d-0cc1-41e0-9df1-56d424984413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16832
56161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1683256161
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1947229088
Short name T1425
Test name
Test status
Simulation time 21562767816 ps
CPU time 38.68 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:53:34 PM PDT 24
Peak memory 206420 kb
Host smart-f24a8a86-f1b5-407b-a8d5-2a2aad21dd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19472
29088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1947229088
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3019373218
Short name T2177
Test name
Test status
Simulation time 546616245 ps
CPU time 1.84 seconds
Started Jul 03 04:52:59 PM PDT 24
Finished Jul 03 04:53:02 PM PDT 24
Peak memory 206088 kb
Host smart-a7a3e9da-dfc8-4af6-be78-96cbd849621a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30193
73218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3019373218
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.872623155
Short name T1967
Test name
Test status
Simulation time 137957485 ps
CPU time 0.79 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 206140 kb
Host smart-bc8459dd-e088-41ef-b4ce-9052f0e9849d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87262
3155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.872623155
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.429416818
Short name T2710
Test name
Test status
Simulation time 30280671 ps
CPU time 0.67 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206108 kb
Host smart-7bf38bb7-5feb-44da-b1fb-c398281d3a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42941
6818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.429416818
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.1135840195
Short name T2303
Test name
Test status
Simulation time 909999314 ps
CPU time 1.95 seconds
Started Jul 03 04:52:48 PM PDT 24
Finished Jul 03 04:52:50 PM PDT 24
Peak memory 206352 kb
Host smart-e89bd479-3799-41ed-b9bb-e55c5893c336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11358
40195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1135840195
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1388022487
Short name T1552
Test name
Test status
Simulation time 216916078 ps
CPU time 2.11 seconds
Started Jul 03 04:52:56 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206292 kb
Host smart-e6a05ee9-9863-49d4-98d4-9b5dc52a31ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13880
22487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1388022487
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1331135096
Short name T943
Test name
Test status
Simulation time 160481230 ps
CPU time 0.81 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 205980 kb
Host smart-aa1b9c40-c7f5-4dd8-bf53-cfe0a2a82850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13311
35096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1331135096
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2865179475
Short name T1116
Test name
Test status
Simulation time 159505602 ps
CPU time 0.78 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:52:52 PM PDT 24
Peak memory 206084 kb
Host smart-27811331-ba52-40fc-8801-682f749e7e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28651
79475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2865179475
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.947941311
Short name T2464
Test name
Test status
Simulation time 167872151 ps
CPU time 0.85 seconds
Started Jul 03 04:52:47 PM PDT 24
Finished Jul 03 04:52:49 PM PDT 24
Peak memory 206104 kb
Host smart-a0ac5fd0-d18b-4800-906e-868ee093ef76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94794
1311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.947941311
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.1719778058
Short name T756
Test name
Test status
Simulation time 4974922254 ps
CPU time 36.79 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:53:28 PM PDT 24
Peak memory 206348 kb
Host smart-07c3a5c3-336d-4d03-b169-5073a4a7f445
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1719778058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.1719778058
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.314401627
Short name T2674
Test name
Test status
Simulation time 229448243 ps
CPU time 0.9 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:52:53 PM PDT 24
Peak memory 206092 kb
Host smart-c395216d-08bd-428f-ba58-df6b8de05060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440
1627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.314401627
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3163413743
Short name T1144
Test name
Test status
Simulation time 23341935339 ps
CPU time 22.88 seconds
Started Jul 03 04:52:59 PM PDT 24
Finished Jul 03 04:53:23 PM PDT 24
Peak memory 206196 kb
Host smart-38312ae3-6017-42c2-8b4d-cf1040d22f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31634
13743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3163413743
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3559010559
Short name T816
Test name
Test status
Simulation time 3328626957 ps
CPU time 4.07 seconds
Started Jul 03 04:52:41 PM PDT 24
Finished Jul 03 04:52:45 PM PDT 24
Peak memory 206192 kb
Host smart-fe55d4a7-2635-478c-8d04-6c9dfa0a1e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35590
10559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3559010559
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1919836921
Short name T2692
Test name
Test status
Simulation time 8282516066 ps
CPU time 81.68 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:54:19 PM PDT 24
Peak memory 206408 kb
Host smart-8df216a9-5820-4947-8eda-f4652a59e5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19198
36921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1919836921
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.4082019728
Short name T401
Test name
Test status
Simulation time 4133306110 ps
CPU time 107.01 seconds
Started Jul 03 04:52:50 PM PDT 24
Finished Jul 03 04:54:38 PM PDT 24
Peak memory 206368 kb
Host smart-16c8b547-96a7-4b61-9a20-d948ab2e7a13
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4082019728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.4082019728
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.1513359249
Short name T867
Test name
Test status
Simulation time 234684294 ps
CPU time 0.92 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:53:00 PM PDT 24
Peak memory 206004 kb
Host smart-25f545bb-7698-4383-a491-0a968119de8a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1513359249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.1513359249
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1531417519
Short name T2196
Test name
Test status
Simulation time 191960693 ps
CPU time 0.91 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:53:00 PM PDT 24
Peak memory 206112 kb
Host smart-b03938e5-60f5-4240-82f6-a04294da8399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15314
17519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1531417519
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2708792806
Short name T1719
Test name
Test status
Simulation time 4835141843 ps
CPU time 42.07 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:53:35 PM PDT 24
Peak memory 206368 kb
Host smart-af0777fa-7485-4883-abcb-4ce3d583542c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27087
92806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2708792806
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.2284712146
Short name T157
Test name
Test status
Simulation time 4435541569 ps
CPU time 123.36 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:54:55 PM PDT 24
Peak memory 206336 kb
Host smart-95ef22fe-724f-467e-9998-b1613ed6a09a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2284712146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.2284712146
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.922401803
Short name T922
Test name
Test status
Simulation time 157827437 ps
CPU time 0.76 seconds
Started Jul 03 04:52:54 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 205968 kb
Host smart-41e2297d-b144-4adb-b54c-5fdd9043cfa5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=922401803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.922401803
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2584296415
Short name T449
Test name
Test status
Simulation time 151295646 ps
CPU time 0.85 seconds
Started Jul 03 04:52:56 PM PDT 24
Finished Jul 03 04:52:58 PM PDT 24
Peak memory 206092 kb
Host smart-51be0c9b-5fa0-4297-b96a-8e52797bee85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25842
96415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2584296415
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1871335155
Short name T2224
Test name
Test status
Simulation time 209261867 ps
CPU time 0.86 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 206128 kb
Host smart-ef9303d7-8d89-40fb-bd19-cde8438da0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18713
35155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1871335155
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2920674152
Short name T1369
Test name
Test status
Simulation time 194458731 ps
CPU time 0.87 seconds
Started Jul 03 04:52:44 PM PDT 24
Finished Jul 03 04:52:45 PM PDT 24
Peak memory 206112 kb
Host smart-4de623fd-0fc7-4341-97a0-64bb0765aba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29206
74152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2920674152
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2245527148
Short name T999
Test name
Test status
Simulation time 215228925 ps
CPU time 0.81 seconds
Started Jul 03 04:52:58 PM PDT 24
Finished Jul 03 04:53:00 PM PDT 24
Peak memory 206128 kb
Host smart-5fb3285b-77cb-4bec-9b2a-0a9878be8183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22455
27148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2245527148
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1814347408
Short name T26
Test name
Test status
Simulation time 176632559 ps
CPU time 0.81 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 206076 kb
Host smart-9ba629b5-df04-4588-bd7f-48b6318e2c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18143
47408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1814347408
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2866348084
Short name T1320
Test name
Test status
Simulation time 146918610 ps
CPU time 0.76 seconds
Started Jul 03 04:52:49 PM PDT 24
Finished Jul 03 04:52:50 PM PDT 24
Peak memory 206096 kb
Host smart-684947a4-7be9-4017-bb7c-2502834570cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28663
48084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2866348084
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3652172095
Short name T1793
Test name
Test status
Simulation time 220715250 ps
CPU time 0.93 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:52:58 PM PDT 24
Peak memory 205968 kb
Host smart-40f97e80-a9e3-44e6-bfb7-d75d83eefd75
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3652172095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3652172095
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1728452148
Short name T1160
Test name
Test status
Simulation time 160110096 ps
CPU time 0.8 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:52:59 PM PDT 24
Peak memory 206084 kb
Host smart-56151043-eb95-4ef8-9439-4f56024bc125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17284
52148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1728452148
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3876468645
Short name T1555
Test name
Test status
Simulation time 42735799 ps
CPU time 0.66 seconds
Started Jul 03 04:52:56 PM PDT 24
Finished Jul 03 04:52:58 PM PDT 24
Peak memory 206104 kb
Host smart-39424d34-5eee-4f39-ab9e-1e402807c02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38764
68645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3876468645
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2141589479
Short name T243
Test name
Test status
Simulation time 13512051836 ps
CPU time 28.9 seconds
Started Jul 03 04:52:56 PM PDT 24
Finished Jul 03 04:53:26 PM PDT 24
Peak memory 206360 kb
Host smart-c3425d3d-4332-4aaf-846b-36107295b672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21415
89479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2141589479
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.273111636
Short name T1104
Test name
Test status
Simulation time 158467825 ps
CPU time 0.8 seconds
Started Jul 03 04:52:46 PM PDT 24
Finished Jul 03 04:52:47 PM PDT 24
Peak memory 206128 kb
Host smart-45d0c39f-dc8a-4ef2-83a3-f960154ddd77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27311
1636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.273111636
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2605612562
Short name T1468
Test name
Test status
Simulation time 243480660 ps
CPU time 0.88 seconds
Started Jul 03 04:52:50 PM PDT 24
Finished Jul 03 04:52:52 PM PDT 24
Peak memory 206128 kb
Host smart-ae903c6a-6f92-49e9-9323-e8e4bcbf94a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26056
12562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2605612562
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2196913511
Short name T1850
Test name
Test status
Simulation time 11203614837 ps
CPU time 101.69 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:54:40 PM PDT 24
Peak memory 206308 kb
Host smart-40c0c7bc-9de3-4764-90d0-8b7f90577cf0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2196913511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2196913511
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.288486432
Short name T441
Test name
Test status
Simulation time 8673732613 ps
CPU time 76 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:54:09 PM PDT 24
Peak memory 206352 kb
Host smart-69ee9f64-f658-4e76-b8b6-5a6a4c1ae758
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=288486432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.288486432
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.3233250335
Short name T2701
Test name
Test status
Simulation time 16599371644 ps
CPU time 115.63 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:54:48 PM PDT 24
Peak memory 206352 kb
Host smart-0c562eb8-ed37-431f-92a8-8756aa22375a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3233250335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.3233250335
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3030166958
Short name T2037
Test name
Test status
Simulation time 243241389 ps
CPU time 0.87 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206108 kb
Host smart-13f1418a-d942-41ee-8f89-ff8dd5d2fbb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30301
66958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3030166958
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.4080987078
Short name T2268
Test name
Test status
Simulation time 195417132 ps
CPU time 0.84 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:52:53 PM PDT 24
Peak memory 206128 kb
Host smart-6e54329f-661b-42ce-ab9c-8520f76e46f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40809
87078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.4080987078
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1395268444
Short name T2628
Test name
Test status
Simulation time 169352186 ps
CPU time 0.77 seconds
Started Jul 03 04:52:55 PM PDT 24
Finished Jul 03 04:52:58 PM PDT 24
Peak memory 206124 kb
Host smart-e83a6cd9-a4ec-4fdf-8e66-761fd0b824a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13952
68444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1395268444
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.997950920
Short name T2076
Test name
Test status
Simulation time 161766019 ps
CPU time 0.78 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:56 PM PDT 24
Peak memory 206092 kb
Host smart-bb0244ba-b6b6-4bfd-bb8d-7190bbde3ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99795
0920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.997950920
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.4066736158
Short name T1638
Test name
Test status
Simulation time 186903630 ps
CPU time 0.84 seconds
Started Jul 03 04:52:53 PM PDT 24
Finished Jul 03 04:52:55 PM PDT 24
Peak memory 206096 kb
Host smart-54e544df-a188-4f24-b5b4-a2054b901035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40667
36158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.4066736158
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2220109932
Short name T1557
Test name
Test status
Simulation time 251293700 ps
CPU time 0.95 seconds
Started Jul 03 04:52:49 PM PDT 24
Finished Jul 03 04:52:51 PM PDT 24
Peak memory 206092 kb
Host smart-10358407-21ef-44de-a9a9-4e0b4edb0819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22201
09932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2220109932
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.4233558928
Short name T551
Test name
Test status
Simulation time 6380099130 ps
CPU time 45.3 seconds
Started Jul 03 04:52:50 PM PDT 24
Finished Jul 03 04:53:36 PM PDT 24
Peak memory 206400 kb
Host smart-bb494cba-323a-422e-a308-4e51d9c132c1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4233558928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.4233558928
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.5919511
Short name T1720
Test name
Test status
Simulation time 196867991 ps
CPU time 0.82 seconds
Started Jul 03 04:52:52 PM PDT 24
Finished Jul 03 04:52:54 PM PDT 24
Peak memory 206132 kb
Host smart-2dc515ae-cabc-4cf1-b8bf-82486b855680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59195
11 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.5919511
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2210841089
Short name T1106
Test name
Test status
Simulation time 157764605 ps
CPU time 0.8 seconds
Started Jul 03 04:52:51 PM PDT 24
Finished Jul 03 04:52:53 PM PDT 24
Peak memory 206076 kb
Host smart-9983a6ef-25eb-447b-9e75-fed97c3f6ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22108
41089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2210841089
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3026733247
Short name T1065
Test name
Test status
Simulation time 193841315 ps
CPU time 0.82 seconds
Started Jul 03 04:53:01 PM PDT 24
Finished Jul 03 04:53:03 PM PDT 24
Peak memory 205944 kb
Host smart-15e77ad5-d00c-40b8-b6dd-292761a69f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30267
33247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3026733247
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1432223088
Short name T1489
Test name
Test status
Simulation time 7583938680 ps
CPU time 66.06 seconds
Started Jul 03 04:52:57 PM PDT 24
Finished Jul 03 04:54:04 PM PDT 24
Peak memory 206200 kb
Host smart-19c8b0d3-89c9-4329-838c-3e9eacabe878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14322
23088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1432223088
Directory /workspace/9.usbdev_streaming_out/latest
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