Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	168076	1		T1	34		T2	14		T3	3
all_values[1]	168076	1		T1	34		T2	14		T3	3
all_values[2]	168076	1		T1	34		T2	14		T3	3
all_values[3]	168076	1		T1	34		T2	14		T3	3
all_values[4]	168076	1		T1	34		T2	14		T3	3
all_values[5]	168076	1		T1	34		T2	14		T3	3
all_values[6]	168076	1		T1	34		T2	14		T3	3
all_values[7]	168076	1		T1	34		T2	14		T3	3
all_values[8]	168076	1		T1	34		T2	14		T3	3
all_values[9]	168076	1		T1	34		T2	14		T3	3
all_values[10]	168076	1		T1	34		T2	14		T3	3
all_values[11]	168076	1		T1	34		T2	14		T3	3
all_values[12]	168076	1		T1	34		T2	14		T3	3
all_values[13]	168076	1		T1	34		T2	14		T3	3
all_values[14]	168076	1		T1	34		T2	14		T3	3
all_values[15]	168076	1		T1	34		T2	14		T3	3
all_values[16]	168076	1		T1	34		T2	14		T3	3
all_values[17]	168076	1		T1	34		T2	14		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3018639	1		T1	612		T2	238		T3	54
auto[1]	6729	1		T2	14		T34	2		T47	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3020673	1		T1	612		T2	252		T3	54
auto[1]	4695	1		T225	61		T226	79		T227	116

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	167110	1		T1	34		T2	14		T3	3
all_values[0]	auto[0]	auto[1]	139	1		T225	1		T226	4		T227	3
all_values[0]	auto[1]	auto[0]	697	1		T49	3		T20	4		T50	3
all_values[0]	auto[1]	auto[1]	130	1		T225	4		T226	1		T227	5
all_values[1]	auto[0]	auto[0]	166287	1		T1	34		T3	3		T29	2
all_values[1]	auto[0]	auto[1]	127	1		T225	2		T227	1		T228	6
all_values[1]	auto[1]	auto[0]	1528	1		T2	14		T34	2		T47	3
all_values[1]	auto[1]	auto[1]	134	1		T225	3		T226	3		T227	5
all_values[2]	auto[0]	auto[0]	167699	1		T1	34		T2	14		T3	3
all_values[2]	auto[0]	auto[1]	133	1		T226	4		T227	1		T228	5
all_values[2]	auto[1]	auto[0]	128	1		T41	2		T44	2		T45	2
all_values[2]	auto[1]	auto[1]	116	1		T226	1		T227	7		T228	1
all_values[3]	auto[0]	auto[0]	166294	1		T1	34		T2	14		T3	3
all_values[3]	auto[0]	auto[1]	150	1		T225	4		T226	1		T228	3
all_values[3]	auto[1]	auto[0]	1504	1		T69	1485		T227	2		T298	1
all_values[3]	auto[1]	auto[1]	128	1		T226	4		T227	3		T228	5
all_values[4]	auto[0]	auto[0]	167781	1		T1	34		T2	14		T3	3
all_values[4]	auto[0]	auto[1]	144	1		T225	3		T226	3		T227	1
all_values[4]	auto[1]	auto[0]	19	1		T70	2		T299	2		T300	1
all_values[4]	auto[1]	auto[1]	132	1		T225	1		T226	1		T227	7
all_values[5]	auto[0]	auto[0]	167783	1		T1	34		T2	14		T3	3
all_values[5]	auto[0]	auto[1]	144	1		T225	3		T226	3		T227	5
all_values[5]	auto[1]	auto[0]	28	1		T225	1		T299	1		T301	4
all_values[5]	auto[1]	auto[1]	121	1		T227	3		T228	3		T229	5
all_values[6]	auto[0]	auto[0]	167792	1		T1	34		T2	14		T3	3
all_values[6]	auto[0]	auto[1]	117	1		T226	1		T227	5		T228	3
all_values[6]	auto[1]	auto[0]	33	1		T225	5		T227	1		T301	2
all_values[6]	auto[1]	auto[1]	134	1		T226	4		T227	2		T228	5
all_values[7]	auto[0]	auto[0]	167776	1		T1	34		T2	14		T3	3
all_values[7]	auto[0]	auto[1]	134	1		T226	4		T227	6		T228	2
all_values[7]	auto[1]	auto[0]	36	1		T51	2		T52	2		T227	1
all_values[7]	auto[1]	auto[1]	130	1		T225	5		T226	1		T227	1
all_values[8]	auto[0]	auto[0]	167785	1		T1	34		T2	14		T3	3
all_values[8]	auto[0]	auto[1]	130	1		T227	3		T228	3		T229	4
all_values[8]	auto[1]	auto[0]	38	1		T54	11		T225	1		T298	1
all_values[8]	auto[1]	auto[1]	123	1		T225	4		T226	5		T227	5
all_values[9]	auto[0]	auto[0]	167764	1		T1	34		T2	14		T3	3
all_values[9]	auto[0]	auto[1]	132	1		T225	3		T226	4		T227	5
all_values[9]	auto[1]	auto[0]	49	1		T66	5		T67	5		T68	5
all_values[9]	auto[1]	auto[1]	131	1		T225	1		T226	1		T227	2
all_values[10]	auto[0]	auto[0]	167786	1		T1	34		T2	14		T3	3
all_values[10]	auto[0]	auto[1]	108	1		T226	1		T227	1		T228	1
all_values[10]	auto[1]	auto[0]	28	1		T227	1		T302	1		T303	2
all_values[10]	auto[1]	auto[1]	154	1		T225	4		T226	4		T227	4
all_values[11]	auto[0]	auto[0]	167685	1		T1	34		T2	14		T3	3
all_values[11]	auto[0]	auto[1]	136	1		T226	4		T227	5		T229	2
all_values[11]	auto[1]	auto[0]	142	1		T48	2		T74	2		T75	2
all_values[11]	auto[1]	auto[1]	113	1		T225	3		T226	1		T227	2
all_values[12]	auto[0]	auto[0]	167769	1		T1	34		T2	14		T3	3
all_values[12]	auto[0]	auto[1]	123	1		T226	4		T227	3		T229	2
all_values[12]	auto[1]	auto[0]	49	1		T77	3		T78	3		T79	3
all_values[12]	auto[1]	auto[1]	135	1		T225	4		T227	4		T229	6
all_values[13]	auto[0]	auto[0]	167795	1		T1	34		T2	14		T3	3
all_values[13]	auto[0]	auto[1]	150	1		T226	4		T227	1		T228	5
all_values[13]	auto[1]	auto[0]	35	1		T229	1		T298	1		T304	6
all_values[13]	auto[1]	auto[1]	96	1		T225	4		T226	1		T227	5
all_values[14]	auto[0]	auto[0]	167801	1		T1	34		T2	14		T3	3
all_values[14]	auto[0]	auto[1]	141	1		T225	3		T226	4		T228	2
all_values[14]	auto[1]	auto[0]	29	1		T227	5		T228	1		T229	1
all_values[14]	auto[1]	auto[1]	105	1		T225	2		T226	1		T228	5
all_values[15]	auto[0]	auto[0]	167783	1		T1	34		T2	14		T3	3
all_values[15]	auto[0]	auto[1]	108	1		T225	3		T227	2		T228	2
all_values[15]	auto[1]	auto[0]	32	1		T225	1		T228	1		T299	3
all_values[15]	auto[1]	auto[1]	153	1		T226	4		T227	6		T228	5
all_values[16]	auto[0]	auto[0]	167752	1		T1	34		T2	14		T3	3
all_values[16]	auto[0]	auto[1]	160	1		T226	3		T227	3		T228	2
all_values[16]	auto[1]	auto[0]	48	1		T71	8		T72	8		T73	8
all_values[16]	auto[1]	auto[1]	116	1		T227	5		T228	5		T229	4
all_values[17]	auto[0]	auto[0]	167772	1		T1	34		T2	14		T3	3
all_values[17]	auto[0]	auto[1]	149	1		T225	1		T228	5		T229	1
all_values[17]	auto[1]	auto[0]	36	1		T57	2		T58	2		T59	2
all_values[17]	auto[1]	auto[1]	119	1		T225	3		T226	3		T227	5