Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	168076	1		T1	34		T2	14		T3	3
all_pins[1]	168076	1		T1	34		T2	14		T3	3
all_pins[2]	168076	1		T1	34		T2	14		T3	3
all_pins[3]	168076	1		T1	34		T2	14		T3	3
all_pins[4]	168076	1		T1	34		T2	14		T3	3
all_pins[5]	168076	1		T1	34		T2	14		T3	3
all_pins[6]	168076	1		T1	34		T2	14		T3	3
all_pins[7]	168076	1		T1	34		T2	14		T3	3
all_pins[8]	168076	1		T1	34		T2	14		T3	3
all_pins[9]	168076	1		T1	34		T2	14		T3	3
all_pins[10]	168076	1		T1	34		T2	14		T3	3
all_pins[11]	168076	1		T1	34		T2	14		T3	3
all_pins[12]	168076	1		T1	34		T2	14		T3	3
all_pins[13]	168076	1		T1	34		T2	14		T3	3
all_pins[14]	168076	1		T1	34		T2	14		T3	3
all_pins[15]	168076	1		T1	34		T2	14		T3	3
all_pins[16]	168076	1		T1	34		T2	14		T3	3
all_pins[17]	168076	1		T1	34		T2	14		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3023188	1		T1	612		T2	240		T3	54
values[0x1]	2180	1		T2	12		T34	1		T47	1
transitions[0x0=>0x1]	1916	1		T2	12		T34	1		T47	1
transitions[0x1=>0x0]	1930	1		T2	12		T34	1		T47	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	167975	1		T1	34		T2	14		T3	3
all_pins[0]	values[0x1]	101	1		T20	1		T305	1		T306	1
all_pins[0]	transitions[0x0=>0x1]	85	1		T20	1		T305	1		T306	1
all_pins[0]	transitions[0x1=>0x0]	996	1		T2	12		T34	1		T47	1
all_pins[1]	values[0x0]	167064	1		T1	34		T2	2		T3	3
all_pins[1]	values[0x1]	1012	1		T2	12		T34	1		T47	1
all_pins[1]	transitions[0x0=>0x1]	998	1		T2	12		T34	1		T47	1
all_pins[1]	transitions[0x1=>0x0]	102	1		T41	1		T44	1		T45	1
all_pins[2]	values[0x0]	167960	1		T1	34		T2	14		T3	3
all_pins[2]	values[0x1]	116	1		T41	1		T44	1		T45	1
all_pins[2]	transitions[0x0=>0x1]	98	1		T41	1		T44	1		T45	1
all_pins[2]	transitions[0x1=>0x0]	46	1		T69	1		T226	1		T228	1
all_pins[3]	values[0x0]	168012	1		T1	34		T2	14		T3	3
all_pins[3]	values[0x1]	64	1		T69	1		T226	1		T228	1
all_pins[3]	transitions[0x0=>0x1]	48	1		T69	1		T226	1		T228	1
all_pins[3]	transitions[0x1=>0x0]	47	1		T70	1		T225	1		T227	4
all_pins[4]	values[0x0]	168013	1		T1	34		T2	14		T3	3
all_pins[4]	values[0x1]	63	1		T70	1		T225	1		T227	4
all_pins[4]	transitions[0x0=>0x1]	51	1		T70	1		T225	1		T227	3
all_pins[4]	transitions[0x1=>0x0]	43	1		T298	3		T302	1		T304	1
all_pins[5]	values[0x0]	168021	1		T1	34		T2	14		T3	3
all_pins[5]	values[0x1]	55	1		T227	1		T298	3		T302	2
all_pins[5]	transitions[0x0=>0x1]	38	1		T227	1		T302	2		T304	2
all_pins[5]	transitions[0x1=>0x0]	42	1		T226	3		T228	3		T299	1
all_pins[6]	values[0x0]	168017	1		T1	34		T2	14		T3	3
all_pins[6]	values[0x1]	59	1		T226	3		T228	3		T299	1
all_pins[6]	transitions[0x0=>0x1]	48	1		T226	2		T228	2		T299	1
all_pins[6]	transitions[0x1=>0x0]	47	1		T51	1		T52	1		T225	2
all_pins[7]	values[0x0]	168018	1		T1	34		T2	14		T3	3
all_pins[7]	values[0x1]	58	1		T51	1		T52	1		T225	2
all_pins[7]	transitions[0x0=>0x1]	43	1		T51	1		T52	1		T225	1
all_pins[7]	transitions[0x1=>0x0]	38	1		T54	1		T226	1		T227	2
all_pins[8]	values[0x0]	168023	1		T1	34		T2	14		T3	3
all_pins[8]	values[0x1]	53	1		T54	1		T225	1		T226	2
all_pins[8]	transitions[0x0=>0x1]	42	1		T54	1		T225	1		T226	1
all_pins[8]	transitions[0x1=>0x0]	64	1		T66	2		T67	2		T68	2
all_pins[9]	values[0x0]	168001	1		T1	34		T2	14		T3	3
all_pins[9]	values[0x1]	75	1		T66	2		T67	2		T68	2
all_pins[9]	transitions[0x0=>0x1]	51	1		T66	2		T67	2		T68	2
all_pins[9]	transitions[0x1=>0x0]	50	1		T228	2		T229	1		T299	1
all_pins[10]	values[0x0]	168002	1		T1	34		T2	14		T3	3
all_pins[10]	values[0x1]	74	1		T226	1		T228	3		T229	1
all_pins[10]	transitions[0x0=>0x1]	58	1		T228	1		T229	1		T299	1
all_pins[10]	transitions[0x1=>0x0]	85	1		T48	1		T74	1		T75	1
all_pins[11]	values[0x0]	167975	1		T1	34		T2	14		T3	3
all_pins[11]	values[0x1]	101	1		T48	1		T74	1		T75	1
all_pins[11]	transitions[0x0=>0x1]	87	1		T48	1		T74	1		T75	1
all_pins[11]	transitions[0x1=>0x0]	49	1		T77	1		T78	1		T79	1
all_pins[12]	values[0x0]	168013	1		T1	34		T2	14		T3	3
all_pins[12]	values[0x1]	63	1		T77	1		T78	1		T79	1
all_pins[12]	transitions[0x0=>0x1]	49	1		T77	1		T78	1		T79	1
all_pins[12]	transitions[0x1=>0x0]	30	1		T226	1		T227	1		T228	2
all_pins[13]	values[0x0]	168032	1		T1	34		T2	14		T3	3
all_pins[13]	values[0x1]	44	1		T225	1		T226	1		T227	4
all_pins[13]	transitions[0x0=>0x1]	37	1		T225	1		T226	1		T227	4
all_pins[13]	transitions[0x1=>0x0]	45	1		T225	1		T228	3		T298	1
all_pins[14]	values[0x0]	168024	1		T1	34		T2	14		T3	3
all_pins[14]	values[0x1]	52	1		T225	1		T228	4		T298	1
all_pins[14]	transitions[0x0=>0x1]	35	1		T225	1		T228	1		T298	1
all_pins[14]	transitions[0x1=>0x0]	56	1		T227	3		T228	1		T229	3
all_pins[15]	values[0x0]	168003	1		T1	34		T2	14		T3	3
all_pins[15]	values[0x1]	73	1		T227	3		T228	4		T229	3
all_pins[15]	transitions[0x0=>0x1]	60	1		T227	3		T228	4		T229	3
all_pins[15]	transitions[0x1=>0x0]	51	1		T71	4		T72	4		T73	4
all_pins[16]	values[0x0]	168012	1		T1	34		T2	14		T3	3
all_pins[16]	values[0x1]	64	1		T71	4		T72	4		T73	4
all_pins[16]	transitions[0x0=>0x1]	54	1		T71	4		T72	4		T73	4
all_pins[16]	transitions[0x1=>0x0]	43	1		T57	1		T58	1		T59	1
all_pins[17]	values[0x0]	168023	1		T1	34		T2	14		T3	3
all_pins[17]	values[0x1]	53	1		T57	1		T58	1		T59	1
all_pins[17]	transitions[0x0=>0x1]	34	1		T57	1		T58	1		T59	1
all_pins[17]	transitions[0x1=>0x0]	96	1		T20	1		T305	1		T306	1