Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1		T225	4		T226	4		T227	7
all_values[1]	266	1		T225	4		T226	4		T227	7
all_values[2]	266	1		T225	4		T226	4		T227	7
all_values[3]	266	1		T225	4		T226	4		T227	7
all_values[4]	266	1		T225	4		T226	4		T227	7
all_values[5]	266	1		T225	4		T226	4		T227	7
all_values[6]	266	1		T225	4		T226	4		T227	7
all_values[7]	266	1		T225	4		T226	4		T227	7
all_values[8]	266	1		T225	4		T226	4		T227	7
all_values[9]	266	1		T225	4		T226	4		T227	7
all_values[10]	266	1		T225	4		T226	4		T227	7
all_values[11]	266	1		T225	4		T226	4		T227	7
all_values[12]	266	1		T225	4		T226	4		T227	7
all_values[13]	266	1		T225	4		T226	4		T227	7
all_values[14]	266	1		T225	4		T226	4		T227	7
all_values[15]	266	1		T225	4		T226	4		T227	7
all_values[16]	266	1		T225	4		T226	4		T227	7
all_values[17]	266	1		T225	4		T226	4		T227	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2571	1		T225	38		T226	51		T227	53
auto[1]	2217	1		T225	34		T226	21		T227	73

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	921	1		T225	26		T226	11		T227	27
auto[1]	3867	1		T225	46		T226	61		T227	99

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2854	1		T225	49		T226	41		T227	81
auto[1]	1934	1		T225	23		T226	31		T227	45

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	24	1		T302	1		T307	3		T300	2
all_values[0]	auto[0]	auto[0]	auto[1]	54	1		T226	1		T227	2		T228	3
all_values[0]	auto[0]	auto[1]	auto[0]	19	1		T302	1		T303	2		T307	1
all_values[0]	auto[0]	auto[1]	auto[1]	55	1		T225	2		T227	2		T228	2
all_values[0]	auto[1]	auto[0]	auto[1]	64	1		T225	2		T226	1		T227	2
all_values[0]	auto[1]	auto[1]	auto[1]	50	1		T226	2		T227	1		T298	4
all_values[1]	auto[0]	auto[0]	auto[0]	32	1		T226	2		T228	2		T229	4
all_values[1]	auto[0]	auto[0]	auto[1]	52	1		T225	1		T227	1		T228	4
all_values[1]	auto[0]	auto[1]	auto[0]	21	1		T227	2		T298	2		T304	3
all_values[1]	auto[0]	auto[1]	auto[1]	49	1		T225	1		T226	1		T227	2
all_values[1]	auto[1]	auto[0]	auto[1]	53	1		T225	2		T226	1		T228	1
all_values[1]	auto[1]	auto[1]	auto[1]	59	1		T227	2		T299	1		T298	2
all_values[2]	auto[0]	auto[0]	auto[0]	44	1		T225	4		T229	1		T302	2
all_values[2]	auto[0]	auto[0]	auto[1]	58	1		T226	3		T227	2		T228	1
all_values[2]	auto[0]	auto[1]	auto[0]	18	1		T228	2		T304	1		T300	1
all_values[2]	auto[0]	auto[1]	auto[1]	40	1		T227	4		T229	1		T299	1
all_values[2]	auto[1]	auto[0]	auto[1]	46	1		T226	1		T228	3		T229	3
all_values[2]	auto[1]	auto[1]	auto[1]	60	1		T227	1		T228	1		T299	2
all_values[3]	auto[0]	auto[0]	auto[0]	21	1		T225	1		T227	1		T301	1
all_values[3]	auto[0]	auto[0]	auto[1]	59	1		T225	1		T228	1		T229	2
all_values[3]	auto[0]	auto[1]	auto[0]	15	1		T227	4		T298	1		T301	1
all_values[3]	auto[0]	auto[1]	auto[1]	53	1		T226	1		T227	1		T228	3
all_values[3]	auto[1]	auto[0]	auto[1]	71	1		T225	2		T226	1		T227	1
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T226	2		T228	1		T229	2
all_values[4]	auto[0]	auto[0]	auto[0]	23	1		T225	1		T226	1		T228	1
all_values[4]	auto[0]	auto[0]	auto[1]	62	1		T225	1		T226	1		T227	1
all_values[4]	auto[0]	auto[1]	auto[0]	14	1		T299	2		T300	1		T308	1
all_values[4]	auto[0]	auto[1]	auto[1]	58	1		T226	1		T227	3		T228	2
all_values[4]	auto[1]	auto[0]	auto[1]	64	1		T225	1		T228	3		T229	4
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T225	1		T226	1		T227	3
all_values[5]	auto[0]	auto[0]	auto[0]	29	1		T225	1		T226	2		T228	1
all_values[5]	auto[0]	auto[0]	auto[1]	65	1		T225	1		T226	1		T227	1
all_values[5]	auto[0]	auto[1]	auto[0]	20	1		T225	1		T299	1		T301	2
all_values[5]	auto[0]	auto[1]	auto[1]	53	1		T227	3		T228	1		T229	3
all_values[5]	auto[1]	auto[0]	auto[1]	50	1		T225	1		T226	1		T227	1
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T227	2		T228	1		T229	2
all_values[6]	auto[0]	auto[0]	auto[0]	30	1		T225	1		T229	1		T304	1
all_values[6]	auto[0]	auto[0]	auto[1]	48	1		T227	2		T228	1		T229	2
all_values[6]	auto[0]	auto[1]	auto[0]	28	1		T225	3		T227	1		T301	2
all_values[6]	auto[0]	auto[1]	auto[1]	64	1		T226	1		T227	1		T228	2
all_values[6]	auto[1]	auto[0]	auto[1]	50	1		T226	3		T227	2		T228	2
all_values[6]	auto[1]	auto[1]	auto[1]	46	1		T227	1		T228	2		T299	1
all_values[7]	auto[0]	auto[0]	auto[0]	25	1		T302	1		T307	1		T308	1
all_values[7]	auto[0]	auto[0]	auto[1]	61	1		T226	2		T227	3		T299	2
all_values[7]	auto[0]	auto[1]	auto[0]	23	1		T227	1		T299	1		T301	4
all_values[7]	auto[0]	auto[1]	auto[1]	48	1		T225	2		T227	1		T228	2
all_values[7]	auto[1]	auto[0]	auto[1]	59	1		T225	1		T226	2		T227	1
all_values[7]	auto[1]	auto[1]	auto[1]	50	1		T225	1		T227	1		T228	3
all_values[8]	auto[0]	auto[0]	auto[0]	34	1		T225	1		T299	4		T298	2
all_values[8]	auto[0]	auto[0]	auto[1]	54	1		T227	2		T228	3		T229	1
all_values[8]	auto[0]	auto[1]	auto[0]	24	1		T298	1		T302	3		T303	1
all_values[8]	auto[0]	auto[1]	auto[1]	54	1		T225	2		T226	2		T227	2
all_values[8]	auto[1]	auto[0]	auto[1]	56	1		T226	1		T229	2		T298	2
all_values[8]	auto[1]	auto[1]	auto[1]	44	1		T225	1		T226	1		T227	3
all_values[9]	auto[0]	auto[0]	auto[0]	30	1		T225	1		T229	1		T304	3
all_values[9]	auto[0]	auto[0]	auto[1]	48	1		T225	1		T226	2		T227	1
all_values[9]	auto[0]	auto[1]	auto[0]	20	1		T227	1		T299	1		T301	2
all_values[9]	auto[0]	auto[1]	auto[1]	53	1		T227	1		T229	1		T302	1
all_values[9]	auto[1]	auto[0]	auto[1]	62	1		T226	2		T227	3		T228	2
all_values[9]	auto[1]	auto[1]	auto[1]	53	1		T225	2		T227	1		T228	2
all_values[10]	auto[0]	auto[0]	auto[0]	31	1		T225	1		T227	2		T302	1
all_values[10]	auto[0]	auto[0]	auto[1]	43	1		T226	1		T227	1		T228	1
all_values[10]	auto[0]	auto[1]	auto[0]	19	1		T227	1		T302	1		T303	2
all_values[10]	auto[0]	auto[1]	auto[1]	62	1		T225	2		T226	1		T227	2
all_values[10]	auto[1]	auto[0]	auto[1]	58	1		T225	1		T226	2		T227	1
all_values[10]	auto[1]	auto[1]	auto[1]	53	1		T228	2		T229	2		T299	1
all_values[11]	auto[0]	auto[0]	auto[0]	28	1		T225	1		T227	1		T228	2
all_values[11]	auto[0]	auto[0]	auto[1]	55	1		T226	2		T227	3		T229	2
all_values[11]	auto[0]	auto[1]	auto[0]	34	1		T225	1		T228	1		T298	3
all_values[11]	auto[0]	auto[1]	auto[1]	43	1		T225	1		T228	1		T229	2
all_values[11]	auto[1]	auto[0]	auto[1]	59	1		T226	2		T227	2		T229	1
all_values[11]	auto[1]	auto[1]	auto[1]	47	1		T225	1		T227	1		T228	3
all_values[12]	auto[0]	auto[0]	auto[0]	29	1		T225	1		T226	1		T228	3
all_values[12]	auto[0]	auto[0]	auto[1]	44	1		T226	2		T299	2		T298	1
all_values[12]	auto[0]	auto[1]	auto[0]	26	1		T227	1		T228	4		T299	1
all_values[12]	auto[0]	auto[1]	auto[1]	59	1		T225	2		T227	3		T229	3
all_values[12]	auto[1]	auto[0]	auto[1]	53	1		T226	1		T227	2		T229	2
all_values[12]	auto[1]	auto[1]	auto[1]	55	1		T225	1		T227	1		T229	2
all_values[13]	auto[0]	auto[0]	auto[0]	35	1		T225	1		T227	2		T229	2
all_values[13]	auto[0]	auto[0]	auto[1]	61	1		T226	1		T227	1		T228	1
all_values[13]	auto[0]	auto[1]	auto[0]	28	1		T298	1		T304	4		T309	4
all_values[13]	auto[0]	auto[1]	auto[1]	40	1		T225	1		T227	2		T228	2
all_values[13]	auto[1]	auto[0]	auto[1]	57	1		T225	1		T226	3		T228	3
all_values[13]	auto[1]	auto[1]	auto[1]	45	1		T225	1		T227	2		T228	1
all_values[14]	auto[0]	auto[0]	auto[0]	40	1		T227	4		T229	2		T301	1
all_values[14]	auto[0]	auto[0]	auto[1]	59	1		T225	1		T226	1		T228	1
all_values[14]	auto[0]	auto[1]	auto[0]	24	1		T227	3		T228	1		T229	1
all_values[14]	auto[0]	auto[1]	auto[1]	42	1		T225	1		T226	2		T228	1
all_values[14]	auto[1]	auto[0]	auto[1]	58	1		T225	1		T226	1		T228	2
all_values[14]	auto[1]	auto[1]	auto[1]	43	1		T225	1		T228	2		T299	1
all_values[15]	auto[0]	auto[0]	auto[0]	31	1		T225	2		T226	1		T299	2
all_values[15]	auto[0]	auto[0]	auto[1]	48	1		T225	1		T228	1		T229	2
all_values[15]	auto[0]	auto[1]	auto[0]	20	1		T228	1		T299	2		T301	1
all_values[15]	auto[0]	auto[1]	auto[1]	61	1		T226	2		T227	2		T228	1
all_values[15]	auto[1]	auto[0]	auto[1]	43	1		T227	1		T228	2		T229	1
all_values[15]	auto[1]	auto[1]	auto[1]	63	1		T225	1		T226	1		T227	4
all_values[16]	auto[0]	auto[0]	auto[0]	22	1		T225	1		T226	1		T228	1
all_values[16]	auto[0]	auto[0]	auto[1]	67	1		T226	1		T227	3		T228	1
all_values[16]	auto[0]	auto[1]	auto[0]	15	1		T225	3		T226	1		T302	1
all_values[16]	auto[0]	auto[1]	auto[1]	47	1		T227	1		T228	4		T229	1
all_values[16]	auto[1]	auto[0]	auto[1]	70	1		T227	2		T228	1		T229	2
all_values[16]	auto[1]	auto[1]	auto[1]	45	1		T226	1		T227	1		T229	2
all_values[17]	auto[0]	auto[0]	auto[0]	27	1		T225	1		T226	2		T227	2
all_values[17]	auto[0]	auto[0]	auto[1]	66	1		T225	1		T228	3		T299	1
all_values[17]	auto[0]	auto[1]	auto[0]	18	1		T227	1		T301	1		T304	5
all_values[17]	auto[0]	auto[1]	auto[1]	48	1		T225	1		T226	1		T227	1
all_values[17]	auto[1]	auto[0]	auto[1]	59	1		T226	1		T228	1		T299	2
all_values[17]	auto[1]	auto[1]	auto[1]	48	1		T225	1		T227	3		T228	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal